Class / Patent application number | Description | Number of patent applications / Date published |
257485000 | Specified materials | 17 |
20080197440 | Nonvolatile Memory - To provide a nonvolatile memory which realizes nonvolatile characteristic similar to a flash memory and a high-speed access equivalent to SRAM, has an integration degree exceeding that of DRAM, requires low voltage and low power consumption, and can be driven by a small-size battery, there are provided: (1) a non-volatile memory, including: a pair of metal electrodes; and a nano-hole-containing metal oxide film having a film thickness of 0.05 μm to 5 μm, which has a honeycomb structure and is provided between the pair of metal electrodes in a Schottky junction state, to use an interface state produced in a partition wall of the nano-hole-containing metal oxide film as a memory charge holder; and (2) a non-volatile memory, including: a substrate electrode; a nano-hole-containing metal oxide film formed by anodic oxidation of a surface of the substrate electrode; and a metal electrode formed to an upper end portion of a partition wall of the nano-hole-containing metal oxide film by Schottky junction, in which the nano-hole-containing metal oxide film has a structure in which a plurality of double Schottky barriers are formed in parallel. | 08-21-2008 |
20090289322 | MEMORY DEVICES HAVING A CARBON NANOTUBE - In a memory device having a carbon nanotube and a method of manufacturing the same, the memory device includes a lower electrode, an upper electrode having a first void exposing a sidewall of a diode therein, an insulating interlayer pattern having a second void exposing a portion of the lower electrode between the lower electrode and the upper electrode, and a carbon nanotube wiring capable of being electrically connected with the diode of the upper electrode by a voltage applied to the lower electrode. The memory device may reduce generation of a leakage current in a cross-bar memory. | 11-26-2009 |
20110156199 | LOW LEAKAGE AND/OR LOW TURN-ON VOLTAGE SCHOTTKY DIODE - A Schottky diode and a method of manufacturing the Schottky diode are disclosed. The Schottky diode has an N-well or N-epitaxial layer with a first region, a second region substantially adjacent to an electron doped buried layer that has a donor electron concentration greater than that of the first region, and a third region substantially adjacent to the anode that has a donor electron concentration that is less than that of the first region. The second region may be doped with implanted phosphorus and the third region may be doped with implanted boron. | 06-30-2011 |
20110221027 | Using Alloy Electrodes to Dope Memristors - Various embodiments of the present invention are direct to nanoscale, reconfigurable, memristor devices. In one aspect, a memristor device comprises an electrode ( | 09-15-2011 |
20140306315 | ENHANCED ELECTRON MOBILITY AT THE INTERFACE BETWEEN GD2O3(100)/N-SI(100) - A multilayered structure is provided. The multilayered structure may include a silicon substrate and a film of gadolinium oxide disposed on the silicon substrate. The top surface of the silicon substrate may have silicon orientated in the 100 direction (Si(100)) and the gadolinium oxide disposed thereon may have an orientation in the 100 direction (Gd | 10-16-2014 |
20150325667 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD - A semiconductor device comprising at least one active layer on a substrate and a a Schottky contact to the at least one active layer, the Schottky contact comprising a body of at least titanium and nitrogen that is electrically coupled with the at least one active layer. | 11-12-2015 |
20160079443 | JUNCTION BARRIER SCHOTTKY DIODE - A JBS diode includes a silicon substrate, a first P doped region, a metal layer, a second P doped region, and a first N doped region. The silicon substrate includes an upper surface. An NBL is provided in the bottom of the silicon substrate. An N well is provided between the upper surface and the NBL. The first P doped region is arranged in the N well, and extending downward from the upper surface. The metal layer covers the upper surface, and located on a side of the first P doped region. The second P doped region is arranged in the N well, extending downward from the upper surface, and located at the other side of the first P doped region. The first N doped region is arranged in the N well, extending downward from the upper surface, and located at the other side of the first P doped region. | 03-17-2016 |
257486000 | Layered (e.g., a diffusion barrier material layer or a silicide layer or a precious metal layer) | 10 |
20090085145 | SEMICONDUCTOR STRUCTURE COMPRISING AN ELECTRICALLY CONDUCTIVE FEATURE AND METHOD OF FORMING A SEMICONDUCTOR STRUCTURE - A semiconductor structure comprises a semiconductor substrate. A layer of an electrically insulating material is formed over the semiconductor substrate. An electrically conductive feature is formed in the layer of electrically insulating material. A first layer of a semiconductor material is formed between the electrically conductive feature and the layer of electrically insulating material. | 04-02-2009 |
20090096053 | Schottky Barrier Semiconductor Device and Method for Manufacturing the Same - A silicon carbide Schottky barrier semiconductor device provided with a Ta electrode as a Schottky electrode, in which the Schottky barrier height is controlled to a desired value in a range where power loss is minimized without increasing the n factor. The method for manufacturing the silicon carbide Schottky barrier semiconductor device includes the steps of depositing Ta on a crystal face of an n-type silicon carbide epitaxial film, the crystal face having an inclined angle in the range of 0° to 10° from a (000-1) C face, and carrying out a thermal treatment at a temperature range of 300 to 1200° C. to form the Schottky electrode. | 04-16-2009 |
20100289109 | SCHOTTKY DIODES CONTAINING HIGH BARRIER METAL ISLANDS IN A LOW BARRIER METAL LAYER AND METHODS OF FORMING THE SAME - Fabrication of a Schottky diodes may include providing a Schottky contact layer containing a low barrier metal layer with spaced apart high barrier metal islands therein on a first surface of a substrate. A diode contact is formed on a second surface of the substrate that is opposite to the first surface. Formation of the Schottky contact layer may include providing a liquid mixture of a high barrier metal and a low barrier metal on the first surface of the substrate. Temperature and/or relative concentrations of the high and low barrier metals in the liquid mixture may be controlled to cause regions of the high barrier metal to solidify within the liquid mixture and agglomerate to form the spaced apart high barrier metal islands while inhibiting solidification of the low barrier metal. The temperature and relative concentrations may then be controlled to cause the low barrier metal to solidify and form the low barrier metal layer containing the high barrier metal islands. | 11-18-2010 |
20110169124 | METHOD FOR DEPINNING THE FERMI LEVEL OF A SEMICONDUCTOR AT AN ELECTRICAL JUNCTION AND DEVICES INCORPORATING SUCH JUNCTIONS - An electrical device in which an interface layer is disposed between and in contact with a metal and a Si-based semiconductor, the interface layer being of a thickness effective to depin of the Fermi level of the semiconductor while still permitting current to flow between the metal and the semiconductor. The interface layer may include a layer of a passivating material (e.g., made from nitrogen, oxygen, oxynitride, arsenic, hydrogen and/or fluorine) and sometimes also includes a separation layer. In some cases, the interface layer may be a monolayer of a semiconductor passivating material. The interface layer thickness corresponds to a minimum specific contact resistance of less than or equal to 10 Ω-μm | 07-14-2011 |
20120193747 | SCHOTTKY BARRIER DIODE, A METHOD OF FORMING THE DIODE AND A DESIGN STRUCTURE FOR THE DIODE - Disclosed are embodiments of a Schottky barrier diode. This diode can be formed in a semiconductor substrate having a doped region with a first conductivity type. A trench isolation structure can laterally surround a section of the doped region at the top surface of the substrate. A semiconductor layer can be positioned on the top surface of the substrate. This semiconductor layer can have a Schottky barrier portion over the defined section of the doped region and a guardring portion over the trench isolation structure laterally surrounding the Schottky barrier portion. The Schottky barrier portion can have the first conductivity type and the guarding portion can have a second conductivity type different from the first conductivity type. A metal silicide layer can overlie the semiconductor layer. Also disclosed are embodiments of a method of forming this Schottky barrier diode and of a design structure for the Schottky barrier diode. | 08-02-2012 |
20150097261 | INTERCONNECT SYSTEM - An electrical contact and electrical interconnect network comprising graphene and a transition metal for a solid state device and an interconnect network for a circuit board or substrate are disclosed. | 04-09-2015 |
20150325709 | SEMICONDUCTOR DEVICE - A semiconductor device is provided with a semiconductor layer including Si and a Schottky electrode being in Schottky contact with at least a part of one of main surfaces of the semiconductor layer. A material of the Schottky electrode is a Al—Si alloy including at least one metal selected from the group consisting of Ti, Ta, Nb, Hf, Zr, W, Mo and V. | 11-12-2015 |
20160172491 | METHOD FOR DEPINNING THE FERMI LEVEL OF A SEMICONDUCTOR AT AN ELECTRICAL JUNCTION AND DEVICES INCORPORATING SUCH JUNCTIONS | 06-16-2016 |
20160172492 | METHOD FOR DEPINNING THE FERMI LEVEL OF A SEMICONDUCTOR AT AN ELECTRICAL JUNCTION AND DEVICES INCORPORATING SUCH JUNCTIONS | 06-16-2016 |
20160181388 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE COMPRISING A METAL NITRIDE LAYER AND SEMICONDUCTOR DEVICE | 06-23-2016 |