Class / Patent application number | Description | Number of patent applications / Date published |
257413000 | Polysilicon laminated with silicide | 32 |
20080203501 | SEMICONDUCTOR DEVICE - A semiconductor device with higher reliability and a manufacturing method thereof are provided. The semiconductor device includes a semiconductor layer overlapping with a gate electrode and having an impurity region outside a region which overlaps with the gate electrode; a first conductive layer which is provided on a side provided with the gate electrode of the semiconductor layer and partially in contact with the impurity region; an insulating layer provided over the gate electrode and the first conductive layer; and a second conductive layer which is formed in the insulating layer and in contact with the first conductive layer through an opening at least part of which overlaps with the first conductive layer. | 08-28-2008 |
20080290429 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes forming a gate insulation layer over a substrate, a first conductive layer over the gate insulation layer, and a second conductive layer over the first conductive layer, etching the second conductive layer to form a second gate electrode using a first mask pattern having a first width, forming an insulation layer over a resultant where the second gate electrode is formed, and etching the insulation layer, the first conductive layer and the gate insulation layer sequentially to form a gate using a second mask pattern having a second width greater than the first width, the gate including an etched gate insulation layer, a first gate electrode, the second gate electrode, and a gate hard mask, which are stacked in sequence, wherein both sidewalls and a top surface of the second gate electrode are covered with the gate hard mask. | 11-27-2008 |
20090050985 | Semiconductor device with increased channel length and method for fabricating the same - A semiconductor device with an increased channel length and a method for fabricating the same are provided. The semiconductor device includes: a substrate with an active region including a planar active region and a prominence active region formed on the planar active region; a gate insulation layer formed over the active region; and a gate structure including at least one gate lining layer encompassing the prominence active region on the gate insulation layer. | 02-26-2009 |
20090146225 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for manufacturing a semiconductor device includes a gate dielectric film formed over an active area of a semiconductor substrate, and a gate electrode formed over the gate dielectric film and formed of a silicidation film having a polysilicon area at the bottom of the gate electrode. Therefore, with embodiments, a work function can variously controlled and the gate pattern having different work function can be applied to the transistors by using a non-silicided polysilicon region due to the formation a partially silicided gate pattern, such that the resistance of the gate electrode and junction can be reduced, making it possible to maximize the device characteristics. | 06-11-2009 |
20090159994 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Semiconductor devices and manufacturing methods thereof are provided. A semiconductor device can include a gate dielectric, a gate electrode, sidewall spacers, and source and drain regions. The gate electrode can include an electrode seed layer and an electrode metal layer. In another embodiment, the gate electrode can be formed of a deposited metal silicon layer. | 06-25-2009 |
20090230484 | METHOD OF FABRICATING A SEMICONDUCTOR DEVICE - Embodiments relate to a method of fabricating a semiconductor device. In embodiments, a gate pattern may be formed on a semiconductor substrate, and sidewalls having a lower height than a height of the gate pattern may be formed at both sides of the gate pattern using a photoresist pattern. A silicide layer may be formed on exposed upper surface and side surfaces of the gate pattern and a portion of the semiconductor substrate at both sides of the sidewalls. Therefore, the silicide layer formed on a gate may be enlarged, and may reduce gate resistance. | 09-17-2009 |
20090236676 | STRUCTURE AND METHOD TO MAKE HIGH PERFORMANCE MOSFET WITH FULLY SILICIDED GATE - The present invention in one embodiment provides a method of producing a device including providing a semiconducting device including a gate structure including a silicon containing gate conductor atop a substrate; forming a metal layer on at least the silicon containing gate conductor; and directing chemically inert ions to impact the metal layer, wherein momentum transfer from of the chemically inert ions force metal atoms from the metal layer into the silicon containing gate conductor to provide a silicide gate conductor. | 09-24-2009 |
20090243002 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device according to one embodiment includes: a semiconductor substrate; a gate electrode formed on the semiconductor substrate via a gate insulating film; a first silicide layer formed on the gate electrode; a channel region formed in the semiconductor substrate below the gate electrode; source/drain regions formed in regions in the semiconductor substrate, the regions sandwiching the channel region; and second silicide layers formed on the source/drain regions and having an average grain size smaller than that of the first silicide layer or an average number of compositional boundaries in a crystal grain larger than that of the first silicide layer. | 10-01-2009 |
20090261429 | TRANSISTOR AND METHOD FOR MANUFACTURING THEREOF - A transistor includes a gate insulating layer over a semiconductor substrate; a first insulating layer on both sides of the gate insulating layer; first spacers over the first insulating layer and being spaced apart from each other; and a gate conductive plug between the first spacers. A method for manufacturing a transistor includes sequentially depositing a first insulating layer and a second insulating layer over a semiconductor substrate; etching the second insulating layer; implanting impurity ions; depositing and etching a layer of spacer material to form first spacers; removing a first portion of the first insulating layer between the first spacers; depositing a gate insulating layer the place of the first portion of the first insulating layer; forming a gate conductive plug on the gate insulating layer; forming second spacers on sidewalls of the gate conductive plug; and forming a silicide on an upper surface of the gate conductive plug. | 10-22-2009 |
20090294878 | CIRCUITRY AND GATE STACKS - The present invention includes semiconductor circuitry. Such circuitry encompasses a metal silicide layer over a substrate and a layer comprising silicon, nitrogen and oxygen in physical contact with the metal silicide layer. The present invention also includes a gate stack which encompasses a polysilicon layer over a substrate, a metal silicide layer over the polysilicon layer, an antireflective material layer over the metal silicide layer, a silicon nitride layer over the antireflective material layer, and a layer of photoresist over the silicon nitride layer, for photolithographically patterning the layer of photoresist to form a patterned masking layer from the layer of photoresist and transferring a pattern from the patterned masking layer to the silicon nitride layer, antireflective material layer, metal silicide layer and polysilicon layer. The patterned silicon nitride layer, antireflective material layer, metal silicide layer and polysilicon layer encompass a gate stack. | 12-03-2009 |
20090321856 | SELF-ALIGNED INSULATING ETCHSTOP LAYER ON A METAL CONTACT - A semiconductor device comprising a substrate having a transistor that includes a metal gate structure; a first oxide layer formed over the substrate; a silane layer formed on the first oxide layer; and a non-conductive metal oxide layer grown on the metal gate structure, wherein the silane layer inhibits nucleation and growth of the non-conductive metal oxide layer. | 12-31-2009 |
20100001354 | SELF ALIGNED MOS STRUCTURE WITH POLYSILICON CONTACT - A method for fabricating a semiconductor integrated circuit and resulting structure. The method includes providing a semiconductor substrate with an overlying dielectric layer and forming a polysilicon gate layer and an overlying capping layer. The gate layer is overlying the dielectric layer. The method also includes patterning the polysilicon gate layer to form a gate structure and a local interconnect structure. The gate structure and the local interconnect structure include a contact region defined therebetween. The gate structure also includes the overlying capping layer. The method includes forming sidewall spacers on the gate structure and the local interconnect structure and removing the sidewall spacer on the local interconnect structure. The method also includes forming contact polysilicon on the contact region and implanting a dopant impurity into the contact polysilicon. The method diffuses the dopant impurity from the contact polysilicon into the contact region in the substrate to form a diffused junction region. The method selectively removes the capping layer overlying the gate structure. The method then forms a silicide layer overlying the gate structure and surface of the contact polysilicon, whereupon the sidewall spacers isolate the silicide layer on the gate structure from the silicide layer on the contact polysilicon. | 01-07-2010 |
20100025782 | TECHNIQUE FOR REDUCING SILICIDE NON-UNIFORMITIES IN POLYSILICON GATE ELECTRODES BY AN INTERMEDIATE DIFFUSION BLOCKING LAYER - Threshold variability in advanced transistor elements, as well as increased leakage currents, may be reduced by incorporating a barrier material in a polysilicon gate electrode. The barrier material results in a well-controllable and well-defined metal silicide in the polysilicon gate electrode during the silicidation sequence and during the further processing by significantly reducing the diffusion of a metal species, such as nickel, into the vicinity of the gate dielectric material. | 02-04-2010 |
20100171188 | INTEGRATED CIRCUIT DEVICE WITH SINGLE CRYSTAL SILICON ON SILICIDE AND MANUFACTURING METHOD - A silicide element separates a single crystal silicon node from an underlying silicon substrate, and is capable of acting as a conductive element for interconnecting devices on the device. The single crystal silicon node can act as one terminal of a diode, and a second semiconductor node on top of it can act as the other terminal of the diode. The single crystal silicon node can act as one of the terminals of the transistor, and second and third semiconductor nodes are formed in series on top of it, providing a vertical transistor structure, which can be configured as a field effect transistor or bipolar junction transistor. The silicide element can be formed by a process that consumes a base of a protruding single crystal element by silicide formation processes, while shielding upper portions of the protruding element from the silicide formation process. | 07-08-2010 |
20110068418 | SUBSTRATE SYMMETRICAL SILICIDE SOURCE/DRAIN SURROUNDING GATE TRANSISTOR - Field effect transistors described herein include first and second terminals vertically separated by a channel region. The first and second terminals comprise first and second silicide elements respectively. The first silicide element prevents the migration of carriers from the first terminal into the underlying semiconductor body or adjacent devices which can activate parasitic devices. The first silicide element is also capable of acting as a low resistance conductive line for interconnecting devices or elements. The second silicide element provides a low resistance contact between the second terminal and overlying elements. | 03-24-2011 |
20110095381 | Gate structure and method for making same - A MOS transistor having its gate successively comprising an insulating layer, a metal silicide layer, a layer of a conductive encapsulation material, and a polysilicon layer. | 04-28-2011 |
20110121411 | THREE-DIMENSIONAL MEMORY DEVICES AND METHODS OF MANUFACTURING AND OPERATING THE SAME - The invention provides a semiconductor cell comprising a gate, a dielectric layer, a channel layer, a source region, a drain region and an oxide region. The dielectric layer is adjacent to the gate. The channel layer is adjacent to the dielectric layer and is formed above a source region, a drain region, and an oxide region. | 05-26-2011 |
20110163394 | SEMICONDUCTOR CONTACT STRUCTURE AND METHOD OF FABRICATING THE SAME - Semiconductor fabricating technology is provided, and particularly, a method of fabricating a semiconductor device improving a contact characteristic between a silicon layer including carbon and a metal layer during a process of fabricating a semiconductor device is provided. A semiconductor device including the silicon layer including carbon and the metal layer formed on the silicon layer is provided. A metal silicide layer is interposed between the silicon layer including carbon and the metal layer. | 07-07-2011 |
20110241133 | Semiconductor device and manufacturing method thereof - A semiconductor device has a gate electrode including polysilicon, and a hydrogen occluding layer covering at least a top face of the gate electrode and having a function of occluding hydrogen. | 10-06-2011 |
20110316096 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor device can be manufactured by a method that includes forming a structure that includes a plurality of layers of semiconductor material. One or more etching processes are performed on the multi-layered semiconductor structure, and then an Ar/O | 12-29-2011 |
20120098073 | Semiconductor Device - A semiconductor device is provided. The semiconductor device includes: a substrate; device isolation regions formed in the substrate; an impurity region formed in a region of the substrate between every two adjacent ones of the device isolation regions; a gate electrode formed on the substrate; first and second interlayer insulating films sequentially formed on the substrate; a metal interlayer insulating film formed on the second interlayer insulating film and comprising metal wiring layers; a first contact plug electrically connecting each of the metal wiring layers and the impurity region; and a second contact plug electrically connecting each of the metal wiring layers and the gate electrode, wherein the first contact plug is formed in the first and second interlayer insulating films, and the second contact plug is formed in the second interlayer insulating film. | 04-26-2012 |
20120104516 | METAL SILICIDE FORMATION - Techniques for forming metal silicide contact pads on semiconductor devices are disclosed, and in one exemplary embodiment, a method may comprise depositing a metal layer on and between a plurality of raised silicon-based features formed on a semiconductor substrate, the metal layer comprising metal capable of reacting with external silicon-based portions of the features to form a metal silicide. In addition, such a method may also include depositing a cap layer on the metal layer deposited on and between the plurality of raised silicon-based features, wherein a thickness of the cap layer on the metal layer between the raised features is greater than or equal to a thickness of the cap layer on the metal layer on the raised features. Furthermore, such a method may also include annealing the structure to cause portions of the metal layer to react with portions of the external silicon-based portions of the features to form metal silicide pads on and between the raised features. | 05-03-2012 |
20120119310 | STRUCTURE AND METHOD TO FABRICATE A BODY CONTACT - A structure and method to fabricate a body contact on a transistor is disclosed. The method comprises forming a semiconductor structure with a transistor on a handle wafer. The structure is then inverted, and the handle wafer is removed. A silicided body contact is then formed on the transistor in the inverted position. The body contact may be connected to neighboring vias to connect the body contact to other structures or levels to form an integrated circuit. | 05-17-2012 |
20120299125 | SELF-ALIGNED CONTACTS - A method of forming a gate structure with a self-aligned contact is provided and includes sequentially depositing a sacrificial layer and a secondary layer onto poly-Si disposed at a location of the gate structure, encapsulating the sacrificial layer, the secondary layer and the poly-Si, removing the sacrificial layer through openings formed in the secondary layer and forming silicide within at least the space formally occupied by the sacrificial layer. | 11-29-2012 |
20130026582 | PARTIAL POLY AMORPHIZATION FOR CHANNELING PREVENTION - Semiconductor devices are formed without zipper defects or channeling and through-implantation and with different silicide thicknesses in the gates and source/drain regions, Embodiments include forming a gate on a substrate, forming a nitride cap on the gate, forming a source/drain region in the substrate on each side of the gate, forming a wet cap fill layer on the source/drain region on each side of the gate, removing the nitride cap from the gate, and forming an amorphized layer in a top portion of the gate. Embodiments include forming the amorphized layer by implanting low energy ions. | 01-31-2013 |
20130134527 | STRUCTURE AND METHOD TO FABRICATE A BODY CONTACT - A structure and method to fabricate a body contact on a transistor is disclosed. The method comprises forming a semiconductor structure with a transistor on a handle wafer. The structure is then inverted, and the handle wafer is removed. A silicided body contact is then formed on the transistor in the inverted position. The body contact may be connected to neighboring vias to connect the body contact to other structures or levels to form an integrated circuit. | 05-30-2013 |
20130328138 | METHOD FOR PRODUCING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method for producing a semiconductor device includes a first step including forming a planar silicon layer and forming first and second pillar-shaped silicon layers; a second step including forming a gate insulating film around each of the first and second pillar-shaped silicon layers, forming a metal film and a polysilicon film around the gate insulating film, the thickness of the polysilicon film being smaller than half of a distance between the first and second pillar-shaped silicon layers, forming a third resist, and forming a gate line; and a third step including depositing a fourth resist so that a portion of the polysilicon film on an upper side wall of each of the first and second pillar-shaped silicon layers is exposed, removing the exposed portion of the polysilicon film, removing the fourth resist, and removing the metal film to form first and second gate electrodes. | 12-12-2013 |
20140048892 | SELF ALIGNED MOS STRUCTURE WITH POLYSILICON CONTACT - An integrated circuit structure has a substrate comprising a well region and a surface region, an isolation region within the well region, a gate insulating layer overlying the surface region, first and second source/drain regions within the well region of the substrate. The structure also has a channel region formed between the first and second source/drain regions and within a vicinity of the gate insulating layer, and a gate layer overlying the gate insulating layer and coupled to the channel region. The structure has sidewall spacers on edges of the gate layer to isolate the gate layer, a local interconnect layer overlying the surface region of the substrate and having an edge region extending within a vicinity of the first source/drain region. A contact layer on the first source/drain region in contact with the edge region and has a portion abutting a portion of the sidewall spacers. | 02-20-2014 |
20140091403 | METHOD FOR PRODUCING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method for producing a semiconductor device includes a step of forming a first insulating film around a fin-shaped silicon layer and forming a pillar-shaped silicon layer in an upper portion of the fin-shaped silicon layer; a step of implanting an impurity into upper portions of the pillar-shaped silicon layer and fin-shaped silicon layer and a lower portion of the pillar-shaped silicon layer to form diffusion layers; and a step of forming a polysilicon gate electrode, a polysilicon gate line, and a polysilicon gate pad. The polysilicon gate electrode and the polysilicon gate pad have a larger width than the polysilicon gate line. After these steps follow a step of depositing an interlayer insulating film, exposing and etching the polysilicon gate electrode and the polysilicon gate line, and depositing a metal layer to form a metal gate electrode and a metal gate line, and a step of forming a contact. | 04-03-2014 |
20140159172 | Transistors, Semiconductor Devices, and electronic devices including transistor gates with conductive elements including cobalt silicide - A method for fabricating a transistor gate with a conductive element that includes cobalt silicide includes use of a sacrificial material as a place-holder between sidewall spacers of the transistor gate until after high temperature processes, such as the fabrication of raised source and drain regions, have been completed. In addition, semiconductor devices (e.g., DRAM devices and NAND flash memory devices) with transistor gates that include cobalt silicide in their conductive elements are also disclosed, as are transistors with raised source and drain regions and cobalt silicide in the transistor gates thereof. Intermediate semiconductor device structures that include transistor gates with sacrificial material or a gap between upper portions of sidewall spacers are also disclosed. | 06-12-2014 |
20140374845 | SEMICONDUCTOR DEVICE - A semiconductor device includes a fin-shaped silicon layer on a semiconductor substrate and extending in a first direction and a first insulating film around the fin-shaped semiconductor layer. A pillar-shaped silicon layer resides on the fin-shaped silicon layer. A width of the pillar-shaped semiconductor layer, perpendicular to the first direction is equal to a width of the fin-shaped semiconductor layer perpendicular to the first direction. A gate insulating film is around the pillar-shaped semiconductor layer and a metal gate electrode is around the gate insulating film. A metal gate line extends in a second direction perpendicular to the first direction of the fin-shaped semiconductor layer and is connected to the metal gate electrode. A metal gate pad is connected to the metal gate line, where the width of the metal gate electrode and the width of the metal gate pad are larger than the width of the metal gate line. | 12-25-2014 |
20150014792 | III-V COMPOUND SEMICONDUCTOR DEVICE HAVING METAL CONTACTS AND METHOD OF MAKING THE SAME - A semiconductor device comprises a semiconductor substrate; a channel layer of at least a first III-V semiconductor compound above the semiconductor substrate; a gate stack structure above a first portion of the channel layer; a source region and a drain region comprising at least a second III-V semiconductor compound above a second portion of the channel layer; and a first metal contact structure above the S/D regions comprising a first metallic contact layer contacting the S/D regions. The first metallic contact layer comprises at least one metal-III-V semiconductor compound. | 01-15-2015 |