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Gate insulator includes material (including air or vacuum) other than SiO 2

Subclass of:

257 - Active solid-state devices (e.g., transistors, solid-state diodes)

257213000 - FIELD EFFECT DEVICE

257288000 - Having insulated electrode (e.g., MOSFET, MOS diode)

Patent class list (only not empty are listed)

Deeper subclasses:

Class / Patent application numberDescriptionNumber of patent applications / Date published
257411000 Composite or layered gate insulator (e.g., mixture such as silicon oxynitride) 184
Entries
DocumentTitleDate
20090026557SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The method of manufacturing a semiconductor device comprises; forming an HfSiO film 01-29-2009
20080258242Low contact resistance ohmic contact for a high electron mobility transistor and fabrication method thereof - A semiconductor device (10-23-2008
20130032899SEMICONDUCTOR DEVICE - An N-type MIS transistor includes an active region surrounded by an element isolation region in a semiconductor substrate, a gate insulating film formed on the active region and the element isolation region and having a high-k insulating film, and a gate electrode formed on the gate insulating film. An N-type impurity region is formed at least in a portion located below the gate insulating film out of a portion of the active region which contacts the element isolation region.02-07-2013
20130032898METAL-GATE/HIGH-k/GE MOSFET WITH LASER ANNEALING AND FABRICATION METHOD THEREOF - The present invention discloses a metal-gate/high-κ/Ge MOSFET with laser annealing and a fabrication method thereof. The fabrication method comprises the following steps: forming a substrate; implanting a source area and a drain area on the substrate; activating the source area and the drain area by first laser light; depositing gate dielectric material on the substrate; annealing high-κ dielectric material by second laser light; and forming a metal gate on the high-κ dielectric material.02-07-2013
20130032897MOSFET GATE ELECTRODE EMPLOYING ARSENIC-DOPED SILICON-GERMANIUM ALLOY LAYER - A stack of a gate dielectric layer, a metallic material layer, an amorphous silicon-germanium alloy layer, and an amorphous silicon layer is deposited on a semiconductor substrate. In one embodiment, the amorphous silicon-germanium alloy layer is deposited as an in-situ amorphous arsenic-doped silicon-germanium alloy layer. In another embodiment, the amorphous silicon-germanium alloy layer is deposited as intrinsic semiconductor material layer, and arsenic is subsequently implanted into the amorphous silicon-germanium alloy layer. The stack is patterned and annealed to form a gate electrode.02-07-2013
20130075832PROCESS FOR PRODUCING A CONDUCTING ELECTRODE - A process for producing a conducting electrode on a substrate, including: depositing a layer made of a dielectric; depositing a protective layer made of the nitride of a metal on the dielectric layer; depositing a functionalization layer made of a material including a chemical species, such that the free enthalpy of formation of the nitride of the species is less, in absolute value, than the free enthalpy of formation of the nitride of the metal of the protective layer over the temperature range between 0° C. and 1200° C.; and annealing the assembly including the protective layer and the funtionalization layer so that the species diffuse from the functionalization layer into the protective layer and the nitrogen atoms migrate from the protective layer into the functionalization layer.03-28-2013
20130082337OXYGEN SCAVENGING SPACER FOR A GATE ELECTRODE - At least one layer including a scavenging material and a dielectric material is deposited over a gate stack, and is subsequently anisotropically etched to form a oxygen-scavenging-material-including gate spacer. The oxygen-scavenging-material-including gate spacer can be a scavenging-nanoparticle-including gate spacer or a scavenging-island-including gate spacer. The scavenging material is distributed within the oxygen-scavenging-material-including gate spacer in a manner that prevents an electrical short between a gate electrode and a semiconductor material underlying a gate dielectric. The scavenging material actively scavenges oxygen that diffuses toward the gate dielectric from above, or from the outside of, a dielectric gate spacer that can be formed around the oxygen-scavenging-material-including gate spacer.04-04-2013
20130075831METAL GATE STACK HAVING TIALN BLOCKING/WETTING LAYER - A metal gate stack having a TiAlN blocking/wetting layer, and methods of manufacturing the same, are disclosed. In an example, an integrated circuit device includes a semiconductor substrate and a gate stack disposed over the semiconductor substrate. The gate stack includes a gate dielectric layer disposed over the semiconductor substrate; a work function layer disposed over the gate dielectric layer; a multi-function wetting/blocking layer disposed over the work function layer, wherein the multi-function wetting/blocking layer is a titanium aluminum nitride layer; and a conductive layer disposed over the multi-function wetting/blocking layer.03-28-2013
20100044805METAL GATES WITH LOW CHARGE TRAPPING AND ENHANCED DIELECTRIC RELIABILITY CHARACTERISTICS FOR HIGH-k GATE DIELECTRIC STACKS - A multilayered gate stack having improved reliability (i.e., low charge trapping and gate leakage degradation) is provided. The inventive multilayered gate stack includes, from bottom to top, a metal nitrogen-containing layer located on a surface of a high-k gate dielectric and Si-containing conductor located directly on a surface of the metal nitrogen-containing layer. The improved reliability is achieved by utilizing a metal nitrogen-containing layer having a compositional ratio of metal to nitrogen of less than 1.1. The inventive gate stack can be useful as an element of a complementary metal oxide semiconductor (CMOS). The present invention also provides a method of fabricating such a gate stack in which the process conditions of a sputtering process are varied to control the ratio of metal and nitrogen within the sputter deposited layer.02-25-2010
20100044804NOVEL HIGH-K METAL GATE STRUCTURE AND METHOD OF MAKING - The present disclosure provides a semiconductor device that includes a semiconductor substrate, a transistor formed in the substrate, the transistor including a high-k gate dielectric formed over the substrate, the high-k gate dielectric having a first length measured from one sidewall to the other sidewall of the high-k gate dielectric, and a metal gate formed over the high-k gate dielectric, the metal gate having a second length measured from one sidewall to the other sidewall of the metal gate, the second length being smaller than the first length.02-25-2010
20090179281Schottky barrier source/drain N-MOSFET using ytterbium silicide - An N-type Schottky barrier Source/Drain Transistor (N-SSDT) that uses ytterbium silicide (YbSi07-16-2009
20090159991CMOS DEVICES WITH DIFFERENT METALS IN GATE ELECTRODES USING SPIN ON LOW-K MATERIAL AS HARD MASK - A semiconductor structure and a method of forming the same. The semiconductor structure includes a semiconductor substrate, a gate dielectric layer on top of the semiconductor substrate. The structure also includes a first metal containing region on top of the gate dielectric layer. The structure also includes a second metal containing region on top of the gate dielectric layer wherein the first and second metal containing regions are in direct physical contact with each other. The structure further includes a gate electrode layer on top of both the first and second metal containing regions and the gate electrode layer is in direct physical contact with both the first and second metal containing regions. The structure further includes a patterned photoresist layer on top of the gate electrode layer.06-25-2009
20120261771SEMICONDUCTOR STRUCTURES WITH DUAL TRENCH REGIONS AND METHODS OF MANUFACTURING THE SEMICONDUCTOR STRUCTURES - Semiconductor structures with dual trench regions and methods of manufacturing the semiconductor structures are provided herein. The method includes forming a gate structure on an active region and high-k dielectric material formed in one or more trenches adjacent to the active region. The method further includes forming a sacrificial material over the active region and portions of the high-k dielectric material adjacent sidewalls of the active region. The method further includes removing unprotected portions of the high-k dielectric material, leaving behind a liner of high-k dielectric material on the sidewalls of the active region. The method further includes removing the sacrificial material and forming a raised source and drain region adjacent to sidewalls of the gate structure.10-18-2012
20120181631METHOD AND STRUCTURE FOR PMOS DEVICES WITH HIGH K METAL GATE INTEGRATION AND SiGe CHANNEL ENGINEERING - Various techniques for changing the workfunction of the substrate by using a SiGe channel which, in turn, changes the bandgap favorably for a p-type metal oxide semiconductor field effect transistors (pMOSFETs) are disclosed. In the various techniques, a SiGe film that includes a low doped SiGe region above a more highly doped SiGe region to allow the appropriate threshold voltage (Vt) for pMOSFET devices while preventing pitting, roughness and thinning of the SiGe film during subsequent cleans and processing is provided.07-19-2012
20120181630REPLACEMENT GATE WITH REDUCED GATE LEAKAGE CURRENT - Replacement gate work function material stacks are provided, which provides a work function about the energy level of the conduction band of silicon. After removal of a disposable gate stack, a gate dielectric layer is formed in a gate cavity. A metallic compound layer including a metal and a non-metal element is deposited directly on the gate dielectric layer. At least one barrier layer and a conductive material layer is deposited and planarized to fill the gate cavity. The metallic compound layer includes a material having a work function about 4.4 eV or less, and can include a material selected from tantalum carbide and a hafnium-silicon alloy. Thus, the metallic compound layer can provide a work function that enhances the performance of an n-type field effect transistor employing a silicon channel.07-19-2012
20090302401PFET ENHANCEMENT DURING SMT - An integrated circuit having a substrate on which first and second active regions are defined. The first active region comprises a first transistor and the second active region comprises a second transistor having a first type stress. A barrier layer is provided over the substrate to reduce outdiffusion of dopants in the first active region.12-10-2009
20120217591SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME, AND POWER SUPPLY APPARATUS - A semiconductor device includes an electrode material diffusion suppression layer provided either between a gate electrode and a gate insulation film, between Al-containing ohmic electrodes and an Au interconnection, and below the gate electrode and above the Al-containing ohmic electrodes, the electrode material diffusion suppression layer having a structure wherein a first the TaN layer, a Ta layer, and a second the TaN layer are stacked in sequence.08-30-2012
20130069174CONTACT FOR HIGH-K METAL GATE DEVICE - A method of making an integrated circuit includes providing a substrate with a high-k dielectric and providing a polysilicon gate structure over the high-k dielectric. A doping process is performed on the substrate adjacent to the polysilicon gate structure, after which the polysilicon gate structure is removed and replaced with a metal gate structure. An interlayer dielectric (ILD) is deposited over the metal gate structure and the doped substrate, and a dry etch process forms a trench in the ILD to a top surface of the metal gate structure. After the dry etch process, a wet etch process forms an undercut near the top surface of the metal gate structure. The trench and undercut are then filled with a conductive material.03-21-2013
20130056837SELF-ALIGNED INSULATED FILM FOR HIGH-K METAL GATE DEVICE - A method of making an integrated circuit includes providing a semiconductor substrate and forming a gate dielectric over the substrate, such as a high-k dielectric. A metal gate structure is formed over the semiconductor substrate and the gate dielectric and a thin dielectric film is formed over that. The thin dielectric film includes oxynitride combined with metal from the metal gate. The method further includes providing an interlayer dielectric (ILD) on either side of the metal gate structure.03-07-2013
20130056836Techniques Providing Metal Gate Devices with Multiple Barrier Layers - A semiconductor device with a metal gate is disclosed. An exemplary semiconductor device with a metal gate includes a semiconductor substrate, source and drain features on the semiconductor substrate, a gate stack over the semiconductor substrate and disposed between the source and drain features. The gate stack includes a HK dielectric layer formed over the semiconductor substrate, a plurality of barrier layers of a metal compound formed on top of the HK dielectric layer, wherein each of the barrier layers has a different chemical composition; and a stack of metals gate layers deposited over the plurality of barrier layers.03-07-2013
20090079016METHOD FOR FORMING A DIELECTRIC STACK - The present invention provides a method for fabricating a dielectric stack in an integrated circuit comprising the steps of (i) forming a high-k dielectric layer on a semiconductor substrate, (ii) subjecting the semiconductor substrate with the high-k dielectric layer to a nitrogen comprising vapor phase reactant and silicon comprising vapor phase reactant in a plasma-enhanced chemical vapor deposition process (PECVD) or a plasma-enhanced atomic layer chemical vapor deposition (PE ALCVD) process. Furthermore, the present invention provides a dielectric stack in an integrated circuit comprising (i) a high-k dielectric layer comprising at least a high-k material, (ii) a dielectric layer comprising at least silicon and nitrogen; (iii) an intermediate layer disposed between the high-k dielectric layer and the dielectric layer, the intermediate layer comprising the high-k material, silicon, and nitrogen.03-26-2009
20090267162METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device comprises: forming a gate insulator on a substrate, the gate insulator including a high-dielectric film in whole or part; forming a first metal film on the gate insulator; forming a second metal film on the first metal film; and forming a reaction film between the gate insulator and the first metal film by letting the high-dielectric film and the first metal film react with each other through a thermal treatment.10-29-2009
20100123205METHOD TO PREVENT SURFACE DECOMPOSITION OF III-V COMPOUND SEMICONDUCTORS - A method of preventing surface decomposition of a III-V compound semiconductor is provided. The method includes forming a silicon film having a thickness from 10 Å to 400 Å on a surface of an III-V compound semiconductor. After forming the silicon film onto the surface of the III-V compound semiconductor, a high performance semiconductor device including, for example, a MOSFET, can be formed on the capped/passivated III-V compound semiconductor. During the MOSFET fabrication, a high k dielectric can be formed on the capped/passivated III-V compound semiconductor and thereafter, activated source and drain regions can be formed into the III-V compound semiconductor.05-20-2010
20090014817INSULATING FILM AND ELECTRONIC DEVICE - An electronic device including a semiconductor layer having silicon as a major component; and a dielectric film epitaxially grown directly on a major surface of the semiconductor layer, wherein the dielectric film consists of a dielectric material having a Ruddlesden-Popper type structure, the Ruddlesden-Popper type structure is expressed by a chemical formula A01-15-2009
20130161764REPLACEMENT GATE HAVING WORK FUNCTION AT VALENCE BAND EDGE - Replacement gate stacks are provided, which increase the work function of the gate electrode of a p-type field effect transistor (PFET). In one embodiment, the work function metal stack includes a titanium-oxide-nitride layer located between a lower titanium nitride layer and an upper titanium nitride layer. The stack of the lower titanium nitride layer, the titanium-oxide-nitride layer, and the upper titanium nitride layer produces the unexpected result of increasing the work function of the work function metal stack significantly. In another embodiment, the work function metal stack includes an aluminum layer deposited at a temperature not greater than 420° C. The aluminum layer deposited at a temperature not greater than 420° C. produces the unexpected result of increasing the work function of the work function metal stack significantly.06-27-2013
20110298062METAL GATE STRUCTURES AND METHODS FOR FORMING THEREOF - Metal gate structures and methods for forming thereof are provided herein. In some embodiments, a method for forming a metal gate structure on a substrate having a feature formed in a high k dielectric layer may include depositing a first layer within the feature atop the dielectric layer; depositing a second layer comprising cobalt or nickel within the feature atop the first layer; and depositing a third layer comprising a metal within the feature atop the second layer to fill the feature, wherein at least one of the first or second layers forms a wetting layer to form a nucleation layer for a subsequently deposited layer, wherein one of the first, second, or third layers forms a work function layer, and wherein the third layer forms a gate electrode.12-08-2011
20110298061STRUCTURE AND METHOD FOR REPLACEMENT GATE MOSFET WITH SELF-ALIGNED CONTACT USING SACRIFICIAL MANDREL DIELECTRIC - The present disclosure provides a method for forming a semiconductor device that includes forming a replacement gate structure overlying a channel region of a substrate. A mandrel dielectric layer is formed overlying source and drain regions of the substrate. The replacement gate structure is removed to provide an opening exposing the channel region of the substrate. A functional gate structure is formed over the channel region including a work function metal layer. A protective cap structure is formed over the functional gate structure. At least one via is etched through the mandrel dielectric layer selective to the protective cap structure to expose a portion of at least one of the source region and the drain region. A conductive fill is then formed in the vias to provide a contact to the at least one of the source region and the drain region.12-08-2011
20110298060INTERFACE STRUCTURE FOR CHANNEL MOBILITY IMPROVEMENT IN HIGH-K METAL GATE STACK - A gate stack structure for field effect transistor (FET) devices includes a nitrogen rich first dielectric layer formed over a semiconductor substrate surface; a nitrogen deficient, oxygen rich second dielectric layer formed on the nitrogen rich first dielectric layer, the first and second dielectric layers forming, in combination, a bi-layer interfacial layer; a high-k dielectric layer formed over the bi-layer interfacial layer; a metal gate conductor layer formed over the high-k dielectric layer; and a work function adjusting dopant species diffused within the high-k dielectric layer and within the nitrogen deficient, oxygen rich second dielectric layer, and wherein the nitrogen rich first dielectric layer serves to separate the work function adjusting dopant species from the semiconductor substrate surface.12-08-2011
20120139061Self-Aligned Contact For Replacement Gate Devices - A conductive top surface of a replacement gate stack is recessed relative to a top surface of a planarization dielectric layer by at least one etch. A dielectric capping layer is deposited over the planarization dielectric layer and the top surface of the replacement gate stack so that the top surface of a portion of the dielectric capping layer over the replacement gate stack is vertically recessed relative to another portion of the dielectric layer above the planarization dielectric layer. The vertical offset of the dielectric capping layer can be employed in conjunction with selective via etch processes to form a self-aligned contact structure.06-07-2012
20100090292Semiconductor device and method of manufacturing same - A method of manufacturing a semiconductor device, comprises: forming a high dielectric gate insulating film in an nMIS formation region and a pMIS formation region of a semiconductor substrate; forming a first metal film on the high dielectric gate insulating film, the first metal film; removing the first metal film in the nMIS formation region; forming a second metal film on the high dielectric gate insulating film of the nMIS formation region and on the first metal film of the pMIS formation region; and processing the first metal film and the second metal film. The high dielectric gate insulating film has a dielectric constant higher than a dielectric constant of silicon oxide. The first metal film does not contain silicon and germanium. The second metal film contains at least one of silicon and germanium.04-15-2010
20100213554GATE STRUCTURE AND METHOD FOR TRIMMING SPACERS - A gate structure includes a gate disposed on a substrate, a first spacer disposed on the substrate and surrounding the gate and a second spacer disposed on the first spacer and surrounding the gate, the second spacer is lower than the first spacer.08-26-2010
20110291204SEMICONDUCTOR DEVICE HAVING STI WITH NITRIDE LINER AND UV LIGHT SHIELDING FILM - A semiconductor device has: a silicon substrate; trench formed downward from the surface of the silicon substrate, the trench defining active regions on the surface of the silicon substrate; a first liner layer of a silicon nitride film covering an inner wall of the trench; a second liner layer of a silicon nitride layer formed on the first liner layer; an element isolation region of an insulator formed on the second liner layer; a p-channel MOS transistor formed in and on one of the active regions; a contact etch stopper layer of a silicon nitride layer not having a ultraviolet shielding ability, formed above the silicon substrate, and covering the p-channel MOS transistor; and a light shielding film of a silicon nitride layer having the ultraviolet shielding ability and formed above the contact etch stopper layer.12-01-2011
20090008724SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The semiconductor device according to the present invention comprises a gate insulating film 01-08-2009
20080272444METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device of the present invention is a method of manufacturing a semiconductor device that is provided with a step of successively forming a gate insulating film and a gate electrode on a semiconductor substrate and a step of forming a silicon nitride film that covers at least the gate insulating film and the side portions of the gate electrode, in which the silicon nitride film is formed by laminating a plurality of silicon nitride layers by repeating a step of forming a silicon nitride layer of a predetermined thickness by the low-pressure chemical vapor deposition method and a step of exposing the silicon nitride layer to nitrogen.11-06-2008
20110169104METHODS AND APPARATUS OF FLUORINE PASSIVATION - The present disclosure provides methods and apparatus of fluorine passivation in IC device fabrication. In one embodiment, a method of fabricating a semiconductor device includes providing a substrate and passivating a surface of the substrate with a mixture of hydrofluoric acid and alcohol to form a fluorine-passivated surface. The method further includes forming a gate dielectric layer over the fluorine-passivated surface, and then forming a metal gate electrode over the gate dielectric layer. A semiconductor device fabricated by such a method is also disclosed.07-14-2011
20120187506Metal High-K Transistor Having Silicon Sidewall For Reduced Parasitic Capacitance, and Process to Fabricate Same - A method forms a metal high dielectric constant (MHK) transistor and includes: providing a MHK stack disposed on a substrate, the MHK stack including a first layer of high dielectric constant material, a second overlying layer, and a third overlying layer, selectively removing only the second and third layers, without removing the first layer, to form an upstanding portion of a MHK gate structure; forming a first sidewall layer on sidewalls of the upstanding portion of the MHK gate structure; forming a second sidewall layer on sidewalls of the first sidewall layer; removing a portion of the first layer to form exposed surfaces; forming an offset spacer layer over the second sidewall layer and over the first layer, and forming in the substrate extensions that underlie the first and second sidewall layers and that extend under a portion but not all of the upstanding portion of the MHK gate structure.07-26-2012
20100006954TRANSISTOR DEVICE - A transistor device includes a semiconductor substrate, a source doping region and a drain doping region in the semiconductor, a channel region between the source doping region and the drain doping region, a gate stack on the channel region, wherein the gate stack includes an amorphous interfacial layer, a crystalline metal oxide gate dielectric layer and a gate conductor.01-14-2010
20090045471Semiconductor device fabricated by selective epitaxial growth method - A semiconductor device in which selectivity in epitaxial growth is improved. There is provided a semiconductor device comprising a gate electrode formed over an Si substrate, which is a semiconductor substrate, with a gate insulating film therebetween and an insulating layer formed over sides of the gate electrode and containing a halogen element. With this semiconductor device, a silicon nitride film which contains the halogen element is formed over the sides of the gate electrode when an SiGe layer is formed over the Si substrate. Therefore, the SiGe layer epitaxial-grows over the Si substrate with high selectivity. As a result, an OFF-state leakage current which flows between, for example, the gate electrode and source/drain regions is suppressed and a manufacturing process suitable for actual mass production is established.02-19-2009
20090294876METHOD FOR DEPOSITION OF AN ULTRA-THIN ELECTROPOSITIVE METAL-CONTAINING CAP LAYER - A method of forming an electropositive metal-containing capping layer atop a stack of a high k gate dielectric/interfacial layer that avoids chemically and physically altering the high k gate dielectric and the interfacial layer is provided. The method includes chemical vapor deposition of an electropositive metal-containing precursor at a temperature that is about 400° C. or less. The present invention also provides semiconductor structures such as, for example, MOSCAPs and MOSFETs, that include a chemical vapor deposited electropositive metal-containing capping layer atop a stack of a high k gate dielectric and an interfacial layer. The presence of the CVD electropositive metal-containing capping layer does not physically or chemically alter the high k gate dielectric and the interfacial layer.12-03-2009
20090166766METAL OXIDE SEMICONDUCTOR TRANSISTOR WITH Y SHAPE METAL GATE - A metal oxide semiconductor (MOS) transistor with a Y structure metal gate is provided. The MOS transistor includes a substrate, a Y structure metal gate positioned on the substrate, two doping regions disposed in the substrate on two sides of the Y structure metal structure, a spacer, an insulating layer positioned outside the spacer, a dielectric layer positioned outside the insulating layer and a bevel edge covering the spacer. The spacer has a vertical sidewall, and the vertical sidewall surrounds a recess. A part of the Y structure metal gate is disposed in the recess, and a part of the Y structure metal gate is positioned on the bevel edge.07-02-2009
20120292719HIGH-K METAL GATE DEVICE - A device includes a substrate with a device region surrounded by an isolation region, in which the device region includes edge portions along a width of the device region and a central portion. The device further includes a gate layer disposed on the substrate over the device region, in which the gate layer includes a graded thickness in which the gate layer at edge portions of the device region has a thickness T11-22-2012
20080283939DIELECTRIC-MODULATED FIELD EFFECT TRANSISTOR AND METHOD OF FABRICATING THE SAME - The present invention relates to a Field-Effect Transistor (FET) and, more particularly, to a Dielectric-Modulated Field-Effect Transistor (DMFET) and a method of fabricating the same. A DMFET according to an embodiment of the present invention comprises a substrate in which a source and a drain are formed, wherein the source and the drain are spaced apart from each other, a gate formed on a region between the source and the drain, of the substrate, wherein at least part of the gate is spaced apart from the substrate, biomolecules formed below a region spaced apart from the substrate, of the gate, and a linker for combining the gate and the biomolecules.11-20-2008
20080308881Method for Controlled Formation of a Gate Dielectric Stack - The present disclosure relates to methods for forming a gate stack in a MOSFET device and to MOSFET devices obtainable through such methods. In exemplary methods described herein, a rare-earth-containing layer is deposited on a layer of a silicon-containing dielectric material. Before these layers are annealed, a gate electrode material is deposited on the rare-earth-containing layer. Annealing is performed after the deposition of the gate electrode material, such that a rare earth silicate layer is formed.12-18-2008
20080308882APPLICATION OF GATE EDGE LINER TO MAINTAIN GATE LENGTH CD IN A REPLACEMENT GATE TRANSISTOR FLOW - A method to maintain a well-defined gate stack profile, deposit or grow a uniform gate dielectric, and maintain gate length CD control by means of an inert insulating liner deposited after dummy gate etch and before the spacer process. The liner material is selective to wet chemicals used to remove the dummy gate oxide thereby preventing undercut in the spacer region. The method is aimed at making the metal gate electrode technology a feasible technology with maximum compatibility with the existing fabrication environment for multiple generations of CMOS transistors, including those belonging to the 65 nm, 45 nm and 25 nm technology nodes, that are being used in analog, digital or mixed signal integrated circuit for various applications such as communication, entertainment, education and security products.12-18-2008
20130119484SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - The present invention provides a method of manufacturing a semiconductor device comprising: providing a semiconductor substrate, on which a high-k dielectric layer and a patterned gate are formed sequentially; nitridating portions of the high-k dielectric layer on the semiconductor substrate which are not covered by the gate; and forming spacers around the gate. Accordingly, the present invention further provides a semiconductor device. Portions of the high-k dielectric layer on the semiconductor substrate, which are not covered by the gate or the spacers positioned thereon, are nitridated, such that an oxygen diffusion barrier layer is formed on the surface of the high-k dielectric layer, thereby oxygen diffusion in the lateral direction into the high-k dielectric layer under the gate is prevented, and the operation performance of the semiconductor device is optimized.05-16-2013
20080265341Manufacture of semiconductor device having insulation film of high dielectric constant - A method contains the steps of (a) heating a silicon substrate in a reaction chamber; and (b) supplying film-forming gas containing source gas, nitridizing gas, and nitridation enhancing gas to a surface of the heated silicon substrate, to deposit on the silicon substrate an Hf10-30-2008
20090050981SEMICONDUCTOR DEVICE - A semiconductor device includes a first-type internal stress film formed of a silicon oxide film over source/drain regions of an nMISFET and a second-type internal stress film formed of a TEOS film over source/drain regions of a pMISFET. In a channel region of the nMISFET, a tensile stress is generated in the direction of movement of electrons due to the first-type internal stress film, so that the mobility of electrons is increased. In a channel region of the pMISFET, a compressive stress is generated in the direction of movement of holes due to the second-type internal stress film, so that the mobility of holes is increased.02-26-2009
20080258243FIELD EFFECT TRANSISTOR - A field effect transistor includes: a first nitride semiconductor layer having a plane perpendicular to a (0001) plane or a plane tilted with respect to the (0001) plane as a main surface; a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a wider bandgap than the first nitride semiconductor layer; a third nitride semiconductor layer formed on the second nitride semiconductor layer; and a source electrode and a drain electrode formed so as to contact at least a part of the second nitride semiconductor layer or the third nitride semiconductor layer. A recess that exposes a part of the second nitride semiconductor layer is formed between the source electrode and the drain electrode in the third nitride semiconductor layer. A gate electrode is formed in the recess and an insulating film is formed between the third nitride semiconductor layer and the gate electrode.10-23-2008
20090179282METAL GATE DEVICE WITH REDUCED OXIDATION OF A HIGH-K GATE DIELECTRIC - Embodiments of the invention provide a device with a metal gate, a high-k gate dielectric layer and reduced oxidation of a substrate beneath the high-k gate dielectric layer. An oxygen barrier, or capping, layer on the high-k gate dielectric layer and metal gate may prevent such oxidation during processes such as spacer formation and annealing of ion implanted regions.07-16-2009
20100200937METHOD AND STRUCTURE FOR PMOS DEVICES WITH HIGH K METAL GATE INTEGRATION AND SiGe CHANNEL ENGINEERING - Various techniques for changing the workfunction of the substrate by using a SiGe channel which, in turn, changes the bandgap favorably for a p-type metal oxide semiconductor field effect transistors (pMOSFETs) are disclosed. In the various techniques, a SiGe film that includes a low doped SiGe region above a more highly doped SiGe region to allow the appropriate threshold voltage (Vt) for pMOSFET devices while preventing pitting, roughness and thinning of the SiGe film during subsequent cleans and processing is provided.08-12-2010
20120068275SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes forming a high-dielectric constant insulating film including a high-dielectric constant film; forming a first conductive film including an oxide film on an upper surface thereof and containing at least one of high melting point metal or a compound thereof; forming a second conductive film containing silicon on the first conductive film with the oxide film being interposed therebetween; forming a mixing layer by performing ion implantation to the first and second conductive films to mix a constituent material of the oxide film and silicon of the second conductive film together; and forming the mixing layer into a conductive layer by performing heat treatment.03-22-2012
20090321853HIGH-k/METAL GATE MOSFET WITH REDUCED PARASITIC CAPACITANCE - The present invention provides a high-k gate dielectric/metal gate MOSFET that has a reduced parasitic capacitance. The inventive structure includes at least one metal oxide semiconductor field effect transistor (MOSFET) 12-31-2009
20120104513FIELD EFFECT TRANSISTOR HAVING AN ASYMMETRIC GATE ELECTRODE - The gate electrode of a metal oxide semiconductor field effect transistor (MOSFET) comprises a source side gate electrode and a drain side gate electrode that abut each other near the middle of the channel. In one embodiment, the source side gate electrode comprises a silicon oxide based gate dielectric and the drain side gate electrode comprises a high-k gate dielectric. The source side gate electrode provides high carrier mobility, while the drain side gate electrode provides good short channel effect and reduced gate leakage. In another embodiment, the source gate electrode and drain gate electrode comprises different high-k gate dielectric stacks and different gate conductor materials, wherein the source side gate electrode has a first work function a quarter band gap away from a band gap edge and the drain side gate electrode has a second work function near the band gap edge.05-03-2012
20090242999METHOD FOR ENCAPSULATING A HIGH-K GATE STACK BY FORMING A LINER AT TWO DIFFERENT PROCESS TEMPERATURES - Encapsulation of a gate stack comprising a high-k dielectric material may be accomplished on the basis of a silicon nitride material that is deposited in a sequence of two deposition processes, in which the first process may be performed on the basis of a moderately low process temperature, thereby passivating sensitive surfaces without unduly contaminating the same, while, in a second deposition process, a moderately high process temperature may be used to provide enhanced material characteristics and a reduced overall cycle time compared to conventional ALD or multi-layer deposition techniques.10-01-2009
20090256213STRUCTURE AND METHOD FOR MANUFACTURING DEVICE WITH A V-SHAPE CHANNEL NMOSFET - A CMOS structure includes a v-shape surface in an nMOSFET region. The v-shape surface has an orientation in a (100) plane and extends into a Si layer in the nMOSFET region. The nMOSFET gate dielectric layer is a high-k material, such as Hf02. The nMOSFET has a metal gate layer, such as Ta. Poly-Si is deposited on top of the metal gate layer.10-15-2009
20090140353Method of Film Deposition and Film Deposition System - The present invention is a method of film deposition that comprises a film-depositing step of supplying a high-melting-point organometallic material gas and a nitrogen-containing gas to a processing vessel that can be evacuated, so as to deposit a thin film of a metallic compound of a high-melting-point metal on a surface of an object to be processed placed in the processing vessel. A partial pressure of the nitrogen-containing gas during the film-depositing step is 17% or lower, in order to increase carbon density contained in the thin film.06-04-2009
20100148280SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a semiconductor substrate, a gate insulating film formed on a semiconductor substrate and containing a first element and a second element, and a gate electrode formed on the gate insulating film. The gate insulating film has a higher content of the first element in a portion thereof closer to the semiconductor substrate than in a portion thereof closer to the gate electrode, and a higher content of the second element in a portion thereof closer to the gate electrode than in a portion thereof closer to the semiconductor substrate.06-17-2010
20100181630DIRECT CONTACT BETWEEN HIGH-K/METAL GATE AND WIRING PROCESS FLOW - A low resistance contact is formed to a metal gate or a transistor including a High-K gate dielectric in a high integration density integrated circuit by applying a liner over a gate stack, applying a fill material between the gate stacks, planarizing the fill material to support high-resolution lithography, etching the fill material and the liner selectively to each other to form vias and filling the vias with a metal, metal alloy or conductive metal compound such as titanium nitride.07-22-2010
20090079015Lanthanide dielectric with controlled interfaces - Methods and devices for a dielectric are provided. One method embodiment includes forming a passivation layer on a substrate, wherein the passivation layer contains a composition of silicon, oxygen, and nitrogen. The method also includes forming a lanthanide dielectric film on the passivation layer, and forming an encapsulation layer on the lanthanide dielectric film.03-26-2009
20100193882IN SITU FORMED DRAIN AND SOURCE REGIONS INCLUDING A STRAIN-INDUCING ALLOY AND A GRADED DOPANT PROFILE - The dopant profile of a transistor may be obtained on the basis of an in situ doped strain-inducing semiconductor alloy wherein a graded dopant concentration may be established along the height direction. Consequently, the semiconductor alloy may be positioned in close proximity to the channel region, thereby enhancing the overall strain-inducing efficiency, while not unduly compromising the finally obtained dopant profile. Furthermore, additional implant species may be incorporated prior to selectively growing the semiconductor alloy, thereby avoiding implantation-induced relaxation of the internal strain.08-05-2010
20100258881DUAL METAL AND DUAL DIELECTRIC INTEGRATION FOR METAL HIGH-K FETS - The present invention, in one embodiment, provides a method of forming a semiconductor device that includes providing a substrate including a first conductivity type region and a second conductivity type region; forming a gate stack including a gate dielectric atop the first conductivity type region and the second conductivity type region of the substrate and a first metal gate conductor overlying the high-k gate dielectric; removing a portion of the first metal gate conductor that is present in the first conductivity type region to expose the gate dielectric present in the first conductivity type region; applying a nitrogen based plasma to the substrate, wherein the nitrogen based plasma nitrides the gate dielectric that is present in the first conductivity type region and nitrides the first metal gate conductor that is present in the second conductivity type region; and forming a second metal gate conductor overlying at least the gate dielectric that is present in the first conductivity type region.10-14-2010
20120228723GATE STRUCTURE AND METHOD FOR FABRICATING THE SAME - A gate structure and a method for fabricating the same are described. A substrate is provided, and a gate dielectric layer is formed on the substrate. The formation of the gate dielectric layer includes depositing a silicon nitride layer on the substrate by simultaneously introducing a nitrogen-containing gas and a silicon-containing gas. A gate is formed on the gate dielectric layer, so as to form the gate structure.09-13-2012
20110108927DAMASCENE GATE HAVING PROTECTED SHORTING REGIONS - The present invention relates generally to semiconductor devices and, more specifically, to damascene gates having protected shorting regions and related methods for their manufacture. A first aspect of the invention provides a method of forming a damascene gate with protected shorting regions, the method comprising: forming a damascene gate having: a gate dielectric atop a substrate; a gate conductor atop the gate dielectric; a conductive liner laterally adjacent the gate conductor; a spacer between the conductive liner and the substrate; and a first dielectric atop the gate conductor; removing a portion of the conductive liner; and depositing a second dielectric atop a remaining portion of the conductive liner, such that the second dielectric is laterally adjacent both the first dielectric and the gate.05-12-2011
20110101470HIGH-K METAL GATE ELECTRODE STRUCTURES FORMED BY SEPARATE REMOVAL OF PLACEHOLDER MATERIALS IN TRANSISTORS OF DIFFERENT CONDUCTIVITY TYPE - In a replacement gate approach, a superior cross-sectional shape of the gate opening may be achieved by performing a material erosion process in an intermediate state of removing the placeholder material. Consequently, the remaining portion of the placeholder material may efficiently protect the underlying sensitive materials, such as a high-k dielectric material, when performing the corner rounding process sequence.05-05-2011
20100244155MAINTAINING INTEGRITY OF A HIGH-K GATE STACK BY AN OFFSET SPACER USED TO DETERMINE AN OFFSET OF A STRAIN-INDUCING SEMICONDUCTOR ALLOY - In sophisticated transistor elements including a high-k gate metal stack, the integrity of the sensitive gate materials may be ensured by a spacer element that may be concurrently used as an offset spacer for defining a lateral offset of a strain-inducing semiconductor alloy. The cap material of the sophisticated gate stack may be removed without compromising integrity of the offset spacer by providing a sacrificial spacer element. Consequently, an efficient strain-inducing mechanism may be obtained in combination with the provision of a sophisticated gate stack with the required material integrity, while reducing overall process complexity compared to conventional strategies.09-30-2010
20110057272SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device includes forming an insulating layer over a semiconductor region; forming a multilayer resist composite including a plurality of resist layers over the insulating layer; forming an opening in the resist layers of the multilayer resist composite except in the lowermost resist layer adjacent to the insulating layer; forming a reflow opening in the lowermost resist layer; reflowing part of the lowermost resist layer exposed in the reflow opening by heating to form a slope at the surface of the lowermost resist layer; forming a first gate opening in the lowermost resist layer so as to extend from the slope; and forming a gate electrode having a shape depending on the shapes of the opening in the multilayer resist composite, the slope and the first gate opening.03-10-2011
20100084718ADVANCED METAL GATE METHOD AND DEVICE - The present disclosure provides a method of fabricating a semiconductor device that includes forming a high-k dielectric over a substrate, forming a first metal layer over the high-k dielectric, forming a second metal layer over the first metal layer, forming a first silicon layer over the second metal layer, implanting a plurality of ions into the first silicon layer and the second metal layer overlying a first region of the substrate, forming a second silicon layer over the first silicon layer, patterning a first gate structure over the first region and a second gate structure over a second region, performing an annealing process that causes the second metal layer to react with the first silicon layer to form a silicide layer in the first and second gate structures, respectively, and driving the ions toward an interface of the first metal layer and the high-k dielectric in the first gate structure.04-08-2010
20090039446Semiconductor device with a high-k gate dielectric and a metal gate electrode - A semiconductor device is described. That semiconductor device comprises a high-k gate dielectric layer that is formed on a substrate that applies strain to the high-k gate dielectric layer, and a metal gate electrode that is formed on the high-k gate dielectric layer.02-12-2009
20080283940LOW-TEMPERATURE GROWN HIGH QUALITY ULTRA-THIN CoTiO3 GATE DIELECTRICS - A gate oxide and method of fabricating a gate oxide that produces a more reliable and thinner equivalent oxide thickness than conventional SiO11-20-2008
20110108928METHOD FOR FORMING HIGH-K METAL GATE DEVICE - The present disclosure provides a method of fabricating a semiconductor device that includes providing a semiconductor substrate, forming a metal gate on the substrate, the metal gate having a first gate resistance, removing a portion of the metal gate thereby forming a trench; and forming a conductive structure within the trench such that a second gate resistance of the conductive structure and remaining portion of the metal gate is lower than the first gate resistance.05-12-2011
20100133628HIGH-K GATE ELECTRODE STRUCTURE FORMED AFTER TRANSISTOR FABRICATION BY USING A SPACER - During a replacement gate approach, the inverse tapering of the opening obtained after removal of the polysilicon material may be reduced by depositing a spacer layer and forming corresponding spacer elements on inner sidewalls of the opening. Consequently, the metal-containing gate electrode material and the high-k dielectric material may be deposited with enhanced reliability.06-03-2010
20090065875METAL-OXIDE-SEMICONDUCTOR DEVICE WITH A DOPED TITANATE BODY - A metal-oxide-semiconductor (MOS) device having a body of single-crystal strontium titanate or barium titanate (03-12-2009
20090065877SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes: a first MOSFET including: first source and drain regions formed at a distance from each other in a first semiconductor region; a first insulating film formed on the first semiconductor region between the first source region and the first drain region; a first gate electrode formed on the first insulating film; a first sidewall insulating film formed at side portions of the first gate electrode; a first single-crystal silicon layer formed on each of the first source and drain regions, and having at least an upper-face made of a {111} plane; a first NiSi layer formed at least on the first single-crystal silicon layer, and having a portion whose interface with the first single-crystal silicon is on the {111} plane of the first single-crystal silicon layer and a part of the portion of the first NiSi layer being in contact with the first sidewall insulating film; and a first TiN film being in contact with the portion of the first NiSi layer on the {111} plane of the first single-crystal silicon.03-12-2009
20110115034TRANSISTOR - A transistor including a substrate, a gate, a semiconductor layer, a stacked insulating layer and a source and a drain is provided. The gate is disposed on the substrate. The semiconductor layer is disposed on the substrate, and a first type carrier is the main carrier in the semiconductor layer. The stacked insulating layer is disposed between the semiconductor layer and the gate, and includes a first insulating layer and a second insulating layer. The first insulating layer contains a first group withdrawing the first type carrier, the second insulating layer contains a second group withdrawing a second type carrier, and the first insulating layer is disposed between the semiconductor layer and the second insulating layer. The source and the drain are disposed on the substrate and at two sides of the semiconductor layer.05-19-2011
20110018072METAL GATE TRANSISTOR AND METHOD FOR FABRICATING THE SAME - A metal gate transistor is disclosed. The metal gate transistor preferably includes: a substrate, a metal gate disposed on the substrate, and a source/drain region disposed in the substrate with respect to two sides of the metal gate. The metal gate includes a U-shaped high-k dielectric layer, a U-shaped cap layer disposed over the surface of the U-shaped high-k dielectric layer, and a U-shaped metal layer disposed over the U-shaped cap layer.01-27-2011
20090032889FIELD EFFECT TRANSISTOR HAVING AN ASYMMETRIC GATE ELECTRODE - The gate electrode of a metal oxide semiconductor field effect transistor (MOSFET) comprises a source side gate electrode and a drain side gate electrode that abut each other near the middle of the channel. In one embodiment, the source side gate electrode comprises a silicon oxide based gate dielectric and the drain side gate electrode comprises a high-k gate dielectric. The source side gate electrode provides high carrier mobility, while the drain side gate electrode provides good short channel effect and reduced gate leakage. In another embodiment, the source gate electrode and drain gate electrode comprises different high-k gate dielectric stacks and different gate conductor materials, wherein the source side gate electrode has a first work function a quarter band gap away from a band gap edge and the drain side gate electrode has a second work function near the band gap edge.02-05-2009
20110241130SEMICONDUCTOR DEVICE HAVING A BLOCKING STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a blocking structure between a metal layer and at least one underlying layer. The blocking structure has a first layer configured for preventing diffusion of metal from the metal layer into the at least one underlying layer, and a second layer configured for enhancing electrical performance of the semiconductor device.10-06-2011
20100038728FIELD EFFECT TRANSISTOR WITH SUPPRESSED CORNER LEAKAGE THROUGH CHANNEL MATERIAL BAND-EDGE MODULATION, DESIGN STRUCTURE AND METHOD - Disclosed are embodiments of field effect transistors (FETs) having suppressed sub-threshold corner leakage, as a function of channel material band-edge modulation. Specifically, the FET channel region is formed with different materials at the edges as compared to the center. Different materials with different band structures and specific locations of those materials are selected in order to effectively raise the threshold voltage (Vt) at the edges of the channel region relative to the Vt at the center of the channel region and, thereby to suppress of sub-threshold corner leakage. Also disclosed are design structures for such FETs and method embodiments for forming such FETs.02-18-2010
20100065925LOCAL CHARGE AND WORK FUNCTION ENGINEERING ON MOSFET - The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate having a source region and a drain region, defining a first dimension from the source to drain; and a gate stack disposed on the semiconductor substrate and partially interposed between the source region and the drain region. The gate stack includes a high k dielectric layer disposed on the semiconductor substrate; a first metal feature disposed on the high k dielectric layer, the first metal gate feature having a first work function and defining a second dimension parallel with the first dimension; and a second metal feature having a second work function different from the first work function and defining a third dimension parallel with the first dimension, the third dimension being less than the second dimension.03-18-2010
20100065926PHOTORESIST ETCH BACK METHOD FOR GATE LAST PROCESS - A method is provided for fabricating a semiconductor device. The method includes providing a substrate including a dummy gate structure formed thereon, removing the dummy gate structure to form a trench, forming a first metal layer over the substrate to fill a portion of the trench, forming a protection layer in a remaining portion of the trench, removing a unprotected portion of the first metal layer, removing the protection layer from the trench, and forming a second metal layer over the substrate to fill the trench.03-18-2010
20110101469STRAIN ENHANCEMENT IN TRANSISTORS COMPRISING AN EMBEDDED STRAIN-INDUCING SEMICONDUCTOR ALLOY BY CORNER ROUNDING AT THE TOP OF THE GATE ELECTRODE - In MOS transistor elements, a strain-inducing semiconductor alloy may be embedded in the active region with a reduced offset from the channel region by applying a spacer structure of reduced width. In order to reduce the probability of creating semiconductor residues at the top area of the gate electrode structure, a certain degree of corner rounding of the semiconductor material may be introduced, which may be accomplished by ion implantation prior to epitaxially growing the strain-inducing semiconductor material. This concept may be advantageously combined with the provision of sophisticated high-k metal gate electrodes that are provided in an early manufacturing stage.05-05-2011
20110068416SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method for manufacturing the same substantially prevent the degradation of the reliability and characteristics due to hot carriers by using a high-k dielectric material as a gate sidewall spacer material of a gate structure.03-24-2011
20110031562SEALING LAYER OF A FIELD EFFECT TRANSISTOR - An exemplary structure for a gate structure of a field effect transistor comprises a gate electrode; a gate insulator under the gate electrode having footing regions on opposing sides of the gate electrode; and a sealing layer on sidewalls of the gate structure, wherein a thickness of lower portion of the sealing layer overlying the footing regions is less than a thickness of upper portion of the sealing layer on sidewalls of the gate electrode, whereby the field effect transistor made has almost no recess in the substrate surface.02-10-2011
20110248359SEMICONDUCTOR DEVICE HAVING METAL GATE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a semiconductor substrate, a gate dielectric layer formed on the semiconductor substrate, and at least a first conductive-type metal gate formed on the gate dielectric layer. The first conductive-type metal gate includes a filling metal layer and a U-type metal layer formed between the filling metal layer and the gate dielectric layer. A topmost portion of the U-type metal layer is lower than the filling metal layer.10-13-2011
20110254106SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device includes a gate insulation film formed over a semiconductor substrate; a cap film formed over the gate insulation film; a silicon oxide film formed over the cap film; a metal gate electrode formed over the silicon oxide film; and source/drain diffused layers formed in the semiconductor substrate on both sides of the metal gate electrode.10-20-2011
20110073963SUPERIOR FILL CONDITIONS IN A REPLACEMENT GATE APPROACH BY CORNER ROUNDING PRIOR TO COMPLETELY REMOVING A PLACEHOLDER MATERIAL - In a replacement gate approach, a superior cross-sectional shape of the gate opening may be achieved by performing a material erosion process in an intermediate state of removing the placeholder material. Consequently, the remaining portion of the placeholder material may efficiently protect the underlying sensitive materials, such as a high-k dielectric material, when performing the corner rounding process sequence.03-31-2011
20120146159STRUCTURE AND METHOD FOR OVERLAY MARKS - The overlay mark and method for making the same are described. In one embodiment, a semiconductor overlay structure includes gate stack structures formed on the semiconductor substrate and configured as an overlay mark, and a doped semiconductor substrate disposed on both sides of the gate stack structure that includes at least as much dopant as the semiconductor substrate adjacent to the gate stack structure in a device region. The doped semiconductor substrate is formed by at least three ion implantation steps.06-14-2012
20100059834INTEGRATED ELECTRONIC CIRCUIT INCLUDING A THIN FILM PORTION BASED ON HAFNIUM OXIDE - An integrated electronic circuit has a thin layer portion based on hafnium oxide. This portion additionally contains magnesium atoms, so that the portion is in the form of a hafnium-and-magnesium mixed oxide. Such a portion has a high dielectric constant and a very low leakage current. It is particularly suitable for forming a part of a gate insulation layer of a MOS transistor or a part of a MIM capacitor dielectric.03-11-2010
20100059833METAL GATE TRANSISTOR AND METHOD FOR FABRICATING THE SAME - A method for fabricating metal gate transistor is disclosed. First, a substrate having a first transistor region and a second transistor region is provided. Next, a stacked film is formed on the substrate, in which the stacked film includes at least one high-k dielectric layer and a first metal layer. The stacked film is patterned to form a plurality of gates in the first transistor region and the second transistor region, a dielectric layer is formed on the gates, and a portion of the dielectric layer is planarized until reaching the top of each gates. The first metal layer is removed from the gate of the second transistor region, and a second metal layer is formed over the surface of the dielectric layer and each gate for forming a plurality of metal gates in the first transistor region and the second transistor region.03-11-2010
20110260263SEMICONDUCTOR DEVICE WITH ISOLATION TRENCH LINER - A method of manufacturing a semiconductor device is provided herein, where the width effect is reduced in the resulting semiconductor device. The method involves providing a substrate having semiconductor material, forming an isolation trench in the semiconductor material, and lining the isolation trench with a liner material that substantially inhibits formation of high-k material thereon. The lined trench is then filled with an insulating material. Thereafter, a layer of high-k gate material is formed over at least a portion of the insulating material and over at least a portion of the semiconductor material. The liner material divides the layer of high-k gate material, which prevents the migration of oxygen over the active region of the semiconductor material.10-27-2011
20110215425TUNNELING FIELD-EFFECT TRANSISTOR WITH DIRECT TUNNELING FOR ENHANCED TUNNELING CURRENT - Horizontal and vertical tunneling field-effect transistors (TFETs) having an abrupt junction between source and drain regions increases probability of direct tunneling of carriers (e.g., electrons and holes). The increased probability allows a higher achievable on current in TFETs having the abrupt junction. The abrupt junction may be formed by placement of a dielectric layer or a dielectric layer and a semiconductor layer in a current path between the source and drain regions. The dielectric layer may be a low permittivity oxide such as silicon oxide, lanthanum oxide, zirconium oxide, or aluminum oxide.09-08-2011
20090152650HIGH-K DIELECTRIC AND METAL GATE STACK WITH MINIMAL OVERLAP WITH ISOLATION REGION AND RELATED METHODS - A high-k dielectric and metal gate stack with minimal overlap with an adjacent oxide isolation region and related methods are disclosed. One embodiment of the gate stack includes a high dielectric constant (high-k) dielectric layer, a tuning layer and a metal layer positioned over an active region defined by an oxide isolation region in a substrate, wherein an outer edge of the high-k dielectric layer, the tuning layer and the metal layer overlaps the oxide isolation region by less than approximately 200 nanometers. The gate stack and related methods eliminate the regrowth effect in short channel devices by restricting the amount of overlap area between the gate stack and adjacent oxide isolation regions.06-18-2009
20090174012Field Effect Transistor - Provided is a field effect transistor, provided with a gate electrode 07-09-2009
20100301428TANTALUM SILICON OXYNITRIDE HIGH-K DIELECTRICS AND METAL GATES - Electronic apparatus and methods of forming the electronic apparatus include a tantalum silicon oxynitride film on a substrate for use in a variety of electronic systems. The tantalum silicon oxynitride film may be structured as one or more monolayers. The tantalum silicon oxynitride film may be formed using a monolayer or partial monolayer sequencing process. Metal electrodes may be disposed on a dielectric containing a tantalum silicon oxynitride film.12-02-2010
20120032279III-V METAL-OXIDE-SEMICONDUCTOR DEVICE - A barrier layer, hafnium oxide layer, between a III-V semiconductor layer and an lanthanum oxide layer is used to prevent interaction between the III-V semiconductor layer and the lanthanum oxide layer. Meanwhile, the high dielectric constant of the lanthanum oxide can be used to increase the capacitance of the semiconductor device.02-09-2012
20120306027TRANSISTORS WITH EMBEDDED STRAIN-INDUCING MATERIAL FORMED IN CAVITIES PROVIDED BY AN OXIDIZING ETCH PROCESS - When forming sophisticated semiconductor devices including transistors with sophisticated high-k metal gate electrode structures and a strain-inducing semiconductor alloy, transistor uniformity and performance may be enhanced by providing superior growth conditions during the selective epitaxial growth process. To this end, a semiconductor material may be preserved at the isolation regions in order to avoid the formation of pronounced shoulders. Furthermore, in some illustrative embodiments, additional mechanisms are implemented in order to avoid undue material loss, for instance upon removing a dielectric cap material and the like.12-06-2012
20110068417GATE INSULATING MATERIAL, GATE INSULATING FILM AND ORGANIC FIELD-EFFECT TRANSISTOR - To provide a gate insulating material which has high chemical resistance, is superior in coatability of a resist and an organic semiconductor coating liquid, and has small hysteresis, a gate insulating film and an FET using the same by a polysiloxane having an epoxy group-containing silane compound as a copolymerization component.03-24-2011
20090065876Metal High-K Transistor Having Silicon Sidewall for Reduced Parasitic Capacitance, and Process to Fabricate Same - A method is disclosed to reduce parasitic capacitance in a metal high dielectric constant (MHK) transistor. The method includes forming a MHK gate stack upon a substrate, the MHK gate stack having a bottom layer of high dielectric constant material, a middle layer of metal, and a top layer of one of amorphous silicon or polycrystalline silicon. The method further forms a depleted sidewall layer on sidewalls of the MHK gate stack so as to overlie the middle layer and the top layer, and not the bottom layer. The depleted sidewall layer is one of amorphous silicon or polycrystalline silicon. The method further forms an offset spacer layer over the depleted sidewall layer and over exposed surfaces of the bottom layer.03-12-2009
20110316095Semiconductor device and manufacturing method thereof - A semiconductor device includes a silicon substrate, an SiO film, and a High-K film. The SiO film is first formed on the silicon substrate and then subjected to a nitridation process to obtain an SiON film from the SiO film. The nitridation process is performed such that nitrogen concentration in the SiO film decreases from an interface with the silicon substrate below and an interface with the High-K film above, and nitrogen having predetermined concentration or more is introduced in a thickness within a range of 0.2 nm to 1 nm from the interface with the silicon substrate. The SiON film is etched up to a depth to which nitrogen of the predetermined concentration or more is introduced. The High-K film is then formed on the SiON film.12-29-2011
20120043625Field effect transistors, methods of fabricating a carbon-insulating layer using molecular beam epitaxy and methods of fabricating a field effect transistor - Field effect transistors, methods of fabricating a carbon insulating layer using molecular beam epitaxy and methods of fabricating a field effect transistor using the same are provided, the methods of fabricating the carbon insulating layer include maintaining a substrate disposed in a molecular beam epitaxy chamber at a temperature in a range of about 300° C. to about 500° C. and maintaining the chamber in vacuum of 1002-23-2012
20120043624ULTRA-THIN BODY TRANSISTOR AND METHOD FOR MANUFCTURING THE SAME - An ultra-thin body transistor and a method for manufacturing an ultra-thin body transistor are disclosed. The ultra-thin body transistor comprises: a semiconductor substrate; a gate structure on the semiconductor substrate; and a source region and a drain region in the semiconductor substrate and on either side of the gate structure; in which the gate structure comprises a gate dielectric layer, a gate embedded in the gate dielectric layer, and a spacer on both sides of the gate; the ultra-thin body transistor further comprises: a body region and a buried insulated region located sequentially under the gate structure and in a well region; two ends of the body region and the buried insulated region are connected with the source region and the drain region respectively; and the body region is isolated from other regions in the well region by the buried insulated region under the body region. The ultra-thin body transistor has a thinner body region, which decreases the short channel effect. In the method for manufacturing an ultra-thin body transistor together with the replacement-gate process, the forming of the buried insulated region is self-aligned with the gate, which reduces the parasitic resistance under the spacer.02-23-2012
20120043623METHOD AND STRUCTURE FOR FORMING HIGH-K/METAL GATE EXTREMELY THIN SEMICONDUCTOR ON INSULATOR DEVICE - A semiconductor device is provided that includes a gate structure present on a substrate. The gate structure includes a gate conductor with an undercut region in sidewalls of a first portion of the gate conductor, wherein a second portion of the gate conductor is present over the first portion of the gate conductor and includes a protruding portion over the undercut region. A spacer is adjacent to sidewalls of the gate structure, wherein the spacer includes an extending portion filling the undercut region. A raised source region and a raised drain region is present adjacent to the spacers. The raised source region and the raised drain region are separated from the gate conductor by the extending portion of the spacers.02-23-2012
20120043622PROGRAMMABLE FETs USING Vt-SHIFT EFFECT AND METHODS OF MANUFACTURE - Programmable field effect transistors (FETs) are provided using high-k dielectric metal gate Vt shift effect and methods of manufacturing the same. The method of controlling Vt shift in a high-k dielectric metal gate structure includes applying a current to a gate contact of the high-k dielectric metal gate structure to raise a temperature of a metal forming a gate stack. The temperature is raised beyond a Vt shift temperature threshold for providing an on-state.02-23-2012
20100276763LGA SUBSTRATE AND METHOD OF MAKING SAME - A transistor comprises a gate (11-04-2010
20110049646Semiconductor Device and Method of Forming the Same - Methods of forming a semiconductor device include forming an insulation layer on a semiconductor structure, forming an opening in the insulation layer, the opening having a sidewall defined by one side of the insulation layer, forming a first metal layer in the opening, at least partially exposing the sidewall of the opening by performing a wet-etching process on the first metal layer, and selectively forming a second metal layer on the etched first metal layer. An average grain size of the first metal layer is smaller than an average grain size of the second metal layer. Related semiconductor devices are also disclosed.03-03-2011
20110049645STRUCTURE WITH REDUCED FRINGE CAPACITANCE - A structure includes a substrate and a gate stack disposed on the substrate. The structure also includes a nitride encapsulation layer disposed on a side wall of the gate stack and which has been exposed to a plasma source. The structure also includes at least one other element contacting the nitride encapsulation layer in a region where the nitride encapsulation layer contacts the side wall of the gate stack.03-03-2011
20120153406SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes forming a gate dielectric layer over a substrate, forming a dipole capping layer over the gate dielectric layer, stacking a metal gate layer and a polysilicon layer over the dipole capping layer, and forming a gate pattern by etching the polysilicon layer, the metal gate layer, the dipole capping layer, and the gate dielectric layer.06-21-2012
20120153405Semiconductor Device Comprising a Contact Structure with Reduced Parasitic Capacitance - In sophisticated semiconductor devices, at least a portion of the interlayer dielectric material of the contact level may be provided in the form of a low-k dielectric material which may, in some illustrative embodiments, be accomplished on the basis of a replacement gate approach. Hence, superior electrical performance, for instance with respect to the parasitic capacitance, may be accomplished.06-21-2012
20120025326SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - An interface oxide layer, a gate insulating film, and a gate electrode are sequentially provided on the upper surface of a semiconductor substrate. The gate insulating film has a first high-k film and a second high-k film. The first high-k film is provided on the interface oxide layer, and contains nitrogen. The second high-k film is provided on the first high-k film, and contains nitrogen. The first high-k film has a lower nitrogen concentration than the second high-k film.02-02-2012
20120061772Transistor having replacement metal gate and process for fabricating the same - A transistor is fabricated by removing a polysilicon gate over a doped region of a substrate and forming a mask layer over the substrate such that the doped region is exposed through a hole within the mask layer. An interfacial layer is deposited on top and side surfaces of the mask layer and on a top surface of the doped region. A layer adapted to reduce a threshold voltage of the transistor and/or reduce a thickness of an inversion layer of the transistor is deposited on the interfacial layer. The layer includes metal, such as aluminum or lanthanum, which diffuses into the interfacial layer, and also includes oxide, such as hafnium oxide. A conductive plug, such as a metal plug, is formed within the hole of the mask layer. The interfacial layer, the layer on the interfacial layer, and the conductive plug are a replacement gate of the transistor.03-15-2012
20100096704Suspended nanochannel transistor structure and method for fabricating the same - The present invention discloses a suspended nanochannel transistor structure and a method for fabricating the same. The transistor structure of the present invention comprises a substrate; a side gate formed on the substrate; a dielectric layer covering the substrate and the side gate; a suspended nanochannel formed beside the lateral of the side gate with an air gap existing between the suspended nanochannel and the dielectric layer; a source and a drain formed over the dielectric layer and respectively arranged at two ends of the suspended nanochannel. The electrostatic force of the side gate attracts or repels the suspended nanochannel and thus fast varies the equivalent thickness of the side-gate dielectric layer. Thereby, the on/off state of the element is rapidly switched, or the initial voltage of the channel is altered.04-22-2010
20090134479Semiconductor device and method for manufacturing the same - It is possible to prevent the deterioration of device characteristic as much as possible. A semiconductor device includes: a semiconductor substrate; a gate insulating film provided above the semiconductor substrate and containing a metal, oxygen and an additive element; a gate electrode provided above the gate insulating film; and source/drain regions provided in the semiconductor substrate on both sides of the gate electrode. The additive element is at least one element selected from elements of Group 5, 6, 15, and 16 at a concentration of 0.003 atomic % or more but 3 atomic % or less.05-28-2009
20110089501Tunable Stressed Polycrystalline Silicon on Dielectrics in an Integrated Circuit - A method of forming an integrated circuit device is disclosed. A polycrystalline silicon layer is formed in direct contact with a dielectric material so that the dielectric material induces a stress in the polycrystalline silicon layer as the polycrystalline silicon layer is formed. A MOS transistor that includes a gate comprising the polycrystalline silicon is then completed.04-21-2011
20120119307SELF-ALIGNED CONTACT EMPLOYING A DIELECTRIC METAL OXIDE SPACER - A dielectric liner is formed on sidewalls of a gate stack and a lower contact-level dielectric material layer is deposited on the dielectric liner and planarized. The dielectric liner is recessed relative to the top surface of the lower contact-level dielectric material layer and the top surface of the gate stack. A dielectric metal oxide layer is deposited and planarized to form a dielectric metal oxide spacer that surrounds an upper portion of the gate stack. The dielectric metal oxide layer has a top surface that is coplanar with a top surface of the planarized lower contact-level dielectric material layer. Optionally, the conductive material in the gate stack may be replaced. After deposition of at least one upper contact-level dielectric material layer, at least one via hole extending to a semiconductor substrate is formed employing the dielectric metal oxide spacer as a self-aligning structure.05-17-2012
20120119308GATE ETCH OPTIMIZATION THROUGH SILICON DOPANT PROFILE CHANGE - Improved semiconductor devices including metal gate electrodes are formed with reduced performance variability by reducing the initial high dopant concentration at the top portion of the silicon layer overlying the metal layer. Embodiments include reducing the dopant concentration in the upper portion of the silicon layer, by implanting a counter-dopant into the upper portion of the silicon layer, removing the high dopant concentration portion and replacing it with undoped or lightly doped silicon, and applying a gettering agent to the upper surface of the silicon layer to form a thin layer with the gettered dopant, which layer can be removed or retained.05-17-2012
20120211844Semiconductor Device Comprising Self-Aligned Contact Elements and a Replacement Gate Electrode Structure - When forming sophisticated semiconductor devices including high-k metal gate electrode structures, a raised drain and source configuration may be used for controlling the height upon performing a replacement gate approach, thereby providing superior conditions for forming contact elements and also obtaining a well-controllable reduced gate height.08-23-2012
20100244156METHODS FOR PROTECTING GATE STACKS DURING FABRICATION OF SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICES FABRICATED FROM SUCH METHODS - Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methods are provided. In an embodiment, a method for fabricating a semiconductor device comprises forming a gate stack comprising a first gate stack-forming layer overlying a semiconductor substrate and forming first sidewall spacers about sidewalls of the gate stack. After the step of forming the first sidewall spacers, a portion of the first gate stack-forming layer is exposed. The exposed portion is anisotropically etched using the gate stack and the first sidewall spacers as an etch mask. Second sidewall spacers are formed adjacent the first sidewall spacers after the step of anisotropically etching.09-30-2010
20120133000FIELD EFFECT TRANSISTOR WITH CHANNEL REGION EDGE AND CENTER PORTIONS HAVING DIFFERENT BAND STRUCTURES FOR SUPPRESSED CORNER LEAKAGE - Disclosed are embodiments of field effect transistors (FETs) having suppressed sub-threshold corner leakage, as a function of channel material band-edge modulation. Specifically, the FET channel region is formed with different materials at the edges as compared to the center. Different materials with different band structures and specific locations of those materials are selected in order to effectively raise the threshold voltage (Vt) at the edges of the channel region relative to the Vt at the center of the channel region and, thereby to suppress of sub-threshold corner leakage. Also disclosed are design structures for such FETs and method embodiments for forming such FETs.05-31-2012
20090057786SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a high dielectric constant gate insulator film provided on a Si substrate which is a semiconductor substrate, a gate electrode formed on the high dielectric constant gate insulator film, a protective film provided on side surfaces of the high dielectric constant gate insulator film and the gate insulator, and a side wall film provided on the outside of the protective film. The protective film includes a high dielectric constant material having, in its composition, at least one metal selected from the group consisting of Hf, Zr, Al, La, Pr, Y, Ti, Ta and W, whereby it is possible to suppress the causes of such troubles as dispersions of characteristics and deterioration of short channel characteristic.03-05-2009
20120168880Method of Fabricating Semiconductor Device - Method of fabricating thin-film transistors in which contact with connecting electrodes becomes reliable. When contact holes are formed, the bottom insulating layer is subjected to a wet etching process, thus producing undercuttings inside the contact holes. In order to remove the undercuttings, a light etching process is carried out to widen the contact holes. Thus, tapering section are obtained, and the covering of connection wiring is improved.07-05-2012
20100052075INTEGRATING A FIRST CONTACT STRUCTURE IN A GATE LAST PROCESS - A semiconductor device is provided which includes a semiconductor substrate, a transistor formed on the substrate, the transistor having a gate stack including a metal gate and high-k gate dielectric and a dual first contact formed on the substrate. The dual first contact includes a first contact feature, a second contact feature overlying the first contact feature, and a metal barrier formed on sidewalls and bottom of the second contact feature, the metal barrier layer coupling the first contact feature to the second contact feature.03-04-2010
20090115001MOS DEVICES WITH MULTI-LAYER GATE STACK - An embodiment of a semiconductor device includes a semiconductor substrate having a principal surface, spaced-apart source and drain regions separated by a channel region at the principal surface, and a multilayered gate structure located over the channel region. The multilayered gate structure includes a gate dielectric layer in contact with the channel region, a first conductor comprising a metal oxide overlying the gate dielectric layer, a second conductor overlying the first conductor, and an impurity migration inhibiting layer between the gate dielectric layer and the first conductor or between the first conductor and the second conductor.05-07-2009
20100270626ATOMIC LAYER DEPOSITION OF HAFNIUM LANTHANUM OXIDES - There is provided an improved method for depositing thin films using precursors to deposit binary oxides by atomic layer deposition (ALD) techniques. Also disclosed is an ALD method for depositing a high-k dielectric such as hafnium lanthanum oxide (HfLaO) on a substrate. Embodiments of the present invention utilize a combination of ALD precursor elements and cycles to deposit a film with desired physical and electrical characteristics. Electronic components and systems that integrate devices fabricated with methods consistent with the present invention are also disclosed.10-28-2010
20120217590Filling Narrow Openings Using Ion Beam Etch - Generally, the subject matter disclosed herein relates to modern sophisticated semiconductor devices and methods for forming the same, wherein a multilayer metal fill may be used to fill narrow openings formed in an interlayer dielectric layer. One illustrative method disclosed herein includes forming an opening in a dielectric material layer of a semiconductor device formed above a semiconductor substrate, the opening having sidewalls and a bottom surface. The method also includes forming a first layer of first fill material above the semiconductor device by forming the first layer inside the opening and at least above the sidewalls and the bottom surface of the opening. Furthermore, the method includes performing a first angled etching process to at least partially remove the first layer of first fill material from above the semiconductor device by at least partially removing a first portion of the first layer proximate an inlet of the opening without removing a second portion of the first layer proximate the bottom of said opening, and forming a second layer of second fill material above the semiconductor device by forming the second layer inside the opening and above the first layer.08-30-2012
20120074508POWER SEMICONDUCTOR DEVICE - A power semiconductor device less prone to cause a reaction between a metal material for interconnection and an electrode or the like connected to a semiconductor region during the high-temperature operation thereof and less prone to be strained during the high-temperature operation thereof. The power semiconductor device can be an SiC power device or the like in which a first metal layer containing at least one selected from the group consisting of Pt, Ti, Mo, W and Ta is formed on a source electrode formed on the semiconductor region, such as a source region or the like. A second metal layer containing at least one selected from the group consisting of Mo, W and Cu is formed on the first metal layer. A third metal layer containing at least one selected from the group consisting of Pt, Mo and W is formed on the second metal layer.03-29-2012
20100006956Metal High-K Transistor Having Silicon Sidewall For Reduced Parasitic Capacitance, And Process To Fabricate Same - A method is disclosed to reduce parasitic capacitance in a metal high dielectric constant (MHK) transistor. The method includes forming a MHK gate stack upon a substrate, the MHK gate stack having a bottom layer of high dielectric constant material, a middle layer of metal, and a top layer of one of amorphous silicon or polycrystalline silicon. The method further forms a depleted sidewall layer on sidewalls of the MHK gate stack so as to overlie the middle layer and the top layer, and not the bottom layer. The depleted sidewall layer is one of amorphous silicon or polycrystalline silicon. The method further forms an offset spacer layer over the depleted sidewall layer and over exposed surfaces of the bottom layer.01-14-2010
20100006955METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A semiconductor device manufacturing method includes the steps of: successively forming, on a semiconductor substrate, a gate insulating film and first and second dummy sections stacked in this order; forming a notch section by processing the gate insulating film and the first and second dummy gate sections into a previously set pattern and making the first dummy gate section move back in the gate length direction relative to the second dummy gate section; forming a side wall of an insulating material in a side part of each of the gate insulating film and the first and second dummy gate sections and embedding the notch section therewith; removing the first and second dummy gate sections to leave the gate insulating film and the notch section in the bottom of a removed portion; and forming a gate electrode made of a conductive material by embedding the removed portion with the conductive material.01-14-2010
20100006953INTEGRATED CIRCUIT INCLUDING A DIELECTRIC LAYER - An integrated circuit including a dielectric layer and a method for manufacturing. One embodiment provides a substrate having a first side and a second side and at least one dielectric layer. The dielectric layer includes a zirconium oxide and at least one dopant selected from the group consisting of hafnium and titanium and having a first side and a second side. The first side of the dielectric layer is arranged at least on a subarea of the first side of the semiconductor substrate.01-14-2010
20120256277SEMICONDUCTOR DEVICE EXHIBITING REDUCED PARASITICS AND METHOD FOR MAKING SAME - A semiconductor device includes a substrate and a gate stack disposed on the substrate. An upper layer of the gate stack is a metal gate conductor and a lower layer of the gate stack is a gate dielectric. A gate contact is in direct contact with the metal gate conductor.10-11-2012
20120256276Metal Gate and Fabricating Method Thereof - A method of manufacturing a metal gate is provided. The method includes providing a substrate. Then, a gate dielectric layer is formed on the substrate. A multi-layered stack structure having a work function metal layer is formed on the gate dielectric layer. An O10-11-2012
20120256275METAL GATE STRUCTURE AND MANUFACTURING METHOD THEREOF - A manufacturing method of a metal gate structure includes first providing a substrate having a dummy gate formed thereon. The dummy gate includes a high-K gate dielectric layer, a bottom barrier layer, a first etch stop layer and a sacrificial layer sequentially and upwardly stacked on the substrate. Then, the sacrificial layer is removed to form a gate trench with the first etch stop layer exposed on the bottom of the gate trench. After forming the gate trench, a first work function metal layer is formed in the gate trench.10-11-2012
20090026556Nitride semiconductor device and method for producing nitride semiconductor device - A method for producing a nitride semiconductor device according to the present invention includes the steps of: forming an insulating film containing oxygen on the surface of a group III nitride semiconductor; and placing the group III nitride semiconductor under a nitrogen atmosphere in advance of the step of forming the insulating film. A nitride semiconductor device according to the present invention includes a group III nitride semiconductor; and an insulating film containing oxygen formed on the surface of the group III nitride semiconductor, wherein the nitrogen concentration in a region provided with the insulating film is higher than the nitrogen concentration in a region not provided with the insulating film on the surface of the group III nitride semiconductor.01-29-2009
20090020835INSULATING FILM AND ELECTRONIC DEVICE - An electronic device including a semiconductor layer containing silicon as a major component; and a dielectric film epitaxially grown directly on a major surface of the semiconductor layer, a difference between 201-22-2009
20120228724Non-Volatile Anti-Fuse With Consistent Rupture - In an embodiment of the invention, a non-volatile anti-fuse memory cell is disclosed. The memory cell consists of a programmable n-channel diode-connectable transistor. The poly-silicon gate of the transistor has two portions. One portion is doped more highly than a second portion. The transistor also has a source with two portions where one portion of the source is doped more highly than a second portion. The portion of the gate that is physically closer to the source is more lightly doped than the other portion of the poly-silicon gate. The portion of the source that is physically closer to the lightly doped portion of the poly-silicone gate is lightly doped with respect to the other portion of the source. When the transistor is programmed, a rupture in the insulator will most likely occur in the portion of the poly-silicone gate that is heavily doped.09-13-2012
20110121409Field effect transistors, methods of fabricating a carbon-insulating layer using molecular beam epitaxy and methods of fabricating a field effect transistor - Field effect transistors, methods of fabricating a carbon insulating layer using molecular beam epitaxy and methods of fabricating a field effect transistor using the same are provided, the methods of fabricating the carbon insulating layer include maintaining a substrate disposed in a molecular beam epitaxy chamber at a temperature in a range of about 300° C. to about 500° C. and maintaining the chamber in vacuum of 1005-26-2011
20100327376Metal High-K Transistor Having Silicon Sidewall For Reduced Parasitic Capacitance, And Process To Fabricate Same - A method forms a metal high dielectric constant (MHK) transistor and includes: providing a MHK stack disposed on a substrate, the MHK stack including a first layer of high dielectric constant material, a second overlying layer, and a third overlying layer; selectively removing only the second and third layers, without removing the first layer, to form an upstanding portion of a MHK gate structure; forming a first sidewall layer on sidewalls of the upstanding portion of the MHK gate structure; forming a second sidewall layer on sidewalls of the first sidewall layer; removing a portion of the first layer to form exposed surfaces; forming an offset spacer layer over the second sidewall layer and over the first layer, and forming in the substrate extensions that underlie the first and second sidewall layers and that extend under a portion but not all of the upstanding portion of the MHK gate structure.12-30-2010
20080296704SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Top and bottom surfaces of a gate insulating film are terminated with fluorine atoms and the top surface of the gate insulating film is then etched. New dangling bonds are formed on the top surface of the gate insulating film. Such new dangling bonds are terminated with nitrogen atoms. A semiconductor device is thus obtained that has a silicon substrate and a gate insulating film formed on the silicon substrate and that almost all dangling bonds on the top surface of the gate insulating film are terminated with nitrogen atoms and almost all dangling bonds on the bottom surface contacting the silicon substrate are terminated with fluorine atoms.12-04-2008
20120261769METHOD OF MAKING A SEMICONDUCTOR STRUCTURE USEFUL IN MAKING A SPLIT GATE NON-VOLATILE MEMORY CELL - A semiconductor device comprises a semiconductor substrate and a select gate structure over a first portion of the semiconductor substrate. The select gate structure comprises a sidewall forming a corner with a second portion of the semiconductor substrate and a charge storage stack over an area comprising the second portion of the semiconductor substrate, the sidewall, and the corner. A corner portion of a top surface of the charge storage stack is non-conformal with the corner, and the corner portion of the top surface of the charge storage stack has a radius of curvature measuring approximately one-third of a thickness of the charge storage stack over the second portion of the substrate or greater. A control gate layer is formed over the charge storage stack. A portion of the control gate layer conforms to the corner portion of the top surface of the charge storage stack.10-18-2012
20120261770METAL GATE STRUCTURE - A metal gate structure includes a high-K gate dielectric layer, an N-containing layer, a work function metal layer, and an N-trapping layer. The N-containing layer is positioned between the work function metal layer and the high-K gate dielectric layer. The N-trapping layer is positioned between the work function metal layer and the high-K gate dielectric layer, and the N-trapping layer contains no nitrogen or low-concentration nitrogen.10-18-2012
20120299123Gate-Last Fabrication of Quarter-Gap MGHK FET - A quarter-gap p-type field effect transistor (PFET) formed by gate-last fabrication includes a gate stack formed on a silicon substrate, the gate stack including: a high-k dielectric layer located on the silicon substrate; and a gate metal layer located over the high-k dielectric layer, the gate metal layer including titanium nitride and having a thickness of about 20 angstroms; and a metal contact formed over the gate stack. A quarter-gap n-type field effect transistor (NFET) formed by gate-last fabrication includes a gate stack formed on a silicon substrate, the gate stack including: a high-k dielectric layer located on the silicon substrate; and a first gate metal layer located over the high-k dielectric layer, the first gate metal layer including titanium nitride; and a metal contact formed over the gate stack.11-29-2012
20110037131GATE STRUCTURE FOR FIELD EFFECT TRANSISTOR - A field effect transistor having a gate structure that comprises an interfacial layer positioned in between the transistor channel region and a high-K dielectric layer of the gate stack. The interfacial layer comprises Al02-17-2011
20120319215SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The present invention discloses a semiconductor device and method of manufacturing the same, comprising: forming an insulating isolation layer on a substrate; forming an insulating isolation layer trench in the insulating isolation layer; forming an active region layer in the insulating isolation layer trench; and forming a semiconductor device structure in and above the active region layer, wherein the carrier mobility of the active region layer is higher than that of the substrate. In accordance with the semiconductor device and the manufacturing method thereof in the present invention, an active region formed of a material different from that of the substrate is used, the carrier mobility in the channel region is enhanced, thereby the device response speed is substantially improved and the device performance is enhanced greatly. Furthermore, unlike the existing STI manufacturing process, in the present invention a STI is formed first, and then filling is performed to form an active region, to avoid the problem of generation of holes in the STI and improve the device reliability.12-20-2012
20120319214STRUCTURE OF METAL GATE AND FABRICATION METHOD THEREOF - A method for fabricating a metal gate includes the following steps. First, a substrate having an interfacial dielectric layer above the substrate is provided. Then, a gate trench having a barrier layer is formed in the interfacial dielectric layer. A source layer is disposed above the barrier layer. Next, a process is performed to have at least one element in the source layer move into the barrier layer. Finally, the barrier layer is removed and a metal layer fills up the gate trench.12-20-2012
20110227170MOSFET STRUCTURE AND METHOD OF FABRICATING THE SAME - There is provided a MOSFET structure and a method of fabricating the same. The method comprises: providing a semiconductor substrate; forming a dummy s gate on the semiconductor substrate; forming source/drain regions; selectively etching the dummy gate to a position where a channel is to be formed; and epitaxially growing a channel layer at the position where the channel is to be formed and forming a gate on the channel layer, wherein the channel layer comprises a material of high mobility. Thereby, the channel of the device is replaced with the material of high mobility after the source/drain region is formed, and thus it is possible to suppress the short channel effect and also to improve the device performance.09-22-2011
20120080760Dielectric structure, transistor and manufacturing method thereof - The present invention discloses a dielectric structure, a transistor and a manufacturing method thereof with praseodymium oxide. The transistor with praseodymium oxide comprises at least a III-V substrate, a gate dielectric layer and a gate. The gate dielectric layer is disposed on the III-V substrate, and the gate is disposed on the gate dielectric layer, and the gate dielectric layer is praseodymium oxide (Pr04-05-2012
20120326244SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate, a source region, a drain region, an insulating film and a gate electrode. The source region is formed in the semiconductor substrate. The drain region is formed in the semiconductor substrate with being separate from the source region. The insulating film is formed between the source region and the drain region and on or above the semiconductor substrate. The insulating film includes lanthanum aluminate containing at least one element selected from Si, Ge, Mg, Ca, Sr, Ba and N. The lanthanum aluminate contains at least one element selected from Ti, Hf and Zr. The gate electrode is formed on the insulating film.12-27-2012
20120326243TRANSISTOR HAVING ALUMINUM METAL GATE AND METHOD OF MAKING THE SAME - A transistor having an aluminum metal gate includes a substrate, a high-k gate dielectric layer, an aluminum metal gate and a source/drain region. The high-k gate dielectric layer is disposed on the substrate. The aluminum metal gate includes a work function tuning layer and an aluminum metal layer disposed orderly on the high-k gate dielectric layer, where the aluminum metal layer comprises a first aluminum metal layer and a second aluminum metal layer. Furthermore, the source/drain region is disposed in the substrate at each of two sides of the aluminum metal gate.12-27-2012
20120091540STRAINED STRUCTURE OF A P-TYPE FIELD EFFECT TRANSISTOR - In a p-type field effect transistor, a pair of spacers are formed over the top surface of a substrate. A channel recess cavity includes an indentation in the substrate top surface between the pair of spacers. A gate stack has a bottom portion in the channel recess cavity and a top portion extending outside the channel recess cavity. A source/drain (S/D) recess cavity has a bottom surface and sidewalls below the substrate top surface. The S/D recess cavity has a portion extending below the gate stack. A strained material is filled the S/D recess cavity04-19-2012
20120286373GATE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - Gates structures and methods for manufacturing the same are disclosed. In an example, the gate structure comprises a gate stack formed on a semiconductor substrate, the gate stack comprising a high-K dielectric layer and a metal gate electrode from bottom to top; a first dielectric layer on sidewalls of the gate stack, the first dielectric layer serving as first sidewall spacers; and a sacrificial metal layer on the first dielectric layer, the sacrificial metal layer serving as second sidewall spacers. The sacrificial metal layer in the gate structure reduces a thickness of an interfacial oxide layer in the step of annealing. The gate structure may be applied to a semiconductor device having a small size because the gate dielectric layer has a low EOT value.11-15-2012
20120286372Reliability of high-K gate dielectric layers - A method for improving the reliability of a high-k gate dielectric layer comprises incorporating a noble metal into a transistor gate stack that contains the high-k gate dielectric layer and annealing the transistor gate stack in a molecular hydrogen or deuterium containing atmosphere. The annealing process drives at least a portion of the molecular hydrogen or deuterium toward the high-k gate dielectric layer. When the molecular hydrogen or deuterium contacts the noble metal, it is converted into atomic hydrogen or deuterium that is able to treat the high-k gate dielectric layer and improve its reliability.11-15-2012
20100213553METAL OXIDE SEMICONDUCTOR DEVICES HAVING BURIED GATE CHANNELS AND METHODS FOR FABRICATING THE SAME - Methods for forming a semiconductor device comprising a semiconductor substrate are provided. In accordance with an exemplary embodiment, a method comprises forming a channel layer overlying the semiconductor substrate, forming a channel capping layer having a first surface overlying the channel layer, oxidizing the first surface of the channel capping layer, and depositing a high-k dielectric layer overlying the channel capping layer.08-26-2010
20130020656HIGH PERFORMANCE HKMG STACK FOR GATE FIRST INTEGRATION - Semiconductor devices are formed with a silicide interface between the work function layer and polycrystalline silicon. Embodiments include forming a high-k/metal gate stack by: forming a high-k dielectric layer on a substrate, forming a work function metal layer on the high-k dielectric layer, forming a silicide on the work function metal layer, and forming a poly Si layer on the silicide. Embodiments include forming the silicide by: forming a reactive metal layer in situ on the work function layer, forming an a-Si layer in situ on the entire upper surface of the reactive metal layer, and annealing concurrently with forming the poly Si Layer.01-24-2013
20120241873SEMICONDUCTOR DEVICE - A semiconductor device is disclosed. The semiconductor device includes: a substrate; a gate structure disposed on the substrate, wherein the gate structure comprises a high-k dielectric layer; and a first seal layer disposed on a sidewall of the gate structure, wherein the first seal layer is an oxygen-free seal layer.09-27-2012
20080246099LOW TEMPERATURE POLY OXIDE PROCESSES FOR HIGH-K/METAL GATE FLOW - An integrated circuit device is disclosed as comprising a feature that is susceptible to oxidation. A poly-oxide coating is used over the feature susceptible to oxidation to protect the feature susceptible to oxidation from oxidizing. Various method can be used to form the poly-oxide coating include conversion of a ploy-silicon coating using UV O10-09-2008
20090218639SEMICONDUCTOR DEVICE COMPRISING A METAL GATE STACK OF REDUCED HEIGHT AND METHOD OF FORMING THE SAME - By providing a CMP stop layer in a metal gate stack, the initial height thereof may be efficiently reduced after the definition of the deep drain and source areas, thereby providing enhanced process conditions for forming highly stressed dielectric materials. Consequently, the dielectric material may be positioned more closely to the channel region substantially without deteriorating gate conductivity.09-03-2009
20130168780METHOD AND STRUCTURE TO REDUCE FET THRESHOLD VOLTAGE SHIFT DUE TO OXYGEN DIFFUSION - Oxygen scavenging material embedded in an isolation structure provides improved protection of high dielectric constant (Hi-K) materials from oxygen contamination while avoiding alteration of work function and switching threshold shift in transistors including such Hi-K materials.07-04-2013
20130140645SEMICONDUCTOR FUSES IN A SEMICONDUCTOR DEVICE COMPRISING METAL GATES - In a replacement gate approach, the semiconductor material of the gate electrode structures may be efficiently removed during a wet chemical etch process, while this material may be substantially preserved in electronic fuses. Consequently, well-established semiconductor-based electronic fuses may be used instead of requiring sophisticated metal-based fuse structures. The etch selectivity of the semiconductor material may be modified on the basis of ion implantation or electron bombardment.06-06-2013
20080217706SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - There is provided a method of manufacturing a semiconductor device, including forming a structure including a first layer containing Si and a metal oxide layer in contact with the first layer, the metal oxide layer having a dielectric constant higher than that of silicon oxide, and heating the structure in an atmosphere containing He and/or Ne.09-11-2008
20120248550PLASMA DOPING TO REDUCE DIELECTRIC LOSS DURING REMOVAL OF DUMMY LAYERS IN A GATE STRUCTURE - The embodiments of methods and structures disclosed herein provide mechanisms of performing doping an inter-level dielectric film, ILD10-04-2012
20130093029PROCESS FOR PREPARING A BERYLLIUM OXIDE LAYER ON A SEMICONDUCTOR SUBSTRATE - A process for creating a beryllium oxide film on the surface of a semiconductor material is disclosed. The process is useful for making gate dielectric layers for metal-oxide-semiconductor (MOS) devices, particularly III-V semiconductor devices.04-18-2013
20110266637Precise Resistor on a Semiconductor Device - A method includes forming a polysilicon layer on a substrate; and patterning the polysilicon layer to form a polysilicon resistor and a polysilicon gate. A first ion implantation is performed on the polysilicon resistor to adjust electric resistance of the polysilicon resistor. A second ion implantation is performed on a top portion of the polysilicon resistor such that the top portion of the polysilicon resistor has an enhanced etch resistance. An etch process is then used to remove the polysilicon gate while the polysilicon resistor is protected by the top portion.11-03-2011
20130126984Patterning of Sensitive Metal-Containing Layers With Superior Mask Material Adhesion by Providing a Modified Surface Layer - When patterning metal-containing material layers, such as titanium nitride, in critical manufacturing stages, for instance upon forming sophisticated high-k metal gate electrode structures or providing hard mask materials for patterning a metallization system, the surface adhesion of a resist material on the titanium nitride material may be improved by applying a controlled oxidation process.05-23-2013
20110272765MOSFET GATE AND SOURCE/DRAIN CONTACT METALLIZATION - A MOSFET is described incorporating a common metal process to make contact to the source, drain and the metal gate respectively which may be formed concurrently with the same metal or metals.11-10-2011
20130175641REPLACEMENT GATE MOSFET WITH A HIGH PERFORMANCE GATE ELECTRODE - In a replacement gate scheme, a continuous material layer is deposited on a bottom surface and a sidewall surface in a gate cavity. A vertical portion of the continuous material layer is removed to form a gate component of which a vertical portion does not extend to a top of the gate cavity. The gate component can be employed as a gate dielectric or a work function metal portion to form a gate structure that enhances performance of a replacement gate field effect transistor.07-11-2013
20120273903SEMICONDUCTOR DEVICE - A semiconductor device includes: a high dielectric constant gate insulating film formed on an active region in a substrate; a gate electrode formed on the high dielectric constant gate insulating film; and an insulating sidewall formed on each side surface of the gate electrode. The high dielectric constant gate insulating film is continuously formed so as to extend from under the gate electrode to under the insulating sidewall. At least part of the high dielectric constant gate insulating film located under the insulating sidewall has a smaller thickness than a thickness of part of the high dielectric constant gate insulating film located under the gate electrode.11-01-2012
20120273902GATE STACK STRUCTURE WITH ETCH STOP LAYER AND MANUFACTURING PROCESS THEREOF - A gate stack structure with an etch stop layer is provided. The gate stack structure is formed over a substrate. A spacer is formed on a sidewall of the gate stack structure. The gate stack structure includes a gate dielectric layer, a barrier layer, a repair layer and the etch stop layer. The gate dielectric layer is formed on the substrate. The barrier layer is formed on the gate dielectric layer. The barrier layer and an inner sidewall of the spacer collectively define a trench. The repair layer is formed on the barrier layer and an inner wall of the trench. The etch stop layer is formed on the repair layer.11-01-2012
20120273901SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - The present invention relates to a semiconductor device and a method for manufacturing the same. According to the present invention, when a gate is formed via a replacement gate process, a portion of a work function metal layer and a portion of a first metal layer are removed after the work function metal layer and the first metal layer are formed, and then the removed portions are replaced with a second metal layer. A device having such a gate structure greatly reduces the resistivity of the whole gate, due to a portion of the work function metal layer with a high resistivity being removed and the removed portion being filled with the second metal layer with a low resistivity, thereby AC performances of the device are improved.11-01-2012
20130119485Transistor Performance Improving Method with Metal Gate - The present disclosure provides a method for making a semiconductor device having metal gate stacks. The method includes forming a high k dielectric material layer on a semiconductor substrate; forming a first metal layer on the high k dielectric material layer; forming a silicon layer on the first metal layer; patterning the silicon layer, the first metal layer and the high k dielectric material layer to form a gate stack; and performing a silicidation process to fully change the silicon layer into a silicide electrode.05-16-2013
20110309455Gate-Last Fabrication of Quarter-Gap MGHK FET - A quarter-gap p-type field effect transistor (PFET) formed by gate-last fabrication includes a gate stack formed on a silicon substrate, the gate stack including: a high-k dielectric layer located on the silicon substrate; and a gate metal layer located over the high-k dielectric layer, the gate metal layer including titanium nitride and having a thickness of about 20 angstroms; and a metal contact formed over the gate stack. A quarter-gap n-type field effect transistor (NFET) formed by gate-last fabrication includes a gate stack formed on a silicon substrate, the gate stack including: a high-k dielectric layer located on the silicon substrate; and a first gate metal layer located over the high-k dielectric layer, the first gate metal layer including titanium nitride; and a metal contact formed over the gate stack.12-22-2011
20130187241INTERFACIAL LAYER REGROWTH CONTROL IN HIGH-K GATE STRUCTURE FOR FIELD EFFECT TRANSISTOR - A field effect transistor having a gate structure comprising a high-K dielectric layer, a gate electrode located on the high-K dielectric layer, and an interfacial layer located in between the high-K dielectric layer and a channel region of the field effect transistor. The interfacial layer comprises a layer of SiO07-25-2013
20130187242CHANNEL SURFACE TECHNIQUE FOR FABRICATION OF FinFET DEVICES - A FinFET (p-channel) device is formed having a fin structure with sloped or angled sidewalls (e.g., a pyramidal or trapezoidal shaped cross-section shape). When using conventional semiconductor substrates having a (100) surface orientation, the fin structure is formed in a way (groove etching) which results in sloped or angled sidewalls having a (111) surface orientation. This characteristic substantially increases hole mobility as compared to conventional fin structures having vertical sidewalls.07-25-2013
20120018816SELF-ALIGNED SILICIDATION FOR REPLACEMENT GATE PROCESS - A semiconductor device is formed with low resistivity self aligned silicide contacts with high-K/metal gates. Embodiments include postponing silicidation of a metal layer on source/drain regions in a silicon substrate until deposition of a high-K dielectric, thereby preserving the physical and morphological properties of the silicide film and improving device performance. An embodiment includes forming a replaceable gate electrode on a silicon-containing substrate, forming source/drain regions, forming a metal layer on the source/drain regions, forming an ILD over the metal layer on the substrate, removing the replaceable gate electrode, thereby forming a cavity, depositing a high-K dielectric layer in the cavity at a temperature sufficient to initiate a silicidation reaction between the metal layer and underlying silicon, and forming a metal gate electrode on the high-K dielectric layer.01-26-2012

Patent applications in class Gate insulator includes material (including air or vacuum) other than SiO 2

Patent applications in all subclasses Gate insulator includes material (including air or vacuum) other than SiO 2