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Including lightly doped drain portion adjacent channel (e.g., lightly doped drain, LDD device)

Subclass of:

257 - Active solid-state devices (e.g., transistors, solid-state diodes)

257213000 - FIELD EFFECT DEVICE

257288000 - Having insulated electrode (e.g., MOSFET, MOS diode)

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DocumentTitleDate
20130134525METAL-OXIDE-SEMICONDUCTOR (MOS) DEVICE AND METHOD FOR FABRICATING THE SAME - A Metal-Oxide-Semiconductor (MOS) device is disclosed. The MOS device includes a substrate, a well region formed in the substrate, and a gate located on the substrate. The MOS device also includes a first lightly-doped region arranged in the well region at a first side of the gate and overlapping with the gate, and a second lightly-doped region arranged in the well region at a second side of the gate and overlapping with the gate. Further, the MOS device includes a first heavily-doped region formed in the first lightly-doped region, and a second heavily-doped region formed in the second lightly-doped region. The MOS device also includes a first high-low-voltage gate oxide boundary arranged between the first heavily-doped region and the gate, and a second high-low-voltage gate oxide boundary arranged between the second heavily-doped region and the gate. The gate covers the first high-low-voltage gate oxide boundary and the second high-low-voltage gate oxide boundary at the first side and the second side of the gate, respectively.05-30-2013
20110193179LIGHTLY DOPED SOURCE/DRAIN LAST METHOD FOR DUAL-EPI INTEGRATION - An integrated circuit device and method for fabricating the integrated circuit device is disclosed. The method involves providing a substrate; forming a gate structure over the substrate; forming an epitaxial layer in a source and drain region of the substrate that is interposed by the gate structure; and after forming the epitaxial layer, forming a lightly doped source and drain (LDD) feature in the source and drain region.08-11-2011
20110193178Bottom-Notched SiGe FinFET Formation Using Condensation - An integrated circuit structure includes a substrate and a germanium-containing semiconductor fin over the substrate. The germanium-containing semiconductor fin has an upper portion having a first width, and a neck region under the upper portion and having a second width smaller than the first width.08-11-2011
20100164021METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device may include implanting fluorine ions into a portion of a poly gate region on a semiconductor substrate; forming a gate oxide film over the semiconductor substrate such that the gate oxide film is thicker in the fluorine-implanted region; forming the poly gate over the gate oxide film in the poly gate region; and forming lightly doped drains in active regions of the semiconductor substrate on both sides of the poly gate. Further, the method of manufacturing the semiconductor device includes forming spacers over both sidewalls of the poly gate; and forming source and drain regions in the active regions.07-01-2010
20100164019METHOD OF MANUFACTURING NONVOLATILE MEMORY DEVICE - A method of manufacturing a nonvolatile memory (NVM) device having a memory gate and a selection gate. A method of manufacturing a NVM device may include a spacer poly formed on and/or over a surface of a substrate including a memory gate. A method of manufacturing a NVM device may include a sacrificing film formed on and/or over a surface of a spacer poly. A method of manufacturing a NVM device may include an etch-back process performed to form a selection gate. The thickness of a memory gate may be minimized. A bridge between a selection gate and a source/drain may be minimized.07-01-2010
20130075830SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - In a method, a gate dielectric film is formed on a semiconductor substrate. A gate electrode is formed on the gate dielectric film. Impurities of a first conduction-type are introduced into a drain-layer formation region. The impurities of the first conduction-type in the drain-layer formation region are activated by performing heat treatment. Single crystals of the semiconductor substrate in a source-layer formation region are amorphized by introducing inert impurities into the source-layer formation region. Impurities of a second conduction-type is introduced into the source-layer formation region. At least an amorphous semiconductor in the source-layer formation region is brought into a single crystal semiconductor and the impurities of the second conduction-type in the source-layer formation region is activated by irradiating the semiconductor substrate with microwaves. The impurities of the second conduction-type in the source-layer formation region is shallower than the impurities of the first conduction-type in the drain-layer formation region.03-28-2013
20130082335Extended Drain Lateral DMOS Transistor with Reduced Gate Charge and Self-Aligned Extended Drain - A method to form a LDMOS transistor includes forming a gate/source/body opening and a drain opening in a field oxide on a substrate structure, forming a gate oxide in the gate/source/body opening, and forming a polysilicon layer over the substrate structure. The polysilicon layer is anisotropically etched to form polysilicon spacer gates separated by a space in the gate/source/body opening and a polysilicon drain contact in the drain opening. A body region is formed self-aligned about outer edges of the polysilicon spacer gates, a source region is formed self-aligned about inner edges of the polysilicon spacer gates, and a drain region is formed under the polysilicon drain contact and self-aligned with respect to the polysilicon spacer gates. A drift region forms in the substrate structure between the body region and the drain region, and a channel region forms in the body region between the source region and the drift region.04-04-2013
20090159990SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device and/or a method of manufacturing the same that may include: Forming a gate insulating film over a semiconductor substrate in a gate region. Forming a first gate pattern over the gate insulating film. Forming a second gate pattern over the first gate pattern, such that the second gate pattern is wider than the first gate pattern. Forming sidewall spacers at both sides of the first gate pattern and the second gate pattern, such that spaces are formed between the sidewall spacers and the first gate pattern below the second gate pattern.06-25-2009
20090159989Semiconductor Device and Method of Fabricating the Same - Disclosed is a method of fabricating a semiconductor device. The method can include forming a gate material layer on an inner surface of a trench which extends into a part of a semiconductor substrate by passing through an insulating layer formed on the semiconductor substrate, etching the gate material layer to an initial height in the trench above a top surface of the semiconductor substrate, etching the insulating layer such that the thickness of the insulating layer is reduced, forming a gate electrode in the trench by secondarily etching the etched gate material layer, and removing the insulating layer having the reduced thickness.06-25-2009
20100109097INTEGRATED CIRCUIT SYSTEM EMPLOYING AN ELEVATED DRAIN - A method for manufacturing an integrated circuit system that includes: providing a substrate including an active device; forming a drift region in the substrate, the drift region bounded in part by a top surface of the substrate and spaced apart from a source; and forming a drain above the drift region.05-06-2010
20100025779SHALLOW PN JUNCTION FORMED BY IN SITU DOPING DURING SELECTIVE GROWTH OF AN EMBEDDED SEMICONDUCTOR ALLOY BY A CYCLIC GROWTH/ETCH DEPOSITION PROCESS - A silicon/carbon alloy may be formed in drain and source regions, wherein another portion may be provided as an in situ doped material with a reduced offset with respect to the gate electrode material. For this purpose, in one illustrative embodiment, a cyclic epitaxial growth process including a plurality of growth/etch cycles may be used at low temperatures in an ultra-high vacuum ambient, thereby obtaining a substantially bottom to top fill behavior.02-04-2010
20120181628METHOD TO TAILOR LOCATION OF PEAK ELECTRIC FIELD DIRECTLY UNDERNEATH AN EXTENSION SPACER FOR ENHANCED PROGRAMMABILITY OF A PROMPT-SHIFT DEVICE - A prompt-shift device having reduced programming time in the sub-millisecond range is provided. The prompt-shift device includes an altered extension region located within said semiconductor substrate and on at least one side of the patterned gate region, and an altered halo region located within the semiconductor substrate and on at least one side of the patterned gate region. The altered extension region has an extension ion dopant concentration of less than about 1E20 atoms/cm07-19-2012
20120181627METHOD TO TAILOR LOCATION OF PEAK ELECTRIC FIELD DIRECTLY UNDERNEATH AN EXTENSION SPACER FOR ENHANCED PROGRAMMABILITY OF A PROMPT-SHIFT DEVICE - A prompt-shift device having reduced programming time in the sub-millisecond range is provided. The prompt-shift device includes an altered extension region located within said semiconductor substrate and on at least one side of the patterned gate region, and an altered halo region located within the semiconductor substrate and on at least one side of the patterned gate region. The altered extension region has an extension ion dopant concentration of less than about 1E20 atoms/cm07-19-2012
20120181626Fabrication of Semiconductor Architecture Having Field-effect Transistors Especially Suitable for Analog Applications - An insulated-gate field-effect transistor (07-19-2012
20120181625METHOD OF MANUFACTURING STRAINED SOURCE/DRAIN STRUCTURES - An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides a processing for forming improved source/drain features in the semiconductor device. Semiconductor devices with the improved source/drain features may prevent or reduce defects and achieve high strain effect resulting from epi layers. In an embodiment, the source/drain features comprises a second portion surrounding a first portion, and a third portion between the second portion and the semiconductor substrate, wherein the second portion has a composition different from the first and third portions.07-19-2012
20090302400METAL HIGH DIELECTRIC CONSTANT TRANSISTOR WITH REVERSE-T GATE - A transistor is provided. The transistor includes a silicon layer including a source region and a drain region. A gate stack is disposed on the silicon layer between the source region and the drain region. The gate stack comprises a first layer of a high dielectric constant material, a second layer comprising a metal or metal alloy, and a third layer comprising silicon or polysilicon. A lateral extent of the second layer of the gate stack is substantially greater than a lateral extent of the third layer of the gate stack. Also provided are methods for fabricating such a transistor.12-10-2009
20120217589Semiconductor structure and method for manufacturing the same - A method for manufacturing a semiconductor structure comprises: providing a substrate (08-30-2012
20120217588Structure and Method to Enabling A Borderless Contact To Source Regions and Drain Regions Of A Complementary Metal Oxide Semiconductor (CMOS) Transistor - A semiconductor device that includes a gate structure on a channel region of a semiconductor substrate. A first source region and a first drain region are present in the semiconductor substrate on opposing sides of the gate structure. At least one spacer is present on the sidewalls of the gate structure. The at least one spacer includes a first spacer and a second spacer. The first spacer of the at least one spacer is in direct contact with the sidewall of the gate structure and is present over an entire width of the first source region and the first drain region. The second spacer of the at least one spacer extends from the first spacer of the at least one spacer and has a length that covers an entire length of a first source region and a first drain region.08-30-2012
20130069172SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device and a method for fabricating the same are provided. The semiconductor device includes a gate structure, a source region and a drain region. The gate structure is disposed on a substrate. The source and drain regions disposed at respective sides of the gate structure include a boron-doped silicon germanium (SiGeB) layer substantially without stress relaxation. The boron-doped silicon germanium (SiGeB) layer has a germanium concentration greater than 30 at % and an in-situ doping concentration of boron ranging between 2.65×1003-21-2013
20090273042METAL HIGH DIELECTRIC CONSTANT TRANSISTOR WITH REVERSE-T GATE - A transistor is provided. The transistor includes a silicon layer including a source region and a drain region. A gate stack is disposed on the silicon layer between the source region and the drain region. The gate stack comprises a first layer of a high dielectric constant material, a second layer comprising a metal or metal alloy, and a third layer comprising silicon or polysilicon. A lateral extent of the second layer of the gate stack is substantially greater than a lateral extent of the third layer of the gate stack. Also provided are methods for fabricating such a transistor.11-05-2009
20090273041TRANSISTOR WITH HIGH-K DIELECTRIC SIDEWALL SPACER - A transistor is provided that includes a silicon layer including a source region and a drain region, a gate stack disposed on the silicon layer between the source region and the drain region, and a sidewall spacer disposed on sidewalls of the gate stack. The gate stack includes a first layer of high dielectric constant material, a second layer comprising a metal or metal alloy, and a third layer comprising silicon or polysilicon. The sidewall spacer includes a high dielectric constant material and covers the sidewalls of at least the second and third layers of the gate stack. Also provided is a method for fabricating such a transistor.11-05-2009
20090256212LATERAL DRAIN-EXTENDED MOSFET HAVING CHANNEL ALONG SIDEWALL OF DRAIN EXTENSION DIELECTRIC - An integrated circuit (10-15-2009
20130161763SOURCE-DRAIN EXTENSION FORMATION IN REPLACEMENT METAL GATE TRANSISTOR DEVICE - A method includes forming on a surface of a semiconductor a dummy gate structure comprised of a plug; forming a first spacer surrounding the plug, the first spacer being a sacrificial spacer; and performing an angled ion implant so as to implant a dopant species into the surface of the semiconductor adjacent to an outer sidewall of the first spacer to form a source extension region and a drain extension region, where the implanted dopant species extends under the outer sidewall of the first spacer by an amount that is a function of the angle of the ion implant. The method further includes performing a laser anneal to activate the source extension and the drain extension implant. The method further includes forming a second spacer surrounding the first spacer, removing the first spacer and the plug to form an opening, and depositing a gate stack in the opening.06-27-2013
20090146223PROCESS AND METHOD TO LOWER CONTACT RESISTANCE - A method removes the spacers from the sides of a transistor gate stack, and after the spacers are removed, the method implants an additional impurity into surface regions of the substrate not protected by the gate conductor (or alternatively just amorphizes these surface regions, without adding more impurity). The method then performs a laser anneal on the additional impurity (to activate the additional impurity) or amorphized regions (to recrystallize the amorphized regions). After this, permanent spacers are formed on the sidewalls of the gate conductor. Then, the surface regions of the substrate not protected by the gate conductor and the permanent spacers are silicided, to create silicide source/drain regions. This forms the silicide regions in the additional impurity or in the recrystallized amorphized regions to reduce the source/drain resistance by improving the active dopant concentration at the silicon-silicide interface.06-11-2009
20090057785METHOD OF FABRICATING EXTENDED DRAIN MOS TRANSISTOR - A method of fabricating an extended drain MOS transistor which reduces a design rule and prevents the generation of leakage current. The method includes sequentially forming a diffusion film, a first conductive epitaxial layer, a gate oxide layer and a hard mask layer over a semiconductor substrate, forming a first hard mask pattern having a first thickness by performing a first etching process on the hard mask layer, forming a second hard mask pattern having a second thickness by performing a second etching process on the first hard mask layer, and then forming a thin gate oxide layer by performing a third etching process on the gate oxide layer using the second hard mask pattern as a mask.03-05-2009
20100244154SEMICONDUCTOR DEVICE INCLUDING MISFET - A semiconductor device includes a semiconductor substrate, a gate insulating film, a gate electrode, a source/drain layer, and a germanide layer. The gate insulating film is formed on the semiconductor substrate. The gate electrode is formed on the gate insulating film. The source/drain layer is formed on both sides of the gate electrode, contains silicon germanium, and has a germanium layer in a surface layer portion. The germanide layer is formed on the germanium layer of the source/drain layer.09-30-2010
20100171186SYSTEM AND METHOD FOR METAL-OXIDE-SEMICONDUCTOR FIELD EFFECT TRANSISTOR - System and method for metal-oxide-semiconductor field effect transistor. In a specific embodiment, the invention provides a field effect transistor (FET), which includes a substrate material, the substrate material being characterized by a first conductivity type, the substrate material including a first portion, a second portion, and a third portion, the third portion being positioned between the first portion and the second portion. The FET also includes a source portion positioned within the first portion, the source portion being characterized by a second conductivity type, the second conductivity type being opposite of the first conductivity type. A first drain portion is positioned within second portion and characterized by the second conductivity type and a first doping concentration. A second drain portion is positioned within the second portion and is characterized by the second conductivity type and a second doping concentration, the second doping concentration being different from the first doping concentration.07-08-2010
20110291202DEVICE AND METHOD OF REDUCING JUNCTION LEAKAGE - A device and method for reducing junction leakage in a semiconductor junction includes forming a faceted raised structure in a source/drain region of the device. Dopants are diffused from the faceted raised structure into a substrate below the faceted raised structure to form source/drain regions. A sprinkle implantation is applied on the faceted raised structure to produce a multi-depth dopant profile in the substrate for the source/drain regions.12-01-2011
20090159988SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method for manufacturing the same are disclosed. The disclosed semiconductor device includes a semiconductor substrate having a device isolation structure for delimiting an active region, the active region being recessed and grooves being defined in channel forming areas of the active region; gates formed in and over the grooves; gate spacers formed on both sidewalls of the gates over portions of the recessed active region which are positioned on both sides of the gates; an LDD region formed in the active region under the gate spacers; junction areas formed in the active region on both sides of the gates including the gate spacers; and landing plugs formed on the junction areas.06-25-2009
20110186938SEMICONDUCTOR STRUCTURES AND METHODS OF MANUFACTURING THE SAME - A semiconductor structure has embedded stressor material for enhanced transistor performance. The method of forming the semiconductor structure includes etching an undercut in a substrate material under one or more gate structures while protecting an implant with a liner material. The method further includes removing the liner material on a side of the implant and depositing stressor material in the undercut under the one or more gate structures.08-04-2011
20100032773Semiconductor Devices and Methods for Manufacturing a Semiconductor Device - In an embodiment, a semiconductor device is provided. The semiconductor device may include a first diffusion region, a second diffusion region an active region disposed between the first diffusion region and the second diffusion region, a control region disposed above the active region, a first trench isolation disposed laterally adjacent to the first diffusion region opposite to the active region, and a second trench isolation disposed between the second diffusion region and the active region. The second trench isolation may have a smaller depth than the first trench isolation.02-11-2010
20100032774LOW COST HIGH VOLTAGE POWER FET AND FABRICATION - A power field effect transistor (FET) is disclosed which is fabricated in as few as six photolithographic steps and which is capable of switching current with a high voltage drain potential (e.g., up to about 50 volts). In a described n-channel metal oxide semiconductor (NMOS) embodiment, a drain node includes an n-well region with a shallow junction gradient, such that the depletion region between the n-well and the substrate is wider than 1 micron. Extra photolithographic steps are avoided using blanket ion implantation for threshold adjust and lightly doped drain (LDD) implants. A modified embodiment provides an extension of the LDD region partially under the gate for a longer operating life.02-11-2010
20090152648Semiconductor Device and Method of Fabricating the Same - Disclosed are a semiconductor device and a method of fabricating the same. The semiconductor device includes a gate electrode that includes a body part disposed on the semiconductor substrate and a projecting part projecting downward from the body part; and source/drain regions at opposite sides of the gate electrode.06-18-2009
20090152646Structure and method for manufacturing device with planar halo profile - A semiconductor device and method for manufacturing the device with a planar halo profile is provided. The semiconductor device can be a MOSFET. The method of forming the structure includes forming an angled spacer adjacent a gate structure and implanting a halo implant at an angle to form a halo profile having low dopant concentration near a gate dielectric under the gate structure. The structure includes an underlying wafer or substrate and an angled gate spacer having an upper portion and an angled lower portion. The upper portion is structured to prevent halo dopants from penetrating an inversion layer of the structure. The structure further includes a low concentration halo dopant within a channel of a gate structure.06-18-2009
20080237745SRAM CELL WITH ASYMMETRICAL TRANSISTORS FOR REDUCED LEAKAGE - A method of fabricating an SRAM cell with reduced leakage is disclosed. The method comprises fabricating asymmetrical transistors in the SRAM cell. The transistors are asymmetrical in a manner that reduces the drain leakage current of the transistors. The fabrication of asymmetrical pass transistors comprises forming a dielectric region on a surface of a substrate having a first conductivity type. A gate region having a length and a width is formed on the dielectric region. Source and drain extension regions having a second conductivity type are formed in the substrate on opposite sides of the gate region. A first pocket impurity region having a first concentration and the first conductivity type is formed adjacent the source. A second pocket impurity region having a second concentration and the first conductivity type may be formed adjacent the drain. If formed, the second concentration is smaller than the first concentration, reducing the gate induced drain leakage current.10-02-2008
20100038727Carbon-Doped Epitaxial SiGe - A method for forming carbon-doped epitaxial SiGe of a PMOS transistor by providing a semiconductor substrate having a PMOS transistor gate stack and recess etched active regions. The method includes forming carbon-doped epitaxial SiGe within the recess etched active regions. A PMOS transistor includes a semiconductor substrate, a PMOS transistor gate stack, and source/drain extensions. The PMOS transistor also includes carbon-doped epitaxial SiGe source/drain regions.02-18-2010
20090045470SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - Provided is a technology capable of suppressing a reduction in electron mobility in a channel region formed in a strained silicon layer. A p type strained silicon layer is formed over a p type silicon-germanium layer formed over a semiconductor substrate. The p type strained layer has a thickness adjusted to be thicker than the critical film thickness at which no misfit dislocation occurs. Accordingly, misfit dislocations occur in the vicinity of the interface between the p type strained silicon layer and p type silicon-germanium layer. At a position which is below the end of a gate electrode and at which misfit dislocations occur, the impurity concentration of the n type strained silicon layer and n type silicon-germanium layer is 1×1002-19-2009
20090090982Ultra-abrupt semiconductor junction profile - The present invention discloses a method including: providing a substrate; forming recessed regions adjacent to both sides of a gate on the substrate; performing an angled co-implant of a species in two steps with two different energies and two different doses into the recessed regions; forming Silicon-Germanium in the recessed regions; forming source/drain extensions adjacent to both sides of the gate with a dopant; and performing an anneal to activate the dopant.04-09-2009
20090090980ASYMMETRIC-LDD MOS DEVICE - The present invention proposes a new asymmetric-lightly-doped drain (LDD) metal oxide semiconductor (MOS) transistor that is fully embedded in a CMOS logic. The radio frequency (RF) power performance of both conventional and asymmetric MOS transistor is measured and compared. The output power can be improved by 38% at peak power-added efficiency (PAE). The PAE is also improved by 16% at 10-dBm output power and 2.4 GHz. These significant improvements of RF power performance by this new MOS transistor make the RF-CMOS system-on-chip design a step further. Index Terms—Lightly-doped-drain (LDD), metal oxide semiconductor field effect transistor (MOSFET), metal oxide semiconductor (MOS) transistor, radio frequency (RF) power transistor.04-09-2009
20110198707SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD - A semiconductor device manufacturing method includes, forming isolation region having an aspect ratio of 1 or more in a semiconductor substrate, forming a gate insulating film, forming a silicon gate electrode and a silicon resistive element, forming side wall spacers on the gate electrode, heavily doping a first active region with phosphorus and a second active region and the resistive element with p-type impurities by ion implantation, forming salicide block at 500 ° C. or lower, depositing a metal layer covering the salicide block, and selectively forming metal silicide layers. The method may further includes, forming a thick and a thin gate insulating films, and performing implantation of ions of a first conductivity type not penetrating the thick gate insulating film and oblique implantation of ions of the opposite conductivity type penetrating also the thick gate insulating film before the formation of side wall spacers.08-18-2011
20090278209SEMICONDUCTOR DEVICE AND METHOD OF FABRICATION - A semiconductor device includes a gate electrode provided on a semiconductor region with a gate insulating film being interposed therebetween, extension diffusion layers provided in regions on both sides of the gate electrode of the semiconductor region, a first-conductivity type first impurity being diffused in the extension diffusion layers, and source and drain diffusion layers provided in regions farther outside than the respective extension diffusion layers of the semiconductor region and having junction depths deeper than the respective extension diffusion layers. At least one of the extension diffusion layers on both sides of the gate electrode contains carbon.11-12-2009
20090278210SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes: a high dielectric constant gate insulating film formed on an active region in a substrate; a gate electrode formed on the high dielectric constant gate insulating film; and an insulating sidewall formed on each side surface of the gate electrode. The high dielectric constant gate insulating film is continuously formed so as to extend from under the gate electrode to under the insulating sidewall. At least part of the high dielectric constant gate insulating film located under the insulating sidewall has a smaller thickness than a thickness of part of the high dielectric constant gate insulating film located under the gate electrode.11-12-2009
20090283843NMOS Transistor Including Extended NLDD-Drain For Improved Ruggedness - A MOS transistor includes a conductive gate insulated from a semiconductor layer by a first dielectric layer, lightly-doped source/drain regions being formed self-aligned to respective first and second edges of the conductive gate, a source region being formed self-aligned to a first spacer, a drain region being formed a first distance away from the edge of a second spacer, a source contact opening and source metallization formed above the source region, and a drain contact opening and drain metallization formed above the drain region. The lightly-doped source region remains under the first spacer while the lightly-doped drain region remains under the second spacer and extends over the first distance to the drain region. The distance between the first edge of the conductive gate to the source contact opening is the same as the distance between the second edge of the conductive gate to the drain contact opening.11-19-2009
20130099326SEMICONDUCTOR STRUCTURE - A semiconductor structure includes a substrate, a gate structure, and two silicon-containing structures. The substrate includes two recesses defined therein and two doping regions of a first dopant type. Each of the two doping regions extends along a bottom surface and at least portion of a sidewall of a corresponding one of the two recesses. The gate structure is over the substrate and between the two recesses. The two silicon-containing structures are of a second dopant type different from the first dopant type. Each of the two silicon-containing structures fills a corresponding one of the two recesses, and an upper portion of each of the two silicon-containing structures has a dopant concentration higher than that of a lower portion of each of the two silicon-containing structures.04-25-2013
20090294875Metal Oxide Semiconductor Device and Method for Manufacturing the Same - A Metal Oxide Semiconductor device includes a semiconductor substrate; a gate electrode formed on the surface of the substrate, having an offset spacer on each side; source/drain electrodes in the substrate having lightly doped regions respectively; metal silicide located on the gate electrode and the source/drain electrodes; and first impurity ions and second impurity ions in the lightly doped regions. A method for manufacturing a Metal Oxide Semiconductor device includes forming a gate electrode on a semiconductor substrate; implanting first impurity ions and second impurity ions to form lightly doped regions; depositing a dielectric layer and etching the dielectric layer to form offset spacers; implanting the first impurity ions to form the source/drain electrodes; forming metal silicide on the surfaces of the gate electrode and the source/drain regions. This invention can effectively prevent metal nickel diffusion into the lightly doped regions.12-03-2009
20090166762MONITORING PATTERN OF SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A monitoring pattern of a semiconductor device and a method for fabricating the same, capable of increasing an area utilization rate. The monitoring pattern of a semiconductor device includes a gate electrode formed on a semiconductor substrate provided with an isolation film, a spacer formed on one sidewall of the gate electrode, an LDD region formed on the surface of the semiconductor substrate, a salicide formed over the entire surface of the semiconductor substrate in a region other than the region provided by the spacer, an interlayer dielectric film formed over the entire surface of the semiconductor substrate, contacts, each passing through the interlayer dielectric film arranged on the salicide, and a metal line arranged on the interlayer dielectric film, while being connected to the contacts.07-02-2009
20080251861SEMICONDUCTOR APPARATUS AND PRODUCTION METHOD OF THE SAME - In order to provide a semiconductor apparatus and a production method of the semiconductor apparatus that achieves a small interface trap density by implantation of fluorine and that achieves both small property fluctuation and a small leak current, a semiconductor apparatus includes: a semiconductor substrate; a well layer formed on the semiconductor substrate; a channel dope layer formed on the well layer; a source/drain diffused layer provided at an upper peripheral of the channel dope layer; gate electrodes formed on the channel dope layer via a gate insulation film; a polycrystalline silicon plug which is formed between the gate electrodes and which touches the source/drain diffused layer while piercing the gate insulation film; and fluorine which is selectively implanted only in a source area of the source/drain diffused layer.10-16-2008
20090166764TRANSISTOR AND FABRICATING METHOD THEREOF - A transistor and fabricating method thereof includes sequentially forming a gate oxide layer and a poly gate over an active area of a semiconductor substrate, forming a drift region in the active area adjacent to the poly gate, and then forming a source/drain by simultaneously implanting impurity ions of various types into the drift region at a lower depth profile than that of the drift region.07-02-2009
20090166763SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - Embodiments relate to a semiconductor device having a minimized on-resistance. According to embodiments, a semiconductor device may include at least one of the following: a first conductive type well formed on and/or over a semiconductor substrate, a second conductive type body region formed within the first conductive type well a first conductive type source region formed on and/or over the surface of the body region, a first conductive type drain region formed on and/or over the surface of the first conductive type well. Further, according to embodiments, a semiconductor device may include a field insulation layer positioned between the first conductive type source region and the first conductive type drain region and a gate electrode formed on and/or over the field insulation layer. The source region may be formed at a lower position than the drain region.07-02-2009
20090166761FIELD EFFECT TRANSISTOR STRUCTURE WITH AN INSULATING LAYER AT THE JUNCTION - A method of making a FET includes forming a gate structure (07-02-2009
20080283938Semiconductor device and method for manufacturing the same - Provided are a semiconductor device and a method for manufacturing the same. The semiconductor device may include a substrate having a plurality of isolation areas formed therein, the isolation areas defining an active region, a gate electrode formed on the active region, spacers formed on sides of the gate electrode, a source region formed in the substrate at a side of the spacer formed at a first side of the gate electrode, a drain region formed in the substrate at a side of the spacer formed on a second side of the gate electrode, and lightly doped drain regions formed in the substrate below the spacer.11-20-2008
20080283937Semiconductor Device and Method for Fabricating the Same - Provided are a semiconductor device and a method for fabricating the same. The semiconductor device can include a transistor structure, including a gate dielectric on a substrate, a gate electrode on the gate dielectric, a spacer at sidewalls of the gate electrode, and source/drain regions in the substrate; and an interlayer dielectric on the transistor structure where an air gap is provided in a region between the spacer, the interlayer dielectric, and the source/drain region of the substrate.11-20-2008
20080290426DMOS DEVICE WITH SEALED CHANNEL PROCESSING - A method of fabricating an electronic device and a resulting electronic device. The method includes forming a pad oxide layer on a substrate, forming a silicon nitride layer over the pad oxide layer, and forming a top oxide layer over the silicon nitride layer. A first dopant region is then formed in a first portion of the substrate. A first portion of the top oxide layer is removed; a remaining portion of the top oxide layer is used to align a second dopant mask and a second dopant region is formed. An annealing step drives-in the dopants but oxygen diffusion to the substrate is limited by the silicon nitride layer; the silicon nitride layer thereby assures that the uppermost surface of the silicon is substantially planar in an area proximate to the dopant regions after the annealing step.11-27-2008
20080303103SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME - The present invention provides a semiconductor structure and a method of forming the same. The method includes the steps of providing a substrate, forming a mask layer with an opening on the substrate, locally oxidizing the substrate to form an oxide layer within the opening, removing the oxide layer, such that a partial surface of the substrate becomes a curve surface, forming a sacrificial layer on the curve surface, forming a first doped region in the substrate and under the hard mask layer, forming a gate stack within the opening, removing the hard mask layer, forming a spacer on a sidewall of the gate stack, and forming a second doped region in the substrate and under the spacer. The second doped region has a dopant concentration is larger than that of the first doped region. Therefore, the oxide layer increases the surface area of the substrate so as to increase the channel length. Thus, the leakage between the source region and the drain region can be improved.12-11-2008
20100127338SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device may include a semiconductor substrate, a salicide, a gate electrode, and an insulating layer. The semiconductor substrate has a lightly doped drain (LDD) region formed therein. The salicide is formed on the LDD region. The gate electrode is formed on the semiconductor substrate. The gate electrode has a stacked structure of a gate oxide and a metal layer. The insulating layer is formed on the semiconductor substrate and at a side of the gate electrode.05-27-2010
20130119483SILICIDE CONTACTS HAVING DIFFERENT SHAPES ON REGIONS OF A SEMICONDUCTOR DEVICE - A structure and method for fabricating silicide contacts for semiconductor devices is provided. Specifically, the structure and method involves utilizing chemical vapor deposition (CVD) and annealing to form silicide contacts of different shapes, selectively on regions of a semiconductor field effect transistor (FET), such as on source and drain regions. The shape of silicide contacts is a critical factor that can be manipulated to reduce contact resistance. Thus, the structure and method provide silicide contacts of different shapes with low contact resistance, wherein the silicide contacts also mitigate leakage current to enhance the utility and performance of FETs in low power applications.05-16-2013
20090090979HIGH PERFORMANCE MOSFET - A semiconductor structure which exhibits high device performance and improved short channel effects is provided. In particular, the present invention provides a metal oxide semiconductor field effect transistor (MOFET) that includes a low dopant concentration within an inversion layer of the structure; the inversion layer is an epitaxial semiconductor layer that is formed atop a portion of the semiconductor substrate. The inventive structure also includes a well region of a first conductivity type beneath the inversion layer, wherein the well region has a central portion and two horizontally abutting end portions. The central portion has a higher concentration of a first conductivity type dopant than the two horizontally abutting end portions. Such a well region may be referred to as a non-uniform super-steep retrograde well.04-09-2009
20110266636METHOD FOR FORMING AN OFFSET SPACER OF A MOS DEVICE - A method for forming an offset spacer of a MOS device is disclosed. The method includes the steps of: providing a substrate having a gate structure thereon; forming a dielectric stack on the substrate and the gate structure, wherein the dielectric stack comprises a first dielectric layer, a second dielectric layer, a third dielectric layer, and a fourth dielectric layer; and performing an etching process on the dielectric stack to form an offset spacer around the gate structure.11-03-2011
20100200935SEMICONDUCTOR DEVICE COMPRISING GATE ELECTRODE HAVING ARSENIC AND PHOSPHORUS - A semiconductor device is disclosed, which comprises a gate electrode having a laminated structure of a polycrystalline silicon film or a polycrystalline germanium film containing arsenic and a first nickel silicide layer formed in sequence on an element forming region of a semiconductor substrate through a gate insulating film, a sidewall insulating film formed on a side surface of the gate electrode, source/drain layers containing arsenic formed in the element forming region at both side portions of the gate electrode, and second nickel silicide layers formed on the source/drain layers, wherein a peak concentration of arsenic contained in the gate electrode is at least 1/10 of a peak concentration of arsenic contained in the source/drain layers.08-12-2010
20090321851SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device 12-31-2009
20110140204TRANSISTORS WITH AN EXTENSION REGION HAVING STRIPS OF DIFFERING CONDUCTIVITY TYPE AND METHODS OF FORMING THE SAME - Methods of forming transistors and transistors are disclosed, such as a transistor having a gate dielectric over a semiconductor having a first conductivity type, a control gate over the gate dielectric, source and drain regions having a second conductivity type in the semiconductor having the first conductivity type, and strips having the second conductivity type within the semiconductor having the first conductivity type and interposed between the control gate and at least one of the source and drain regions.06-16-2011
20080290425Method for Fabricating a Semiconductor Element, and Semiconductor Element - In a method for fabricating a semiconductor element in a substrate, first implantation ions are implanted into the substrate, whereby micro-cavities are produced in a first partial region of the substrate. Furthermore, pre-amorphization ions are implanted into the substrate, whereby a second partial region of the substrate is at least partly amorphized, and whereby crystal defects are produced in the substrate. Furthermore, second implantation ions are implanted into the second partial region of the substrate. Furthermore, the substrate is heated, such that at least some of the crystal defects are eliminated using the second implantation ions. Furthermore, dopant atoms are implanted into the second partial region of the substrate, wherein the semiconductor element is formed using the dopant atoms.11-27-2008
20090212375SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In a well region, an irregular structure is formed in a gate width direction, and a gate electrode is formed in concave portions and on top surfaces of convex portions via an insulating film. Upper and lower source regions are formed on one side of the gate electrode in a gate length direction, and upper and lower drain regions are formed on the other side thereof. By thus forming the lower source and drain regions in the source and drain regions, current concentration occurring in an upper portion of a channel region, which is generated as the gate length becomes shorter, may be suppressed and a current may be allowed to flow uniformly in the entire channel region, and hence an effective gate width is made wider owing to the irregular structure formed in the well region. Accordingly, an on-resistance of a semiconductor device is reduced to enhance driving performance.08-27-2009
20090236674MOS Transistor and Manufacturing Method Thereof - Disclosed are a MOS transistor having a low resistance ohmic contact characteristic and a manufacturing method thereof capable of improving a drive current of the MOS transistor. A gate oxide layer, a gate electrode, and a spacer are formed on a silicon substrate, and a silicon carbide layer is deposited thereon. A photolithography process is performed, and the silicon carbide layer is etched except for predetermined portions corresponding to source-drain regions and the gate electrode. Then, a metal layer is formed on the resulting structure after performing a source-drain ion implantation process. The metal layer is heated to form a salicide layer on the gate electrode and the source-drain diffusion regions. Then, the unreacted metal layer is removed, thereby forming the MOS transistor.09-24-2009
20090250772FIELD EFFECT TRANSISTOR AND METHOD OF MANUFACTURE - A semiconductor structure and method of manufacture and, more particularly, a field effect transistor that has a body contact and method of manufacturing the same is provided. The structure includes a device having a raised source region of a first conductivity type and an active region below the raised source region extending to a body of the device. The active region has a second conductivity type different than the first conductivity type. A contact region is in electric contact with the active region. The method includes forming a raised source region over an active region of a device and forming a contact region of a same conductivity type as the active region, wherein the active region forms a contact body between the contact region and a body of the device.10-08-2009
20090140352METHOD OF FORMING INTERLAYER DIELECTRIC FOR SEMICONDUCTOR DEVICE - A method of forming an interlayer dielectric for a semiconductor device minimizing voids. During a process for forming a PMD oxide film being used as an interlayer dielectric, since TEOS impurities are added under a low-pressure controlled atmosphere, and gap filling characteristics are improved. Therefore, voids are minimized in the PMD oxide film. As a result, contact holes are prevented from shorting with each other through a void, and thus current leakage is suppressed. Further, it is not necessary to perform a rapid thermal anneal to improve the density of the PMD oxide film, nor to deposit a second PMD oxide film after planarization. As a result, the manufacturing process can be simplified.06-04-2009
20120032277SEMICONDUCTOR DEVICE - A semiconductor device includes a MOS transistor. The MOS transistor includes a pair of first, second, and third impurity diffusion regions. The second impurity diffusion regions have a first conductive type and are provided in a semiconductor substrate in opposite sides of the first impurity diffusion region. The impurities concentration of the first conductive type in the second impurity diffusion regions is higher than the impurities concentration of the first conductive type in the first impurity diffusion regions. The third impurity diffusion regions have a second conductive type and are provided in the semiconductor substrate such that it contacts not the second impurity diffusion regions, but the first impurity diffusion regions.02-09-2012
20100001352Semiconductor device and method of manufacturing the same - A semiconductor device includes a MOSFET having: a gate electrode provided over a silicon substrate; and a first impurity diffusion region and a second impurity diffusion region provided in the silicon substrate in different sides of said first gate electrode, wherein the MOSFET has an extension region in an upper section of the first impurity diffusion region and no extension region in an upper section of the second impurity diffusion region, and has a first silicide layer over the first impurity diffusion region and has no silicide layer over the second impurity diffusion region in vicinity of a side edge of the gate electrode.01-07-2010
20100237440SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a gate insulating film formed on a semiconductor region of a first conductivity type, a gate electrode formed on the gate insulating film and including a polysilicon film of a second conductivity type and a first silicon mixed crystal layer formed on the polysilicon film, a first silicide layer formed on the first silicon mixed crystal layer, impurity diffused regions of the second conductivity type formed in the semiconductor region laterally outside the gate electrode, second silicon mixed crystal layers containing carbon formed in upper regions of the impurity diffused regions, and second silicide layers formed on the second silicon mixed crystal layers.09-23-2010
20100244152Configuration and fabrication of semiconductor structure having extended-drain field-effect transistor - An extended-drain insulated-gate field-effect transistor (104 or 106) contains first and second source/drain zones 324 and 184B or 364 and 186B) laterally separated by a channel (322 or 362) zone constituted by part of a first well region (184A or 186A). A gate dielectric layer (344 or 384) overlies the channel zone. A gate electrode (346 or 386) overlies the gate dielectric layer above the channel zone. The first source/drain zone is normally the source. The second S/D zone, normally the drain, is constituted with a second well region (184B or 186B). A well-separating portion 186A or 186B/212U) of the semiconductor body extends between the well regions and is more lightly doped than each well region. The configuration of the well regions cause the maximum electric field in the IGFET's portion of the semiconductor body to occur well below the upper semiconductor surface, typically at or close to where the well regions are closest to each other. The IGFET's operating characteristics are stable with operational time.09-30-2010
20100244153METHOD OF FABRICATING SPACERS IN A STRAINED SEMICONDUCTOR DEVICE - The present disclosure provides a method for fabricating a semiconductor device that includes forming a gate stack over a silicon substrate, forming dummy spacers on sidewalls of the gate stack, isotropically etching the silicon substrate to form recess regions on either side of the gate stack, forming a semiconductor material in the recess regions, the semiconductor material being different from the silicon substrate, removing the dummy spacers, forming spacer layers having an oxide-nitride-oxide configuration over the gate stack and the semiconductor material, and etching the spacer layers to form gate spacers on the sidewalls of the gate stack.09-30-2010
20110057271Semiconductor Device with Increased Breakdown Voltage - Optimization of the implantation structure of a metal oxide silicon field effect transistor (MOSFET) device fabricated using conventional complementary metal oxide silicon (CMOS) logic foundry technology to increase the breakdown voltage. The techniques used to optimize the implantation structure involve lightly implanting the gate region, displacing the drain region from the gate region, and implanting P-well and N-well regions adjacent to one another without an isolation region in between.03-10-2011
20110057270SEMICONDUCTOR DEVICE - A semiconductor device includes, a gate insulating film, a gate electrode, a source/drain region, and a Si mixed crystal layer in the source/drain region. The Si mixed crystal layer includes a first Si mixed crystal layer that includes impurities with a first concentration, a second Si mixed crystal layer formed over the first Si mixed crystal layer and that includes the impurities with a second concentration higher than the first concentration, and a third Si mixed crystal layer formed over the second Si mixed crystal layer and that includes the impurities with a third concentration lower than the second concentration.03-10-2011
20090152647FIELD-EFFECT TRANSISTOR INCLUDING LOCALIZED HALO ION REGIONS, AND SEMICONDUCTOR MEMORY, MEMORY CARD, AND SYSTEM INCLUDING THE SAME - A field-effect transistor including localized halo ion regions that can optimize HEIP characteristics and GIDL characteristics. The field-effect transistor includes a substrate, an active region, a gate structure, and halo ion regions. The active region includes source/drain regions and a channel region formed at a partial region in the substrate. The gate structure electrically contacts the active region. The halo ion regions are locally formed adjacent to both end portions of the source/drain regions in the substrate.06-18-2009
20090072325METAL-OXIDE SEMICONDUCTOR TRANSISTOR - A metal-oxide semiconductor (MOS) transistor includes a gate structure positioned in an active area defined in a substrate, a recessed source/drain, and an asymmetric shallow trench isolation (STI) for electrically isolating the active areas. A surface of the asymmetric STI and the substrate is coplanar.03-19-2009
20110121408SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC DEVICE HAVING THE SAME - A semiconductor device, which can improve the effect of a hydrogenation treatment in case of using a GOLD structure, and a method of manufacturing thereof is provided. A gate insulating film is formed on a semiconductor layer, and a source region, a drain region, and LDD regions are formed in the semiconductor layer. A main gate is formed on the gate insulating film. A sub-gate is formed on the main gate and the gate insulating film so as to cover a part of the main gate and either the LDD regions adjacent to the source region or the drain region. An interlayer insulating film containing hydrogen is formed on the sub-gate, main gate, and gate insulating film. Subsequently, a heat treatment for hydrogenation is performed to terminate a crystal defect of the semiconductor layer with hydrogen.05-26-2011
20110001197METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A sidewall spacer film or the like is removed without damaging a device structure section. Specifically disclosed is a method for manufacturing a semiconductor device, which comprises a step of forming a first thin film composed of GeCOH or GeCH on a substrate (01-06-2011
20110042758SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes: a semiconductor substrate in which a SiGe layer having a first width in a channel direction is embedded in a channel forming region; gate insulating film formed on the channel forming region; a gate electrode formed on the gate insulating film and having a region protruding from a forming region of the SiGe layer with a second width wider than the first width; and source/drain regions having extension regions formed on the semiconductor substrate which sandwiches the channel forming region, thereby forming a field effect transistor, wherein the extension region is apart from the SiGe layer so that a depletion layer extending from a junction surface between the extension region and the semiconductor substrate does not reach the SiGe layer.02-24-2011
20110115032HIGH-K/METAL GATE TRANSISTOR WITH L-SHAPED GATE ENCAPSULATION LAYER - A transistor is provided that includes a silicon layer with a source region and a drain region, a gate stack disposed on the silicon layer between the source region and the drain region, an L shaped gate encapsulation layer disposed on sidewalls of the gate stack, and a spacer disposed above the horizontal portion of the gate encapsulation layer and adjacent to the vertical portion of the gate encapsulation layer. The gate stack has a first layer of high dielectric constant material, a second layer comprising a metal or metal alloy, and a third layer comprising silicon or polysilicon. The gate encapsulation layer has a vertical portion covering the sidewalls of the first, second, and third layers of the gate stack and a horizontal portion covering a portion of the silicon layer that is adjacent to the gate stack.05-19-2011
20100078736ASYMMETRIC TRANSISTOR DEVICES FORMED BY ASYMMETRIC SPACERS AND TILTED IMPLANTATION - An asymmetric transistor configuration is disclosed in which asymmetric extension regions and/or halo regions may be combined with an asymmetric spacer structure which may be used to further adjust the overall dopant profile of the asymmetric transistor.04-01-2010
20090261426LATERAL DIFFUSION FIELD EFFECT TRANSISTOR WITH DRAIN REGION SELF-ALIGNED TO GATE ELECTRODE - A disposable structure displaced from an edge of a gate electrode and a drain region aligned to the disposable structure is formed. Thus, the drain region is self-aligned to the edge of the gate electrode. The disposable structure may be a disposable spacer, or alternately, the disposable structure may be formed simultaneously with, and comprise the same material as, a gate electrode. After formation of the drain regions, the disposable structure is removed. The self-alignment of the drain region to the edge of the gate electrode provides a substantially constant drift distance that is independent of any overlay variation of lithographic processes.10-22-2009
20090032888SEMICONDUCTOR DEVICE - A sidewall spacer structure is formed adjacent to a gate structure whereby a material forming an outer surface of the sidewall spacer structure contains nitrogen. Subsequent to its formation the sidewall spacer structure is annealed to harden the sidewall spacer structure from a subsequent cleaning process. An epitaxial layer is formed subsequent to the cleaning process.02-05-2009
20100164020TRANSISTOR WITH AN EMBEDDED STRAIN-INDUCING MATERIAL HAVING A GRADUALLY SHAPED CONFIGURATION - In a transistor, a strain-inducing semiconductor alloy, such as silicon/germanium, silicon/carbon and the like, may be positioned very close to the channel region by providing gradually shaped cavities which may then be filled with the strain-inducing semiconductor alloy. For this purpose, two or more “disposable” spacer elements of different etch behavior may be used in order to define different lateral offsets at different depths of the corresponding cavities. Consequently, enhanced uniformity and, thus, reduced transistor variability may be accomplished, even for sophisticated semiconductor devices.07-01-2010
20100164018HIGH-VOLTAGE METAL-OXIDE-SEMICONDUCTOR DEVICE - A high-voltage MOS transistor includes a gate overlying an active area of a semiconductor substrate; a drain doping region pulled back away from an edge of the gate by a distance L; a first lightly doped region between the gate and the drain doping region; a source doping region in a first ion well; and a second lightly doped region between the gate and the source doping region.07-01-2010
20100244151Structure and fabrication of field-effect transistor having source/drain extension defined by multiple local concentration maxima - An insulated-gate field-effect transistor (09-30-2010
20100244149Structure and fabrication of like-polarity field-effect transistors having different configurations of source/drain extensions, halo pockets, and gate dielectric thicknesses - A group of high-performance like-polarity insulated-gate field-effect transistors (09-30-2010
20110073962METHOD AND APPARATUS FOR FORMING A SEMICONDUCTOR GATE - The present disclosure provides an apparatus and method for fabricating a semiconductor gate. The apparatus includes, a substrate having an active region and a dielectric region that forms an interface with the active region; a gate electrode located above a portion of the active region and a portion of the dielectric region; and a dielectric material disposed within the gate electrode, the dielectric material being disposed near the interface between the active region and the dielectric region. The method includes, providing a substrate having an active region and a dielectric region that forms an interface with the active region; forming a gate electrode over the substrate, the gate electrode having an opening near a region of the gate electrode that is above the interface; and filling the opening with a dielectric material.03-31-2011
20110241129TRANSISTOR, SEMICONDUCTOR DEVICE AND TRANSISTOR FABRICATION PROCESS - The present invention provides a transistor, a semiconductor device and a transistor fabrication process that thoroughly ameliorate electric fields in a transistor element. Namely, the transistor includes a semiconductor substrate, incline portions, a gate electrode, side walls, and a source and a drain. The semiconductor substrate includes a protrusion portion at a surface thereof. The incline portions constitute side surface portions of the protrusion portion and are inclined from the bottom to the top of the protrusion portion. The gate electrode is formed on the top of the protrusion portion, with a gate insulation film interposed therebelow. The side walls are formed on the top of the protrusion portion at two side surfaces of the gate electrode and the gate insulation film. The source and the drain each include a low density region and a high-density region.10-06-2011
20110241128MULTILAYER SIDEWALL SPACER FOR SEAM PROTECTION OF A PATTERNED STRUCTURE - A semiconducting device with a multilayer sidewall spacer and method of forming are described. In one embodiment, the method includes providing a substrate containing a patterned structure on a surface of the substrate and depositing a first spacer layer over the patterned structure at a first substrate temperature, where the first spacer layer contains a first material. The method further includes depositing a second spacer layer over the patterned substrate at a second substrate temperature that is different from the first substrate temperature, where the first and second materials contain the same chemical elements, and the depositing steps are performed in any order. The first and second spacer layers are then etched to form the multilayer sidewall spacer on the patterned structure.10-06-2011
20100187641HIGH PERFORMANCE MOSFET - A semiconductor structure which exhibits high device performance and improved short channel effects is provided. In particular, the present invention provides a metal oxide semiconductor field effect transistor (MOFET) that includes a low dopant concentration within an inversion layer of the structure; the inversion layer is an epitaxial semiconductor layer that is formed atop a portion of the semiconductor substrate. The inventive structure also includes a well region of a first conductivity type beneath the inversion layer, wherein the well region has a central portion and two horizontally abutting end portions. The central portion has a higher concentration of a first conductivity type dopant than the two horizontally abutting end portions. Such a well region may be referred to as a non-uniform super-steep retrograde well.07-29-2010
20120241872NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device in one embodiment includes a select gate switch transistor having a gate insulating film formed on a semiconductor substrate, a gate electrode formed on the gate insulating film, and first and second source/drain regions provided in the semiconductor substrate so as to face each other across the gate electrode. The first source/drain region includes a first n-type impurity layer and a second n-type impurity layer which has a higher impurity concentration and has a shallower depth than the first n-type impurity layer. The second source/drain region has a third n-type impurity layer which has a lower impurity concentration and has a shallower depth than the first n-type impurity layer and a fourth n-type impurity layer which has a higher impurity concentration and has a deeper depth than the third n-type impurity layer.09-27-2012
20090115000SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method for manufacturing the same includes forming a poly-gate including a first poly-gate portion and a second poly-gate portion on and/or over a semiconductor substrate, forming a trench having a predetermined depth in the poly-gate, implanting dopant ions into the entire surface of the semiconductor substrate and the poly-gate including the trench, forming a contact barrier layer to cover a portion of the poly-gate including the trench while exposing an upper surface of the remaining portion of the poly-gate on which a contact will be formed, and forming a contact on the exposed upper surface of the poly-gate.05-07-2009
20100065924Ultra-Shallow Junctions using Atomic-Layer Doping - A semiconductor device and a method of manufacturing are provided. A substrate has a gate stack formed thereon. Ultra-shallow junctions are formed by depositing an atomic layer of a dopant and performing an anneal to diffuse the dopant into the substrate on opposing sides of the gate stack. The substrate may be recessed prior to forming the atomic layer and the recess may be filled by an epitaxial process. The depositing, annealing, and, if used, epitaxial growth may be repeated a plurality of times to achieve the desired junctions. Source/drain regions are also provided on opposing sides of the gate stack.03-18-2010
20100237439HIGH-VOLTAGE METAL-DIELECTRIC-SEMICONDUCTOR DEVICE AND METHOD OF THE SAME - A high-voltage metal-dielectric-semiconductor transistor includes a semiconductor substrate; a trench isolation region in the semiconductor substrate surrounding an active area; a gate overlying the active area; a drain doping region of a first conductivity type in the active area; a source doping region of the first conductivity type in a first well of a second conductivity type in the active area; and a source lightly doped region of the first conductivity type between the gate and the source doping region; wherein no isolation is formed between the gate and the drain doping region.09-23-2010
20100123204Semiconductor Device and Method for Fabricating the Same - The present disclosure relates to a semiconductor device and a method of forming the semiconductor device that includes forming a gate insulating film on a semiconductor substrate, forming a polysilicon layer containing fluorine on the gate insulating film, forming a gate pattern by patterning the gate insulating film and the polysilicon layer, forming a metal layer on the semiconductor substrate including the gate pattern, and reacting the metal layer with the patterned polysilicon layer to form an FUSI dual gate having a lower Si-rich silicide layer and an upper Ni-rich silicide layer. The present method can reliably control a work function of an FUSI dual gate formed thereby, improve a device performance and an NBTI characteristic by preventing Vfb from shifting. The present invention is generally applicable to high performance devices, as well as lower power devices and memory devices.05-20-2010
20110068415Radio Frequency Device and Method for Fabricating the Same - A radio frequency (RF) device that can achieve high frequency response while maintaining high output impedance and high breakdown voltage includes a substrate, a gate, at least a dummy gate, at least a doped region, a source region and a drain region. The substrate includes a well of first type and a well of second type. The well of second type is adjacent to the well of first type.03-24-2011
20090026554SOURCE/DRAIN STRESSORS FORMED USING IN-SITU EPITAXIAL GROWTH - A method for forming a semiconductor device is provided. The method includes forming a semiconductor layer. The method further includes forming a gate structure overlying the semiconductor layer. The method further includes forming a high-k sidewall spacer adjacent to the gate structure. The method further includes forming a recess in the semiconductor layer, the recess aligned to the high-k sidewall spacer. The method further includes forming an in-situ doped epitaxial material in the recess, the epitaxial material having a natural lattice constant different from a lattice constant of the semiconductor layer to create stress in a channel region of the semiconductor device.01-29-2009
20110031561SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - The present invention provides a semiconductor device which suppresses a short circuit and a leakage current between a semiconductor film and a gate electrode generated by a break or thin thickness of a gate insulating film in an end portion of a channel region of the semiconductor film, and the manufacturing method of the semiconductor device. Plural thin film transistors which each have semiconductor film provided over a substrate continuously, conductive films provided over the semiconductor film through a gate insulating film, source and drain regions provided in the semiconductor film which are not overlapped with the conductive films, and channel regions provided in the semiconductor film existing under the conductive films and between the source and drain regions. And impurity regions provided in the semiconductor film which is not overlapped with the conductive film and provided adjacent to the source and drain regions. Further, the conductive films are provided over the channel regions and regions of the semiconductor film which are provided adjacent to the channel regions.02-10-2011
20090014814POWER SEMICONDUCTOR DEVICE HAVING IMPROVED PERFORMANCE AND METHOD - In one embodiment, a semiconductor device is formed in a body of semiconductor material. The semiconductor device includes a counter-doped drain region spaced apart from a channel region.01-15-2009
20100244150Configuration and fabrication of semiconductor structure in which source and drain extensions of field-effect transistor are defined with different dopants - An insulated-gate field-effect transistor (09-30-2010
20100244148Structure and fabrication of field-effect transistor having nitrided gate dielectric layer with tailored vertical nitrogen concentration profile - A gate dielectric layer (09-30-2010
20100244147Configuration and fabrication of semiconductor structure having asymmetric field-effect transistor with tailored pocket portions along source/drain zone - An asymmetric insulated-gate field effect transistor (09-30-2010
20090001485Semiconductor Device and Manufacturing Method Thereof - Disclosed is a semiconductor device that can be used as a high voltage transistor. The semiconductor device can include a gate electrode on a semiconductor substrate, drift regions in the substrate at opposite sides of the gate electrode, a source region in one of the drift regions and a drain region in the other of the drift regions, and a shallow trench isolation (STI) region in a portion of the drift region between the gate electrode and the drain region. The portion of the drift region below the STI region can have a doping profile in which the concentration of impurities decreases from the concentration at the lower surface of the STI region, and then increases, and then again decreases.01-01-2009
20080251862ACCUMULATION FIELD EFFECT MICROELECTRONIC DEVICE AND PROCESS FOR THE FORMATION THEREOF - A gated microelectronic device is provided that has a source with a source ohmic contact with the source characterized by a source dopant type and concentration. A drain with a drain ohmic contact with the drain characterized by a drain dopant type and concentration. An intermediate channel portion characterized by a channel portion dopant type and concentration. An insulative dielectric is in contact with the channel portion and overlaid in turn by a gate. A gate contact applies a gate voltage bias to control charge carrier accumulation and depletion in the underlying channel portion. This channel portion has a dimension normal to the gate which is fully depleted in the off-state. The dopant type is the same across the source, drain and the channel portion of the device. The device on-state current is determined by the doping and, unlike a MOSFET, is not directly proportional to device capacitance.10-16-2008
20110254105Strained Semiconductor Device with Recessed Channel - A semiconductor device having a strained channel and a method of manufacture thereof is provided. The semiconductor device has a gate electrode formed over a channel recess. A first recess and a second recess formed on opposing sides of the gate electrode are filled with a stress-inducing material. The stress-inducing material extends into an area wherein source/drain extensions overlap an edge of the gate electrode. In an embodiment, sidewalls of the channel recess and/or the first and second recesses may be along {111} facet planes.10-20-2011
20100320546SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a MOS transistor, a source electrode and a drain electrode on the MOS transistor each include a first carbon doped silicon layer including carbon at a first carbon concentration and phosphorus at a first phosphorus concentration and a second carbon doped silicon layer over the first silicon carbide layer, which includes phosphorus at a second phosphorus concentration higher than the first phosphorus concentration, and which includes carbon at a second carbon concentration less than or equal to the first carbon concentration.12-23-2010
20100117163SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device according to one embodiment includes: a gate electrode formed on a semiconductor substrate via a gate insulating film; first and second spacers respectively formed on two side faces of the gate electrode; a gate sidewall formed on a side face of the first spacer; a channel region formed in the semiconductor substrate under the gate insulating film; first and second impurity diffused layers respectively formed on the first spacer side and the second spacer side of the channel region, the first impurity diffused layer including a first extension region in the gate electrode side thereon, the second impurity diffused layer including a second extension region in the gate electrode side thereon; a first silicide layer formed on the first impurity diffused layer; and a second silicide layer formed on the second impurity diffused layer, the channel region being closer to the second silicide layer than the first silicide layer.05-13-2010
20110215423SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD THEREOF - There are provided a semiconductor device which can be miniaturized without being deteriorated in characteristics, and a manufacturing method thereof. The semiconductor device includes a semiconductor substrate having a main surface, a source region and a drain region formed apart from each other in the main surface, a gate electrode layer formed over the main surface sandwiched between the source region and the drain region, a first conductive layer formed so as to be in contact with the surface of the source region, and a second conductive layer formed so as to be in contact with the surface of the drain region. A recess is formed in the main surface so as to extend from the contact region between the first conductive layer and the source region through a part underlying the gate electrode layer to the contact region between the second conductive layer and the drain region.09-08-2011
20110073961SELF-ALIGNED WELL IMPLANT FOR IMPROVING SHORT CHANNEL EFFECTS CONTROL, PARASITIC CAPACITANCE, AND JUNCTION LEAKAGE - A method of forming a self-aligned well implant for a transistor includes forming a patterned gate structure over a substrate, including a gate conductor, a gate dielectric layer and sidewall spacers, the substrate including an undoped semiconductor layer beneath the gate dielectric layer and a doped semiconductor layer beneath the undoped semiconductor layer; removing portions of the undoped semiconductor layer and the doped semiconductor layer left unprotected by the patterned gate structure, wherein a remaining portion of the undoped semiconductor layer beneath the patterned gate structure defines a transistor channel and a remaining portion of the doped semiconductor layer beneath the patterned gate structure defines the self-aligned well implant; and growing a new semiconductor layer at locations corresponding to the removed portions of the undoped semiconductor layer and the doped semiconductor layer, the new semiconductor layer corresponding to source and drain regions of the transistor.03-31-2011
20100044803SEALING STRUCTURE FOR HIGH-K METAL GATE AND METHOD OF MAKING - The present disclosure provides a semiconductor device that includes a semiconductor substrate and a transistor formed in the substrate. The transistor includes a gate stack having a high-k dielectric and metal gate, a sealing layer formed on sidewalls of the gate stack, the sealing layer having an inner edge and an outer edge, the inner edge interfacing with the sidewall of the gate stack, a spacer formed on the outer edge of the sealing layer, and a source/drain region formed on each side of the gate stack, the source/drain region including a lightly doped source/drain (LDD) region that is aligned with the outer edge of the sealing layer.02-25-2010
20120146158SEMICONDUCTOR DEVICE INCLUDING ASYMMETRIC LIGHTLY DOPED DRAIN (LDD) REGION, RELATED METHOD AND DESIGN STRUCTURE - A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate including a first source drain region, a second source drain region, and an intrinsic region therebetween; an asymmetric lightly doped drain (LDD) region within the substrate, wherein the asymmetric LDD region extends from the first source drain region into the intrinsic region between the first source drain region and the second source drain region; and a gate positioned atop the semiconductor substrate, wherein an outer edge of the gate overlaps the second source drain region. A related method and design structure are also disclosed.06-14-2012
20120038008Field Effect Transistor Device with Self-Aligned Junction and Spacer - In one aspect of the present invention, a method for fabricating a field effect transistor device includes forming a dummy gate stack on a first portion of a substrate, forming a source region and a drain region adjacent to the dummy gate stack, forming a ion doped source extension portion in the substrate, forming an ion doped drain extension portion in the substrate, forming a first spacer portion adjacent to the dummy gate stack, removing the dummy gate stack to expose a channel region of the substrate, a portion of the ion doped source extension portion, and a portion of the ion doped drain extension portion, forming a second spacer portion on the exposed portion of the ion doped source extension portion and on the exposed portion of the ion doped drain extension portion, and forming a gate stack on the exposed channel region of the substrate.02-16-2012
20120038007Field Effect Transistor Device With Self-Aligned Junction - A method for fabricating a field effect transistor device includes forming a dummy gate stack on a first portion of a substrate, forming a source region and a drain region adjacent to the dummy gate stack, forming a ion doped source extension portion in the substrate, the source extension portion extending from the source region into the first portion of the substrate, forming an ion doped drain extension portion in the substrate, the drain extension portion extending from the drain region into the first portion of the substrate, removing a portion of the dummy gate stack to expose an interfacial layer of the dummy gate stack, implanting ions in the source extension portion and the drain extension portion to form a channel region in the first portion of the substrate, removing the interfacial layer, and forming a gate stack on the channel region of the substrate.02-16-2012
20110316094SEMICONDUCTOR DEVICES WITH ASYMMETRIC HALO IMPLANTATION AND METHOD OF MANUFACTURE - a method comprises forming a hardmask over one or more gate structures. The method further comprises forming a photoresist over the hardmask. The method further comprises forming an opening in the photoresist over at least one of the gate structures. The method further comprises stripping the hardmask that is exposed in the opening and which is over the at least one of the gate structures. The method further comprises removing the photoresist. The method further comprises providing a halo implant on a side of the least one of the at least one of the gate structures.12-29-2011
20110316093SHORT CHANNEL SEMICONDUCTOR DEVICES WITH REDUCED HALO DIFFUSION - A short channel semiconductor device is formed with halo regions that are separated from the bottom of the gate electrode and from each other. Embodiments include implanting halo regions after forming source/drain regions and source/drain extension regions. An embodiment includes forming source/drain extension regions in a substrate, forming source/drain regions in the substrate, forming halo regions under the source/drain extension regions, after forming the source drain regions, and forming a gate electrode on the substrate between the source/drain regions. By forming the halo regions after the high temperature processing involved informing the source/drain and source/drain extension regions, halo diffusion is minimized, thereby maintaining sufficient distance between halo regions and reducing short channel NMOS Vt roll-off.12-29-2011
20120056277SEMICONDUCTOR DEVICE INTEGRATED WITH CONVERTER AND PACKAGE STRUCTURE THEREOF - The present invention provides a semiconductor device including a semiconductor substrate having a first conductive type, at least one high-side transistor device and at least one low-side transistor device. The high-side transistor device includes a doped high-side base region having a second conductive type, a doped high-side source region having the first conductive type and a doped drain region having the first conductive type. The doped high-side base region is disposed within the semiconductor substrate, and the doped high-side source region and the doped drain region are disposed within the doped high-side base region. The doped high-side source region is electrically connected to the semiconductor substrate, and the semiconductor substrate is regarded as a drain of the low-side transistor device.03-08-2012
20120056276STRAINED ASYMMETRIC SOURCE/DRAIN - The present disclosure provides a semiconductor device and methods of making wherein the semiconductor device has strained asymmetric source and drain regions. A method of fabricating the semiconductor device includes providing a substrate and forming a poly gate stack on the substrate. A dopant is implanted in the substrate at an implant angle ranging from about 10° to about 25° from perpendicular to the substrate. A spacer is formed adjacent the poly gate stack on the substrate. A source region and a drain region are etched in the substrate. A strained source layer and a strained drain layer are respectively deposited into the etched source and drain regions in the substrate, such that the source region and the drain region are asymmetric with respect to the poly gate stack. The poly gate stack is removed from the substrate and a high-k metal gate is formed using a gate-last process where the poly gate stack was removed.03-08-2012
20110049644FABRICATION METHOD OF SEMICONDUCTOR DEVICE - A fabrication method of a semiconductor device includes: forming a gate insulating film and a gate electrode on an N type well; forming first source/drain regions by implanting a first element in regions of the N type well on both sides of the gate electrode, the first element being larger than silicon and exhibiting P type conductivity; forming second source/drain regions by implanting a second element in the regions of the N type well on the both sides of the gate electrode, the second element being smaller than silicon and exhibiting P type conductivity; and forming a metal silicide layer on the source/drain regions.03-03-2011
20110049643SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a method of manufacturing a semiconductor device including forming a gate structure includes a metal gate electrode on a semiconductor substrate, forming two first sidewalls of an insulating material on both side surfaces of the gate structure, introducing impurity into the semiconductor substrate using the first sidewalls as a mask, and forming two extension regions of a first conductivity type and two halo regions of a second conductivity type deeper than the extension regions in the semiconductor substrate, forming two recess regions on the semiconductor substrate by etching the semiconductor substrate using the first sidewalls as a mask, forming SiGe layers in the recess regions, forming two second sidewalls of an insulating material on side surfaces of the first sidewalls, and dry etching the mask layer.03-03-2011
20120112292INTERMIXED SILICIDE FOR REDUCTION OF EXTERNAL RESISTANCE IN INTEGRATED CIRCUIT DEVICES - A method for forming an alternate conductive path in semiconductor devices includes forming a silicided contact in a source/drain region adjacent to an extension diffusion region and removing sidewall spacers from a gate structure. A metal layer is formed over a portion of the extension diffusion region in a substrate layer to intermix metal from the metal layer with the portion of the extension region without annealing the metal layer. An unmixed portion of the metal layer is removed. The alternate conductive path is formed on the extension diffusion region with intermixed metal by thermal processing after the unmixed portion of the metal layer has been removed.05-10-2012
20090134477SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device and a method of fabricating the same include a gate electrode formed over the silicon substrate, the gate electrode including low-concentration conductive impurity regions, a high-concentration conductive impurity region formed between the low-concentration conductive impurity regions and a first silicide layer formed over the high-concentration conductive impurity region, and contact electrodes including a first contact electrode connected electrically to the gate electrode and a second contact electrode connected electrically to source/drain regions. The first contact electrode contacts the uppermost surface of the gate electrode and a sidewall of the gate electrode. The gate electrode can be easily connected to the contact electrode, the high-concentration region can be disposed only on the channel region, making it possible to maximize overall performance of the semiconductor device.05-28-2009
20110089500MULTI-GATE SEMICONDUCTOR DEVICES - A semiconductor device includes a substrate, a source region formed over the substrate, a drain region formed over the substrate, a first gate electrode over the substrate adjacent to the source region and between the source and drain regions, and a second gate electrode over the substrate adjacent to the drain region and between the source and drain regions.04-21-2011
20110089499STRUCTURE AND METHOD FOR MANUFACTURING ASYMMETRIC DEVICES - A plurality of gate structures are formed on a substrate. Each of the gate structures includes a first gate electrode and source and drain regions. The first gate electrode is removed from each of the gate structures. A first photoresist is applied to block gate structures having source regions in a source-down direction. A first halo implantation is performed in gate structures having source regions in a source-up direction at a first angle. The first photoresist is removed. A second photoresist is applied to block gate structures having source regions in a source-up direction. A second halo implantation is performed in gate structures having source regions in a source-down direction at a second angle. The second photoresist is removed. Replacement gate electrodes are formed in each of the gate structures.04-21-2011
20100289093SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device is described, which includes a substrate, a gate structure, doped regions and lightly doped regions. The substrate has a stepped upper surface, which includes a first surface, a second surface and a third surface. The second surface is lower than the first surface. The third surface connects the first surface and the second surface. The gate structure is disposed on the first surface. The doped regions are configured in the substrate at both sides of the gate structure and under the second surface. The lightly doped regions are configured in the substrate between the gate structure and the doped regions, respectively. Each lightly doped region includes a first part and a second part connecting with each other. The first part is disposed under the second surface, and the second part is disposed under the third surface.11-18-2010
20120126342FIELD EFFECT TRANSISTORS WITH LOW K SIDEWALL SPACERS AND METHODS OF FABRICATING SAME - Field effect transistors and method for forming filed effect transistors. The field effect transistors including: a gate dielectric on a channel region in a semiconductor substrate; a gate electrode on the gate dielectric; respective source/drains in the substrate on opposite sides of the channel region; sidewall spacers on opposite sides of the gate electrode proximate to the source/drains; and wherein the sidewall spacers comprise a material having a dielectric constant lower than that of silicon dioxide and capable of absorbing laser radiation.05-24-2012
20090057784Extension tailored device - The present invention discloses a semiconductor device with tailored extension structure comprising a semiconductor substrate. A gate dielectric is formed on the semiconductor substrate. A gate is formed on the gate dielectric. A first isolation layer is formed over the sidewall of the gate. Dielectric spacers are formed on the sidewall of the first isolation layer. And at least one of the p-n junctions of source and drain regions is formed under the dielectric spacers and therefore forming the fringing field induced extension region. Silicide layer is formed on the gate or the doped regions. The first dielectric layer is formed over the silicide layer, dielectric spacer and portion of semiconductor substrate. The second dielectric layer is formed over the first dielectric layer. A metal plug or interconnecting structure is formed in the first dielectric layer and second dielectric layer to electrically connect to at least one of doped regions.03-05-2009
20120168879TRANSISTOR AND METHOD FOR FORMING THE SAME - The invention discloses a semiconductor device which comprises an NMOS transistor and a PMOS transistor formed on a substrate; and grid electrodes, source cathode doped areas, drain doped areas, and side walls formed on two sides of the grid electrodes are arranged on the NMOS transistor and the PMOS transistor respectively. The device is characterized in that the side walls on the two sides of the grid electrode of the NMOS transistor possess tensile stress, and the side walls on the two sides of the grid electrode of the PMOS transistor possess compressive stress. The stress gives the side walls a greater role in adjusting the stress applied to channels and the source/drain areas, with the carrier mobility further enhanced and the performance of the device improved.07-05-2012
20120175713SEMICONDUCTOR STRUCTURES AND METHODS OF MANUFACTURING THE SAME - A semiconductor structure has embedded stressor material for enhanced transistor performance. The method of forming the semiconductor structure includes etching an undercut in a substrate material under one or more gate structures while protecting an implant with a liner material. The method further includes removing the liner material on a side of the implant and depositing stressor material in the undercut under the one or more gate structures.07-12-2012
20100270625METHOD OF FABRICATING HIGH-VOLTAGE METAL OXIDE SEMICONDUCTOR TRANSISTOR DEVICES - A process of fabricating a transistor employs a relatively thicker sacrificial nitride layer that reduces the time and cost associated with chemical-mechanical polish (CMP) processes by reducing the topography associated with the transistor. The process includes forming the gate oxide region and a field oxide region on a substrate. A polysilicon layer is formed on the gate oxide region and the field oxide region. A sacrificial nitride layer is formed on the polysilicon layer, wherein the sacrificial nitride layer has a thickness approximately equal to or greater than a thickness of the gate oxide region. A polysilicon gate is formed by selectively removing portions of the polysilicon layer and the sacrificial layer to expose a portion of the gate oxide region adjacent to the polysilicon gate. Source/drain regions are formed adjacent to the polysilicon gate using lightly-doped drain (LDD) implantation. A spacer layer is formed over the polysilicon gate and source/drain regions. Portions of the spacer layer are selectively removed, along with the sacrificial nitride layer and the gate oxide region to form sidewall spacers at each end of the polysilicon gate. A pre-metal dielectric layer is formed on the high-voltage MOS transistor, and the pre-metal dielectric layer is planarized.10-28-2010
20090090981SEMICONDUCTOR DEVICE - A semiconductor device which has a high dielectric strength and allows its on resistance to be made sufficiently small is provided. This semiconductor device comprises a first electroconducive-type semiconductor layer, and a gate electrode which is disposed on a given region of an insulation film formed on the main surface of the semiconductor layer. The semiconductor layer includes: a body region of the first electroconducive type which is formed near the main surface side; a drain region of the second electroconducive type which is formed near the main surface side; and a buried region of the second electroconducive type which is formed in a position that is not right under the body region and right under at least the drain region and is connected to the drain region.04-09-2009
20100006952FIELD EFFECT TRANSISTOR AND METHOD OF FABRICATING SAME - An FET and method of fabricating an FET. The method includes forming a gate dielectric layer on a top surface of a silicon region of a substrate and forming a gate electrode on a top surface of the gate dielectric layer; forming a source and a drain in the silicon region of and separated by a channel region under the gate electrode, the source having a source extension extending under the gate electrode and the drain having a drain extension extending under the gate electrode, the source, source extension, drain and drain extension doped a first type; and forming a source delta region contained entirely within the source and forming a drain delta region contained entirely within the drain, the delta source region and the delta drain region doped a second dopant type, the second dopant type opposite from the first dopant type.01-14-2010
20120256274Schottky Diodes Having Metal Gate Electrodes And Methods of Formation Thereof - In one embodiment, the semiconductor device includes a first doped region disposed in a first region of a substrate. A first metal electrode having a first portion of a metal layer is disposed over and contacts the first doped region. A second doped region is disposed in a second region of the substrate. A dielectric layer is disposed on the second doped region. A second metal electrode having a second portion of the metal layer is disposed over the dielectric layer. The second metal electrode is capacitively coupled to the second doped region.10-11-2012
20090020833SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A method of fabricating a semiconductor device includes forming first spacers formed of a TEOS layer and second spacers formed of a first nitride layer on sidewalls of a gate electrode formed on a semiconductor substrate, and then forming source/drain regions in the semiconductor substrate using the first and second spacers and the gate electrode as masks, and then removing the second spacers, and then depositing a second nitride layer on an entire surface of the semiconductor substrate, and then implanting ions into the second nitride layer to generate compressive stress, and then etching the second nitride layer to form barrier nitride layers on the side walls of the first spacers. Because the barrier nitride has compressive stress, it is possible to prevent the movement of mobile ions, minimize influence on charge loss and charge gain in a flash memory device, and enhance a retention characteristic.01-22-2009
20090020832Semiconductor Devices and the Manufacture Thereof - A power semiconductor device includes a semiconductor body (01-22-2009
20110121407BIDIRECTIONAL POWER SWITCH CONTROLLABLE TO BE TURNED ON AND OFF - A bidirectional power transistor formed horizontally in a semiconductor layer disposed on a heavily-doped semiconductor wafer with an interposed insulating layer, the wafer being capable of being biased to a reference voltage, the product of the average dopant concentration and of the thickness of the semiconductor layer ranging between 5·1005-26-2011
20100327375SHALLOW EXTENSION REGIONS HAVING ABRUPT EXTENSION JUNCTIONS - A method of forming a semiconductor device is provided that includes forming a gate structure atop a substrate and implanting dopants into the substrate to a depth of 10 nm or less from an upper surface of the substrate. In a following step, an anneal is performed with a peak temperature ranging from 1200° C. to 1400° C., and a hold time period ranging from 1 millisecond to 5 milliseconds.12-30-2010
20120299122HIGH-K/METAL GATE TRANSISTOR WITH L-SHAPED GATE ENCAPSULATION LAYER - A transistor is provided that includes a silicon layer with a source region and a drain region, a gate stack disposed on the silicon layer between the source region and the drain region, an L shaped gate encapsulation layer disposed on sidewalls of the gate stack, and a spacer disposed above the horizontal portion of the gate encapsulation layer and adjacent to the vertical portion of the gate encapsulation layer. The gate stack has a first layer of high dielectric constant material, a second layer comprising a metal or metal alloy, and a third layer comprising silicon or polysilicon. The gate encapsulation layer has a vertical portion covering the sidewalls of the first, second, and third layers of the gate stack and a horizontal portion covering a portion of the silicon layer that is adjacent to the gate stack.11-29-2012
20120299121Source/Drain Formation and Structure - A system and method for forming semiconductor structures is disclosed. An embodiment comprises forming a high diffusibility layer adjacent to a gate stack and forming a low diffusibility layer adjacent to the high diffusibility layer. After these two layers are formed, an anneal is performed to diffuse dopants from the high diffusibility layer underneath the gate stack to help form a channel region.11-29-2012
20110037130METHOD AND STRUCTURE FOR SELF ALIGNED CONTACT FOR INTEGRATED CIRCUITS - A high voltage integrated circuit device includes a semiconductor substrate having a surface region with a contact region, which is coupled to a source/drain region. The device has a plasma enhanced oxide overlying the surface region, a stop layer overlying the plasma enhanced oxide, and a contact opening through a portion of the stop layer and through a portion of the plasma enhanced oxide layer. The contact opening exposes a portion of the contact region without damaging it. The device has a silicide layer overlying the contact region to form a silicided contact region and an interlayer dielectric overlying the silicided contact region to fill the contact opening and provide a thickness of material overlying the stop layer. An opening in the interlayer dielectric layer is formed through a portion of the thickness to expose a portion of the silicided contact region and expose a portion of the stop layer.02-17-2011
20120319213Semiconductor structure and method for manufacturing the same - The present invention provides a method for manufacturing a semiconductor structure, comprising: forming a first contact layer on an exposed active region of a first spacer; forming a second spacer at a region of the first contact layer close to a gate stack to partially cover the exposed active region; forming a second contact layer in the uncovered exposed active region, wherein when a diffusion coefficient of the first contact layer is the same as that of the second contact layer, the first contact layer has a thickness less than that of the second contact layer; and when the diffusion coefficient of the first contact layer is different from that of the second contact layer, the diffusion coefficient of the first contact layer is smaller than that of the second contact layer. Correspondingly, the present invention also provides a semiconductor structure. The present invention is beneficial to the suppression of the diffusion of corresponding compositions from the contact layers into the channel region, reduction of the short channel effects, and improvement of the reliability of the semiconductor structure.12-20-2012
20090026555Transistor with Dopant-Bearing Metal in Source and Drain - A transistor and method of manufacturing thereof. A gate dielectric and gate are formed over a workpiece, and the source and drain regions of a transistor are recessed. The recesses are filled with a dopant-bearing metal, and a low-temperature anneal process is used to form doped regions within the workpiece adjacent the dopant-bearing metal regions. A transistor having a small effective oxide thickness and a well-controlled junction depth is formed.01-29-2009
20100230765INTEGRATED CIRCUIT SYSTEM EMPLOYING STRESS MEMORIZATION TRANSFER - An integrated circuit system that includes: a substrate including a source/drain region defined by a spacer; a gate over the substrate; a gate dielectric between the gate and the substrate; a recrystallized region within the gate and the source/drain region; and a channel exhibiting the characteristics of stress memorization.09-16-2010
20120280332PIXEL STRUCTURE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a pixel structure is provided. A patterned semiconductor layer including a lower electrode, a doped source region, a doped drain region and a channel region is formed on a substrate. A gate dielectric layer is formed on the patterned semiconductor layer. A patterned first metal layer including a gate electrode, a scan line and a common electrode is formed on the gate dielectric layer, wherein the channel region is disposed below the gate electrode. A first dielectric layer and a first passivation layer are sequentially formed on the patterned first metal layer. A patterned second metal layer including a source, a drain and a data line is formed on the first passivation layer, wherein the data line is disposed above the common electrode, and the first dielectric layer and the first passivation layer are disposed between the data line and the common electrode.11-08-2012
20090001484REDUCING TRANSISTOR JUNCTION CAPACITANCE BY RECESSING DRAIN AND SOURCE REGIONS - By recessing portions of the drain and source areas on the basis of a spacer structure, the subsequent implantation process for forming the deep drain and source regions may result in a moderately high dopant concentration extending down to the buried insulating layer of an SOI transistor. Furthermore, the spacer structure maintains a significant amount of a strained semiconductor alloy with its original thickness, thereby providing an efficient strain-inducing mechanism. By using sophisticated anneal techniques, undue lateral diffusion may be avoided, thereby allowing a reduction of the lateral width of the respective spacers and thus a reduction of the length of the transistor devices. Hence, enhanced charge carrier mobility in combination with reduced junction capacitance may be accomplished on the basis of reduced lateral dimensions.01-01-2009
20120286371Field Effect Transistor Device With Self-Aligned Junction - A field effect transistor device includes a substrate including a source region, a drain region, and a channel region disposed between the source region and the drain region, wherein the source region is connected to the channel region with a source extension portion, and the drain region is connected to the channel region with a drain extension portion, wherein the channel region includes a source transition portion including n-type and p-type ions and a drain transition portion including n-type and p-type ions, and a gate stack portion disposed on the channel region.11-15-2012
20120286370SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and method for manufacturing the same are disclosed. The method comprises: forming a gate insulating layer and a gate above a substrate; forming a spacer on both sides of the gate respectively; etching the substrate with the gate and spacers as mask to form indents; respectively forming a dummy sidewall on the side of the spacers opposite to the gate; etching substrate with the gate, spacers and dummy sidewalls as mask to form recesses which are deeper than the indents; removing the dummy sidewalls; and filling SiGe in the indents and recesses to form source/drain extent regions and source/drain regions of the semiconductor device; wherein before the step of filling SiGe, a step of heating the substrate to reflow the substrate material so as to at least change the shape of the side surface of the indent on the side close to the gate is implemented.11-15-2012
20130015535Configuration and Fabrication of Semiconductor Structure Having Asymmetric Field-effect Transistor with Tailored Pocket Portion Along Source/Drain Zone - An asymmetric insulated-gate field effect transistor (01-17-2013
20130020655SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The present invention relates to a semiconductor device and its manufacturing method. The semiconductor device comprises: a gate structure located on a substrate, Ge-containing semiconductor layers located on the opposite sides of the gate structure, a doped semiconductor layer epitaxially grown between the Ge-containing semiconductor layers, the bottom surfaces of the Ge-containing semiconductor layers located on the same horizontal plane as that of the epitaxial semiconductor layer. The epitaxial semiconductor layer is used as a channel region, and the Ge-containing semiconductor layers are used as source/drain extension regions.01-24-2013
20080246098SPLIT-CHANNEL ANTIFUSE ARRAY ARCHITECTURE - Generally, the present invention provides a variable thickness gate oxide anti-fuse transistor device that can be employed in a non-volatile, one-time-programmable (OTP) memory array application. The anti-fuse transistor can be fabricated with standard CMOS technology, and is configured as a standard transistor element having a source diffusion, gate oxide, polysilicon gate and optional drain diffusion. The variable gate oxide underneath the polysilicon gate consists of a thick gate oxide region and a thin gate oxide region, where the thin gate oxide region acts as a localized breakdown voltage zone. A conductive channel between the polysilicon gate and the channel region can be formed in the localized breakdown voltage zone during a programming operation. In a memory array application, a wordline read current applied to the polysilicon gate can be sensed through a bitline connected to the source diffusion, via the channel of the anti-fuse transistor. More specifically, the present invention provides an effective method for utilizing split channel MOS structures as an anti-fuse cell suitable for OTP memories.10-09-2008
20080237744Semiconductor Device and Manufacturing Method Thereof - Provided is a semiconductor device and manufacturing method thereof. The semiconductor device includes a gate dielectric on a semiconductor substrate; and a gate electrode on the gate dielectric. The gate dielectric has a structure in which a buffer dielectric and a dielectric layer including a high-k material are stacked. The gate dielectric can be formed so as to reduce surface roughness between the gate dielectric and the semiconductor substrate and to improve the dielectric constant of the gate dielectric.10-02-2008
20080224237SEMICONDUCTOR DEVICES - An embodiment of a semiconductor device includes a gate electrode overlying a substrate and a lightly doped epitaxial layer formed on the substrate. A high energy implant region forms a well in a source side of the lightly doped epitaxial layer. A self-aligned halo implant region is formed on a source side of the device and within the high energy well implant. An implant region on a drain side of the lightly doped epitaxial layer forms a gate overlapped LDD (GOLD). A doped region within the halo implant region forms a source. A doped region within the gate overlapped LDD (GOLD) forms a drain.09-18-2008
20130181301METHOD FOR MANUFACTURING A FIELD-EFFECT SEMICONDUCTOR DEVICE FOLLOWING A REPLACEMENT GATE PROCESS - A method of manufacturing a semiconductor device is disclosed. In one aspect, the method includes: forming a dummy gate over a substrate layer; forming first gate insulating spacers adjacent to sidewalls of the dummy gate and over the substrate layer, the first spacers having two sidewalls and two surface profiles where the sidewalls meet the substrate layer; forming a source and drain region using the surface profiles; forming second gate insulating spacers adjacent to the sidewalls of the first spacers and over the source and drain regions; removing the dummy gate and the first spacers, thereby forming a first recess; depositing a dielectric layer in the first recess along the side walls of the second spacers and over the substrate layer, thereby forming a second recess; and depositing a gate electrode in the second recess.07-18-2013
20130099327CMOS DEVICES AND METHOD FOR MANUFACTURING THE SAME - A complementary metal-oxide semiconductor (CMOS) device is disclosed. The CMOS device includes a substrate, a well region formed in the substrate, and a gate formed on the substrate. The CMOS device also includes a first region and a second region formed in the well region and arranged at two sides of the gate. Further, the CMOS device includes a first light-doped drain (LDD) region and a second LDD region formed in the well region and extending the first region and the second region, respectively, towards the gate. The CMOS device also includes a first doped layer formed in the first LDD region, and a conduction type of an ion doped in the first doped layer is opposite to a conduction type of an ion doped in the first LDD region.04-25-2013
20110266635Native Devices Having Improved Device Characteristics and Methods for Fabrication - A method for fabricating a native device is presented. The method includes forming a gate structure over a substrate starting at an outer edge of an inner marker region, where the gate structure extends in a longitudinal direction, and performing MDD implants, where each implant is performed using a different orientation with respect to the gate structure, performing pocket implants, where each implant is performed using a different orientation with respect to the gate structure, and concentrations of the pocket implants vary based upon the orientations. A transistor fabricated as a native device, is presented, which includes an inner marker region, an active outer region which surrounds the inner marker region, a gate structure coupled to the inner marker region, and first and second source/drain implants located within the active outer region and interposed between the first source/drain implant and the second source/drain implant.11-03-2011
20090050980METHOD OF FORMING A SEMICONDUCTOR DEVICE WITH SOURCE/DRAIN NITROGEN IMPLANT, AND RELATED DEVICE - A method of forming a semiconductor device with source/drain nitrogen implant, and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a substrate, implanting a dopant species into an active region adjacent to the gate stack, and reducing a diffusivity of the dopant species by implanting nitrogen into the active region.02-26-2009
20110233688NOVEL DEVICES WITH VERTICAL EXTENSIONS FOR LATERAL SCALING - A method of forming a semiconductor device is provided, in which extension regions are formed atop the substrate in a vertical orientation. In one embodiment, the method includes providing a semiconductor substrate doped with a first conductivity dopant. Raised extension regions are formed on first portions of the semiconductor substrate that are separated by a second portion of the semiconductor substrate. The raised extension regions have a first concentration of a second conductivity dopant. Raised source regions and raised drain regions are formed on the raised extension regions. The raised source regions and the raised drain regions each have a second concentration of the second conductivity dopant, wherein the second concentration is greater than the first concentration. A gate structure is formed on the second portion of the semiconductor substrate.09-29-2011
20100314694SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes: a channel region formed in a semiconductor substrate; a source region formed on one side of the channel region; a drain region formed on the other side of the channel region; a gate electrode formed on the channel region via a gate insulating film; and a stress-introducing layer that applies stress to the channel region, the semiconductor device having a stress distribution in which source region-side and drain region-side peaks are positioned between a pn junction boundary of the channel region and the source region and a pn junction boundary of the channel region and the drain region.12-16-2010
20090179280HIGH THRESHOLD NMOS SOURCE-DRAIN FORMATION WITH As, P AND C TO REDUCE DAMAGE - Pipe defects in n-type lightly doped drain (NLDD) regions and n-type source/drain (NDS) regions are associated with arsenic implants, while excess diffusion in NLDD and NSD regions is mainly due to phosphorus interstitial movement. Carbon implanatation is commonly used to reduce phosphorus diffusion in the NLDD, but contributes to gated diode leakage (GDL). In high threshold NMOS transistors GDL is commonly a dominant off-state leakage mechanism. This invention provides a method of forming an NMOS transistor in which no carbon is implanted into the NLDD, and the NSD is formed by a pre-amorphizing implant (PAI), a phosphorus implant and a carbon species implant. Use of carbon in the NDS allows a higher concentration of phosphorus, resulting in reduced series resistance and reduced pipe defects. An NMOS transistor with less than 1·1007-16-2009
20120018815Semiconductor device with reduced contact resistance and method of manufacturing thereof - A method (and semiconductor device) of fabricating a semiconductor device provides a filed effect transistor (FET) with reduced contact resistance (and series resistance) for improved device performance. An impurity is implanted in the source/drain (S/D) regions after contact silicide formation and a spike anneal process is performed that lowers the schottky barrier height (SBH) of the interface between the silicide and the lower junction region of the S/D regions. This results in lower contact resistance and reduces the thickness (and Rs) of the region at the silicide-semiconductor interface.01-26-2012
20120032278SHALLOW PN JUNCTION FORMED BY IN SITU DOPING DURING SELECTIVE GROWTH OF AN EMBEDDED SEMICONDUCTOR ALLOY BY A CYCLIC GROWTH/ETCH DEPOSITION PROCESS - A silicon/carbon alloy may be formed in drain and source regions, wherein another portion may be provided as an in situ doped material with a reduced offset with respect to the gate electrode material. For this purpose, in one illustrative embodiment, a cyclic epitaxial growth process including a plurality of growth/etch cycles may be used at low temperatures in an ultra-high vacuum ambient, thereby obtaining a substantially bottom to top fill behavior.02-09-2012
20130200470SEMICONDUCTOR STRUCTURE AND METHOD OF FABRICATING THE SAME - A semiconductor structure and a method of fabricating the same comprising the steps of providing a substrate, forming at least one fin structure on said substrate, forming a gate covering said fin structure, forming a plurality of epitaxial structures covering said fin structures, performing a gate pullback process to reduce the critical dimension (CD) of said gate and separate said gate and said epitaxial structures, forming lightly doped drains (LDD) in said fin structures, and forming a spacer on said gate and said fin structures.08-08-2013
20100078735CMOS DEVICE COMPRISING NMOS TRANSISTORS AND PMOS TRANSISTORS HAVING INCREASED STRAIN-INDUCING SOURCES AND CLOSELY SPACED METAL SILICIDE REGIONS - In a CMOS manufacturing process flow, a cap layer formed on top of a gate electrode material may be maintained throughout the entire implantation sequence for defining the drain and source regions and may be removed during an etch process in which the width of a sidewall spacer structure may be reduced so as to reduce a lateral offset of metal silicide regions and of a stressed dielectric material. Thus, overall enhanced transistor performance may be obtained while nevertheless providing a high degree of compatibility with existing CMOS process strategies.04-01-2010

Patent applications in class Including lightly doped drain portion adjacent channel (e.g., lightly doped drain, LDD device)