Class / Patent application number | Description | Number of patent applications / Date published |
257407000 | With gate electrode of controlled workfunction material (e.g., low workfunction gate material) | 58 |
20080197424 | SEMICONDUCTOR STRUCTURE INCLUDING GATE ELECTRODE HAVING LATERALLY VARIABLE WORK FUNCTION - A semiconductor structure, such as a CMOS structure, includes a gate electrode that has a laterally variable work function. The gate electrode that has the laterally variable work function may be formed using an angled ion implantation method or a sequential layering method. The gate electrode that has the laterally variable work function provides enhanced electrical performance within an undoped channel field effect transistor device. | 08-21-2008 |
20080224235 | Selectively depositing aluminium in a replacement metal gate process - A method for carrying out a replacement metal gate process comprises providing a transistor in a reactor, wherein the transistor includes a gate stack, removing at least a portion of the gate stack to expose a surface of a barrier layer, causing a temperature of the reactor be less than or equal to 150° C., introducing methylpyrrolidine:alane (MPA) proximate to the surface of the barrier layer, and carrying out a CVD process to deposit aluminum metal on the barrier layer using a bottom-up deposition mechanism. | 09-18-2008 |
20080224236 | METAL GATE ELECTRODE FOR SEMICONDUCTOR DEVICES - A gate electrode for semiconductor devices, the gate electrode comprising a mixture of a metal having a work function of about 4 eV or less and a metal nitride. | 09-18-2008 |
20080237743 | Integration Scheme for Dual Work Function Metal Gates - A method for making PMOS and NMOS transistors | 10-02-2008 |
20080277743 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a substrate having a recess in an area where a gate is to be formed, spacers formed over sidewalls of the recess, and a first gate electrode filling in the recess. The spacers include material having the first work function or insulation material. The first gate electrode includes material having a second work function, wherein the second work function is higher than that of the spacers. | 11-13-2008 |
20080315328 | DUAL POLY DEPOSITION AND THROUGH GATE OXIDE IMPLANTS - Dopants are implanted at relatively high energies into an unmasked first region of a semiconductor substrate through a thin layer of gate electrode material and a gate dielectric layer. Lower energy dopants are then implanted into the thin layer of gate electrode material. The first region is then masked off, and the process is repeated in a previously masked, but now unmasked, second region of the semiconductor substrate. A second (and usually thicker) layer of gate electrode material is then formed over the thin layer of gate electrode material. The layer of thick gate electrode material, the layer of thin gate electrode material and the layer of gate dielectric material are patterned to form one or more gate structures over the doped regions of the substrate. Source and drain regions are formed in the substrate regions adjacent to the gate structures to establish one or more MOS transistors. | 12-25-2008 |
20090001483 | Method for Forming a Nickelsilicide FUSI Gate | 01-01-2009 |
20090014813 | Metal Gates of PMOS Devices Having High Work Functions - A semiconductor structure includes a refractory metal silicide layer; a silicon-rich refractory metal silicide layer on the refractory metal silicide layer; and a metal-rich refractory metal silicide layer on the silicon-rich refractory metal silicide layer. The refractory metal silicide layer, the silicon-rich refractory metal silicide layer and the metal-rich refractory metal silicide layer include same refractory metals. The semiconductor structure forms a portion of a gate electrode of a metal-oxide-semiconductor device. | 01-15-2009 |
20090032887 | TRANSISTOR HAVING GATE ELECTRODE WITH CONTROLLED WORK FUNCTION AND MEMORY DEVICE HAVING THE SAME - A transistor includes a gate insulation layer over a substrate, a gate line comprising electrodes each having a different work function on the gate insulation layer, and a source junction and a drain junction formed inside portions of the substrate on first and second sides of the gate line. | 02-05-2009 |
20090057783 | Semiconductor device and method of fabricating metal gate of the same - Provided is a semiconductor device and a method of fabricating a metal gate in the semiconductor device. The semiconductor device includes a metal gate formed on a gate insulating film, the metal gate is formed of a mixture of a metal nitride and a metal carbide, and a work function of the metal gate is determined according to ratios of the metal nitride with respect to the metal carbide. | 03-05-2009 |
20090079014 | TRANSISTORS WITH HIGH-K DIELECTRIC SPACER LINER TO MITIGATE LATERAL OXIDE ENCROACHMENT - Embodiments of the invention generally relate to transistors with high-k dielectric spacer liner to mitigate lateral oxide encroachment. In this regard a semiconductor device is introduced having a substrate, a high-k gate dielectric layer on the substrate, a metal gate electrode on the high-k gate dielectric layer, and a high-k dielectric layer on either side of and adjacent to the metal gate electrode and high-k gate dielectric layer, extending a distance away from the metal gate electrode and high-k gate dielectric layer on the substrate. Other embodiments are also disclosed and claimed. | 03-26-2009 |
20090140351 | MOS Devices Having Elevated Source/Drain Regions - A method for forming a semiconductor device includes providing a semiconductor substrate; forming a gate dielectric over the semiconductor substrate; forming a gate electrode over the gate dielectric; forming a slim spacer on sidewalls of the gate dielectric and the gate electrode; forming a silicon carbon (SiC) region adjacent the slim spacer; forming a deep source/drain region comprising at least a portion of the silicon carbon region; blanket forming a metal layer, wherein a first interface between the metal layer and the deep source/drain is higher than a second interface between the gate dielectric and the semiconductor substrate; and annealing the semiconductor device to form a silicide region. Preferably, a horizontal spacing between an inner edge of the silicide region and a respective edge of the gate electrode is preferably less than about 150 Å. | 06-04-2009 |
20090174010 | SRAM DEVICE STRUCTURE INCLUDING SAME BAND GAP TRANSISTORS HAVING GATE STACKS WITH HIGH-K DIELECTRICS AND SAME WORK FUNCTION - An SRAM semiconductor device includes: at least a first and a second field effect transistor formed on a same substrate, each of the transistors including a gate stack, each gate stack including a semiconductor layer disposed on a metal layer, the metal layer being disposed on a high-k dielectric layer located over a chemical region, wherein the metal layer of the first gate stack and the metal layer of the second gate stack have approximately a same work function, and wherein each channel region has approximately a same band gap. | 07-09-2009 |
20090179279 | METAL GATE ELECTRODE STABILIZATION BY ALLOYING - Stabilized metal gate electrode for complementary metal-oxide-semiconductor (“CMOS”) applications and methods of making the stabilized metal gate electrodes are disclosed. Specifically, the metal gate electrodes are stabilized by alloying wherein the alloy comprises a metal selected from the group consisting of Re, Ru, Pt, Rh, Ni, Al and combinations thereof and an element selected from the group consisting of W, V, Ti, Ta and combinations thereof. | 07-16-2009 |
20090200618 | METHOD OF MAKING TRANSISTOR GATES WITH CONTROLLED WORK FUNCTION - Embodiments of the invention provide methods for making an integrated circuit comprising providing a substrate, forming a structured layer stack on the substrate comprising a dielectric layer located on the substrate and an oxide-free metallic layer located on the dielectric layer, wherein the metallic layer comprising a transition metal. The method further comprises oxidizing the metallic layer, thereby increasing a work function of the metallic layer. Moreover, a substrate for making an integrated circuit is described. | 08-13-2009 |
20090256211 | METAL GATE COMPATIBLE FLASH MEMORY GATE STACK - A first gate stack comprising two stacked gate electrodes in a first device region, a second gate stack comprising a metal gate electrode in a second device region, and a third gate stack comprising a semiconductor gate electrode in a third device region are formed by forming and removing portions of a silicon-oxide based gate dielectric layer, a first doped semiconductor layer, an interfacial dielectric layer, a high-k gate dielectric layer, a metal gate layer, and an optional semiconductor material layer in various device regions. The first gate stack may be employed to form a flash memory, and the second and third gate stacks may be employed to form a pair of p-type and n-type field effect transistors. | 10-15-2009 |
20090302399 | Using Metal/Metal Nitride Bilayers as Gate Electrodes in Self-Aligned Aggressively Scaled CMOS Devices - The present invention is directed to CMOS structures that include at least one nMOS device located on one region of a semiconductor substrate; and at least one pMOS device located on another region of the semiconductor substrate. In accordance with the present invention, the at least one nMOS device includes a gate stack comprising a gate dielectric, a low workfunction elemental metal having a workfunction of less than 4.2 eV, an in-situ metallic capping layer, and a polysilicon encapsulation layer and the at least one pMOS includes a gate stack comprising a gate dielectric, a high workfunction elemental metal having a workfunction of greater than 4.9 eV, a metallic capping layer, and a polysilicon encapsulation layer. The present invention also provides methods of fabricating such a CMOS structure. | 12-10-2009 |
20100025778 | TRANSISTOR STRUCTURE AND METHOD OF MAKING THE SAME - A transistor includes a gate structure of HfMoN. The work function of the gate structure can be modulated by doping the HfMoN with dopants including nitride, silicon or germanium. The gate structure of HfMoN of the present invention is applicable to PMOS, NMOS or CMOS transistors. | 02-04-2010 |
20100052074 | METAL GATE TRANSISTOR AND METHOD FOR FABRICATING THE SAME - A method for fabricating a transistor having metal gate is disclosed. First, a substrate is provided, in which the substrate includes a first transistor region and a second transistor region. A plurality of dummy gates is formed on the substrate, and a dielectric layer is deposited on the dummy gate. The dummy gates are removed to form a plurality of openings in the dielectric layer. A high-k dielectric layer is formed to cover the surface of the dielectric layer and the opening, and a cap layer is formed on the high-k dielectric layer thereafter. The cap layer disposed in the second transistor region is removed, and a metal layer is deposited on the cap layer of the first transistor region and the high-k dielectric layer of the second transistor region. A conductive layer is formed to fill the openings of the first transistor region and the second transistor region. | 03-04-2010 |
20100084717 | Semiconductor device - Provided is a semiconductor device in which occurrence of humps can be suppressed and variations in characteristics of the semiconductor device can be suppressed. The semiconductor device includes: an element isolation film ( | 04-08-2010 |
20120161250 | Transistor Comprising High-K Metal Gate Electrode Structures Including a Polycrystalline Semiconductor Material and Embedded Strain-Inducing Semiconductor Alloys - When forming sophisticated high-k metal gate electrode structures in an early manufacturing stage on the basis of a silicon/germanium semiconductor alloy for adjusting appropriate electronic conditions in the channel region, the efficiency of a strain-inducing embedded semiconductor alloy, such as a silicon/germanium alloy, may be enhanced by initiating a crystal growth in the silicon material of the gate electrode structure after the gate patterning process. In this manner, the negative strain of the threshold voltage adjusting silicon/germanium alloy may be reduced or compensated for. | 06-28-2012 |
20120267726 | DUAL METAL GATE CORNER - In view of the foregoing, disclosed herein are embodiments of an improved field effect transistor (FET) structure and a method of forming the structure. The FET structure embodiments each incorporate a unique gate structure. Specifically, this gate structure has a first section above a center portion of the FET channel region and second sections above the channel width edges (i.e., above the interfaces between the channel region and adjacent isolation regions). The first and second sections differ (i.e., they have different gate dielectric layers and/or different gate conductor layers) such that they have different effective work functions (i.e., a first and second effective work-function, respectively). The different effective work functions are selected to ensure that the threshold voltage at the channel width edges is elevated. | 10-25-2012 |
20120306026 | REPLACEMENT GATE ELECTRODE WITH A TUNGSTEN DIFFUSION BARRIER LAYER - A tungsten barrier portion is employed in a replacement gate structure to block diffusion of material from a metal portion to a work function material portion. The tungsten barrier portion effectively functions as a diffusion barrier layer between the metal portion and the work function material portion so that the composition of the work function material portion is unaffected by anneal and/or usage of the field effect transistor including the replacement gate structure. Thus, the threshold voltage of the field effect transistor can remain stable throughout processing steps and usage in the field. | 12-06-2012 |
20130249020 | Borderless Contacts for Semiconductor Devices - In one exemplary embodiment of the invention, a method (e.g., to fabricate a semiconductor device having a borderless contact) including: forming a first gate structure on a substrate; depositing an interlevel dielectric over the first gate structure; planarizing the interlevel dielectric to expose a top surface of the first gate structure; removing at least a portion of the first gate structure; forming a second gate structure in place of the first gate structure; forming a contact area for the borderless contact by removing a portion of the interlevel dielectric; and forming the borderless contact by filling the contact area with a metal-containing material. | 09-26-2013 |
20130285158 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Provided are a semiconductor device which enables reduction of diffusion of Si in the manufacturing process of an MIPS element and suppression of an increase in EOT, and a method of manufacturing the same. An embodiment of the present invention is a semiconductor device including a field effect transistor having a gate insulating film provided on a silicon substrate and a gate electrode provided on the gate insulating film. The gate electrode is a stack-type electrode including a conductive layer containing at least Ti, N, and O (oxygen) and a silicon layer provided on the conductive layer, and the concentration of oxygen in the conductive layer is highest in the side of the silicon layer. | 10-31-2013 |
20140070330 | METHOD OF FORMING A FIELD EFFECT TRANSISTOR HAVING A GATE STRUCTURE WITH A FIRST SECTION HAVING A FIRST EFFECTIVE WORK FUNCTION ABOVE A CENTER PORTION OF THE CHANNEL REGION AND WITH SECOND SECTIONS HAVING A SECOND EFFECTIVE WORK FUNCTION ABOVE OPPOSING SIDEWALLS OF THE CHANNEL REGION - In view of the foregoing, disclosed herein are embodiments of an improved field effect transistor (FET) structure and a method of forming the structure. The FET structure embodiments each incorporate a unique gate structure. Specifically, this gate structure has a first section above a center portion of the FET channel region and second sections above the channel width edges (i.e., above the interfaces between the channel region and adjacent isolation regions). The first and second sections differ (i.e., they have different gate dielectric layers and/or different gate conductor layers) such that they have different effective work functions (i.e., a first and second effective work-function, respectively). The different effective work functions are selected to ensure that the threshold voltage at the channel width edges is elevated. | 03-13-2014 |
20140124873 | ROBUST REPLACEMENT GATE INTEGRATION - A method including forming a dummy gate on a substrate, wherein the dummy gate includes an oxide, forming a pair of dielectric spacers on opposite sides of the dummy gate, and forming an inter-gate region above the substrate and in contact with at least one of the pair of dielectric spacers, the inter-gate region comprising a protective layer on top of a first oxide layer, wherein the protective layer comprises a material resistant to etching techniques designed to remove oxide. The method may further include removing the dummy gate to leave an opening, and forming a gate within the opening. | 05-08-2014 |
20140239416 | Semiconductor device - A semiconductor device includes a source/drain feature in a substrate. The source/drain feature has an upper portion and a lower portion, the upper portion having a lower concentration of Ge than the lower portion. A Si-containing layer over the source/drain feature includes a metal silicide layer. | 08-28-2014 |
20140264634 | FINFET FOR RF AND ANALOG INTEGRATED CIRCUITS - Methods for making a FinFET having reduced device mismatch and low-frequency noise are disclosed for RF/analog IC designs. A semiconductor fin is formed having a height between 2 and 6 times its width, atomically smooth sidewalls, and rounded active corners to minimize device variability. The fin is operable as a channel between a source and a drain. A first layer of SiO | 09-18-2014 |
20140367801 | MECHANISM FOR FORMING METAL GATE STRUCTURE - Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a semiconductor substrate with a metal gate stack formed on the semiconductor substrate, and the metal gate stack includes a metal gate electrode. The semiconductor device also includes a metal oxide layer formed over the metal gate stack and in direct contact with the metal gate electrode, and a thickness of the metal oxide layer is in a range from about 15 Å to about 40 Å. The metal oxide layer has a first portion made of an oxidized material of the metal gate electrode and has a second portion made of a material different from that of the first portion. | 12-18-2014 |
20150008537 | N-TYPE MOSFET AND METHOD FOR MANUFACTURING THE SAME - An N-type MOSFET and a method for manufacturing the same are disclosed. In one aspect, the method comprises forming source/drain regions in a semiconductor substrate. The method also includes forming an interfacial oxide layer on the semiconductor substrate. The method also includes forming a high-k gate dielectric layer on the interfacial oxide layer. The method also includes forming a first metal gate layer on the high-k gate dielectric layer. The method also includes implanting dopants into the first metal gate layer through conformal doping. The method also includes annealing a gate stack to change an effective work function of the gate stack which includes the first metal gate layer, the high-k gate dielectric, and the interfacial oxide layer. | 01-08-2015 |
20150076623 | METAL GATE TRANSISTOR AND METHOD FOR FABRICATING THE SAME - A method for fabricating metal gate transistor is disclosed. The method includes the steps of: providing a substrate having a NMOS region and a PMOS region; forming a dummy gate on each of the NMOS region and the PMOS region respectively; removing the dummy gates from each of the NMOS region and the PMOS region; forming a n-type work function layer on the NMOS region and the PMOS region; removing the n-type work function layer in the PMOS region; forming a p-type work function layer on the NMOS region and the PMOS region; and depositing a low resistance metal layer on the p-type work function layer of the NMOS region and the PMOS region. | 03-19-2015 |
20150084137 | MECHANISM FOR FORMING METAL GATE STRUCTURE - Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a metal gate stack formed over the semiconductor substrate. The semiconductor device also includes an insulating layer formed over the semiconductor substrate and surrounding the metal gate stack, wherein the metal gate stack includes a metal gate electrode. The semiconductor device further includes a metal oxide structure formed over the insulating layer and in direct contact with the insulating layer. The metal oxide structure includes an oxidized material of the metal gate electrode. | 03-26-2015 |
20150137269 | REPLACEMENT GATE MOSFET WITH A HIGH PERFORMANCE GATE ELECTRODE - In a replacement gate scheme, a continuous material layer is deposited on a bottom surface and a sidewall surface in a gate cavity. A vertical portion of the continuous material layer is removed to form a gate component of which a vertical portion does not extend to a top of the gate cavity. The gate component can be employed as a gate dielectric or a work function metal portion to form a gate structure that enhances performance of a replacement gate field effect transistor. | 05-21-2015 |
20150340462 | RECESSING AND CAPPING OF GATE STRUCTURES WITH VARYING METAL COMPOSITIONS - A approach for recessing and capping metal gate structures is disclosed. Embodiments include: forming a dummy gate electrode on a substrate; forming a hard mask over the dummy gate electrode; forming spacers on opposite sides of the dummy gate electrode and the hard mask; forming an interlayer dielectric (ILD) over the substrate adjacent the spacers; forming a first trench in the ILD down to the dummy gate electrode; removing the dummy gate electrode to form a second trench below the first trench; forming a metal gate structure in the first and second trenches; and forming a gate cap over the metal gate structure. | 11-26-2015 |
20150349080 | FinFETs with Multiple Threshold Voltages - A device includes a substrate, a semiconductor fin over the substrate, and a gate dielectric layer on a top surface and sidewalls of the semiconductor fin. A gate electrode is spaced apart from the semiconductor fin by the gate dielectric layer. The gate electrode includes a top portion over and aligned to the semiconductor fin, and a sidewall portion on a sidewall portion of the dielectric layer. The top portion of the gate electrode has a first work function, and the sidewall portion of the gate electrode has a second work function different from the first work function. | 12-03-2015 |
20150357409 | GATE CONTACT WITH VERTICAL ISOLATION FROM SOURCE-DRAIN - A method of forming a semiconductor structure includes forming a gate structure having a first conductive material above a semiconductor substrate, gate spacers on opposing sides of the first conductive material, and a first interlevel dielectric (ILD) layer surrounding the gate spacers and the first conductive material. An upper portion of the first conductive material is recessed. The gate spacers are recessed until a height of the gate spacers is less than a height of the gate structure. An isolation liner is deposited above the gate spacers and the first conductive material. A portion of the isolation liner is removed so that a top surface of the first conductive material is exposed. A second conductive material is deposited in a contact hole created above the first conductive material and the gate spacers to form a gate contact. | 12-10-2015 |
20150357427 | Integrated Circuit Device with Metal Gates Including Diffusion Barrier Layers and Fabricating Methods Thereof - An integrated circuit device with metal gates including diffusion barrier layers and fabricating methods thereof are provided. The device may include a gate insulating film, a first conductivity type work function regulating film on the gate insulating film and a metal gate pattern on the first conductivity type work function regulating film. The device may include a cobalt film between the gate insulating film and the metal gate pattern to reduce diffusion from the metal gate pattern into the gate insulating film. | 12-10-2015 |
20150372105 | SEMICONDUCTOR DEVICE HAVING METAL GATE AND MANUFACTURING METHOD THEREOF - A semiconductor device having metal gate includes a substrate, a metal gate positioned on the substrate, a high-k gate dielectric layer, and an epitaxial channel layer positioned in between the high-k gate dielectric layer and the substrate. A length of the epitaxial channel layer is larger than a length of the metal gate, and a bottom of the epitaxial channel layer and the substrate are coplanar. | 12-24-2015 |
20150380512 | METAL GATE STRUCTURE AND MANUFACTURING METHOD THEREOF - A method for manufacturing a metal gate structure includes providing a substrate having a high-K gate dielectric layer and a bottom barrier layer sequentially formed thereon, forming a work function metal layer on the substrate, and performing an anneal treatment to the work function metal layer in-situ. | 12-31-2015 |
20150380520 | SEMICONDUCTOR STRUCTURES AND METHODS FOR MULTI-LEVEL WORK FUNCTION - Semiconductor devices that each include a channel region and a gate stack are disclosed. The gate stack includes a gate insulator, a pair of spaced apart first metal gate layers, and a second metal gate layer. The gate insulator extends along the length of the channel region. The first metal gate layers have a first workfunction and extend from the gate insulator. The second metal gate layer is disposed between the first metal gate layers, has a second workfunction different from the first workfunction, and extends from the gate insulator. Methods of fabricating the gate stack are also disclosed. | 12-31-2015 |
20160035854 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating metal gate transistor is disclosed. The method includes the steps of: providing a substrate having a NMOS region and a PMOS region; forming a dummy gate on each of the NMOS region and the PMOS region respectively; removing the dummy gates from each of the NMOS region and the PMOS region; forming a n-type work function layer on the NMOS region and the PMOS region; removing the n-type work function layer in the PMOS region; forming a p-type work function layer on the NMOS region and the PMOS region; and depositing a low resistance metal layer on the p-type work function layer of the NMOS region and the PMOS region. | 02-04-2016 |
20160042954 | REPLACEMENT METAL GATE AND FABRICATION PROCESS WITH REDUCED LITHOGRAPHY STEPS - Embodiments of the present invention provide a replacement metal gate and a fabrication process with reduced lithography steps. Using selective etching techniques, a layer of fill metal is used to protect the dielectric layer in the trenches, eliminating the need for some lithography steps. This, in turn, reduces the overall cost and complexity of fabrication. Furthermore, additional protection is provided during etching, which serves to improve product yield. | 02-11-2016 |
20160043195 | SEMICONDUCTOR DEVICE HAVING SPACER WITH TAPERED PROFILE - A semiconductor device is disclosed. The semiconductor device includes a substrate, a gate structure on the substrate, and a spacer adjacent to the gate structure, in which the bottom of the spacer includes a tapered profile and the tapered profile comprises a convex curve. | 02-11-2016 |
20160079383 | SEMICONDUCTOR DEVICE HAVING MODIFIED PROFILE METAL GATE - A semiconductor device having a semiconductor substrate with a dielectric layer disposed thereon. A trench is defined in the dielectric layer. A metal gate structure is disposed in the trench. The metal gate structure includes a first layer and a second layer disposed on the first layer. The first layer extends to a first height in the trench and the second layer extends to a second height in the trench; the second height is greater than the first height. In some embodiments, the second layer is a work function metal and the first layer is a dielectric. In some embodiments, the second layer is a barrier layer. | 03-17-2016 |
20160079384 | GATE STRUCTURE INTEGRATION SCHEME FOR FIN FIELD EFFECT TRANSISTORS - In one embodiment, a semiconductor device is provided that includes a gate structure present on a channel portion of a fin structure. The gate structure includes a dielectric spacer contacting a sidewall of a gate dielectric and a gate conductor. Epitaxial source and drain regions are present on opposing sidewalls of the fin structure, wherein surfaces of the epitaxial source region and the epitaxial drain region that is in contact with the sidewalls of the fin structure are aligned with an outside surface of the dielectric spacer. In some embodiments, the dielectric spacer, the gate dielectric, and the gate conductor of the semiconductor device are formed using a single photoresist mask replacement gate sequence. | 03-17-2016 |
20160093711 | Tantalum carbide metal gate stack for mid-gap work function applications - Devices with lightly-doped semiconductor channels (e.g., FinFETs) need mid-gap (˜4.6-4.7 eV) work-function layers, preferably with low resistivity and a wide process window, in the gate stack. Tantalum carbide (TaC) has a mid-gap work function that is insensitive to thickness. TaC can be deposited with good adhesion on high-k materials or on optional metal-nitride cap layers. TaC can also serve as the fill metal, or it can be used with other fills such as tungsten (W) or aluminum (Al). The TaC may be sputtered from a TaC target, deposited by ALD or CVD using TaCl | 03-31-2016 |
20160111512 | LOWERING PARASITIC CAPACITANCE OF REPLACEMENT METAL GATE PROCESSES - The present disclosure provides a method of forming a gate structure of a semiconductor device with reduced gate-contact parasitic capacitance. In a replacement gate scheme, a high-k gate dielectric layer is deposited on a bottom surface and sidewalls of a gate cavity. A metal cap layer and a sacrificial cap layer are deposited sequentially over the high-k gate dielectric layer to form a material stack. After ion implantation in vertical portions of the sacrificial cap layer, at least part of the vertical portions of the material stack is removed. The subsequent removal of a remaining portion of the sacrificial cap layer provides a gate component structure. The vertical portions of the gate component structure do not extend to a top of the gate cavity, thereby significantly reducing gate-contact parasitic capacitance. | 04-21-2016 |
20160126331 | METAL GATE STRUCTURE AND METHOD OF FORMING THE SAME - The present invention provides a metal gate structure which is formed in a trench of a dielectric layer. The metal gate structure includes a work function metal layer and a metal layer. The work function metal layer is disposed in the trench and comprises a bottom portion and a side portion, wherein a ratio between a thickness of the bottom portion and a thickness of the side portion is between 2 and 5. The trench is filled with the metal layer. The present invention further provides a method of forming the metal gate structure. | 05-05-2016 |
20160126336 | METHOD OF IMPROVED CA/CB CONTACT AND DEVICE THEREOF - Processes for forming merged CA/CB constructs and the resulting devices are disclosed. Embodiments include providing a replacement metal gate (RMG) between first and second sidewall spacers surrounded by an insulator on a substrate, the RMG having a dielectric layer directly on the first and second sidewall spacers and having metal on the dielectric layer; providing an oxide layer over the insulator, the first and second sidewall spacers, and the RMG; forming a source/drain contact hole through the oxide layer and the insulator, adjacent to the first sidewall spacer; forming a gate contact hole through the oxide layer over the source/drain contact hole and extending to the metal of the RMG; enlarging the source/drain contact hole to the metal of the RMG; and filling the enlarged source/drain contact hole and gate contact hole with metal. | 05-05-2016 |
20160141383 | INTERLAYER DIELECTRIC LAYER WITH TWO TENSILE DIELECTRIC LAYERS - A semiconductor device is disclosed. The semiconductor device includes: a substrate; a first tensile dielectric layer on the substrate; a metal gate in the first tensile dielectric layer; a second tensile dielectric layer on the first tensile dielectric layer; and a contact plug in the first tensile dielectric layer and the second tensile dielectric layer. Preferably, the top surface of the contact plug is even with the top surface of the second tensile dielectric layer, and a carbon content of the second tensile dielectric layer is greater than the carbon content of the first tensile dielectric layer. | 05-19-2016 |
20160163814 | REPLACEMENT GATE PFET MATERIALS HAVING IMPROVED NBTI PERFORMANCE - A method of forming a transistor device includes forming an interfacial layer and a dielectric layer over a substrate; and forming a workfunction metal layer over the dielectric layer, the workfunction metal layer comprising a titanium-aluminum-carbon-oxygen (TiAlCO) layer. | 06-09-2016 |
20160172443 | METHOD AND APPARATUS TO TUNE THRESHOLD VOLTAGE OF DEVICE WITH HIGH ANGLE SOURCE/DRAIN IMPLANTS | 06-16-2016 |
20160181390 | SEMICONDUCTOR DEVICES HAVING LOW CONTACT RESISTANCE AND LOW CURRENT LEAKAGE | 06-23-2016 |
20160197159 | GATE ELECTRODE HAVING A CAPPING LAYER | 07-07-2016 |
20160380069 | SEMICONDUCTOR STRUCTURE WITH INTERFACIAL LAYER AND METHOD FOR MANUFACTURING THE SAME - A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and an interfacial layer formed over the substrate. The semiconductor structure further includes a gate structure formed over the interfacial layer. In addition, the interfacial layer is made of metal germanium oxide, metal silicon oxide, or metal germanium silicon oxide and is in direct contact with a top surface of the substrate. | 12-29-2016 |
20190148523 | FinFET Device and Fabricating Method Thereof | 05-16-2019 |
20220140096 | TRANSISTOR DEVICES AND METHODS OF FORMING TRANSISTOR DEVICES - A transistor device may be provided, including a substrate; a buffer layer arranged over the substrate; a source terminal, a drain terminal, and a gate terminal arranged over the buffer layer; a barrier layer arranged over the buffer layer; and a passivation layer arranged over the barrier layer. The gate terminal may be arranged laterally between the source terminal and the drain terminal, the barrier layer may include a recess laterally between the gate terminal and the drain terminal, a part of the gate terminal may be arranged over the passivation layer and the passivation layer may extend into the recess of the barrier layer. | 05-05-2022 |