Class / Patent application number | Description | Number of patent applications / Date published |
257378000 | Combined with bipolar transistor | 52 |
20080203494 | APPARATUS AND METHOD FOR REDUCING NOISE IN MIXED-SIGNAL CIRCUITS AND DIGITAL CIRCUITS - Apparatus and a method are provided for reducing noise in mixed-signal and digital circuits. One apparatus ( | 08-28-2008 |
20080217699 | Isolated Bipolar Transistor - An isolated bipolar transistor formed in a P-type semiconductor substrate includes an N-type submerged floor isolation region and a filled trench extending downward from the surface of the substrate to the floor isolation region. Together the floor isolation region and the filled trench form an isolated pocket of the substrate which contains the bipolar transistor. The collector of the bipolar transistor may comprise the floor isolation region. The substrate does not contain an epitaxial layer, thereby overcoming the many problems associated with fabricating the same. | 09-11-2008 |
20080237735 | Hetero-Bimos injection process for non-volatile flash memory - A hetero-BiMOS injection system comprises a MOSFET transistor formed on a substrate and a hetero-bipolar transistor formed within the substrate. The bipolar transistor can be used to inject charge carriers into a floating gate of the MOSFET transistor. This is done by operating the MOSFET transistor to form an inversion layer in its channel region and operating the bipolar transistor to drive minority charge carriers from the substrate into a floating gate of the MOSFET transistor. The substrate provides a silicon emitter and a silicon germanium containing base for the bipolar transistor. The inversion layer provides a silicon collector for the bipolar transistor. | 10-02-2008 |
20090050977 | METHOD TO REDUCE BORON PENETRATION IN A SiGe BIPOLAR DEVICE - The invention, in one aspect, provides a method of manufacturing a semiconductor device. This aspect includes forming gate electrodes in a non-bipolar transistor region of a semiconductor substrate, placing a polysilicon layer over the gate electrodes in the non-bipolar transistor region and over the semiconductor substrate within a bipolar transistor region. A protective layer is formed over the polysilicon layer. The protective layer has a weight percent of hydrogen that is less than about 9% and is selective to silicon germanium (SiGe), such that SiGe does not form on the protective layer. This aspect further includes forming emitters for bipolar transistors in the bipolar transistor region, including forming a SiGe layer under a portion of the polysilicon layer. | 02-26-2009 |
20090101988 | BIPOLAR TRANSISTORS WITH RESISTORS - Bipolar transistors in complimentary MOS (CMOS) integrated circuits (ICs) are often fabricated as parasitic components, in which emitters of bipolar transistors are implanted in the same processes as CMOS sources/drains, to avoid manufacturing costs associated with dedicated implants for bipolar emitters. Energies and doses of CMOS source/drain implants are typically selected to optimize CMOS transistor performance, resulting in less than optimum values of bipolar parameters such as gain. CMOS ICs often include implanted resistors of a same type as the emitters of the bipolar transistors in the same ICs. This invention discloses bipolar transistors with emitters implanted by CMOS source/drain implants and resistor implants to improve bipolar transistor parameters, and a method for fabricating same. | 04-23-2009 |
20090159983 | Non-Destructive Inline Epi Pattern Shift Monitor Using Selective Epi - Integrated circuits using buried layers under epitaxial layers present a challenge in aligning patterns for surface components to the buried layers, because the epitaxial material over the buried layer diminishes the visibility of and shifts the apparent position of the buried layer. A method of measuring the lateral offset, known as the epi pattern shift, between a buried layer and a pattern for a surface component using planar processing technology and commonly used semiconductor fabrication metrology tools is disclosed. The disclosed method may be used on a pilot wafer to provide optimization data for a production line running production wafers, or may be used on production wafers directly. An integrated circuit fabricated using the instant invention is also disclosed. | 06-25-2009 |
20090159984 | Semiconductor Device and Method for Manufacturing the Same - A semiconductor device and a method for manufacturing the same are provided. An n-well region can be formed on a semiconductor substrate, and a base contact region can be formed on the n-well region. An emitter contact region, a collector contact region, and a p-base region can also be formed on the n-well. The emitter and collector contact regions can include n-type ions, and the base contact region and the p-base region can include p-type ions. Thus, the semiconductor device can include an n-channel metal oxide semiconductor transistor and an NPN bipolar transistor. | 06-25-2009 |
20090166753 | Semiconductor Device and Method of Manufacturing Such a Device - The invention relates to a semiconductor device ( | 07-02-2009 |
20090230481 | SEMICONDUCTOR DEVICE FORMED USING SINGLE POLYSILICON PROCESS AND METHOD OF FABRICATING THE SAME - Provided are a semiconductor device including a source/drain and a gate formed using a doped polysilicon process, and a method of fabricating the semiconductor device. The method comprises: forming a gate insulating layer on a part of an active region on a first conductivity type epitaxial layer; forming a conductive layer on the epitaxial layer; implanting high concentration impurities of a second conductivity type a first portion of the conductive layer on the gate insulating layer and second portions of the conductive layer on both sides of the first insulating layer; patterning the conductive layer; forming a second insulating layer on the epitaxial layer and high concentration impurity regions of the second conductivity type below the second conductive pattern; and implanting low-concentration impurities of the second conductivity type into the epitaxial layer between a gate structure and the high concentration impurity regions. | 09-17-2009 |
20090236668 | METHOD TO IMPROVE WRITER LEAKAGE IN SiGe BIPOLAR DEVICE - The invention, in one aspect, provides a method for fabricating a semiconductor device, which includes conducting an etch through an opening in an emitter layer to form a cavity from an underlying oxide layer that exposes a doped tub. A first silicon/germanium (SiGe) layer, which has a Ge concentration therein, is formed within the cavity and over the doped tub by adjusting a process parameter to induce a strain in the first SiGe layer. A second SiGe layer is formed over the first SiGe layer, and a capping layer is formed over the second SiGe layer. | 09-24-2009 |
20090261421 | SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURE - In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a method includes forming a portion of the unidirectional transistor and a portion of a bidirectional transistor in or over a semiconductor material simultaneously. Other embodiments are described and claimed. | 10-22-2009 |
20090294870 | Semiconductor device with trench gate and method of manufacturing the same - A method of a semiconductor device, which includes an insulated-gate FET and an electronic element, includes three steps. The first step is the step of forming a trench gate of the insulated-gate FET in a first region of a semiconductor base and a trench element-isolation layer in a second region of the semiconductor base, simultaneously. The second step is the step of forming a first diffusion layer of the insulated-gate FET on a side of the trench gate and a second diffusion layer of the electronic element in a region surrounded by the trench element-isolation layer, simultaneously. The third step is the step of forming a third diffusion layer of the insulated-gate FET in the first diffusion layer and a fourth diffusion layer of the electronic element in the second diffusion layer, simultaneously. | 12-03-2009 |
20100032768 | TRANSISTOR OF IMAGE SENSOR AND METHOD FOR MANUFACTURING THE SAME - A transistor of an image sensor and a method for manufacturing the same include simultaneously forming a device isolation layer at a boundary between a first conductive transistor region having a second conductive well formed therein and a second conductive transistor region having a first conductive well formed therein, and a trench dielectric layer at a junction transistor region having no conductive well formed therein, and then simultaneously forming a first gate pattern at the first conductive transistor region, a second gate pattern at the second conductive transistor region and a laminated layer at the junction transistor region, and then forming a bipolar junction in the laminated layer by sequentially implanting a first conductive dopant and a second conductive dopant into the laminated layer. | 02-11-2010 |
20100032769 | IMPLANTED WELL BREAKDOWN IN HIGH VOLTAGE DEVICES - An n-type isolation structure is disclosed which includes an n-type BISO layer in combination with a shallow n-well, in an IC. The n-type BISO layer is formed by implanting n-type dopants into a p-type IC substrate in addition to a conventional n-type buried layer (NBL), prior to growth of a p-type epitaxial layer. The n-type dopants in the BISO implanted layer diffuse upward from the p-type substrate to between one-third and two-thirds of the thickness of the p-type epitaxial layer. The shallow n-type well extends from a top surface of the p-type epitaxial layer to the n-type BISO layer, forming a continuous n-type isolation structure from the top surface of the p-type epitaxial layer to the p-type substrate. The width of the n-type BISO layer may be less than the thickness of the epitaxial layer, and may be used alone or with the NBL to isolate components in the IC. | 02-11-2010 |
20100065920 | METHOD TO REDUCE COLLECTOR RESISTANCE OF A BIPOLAR TRANSISTOR AND INTEGRATION INTO A STANDARD CMOS FLOW - The invention, in one aspect, provides a method for fabricating a semiconductor device. In one aspect, the method provides for a dual implantation of a tub of a bipolar transistor. The tub in bipolar region is implanted by implanting the tub through separate implant masks that are also used to implant tubs associated with MOS fabricate different voltage devices in a non-bipolar region during the fabrication of MOS transistors. | 03-18-2010 |
20100237433 | Bipolar/Dual FET Structure Having FETs With Isolated Channels - According to an exemplary embodiment, a bipolar/dual FET structure includes a bipolar transistor situated over a substrate. The bipolar/dual FET structure further includes an enhancement-mode FET and a depletion-mode FET situated over the substrate. In the bipolar/dual FET structure, the channel of the enhancement-mode FET is situated above the base of the bipolar transistor and the channel of the depletion-mode FET is situated below the base of the bipolar transistor. The channel of the enhancement-mode FET is isolated from the channel of the depletion-mode FET so as to decouple the enhancement-mode FET from the depletion mode FET. | 09-23-2010 |
20100308416 | Method of Fabricating an Integrated Circuit with Gate Self-Protection, and an Integrated Circuit with Gate Self-Protection - An integrated circuit with gate self-protection comprises a MOS device and a bipolar device, wherein the integrated circuit further comprises a semiconductor layer with electrically active regions in which and on which the MOS device and the bipolar device are formed and electrically inactive regions for isolating the electrically active regions from each other. The MOS device comprises a gate structure and a body contacting structure, wherein the body contacting structure is formed of a base layer deposited in a selected region over an electrically active region of the semiconductor layer, and the body contacting structure is electrically connected with the gate structure. The base layer forming the body contacting structure also forms the base of the bipolar device. The present invention further relates to a method for fabricating such an integrated circuit. | 12-09-2010 |
20110001196 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a substrate of a first conductive type, a first doped region of a second conductive type, at least one second doped region of the first conductive type, a third doped region of the second conductive type, a gate structure, and at least one contact. The first and the second doped regions are configured in the substrate, and each second doped region is surrounded by the first doped region. The third doped region is configured in the substrate outside of the first doped region. The gate structure is disposed on the substrate between the first and third doped regions. The contact is disposed on the substrate. Each contact connects, in a direction parallel to the gate structure, the first and second doped regions alternately. | 01-06-2011 |
20110057266 | BIPOLAR TRANSISTOR INTEGRATED WITH METAL GATE CMOS DEVICES - A high-k gate dielectric layer and a metal gate layer are formed and patterned to expose semiconductor surfaces in a bipolar junction transistor region, while covering a CMOS region. A disposable material portion is formed on a portion of the exposed semiconductor surfaces in the bipolar junction transistor area. A semiconductor layer and a dielectric layer are deposited and patterned to form gate stacks including a semiconductor portion and a dielectric gate cap in the CMOS region and a cavity containing mesa over the disposable material portion in the bipolar junction transistor region. The disposable material portion is selectively removed and a base layer including an epitaxial portion and a polycrystalline portion fills the cavity formed by removal of the disposable material portion. The emitter formed by selective epitaxy fills the cavity in the mesa. | 03-10-2011 |
20110073955 | ISOLATION TRENCH WITH ROUNDED CORNERS FOR BiCMOS PROCESS - A semiconductor device comprising a first transistor device ( | 03-31-2011 |
20110127615 | SEMICONDUCTOR APPARATUS AND MANUFACTURING METHOD THEREOF - A high-performance semiconductor apparatus which can be easily introduced into the MOS process, reduces the leakage current (electric field strength) between the emitter and the base, and is insusceptible to noise or surge voltage, and a manufacturing method of the semiconductor apparatus. The emitter | 06-02-2011 |
20110215417 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE THEREOF - A semiconductor device ( | 09-08-2011 |
20110215418 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of the first conductivity type, a first main electrode, a third semiconductor region of a second conductivity type, a second main electrode, and a plurality of embedded semiconductor regions of the second conductivity type. The second semiconductor region is formed on a first major surface of the first semiconductor region. The first main electrode is formed on a face side opposite to the first major surface of the first semiconductor region. The third semiconductor region is formed on a second major surface of the second semiconductor region on a side opposite to the first semiconductor region. The second main electrode is formed to bond to the third semiconductor region. The embedded semiconductor regions are provided in a termination region. A distance between the embedded semiconductor region and the second major surface along a direction from the second major surface toward the first major surface becomes longer toward outside from the device region. | 09-08-2011 |
20110233684 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a first main electrode, a base layer of a first conductivity type, a barrier layer of the first conductivity type, a diffusion layer of a second conductivity type, a base layer of the second conductivity type, a first conductor layer, a second conductor layer, and a second main electrode. The base layer of the first conductivity type is provided on the first main electrode. The barrier layer of the first conductivity type and the diffusion layer of the second conductivity type are provided on the base layer of the first conductivity type. The barrier layer of the first conductivity type and the diffusion layer of the second conductivity type are arranged alternately. The base layer of the second conductivity type is provided on the barrier layer of the first conductivity type. The first conductor layer and the second conductor layer are provided between the base layer of the second conductivity type and the diffusion layer of the second conductivity type and between the barrier layer of the first conductivity type and the diffusion layer of the second conductivity type. The first conductor layer and the second conductor layer are provided with trench configurations with an interposed insulating film. The second main electrode is connected to the base layer of the second conductivity type. Bottom faces of the barrier layer of the first conductivity type and the diffusion layer of the second conductivity type are positioned on the first main electrode side of lower ends of the first conductor layer and the second conductor layer. The barrier layer of the first conductivity type and the diffusion layer of the second conductivity type form a super junction proximally to tips of the first conductor layer and the second conductor layer. | 09-29-2011 |
20110303987 | BIPOLAR FIELD EFFECT TRANSISTOR STRUCTURES AND METHODS OF FORMING THE SAME - Bipolar field effect transistor (BiFET) structures and methods of forming the same are provided. In one embodiment, an apparatus includes a substrate and a plurality of epitaxial layers disposed over the substrate. The plurality of epitaxial layers includes a first epitaxial layer, a second epitaxial layer disposed over the first epitaxial layer, and a third epitaxial layer disposed over the second epitaxial layer. The first epitaxial layer includes at least a portion of a channel of a first field effect transistor (FET) and the third epitaxial layer includes at least a portion of a channel of a second FET. | 12-15-2011 |
20120018811 | FORMING BIPOLAR TRANSISTOR THROUGH FAST EPI-GROWTH ON POLYSILICON - Provided is a semiconductor device that includes a first transistor and a second transistor that are formed on the same substrate. The first transistor includes a first collector, a first base, and a first emitter. The first collector includes a first doped well disposed in the substrate. The first base includes a first doped layer disposed above the substrate and over the first doped well. The first emitter includes a doped element disposed over a portion of the first doped layer. The second transistor includes a second collector, a second base, and a second emitter. The second collector includes a doped portion of the substrate. The second base includes a second doped well disposed in the substrate and over the doped portion of the substrate. The second emitter includes a second doped layer disposed above the substrate and over the second doped well. | 01-26-2012 |
20120032274 | Vertically Stacked FETs With Series Bipolar Junction Transistor - Vertically stacked Field Effect Transistors (FETs) are created on a vertical structure formed on a semiconductor substrate where a first FET and a second FET are controllable independently. A bipolar junction transistor is connected between and in series with the first FET and the second FET, the bipolar junction transistor may be controllable independently of the first and second FET. | 02-09-2012 |
20120074505 | 3D Integrated circuit in planar process - Techniques related to 3D integrated circuits formed on a single wafer are disclosed. According to one embodiment, an integrated circuit comprises a first device forming a first projection area on a wafer and a second device forming a second projection area on the wafer. The first projection area overlaps with the second projection area partially or completely. The area being shared between the two devices refers to the partial or complete overlapping of the projection areas of the two devices. In one embodiment, two or more devices in different layers of the integrated circuit or two or more devices at different depths in a same layer of the integrated circuit may share an area on the same wafer in a certain manner. Thereby, the area of the chip is saved and the chip cost of the integrated circuit is significantly reduced. | 03-29-2012 |
20120132999 | METHOD OF MANUFACTURING A BIPOLAR TRANSISTOR AND BIPOLAR TRANSISTOR - Consistent with an example embodiment, there is method of manufacturing a bipolar transistor comprising providing a substrate including an active region; depositing a layer stack; forming a base window over the active region in said layer stack; forming at least one pillar in the base window, wherein a part of the pillar is resistant to polishing; depositing an emitter material over the resultant structure, thereby filling said base window; and planarizing the deposited emitter material by polishing. Consistent with another example embodiment, a bipolar transistor may be manufactured according to the afore-mentioned method. | 05-31-2012 |
20120139056 | BIPOLAR TRANSISTOR INTEGRATED WITH METAL GATE CMOS DEVICES - A high-k gate dielectric layer and a metal gate layer are formed and patterned to expose semiconductor surfaces in a bipolar junction transistor region, while covering a CMOS region. A disposable material portion is formed on a portion of the exposed semiconductor surfaces in the bipolar junction transistor area. A semiconductor layer and a dielectric layer are deposited and patterned to form gate stacks including a semiconductor portion and a dielectric gate cap in the CMOS region and a cavity containing mesa over the disposable material portion in the bipolar junction transistor region. The disposable material portion is selectively removed and a base layer including an epitaxial portion and a polycrystalline portion fills the cavity formed by removal of the disposable material portion. The emitter formed by selective epitaxy fills the cavity in the mesa. | 06-07-2012 |
20120241870 | Bipolar junction transistor with surface protection and manufacturing method thereof - The present invention discloses a bipolar junction transistor (BJT) with surface protection and a manufacturing method thereof. The BJT includes: a first conductive type base, a second conductive type emitter, and a second conductive type collector, which are formed in a substrate, wherein the base is formed between and separates the emitter and the collector, and the base includes a base contact region functioning as an electrical contact node of the base; and a gate structure which is formed on the substrate between the base contact region and the second conductive type emitter. | 09-27-2012 |
20120267720 | METHOD AND APPARATUS FOR BURIED-CHANNEL SEMICONDUCTOR DEVICE - Methods and apparatus of integrating a buried-channel PMOS into a BiCMOS process. The apparatus comprises at least one bipolar transistor and at least one MOS device coupled to the at least one bipolar transistor, such that a gate of the at least one MOS device may be coupled to an emitter of the at least one bipolar transistor. The MOS device comprises a buried channel having mobility means, such as strained silicon for promoting hole mobility in the buried channel, and confinement means, such as a cap layer disposed proximate to the buried channel for limiting leakage of holes from the buried channel. The apparatus may be formed by exposing a substrate in a PMOS, forming a SiGe layer on the substrate, forming an oxide layer on the SiGe layer, masking the PMOS, and removing at least some of the oxide and at least some of the SiGe layer. | 10-25-2012 |
20130001703 | SEMICONDUCTOR DEVICE - A combined switching device includes a MOSFET disposed in a MOSFET area and IGBTs disposed in IGBT areas of a SiC substrate. The MOSFET and the IGBTs have gate electrodes respectively connected, a source electrode and emitter electrodes respectively connected, and a drain electrode and a collector electrode respectively connected. The MOSFET and the IGBTs are disposed with a common n-buffer layer. A top surface element structure of the MOSFET and top surface element structures of the IGBTs are disposed on the first principal surface side of the SiC substrate. Concave portions and convex portions are disposed on the second principal surface side of the SiC substrate. The MOSFET is disposed at a position corresponding to the convex portion of the SiC substrate. The IGBTs are disposed at positions corresponding to the concave portions of the SiC substrate. | 01-03-2013 |
20130009252 | High Voltage Bipolar Transistor with Trench Field Plate - A bipolar transistor structure includes an epitaxial layer on a semiconductor substrate, a bipolar transistor device formed in the epitaxial layer and a trench structure formed in the epitaxial layer adjacent at least two opposing lateral sides of the bipolar transistor device. The trench structure includes a field plate spaced apart from the epitaxial layer by an insulating material. The bipolar transistor structure further includes a base contact connected to a base of the bipolar transistor device, an emitter contact connected to an emitter of the bipolar transistor device and isolated from the base contact and an electrical connection between the emitter contact and the field plate. | 01-10-2013 |
20130032891 | METHOD OF MANUFACTURING AN IC COMPRISING A PLURALITY OF BIPOLAR TRANSISTORS AND IC COMPRISING A PLURALITY OF BIPOLAR TRANSISTORS - A method of manufacturing an integrated circuit comprising bipolar transistors including first and second type bipolar transistors, the method comprising providing a substrate comprising first isolation regions each separated from a second isolation region by an active region comprising a collector impurity of one of the bipolar transistors; forming a base layer stack over the substrate; forming a first emitter cap layer of a first effective thickness over the base layer stack in the areas of the first type bipolar transistor; forming a second emitter cap layer of a second effective thickness different from the first effective thickness over the base layer stack in the areas of the second type bipolar transistor; and forming an emitter over the emitter cap layer of each of the bipolar transistors. An IC in accordance with this method. | 02-07-2013 |
20130032892 | BIPOLAR TRANSISTOR IN BIPOLAR-CMOS TECHNOLOGY - A process of forming an integrated circuit containing a bipolar transistor and an MOS transistor, by forming a base layer of the bipolar transistor using a non-selective epitaxial process so that the base layer has a single crystalline region on a collector active area and a polycrystalline region on adjacent field oxide, and concurrently implanting the MOS gate layer and the polycrystalline region of the base layer, so that the base-collector junction extends into the substrate less than one-third of the depth of the field oxide, and vertically cumulative doping density of the polycrystalline region of the base layer is between 80 percent and 125 percent of a vertically cumulative doping density of the MOS gate. An integrated circuit containing a bipolar transistor and an MOS transistor formed by the described process. | 02-07-2013 |
20130075829 | ELECTROSTATIC DISCHARGE PROTECTION DEVICE - An electrostatic discharge (ESD) protection device includes a first transistor and a second transistor. The first transistor includes a first bulk electrode, a first electrode and a second electrode. The first bulk electrode and the first electrode form a first parasitic diode. The first bulk electrode and the second electrode form a second parasitic diode. The second transistor includes a second bulk electrode, a third electrode and a fourth electrode. The second bulk electrode and the third electrode form a third parasitic diode. The second bulk electrode and the fourth electrode form a fourth parasitic diode. The first bulk electrode is connected to the third electrode, and the second bulk electrode is connected to the first electrode. | 03-28-2013 |
20130093023 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a first insulated gate field effect transistor, a second insulated gate field effect transistor, a bipolar transistor, a first element isolation structure formed on a main surface above a pn junction formed between an emitter region and a base region, a second element isolation structure formed on the main surface above a pn junction formed between the base region and a collector region, and a third element isolation structure formed on the main surface opposite to the second element isolation structure relative to the collector region, in which the semiconductor device further includes a bipolar dummy electrode formed on at least one of the first element isolation structure, the second element isolation structure and the third element isolation structure and having a floating potential. | 04-18-2013 |
20130105911 | SEMICONDUCTOR DEVICE | 05-02-2013 |
20130270649 | BIPOLAR TRANSISTOR MANUFACTURING METHOD - A method for manufacturing a bipolar transistor, including the steps of: forming a first surface-doped region of a semiconductor substrate having a semiconductor layer extending thereon with an interposed first insulating layer; forming, at the surface of the device, a stack of a silicon layer and of a second insulating layer; defining a trench crossing the stack and the semiconductor layer opposite to the first doped region, and then an opening in the exposed region of the first insulating layer; forming a single-crystal silicon region in the opening; forming a silicon-germanium region at the surface of single-crystal silicon region, in contact with the remaining regions of the semiconductor layer and of the silicon layer; and forming a second doped region at least in the remaining space of the trench. | 10-17-2013 |
20130277753 | BICMOS DEVICES ON ETSOI - A BiCMOS device structure, method of manufacturing the same and design structure thereof are provided. The BiCMOS device structure includes a substrate having a layer of semiconductor material upon an insulating layer. The BiCMOS device structure further includes a bipolar junction transistor structure formed in a first region of the substrate having an extrinsic base layer formed at least partially from a portion of the layer of semiconductor material. | 10-24-2013 |
20130328130 | BIPOLAR TRANSISTOR IN BIPOLAR-CMOS TECHNOLOGY - A process of forming an integrated circuit containing a bipolar transistor and an MOS transistor, by forming a base layer of the bipolar transistor using a non-selective epitaxial process so that the base layer has a single crystalline region on a collector active area and a polycrystalline region on adjacent field oxide, and concurrently implanting the MOS gate layer and the polycrystalline region of the base layer, so that the base-collector junction extends into the substrate less than one-third of the depth of the field oxide, and vertically cumulative doping density of the polycrystalline region of the base layer is between 80 percent and 125 percent of a vertically cumulative doping density of the MOS gate. An integrated circuit containing a bipolar transistor and an MOS transistor formed by the described process. | 12-12-2013 |
20130341729 | SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SAME, AND NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - Provided is a semiconductor element having, while maintaining the same integratability as a conventional MOSFET, excellent switch characteristics compared with the MOSFET, that is, having the S-value less than 60 mV/order at room temperature. Combining the MOSFET and a tunnel bipolar transistor having a tunnel junction configures a semiconductor element that shows an abrupt change in the drain current with respect to a change in the gate voltage (an S-value of less than 60 mV/order) even at a low voltage. | 12-26-2013 |
20140035064 | SEMICONDUCTOR STRUCTURES AND METHODS OF MANUFACTURE - Semiconductor structures and methods of manufacture are disclosed herein. Specifically, disclosed herein are methods of manufacturing a high-voltage metal-oxide-semiconductor field-effect transistor and respective structures. A method includes forming a field-effect transistor (FET) on a substrate in a FET region, forming a high-voltage FET (HVFET) on a dielectric stack over a over lightly-doped diffusion (LDD) drain in a HVFET region, and forming an NPN on the substrate in an NPN region. | 02-06-2014 |
20140084380 | System and Method for an Integrated Circuit Having Transistor Segments - In accordance with an embodiment, an integrated circuit has a first transistor made of a plurality of first transistor segments disposed in a well area, and a second transistor made of at least one second transistor segment. Drain regions of the plurality of first transistor segments and the at least one second transistor segment are coupled to a common output node. The at least one second transistor segment is disposed in the well area such that an electrostatic discharge pulse applied to a common output node homogenously triggers parasitic bipolar devices coupled to each drain region of the plurality of first transistor segments and the drain region of the at least one second transistor segment. | 03-27-2014 |
20140124871 | LATERAL BIPOLAR JUNCTION TRANSISTOR - A lateral bipolar junction transistor includes an emitter region; a base region surrounding the emitter region; a gate disposed at least over a portion of the base region; and a collector region surrounding the base region; wherein the portion of the base region under the gate does not under go a threshold voltage implant process. | 05-08-2014 |
20150108580 | METHODS OF FORMING BIPOLAR DEVICES AND AN INTEGRATED CIRCUIT PRODUCT CONTAINING SUCH BIPOLAR DEVICES - One method disclosed herein includes performing at least one common process operation to form a plurality of first gate structures for each of a plurality of field effect transistors and a plurality of second gate structures above a region where a bipolar transistor will be formed and performing an ion implantation process and a heating process to form a continuous doped emitter region that extends under all of the second gate structures. A device disclosed herein includes a first plurality of field effect transistors with first gate structures, a bipolar transistor that has an emitter region and a plurality of second gate structures positioned above the emitter region, wherein the bipolar transistor comprises a continuous doped emitter region that extends laterally under all of the plurality of second gate structures. | 04-23-2015 |
20150303189 | SEMICONDUCTOR DEVICE - A semiconductor device which uses a fin-type semiconductor layer to form a bipolar transistor. The substrate of the device is a semiconductor substrate. A collector is a first-conductivity type impurity region which is formed in the semiconductor substrate. A base is a second-conductivity type impurity region which is formed in the surface layer of the collector. A first semiconductor layer is a fin-type semiconductor layer which lies over the base. An emitter is formed in the first semiconductor layer and its bottom is coupled to the base. A first contact is coupled to the collector, a second contact is coupled to the base, and a third contact is coupled to the emitter. | 10-22-2015 |
20160064371 | NON-PLANAR ESD DEVICE FOR NON-PLANAR OUTPUT TRANSISTOR AND COMMON FABRICATION THEREOF - Protecting non-planar output transistors from electrostatic discharge (ESD) events includes providing a non-planar semiconductor structure, the structure including a semiconductor substrate with a well of n-type or p-type. The provided non-planar structure further includes raised semiconductor structure(s) coupled to the substrate, non-planar transistor(s) of a type opposite the well, each transistor being situated on one of the raised structure(s), the non-planar transistor(s) each including a source, a drain and a gate, the non-planar structure further including parasitic bipolar junction transistor(s) (BJT(s)) on the raised structure(s), each BJT including a collector and an emitter situated on the raised structure and a base being the well, and a well contact for the base of the BJT. Protecting the non-planar output transistors further includes electrically coupling the drain of the non-planar transistor and the collector of the BJT to an output of a circuit, and electrically coupling the source of the non-planar transistor, the emitter of the BJT and the well contact to a ground of the circuit. | 03-03-2016 |
20160079237 | High Voltage Semiconductor Power Switching Device - A three terminal high voltage Darlington bipolar transistor power switching device includes two high voltage bipolar transistors, with collectors connected together serving as the collector terminal. The base of the first high voltage bipolar transistor serves as the base terminal. The emitter of the first high voltage bipolar transistor connects to the base of the second high voltage bipolar transistor (inner base), and the emitter of the second high voltage bipolar transistor serves as the emitter terminal. A diode has its anode connected to the inner base (emitter of the first high voltage bipolar transistor, or base of the second high voltage bipolar transistor), and its cathode connected to the base terminal. Similarly, a three terminal hybrid MOSFET/bipolar high voltage switching device can be formed by replacing the first high voltage bipolar transistor of the previous switching device by a high voltage MOSFET. | 03-17-2016 |
20160141363 | METHOD OF IMPROVING LATERAL BJT CHARACTERISTICS IN BCD TECHNOLOGY - In a lateral BJT formed using a BiCMOS process, the collector-to-emitter breakdown voltage (BV | 05-19-2016 |
20170236794 | Multichip modules and methods of fabrication | 08-17-2017 |