Entries |
Document | Title | Date |
20080203481 | NONVOLATILE SEMICONDUCTOR MEMORY AND METHOD OF MANUFACTURING THE SAME - A nonvolatile semiconductor memory has a semiconductor substrate, a first insulating film formed on a channel region on a surface portion of the semiconductor substrate, a charge accumulating layer formed on the first insulating film, a second insulating film formed on the charge accumulating layer, a control gate electrode formed on the second insulating film, and a third insulating film including an Si—N bond that is formed on a bottom surface and side surfaces of the charge accumulating layer. | 08-28-2008 |
20080203482 | Transistors having gate pattern for self-alignment with channel impurity diffusion region in active region and methods of forming the same - A transistor having a gate pattern suitable for self-alignment with a channel impurity diffusion region in an active region includes an active region and an isolation layer disposed in a semiconductor substrate. The isolation layer is formed to define the active region. An insulating layer covering the active region and the isolation layer is disposed. The insulating layer has a channel-induced hole on the active region. A channel impurity diffusion region and a gate trench are formed in the active region to be aligned with the channel-induced hole. The insulating layer is removed from the semiconductor substrate. A gate pattern is disposed in the gate trench to overlap the channel impurity diffusion region. | 08-28-2008 |
20080217694 | SPACERS FOR FINFETS (FIELD EFFECT TRANSISTORS) - A spacer structure for FinFETs. The structure includes (a) a substrate, (b) a semiconductor fin region on top of the substrate, (c) a gate dielectric region on side walls of the semiconductor fin region, and (d) a gate electrode region on top and on side walls of the semiconductor fin region. The gate dielectric region (i) is sandwiched between and (ii) electrically insulates the gate electrode region and the semiconductor fin region. The structure further includes a first spacer region on a first side wall of the gate electrode region. A first side wall of the semiconductor fin region is exposed to a surrounding ambient. A top surface of the first spacer region is coplanar with a top surface of the gate electrode region. | 09-11-2008 |
20080224221 | CASCODE CURRENT MIRROR AND METHOD - A cascode amplifier (CA) ( | 09-18-2008 |
20080224222 | SEMICONDUCTOR DEVICE HAVING A FIN TRANSISTOR AND METHOD FOR FABRICATING THE SAME - A fin transistor includes fin active region, an isolation layer covering both sidewalls of a lower portion of the fin active region, a gate insulation layer disposed over a surface of the fin active region, and a gate electrode disposed over the gate insulation layer and the isolation layer, and having a work function ranging from approximately 4.4 eV to approximately 4.8 eV. | 09-18-2008 |
20080224223 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes: a first gate electrode formed above a first active region in a substrate with a first gate insulating film interposed therebetween; and a second gate electrode formed above a second active region in the substrate with a second gate insulating film interposed therebetween. The first gate electrode has a shorter gate length than the second gate electrode, the first gate electrode is fully silicided, and at least a portion of the second gate electrode in contact with the second gate insulating film is not silicided. | 09-18-2008 |
20080224224 | TUNNEL FIELD-EFFECT TRANSISTOR WITH GATED TUNNEL BARRIER - A tunnel field effect transistor (TFET) is disclosed. In one aspect, the transistor comprises a gate that does not align with a drain, and only overlap with the source extending at least up to the interface of the source-channel region and optionally overlaps with part of the channel. Due to the shorter gate, the total gate capacitance is reduced, which is directly reflected in an improved switching speed of the device. In addition to the advantage of an improved switching speed, the transistor also has a processing advantage (no alignment of the gate with the drain is necessary), as well as a performance improvement (the ambipolar behavior of the TFET is reduced). | 09-18-2008 |
20080251847 | MEMORY CELL ARRAY IN A SEMICONDUCTOR MEMORY DEVICE - A memory cell array in a semiconductor device includes a semiconductor substrate having active areas and isolation areas in parallel, a plurality of select lines having generally a U like shape and is configured to cross over the active areas and the isolation areas, and a plurality of word lines formed between the select lines. In view of the select line being formed in U like shape, an occurrence of a punch through phenomenon is prevented by a junction area formed between the select lines. As a result, a margin for reducing a width of the select line is increased. | 10-16-2008 |
20080251848 | Manufacturing method for homogenizing the environment of transistors and associated device - A semiconductor device is provided that includes a plurality of patterns. Each pattern includes at least one field effect transistor. Each field effect transistor includes a source region, a drain region, a channel region, and a gate region formed above the channel region. A portion of the plurality of patterns is formed in a single active area of a semiconductor substrate, where the area delimited by an isolation region. One of the source region and the drain region of each adjacent pattern are formed in said active area. | 10-16-2008 |
20080265328 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device comprising the steps of: forming a first silicon oxide film which covers a first region on the top surface of a silicon substrate, but which does not cover a second region and a third region thereon; oxidizing the silicon substrate to thicken the first silicon oxide film formed on the first region, and to form a second silicon oxide film on the second region and the third region; forming a first silicon film which covers the first region and the second region, but which does not cover the third region; etching and removing the second silicon oxide film formed on the third region by using the first silicon film as a mask; and forming a third silicon oxide film on the third region, the third silicon oxide film being thinner than the second silicon oxide film. | 10-30-2008 |
20080272435 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device includes a first gate structure including a gate dielectric layer directly contacting the substrate, a bottom electrode on the gate dielectric layer and a top electrode on the bottom electrode, and a second gate structure including a gate dielectric layer directly contacting the substrate and a gate electrode on the gate dielectric layer. | 11-06-2008 |
20080277730 | Semiconductor Device Manufactured Using a Laminated Stress Layer - There is presented a method of forming a semiconductor device. The method comprises forming gate structures including forming gate electrodes over a semiconductor substrate and forming spacers adjacent the gate electrodes. Source/drains are formed adjacent the gate structures, and a laminated stress layer is formed over the gate structure and the semiconductor substrate. The formation of the laminated stress layer includes cycling a deposition process to form a first stress layer over the gate structures and the semiconductor substrate and at least a second stress layer over the first stress layer. After the laminated layer is formed, it is subjected to an anneal process conducted at a temperature of about 900° C. or greater. | 11-13-2008 |
20080283921 | DUAL-GATE NMOS DEVICES WITH ANTIMONY SOURCE-DRAIN REGIONS AND METHODS FOR MANUFACTURING THEREOF - A dual-gate device includes an active layer between a first gate structure and a second gate structure. Each gate structure is isolated from the active layer by a dielectric layer and is located above a semiconductor or channel region in the active layer defined by spaced-apart diffusion regions formed by implanting antimony ions. The antimony-doped diffusion regions are particularly suitable in the dual-gate device because it can be implanted and activated at a temperature less than 900° C. and show little movement of the implanted antimony ions even after numerous thermal steps in the manufacturing process. As a result, dual-gate devices with well-controlled channel lengths may be achieved. | 11-20-2008 |
20080283922 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a first conductivity type well formed on a semiconductor substrate, and a first transistor and a second transistor formed on the well. The first transistor has first pocket regions containing a first conductivity type impurity and first source/drain regions containing a second conductivity type impurity, and the second transistor has second pocket regions containing a first conductivity type impurity and second source/drain regions containing a second conductivity type impurity, and executes an analog function. A concentration of the first conductivity type impurity contained in the source-side and the drain-side second pocket regions is lower than a concentration of the first conductivity type impurity included in the first pocket regions. | 11-20-2008 |
20080283923 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device and a manufacturing method thereof are provided. The manufacturing method can form a structure of a thin film transistor (TFT) having a symmetric lightly doped region, and thus provide superior operation reliability and electrical performance. In addition, the manufacturing method forms gate patterns of different TFTs by the same mask process and thereby avoids the misalignment of masks so as to improve the processing yield and reduce the manufacturing cost. | 11-20-2008 |
20080290415 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes: an isolation region formed in a semiconductor substrate; a first active region and a second active region surrounded by the isolation region; an n-type gate electrode and a p-type gate electrode formed on gate insulating films; an insulating film and a silicon region formed on the isolation region and isolating the n-type gate electrode and the p-type gate electrode from each other; and a metal silicide film formed on the upper surfaces of the n-type gate electrode, the silicon region, the p-type gate electrode, and part of the insulating film formed therebetween. The n-type gate electrode is electrically connected to the p-type gate electrode through the metal silicide film. | 11-27-2008 |
20080296689 | Nanotube dual gate transistor and method of operating the same - A nanotube dual gate transistor and associated method of use are provided. The nanotube dual gate transistor includes a substrate, a nanotube material, a source conductor and a drain conductor, a top gate and a back gate. The nanotube material is formed over the substrate having a nanotube channel with a first end and a second end. The source conductor is coupled to the first end of the nanotube channel and the drain conductor is coupled to the second end of the nanotube channel. The back gate is formed under one or more of the devices for receiving a DC signal for establishing a desired optimal operational state of the device(s). The top gate is formed over the nanotube channel for receiving an AC signal for high frequency operation of the device(s) with low gate capacitance. | 12-04-2008 |
20080303094 | SELF-ALIGNED SPLIT GATE MEMORY CELL AND METHOD OF FORMING - A method of forming a split gate memory device using a semiconductor layer includes patterning an insulating layer to leave a pillar thereof. A gate dielectric is formed over the semiconductor layer. A charge storage layer is formed over the gate dielectric and along first and second sides of the pillar. A gate material layer is formed over the gate dielectric and pillar. An etch is performed to leave a first portion of the gate material laterally adjacent to a first side of the pillar and over a first portion of the charge storage layer that is over the gate dielectric to function as a control gate of the memory device and a second portion of the gate material laterally adjacent to a second side of the pillar and over a second portion of the charge storage layer that is over the gate dielectric to function as a select gate. | 12-11-2008 |
20080303095 | VARYING MUGFET WIDTH TO ADJUST DEVICE CHARACTERISTICS - One embodiment of the present invention relates to an integrated circuit that includes a first multi-gate transistor that has a first fin width and a first threshold voltage. The integrated circuit also includes a second multi-gate transistor that has a second fin width that is greater than the first width and a second threshold voltage that is less than the first threshold voltage. Other circuits and methods are also disclosed. | 12-11-2008 |
20080303096 | Semiconductor devices and methods of manufacture thereof - Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes forming a transistor, the transistor including a fin having a first side and a second side opposite the first side. The transistor includes a first gate electrode disposed on the first side of the fin and a second gate electrode disposed on the second side of the fin. The method includes forming a silicide or germanide of a metal on the first gate electrode and the second gate electrode of the transistor. The amount of the metal of the silicide or germanide is substantially homogeneous over the first gate electrode and the second gate electrode proximate the fin. | 12-11-2008 |
20080308869 | SEMICONDUCTOR DEVICE WHICH HAS MOS STRUCTURE AND METHOD OF MANUFACTURING THE SAME - The technology which can control a threshold value appropriately, adopting the material which fitted each gate electrode of the MOS structure from which a threshold value differs without making the manufacturing process complicated, and does not make remarkable diffusion to the channel region from the gate electrode is offered. | 12-18-2008 |
20080315314 | SEMICONDUCTOR DEVICE HAVING A DUAL GATE ELECTRODE AND METHODS OF MAKING THE SAME - Disclosed is a method for forming a dual gate electrode of a semiconductor device, which may improve manufacturing productivity by simplifying a process of forming gate electrodes in PMOS and NMOS regions, respectively, and may provide improvement in performance by making the two gate electrodes have a different thickness and material state in a manner that one of the two gate electrodes has a single-layer structure and the other one has a two-layer structure. | 12-25-2008 |
20080315315 | ELECTRONIC DEVICE INCLUDING A GATED DIODE - An electronic device can include a gated diode, wherein the gated diode includes a junction diode structure including a junction. A first conductive member spaced apart from and adjacent to the junction can be connected to a first signal line. A second conductive member, spaced apart from and adjacent to the junction, can be both electrically connected to a second signal line and electrically insulated from the first conductive member. The junction diode structure can include a p-n or a p-i-n junction. A process for forming the electronic device is also described. | 12-25-2008 |
20090001474 | Semiconductor device with reduced fringe capacitance - In one embodiment of the invention, a non-planar transistor includes a gate electrode and multiple fins. A trench contact is coupled to the fins. The contact bottom is formed above the substrate and does not directly contact the substrate. The contact bottom is higher than the gate top. | 01-01-2009 |
20090008716 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device according to an embodiment includes: a fin type MOSFET having a first gate electrode, and a first gate insulating film for generating Fermi level pinning in the first gate electrode; and a planar type MOSFET having a second gate electrode, and a second gate insulating film for generating no Fermi level pinning in the second gate electrode, or generating Fermi level pinning weaker than that generated in the first gate electrode in the second gate electrode. | 01-08-2009 |
20090014802 | Semiconductor device and method for manufacturing the same - The semiconductor device according to the present invention is a Fin-FET that can substantially increase the channel width without unnecessarily elevating the height of the Fin. The Fin-FET has gate electrodes | 01-15-2009 |
20090020819 | FIN-TYPE FIELD EFFECT TRANSISTOR STRUCTURE WITH MERGED SOURCE/DRAIN SILICIDE AND METHOD OF FORMING THE STRUCTURE - Disclosed herein are embodiments of a multiple fin fin-type field effect transistor (i.e., a multiple fin dual-gate or tri-gate field effect transistor) in which the multiple fins are partially or completely merged by a highly conductive material (e.g., a metal silicide). Merging the fins in this manner allow series resistance to be minimized with little, if any, increase in the parasitic capacitance between the gate and source/drain regions. Merging the semiconductor fins in this manner also allows each of the source/drain regions to be contacted by a single contact via as well as more flexible placement of that contact via. | 01-22-2009 |
20090026543 | FINFET WITH SUBLITHOGRAPHIC FIN WIDTH - At least one recessed region having two parallel edges is formed in an insulator layer over a semiconductor layer such that the lengthwise direction of the recessed region coincides with optimal carrier mobility surfaces of the semiconductor material in the semiconductor layer for finFETs to be formed. Self-assembling block copolymers are applied within the at least one recessed region and annealed to form a set of parallel polymer block lines having a sublithographic width and containing a first polymeric block component. The pattern of sublithographic width lines is transferred into the semiconductor layer employing the set of parallel polymer block lines as an etch mask. Sublithographic width semiconductor fins thus formed may have sidewalls for optimal carrier mobility for p-type finFETs and n-type finFETs. | 01-29-2009 |
20090026544 | SEMICONDUCTOR DEVICE - A non-insulated DC-DC converter has a power MOS•FET for a highside switch and a power MOS•FET for a lowside switch. In the non-insulated DC-DC converter, the power MOS•FET for the highside switch and the power MOS•FET for the lowside switch, driver circuits that control operations of these elements, respectively, and a Schottky barrier diode connected in parallel with the power MOS•FET for the lowside switch are respectively formed in four different semiconductor chips. These four semiconductor chips are housed in one package. The semiconductor chips are mounted over the same die pad. The semiconductor chips are disposed so as to approach each other. | 01-29-2009 |
20090039433 | SEMICONDUCTOR DEVICE WITH HIGH-K/DUAL METAL GATE - An apparatus, and method of manufacture thereof, comprising a first semiconductor device and a second semiconductor device. The first semiconductor device includes a first gate electrode having a first metal layer forming a first trench and a second metal layer filling the first trench, wherein the first and second metal layers have substantially different metallic compositions. The second semiconductor device includes a second gate electrode having a third metal layer forming a second trench and a fourth metal layer filling the second trench, wherein the third and fourth metal layers have substantially different metallic compositions, and wherein the first and third metal layers have substantially different metallic compositions. | 02-12-2009 |
20090065869 | SEMICONDUCTOR DEVICE - A semiconductor device has a plurality of fins formed on a semiconductor substrate to be separated from each other, a first contact region which connects commonly one end side of the plurality of fins, a second contact region which connects commonly the other end side of the plurality of fins, a gate electrode arranged to be opposed to at least both side surfaces of the plurality of fins by sandwiching a gate insulating film therebetween, a source electrode including the first contact region and the plurality of fins on a side closer to the first contact region than the gate electrode, and a drain electrode including the second contact region and the plurality of fins on a side closer to the second contact than the gate electrode. The ratio Rd/Rs of a resistance Rd of each fin in the drain region to a resistance Rs of each fin in the source region is larger than 1. | 03-12-2009 |
20090072316 | DOUBLE LAYER STRESS FOR MULTIPLE GATE TRANSISTORS - Multiple gate transistors are provided with a dual stress layer for increased channel mobility and enhanced effective and saturated drive currents. Embodiments include transistors comprising a first stress layer under the bottom gate and a second stress layer overlying the top gate. Embodiments further include transistors with the bottom gate within or through the first stress layer. Methodology includes sequentially depositing stressed silicon nitride, nitride, oxide, amorphous silicon, and oxide layers on a substrate having a bottom oxide layer thereon, patterning to define a channel length, depositing a top nitride layer, patterning stopping on the stressed silicon nitride layer, removing the amorphous silicon layer, epitaxially growing silicon through a window in the substrate to form source, drain, and channel regions, doping, removing the deposited nitride and oxide layers, growing gate oxides, depositing polysilicon to form gates, growing isolation oxides, and depositing the top stress layer. | 03-19-2009 |
20090072317 | MICROELECTRONIC STRUCTURE BY SELECTIVE DEPOSITION - A finFET structure includes a semiconductor fin located over a substrate. A gate electrode is located traversing the semiconductor fin. The gate electrode has a spacer layer located adjoining a sidewall thereof. The spacer layer does not cover completely a sidewall of the semiconductor fin. The gate electrode and the spacer layer may be formed using a vapor deposition method that provides for selective deposition upon a sidewall of a mandrel layer but not upon an adjoining surface of the substrate, so that the spacer layer does not cover completely the sidewall of the semiconductor fin. Other microelectronic structures may be fabricated using the lateral growth methodology. | 03-19-2009 |
20090079004 | METHOD FOR MAKING A TRANSISTOR WITH SELF-ALIGNED DOUBLE GATES BY REDUCING GATE PATTERNS - This invention relates to an improved microelectronic method for making a double gate structure for a transistor, and particularly gate patterns ( | 03-26-2009 |
20090085118 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a first active region formed having a first portion extending laterally and second portion extendedly vertically upward from a central portion of the first portion; a second active region formed spaced from the first active region, the second active region having a third portion extending laterally, fourth and fifth portions extending vertically downwardly at distal end portions of the third portion, and a sixth portion extending vertically downwardly at a central portion of the third portion; a first gate formed extending vertically and overlapping the first portion of the first active region and the third portion of the second active regions; a second gate formed extending vertically and overlapping the first portion of the first active region and the third portion of the second active regions; a third gate formed extending in a direction perpendicular to the first and second gates and overlapping of the fourth and fifth portions of the second active region; and a plurality of contacts spaced apart predetermined distances from the gates. | 04-02-2009 |
20090085119 | DOUBLE-GATE TRANSISTOR STRUCTURE EQUIPPED WITH A MULTI-BRANCH CHANNEL - Double gate transistor microelectronic device comprising:
| 04-02-2009 |
20090096028 | Transistor of the I-MOS Type Comprising Two Independent Gates and Method of Using Such a Transistor - The transistor comprises a source ( | 04-16-2009 |
20090101978 | FIN-TYPE FIELD EFFECT TRANSISTOR STRUCTURE WITH MERGED SOURCE/DRAIN SILICIDE AND METHOD OF FORMING THE STRUCTURE - Disclosed herein are embodiments of a design structure of a multiple fin fin-type field effect transistor (i.e., a multiple fin dual-gate or tri-gate field effect transistor) in which the multiple fins are partially or completely merged by a highly conductive material (e.g., a metal silicide). Merging the fins in this manner allow series resistance to be minimized with little, if any, increase in the parasitic capacitance between the gate and source/drain regions. Merging the semiconductor fins in this manner also allows each of the source/drain regions to be contacted by a single contact via as well as more flexible placement of that contact via. | 04-23-2009 |
20090108356 | INTEGRATION SCHEME FOR MULTIPLE METAL GATE WORK FUNCTION STRUCTURES - A metal gate stack containing a metal layer having a mid-band-gap work function is formed on a high-k gate dielectric layer. A threshold voltage adjustment oxide layer is formed over a portion of the high-k gate dielectric layer to provide devices having a work function near a first band gap edge, while another portion of the high-k dielectric layer remains free of the threshold voltage adjustment oxide layer. A gate stack containing a semiconductor oxide based gate dielectric and a doped polycrystalline semiconductor material may also be formed to provide a gate stack having a yet another work function located near a second band gap edge which is the opposite of the first band gap edge. A dense circuit containing transistors of p-type and n-type with the mid-band-gap work function are formed in the region containing the threshold voltage adjustment oxide layer. | 04-30-2009 |
20090108357 | SEMICONDUCTOR DEVICE - Electrode placement which applies easy heat dispersion of a semiconductor device with high power density and high exothermic density is provided for the semiconductor device including: a gate electrode, a source electrode, and a drain electrode which are placed on a first surface of a substrate | 04-30-2009 |
20090114991 | SEMICONDUCTOR DEVICES HAVING A CONTACT STRUCTURE AND METHODS OF FABRICATING THE SAME - A semiconductor device includes an isolation region formed in a semiconductor substrate to define an active region. First and second impurity regions spaced apart from each other are formed in the active region. A gate trench region crosses the active region between the first and second impurity regions and extends to the isolation region. A first contact structure having a sidewall in vertical alignment with a sidewall of the gate trench region adjacent to the first impurity region is provided on the first impurity region. A second contact structure having a sidewall in vertical alignment with a sidewall of the gate trench region adjacent to the second impurity region is provided on the second impurity region. A gate electrode is provided in the gate trench region. A gate dielectric layer is interposed between the gate trench region and the gate electrode. | 05-07-2009 |
20090121291 | DENSE CHEVRON NON-PLANAR FIELD EFFECT TRANSISTORS AND METHOD - Disclosed are embodiments of semiconductor structure and a method of forming the semiconductor structure that simultaneously maximizes device density and avoids contacted-gate pitch and fin pitch mismatch, when multiple parallel angled fins are formed within a limited area on a substrate and then traversed by multiple parallel gates (e.g., in the case of stacked, chevron-configured, CMOS devices). This is accomplished by using, not a minimum lithographic fin pitch, but rather by using a fin pitch that is calculated as a function of a pre-selected contacted-gate pitch, a pre-selected fin angle and a pre-selected periodic pattern for positioning the fins relative to the gates within the limited area. Thus, the disclosed structure and method allow for the conversion of a semiconductor product design layout with multiple, stacked, planar FETs in a given area into a semiconductor product design layout with multiple, stacked, chevron-configured, non-planar FETs in the same area. | 05-14-2009 |
20090121292 | Fabrication of local damascene finFETs using contact type nitride damascene mask - Disclosed are methods for forming FinFETs using a first hard mask pattern to define active regions and a second hard mask to protect portions of the insulating regions between active regions. The resulting field insulating structure has three distinct regions distinguished by the vertical offset from a reference plane defined by the surface of the active regions. These three regions will include a lower surface found in the recessed openings resulting from the damascene etch, an intermediate surface and an upper surface on the remaining portions of the lateral field insulating regions. The general correspondence between the reference plane and the intermediate surface will tend to suppress or eliminate residual gate electrode materials from this region during formation of the gate electrodes, thereby improving the electrical isolation between adjacent active regions and improving the performance of the resulting semiconductor devices. | 05-14-2009 |
20090127625 | SEMICONDUCTOR DEVICE - A semiconductor device according to one embodiment includes: a substrate; a plurality of fins made of a semiconductor and formed on the substrate; a plurality of via contact regions formed between the fins, the plurality of via contact regions and the plurality of the fins constituting a closed loop structure; a gate contact region on the substrate arranged at a position surrounded by the closed loop structure; a plurality of gate electrodes connected to the gate contact region respectively, each of the plurality of gate electrodes sandwiching both side faces of each of the plurality of fins between its opposite regions via gate insulating film; and source/drain regions formed in regions in the plurality of fins and in the contact region, the regions being formed on both sides of a region sandwiched by the gate electrodes along longitudinal direction of the fin. | 05-21-2009 |
20090134463 | SEMICONDUCTOR STRUCTURE AND SYSTEM FOR FABRICATING AN INTEGRATED CIRCUIT CHIP - A semiconductor structure and a system for fabricating an integrated circuit chip. The semiconductor structure includes: a buried oxide layer on a semiconductor wafer; a thin fin structure on the buried oxide layer, wherein the thin fin structure includes a first hard mask on a semiconductor fin, wherein the semiconductor fin is disposed between the first hard mask and a surface of the buried oxide layer; and a thick mesa structure on the buried oxide layer, and wherein the thick mesa structure includes a semiconductor mesa. The system for fabricating an integrated circuit chip enables: providing a buried oxide layer on and in direct mechanical contact with a semiconductor wafer; and concurrently forming at least one fin-type field effect transistor and at least one thick-body device on the buried oxide layer. | 05-28-2009 |
20090140341 | INDEPENDENT N-TIPS FOR MULTI-GATE TRANSISTORS - Independent n-tips for multi-gate transistors are generally described. In one example, an apparatus includes a semiconductor fin, one or more multi-gate pull down (PD) devices coupled with the semiconductor fin, the one or more PD devices having an n-tip dopant concentration in the semiconductor fin material adjacent to the one or more PD devices, and one or more multi-gate pass gate (PG) devices coupled with the semiconductor fin, the one or more PG devices having an n-tip dopant concentration in the semiconductor fin material adjacent to the one or more PG devices, wherein the n-tip dopant concentration for the PG device is lower than the n-tip dopant concentration for the PD device. | 06-04-2009 |
20090140342 | SEMICONDUCTOR MEMORY DEVICE AND A METHOD OF MANUFACTURING THE SAME, A METHOD OF MANUFACTURING A VERTICAL MISFET AND A VERTICAL MISFET, AND A METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE - Vertical MISFETs are formed over drive MISFETs and transfer MISFETs. The vertical MISFETs comprise rectangular pillar laminated bodies each formed by laminating a lower semiconductor layer (drain), an intermediate semiconductor layer, and an upper semiconductor layer (source), and gate electrodes formed on corresponding side walls of the laminated bodies with gate insulating films interposed therebetween. In each vertical MISFET, the lower semiconductor layer constitutes a drain, the intermediate semiconductor layer constitutes a substrate (channel region), and the upper semiconductor layer constitutes a source. The lower semiconductor layer, the intermediate semiconductor layer and the upper semiconductor layer are each comprised of a silicon film. The lower semiconductor layer and the upper semiconductor layer are doped with a p type and constituted of a p type silicon film. | 06-04-2009 |
20090146213 | Semiconductor LSI circuit and a method for fabricating the semiconductor LSI circuit - Basic logic gates are formed in a small area, and a highly integrated and microscopic structure is provided. In an nMOSFET and a pMOSFET, gate electrodes are formed facing each other and sandwiching a semiconductor region via gate insulting layers. Respective drain regions of the nMOSFET and the pMOSFET are connected to each other. A high potential is applied to a source region of the pMOSFET while an intermediate potential between the high and a low potential is applied to a source region of the nMOSFET. As a result, a NAND gate is provided. The intermediate potential between the high and the low potential is applied to the source region of the pMOSFET. The low potential is applied to the source region of the nMOSFET. As a result, a NOR gate is provided. | 06-11-2009 |
20090146214 | METHOD FOR MANUFACTURING AN EEPROM CELL - A method for manufacturing a cell of a non-volatile electrically erasable and programmable memory including a dual-gate MOS transistor. The method includes the steps of providing a semiconductor substrate covered with an insulating layer including a thinned down portion and having a first surface common with the substrate and a second surface opposite to the first surface; and incorporating nitrogen at the level of the second surface, whereby the maximum nitrogen concentration is closer to the second surface than to the first surface. | 06-11-2009 |
20090166741 | REDUCING EXTERNAL RESISTANCE OF A MULTI-GATE DEVICE USING SPACER PROCESSING TECHNIQUES - Reducing external resistance of a multi-gate device using spacer processing techniques is generally described. In one example, a method includes depositing a sacrificial gate electrode to one or more multi-gate fins, the one or more multi-gate fins comprising a gate region, a source region, and a drain region, the gate region being disposed between the source and drain regions, patterning the sacrificial gate electrode such that the sacrificial gate electrode material is coupled to the gate region and substantially no sacrificial gate electrode is coupled to the source and drain regions of the one or more multi-gate fins, forming a dielectric film coupled to the source and drain regions of the one or more multi-gate fins, removing the sacrificial gate electrode from the gate region of the one or more multi-gate fins, depositing spacer gate dielectric to the gate region of the one or more multi-gate fins wherein substantially no spacer gate dielectric is deposited to the source and drain regions of the one or more multi-gate fins, the source and drain regions being protected by the dielectric film, and etching the spacer gate dielectric to completely remove the spacer gate dielectric from the gate region area to be coupled with a final gate electrode except a remaining pre-determined thickness of spacer gate dielectric to be coupled with the final gate electrode that remains coupled with the dielectric film. | 07-02-2009 |
20090166742 | REDUCING EXTERNAL RESISTANCE OF A MULTI-GATE DEVICE BY INCORPORATION OF A PARTIAL METALLIC FIN - Reducing external resistance of a multi-gate device by incorporation of a partial metallic fin is generally described. In one example, an apparatus includes a semiconductor substrate and one or more fins of a multi-gate transistor device coupled with the semiconductor substrate, the one or more fins having a gate region, a source region, and a drain region, the gate region being disposed between the source and drain regions where the gate region of the one or more fins includes a semiconductor material and where the source and drain regions of the one or more fins include a metal portion and a semiconductor portion, the metal portion and the semiconductor portion being coupled together. | 07-02-2009 |
20090166743 | INDEPENDENT GATE ELECTRODES TO INCREASE READ STABILITY IN MULTI-GATE TRANSISTORS - Independent gate electrodes for multi-gate transistors are generally described. In one example, an apparatus includes a semiconductor fin, one or more multi-gate pull down (PD) gate stacks coupled with the semiconductor fin, the one or more PD gate stacks including a PD gate electrode, and one or more multi-gate pass gate (PG) gate stacks coupled with the semiconductor fin, the one or more PG gate stacks including a PG gate electrode, the PG gate electrode having a greater threshold voltage than the PD gate electrode. | 07-02-2009 |
20090166744 | Semiconductor device with deep trench structure - Disclosed herein is a semiconductor device with a deep trench structure for effectively isolating heavily doped wells of neighboring elements from each other at a high operating voltage. The semiconductor device with a deep trench structure includes a semiconductor substrate in which a first conductivity type well and a second conductivity type well having conductivity opposite to that of the first conductivity type well are formed, a gate oxide film and a gate electrode laminated on each of the first conductivity type well and the second conductivity type well, second conductivity type drift regions formed on both sides of the gate electrode formed on the first conductivity type well, first conductivity type drift regions formed on both sides of the gate electrode formed on the second conductivity type well, and a first isolation layer having a trench structure deeper than the first and second conductivity type wells and isolating the first conductivity type well and the second conductivity type well from each other. | 07-02-2009 |
20090179273 | SEMICONDUCTOR DEVICE - A semiconductor device according to the present invention includes: a first region having a first conductive type; a plurality of second regions having a second conductive type that differs from the first conductive type, and formed to be arranged in the first region; a plurality of third regions having the first conductive type and formed in the second regions; an electrode forming a channel between the first region and the third region; and a plurality of extended second regions having the second conductive type, arranged in the first region such as to individually include one of the second regions and having an impurity density that is lower than an impunity density of the second regions. | 07-16-2009 |
20090179274 | Semiconductor Device and Method for Fabricating the Same - A semiconductor device and a method for fabricating the same is disclosed, in which one line is formed from a main gate to a sidewall gate, so that it is possible to scale a transistor below nano degree, and the semiconductor device includes a semiconductor substrate; a device isolation layer for dividing the semiconductor substrate into a field region and an active region; a main gate on a predetermined portion of the active region of the semiconductor substrate; a sidewall gate at both sides of the main gate on the semiconductor substrate; a main gate insulating layer between the main gate and the semiconductor substrate; a sidewall gate insulating layer between the sidewall gate and the semiconductor substrate; an insulating interlayer between the main gate and the sidewall gate; a first silicide layer on the surface of the main gate and the sidewall gate, to electrically connect the main gate with the sidewall gate; and source and drain regions at both sides of the sidewall gate in the active region of the semiconductor substrate. | 07-16-2009 |
20090206404 | REDUCING EXTERNAL RESISTANCE OF A MULTI-GATE DEVICE BY SILICIDATION - Reducing external resistance of a multi-gate device by silicidation is generally described. In one example, an apparatus includes a semiconductor substrate, a multi-gate fin coupled with the semiconductor substrate, the multi-gate fin having a first surface, a second surface, and a third surface, the multi-gate fin also having a gate region, a source region, and a drain region, the gate region being disposed between the source and drain regions wherein the source and drain regions of the multi-gate fin are fully or substantially silicized with a metal silicide, and a spacer dielectric material coupled to the first surface and the second surface wherein the spacer dielectric material substantially covers the first surface and the second surface in the source and drain regions. | 08-20-2009 |
20090206405 | FIN FIELD EFFECT TRANSISTOR STRUCTURES HAVING TWO DIELECTRIC THICKNESSES - Fin field-effect-transistor (finFET) structures having two dielectric thicknesses are generally described. In one example, an apparatus includes a semiconductor substrate, a semiconductor fin coupled with the semiconductor substrate, the semiconductor fin having at least a first surface, a second surface, and a third surface, the third surface being substantially parallel to the first surface and substantially perpendicular to the second surface, a spacer dielectric coupled to the second surface of the semiconductor fin, a back gate dielectric having a back gate dielectric thickness coupled to the first surface of the semiconductor fin, and a front gate dielectric having a front gate dielectric thickness coupled to the third surface of the semiconductor fin wherein the back gate dielectric thickness is greater than the front gate dielectric thickness | 08-20-2009 |
20090206406 | MULTI-GATE DEVICE HAVING A T-SHAPED GATE STRUCTURE - A multi-gate device having a T-shaped gate structure is generally described. In one example, an apparatus includes a semiconductor substrate, at least one multi-gate fin coupled with the semiconductor substrate, the multi-gate fin having a gate region, a source region, and a drain region, the gate region being positioned between the source and drain regions, a gate dielectric coupled to the gate region of the multi-gate fin, a gate electrode coupled to the gate dielectric, the gate electrode having a first thickness and a second thickness, the second thickness being greater than the first thickness, a first spacer dielectric coupled to a portion of the gate electrode having the first thickness, and a second spacer dielectric coupled to the first spacer dielectric and coupled to the gate electrode where the second spacer dielectric is coupled to a portion of the gate electrode having the second thickness. | 08-20-2009 |
20090206407 | SEMICONDUCTOR DEVICES HAVING TENSILE AND/OR COMPRESSIVE STRESS AND METHODS OF MANUFACTURING - A semiconductor device and method of manufacturing is disclosed which has a tensile and/or compressive strain applied thereto. The method includes forming at least one trench in a material; and filling the at least one trench by an oxidation process thereby forming a strain concentration in a channel of a device. The structure includes a gate structure having a channel and a first oxidized trench on a first of the channel, respectively. The first oxidized trench creates a strain component in the channel to increase device performance. | 08-20-2009 |
20090230478 | APPARATUS AND METHODS FOR IMPROVING MULTI-GATE DEVICE PERFORMACE - Embodiments of an apparatus and methods for improving multi-gate device performance are generally described herein. Other embodiments may be described and claimed. | 09-17-2009 |
20090256207 | FINFET DEVICES FROM BULK SEMICONDUCTOR AND METHODS FOR MANUFACTURING THE SAME - Disclosed herein is a transistor comprising a first fin having a first gate electrode disposed across the first fin; the gate electrode contacting opposing surfaces of the fin; and a planar oxide layer having a second gate electrode disposed across the planar oxide layer to form a planar metal oxide semiconductor field effect transistor; the first fin and the planar oxide layer being disposed upon a surface of a wafer. | 10-15-2009 |
20090256208 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A method of fabricating a semiconductor device according to one embodiment includes: forming a fin and a film on a semiconductor substrate, the film being located at least either on the fin or under the fin and on the semiconductor substrate; forming a gate electrode so as to sandwich both side faces of the fin via a gate insulating film; and expanding or shrinking the film, thereby generating a strain in a height direction of the fin in a channel region. | 10-15-2009 |
20090267155 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device has a semiconductor substrate, a semiconductor fin which is formed on the semiconductor substrate, which has a long side direction and a short side direction, and which has a carbon-containing silicon film including an impurity and a silicon film formed on the carbon-containing silicon film, a gate electrode which is formed to face both side surfaces of the semiconductor fin in the short side direction, source and drain regions which are respectively formed in the semiconductor fin located in the direction of both sides in the long side direction of the semiconductor fin so as to sandwich the gate electrode, and an element isolation insulating film which is formed on the side surface of the semiconductor fin and between the gate electrode and the semiconductor substrate. | 10-29-2009 |
20090294857 | Method for Manufacturing Semiconductor Apparatus Having Saddle-Fin Transistor and Semiconductor Apparatus Fabricated Thereby - A method for manufacturing a semiconductor memory apparatus may include forming a channel region and a gate region through a self-alignment etching process on a cell region; and forming a three-dimensional multi-channel region through an etching process using a first multi-channel mask on a core region and a peripheral region and forming a gate region through an etching process using a second multi-channel mask, thereby preventing mis-arrangement of gates. | 12-03-2009 |
20090321833 | VERTICAL PROFILE FinFET GATE FORMED VIA PLATING UPON A THIN GATE DIELECTRIC - Methods of making vertical profile FinFET gate electrodes via plating upon a thin gate dielectric are disclosed. In one embodiment, a method for forming a transistor, comprises: providing a semiconductor topography comprising a semiconductor substrate and a semiconductor fin structure extending above the substrate; forming a gate dielectric across exposed surfaces of the semiconductor topography; patterning a mask upon the semiconductor topography such that only a select portion of the gate dielectric is exposed that defines where a gate electrode is to be formed; and plating a metallic material upon the select portion of the gate dielectric to form a gate electrode across a portion of the fin structure. | 12-31-2009 |
20090321834 | Substrate fins with different heights - A device includes a number of fins. Some of the fins have greater heights than other fins. This allows the selection of different drive currents and/or transistor areas. | 12-31-2009 |
20090321835 | THREE-DIMENSIONAL TRANSISTOR WITH DOUBLE CHANNEL CONFIGURATION - A three-dimensional double channel transistor configuration is provided in which a second channel region may be embedded into the body region of the transistor, thereby providing a three-state behavior, which may therefore increase functionality of conventional three-dimensional transistor architectures. The double channel three-dimensional transistors may be used for forming a static RAM cell with a reduced number of transistors, while also providing scalability by taking advantage of the enhanced controllability of FinFETS and nano pipe transistor architectures. | 12-31-2009 |
20090321836 | DOUBLE GATE AND TRI-GATE TRANSISTOR FORMED ON A BULK SUBSTRATE AND METHOD FOR FORMING THE TRANSISTOR - Three-dimensional transistor structures such as FinFETS and tri-gate transistors may be formed on the basis of an enhanced masking regime, thereby enabling the formation of drain and source areas, the fins and isolation structures in a self-aligned manner within a bulk semiconductor material. After defining the basic fin structures, highly efficient manufacturing techniques of planar transistor configurations may be used, thereby even further enhancing overall performance of the three-dimensional transistor configurations. | 12-31-2009 |
20100019321 | MULTIPLE-GATE MOS TRANSISTOR USING Si SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - Provided are a multiple-gate MOS (metal oxide semiconductor) transistor and a method of manufacturing the same. The transistor includes a single crystalline active region having a channel region having an upper portion of a streamlined shape (∩) obtained by patterning an upper portion of a bulk silicon substrate with an embossed pattern, and having a thicker and wider area than the channel region; a nitride layer formed at both side surfaces of the single crystalline active region to expose an upper portion of the single crystalline active region at a predetermined height; and a gate electrode formed to be overlaid with the exposed upper portion of the single crystalline active region of the channel region. | 01-28-2010 |
20100025767 | SEMICONDUCTOR DEVICE - A semiconductor device includes N fins made of semiconductor regions aligned in parallel with each other in the top view plain, a gate electrode formed on both side surfaces of each of the N fins to cross the fins, source/drain layers formed in each of the N fins by sandwiching the gate electrode, a first wiring connected to one of the source/drain layers via a first contact formed in each of M fins, and a second wiring connected to the other one of the source/drain layers via a second contact formed in each of K fins. | 02-04-2010 |
20100044796 | Depletion mode trench MOSFET for improved efficiency of DC/DC converter applications - A DC-to-DC converter includes a high-side transistor and a low-side transistor wherein the high-side transistor is implemented with a high-side enhancement mode MOSFET. The low side-transistor further includes a low-side enhancement MOSFET shunted with a depletion mode transistor having a gate shorted to a source of the low-side enhancement mode MOSFET. A current transmitting in the DC-to-DC converter within a time-period between T | 02-25-2010 |
20100072552 | FIELD EFFECT TRANSISTOR FOR PREVENTING COLLAPSE OR DEFORMATION OF ACTIVE REGIONS - A field effect transistor includes an active region provided in a projecting part on a surface of a semiconductor substrate, the projecting part extending in a fixed direction parallel to the surface, and a gate electrode provided on a sidewall of the projecting part along the fixed direction with a gate insulating films interposed. | 03-25-2010 |
20100096700 | METHOD FOR FABRICATING ASYMMETRIC DOUBLE-GATE TRANSISTORS BY WHICH ASYMMETRIC AND SYMMETRIC DOUBLE-GATE TRANSISTORS CAN BE MADE ON THE SAME SUBSTRATE - A method for fabricating a microelectronic device with one or several asymmetric and symmetric double-gate transistors on the same substrate. | 04-22-2010 |
20100109086 | Method of Fabricating A Fin Field Effect Transistor (FinFET) Device - A method of fabricating a semiconductor using a fin field effect transistor (FINFET) is disclosed. In a particular embodiment, a method includes depositing, on a silicon substrate, a first dummy structure having a first sidewall and a second sidewall separated by a first width. The method also includes depositing, on the silicon substrate, a second dummy structure concurrently with depositing the first dummy structure. The second dummy structure has a third sidewall and a fourth sidewall that are separated by a second width. The second width is substantially greater than the first width. The first dummy structure is used to form a first pair of fins separated by approximately the first width. The second dummy structure is used to form a second pair of fins separated by approximately the second width. | 05-06-2010 |
20100109087 | Multichannel Metal Oxide Semiconductor (MOS) Transistors - Unit cells of metal oxide semiconductor (MOS) transistors are provided including an integrated circuit substrate an a MOS transistor on the integrated circuit substrate. The MOS transistor includes a source region, a drain region and a gate. The gate is positioned between the source region and the drain region. A horizontal channel is provided between the source and drain regions. The horizontal channel includes at least two spaced apart horizontal channel regions. Related methods of fabricating MOS transistors are also provided. | 05-06-2010 |
20100127331 | ASYMMETRIC METAL-OXIDE-SEMICONDUCTOR TRANSISTORS - Mixed gate metal-oxide-semiconductor transistors are provided. The transistors may have an asymmetric configuration that exhibits increased output resistance. Each transistor may be formed from a gate insulating layer formed on a semiconductor. The gate insulating layer may be a high-K material. Source and drain regions in the semiconductor may define a transistor gate length. The gate length may be larger than the minimum specified by semiconductor fabrication design rules. The transistor gate may be formed from first and second gate conductors with different work functions. The relative sizes of the first and gate conductors in a given transistor control the threshold voltage for the transistor. A computer-aided design tool may be used to receive a circuit design from a user. The tool may generate fabrication masks for the given design that include mixed gate transistors with threshold voltages optimized to meet circuit design criteria. | 05-27-2010 |
20100127332 | INTEGRATED CIRCUIT TRANSISTORS - Metal-oxide-semiconductor transistors are provided. A metal-oxide-semiconductor transistor may be formed on a semiconductor substrate. Source and drain regions may be formed in the substrate. A gate insulator such as a high-K dielectric may be formed between the source and drain regions. A gate may be formed from multiple gate conductors. The gate conductors may be metals with different workfunctions. A first of the gate conductors may form a pair of edge gate conductors that are adjacent to dielectric spacers. An opening between the edge gate conductors may be filled with the second gate conductor to form a center gate conductor. A self-aligned gate formation process may be used in fabricating the metal-oxide-semiconductor transistor. | 05-27-2010 |
20100133619 | SEMICONDUCTOR DEVICE HAVING A FIN TRANSISTOR AND METHOD FOR FABRICATING THE SAME - A fin transistor includes fin active region, an isolation layer covering both sidewalls of a lower portion of the fin active region, a gate insulation layer disposed over a surface of the fin active region, and a gate electrode disposed over the gate insulation layer and the isolation layer, and having a work function ranging from approximately 4.4 eV to approximately 4.8 eV. | 06-03-2010 |
20100155846 | Metal-insulator-semiconductor tunneling contacts - A contact to a source or drain region. The contact has a conductive material, but that conductive material is separated from the source or drain region by an insulator. | 06-24-2010 |
20100155847 | SELF ALIGNED FIELD EFFECT TRANSISTOR STRUCTURE - Provided is a self aligned field effect transistor structure. The self aligned field effect transistor structure includes: an active region pattern on a substrate; a first gate electrode and a second gate electrode facing each other with the active region pattern therebetween; and a source electrode and a drain electrode connected to the active region pattern and disposed to be symmetric with respect to a line connecting the first and second gate electrodes, wherein the first and second gate electrodes and the source and drain electrodes are disposed on the same plane of the substrate. | 06-24-2010 |
20100171178 | SEMICONDUCTOR DEVICES INCLUDING DUAL GATE STRUCTURES AND METHODS OF FORMING SUCH SEMICONDUCTOR DEVICES - Semiconductor devices including dual gate structures and methods of forming such semiconductor devices are disclosed. For example, semiconductor devices are disclosed that include a first gate stack that may include a first conductive gate structure formed from a first material, and a second gate stack that may include a dielectric structure formed from an oxide of the first material. For another example, methods including forming a high-K dielectric material layer over a semiconductor substrate, forming a first conductive material layer over the high-K dielectric material layer, oxidizing a portion of the first conductive material layer to convert the portion of the first conductive material layer to a dielectric material layer, and forming a second conductive material layer over both the conductive material layer and the dielectric material layer are also disclosed. | 07-08-2010 |
20100171179 | FULL PERIPHERY MULTI-GATE TRANSISTOR WITH OHMIC STRIP - A full periphery multi-gate transistor with ohmic strip is disclosed. The multi-gate transistor comprises a substrate, a multi-layer structure, a source finger, a drain finger, and a gate. The gate is formed between the source finger and the drain finger, and then a conduction channel is formed between the source finger and the drain finger. The gate also meanderingly wraps around an end of the source finger and an end of the drain finger. Therefore, the end of the source finger and the end of the drain finger are parts of the conduction channel and both provide channel conductance. In addition, an ohmic strip is formed between two gate lines of the gate. | 07-08-2010 |
20100193870 | TECHNIQUES FOR IMPROVING TRANSISTOR-TO-TRANSISTOR STRESS UNIFORMITY - An integrated circuit ( | 08-05-2010 |
20100200923 | MULTIPLE-GATE TRANSISTOR STRUCTURE AND METHOD FOR FABRICATING - A multiple-gate transistor structure which includes a substrate, source and drain islands formed in a portion of the substrate, a fin formed of a semi-conducting material that has a top surface and two sidewall surfaces, a gate dielectric layer overlying the fin, and a gate electrode wrapping around the fin on the top surface and the two sidewall surfaces separating source and drain islands. In an alternate embodiment, a substrate that has a depression of an undercut or a notch in a top surface of the substrate is utilized. | 08-12-2010 |
20100264494 | RECESSED CHANNEL ARRAY TRANSISTOR (RCAT) STRUCTURES AND METHOD OF FORMATION - Recessed channel array transistor (RCAT) structures and method of formation are generally described. In one example, an electronic device includes a semiconductor substrate, a first fin coupled with the semiconductor substrate, the first fin comprising a first source region and a first drain region, and a first gate structure of a recessed channel array transistor (RCAT) formed in a first gate region disposed between the first source region and the first drain region, wherein the first gate structure is formed by removing a sacrificial gate structure to expose the first fin in the first gate region, recessing a channel structure into the first fin, and forming the first gate structure on the recessed channel structure. | 10-21-2010 |
20100270619 | FIN FIELD EFFECT TRANSISTOR HAVING LOW LEAKAGE CURRENT AND METHOD OF MANUFACTURING THE FINFET - Provided is a fin field effect transistor (FinFET) having low leakage current and a method of manufacturing the same. The FinFET includes: a bulk silicon substrate; a fence-shaped body formed by patterning the substrate; an insulating layer formed on a surface of the substrate to a first height of the fence-shaped body; a gate insulating layer formed at side walls and an upper surface of the fence-shaped body at which the insulating layer is not formed; a gate electrode formed on the gate insulating layer; source/drain formed at regions of the fence-shaped body where the gate electrode is not formed. The gate electrode includes first and second gate electrodes which are in contact with each other and have different work functions. Particularly, the second gate electrode having a low work function is disposed to be close to the drain. As a result, the FinFET according to the present invention increases a threshold voltage by using a material having the high work function for the gate electrode and lowers the work function of the gate electrode overlapping with the drain, so that gate induced drain leakage (GIDL) can be reduced. | 10-28-2010 |
20100276756 | SUBSTRATE FINS WITH DIFFERENT HEIGHTS - A device includes a number of fins. Some of the fins have greater heights than other fins. This allows the selection of different drive currents and/or transistor areas. | 11-04-2010 |
20100320541 | METHOD FOR FABRICATING ASYMMETRIC DOUBLE-GATE TRANSISTORS BY WHICH ASYMMETRIC AND SYMMETRIC DOUBLE-GATE TRANSISTORS CAN BE MADE ON THE SAME SUBSTRATE - A method for fabricating a microelectronic device with one or plural asymmetric double-gate transistors, including: a) forming one or plural structures on a substrate including at least a first semiconducting block configured to form a first gate of a double-gate transistor, and at least a second semiconducting block configured to form a second gate of the double-gate transistor, the first block and the second block being located on opposite sides of at least one semiconducting zone and separated from the semiconducting zone by a first gate dielectric zone and a second gate dielectric zone respectively, and b) doping at least one or plural semiconducting zones in the second block of at least one given structure among the structures, using at least one implantation selective relative to the first block. | 12-23-2010 |
20100327360 | FET With Replacement Gate Structure and Method of Fabricating the Same - A MUGFET and method of manufacturing a MUGFET is shown. The method of manufacturing the MUGFET includes forming temporary spacer gates about a plurality of active regions and depositing a dielectric material over the temporary spacer gates, including between the plurality of active regions. The method further includes etching portions of the dielectric material to expose the temporary spacer gates and removing the temporary spacer gates, leaving a space between the active regions and a remaining portion of the dielectric material. The method additionally includes filling the space between the active regions and above the remaining portion of the dielectric material with a gate material. | 12-30-2010 |
20110018063 | APPARATUS AND METHODS FOR IMPROVING MULTI-GATE DEVICE PERFORMANCE - Embodiments of an apparatus and methods for improving multi-gate device performance are generally described herein. Other embodiments may be described and claimed. | 01-27-2011 |
20110018064 | SRAM CELL COMPRISING FINFETS - An SRAM finFET cell includes fins ( | 01-27-2011 |
20110042748 | MULTI-GATE NON-PLANAR FIELD EFFECT TRANSISTOR STRUCTURE AND METHOD OF FORMING THE STRUCTURE USING A DOPANT IMPLANT PROCESS TO TUNE DEVICE DRIVE CURRENT - Disclosed are embodiments of a semiconductor structure that includes one or more multi-gate field effect transistors (MUGFETs), each MUGFET having one or more semiconductor fins. In the embodiments, a dopant implant region is incorporated into the upper portion of the channel region of a semiconductor fin in order to selectively modify (i.e., decrease or increase) the threshold voltage within that upper portion relative to the threshold voltage in the lower portion and, thereby to selectively modify (i.e., decrease or increase) device drive current. In the case of a multiple semiconductor fins, the use of implant regions, the dopant conductivity type in the implant regions and/or the sizes of the implant regions can be varied from fin to fin within a multi-fin MUGFET or between different single and/or multi-fin MUGFETs so that individual device drive current can be optimized. Also disclosed herein are embodiments of a method of forming the semiconductor structure. | 02-24-2011 |
20110049633 | LIGHT EMITTING DEVICE, METHOD FOR MANUFACTURING THEREOF AND ELECTRONIC APPLIANCE - An object of the invention is to provide a method for manufacturing a light emitting device capable of reducing deterioration of elements due to electrostatic charge caused in manufacturing the light emitting device. Another object of the invention is to provide a light emitting device in which defects due to the deterioration of elements caused by the electrostatic charge are reduced. The method for manufacturing the light emitting device includes a step of forming a top-gate type transistor for driving a light emitting element. In the step of forming the top-gate type transistor, when processing a semiconductor layer, a first grid-like semiconductor layer extending in rows and columns is formed over a substrate. The plurality of second island-like semiconductor layers are formed between the first semiconductor layer. The plurality of second island-like second semiconductor layers serve as an active layer of the transistor. | 03-03-2011 |
20110068404 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a first semiconductor layer and a second semiconductor layer that have a form of fins and are arranged a predetermined distance apart from each other, in which a center portion of each serves as a channel region, and side portions sandwiching the center portion serve as source/drain regions, a gate electrode formed on two side surfaces of each of the channel regions of the first semiconductor layer and the second semiconductor layer, with a gate insulating film interposed therebetween, an insulating film formed to fill a gap between the source/drain regions of the first semiconductor layer and the source/drain regions of the second semiconductor layer, and silicide layers formed on side surfaces of the source/drain regions of the first semiconductor layer and the source/drain regions of the second semiconductor layer that are not covered by the insulating film. | 03-24-2011 |
20110068405 | FIN FIELD EFFECT TRANSISTOR - An exemplary structure for the fin field effect transistor comprises a substrate comprising a major surface; a plurality of fin structures protruding from the major surface of the substrate, wherein each fin structure comprises an upper portion and a lower portion separated at a transition location at where the sidewall of the fin structure is at an angle of 85 degrees to the major surface of the substrate, wherein the upper portion has sidewalls that are substantially perpendicular to the major surface of the substrate and a top surface having a first width, wherein the lower portion has tapered sidewalls on opposite sides of the upper portion and a base having a second width larger than the first width; and a plurality of isolation structures between the fin structures, wherein each isolation structure extends from the major surface of the substrate to a point above the transition location. | 03-24-2011 |
20110073951 | ENHANCED STRESS-RETENTION FIN-FET DEVICES AND METHODS OF FABRICATING ENHANCED STRESS RETENTION FIN-FET DEVICES - Fin-FETS and methods of fabricating fin-FETs. The methods include: providing substrate comprising a silicon oxide layer on a top surface of a semiconductor substrate, a stiffening layer on a top surface of the silicon oxide layer, and a single crystal silicon layer on a top surface of the stiffening layer; forming a fin from the single crystal silicon layer; forming a source and a drain in the fin and on opposite sides of a channel region of the fin; forming a gate dielectric layer on at least one surface of the fin in the channel region; and forming a gate electrode on the gate dielectric layer. | 03-31-2011 |
20110079854 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device and a method for fabricating the same are described. A polysilicon layer is formed on a substrate. The polysilicon layer is doped with an N-type dopant. A portion of the polysilicon layer is then removed to form a plurality of dummy patterns. Each dummy pattern has a top, a bottom, and a neck arranged between the top and the bottom, where the width of the neck is narrower than that of the top. A dielectric layer is formed on the substrate to cover the substrate disposed between adjacent dummy patterns, and the top of each dummy pattern is exposed. Thereafter, the dummy patterns are removed to form a plurality of trenches in the dielectric layer. A plurality of gate structures is formed in the trenches, respectively. | 04-07-2011 |
20110095369 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a drain region, a source region, a channel region, an insulating film, a gate electrode, a first semiconductor region, and
| 04-28-2011 |
20110095370 | WORDLINE RESISTANCE REDUCTION METHOD AND STRUCTURE IN AN INTEGRATED CIRCUIT MEMORY DEVICE - Methods and structures for reducing resistance in wordlines of an integrated circuit memory device are disclosed. In one embodiment, the method includes forming multiple columns of polycrystalline silicon for respective number of wordlines, forming core transistor junctions and periphery transistor junctions associated with the wordlines, performing a salicidation process for the periphery transistor junction and performing a salicidation process for the columns of polycrystalline silicon to from the wordlines with low resistance. | 04-28-2011 |
20110121396 | PILLAR-TYPE FIELD EFFECT TRANSISTOR HAVING LOW LEAKAGE CURRENT - A pillar-type field effect transistor having low leakage current is provided. The pillar-type field effect transistor includes: a semiconductor body, source and drain formed in a semiconductor pillar; a gate insulating layer formed on a surface of the semiconductor body; a gate electrode formed on a surface of the gate insulating layer. The gate electrode includes a first gate electrode and a second gate electrode being electrically connected with the first gate electrode. The first gate electrode has a work function higher than that of the second gate electrode. Accordingly, the gate induced drain leakage (GIDL) can be reduced, so that an off-state leakage current can be greatly reduced. | 05-26-2011 |
20110121397 | METHODS FOR PROTECTING GATE STACKS DURING FABRICATION OF SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICES FABRICATED FROM SUCH METHODS - Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methods are provided. Methods for fabricating a semiconductor device include providing a semiconductor substrate having an active region and a shallow trench isolation (STI) region. Epitaxial layer is formed on the active region to define a lateral overhang portion in a divot at the active region/STI region interface. A gate stack is formed having a first gate stack-forming layer overlying the semiconductor substrate. First gate stack-forming layer includes a non-conformal layer of metal gate-forming material which is directionally deposited to form a thinned break portion just below the lateral overhang portion. After the step of forming the gate stack, a first portion of the non-conformal layer is in the gate stack and a second portion is exposed. The thinned break portion at least partially isolates the first and second portions during subsequent etch chemistries. | 05-26-2011 |
20110127610 | Multiple-Gate Semiconductor Device and Method - A system and method for manufacturing multiple-gate semiconductor devices is disclosed. An embodiment comprises multiple fins, wherein intra-fin isolation regions extend into the substrate less than inter-fin isolation regions. Regions of the multiple fins not covered by the gate stack are removed and source/drain regions are formed from the substrate so as to avoid the formation of voids between the fins in the source/drain region. | 06-02-2011 |
20110147842 | MULTI-GATE SEMICONDUCTOR DEVICE WITH SELF-ALIGNED EPITAXIAL SOURCE AND DRAIN - A channel strained multi-gate transistor with low parasitic resistance and method of manufacturing the same. A gate stack may be formed over a semiconductor fin having a gate-coupled sidewall height (H | 06-23-2011 |
20110147843 | Semiconductor Component and Method for Producing a Semiconductor Component - A semiconductor component includes at least one field effect transistor disposed along a trench in a semiconductor region and has at least one locally delimited dopant region in the semiconductor region. The at least one locally delimited dopant region extends from or over a pn junction between the source region and the body region of the transistor or between the drain region and the body region of the transistor into the body region as far as the gate electrode, such that a gap between the pn junction and the gate electrode in the body region is bridged by the locally delimited dopant region. | 06-23-2011 |
20110215411 | Method for Forming an Independent Bottom Gate Connection For Buried Interconnection Including Bottom Gate of a Planar Double Gate MOSFET - A method is provided for making a semiconductor device, which comprises (a) providing a semiconductor structure comprising a top gate ( | 09-08-2011 |
20110227161 | METHOD OF FABRICATING HYBRID IMPACT-IONIZATION SEMICONDUCTOR DEVICE - The present disclosure provides a semiconductor device which includes a semiconductor substrate, a first gate structure disposed over the substrate, the first gate structure including a first gate electrode of a first conductivity type, a second gate structure disposed over the substrate and proximate the first gate structure, the second gate structure including a second gate electrode of a second conductivity type different from the first conductivity type, a first doped region of the first conductivity type disposed in the substrate, the first doped region including a first lightly doped region aligned with a side of the first gate structure, and a second doped region of the second conductivity type disposed in the substrate, the second doped region including a second lightly doped region aligned with a side of the second gate structure. | 09-22-2011 |
20110266625 | Maintaining Integrity of a High-K Gate Stack After Embedding a Stressor Material by Using a Liner - Gate failures in sophisticated high-k metal gate electrode structures formed in an early manufacturing stage may be reduced by forming a protective liner material after the incorporation of a strain-inducing semiconductor alloy and prior to performing any critical wet chemical processes. In this manner, attacks in the sensitive gate materials after the incorporation of the strain-inducing semiconductor material may be avoided, without influencing the further processing of the device. In this manner, very sophisticated circuit designs may be applied in sophisticated gate first approaches. | 11-03-2011 |
20110284965 | REDUCING EXTERNAL RESISTANCE OF A MULTI-GATE DEVICE USING SPACER PROCESSING TECHNIQUES - Reducing external resistance of a multi-gate device using spacer processing techniques is generally described. In one example, a method includes depositing a sacrificial gate electrode to one or more multi-gate fins, the one or more multi-gate fins comprising a gate region, a source region, and a drain region, the gate region being disposed between the source and drain regions, patterning the sacrificial gate electrode such that the sacrificial gate electrode material is coupled to the gate region and substantially no sacrificial gate electrode is coupled to the source and drain regions of the one or more multi-gate fins, forming a dielectric film coupled to the source and drain regions of the one or more multi-gate fins, removing the sacrificial gate electrode from the gate region of the one or more to multi-gate fins, depositing spacer gate dielectric to the gate region of the one or more multi-gate fins wherein substantially no spacer gate dielectric is deposited to the source and drain regions of the one or more multi-gate fins, the source and drain regions being protected by the dielectric film, and etching the spacer gate dielectric to completely remove the spacer gate dielectric from the gate region area to be coupled with a final gate electrode except a remaining pre-determined thickness of spacer gate dielectric to be coupled with the final gate electrode that remains coupled with the dielectric film. | 11-24-2011 |
20110291196 | Self-Aligned Multiple Gate Transistor Formed on a Bulk Substrate - Three-dimensional transistors in a bulk configuration may be formed on the basis of gate openings or gate trenches provided in a mask material. Hence, self-aligned semiconductor fins may be efficiently patterned in the underlying active region in a portion defined by the gate opening, while other gate openings may be efficiently masked, in which planar transistors are to be provided. After patterning the semiconductor fins and adjusting the effective height thereof, the further processing may be continued on the basis of process techniques that may be commonly applied to the planar transistors and the three-dimensional transistors. | 12-01-2011 |
20110316083 | FET with Self-Aligned Back Gate - A back-gated field effect transistor (FET) includes a substrate, the substrate comprising top semiconductor layer on top of a buried dielectric layer on top of a bottom semiconductor layer; a front gate located on the top semiconductor layer; a channel region located in the top semiconductor layer under the front gate; a source region located in the top semiconductor layer on a side of the channel region, and a drain region located in the top semiconductor layer on the side of the channel region opposite the source regions; and a back gate located in the bottom semiconductor layer, the back gate configured such that the back gate abuts the buried dielectric layer underneath the channel region, and is separated from the buried dielectric layer by a separation distance underneath the source region and the drain region. | 12-29-2011 |
20110316084 | FET WITH REPLACEMENT GATE STRUCTURE AND METHOD OF FABRICATING THE SAME - A MUGFET and method of manufacturing a MUGFET is shown. The method of manufacturing the MUGFET includes forming temporary spacer gates about a plurality of active regions and depositing a dielectric material over the temporary spacer gates, including between the plurality of active regions. The method further includes etching portions of the dielectric material to expose the temporary spacer gates and removing the temporary spacer gates, leaving a space between the active regions and a remaining portion of the dielectric material. The method additionally includes filling the space between the active regions and above the remaining portion of the dielectric material with a gate material. | 12-29-2011 |
20120007183 | Multi-gate Transistor Having Sidewall Contacts - A multi-gate transistor having a plurality of sidewall contacts and a fabrication method that includes forming a semiconductor fin on a semiconductor substrate and etching a trench within the semiconductor fin, depositing an oxide material within the etched trench, and etching the oxide material to form a dummy oxide layer along exposed walls within the etched trench; and forming a spacer dielectric layer along vertical sidewalls of the dummy oxide layer. The method further includes removing exposed dummy oxide layer in a channel region in the semiconductor fin and beneath the spacer dielectric layer, forming a high-k material liner along sidewalls of the channel region in the semiconductor fin, forming a metal gate stack within the etched trench, and forming a plurality of sidewall contacts within the semiconductor fin along adjacent sidewalls of the dummy oxide layer. | 01-12-2012 |
20120025314 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method for manufacturing the same are disclosed. The method for forming the semiconductor device includes forming one or more buried gates in a semiconductor substrate, forming a landing plug between the buried gates, forming a bit line region exposing the landing plug over the semiconductor substrate, forming a glue layer in the bit line region, forming a bit line material in the bit line region, and removing the glue layer formed at inner sidewalls of the bit line region, and burying an insulation material in a part where the glue layer is removed. A titanium nitride (TiN) film formed at sidewalls of the damascene bit line is removed, so that resistance of the bit line is maintained and parasitic capacitance of the bit line is reduced, resulting in the improvement of device characteristics. | 02-02-2012 |
20120025315 | Transistor with Embedded Strain-Inducing Material and Dummy Gate Electrodes Positioned Adjacent to the Active Region - The uniformity of transistor characteristics may be enhanced for transistors having incorporated therein a strain-inducing semiconductor material by using appropriately positioned dummy gate electrode structures. To this end, the dummy gate electrode structures may be positioned such that these structures may connect to or may overlap with the edge of the active region, thereby preserving a portion of the initial semiconductor material of the active region at the edge thereof upon forming the corresponding cavities. | 02-02-2012 |
20120032265 | GRADED HIGH GERMANIUM COMPOUND FILMS FOR STRAINED SEMICONDUCTOR DEVICES - Embodiments of an apparatus and methods for providing a graded high germanium compound region are generally described herein. Other embodiments may be described and claimed. | 02-09-2012 |
20120032266 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate; a memory cell region defined in the semiconductor substrate; and a line-and-space pattern formed in the memory cell region in which the lines constitute an active region and the spaces constitute an element isolation region. The first and the second lines of the active region counted from two opposing ends of the memory cell region are each separated into two or more line segments. The segment ends of the line segments of the first and the second lines are linked to form a loop by a linking pattern. | 02-09-2012 |
20120061762 | Asymmetric FinFET devices - Asymmetric FET devices, and a method for fabricating such asymmetric devices on a fin structure is disclosed. The fabrication method includes disposing over the fin a high-k dielectric layer followed by a threshold-modifying layer, performing an ion bombardment at a tilted angle which removes the threshold-modifying layer over one of the fin's side-surfaces. The completed FET devices will be asymmetric due to the threshold-modifying layer being present only in one of two devices on the side of the fin. In an alternate embodiment further asymmetries are introduced, again using tilted ion implantation, resulting in differing gate-conductor materials for the two FinFET devices on each side of the fin. | 03-15-2012 |
20120061763 | METHODS OF FORMING NON-VOLATILE MEMORY DEVICES INCLUDING LOW-K DIELECTRIC GAPS IN SUBSTRATES AND DEVICES SO FORMED - A method of manufacturing a non-volatile memory device, can be provided by forming a gate insulating layer and a gate conductive layer on a substrate that includes active regions that are defined by device isolation regions that include a carbon-containing silicon oxide layer. The gate conductive layer and the gate insulating layer can be sequentially etched to expose the carbon-containing silicon oxide layer. The carbon-containing silicon oxide layer can be wet-etched to recess a surface of the carbon-containing silicon oxide layer to below a surface of the substrate. Then, an interlayer insulating layer can be formed between the gate insulating layer and the gate conductive layer on the carbon-containing silicon oxide layer, where an air gap can be formed between the carbon-containing silicon oxide layer and the gate insulating layer. | 03-15-2012 |
20120098068 | FORMATION OF MULTI-HEIGHT MUGFET - A method and structure comprise a field effect transistor structure that includes a first rectangular fin structure and a second rectangular fin structure, both positioned on a substrate. The sides of the second rectangular fin structure are parallel to the sides of the first rectangular fin structure. Further, a trench insulator is positioned on the substrate and positioned between a side of the first rectangular fin structure and a side of the second rectangular fin structure. A gate conductor is positioned on the trench insulator, positioned over the sides and the top of the first rectangular fin structure, and positioned over the sides and the top of the second rectangular fin structure. The gate conductor runs perpendicular to the sides of the first rectangular fin structure and the sides of the second rectangular fin structure. Also, a gate insulator is positioned between the gate conductor and the first rectangular fin structure and between the gate conductor and the second rectangular fin structure. The gate conductor is positioned adjacent to a relatively larger portion of the sides of the second rectangular fin structure and is positioned adjacent to a relatively smaller portion of the sides of the first rectangular fin structure. | 04-26-2012 |
20120119297 | Semiconductor Devices and Methods of Manufacture Thereof - Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes forming a transistor, the transistor including a fin having a first side and a second side opposite the first side. The transistor includes a first gate electrode disposed on the first side of the fin and a second gate electrode disposed on the second side of the fin. The method includes forming a silicide or germanide of a metal on the first gate electrode and the second gate electrode of the transistor. The amount of the metal of the silicide or germanide is substantially homogeneous over the first gate electrode and the second gate electrode proximate the fin. | 05-17-2012 |
20120126325 | METHOD FOR ADJUSTING FIN WIDTH IN INTEGRATED CIRCUITRY - A method includes growing a plurality of parallel mandrels on a surface of a semiconductor substrate, each mandrel having at least two laterally opposite sidewalls and a predetermined width. The method further includes forming a first type of spacers on the sidewalls of the mandrels, wherein the first type of spacers between two adjacent mandrels are separated by a gap. The predetermined mandrel width is adjusted to close the gap between the adjacent first type of spacers to form a second type of spacers. The mandrels are removed to form a first type of fins from the first type of spacers, and to form a second type of fins from spacers between two adjacent mandrels. The second type of fins are wider than the first type of fins. | 05-24-2012 |
20120126326 | DEVICE AND METHOD FOR FORMING FINS IN INTEGRATED CIRCUITRY - A semiconductor FinFET device includes a plurality of gate lines formed in a first direction, and two types of fin structures. A first type of fin structures is formed in a second direction, and a second type of fin structures formed perpendicular to the first type of fin structures. A contact hole couples to one or more of the second type of fin structures. | 05-24-2012 |
20120126327 | RESONATOR HAVING TERMINALS AND A METHOD FOR MANUFACTURING THE RESONATOR - A resonator and a method for manufacturing a resonator are provided. The method may include doping a wafer, and forming on the wafer a substrate, a drain electrode, a source electrode, a gate electrode, and at least one nanowire. | 05-24-2012 |
20120168868 | MULTI-GATE FIELD-EFFECT TRANSISTOR WITH ENHANCED AND ADAPTABLE LOW-FREQUENCY NOISE - A field-effect transistor has an extra gate above a shallow trench isolation (STI) to enhance and to adapt the low-frequency noise induced by an STI-silicon interface. By changing the voltage applied to the STI gate, the field-effect transistor is able to adapt its low-frequency noise over four decades. The field-effect transistor can be fabricated with a standard CMOS logic process without additional masks or process modification. | 07-05-2012 |
20120168869 | SEMICONDUCTOR DEVICE, AND ITS MANUFACTURING METHOD - The present invention provides a high breakdown voltage transistor that eases an electric field concentration caused between a gate and a drain. | 07-05-2012 |
20120175706 | Chip-Exposed Semiconductor Device - A method of making a chip-exposed semiconductor package comprising the steps of: plating a plurality of electrode on a front face of each chip on a wafer; grinding a backside of the wafer and depositing a back metal then separating each chips; mounting the chips with the plating electrodes adhering onto a front face of a plurality of paddle of a leadframe; adhering a tape on the back metal and encapsulating with a molding compound; removing the tape and sawing through the leadframe and the molding compound to form a plurality of packaged semiconductor devices. | 07-12-2012 |
20120199911 | VERTICAL DISCRETE DEVICE WITH DRAIN AND GATE ELECTRODES ON THE SAME SURFACE AND METHOD FOR MAKING THE SAME - The present technology discloses a vertical discrete device with gate and drain electrodes on the same surface and method for making the same. The vertical discrete device comprises a deep gate contact that couples the buried gate to a gate electrode which is formed on the same surface as the drain electrode. The discrete device according to the present technology can be used in co-packaging power management applications and the source electrode of the discrete device may be attached to the leadframe of the package. | 08-09-2012 |
20120199912 | COMPLEMENTARY STRESS LINER TO IMPROVE DGO/AVT DEVICES AND POLY AND DIFFUSION RESISTORS - Electron mobility and hole mobility is improved in long channel semiconductor devices and resistors by employing complementary stress liners. Embodiments include forming a long channel semiconductor device on a substrate, and forming a complementary stress liner on the semiconductor device. Embodiments include forming a resistor on a substrate, and tuning the resistance of the resistor by forming a complementary stress liner on the resistor. Compressive stress liners are employed for improving electron mobility in n-type devices, and tensile stress liners are employed for improving hole mobility in p-type devices. | 08-09-2012 |
20120223386 | Asymmetric FinFET devices - Asymmetric FET devices, and a method for fabricating such asymmetric devices on a fin structure is disclosed. The fabrication method includes disposing over the fin a high-k dielectric layer followed by a threshold- modifying layer, performing an ion bombardment at a tilted angle which removes the threshold-modifying layer over one of the fin's side-surfaces. The completed FET devices will be asymmetric due to the threshold-modifying layer being present only in one of two devices on the side of the fin. In an alternate embodiment further asymmetries are introduced, again using tilted ion implantation, resulting in differing gate-conductor materials for the two FinFET devices on each side of the fin. | 09-06-2012 |
20120292707 | NANO-ELECTRO-MECHANICAL SYSTEM (NEMS) STRUCTURES ON BULK SUBSTRATES - Semiconductor devices are formed with a nano-electro-mechanical system (NEMS) logic or memory on a bulk substrate. Embodiments include forming source/drain regions directly on a bulk substrate, forming a fin connecting the source/drain regions, forming two gates, one on each side of the fin, the two gates being insulated from the bulk substrate, and forming a substrate gate in the bulk substrate. The fin is separated from each of the two gates and the substrate gate with an air gap. | 11-22-2012 |
20120306017 | WIRING SWITCH DESIGNS BASED ON A FIELD EFFECT DEVICE FOR RECONFIGURABLE INTERCONNECT PATHS - An integrated circuit, including a substrate, at least one metal wiring layer disposed above the substrate. The metal wiring layer including a wiring switch and a plurality of patterned conductors. The wiring switch including a back gate field effect transistor (BGFET). | 12-06-2012 |
20120326236 | MULTI-GATE TRANSISTOR HAVING SIDEWALL CONTACTS - A multi-gate transistor having a plurality of sidewall contacts and a fabrication method that includes forming a semiconductor fin on a semiconductor substrate and etching a trench within the semiconductor fin, depositing an oxide material within the etched trench, and etching the oxide material to form a dummy oxide layer along exposed walls within the etched trench; and forming a spacer dielectric layer along vertical sidewalls of the dummy oxide layer. The method further includes removing exposed dummy oxide layer in a channel region in the semiconductor fin and beneath the spacer dielectric layer, forming a high-k material liner along sidewalls of the channel region in the semiconductor fin, forming a metal gate stack within the etched trench, and forming a plurality of sidewall contacts within the semiconductor fin along adjacent sidewalls of the dummy oxide layer. | 12-27-2012 |
20130001698 | METHOD TO MODIFY THE SHAPE OF A CAVITY USING ANGLED IMPLANTATION - A method of modifying a shape of a cavity in a substrate. The method includes forming one or more cavities on a surface of the substrate between adjacent relief structures. The method also includes directing ions toward the substrate at a non-normal angle of incidence, wherein the ions strike an upper portion of a cavity sidewall, and wherein the ions do not strike a lower portion of the cavity sidewall. The method further includes etching the one or more cavities wherein the upper portion of a cavity sidewall etches more slowly than the lower portion of the sidewall cavity. | 01-03-2013 |
20130009248 | INDEPENDENTLY ACCESSED DOUBLE-GATE AND TRI-GATE TRANSISTORS IN SAME PROCESS FLOW - A method for fabricating double-gate and tri-gate transistors in the same process flow is described. In one embodiment, a sacrificial layer is formed over stacks that include semiconductor bodies and insulative members. The sacrificial layer is planarized prior to forming gate-defining members. After forming the gate-defining members, remaining insulative member portions are removed from above the semiconductor body of the tri-gate device but not the I-gate device. This facilitates the formation of metallization on three sides of the tri-gate device, and the formation of independent gates for the I-gate device. | 01-10-2013 |
20130020647 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - Semiconductor devices are provided. The semiconductor device includes conductive patterns vertically stacked on a substrate to be spaced apart from each other, and pad patterns electrically connected to respective ones of the conductive patterns. Each of the pad patterns includes a flat portion extending from an end of the conductive pattern in a first direction parallel with the substrate and a landing sidewall portion upwardly extending from an end of the flat portion. A width of a portion of the landing sidewall portion in a second direction parallel with the substrate and perpendicular to the first direction is less than a width of the flat portion in the second direction. The related methods are also provided. | 01-24-2013 |
20130032883 | FABRICATION OF FIELD-EFFECT TRANSISTORS WITH ATOMIC LAYER DOPING - Field effect transistors fabricated using atomic layer doping processes are disclosed. In accordance with an embodiment of an atomic layer doping method, a semiconducting surface and a dopant gas mixture are prepared. Further, a dopant layer is grown on the semiconducting surface by applying the dopant gas mixture to the semiconducting surface under a pressure that is less than 500 Torr and a temperature that is between 300° C. and 750° C. The dopant layer includes at least 4×10 | 02-07-2013 |
20130056830 | Semiconductor Structure and Method - An embodiment is a semiconductor structure. The semiconductor structure comprises at least two gate structures on a substrate. The gate structures define a recess between the gate structures, and the recess is defined by a depth in a vertical direction. The depth is from a top surface of at least one of the gate structures to below a top surface of the substrate, and the depth extends in an isolation region in the substrate. The semiconductor structure further comprises a filler material in the recess. The filler material has a first thickness in the vertical direction. The semiconductor structure also comprises an inter-layer dielectric layer in the recess and over the filler material. The inter-layer dielectric layer has a second thickness in the vertical direction below the top surface of the at least one of the gate structures. The first thickness is greater than the second thickness. | 03-07-2013 |
20130087856 | Effective Work Function Modulation by Metal Thickness and Nitrogen Ratio for a Last Approach CMOS Gate - A CMOS structure is formed on a semiconductor substrate that includes first and second regions having an nFET and a pFET respectively formed thereon. Each nFET and pFET device is provided with a gate, a source and drain, and a channel formed on the substrate. A high permittivity dielectric layer formed on top of the channel is superimposed to the permittivity dielectric layer. The pFET gate includes a thick metal nitride alloy layer or rich metal nitride alloy or carbon metal nitride layer that provides a controlled WF. Superimposed to the permittivity dielectric layer, the nFET gate is provided with a thin metal nitride alloy layer, enabling to control the WF. A metal deposition is formed on top of the respective nitride layers. The gate last approach characterized by having a high thermal budget smaller than 500° C. used for post metal deposition, following the dopant activation anneal. | 04-11-2013 |
20130154010 | Integrated Circuit Device, System, and Method of Fabrication - A semiconductor device, comprising a first semiconductor portion having a first end, a second end, and a slit portion, wherein the width of the slit portion is less than the width of at least one of the first end and the second end; a second portion that is a different material than the first semiconductor portion, a third portion that is a different material than the first semiconductor portion, wherein the second and third portions are on opposite sides of the slit portion, and at least three terminals selected from a group consisting of a first terminal connected to the first end, a second terminal connected to the second end, a third terminal connected to the second portion, and a fourth terminal connected to the third portion. | 06-20-2013 |
20130207193 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device including a first insulation film including a first opening reaching a diffusion region of a transistor; a first barrier metal over the diffused region in the first opening; a first conduction layer formed over the first barrier metal in the first opening and formed of a first conductor; a second barrier metal formed over the first conduction layer in the first opening; a second conduction layer formed over the second barrier metal in the first opening and formed of a second conductor; a third barrier metal formed over the first gate electrode in the second opening; a fourth barrier metal formed in the second opening and contacting with the third barrier metal; and a third conduction layer formed of the second conductor contacting with the fourth barrier metal in the second opening. | 08-15-2013 |
20130214360 | METHOD AND APPARATUS FOR REDUCING FLICKER NOISE IN A SEMICONDUCTOR DEVICE - Some embodiments discussed relate to an integrated circuit and methods for making it. Certain examples can include a fin, a gate insulator over a sidewall of the fin, and a noise-reducing dopant at or near an interface of the gate insulator and the sidewall. | 08-22-2013 |
20130264649 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes a substrate including an active region and a field region, first gate structures disposed on the active region, first air gaps disposed between the first gate structures, second gate structures disposed on the field region, second air gaps disposed between the second gate structures, and an interlayer insulating layer disposed on the first gate structures, the first air gaps, the second gate structures, and the second air gaps. A lowermost level of the second air gaps is lower than a lowermost level of the first gate structures. | 10-10-2013 |
20130270643 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FABRICATING THE SAME - A three-dimensional (3D) semiconductor memory device includes an electrode separation pattern, a stack structure, a data storage layer, and a channel structure. The electrode separation pattern is disposed on a substrate. A stack structure is disposed on a sidewall of the electrode separation pattern. The stack structure includes a corrugated sidewall opposite to the sidewall of the electrode separation pattern. The sidewall of the electrode separation pattern is vertical to the substrate. A data storage layer is disposed on the corrugated sidewall. A channel structure is disposed on the charge storage layer. | 10-17-2013 |
20130285144 | DUAL POLYSILICON GATE OF A SEMICONDUCTOR DEVICE WITH A MULTI-PLANE CHANNEL - A dual polysilicon gate of a semiconductor device includes a substrate having a first region, a second region, and a third region, and a channel region with a protrusion structure formed in the substrate of the first region, a gate insulating layer formed over the substrate, a first polysilicon layer filling the channel region, and formed over the gate insulating layer of the first and second regions, a second polysilicon layer formed over the gate insulating layer of the third region, and an insulating layer doped with an impurity, and disposed inside the first polysilicon layer in the channel region. | 10-31-2013 |
20130285145 | FORMATION OF MULTI-HEIGHT MUGFET - A method and structure comprise a field effect transistor structure that includes a first rectangular fin structure and a second rectangular fin structure, both positioned on a substrate. The sides of the second rectangular fin structure are parallel to the sides of the first rectangular fin structure. Further, a trench insulator is positioned on the substrate and positioned between a side of the first rectangular fin structure and a side of the second rectangular fin structure. A gate conductor is positioned on the trench insulator, positioned over the sides and the top of the first rectangular fin structure, and positioned over the sides and the top of the second rectangular fin structure. The gate conductor runs perpendicular to the sides of the first rectangular fin structure and the sides of the second rectangular fin structure. Also, a gate insulator is positioned between the gate conductor and the first rectangular fin structure and between the gate conductor and the second rectangular fin structure. The gate conductor is positioned adjacent to a relatively larger portion of the sides of the second rectangular fin structure and is positioned adjacent to a relatively smaller portion of the sides of the first rectangular fin structure. | 10-31-2013 |
20130299909 | HYBRID PLASMA-SEMICONDUCTOR ELECTRONIC AND OPTICAL DEVICES - The invention provides combination semiconductor and plasma devices, including transistors and phototransistors. A preferred embodiment hybrid plasma semiconductor device has active solid state semiconductor regions; and a plasma generated in proximity to the active solid state semiconductor regions. Devices of the invention are referred to as hybrid plasma-semiconductor devices, in which a plasma, preferably a microplasma, cooperates with conventional solid state semiconductor device regions to influence or perform a semiconducting function, such as that provided by a transistor. The invention provides a family of hybrid plasma electronic/photonic devices having properties previously unavailable. In transistor devices of the invention, a low temperature, glow discharge is integral to the hybrid transistor. Example preferred devices include hybrid BJT and MOSFET devices. | 11-14-2013 |
20130307079 | ETCH RESISTANT BARRIER FOR REPLACEMENT GATE INTEGRATION - Semiconductor devices and methods of their fabrication are disclosed. One device includes a plurality of gates and a dielectric gap filling material with a pre-determined aspect ratio that is between the gates. The device further includes an etch resistant nitride layer that is configured to maintain the aspect ratio of the dielectric gap filling material during fabrication of the device and is disposed above the dielectric gap filling material and between the plurality of gates. | 11-21-2013 |
20130313646 | Structure and Method for Fabricating Fin Devices - A structure and method of forming a semiconductor device with a fin is provided. In an embodiment a hard mask is utilized to pattern a gate electrode layer and is then removed. After the hard mask has been removed, the gate electrode layer may be separated into individual gate electrodes. | 11-28-2013 |
20130320448 | SEMICONDUCTOR DEVICES HAVING THREE-DIMENSIONAL BODIES WITH MODULATED HEIGHTS - Semiconductor devices having three-dimensional bodies with modulated heights and methods to form such devices are described. For example, a semiconductor structure includes a first semiconductor device having a first semiconductor body disposed above a substrate. The first semiconductor body has a first height and an uppermost surface with a first horizontal plane. The semiconductor structure also includes a second semiconductor device having a second semiconductor body disposed above the substrate. The second semiconductor body has a second height and an uppermost surface with a second horizontal plane. The first and second horizontal planes are co-planar and the first and second heights are different. | 12-05-2013 |
20130334605 | MECHANISMS FOR FORMING ULTRA SHALLOW JUNCTION - A fin field-effect transistor (FinFET) includes a substrate and a fin structure over the substrate. The fin structure comprises a lightly doped source and drain (LDD) region uniformly beneath a top surface and sidewall surfaces of the fin structure, the LDD region having a depth less than about 25 nm. Another FinFET includes a substrate and a fin structure over the substrate. The fin structure comprises a lightly doped source and drain (LDD) region, and a top surface of the fin structure has a different crystal structure from a sidewall surface of the fin structure. A method of making a FinFET includes forming a fin structure on a substrate. The method further includes performing a pulsed plasma doping on the fin structure to form lightly doped drain (LDD) regions in the fin structure. | 12-19-2013 |
20140001556 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE | 01-02-2014 |
20140021551 | SEMICONDUCTOR DEVICES AND METHOD OF MANUFACTURING THE SAME - Disclosed are semiconductor devices and methods of manufacturing the same. The semiconductor device includes active portions defined in a semiconductor substrate, a device isolation pattern in a trench formed between the active portions, a gate electrode in a gate recess region crossing the active portions and the device isolation pattern, a gate dielectric layer between the gate electrode and an inner surface of the gate recess region, and a first ohmic pattern and a second ohmic pattern on each of the active portions at both sides of the gate electrode, respectively. The first and second ohmic patterns include a metal-semiconductor compound, and a top surface of the device isolation pattern at both sides of the gate recess region is recessed to be lower than a level of a top surface of the semiconductor substrate. | 01-23-2014 |
20140035040 | TUNNEL FIELD EFFECT TRANSISTOR - A TFET transistor includes an intrinsic channel, source and drain extension regions, source and drain conductive regions, a gate surmounting the channel and laid out such that an end of the channel is not covered by the gate. The transistor includes a first arrangement for forming an isolating space between the sides of the gate and the source conductive region including a first and a second dielectric spacer. The extension region has a thickness strictly greater than that of the channel such that the extension region has an increased thickness opposite the gate dielectric layer. The first face of the first spacer is in contact with the side of the gate followed by the side of the gate dielectric layer such that the first face covers the whole of the side of the layer. | 02-06-2014 |
20140035041 | TECHNIQUES AND CONFIGURATIONS FOR STACKING TRANSISTORS OF AN INTEGRATED CIRCUIT DEVICE - Embodiments of the present disclosure provide techniques and configurations for stacking transistors of a memory device. In one embodiment, an apparatus includes a semiconductor substrate, a plurality of fin structures formed on the semiconductor substrate, wherein an individual fin structure of the plurality of fin structures includes a first isolation layer disposed on the semiconductor substrate, a first channel layer disposed on the first isolation layer, a second isolation layer disposed on the first channel layer, and a second channel layer disposed on the second isolation layer, and a gate terminal capacitively coupled with the first channel layer to control flow of electrical current through the first channel layer for a first transistor and capacitively coupled with the second channel layer to control flow of electrical current through the second channel layer for a second transistor. Other embodiments may be described and/or claimed. | 02-06-2014 |
20140035042 | METHOD FOR MANUFACTURING A TRANSISTOR OF A SEMICONDUCTOR MEMORY DEVICE - A transistor of a semiconductor memory device including a semiconductor substrate having a plurality of active regions and a device isolation region, a plurality of first and second trench device isolation layers, which are arranged alternately with each other on the device isolation region of the semiconductor substrate, the first trench device isolation layers having a first thickness corresponding to a relatively high step height, and the second trench device isolation layers having a second thickness corresponding to a relatively low step height, a recess region formed in each of the active regions by a predetermined depth to have a stepped profile at a boundary portion thereof, the recess region having a height higher than that of the second trench device isolation layers to have an upwardly protruded portion between adjacent two second trench device isolation layers, a gate insulation layer, and a plurality of gate stacks formed on the gate insulation layer to overlap with the stepped profile of the respective active regions and the protruded portion of the relevant recess region. | 02-06-2014 |
20140035043 | FinFETs with Multiple Fin Heights - An integrated circuit structure includes a semiconductor substrate, and a FinFET over the semiconductor substrate. The FinFET includes a semiconductor fin; a gate dielectric on a top surface and sidewalls of the semiconductor fin; a gate electrode on the gate dielectric; and a source/drain region at an end of the semiconductor fin. A first pair of shallow trench isolation (STI) regions includes portions directly underlying portions of the source/drain regions, wherein the first pair of STI regions is separated by, and adjoining a semiconductor strip. The first pair of STI regions further has first top surfaces. A second pair of STI regions comprises portions directly underlying the gate electrode, wherein the second pair of STI regions is separated from each other by, and adjoining, the semiconductor strip. The second pair of STI regions has second top surfaces higher than the first top surfaces. | 02-06-2014 |
20140035044 | FIELD-EFFECT TRANSISTOR AND MANUFACTURING METHOD THEREOF - Disclosed are a field-effect transistor and a manufacturing method thereof. The disclosed field-effect transistor includes: a semiconductor substrate; a source ohmic metal layer formed on one side of the semiconductor substrate; a drain ohmic metal layer formed on another side of the semiconductor substrate; a gate electrode formed between the source ohmic metal layer and the drain ohmic metal layer, on an upper portion of the semiconductor substrate; an insulating film formed on the semiconductor substrate's upper portion including the source ohmic metal layer, the drain ohmic metal layer and the gate electrode; and a plurality of field electrodes formed on an upper portion of the insulating film, wherein the insulating film below the respective field electrodes has different thicknesses. | 02-06-2014 |
20140054709 | Transistor Devices, Memory Cells, And Arrays Of Memory Cells - A transistor device includes a pair of source/drain regions having a channel region there-between. A first gate is proximate the channel region. A gate dielectric is between the first gate and the channel region. A second gate is proximate the channel region. A programmable material is between the second gate and the channel region. The programmable material includes at least one of a) a multivalent metal oxide portion and an oxygen-containing dielectric portion, or b) a multivalent metal nitride portion and a nitrogen-containing dielectric portion. Memory cells and arrays of memory cells are disclosed. | 02-27-2014 |
20140061804 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Provided is a semiconductor device including active regions formed in a semiconductor substrate and arranged in a first direction parallel to a surface of the semiconductor substrate; a first element isolating region formed in the semiconductor substrate and electrically isolating adjacent active regions from each other; and gate electrodes extending over the active regions respectively and arranged in the first direction. The first element isolating region includes a first region extending in a second direction orthogonal to the first direction and a second region extending in a direction intersecting the first region, one gate electrode of adjacent gate electrodes has a first edge side which includes a first overlap part placed on the second region, and another gate electrode of the adjacent gate electrodes has a second edge side which faces the first edge side and includes a second overlap part placed on the second region. | 03-06-2014 |
20140077302 | POWER RECTIFYING DEVICES - According to a power rectifying device of embodiments of the inventive concept, a gate electrode, a source region, and a body region are connected in common to a first terminal, and a substrate beside the body region is connected to a second terminal. Thus, the power rectifying device having two terminals is realized. The gate electrode has s spacer-shape. Thus, a width of the gate electrode may be controlled to accurately control a channel length of a channel region of a transistor structure in the power rectifying device. | 03-20-2014 |
20140077303 | FIN TRANSISTOR AND SEMICONDUCTOR INTEGRATED CIRCUIT INCLUDING THE SAME - Provided are a fin transistor including a plurality of fins and a semiconductor integrated circuit including a plurality of fin transistors. A width of at least one fin of the plurality of fins is different from widths of the other fins, and each width of the plurality of fins is individually determined based on the electrical characteristics of the fin transistor. | 03-20-2014 |
20140097494 | METHOD FOR PRODUCING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method for producing a semiconductor device includes forming a fin-shaped silicon layer, a first insulating film around the fin-shaped silicon layer, a pillar-shaped silicon layer on the fin-shaped silicon layer, a gate electrode and a gate insulating film around the pillar-shaped silicon layer, a gate line connected to the gate electrode, a first diffusion layer in an upper portion of the pillar-shaped silicon layer, a second diffusion layer in a lower portion of the pillar-shaped silicon layer and an upper portion of the fin-shaped silicon layer, and a first silicide and a second silicide on the first diffusion layer and the second diffusion layer; an interlayer insulating film to expose an upper portion of the pillar-shaped silicon layer; etching the interlayer insulating film to form a contact hole; depositing a metal to form the first contact on the second silicide; and performing etching to form the metal wire. | 04-10-2014 |
20140097495 | APPARATUS AND METHODS FOR IMPROVING MULTI-GATE DEVICE PERFORMANCE - Embodiments of an apparatus and methods for improving multi-gate device performance are generally described herein. Other embodiments may be described and claimed. | 04-10-2014 |
20140103439 | Transistor Device and Method for Producing a Transistor Device - A transistor device includes at least one transistor cell. The at least one transistor cell includes a semiconductor fin, and a source region, a drain region, a drift region and a body region in the semiconductor fin. The body region is arranged adjacent the source region and the drift region in a first direction of the semiconductor fin. The source region is arranged adjacent the drift region in a second direction of the semiconductor fin and dielectrically insulated from the drift region by a dielectric layer. The drift region is arranged adjacent the drain region in the first direction and has a doping concentration lower than a doping concentration of the drain region. A gate electrode is adjacent the body region in a third direction of the semiconductor fin. | 04-17-2014 |
20140110786 | SEMICONDUCTOR DEVICE HAVING BURIED CHANNEL ARRAY - A semiconductor device includes a field regions in a substrate to define active regions, gate trenches including active trenches disposed across the active region and field trenches in the field regions, and word lines that fill the gate trenches and extend in a first direction. The word lines include active gate electrodes occupying the active trenches, and field gate electrodes occupying the field trenches. The bottom surface of each field gate electrode, which is disposed between active regions that are adjacent to each other and have one word line therebetween, is disposed at a higher level than the bottom surfaces of the active gate electrodes. | 04-24-2014 |
20140117453 | LOCAL INTERCONNECTS FOR FIELD EFFECT TRANSISTOR DEVICES - A multi-field effect transistor (FET) device includes a first FET device arranged on a substrate, the first FET device including a first active region and a second active region, a second FET device arranged on the substrate, the second FET device including a first active region and a second active region, and a first conductive interconnect electrically connecting the first active region of the first FET device to the first active region of the second FET device, the first conductive interconnect having a first cross sectional area proximate to the first active region of the first FET device that is greater than a second cross sectional area proximate to the first active region of the second FET device. | 05-01-2014 |
20140138774 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a base region of a second conduction type provided over a drain region of a first conduction type, an outer peripheral well region of a second conduction type provided to cover the outer peripheral end of the base region and having an impurity concentration lower than that of the base region, a buried electrode buried in the semiconductor substrate not to overlap the outer peripheral well region, plural gate electrodes connected to the buried electrode and buried in the substrate such that each of them is adjacent to a source region, a gate interconnect provided over the substrate to overlap a portion of the outer peripheral well region in a plan view and connected to the buried electrode, and a grounding electrode provided over the substrate and connected to a portion of the outer peripheral well region not overlapping the gate interconnect in a plan view. | 05-22-2014 |
20140145267 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING SAME - A semiconductor device and method of fabricating the semiconductor device are disclosed. The method includes forming a plurality of gate electrodes at a predetermined interval on a surface of a semiconductor substrate, forming spacers on sidewalls of the gate electrodes, depositing an interconnection layer conformally on the surface of the semiconductor substrate over the gate electrodes and the spacers, selectively etching the interconnection layer, wherein at least a portion of the interconnection layer that is formed on the surface of the semiconductor substrate and sidewalls of the spacers and located between adjacent gate electrodes remains after the selective etch, and forming an electrical contact on the etched interconnection layer located between the adjacent gate electrodes. | 05-29-2014 |
20140145268 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - A semiconductor device includes an insulating interlayer over a substrate in a first region, the insulating layer including contact holes exposing a portion of a surface of the substrate, and contact plugs in the contact holes. The contact plugs include a stacked structure of a first barrier metal layer pattern and a first metal layer pattern. The semiconductor device also includes second metal layer patterns directly contacting with the contact plugs and an upper surface of the insulating interlayer. The second metal layer pattern consists is a metal material layer. | 05-29-2014 |
20140151810 | SEMICONDUCTOR DEVICES INCLUDING PROTRUDING INSULATION PORTIONS BETWEEN ACTIVE FINS - A semiconductor device can include a field insulation layer including a planar major surface extending in first and second orthogonal directions and a protruding portion that protrudes a particular distance from the major surface relative to the first and second orthogonal directions. First and second multi-channel active fins can extend on the field insulation layer, and can be separated from one another by the protruding portion. A conductive layer can extend from an uppermost surface of the protruding portion to cross over the protruding portion between the first and second multi-channel active fins. | 06-05-2014 |
20140175553 | MOS SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a MOS semiconductor device comprises a first gate insulating film formed on a region of part of a channel of a semiconductor substrate, in which a transistor is to be formed, a first gate electrode formed on the first gate insulating film, a second gate insulating film formed on remaining part of the channel, the second gate insulating film including an impurity added to the second gate insulating film to increase a threshold value of the channel immediately under the second gate insulating film, and a second gate electrode formed on the second gate insulating film. | 06-26-2014 |
20140183640 | GATELESS FINFET - A finFET includes a semiconductor fin formed on a base. The fin further includes a body area between a first vertical surface and a second vertical surface. The finFET includes a first contact adjacent to the first vertical surface of the body area. The first vertical surface is spaced away from the first contact by a first dielectric thickness. Also included is a second contact adjacent to the second vertical surface of the body area. The second vertical surface is spaced away from the second contact by a second dielectric thickness. The first dielectric thickness and second dielectric thickness are configured to allow the first contact and second contact to modulate the body area of the fin. | 07-03-2014 |
20140183641 | HIGH EFFICIENCY FINFET DIODE - Disclosed are a FinFET diode of high efficiency, designed to resolve the degradation problem with a conventional FinFET diode arising from reduced active area, and a method of fabrication. The FinFET diode has a doped substrate, two spaced-apart groups of substantially parallel, equally-spaced, elongated semiconductor fin structures, dielectric layers formed between the two groups and among the fin structures for insulation, a plurality of substantially equal-spaced and parallel elongated gate structures perpendicularly traversing both groups of the fin structures, and two groups of semiconductor strips respectively formed lengthwise upon the two groups of the fin structures. The two groups of semiconductor strips are doped to have opposite conductivity types, p-type and n-type. The FinFET diode further has metal contacts formed upon the semiconductor strips. In an embodiment, the semiconductor strips may be integrally formed with the fin structures by epitaxial growth and in-situ doped. | 07-03-2014 |
20140197492 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD - Semiconductor devices and fabrication methods are provided. In an exemplary method, a semiconductor layer including a first opening can be provided. The first opening can be filled with a stress material. The stress material can then be etched to form a second opening having a width less than a width of the first opening to leave a stress material layer in the semiconductor layer and on each sidewall of the second opening. The semiconductor layer can be etched to form a fin structure on a sidewall surface of the stress material layer. A main gate structure can be formed on the sidewall surface of the fin structure. A back gate structure can be formed on the sidewall surface of the stress material layer. | 07-17-2014 |
20140203369 | FIN FIELD-EFFECT TRANSISTORS AND FABRICATION METHOD THEREOF - A method is provided for fabricating a fin field-effect transistor. The method includes providing a semiconductor substrate, and forming a plurality of fins with hard mask layers and an isolation structure. The process also includes forming a first dummy gate layer on the fins and the isolation structure, and polishing the first dummy gate layer until the hard mask layer is exposed. Further, the method includes removing the hard mask layer to expose a top surface of the fins, and forming a second dummy gate material layer on the first dummy gate material layer. Further, the method also includes etching the second dummy gate layer and the first dummy gate layer to form a dummy gate on each of the fins. | 07-24-2014 |
20140203370 | Semiconductor Device and Fabricating Method Thereof - A semiconductor device is provided. The semiconductor device includes a first fin on a substrate, a first gate electrode formed on the substrate to intersect the first fin, a first elevated source/drain on the first fin on both sides of the first gate electrode, and a first metal alloy layer on an upper surface and sidewall of the first elevated source/drain. | 07-24-2014 |
20140210009 | HIGH VOLTAGE FINFET STRUCTURE - Methods for forming FIN-shaped field effect transistors (FINFETs) capable of withstanding high voltage applications and the resulting devices are disclosed. Embodiments include forming a source and a drain on a substrate, forming a thin body (FIN) on the substrate and connecting the source and the drain, forming a gate over top and side surfaces of a first part of the FIN, thereby defining a drain-side FIN region of the FIN between the gate and the drain, and forming a shielding region over top and side surfaces of a second part of the FIN in the drain-side FIN region. | 07-31-2014 |
20140239401 | SILICON NITRIDE GATE ENCAPSULATION BY IMPLANTATION - A FinFET structure which includes: silicon fins on a semiconductor substrate, each silicon fin having two sides and a horizontal surface; a gate wrapping around at least one of the silicon fins, the gate having a first surface and an opposing second surface facing the at least one of the silicon fins; a hard mask on a top surface of the gate; a silicon nitride layer formed in each of the first and second surfaces so as to be below and in direct contact with the hard mask on the top surface of the gate; spacers on the gate and in contact with the silicon nitride layer; and epitaxially deposited silicon on the at least one of the silicon fins so as to form a raised source/drain. | 08-28-2014 |
20140252485 | Low-Cost CMOS Structure with Dual Gate Dielectrics and Method of Forming the CMOS Structure - Impurity atoms of a first type are implanted through a gate and a thin gate dielectric into a channel region that has substantially only the first type of impurity atoms at a middle point of the channel region to increase the average dopant concentration of the first type of impurity atoms in the channel region to adjust the threshold voltage of a transistor. | 09-11-2014 |
20140252486 | Fin Shape For Fin Field-Effect Transistors And Method Of Forming - A fin field-effect transistor (finFET) and a method of forming are provided. A gate electrode is formed over one or more fins. Notches are formed in the ends of the gate electrode along a base of the gate electrode. Optionally, an underlying dielectric layer, such as a shallow trench isolation, may be recessed under the notch, thereby reducing gap fill issues. | 09-11-2014 |
20140264607 | III-V FINFETS ON SILICON SUBSTRATE - A method for forming fin field effect transistors includes forming a dielectric layer on a silicon substrate, forming high aspect ratio trenches in the dielectric layer down to the substrate, the high aspect ratio including a height to width ratio of greater than about 1:1 and epitaxially growing a non-silicon containing semiconductor material in the trenches using an aspect ratio trapping process to form fins. The one or more dielectric layers are etched to expose a portion of the fins. A barrier layer is epitaxially grown on the portion of the fins, and a gate stack is formed over the fins. A spacer is formed around the portion of the fins and the gate stack. Dopants are implanted into the portion of the fins. Source and drain regions are grown over the fins using a non-silicon containing semiconductor material. | 09-18-2014 |
20140264608 | DITCHES NEAR SEMICONDUCTOR FINS AND METHODS FOR FORMING THE SAME - A device includes a semiconductor substrate, and isolation regions extending into the semiconductor substrate. A semiconductor strip is between and contacting the isolation regions. A semiconductor fin overlaps, and is joined to, the semiconductor strip. A ditch extends from a top surface of the isolation regions into the isolation regions, wherein the ditch adjoins the semiconductor fin. | 09-18-2014 |
20140291766 | PLANAR DEVICE ON FIN-BASED TRANSISTOR ARCHITECTURE - Techniques are disclosed for forming a planar-like transistor device on a fin-based field-effect transistor (finFET) architecture during a finFET fabrication process flow. In some embodiments, the planar-like transistor can include, for example, a semiconductor layer which is grown to locally merge/bridge a plurality of adjacent fins of the finFET architecture and subsequently planarized to provide a high-quality planar surface on which the planar-like transistor can be formed. In some instances, the semiconductor merging layer can be a bridged-epi growth, for example, comprising epitaxial silicon. In some embodiments, such a planar-like device may assist, for example, with analog, high-voltage, wide-Z transistor fabrication. Also, provision of such a planar-like device during a finFET flow may allow for the formation of transistor devices, for example, exhibiting lower capacitance, wider Z, and/or fewer high electric field locations for improved high-voltage reliability, which may make such devices favorable for analog design, in some instances. | 10-02-2014 |
20140319614 | FINFET CHANNEL STRESS USING TUNGSTEN CONTACTS IN RAISED EPITAXIAL SOURCE AND DRAIN - Performance of a FinFET is enhanced through a structure that exerts physical stress on the channel. The stress is achieved by a combination of tungsten contacts for the source and drain, epitaxially grown raised source and raised drain, and manipulation of aspects of the tungsten contact deposition resulting in enhancement of the inherent stress of tungsten. The stress can further be enhanced by epitaxially re-growing the portion of the raised source and drain removed by etching trenches for the contacts and/or etching deeper trenches (and corresponding longer contacts) below a surface of the fin. | 10-30-2014 |
20140319615 | FINFET WITH ACTIVE REGION SHAPED STRUCTURES AND CHANNEL SEPARATION - A semiconductor structure in fabrication includes a n-FinFET and p-FinFET. Stress inducing materials such as silicon and silicon germanium are epitaxially grown into naturally diamond-shaped structures atop the silicon fins of the n-FinFET and p-FinFET areas. The diamond structures act as the source, drain and channel between the source and drain. The diamond structures of the channel are selectively separated from the fin while retaining the fin connections of the diamond-shaped growth of the source and the drain. Further fabrication to complete the structure may then proceed. | 10-30-2014 |
20140327080 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - The present invention provides a manufacturing method of a semiconductor structure, comprising the following steps. First, a substrate is provided, a first dielectric layer is formed on the substrate, a metal gate is disposed in the first dielectric layer and at least one source/drain region (S/D region) is disposed on two sides of the metal gate, a second dielectric layer is then formed on the first dielectric layer, a first etching process is then performed to form a plurality of first trenches in the first dielectric layer and the second dielectric layer, wherein the first trenches expose each S/D region. Afterwards, a salicide process is performed to form a salicide layer in each first trench, a second etching process is then performed to form a plurality of second trenches in the first dielectric layer and the second dielectric layer, and the second trenches expose the metal gate. | 11-06-2014 |
20140332892 | STRINGER-FREE GATE ELECTRODE FOR A SUSPENDED SEMICONDUCTOR FIN - At least one semiconductor fin is formed over an insulator layer. Portions of the insulator layer are etched from underneath the at least one semiconductor fin. The amount of the etched portions of the insulator is selected such that a metallic gate electrode layer fills the entire gap between the recessed surfaces of the insulator layer and the bottom surface(s) of the at least one semiconductor fin. An interface between the metallic gate electrode layer and a semiconductor gate electrode layer contiguously extends over the at least one semiconductor fin and does not underlie any of the at least one semiconductor fin. During patterning of a gate electrode, removal of the semiconductor material in the semiconductor gate electrode layer can be facilitated because the semiconductor gate electrode layer is not present under the at least one semiconductor fin. | 11-13-2014 |
20140346604 | THIN FILM TRANSISTOR, DISPLAY APPARATUS INCLUDING THE THIN FILM TRANSISTOR, AND METHOD OF MANUFACTURING THE THIN FILM TRANSISTOR - A thin film transistor includes: a substrate, a semiconductor layer disposed on the substrate, a first gate electrode and a second gate electrode disposed on the semiconductor layer, a gate insulating layer disposed between the semiconductor layer and the first and second gate electrodes and having a first through hole between the first and second gate electrodes and a capping layer covering the first gate electrode and contacting the semiconductor layer via the first through hole. The capping layer includes a conductive material. | 11-27-2014 |
20140361373 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device includes a fin structure, an isolation structure, a gate structure and an epitaxial structure. The fin structure protrudes from the surface of the substrate and includes a top surface and two sidewalls. The isolation structure surrounds the fin structure. The gate structure overlays the top surface and the two sidewalls of a portion of the fin structure, and covers a portion of the isolation structure. The isolation structure under the gate structure has a first top surface and the isolation structure at two sides of the gate structure has a second top surface, wherein the first top surface is higher than the second top surface. The epitaxial layer is disposed at one side of the gate structure and is in direct contact with the fin structure. | 12-11-2014 |
20140374830 | SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF - A semiconductor device includes a fin region with long and short sides, a first field insulating layer including a top surface lower than that of the fin region and adjacent to a side surface of the short side of the fin region, a second field insulating layer including a top surface lower than that of the fin region and adjacent to a side surface of the long side of the fin region, an etch barrier pattern on the first field insulating layer, a first gate on the fin region and the second field insulating layer to face a top surface of the fin region and side surfaces of the long sides of the fin region. A second gate is on the etch barrier pattern overlapping the first field insulating layer. A source/drain region is between the first gate and the second gate, in contact with the etch barrier pattern. | 12-25-2014 |
20150035061 | Semiconductor Device and Method for Fabricating the Same - Provided are a multi-gate transistor device and a method for fabricating the same. The method for fabricating the multi-gate transistor device includes forming first and second fins shaped to protrude on a substrate and aligned and extending in a first direction and a trench separating the first and second fins from each other in the first direction between the first and second fins, performing ion implantation of impurities on sidewalls of the trench, forming a field dielectric film filling the trench, forming a recess in the first fin not exposing the field dielectric film, and growing an epitaxial layer in the recess. | 02-05-2015 |
20150076606 | SEMICONDUCTOR DEVICE WITH LOW-K SPACER - A semiconductor device includes gates and a low-k spacer. The low-k spacer includes low-k spacer portions formed upon the gate sidewalls and a low-k spacer portion formed upon a top surface of an underlying substrate adjacent to the gates. When a structure has previously undergone a gate processing fabrication stage, the gates and at least a portion of the top surface of the substrate may be exposed thereby allowing the formation of the low-k spacer. This exposure may include removing any original gate spacers, removing an original liner formed upon the original spacers, and removing any original fill material formed upon the liner. | 03-19-2015 |
20150076607 | FIN FIELD EFFECT TRANSISTOR WITH MERGED METAL SEMICONDUCTOR ALLOY REGIONS - Raised active regions having faceted semiconductor surfaces are formed on semiconductor fins by selective epitaxy such that the raised active regions are not merged among one another, but are proximal to one another by a distance less than a thickness of a metal semiconductor alloy region to be subsequently formed. A contiguous metal semiconductor alloy region is formed by depositing and reacting a metallic material with the semiconductor material of raised active regions. The contiguous metal semiconductor alloy region is in contact with angled surfaces of the plurality of raised active regions, and can provide a greater contact area and lower parasitic contact resistance than a semiconductor structure including merged semiconductor fins of comparable sizes. Merged fins enable smaller, and/or fewer, contact via structures than a total number of raised active regions can be employed to reduce parasitic capacitance between a gate electrode and the contact via structures. | 03-19-2015 |
20150076608 | DUAL EPITAXY REGION INTEGRATION - A semiconductor device includes a first device region and second device region of opposite polarity. Each device region includes at least a transistor device and associated epitaxy. A high-k barrier is formed to overlay the first device region epitaxy only. The high-k barrier may include a substantially horizontal portion formed upon a top surface of the first device region epitaxy and a substantially vertical portion formed upon an outer surface of the first device region epitaxy. The substantially vertical portion may partially isolate the first device region from the second device region | 03-19-2015 |
20150076609 | METHODS OF FORMING STRESSED LAYERS ON FINFET SEMICONDUCTOR DEVICES AND THE RESULTING DEVICES - One method includes forming a raised isolation structure with a recess above a substrate, forming a gate structure above the fin, forming a plurality of spaced-apart buried fin contact structures within the recess and forming a stress-inducing material layer above the buried fin contact structures. One device includes a plurality of spaced-apart buried fin contact structures positioned within a recess in a raised isolation structure on opposite sides of a gate structure, a stress-inducing material layer formed above the buried fin contact structures and a source/drain contact that extends through the stress-inducing material layer. | 03-19-2015 |
20150076610 | Field Effect Transistor Structure Having One or More Fins - A field effect transistor (FET) having one or more fins provides an extended current path as compared to conventional finFETs. A raised source terminal is disposed on a fin adjacent to a sidewall spacer of a gate structure. The drain terminal and a first portion of the gate structure overlie a first well of a first conductivity type. A raised drain terminal is disposed such that it is spaced apart from the gate structure sidewalls. In some embodiments the drain terminal is disposed on a second, separate fin. the drain terminal and a second portion of the gate structure overlie a second well of a second conductivity type. | 03-19-2015 |
20150091091 | JUNCTION-LESS TRANSISTORS AND FABRICATION METHOD THEREOF - A method is provided for fabricating a junction-less transistor. The method includes providing a semiconductor substrate having a dielectric layer; and forming a semiconductor layer including a first heavily doped layer formed on the dielectric layer, a lightly doped layer formed on the first heavily doped layer and a second heavily doped layer formed on the lightly doped layer. The method also includes etching the semiconductor layer and the dielectric layer to form trenches to expose side surfaces of a portion of the semiconductor layer and a portion of the dielectric layer; and removing the portion of the dielectric layer between the adjacent trenches to form a chamber. Further, the method includes forming a gate structure around the portion of the semiconductor layer between the adjacent trenches; and forming a source region and a drain region in the semiconductor layer at both sides of the gate structure. | 04-02-2015 |
20150102413 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device including a substrate with a plurality of logic cells, transistors provided in the plurality of logic cells, contact plugs connected to electrodes of the transistors, first via plugs in contact with top surfaces of the contact plugs, and first wires in contact with top surfaces of the first via plugs. The first wires may include a common conductive line connected to the plurality of logic cells through the contact plugs, and all of the first wires may be shaped like a straight line extending parallel to a specific direction. | 04-16-2015 |
20150303273 | PATTERNING MULTIPLE, DENSE FEATURES IN A SEMICONDUCTOR DEVICE USING A MEMORIZATION LAYER - Provided are approaches for patterning multiple, dense features in a semiconductor device using a memorization layer. Specifically, an approach includes: patterning a plurality of openings in a memorization layer; forming a gap-fill material within each of the plurality of openings; removing the memorization layer; removing an etch stop layer adjacent the gap-fill material, wherein a portion of the etch stop layer remains beneath the gap-fill material; etching a hardmask to form a set of openings above the set of gate structures, wherein the etch to the hardmask also removes the gap-fill material from atop the remaining portion of the etch stop layer; and etching the semiconductor device to remove the hardmask within each of the set of openings. In one embodiment, a set of dummy S/D contact pillars is then formed over a set of fins of the semiconductor device by etching a dielectric layer selective to the gate structures. | 10-22-2015 |
20150318367 | Controlling Gate Formation for High Density Cell Layout - Methods of forming a semiconductor structure and the semiconductor structure are disclosed. In one embodiment, a semiconductor structure includes a substrate having a first active region, a second active region, and an insulating region separating the first and the second active regions. The structure further includes a vertical gate structure extending over the first and the second active regions and the insulating region, and a horizontal gate structure extending over the insulating region between the first and the second active regions. | 11-05-2015 |
20150325692 | FIN FIELD EFFECT TRANSISTOR (FINFET) DEVICE INCLUDING A SET OF MERGED FINS FORMED ADJACENT A SET OF UNMERGED FINS - Approaches for simultaneously providing a set of merged and unmerged fins in a fin field effect transistor device (FinFET) are disclosed. In at least one approach, the FinFET device includes: a set of merged fins and a set of unmerged fins formed from a substrate, the set of unmerged fins adjacent the set of merged fins; and a planar block formed from the substrate, the planar block adjacent one of: the set of merged fins, and the set of unmerged fins. The FinFET device further includes an epitaxial material over each of the set of merged fins and each of the set of unmerged fins, wherein the epitaxial material merges together over the set of merged fins and remains unmerged over the set of unmerged fins. In at least one approach, the set of merged fins and the set of unmerged fins is formed using a sidewall image transfer process. | 11-12-2015 |
20150340501 | FORMING INDEPENDENT-GATE FINFET WITH TILTED PRE-AMORPHIZATION IMPLANTATION AND RESULTING DEVICE - Methods for producing independent-gate FinFETs with improved channel mobility and the resulting devices are disclosed. Embodiments may include forming an independent-gate fin field-effect transistor (FinFET) above a substrate; and forming stress within the fin between two independent gates of the independent-gate FinFET. | 11-26-2015 |
20150364605 | SEMICONDUCTOR ARRANGEMENTS AND METHODS OF MANUFACTURING THE SAME - A semiconductor arrangement that includes: a substrate; a back gate formed on the substrate; fins formed on opposite sides of the back gate; and back gate dielectric layers interposed between the back gate and the respective fins. The back gate has opposite end portions recessed with respect to a middle portion thereof between the end portions, so that an overlap area between each of the end portions and each of the fins is smaller than an overlap area between the middle portion and the fin. | 12-17-2015 |
20150380567 | THIN FILM TRANSISTOR OF DISPLAY APPARATUS - Disclosed is a thin film transistor (TFT) of a display apparatus which reduces a leakage current caused by a hump and decreases screen defects. The TFT includes an active layer and a first gate electrode with a gate insulator therebetween, and a source electrode and a drain electrode respectively disposed at both ends of the active layer. The gate electrode branches as a plurality of lines and overlaps the active layer. The active layer includes one or more channel areas between the source electrode and the drain electrode, one or more dummy areas, and a plurality of link areas between the one or more channel areas to connect the one or more channel areas in one pattern. A length of each of the one or more dummy areas extends from an edge of a corresponding channel area. | 12-31-2015 |
20160020318 | Semiconductor Device and Method for Fabricating the Same - Provided are a semiconductor device and a method for fabricating the same. The method for fabricating a semiconductor device comprises, providing an active fin and a field insulating film including a first trench disposed on the active fin; forming a second trench through performing first etching of the field insulating film that is disposed on side walls and a lower portion of the first trench; forming a first region and a second region in the field insulating film through performing second etching of the field insulating film that is disposed on side walls and a lower portion of the second trench, the first region is disposed adjacent to the active fin and has a first thickness, and the second region is disposed spaced apart from the active fin as compared with the first region and has a second thickness that is thicker than the first thickness; and forming a gate structure on the active fin and the field insulating film. | 01-21-2016 |
20160027911 | A Radiation-Hardened-by-Design (RHBD) Multi-Gate Device and a Fabrication Method Thereof - The present invention discloses a radiation-hardened-by-design (RHBD) multi-gate device and a fabrication method thereof. The multi-gate device of the present invention includes a substrate; a source region and a drain region, which are on the substrate; a protruding fin structure and a field dielectric layer between the source region and the drain region on the substrate; a gate dielectric and a gate electrode on the fin structure and the dielectric layer; and two isolation layers separated to each other, which are disposed in the drain region between the adjacent two fins, wherein an interlayer is sandwiched between the two isolation layers. The interlayer has a doping type which is opposite to that of the substrate so that a shunt PN junction is formed between the interlayer and the substrate, and the shunt PN junction has an electrode not connected to the drain so that a part of the charges collected by the shunt PN junction are not output to the drain and are ultimately guided out of the multi-gate devices, thereby weakening the influence of the single-event effect. In comparison with a multi-gate device of prior art, the multi-gate device of the present invention may effectively suppress the sensitivity of the device to single event irradiation in the event that the layout areas of the two types of devices are almost same. | 01-28-2016 |
20160035887 | SEMICONDUCTOR DEVICE AND MULTIPLE GATE FIELD EFFECT TRANSISTOR - The present invention provides a semiconductor device, which includes a substrate, a first gate electrode, a second gate electrode, a source region and a drain region, wherein the first gate electrode and the second gate electrode are embedded in the substrate respectively; the source region is formed in the substrate, and at least a portion of the source region is disposed between the first gate electrode and the second gate electrode; and the drain region is formed in the substrate, and at least a portion of the drain region is disposed between the first gate electrode and the second gate electrode. | 02-04-2016 |
20160043075 | RAISED METAL SEMICONDUCTOR ALLOY FOR SELF-ALIGNED MIDDLE-OF-LINE CONTACT - A method to form self-aligned middle-of-line (MOL) contacts between functional gate structures without the need of lithographic patterning and etching by using raised metal semiconductor alloy regions is provided. Raised metal semiconductor alloy regions are formed by reacting a metal layer with a semiconductor material in raised semiconductor material regions formed on portions of at least one active region of a substrate located between functional gate structures. The metal layer includes a metal capable of forming a metal semiconductor alloy with a large volume expansion such that the resulting metal semiconductor alloy regions can be raised to a same height as that of the functional gate structures. As a result, no lithographic patterning and etching between functional gate structures are needed when forming MOL contacts to these raised metal semiconductor alloy regions. | 02-11-2016 |
20160056294 | EPITAXIAL GROWTH OF SILICON FOR FINFETS WITH NON-RECTANGULAR CROSS-SECTIONS - FinFET devices with epitaxially grown fins and methods for fabricating them are provided. Embodiments include forming at least two shallow trench isolation (STI) regions, filled with dielectric material, adjacent to but separate from each other in a silicon substrate; epitaxially growing a silicon-based layer between each adjacent pair of STI regions to form a fin with a non-rectangular cross-section extending from each STI region to each adjacent STI region; forming a gate oxide over and perpendicular to each fin; and forming a gate electrode over the gate oxide to form a FinFET. | 02-25-2016 |
20160064545 | TECHNIQUES AND CONFIGURATIONS FOR STACKING TRANSISTORS OF AN INTEGRATED CIRCUIT DEVICE - Embodiments of the present disclosure provide techniques and configurations for stacking transistors of a memory device. In one embodiment, an apparatus includes a semiconductor substrate, a plurality of fin structures formed on the semiconductor substrate, wherein an individual fin structure of the plurality of fin structures includes a first isolation layer disposed on the semiconductor substrate, a first channel layer disposed on the first isolation layer, a second isolation layer disposed on the first channel layer, and a second channel layer disposed on the second isolation layer, and a gate terminal capacitively coupled with the first channel layer to control flow of electrical current through the first channel layer for a first transistor and capacitively coupled with the second channel layer to control flow of electrical current through the second channel layer for a second transistor. Other embodiments may be described and/or claimed. | 03-03-2016 |
20160093621 | MEMORY DEVICES INCLUDING ONE-TIME PROGRAMMABLE MEMORY CELLS - A memory device including one-time programmable memory cells has a semiconductor substrate with a write region and a read region, a write gate provided on the write region, a read gate provided on the read region, first and second junction patterns provided at both sides of the read gate, and insulating dielectric patterns interposed between the write and read gates and the semiconductor substrate. The read region may have a different conductivity type from the first and second junction patterns, and the write region may have the same conductivity type as the first and second junction patterns. | 03-31-2016 |
20160111497 | High-Voltage Normally-Off Field Effect Transistor With Channel Having Multiple Adjacent Sections - A device having a channel with multiple voltage thresholds is provided. The channel can include a first section located adjacent to a source electrode, which is a normally-off channel and a second section located between the first section and a drain electrode, which is a normally-on channel. The device can include a charge-controlling electrode connected to the source electrode, which extends from the source electrode over at least a portion of the second section of the channel. During operation of the device, a potential difference between the charge-controlling electrode and the channel can control the on/off state of the normally-on section of the channel. | 04-21-2016 |
20160118496 | SEMICONDUCTOR STRUCTURES WITH FIELD EFFECT TRANSISTOR(S) HAVING LOW-RESISTANCE SOURCE/DRAIN CONTACT(S) - Disclosed are semiconductor structures comprising a field effect transistor (FET) having a low-resistance source/drain contact and, optionally, low gate-to-source/drain contact capacitance. The structures comprise a semiconductor body and, contained therein, first and second source/drain regions and a channel region. A first gate is adjacent to the semiconductor body at the channel region and a second, non-functioning, gate is adjacent to the semiconductor body such that the second source/drain region is between the first and second gates. First and second source/drain contacts are on the first and source/drain regions, respectively. The second source/drain contact is wider than the first and, thus, has a lower resistance. Additionally, spacing of the first and second source/drain contacts relative to the first gate can be such that the first gate-to-second source/drain contact capacitance is equal to or less than the first gate-to-first source/drain contact capacitance. Also disclosed are associated formation methods. | 04-28-2016 |
20160133730 | JUNCTIONLESS TUNNEL FET WITH METAL-INSULATOR TRANSITION MATERIAL - Embodiments of the present disclosure provide an integrated circuit (IC) structure, which can include: a doped semiconductor layer having a substantially uniform doping profile; a first gate structure positioned on the doped semiconductor layer; and a second gate structure positioned on the doped semiconductor layer, the second gate structure including a metal-insulator transition material and a gate dielectric layer separating the metal-insulator transition material from the doped semiconductor layer. | 05-12-2016 |
20160141417 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes an active fin formed to extend in a first direction, a gate formed on the active fin and extending in a second direction crossing the first direction, a source/drain formed on upper portions of the active fin and disposed at one side of the gate, an interlayer insulation layer covering the gate and the source/drain, a source/drain contact passing through the interlayer insulation layer to be connected to the source/drain and including a first contact region and a second contact region positioned between the source/drain and the first contact region, and a spacer layer formed between the first contact region and the interlayer insulation layer. A width of the second contact region in the first direction is greater than the sum of a width of the first contact region in the first direction and a width of the spacer layer in the first direction. | 05-19-2016 |
20160149035 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING SAME - A semiconductor device and method of fabricating the semiconductor device are disclosed. The method includes forming a plurality of gate electrodes at a predetermined interval on a surface of a semiconductor substrate, forming spacers on sidewalls of the gate electrodes, depositing an interconnection layer conformally on the surface of the semiconductor substrate over the gate electrodes and the spacers, selectively etching the interconnection layer, wherein at least a portion of the interconnection layer that is formed on the surface of the semiconductor substrate and sidewalls of the spacers and located between adjacent gate electrodes remains after the selective etch, and forming an electrical contact on the etched interconnection layer located between the adjacent gate electrodes. | 05-26-2016 |
20160155843 | MULTI-THRESHOLD VOLTAGE DEVICES AND ASSOCIATED TECHNIQUES AND CONFIGURATIONS | 06-02-2016 |
20160190314 | VERTICAL SLIT TRANSISTOR WITH OPTIMIZED AC PERFORMANCE - A vertical slit transistor includes raised source, drain, and channel regions in a semiconductor substrate. Two gate electrodes are positioned adjacent respective sidewalls of the semiconductor substrate. A dielectric material separates the gate electrodes from the source and drain regions. | 06-30-2016 |
20190148489 | SEMICONDUCTOR DEVICE | 05-16-2019 |
20190148522 | SEMICONDUCTOR DEVICE STRUCTURE WITH BARRIER LAYER AND METHOD FOR FORMING THE SAME | 05-16-2019 |
20190148556 | SEMICONDUCTOR STRUCTURE WITH SOURCE/DRAIN MULTI-LAYER STRUCTURE AND METHOD FOR FORMING THE SAME | 05-16-2019 |
20220140131 | TRANSISTOR WITH PHASE TRANSITION MATERIAL REGION BETWEEN CHANNEL REGION AND EACH SOURCE/DRAIN REGION - A transistor includes a semiconductor substrate, a first source/drain region and a second source/drain region in the semiconductor substrate with a channel region between the source/drain regions, and a gate over the channel region. In addition, the transistor includes a first phase transition material (PTM) region between the first source/drain region and the channel region, and a second PTM region between the second source/drain region and the channel region. The PTM regions provide the transistor with improved off-state current (I | 05-05-2022 |