Class / Patent application number | Description | Number of patent applications / Date published |
257363000 | Including resistor element | 8 |
20090050971 | High voltage durability transistor and method for fabricating same - According to one exemplary embodiment, a method for fabricating a high voltage durability transistor comprises forming a gate over a gate oxide layer formed over a substrate, aligning an exposure mask with the gate, and selectively blocking exposure of the gate during gate implant doping, by exposure shields formed in the exposure mask, thereby producing the high voltage durability transistor. In one embodiment, an exemplary high voltage durability transistor comprises a gate formed over a gate oxide layer, the gate oxide layer being situated over a semiconductor substrate, where the gate has a reduced doping implant due to selective implant blocking provided by exposure shields formed in an exposure mask. The selective implant blocking results in an enhanced dielectric barrier so as to produce a high voltage durability transistor. The enhanced dielectric barrier has a depletion region with an increased thickness. | 02-26-2009 |
20090230477 | Resettable short-circuit protection configuration - A resettable short circuit protection configuration includes a power input terminal, a power output terminal, a first electrically controlled switch, which has a control end and two conducting ends, the two conducting ends being respectively electrically connected to the power input terminal and the power output terminal, a second electrically controlled switch, which has a control end and two conducting ends, the two conducting ends being respectively electrically connected to the power input terminal and the control end of the first electrically controlled switch, a first resistor, which has two opposite ends respectively electrically connected to the control end of the first electrically controlled switch and a grounding terminal, and a second resistor, which has two opposite ends respectively electrically connected to the control end of the second electrically controlled switch and the power output terminal. | 09-17-2009 |
20110303982 | Resistive Device for High-K Metal Gate Technology and Method of Making the Same - A semiconductor device is provided which includes a semiconductor substrate, an isolation structure formed in the substrate for isolating an active region of the substrate, the isolation structure being formed of a first material, an active device formed in the active region of the substrate, the active device having a high-k dielectric and metal gate, and a passive device formed in the isolation structure, the passive device being formed of a second material different from the first material and having a predefined resistivity. | 12-15-2011 |
20120132995 | STACKED AND TUNABLE POWER FUSE - The present disclosure provides a semiconductor device that includes a transistor including a substrate, a source, a drain, and a gate, and a fuse stacked over the transistor. The fuse includes an anode contact coupled to the drain of the transistor, a cathode contact, and a resistor coupled to the cathode contact and the anode contact via a first Schottky diode and a second Schottky diode, respectively. A method of fabricating such semiconductor devices is also provided. | 05-31-2012 |
20140054708 | Stacked and Tunable Power Fuse - The present disclosure provides a semiconductor device that includes a transistor including a substrate, a source, a drain, and a gate, and a fuse stacked over the transistor. The fuse includes an anode contact coupled to the drain of the transistor, a cathode contact, and a resistor coupled to the cathode contact and the anode contact via a first Schottky diode and a second Schottky diode, respectively. A method of fabricating such semiconductor devices is also provided. | 02-27-2014 |
20150294968 | FinFET AND TRANSISTORS WITH RESISTORS AND PROTECTION AGAINST ELECTROSTATIC DISCHARGE (ESD) - A FinFET device includes a plurality of FinFET devices formed on a corresponding plurality of fins in a multilevel interconnect semiconductor device. Each source and each drain is coupled to a metal interconnect level by a metal resistive element that is subjacent the lowermost interconnect level. In one embodiment, a metal segment extending over a plurality of the fins includes contacts to each of the fins, thereby providing subjacent metal resistive elements of different lengths. The plurality of fins and subjacent metal segments are arranged such that each of the FinFET devices has the same total resistance provided by the source and drain metal resistive elements, even though the source metal resistive element and drain metal resistive element associated with the fins may have different lengths. The arrangement provides the same turn-on resistance and the same ESD failure current for each FinFET device. | 10-15-2015 |
20150318278 | Circuit and Method for Reducing BVii on Highly Overdriven Devices - An integrated circuit is formed on a p-type semiconductor substrate connected to ground potential. A deep n-well is disposed in the p-type substrate. A p-well is disposed in the deep n-well. An n+ drain region and an n+ source region are disposed in the p-well, the n+ source region connected to a common potential. A p-type contact is disposed in the p-well and is connected to ground potential through a resistor. | 11-05-2015 |
20160190120 | FIN RESISTOR WITH OVERLYING GATE STRUCTURE - A resistor device includes a resistor body doped with a first type of dopant, an insulating layer disposed above the resistor body, and at least one gate structure disposed above the insulating layer and above the resistor body. A method includes applying a bias voltage to at least a first gate structure disposed above an insulating layer disposed above a resistor body doped with a first type of dopant to affect a resistance of the resistor body. | 06-30-2016 |