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With means to increase breakdown voltage

Subclass of:

257 - Active solid-state devices (e.g., transistors, solid-state diodes)

257213000 - FIELD EFFECT DEVICE

257288000 - Having insulated electrode (e.g., MOSFET, MOS diode)

257327000 - Short channel insulated gate field effect transistor

257335000 - Active channel region has a graded dopant concentration decreasing with distance from source region (e.g., double diffused device, DMOS transistor)

Patent class list (only not empty are listed)

Deeper subclasses:

Class / Patent application numberDescriptionNumber of patent applications / Date published
257339000 With means to increase breakdown voltage 89
20110198692SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF - A semiconductor structure is provided. A second conductivity type well region is disposed on a first conductivity type substrate. A gate structure comprising a first sidewall and second sidewall is provided. The first sidewall is disposed on the second conductivity type well region. A second conductivity type diffused source is disposed on the first conductivity type substrate outside of the second sidewall. A second conductivity type diffused drain is disposed on the second conductivity type well region outside of the first sidewall. First conductivity type buried rings are arranged in a horizontal direction, separated from each other, and formed in the second conductivity type well region. Doped profiles of the first conductivity type buried rings gradually become smaller in a direction from the second conductivity type diffused source to the second conductivity type diffused drain.08-18-2011
20090039424HIGH-VOLTAGE MOS TRANSISTOR DEVICE - A high-voltage transistor device has a substrate, an isolation structure, a source, a gate, a drain, a plurality of doped regions, a plurality of ion wells, and a first dielectric layer disposed on the substrate. The high-voltage transistor device further has a first conductive layer and a plurality of first field plate rings. The first conductive layer is electrically connected to the drain and at least one of the first field plate rings.02-12-2009
20130207185ISOLATED DEVICE AND MANUFACTURING METHOD THEREOF - An isolated device is formed in a substrate in which is formed a high voltage device. The isolated device includes: an isolated well formed in the substrate by a lithography process and an ion implantation process used in forming the high voltage device; a gate formed on the substrate; a source and a drain, which are located in the isolated well at both sides of the gate respectively; a drift-drain region formed beneath the substrate surface, wherein the gate and the drain are separated by the drift-drain region, and the drain is in the drift-drain region; and a mitigation region, which is formed in the substrate and has a shallowest portion located at least below 90% of a depth of the drift-drain region as measured from the substrate surface, wherein the mitigation region and the drift-drain region are defined by a same lithography process.08-15-2013
20130032880HIGH VOLTAGE DEVICE AND MANUFACTURING METHOD THEREOF - The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device is formed in a first conductive type substrate, wherein the substrate has an upper surface. The high voltage device includes: a second conductive type buried layer, which is formed in the substrate; a first conductive type well, which is formed between the upper surface and the buried layer; and a second conductive type well, which is connected to the first conductive type well and located at different horizontal positions. The second conductive type well includes a well lower surface, which has a first part and a second part, wherein the first part is directly above the buried layer and electrically coupled to the buried layer; and the second part is not located above the buried layer and forms a PN junction with the substrate.02-07-2013
20130075816LATERAL DOUBLE DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - Disclosed are an LDMOS device and a method for manufacturing the same capable of decreasing the concentration of a drift region between a source finger tip and a drain, thereby increasing a breakdown voltage. An LDMOS device includes a gate which is formed on a substrate, a source and a drain which are separately arranged on both sides of the substrate with the gate interposed therebetween, a field oxide film which is formed to have a step between the gate and the drain, a drift region which is formed of first condition type impurity ions between the gate and the drain on the substrate, and at least one internal field ring which is formed inside the drift region and formed by selectively ion-implanting second conduction type impurity ions in accordance with the step of the field oxide film.03-28-2013
20100044790Semiconductor device and method of etc. - Provided is a semiconductor device which includes a metal oxide semiconductor (MOS) transistor having high driving performance and high withstanding voltage with a thick gate oxide film. In the local oxidation-of-silicon (LOCOS) offset MOS transistor having high withstanding voltage, in order to prevent a gate oxide film (02-25-2010
20100096696SEMICONDUCTOR DEVICE INCLUDING FIELD EFFECT TRANSISTOR FOR USE AS A HIGH-SPEED SWITCHING DEVICE AND A POWER DEVICE - A body layer of a first conductivity type is formed on a semiconductor substrate, and a source layer of a second conductivity type is formed in a surface region of the body layer. An offset layer of the second conductivity type is formed on the semiconductor substrate, and a drain layer of the second conductivity type is formed in a surface region of the offset layer. An insulating film is embedded in a trench formed in the surface region of the offset layer between the source layer and the drain layer. A gate insulating film is formed on the body layer and the offset layer between the source layer and the insulating film. A gate electrode is formed on the gate insulating film. A first peak of an impurity concentration profile in the offset layer is formed at a position deeper than the insulating film.04-22-2010
20090302384SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE - A semiconductor device according to an aspect of the present invention includes a semiconductor layer, an insulating film formed on the surface of the semiconductor layer, a first insulator embedded in the semiconductor layer with a thickness larger than the thickness of the insulating film, and a resistive element formed on the first insulator. A semiconductor device according to another aspect of the present invention includes a semiconductor layer, an insulating film formed on the surface of the semiconductor layer, a resistive element formed on the insulating film, and a floating region formed on a portion of the semiconductor layer opposed to the resistive element through the insulating film and electrically floating from a periphery thereof.12-10-2009
20130062693SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device which provides compactness and enhanced drain withstand voltage. The semiconductor device includes: a gate electrode; a source electrode spaced from the gate electrode; a drain electrode located opposite to the source electrode with respect to the gate electrode in a plan view and spaced from the gate electrode; at least one field plate electrode located between the gate and drain electrodes in a plan view, provided over the semiconductor substrate through an insulating film and spaced from the gate electrode, source electrode and drain electrode; and at least one field plate contact provided in the insulating film, coupling the field plate electrode to the semiconductor substrate. The field plate electrode extends from the field plate contact at least either toward the source electrode or toward the drain electrode in a plan view.03-14-2013
20120228704High-Voltage MOSFET with High Breakdown Voltage and Low On-Resistance and Method of Manufacturing the Same - A high-voltage transistor is formed in a deep well of a first conductivity type that has been formed in a semiconductor substrate or epitaxial layer of a second conductivity type. A body region of the second conductivity type is formed in the deep well, into which a source region of the first conductivity type is formed. A drain region of the first conductivity type is formed in the deep well and separated from the body region by a drift region in the deep well. A gate dielectric layer is formed over the body region, and a first polysilicon layer formed over the gate dielectric layer embodies the gate of the transistor. The field plate dielectric layer is formed over the drift region after the gate has been formed. Finally, the field plate dielectric is covered by a second polysilicon layer having a field plate positioned over the field plate dielectric layer in the drift region.09-13-2012
20130161740Lateral High-Voltage Transistor with Buried Resurf Layer and Associated Method for Manufacturing the Same - A lateral high-voltage transistor comprising a semiconductor layer of a first conductivity type; a source region of a second conductivity type in the semiconductor layer; a drain region of the second conductivity type in the semiconductor layer; a first isolation layer atop the semiconductor layer between the source and the drain regions; a first well region of the second conductivity type surrounding the drain region; a gate positioned atop the first isolation layer adjacent to the source region; a spiral resistive field plate atop the first isolation layer spiraling between the drain region and the gate, wherein the spiral resistive field plate is coupled in series to the source and drain regions; and a buried layer of the first conductivity type in the first well region, wherein the buried layer is buried beneath a top surface of the first well region below the spiral resistive field plate.06-27-2013
20130161741SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device according an aspect of the present disclosure may include an isolation layer formed within a substrate and formed to define an active region, a junction formed in the active region, well regions formed under the isolation layer, and a plug embedded within the substrate between the junction and the well regions and formed extend to a greater depth than the well regions.06-27-2013
20130207183SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes a semiconductor substrate, a buried layer, a deep well having a first conductivity type being disposed on the buried layer, a first doped region having the first conductivity type and a well having the second conductivity type being disposed in the deep well, a first heavily doped region having the first conductivity type being disposed in the first doped region, a second heavily doped region having the first conductivity type being disposed in the well, a gate disposed between the first heavily doped region and the second heavily doped region, and a first trench structure and a second trench structure being disposed at the two sides of the gate in the semiconductor substrate. The first trench structure contacts the buried layer, and a depth of the second trench structure is substantially larger than a depth of the buried layer.08-15-2013
20130207186STEPPED-SOURCE LDMOS ARCHITECTURE - A semiconductor device can include a source region near a working top surface of a semiconductor region. The device can also include a gate located above the working top surface and located laterally between the source and a drain region. The source region and the gate can at least partially laterally overlap a body region near the working top surface. The source region can include a first portion having the first conductivity type, a second portion having a second conductivity type, and a third portion having the second conductivity type. The second portion can be located laterally between the first and third portions and can penetrate into the semiconductor region to a greater depth than the third portion but no more than the first portion. The lateral location of the third portion can be determined at least in part using the lateral location of the gate.08-15-2013
20110121389LDMOS HAVING A FIELD PLATE - Laterally diffused metal oxide semiconductor transistor for a radio frequency-power: amplifier comprising a drain finger (05-26-2011
20100295125Split gate oxides for a laterally diffused metal oxide semiconductor (LDMOS) - An apparatus is disclosed to increase a breakdown voltage of a semiconductor device. The semiconductor device includes a first heavily doped region to represent a source region. A second heavily doped region represents a drain region of the semiconductor device. A third heavily doped region represents a gate region of the semiconductor device. The semiconductor device includes a gate oxide positioned between the source region and the drain region, below the gate region. The semiconductor device uses a split gate oxide architecture to form the gate oxide. The gate oxide includes a first gate oxide having a first thickness and a second gate oxide having a second thickness.11-25-2010
20110284957SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - To fabricate a power MOSFET, etc. high in voltage-proofing (or breakdown voltage) and low in ON resistance (or On-state resistance) by a trench filling method, trial manufacture of power MOSFETs, etc. has been repeated with varying internal structures and layouts of super junction structures in a chip inner region located inside a guard ring. As a result, there occasionally occurred a source-drain voltage-proofing defect attributable to outer end portions of a supper junction structure. In one aspect of the present invention there is provided a semiconductor device having a power semiconductor element with a super junction structure introduced substantially throughout the whole surface of a drift region, the super junction structure being provided substantially throughout the whole surfaces of end portions of a semiconductor chip which configures the semiconductor device.11-24-2011
20100213545MOS TRANSISTOR WITH A P-FIELD IMPLANT OVERLYING EACH END OF A GATE THEREOF - The present invention provides a method for fabricating a MOS transistor (08-26-2010
20100213544HIGH VOLTAGE DEVICE - A method of forming a device is presented. A substrate prepared with an active device region is provided. The active device region includes gate stack layers of a gate stack that includes at least a gate electrode layer over a gate dielectric layer. An implant mask is formed on the substrate with an opening exposing a portion of a top gate stack layers. Ions are implanted through the opening and gate stack layers into the substrate to form a channel well. The substrate is patterned to at least remove portion of a top gate stack layer unprotected by the implant mask.08-26-2010
20120098063DUMMY GATE FOR A HIGH VOLTAGE TRANSISTOR DEVICE - The present disclosure provides a semiconductor device. The semiconductor device includes a first doped region and a second doped region both formed in a substrate. The first and second doped regions are oppositely doped. The semiconductor device includes a first gate formed over the substrate. The first gate overlies a portion of the first doped region and a portion of the second doped region. The semiconductor device includes a second gate formed over the substrate. The second gate overlies a different portion of the second doped region. The semiconductor device includes a first voltage source that provides a first voltage to the second gate. The semiconductor device includes a second voltage source that provides a second voltage to the second doped region. The first and second voltages are different from each other.04-26-2012
20090273031SEMICONDUCTOR DEVICE - A semiconductor device includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type provided on a major surface of the first semiconductor layer; a third semiconductor layer of a second conductivity type provided on the major surface of the first semiconductor layer, the third semiconductor layer forming a structure of periodical arrangement with the second semiconductor layer; a fourth semiconductor layer of the second conductivity type provided above the third semiconductor layer; a fifth semiconductor layer of the first conductivity type selectively provided on a surface of the fourth semiconductor layer; a first main electrode electrically connected to the first semiconductor layer; a second main electrode provided to contact a surface of the fifth semiconductor layer and a surface of the fourth semiconductor layer; and a control electrode provided above the fifth semiconductor layer, the fourth semiconductor layer, and the second semiconductor layer via an insulative film. A portion is provided locally in the third semiconductor layer, the portion depleting at a voltage not more than one third of a voltage at which the second semiconductor layer and the third semiconductor layer completely deplete.11-05-2009
20120025310SEMICONDUCTOR DEVICE OF WHICH BREAKDOWN VOLTAGE IS IMPROVED - A semiconductor device includes: a semiconductor substrate; a gate electrode formed on the semiconductor substrate through a gate insulating film; a source diffusion layer and a drain diffusion layer formed on both sides of the gate electrode, respectively, in the semiconductor substrate; and a field drain section formed below the gate electrode in the semiconductor substrate so as to be positioned between the gate electrode and the drain diffusion region and include an insulator. The field drain section includes: a first insulating film configured to be contact with the semiconductor substrate, and a second insulating film configured to be formed on the first insulating film and has a dielectric constant higher than a dielectric constant of the first insulating film.02-02-2012
20120025309 OFFSET GATE SEMICONDUCTOR DEVICE - An offset gate semiconductor device includes a substrate and an isolation feature formed in the substrate. An active region is formed in the substrate substantially adjacent to the isolation feature. An interface layer is formed on the substrate over the isolation feature and the active region. A polysilicon layer is formed on the interface layer over the isolation feature and the active region. A trench being formed in the polysilicon layer over the isolation feature. The trench extending to the interface layer. A fill layer is formed to line the trench and a metal gate formed in the trench.02-02-2012
20100001343HIGH VOLTAGE SEMICONDUCTOR DEVICE INCLUDING FIELD SHAPING LAYER AND METHOD OF FABRICATING THE SAME - Provided are a high voltage semiconductor device in which a field shaping layer is formed on the entire surface of a semiconductor substrate and a method of fabricating the same. Specifically, the high voltage semiconductor device includes a first conductivity-type semiconductor substrate. A second conductivity-type semiconductor layer is disposed on a surface of the semiconductor substrate, and a first conductivity-type body region is formed in semiconductor layer. A second conductivity-type source region is formed in the body region. A drain region is formed in the semiconductor layer and is separated from the body region. The field shaping layer is formed on the entire surface of the semiconductor layer facing the semiconductor layer.01-07-2010
20090152628SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - It is desirable to reduce chip area, lower on resistance and improve electric current driving capacity of a DMOS transistor in a semiconductor device with a DMOS transistor. On the surface of an N type epitaxial layer, a P+W layer of the opposite conductivity type (P type) is disposed and a DMOS transistor is formed in the P+W layer. The epitaxial layer and a drain region are insulated by the P+W layer. Therefore, it is possible to form both the DMOS transistor and other device element in a single confined region surrounded by an isolation layer. An N type FN layer is disposed on the surface region of the P+W layer beneath the gate electrode. An N+D layer, which is adjacent to the edge of the gate electrode of the drain layer side, is also formed. P type impurity layers (a P+D layer and a FP layer), which are located below the drain layer, are disposed beneath the contact region of the drain layer.06-18-2009
20090152627SEMICONDUCTOR DEVICE - This invention is directed to offer a MOS transistor that has a high source-drain breakdown BVds, a low on resistance and a high electric current driving capacity. On resistance is lowered by forming an N well layer for lowering on resistance in the drift region. The N well layer is disposed beneath the gate electrode and away from the N well layer with a certain space between them. This space ensures the withstand voltage at the edge of the gate electrode of the drain layer side. Also, the N well layer is formed on the surface of an epitaxial layer in the region that includes a P+L layer. The edge of the N well layer of the drain layer side is located near the edge of the P+L layer of the drain layer side and away from the N well layer. This space makes the expansion of depletion layer from the P+L layer easier, further improving the withstand voltage.06-18-2009
20100264491HIGH BREAKDOWN VOLTAGE SEMICONDUCTOR DEVICE AND HIGH VOLTAGE INTEGRATED CIRCUIT - A high breakdown voltage semiconductor device, in which a semiconductor layer is formed on a semiconductor substrate across a dielectric layer, includes a drain layer on the semiconductor layer, a buffer layer formed so as to envelop the drain layer, a source layer, separated from the drain layer, and formed so as to surround a periphery thereof, a well layer formed so as to envelop the source layer, and a gate electrode formed across a gate insulating film on the semiconductor layer, wherein the planar shape of the drain layer 10-21-2010
20120187484LATERAL DOUBLE DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICE - A lateral double diffused metal oxide semiconductor (LDMOS) device includes a first buried layer having a second conduction type formed in an epitaxial layer having a first conduction type, a first high-voltage well having the second conduction type formed above one region of the first buried layer, a first drain diffusion region having the first conduction type formed above another region of the first buried layer, a second drain diffusion region having the second conduction type formed in a partial region of the first drain diffusion region, the second drain diffusion region including a gate pattern and a drain region, and a first body having the first conduction type including a source region and having a surface in contact with the second drain diffusion region.07-26-2012
20100090278High-Voltage Transistor with High Current Load Capacity and Method for its Production - An isolation area (04-15-2010
20110198693III NITRIDE SEMICONDUCTOR ELECTRONIC DEVICE, METHOD FOR MANUFACTURING III NITRIDE SEMICONDUCTOR ELECTRONIC DEVICE, AND III NITRIDE SEMICONDUCTOR EPITAXIAL WAFER - Provided is a III nitride semiconductor electronic device having a structure capable of reducing leakage current. A laminate 08-18-2011
20090261409SEMICONDUCTOR DEVICES FOR HIGH POWER APPLICATION - Semiconductor devices for high voltage application are presented. A high power semiconductor device includes a first type doped semiconductor substrate and a second type doped epitaxial layer deposited thereon. A first type doped body region is disposed in the second type doped epitaxial layer. A heavily doped drain region is formed in the second type doped epitaxial layer and isolated from the first type doped body region with an isolation region and a channel. A second type deep heavily doped region extends from the heavily doped drain region to the semiconductor substrate. A pair of inversed type heavily doped source regions is disposed in the first type doped body region. A gate electrode is disposed overlying the channel with a dielectric layer interposed therebetween. The high power semiconductor device is isolated from the other semiconductor devices with a first type deep heavily doped region.10-22-2009
20080315306Semiconductor Device and Method of Fabricating the Semiconductor Device - A semiconductor device comprises a gate electrode on a semiconductor substrate, drift regions at opposite sides of the gate electrode, source and drain regions in the respective drift regions, and shallow trench isolation (STI) regions in the respective drift regions between the gate electrode and the source or drain region, wherein the drift regions comprise first and second conductivity-type impurities.12-25-2008
20120104493LATERAL SUPERJUNCTION EXTENDED DRAIN MOS TRANSISTOR - An integrated circuit containing an extended drain MOS transistor with deep semiconductor (SC) RESURF trenches in the drift region, in which each deep SC RESURF trench has a semiconductor RESURF layer at a sidewall of the trench contacting the drift region. The semiconductor RESURF layer has an opposite conductivity type from the drift region. The deep SC RESURF trenches have depth:width ratios of at least 5:1, and do not extend through a bottom surface of the drift region. A process of forming an integrated circuit with deep SC RESURF trenches in the drift region by etching undersized trenches and counterdoping the sidewall region to form the semiconductor RESURF layer. A process of forming an integrated circuit with deep SC RESURF trenches in the drift region by etching trenches and growing an epitaxial layer on the sidewall region to form the semiconductor RESURF layer.05-03-2012
20100258867Semiconductor device - A semiconductor device comprises a substrate and a gate which extends on the substrate in a first horizontal direction. A source region is positioned at a first side of the gate and extends in the first direction. A body region of a first conductivity type is under the source region and extends in the first direction. A drain region of a second conductivity type is at a second side of the gate and extends in the first direction. A drift region of the second conductivity type extends between the body region and the drain region in the substrate in a second horizontal direction. A first buried layer is under the drift region in the substrate, the first buried layer extending in the first and second directions. A plurality of second buried layers is between the first buried layer and the drift region in the substrate. The second buried layers extend in the second direction and are spaced apart from each other in the first direction.10-14-2010
20100224933Semiconductor device - Provided is a semiconductor device including an N-channel high-voltage MOS transistor, in which wiring metal connected to a drain region is laid above a boundary portion between an oxide film formed by LOCOS process or the like on a low impurity concentration region and a high impurity concentration region forming the drain region, to thereby alleviate an electric field concentration at the boundary portion which is a contact portion between the low impurity concentration region and the high impurity concentration region by an electric field generated from the wiring metal toward a semiconductor substrate.09-09-2010
20100001344SEMICONDUCTOR DEVICE AND METHOD OF FORMING A SEMICONDUCTOR DEVICE - A method of forming a semiconductor device having an active area and a termination area surrounding the active area comprises providing a semiconductor substrate, providing a semiconductor layer of a first conductivity type over the semiconductor substrate and forming a mask layer over the semiconductor layer. The mask layer outlines at least two portions of a surface of the semiconductor layer: a first outlined portion outlining a floating region in the active area and a second outlined portion outlining a termination region in the termination area. Semiconductor material of a second conductivity type is provided to the first and second outlined portions so as to provide a floating region of the second conductivity type buried in the semiconductor layer in the active area and a first termination region of the second conductivity type buried in the semiconductor layer in the termination area of the semiconductor device.01-07-2010
20100163985SEMICONDUCTOR AND METHOD FOR MANUFACTURING THE SAME - A semiconductor includes a high voltage region formed in a substrate, first and second drift regions formed in the high voltage region, an isolation layer in the high voltage region, a gate formed on and/or over the first and second drift regions, and a drain and a source formed in the first drift region and the second drift region.07-01-2010
20100163986SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device and a method of manufacturing a semiconductor device. A method may include forming a first well by injecting first conduction type impurity ions on and/or over a semiconductor substrate, forming an extended drain region overlapped with a region of said first well by injecting second conduction type impurities on and/or over a semiconductor substrate, and/or forming a first conduction type second well on and/or over a semiconductor substrate under an extended drain region to overlap with another region of a first well by injecting second conduction type impurities on and/or over a semiconductor substrate. A method may include forming a gate over a first well overlapped with an extended drain region, and/or forming a drain region by injecting second conduction type impurities on and/or over an extended drain region at one side of a gate.07-01-2010
20110057263ULTRA HIGH VOLTAGE MOS TRANSISTOR DEVICE - An ultra high voltage MOS transistor device includes a substrate having a first conductive type, a first well having a second conductive type and a second well having the first conductive type formed in the substrate, a drain region having the second conductive type formed in the first well, a source region having the second conductive type formed in the second well, a first doped region having the first conductive type formed between the second well and the substrate, an insulating layer formed in a first recess in the first well, a gate formed on the substrate between the source region and the first well, and a recessed channel region formed in the substrate underneath the gate.03-10-2011
20090072309Semiconductor device - The semiconductor device according to the present invention includes an SJMOSFET having a plurality of base regions formed at an interval from each other and an SBD (Schottky Barrier Diode) having a Schottky junction between the plurality of base regions. The SBD is provided in parallel with a parasitic diode of the SJMOSFET.03-19-2009
20090108347LATERAL DIFFUSION FIELD EFFECT TRANSISTOR WITH ASYMMETRIC GATE DIELECTRIC PROFILE - A gate stack comprising a uniform thickness gate dielectric, a gate electrode, and an oxygen-diffusion-resistant gate cap is formed on a semiconductor substrate. Thermal oxidation is performed only on the drain side of the gate electrode, while the source side is protected from thermal oxidation. A thermal oxide on the drain side sidewall of the gate electrode is integrally formed with a graded thickness silicon oxide containing gate dielectric, of which the thickness monotonically increases from the source side to the drain side. The thickness profile may be self-aligned to the drain side edge of the gate electrode, or may have a portion with a self-limiting thickness. The graded thickness profile may be advantageously used to form a lateral diffusion metal oxide semiconductor field effect transistor providing an enhanced performance.04-30-2009
20110127607STEPPED-SOURCE LDMOS ARCHITECTURE - A semiconductor device can include a source region near a working top surface of a semiconductor region. The device can also include a gate located above the working top surface and located laterally between the source and a drain region. The source region and the gate can at least partially laterally overlap a body region near the working top surface. The source region can include a first portion having the first conductivity type, a second portion having a second conductivity type, and a third portion having the second conductivity type. The second portion can be located laterally between the first and third portions and can penetrate into the semiconductor region to a greater depth than the third portion but no more than the first portion. The lateral location of the third portion can be determined at least in part using the lateral location of the gate.06-02-2011
20110006366Coupling Well Structure for Improving HVMOS Performance - A semiconductor structure includes a substrate, a first well region of a first conductivity type overlying the substrate, a second well region of a second conductivity type opposite the first conductivity type overlying the substrate, a cushion region between and adjoining the first and the second well regions, an insulation region in a portion of the first well region and extending from a top surface of the first well region into the first well region, a gate dielectric extending from over the first well region to over the second well region, wherein the gate dielectric has a portion over the insulation region, and a gate electrode on the gate dielectric.01-13-2011
20110241110TERMINAL STRUCTURE FOR SUPERJUNCTION DEVICE AND METHOD OF MANUFACTURING THE SAME - A terminal structure for superjunction device is disclosed. The terminal structure comprises from inside out at least one P type implantation ring and several P type trench rings formed in an N type epitaxial layer to form alternating P type and N type regions. A channel cut-off ring is formed at the border of the device. The P type implantation ring is formed adjacent to the active area of the device and covers at least one trench ring. A terminal dielectric layer is formed to cover the P type implantation ring and the trench rings. A plurality of field plates are formed above the terminal dielectric layer. Methods of manufacturing terminal structure are also disclosed.10-06-2011
20130214354SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises a first semiconductor region, a second semiconductor region, a dielectric structure and a gate electrode layer. The first semiconductor region has a first type conductivity. The second semiconductor region has a second type conductivity opposite to the first type conductivity. The first semiconductor region is adjoined to the second semiconductor region. The dielectric structure is on the first semiconductor region and the second semiconductor region. The gate electrode layer is on the dielectric structure.08-22-2013
20090039425HIGH-VOLTAGE MOS TRANSISTOR DEVICE - A HV MOS transistor device having a substrate, a gate, a source, a drain, a first ion well of a first conductive type disposed in the substrate, and a plurality of field plates disposed on the substrate is disclosed. The HV MOS transistor device further has a first doped region of a second conductive type positioned in the first ion well. Therefore, a first interface and a second interface between the first ion well and the first doped region are formed, and the first interface and the second interface are respectively positioned near the drain and the source. In addition, the first interface is positioned under a respective field plate to produce a smooth field distribution and to increase the breakdown voltage of the HV transistor device.02-12-2009
20090032870Semiconductor device and method for manufacturing same - A semiconductor device comprising a field effect transistor having higher breakdown voltage by reducing electric field concentration between the drain region and a gate electrode is provided. A semiconductor device includes, on a silicon substrate, an n-well source region and an n-well drain region, which are formed over a surface layer thereof to be spaced apart from each other; and a gate electrode provided via a gate insulating film, said gate insulating film being formed to extend over said source region and said drain region. Further, LOCOS oxide film 02-05-2009
20120241861Ultra-High Voltage N-Type-Metal-Oxide-Semiconductor (UHV NMOS) Device and Methods of Manufacturing the same - An ultra-high voltage n-type-metal-oxide-semiconductor (UHV NMOS) device with improved performance and methods of manufacturing the same are provided. The UHV NMOS includes a substrate of P-type material; a first high-voltage N-well (HVNW) region disposed in a portion of the substrate; a source and bulk p-well (PW) adjacent to one side of the first HVNW region, and the source and bulk PW comprising a source and a bulk; a gate extended from the source and bulk PW to a portion of the first HVNW region, and a drain disposed within another portion of the first HVNW region that is opposite to the gate; a P-Top layer disposed within the first HVNW region, the P-Top layer positioned between the drain and the source and bulk PW; and an n-type implant layer formed on the P-Top layer.09-27-2012
20110101454SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME - A P type semiconductor substrate includes a P type body region, an N type drift region formed away from the P type body region in a direction parallel to a substrate surface, an N type drain region formed in a region separated by a field oxide film in the N type drift region so as to have a concentration higher than the N type drift region, an N type source region formed in the P type body region so as to have a concentration higher than the N type drift region. A P type buried diffusion region having a concentration higher than the N type drift region is formed of a plurality of parts each of which is connected to a part of the bottom surface of the P type body region and extends parallel to the substrate surface and its tip end reaches the inside of the drift region.05-05-2011
20110163377SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes: an n-type first well diffusion layer; an n-type second well diffusion layer; a p-type source diffusion layer; a p-type third well diffusion layer; a p-type drain diffusion layer; a gate insulating film; a gate electrode; a device isolation insulating film; and a buffer layer. The buffer layer is formed between the first well diffusion layer and the third well diffusion layer to be in contact with an end of the third well diffusion layer opposing the source diffusion layer, and extends from immediately below the gate insulating film to a position deeper than a peak of curvature of impurity concentration distribution of the third well diffusion layer. The buffer layer has an impurity concentration lower than an impurity concentration in the third well diffusion layer.07-07-2011
20100320538Semiconductor device - The semiconductor device according to the present invention includes an SJMOSFET having a plurality of base regions formed at an interval from each other and an SBD (Schottky Barrier Diode) having a Schottky junction between the plurality of base regions. The SBD is provided in parallel with a parasitic diode of the SJMOSFET.12-23-2010
20110133277SEMICONDUCTOR DEVICE - A semiconductor device includes a second conductive-type well configured over a substrate, a first conductive-type body region configured over the second conductive-type well, a gate electrode which overlaps a portion of the first conductive-type body region, and a first conductive-type channel extension region formed over the substrate and which overlaps a portion of the gate electrode.06-09-2011
20110101453LATERAL DOUBLE-DIFFUSED METAL OXIDE SEMICONDUCTOR - The invention provides a lateral double-diffused metal oxide semiconductor (LDMOS). The pre-metal dielectric layer (PMD) of the LDMOS is a silicon rich content material. Additionally, the inter-layer dielectric layer (ILD), inter-metal dielectric layer (IMD), or protective layer of the LDMOS may be formed of a silicon rich content material.05-05-2011
20100059818SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR THE SAME - A semiconductor device includes a first conductive type first semiconductor region, a second semiconductor region, and a second conductive type lateral RESURF region. The first semiconductor region is arranged on a first electrode side. The second semiconductor region includes first conductive type first pillar regions and a terminal part. The second pillar regions are alternately arranged on an element part. The terminal part is formed around the element part along a surface of the first semiconductor region on a second electrode side opposite to the first electrode side of the first semiconductor region. Furthermore, the second conductive type lateral RESURF region is formed in the second semiconductor region on the terminal part.03-11-2010
20100025762SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF - A semiconductor fabrication process according to the present invention defines an auxiliary structure with a plurality of spaces with a predetermined line-width in the oxide layer to prevent the conductive material in the spaces from being removed by etching or defined an auxiliary structure to rise the conductive structure so as to have the conductive structure being exposed by chemical mechanical polishing. Thus, the transmitting circuit can be defined without requiring an additional mask. Hence, the semiconductor fabrication process can reduce the number of required masks to lower the cost.02-04-2010
20090008711Fully Isolated High-Voltage MOS Device - A semiconductor structure includes a semiconductor substrate; an n-type tub extending from a top surface of the semiconductor substrate into the semiconductor substrate, wherein the n-type tub comprises a bottom buried in the semiconductor substrate; a p-type buried layer (PBL) on a bottom of the tub, wherein the p-type buried layer is buried in the semiconductor substrate; and a high-voltage n-type metal-oxide-semiconductor (HVNMOS) device over the PBL and within a region encircled by sides of the n-type tub.01-08-2009
20110095365Power transistor with improved high-side operating characteristics and reduced resistance and related apparatus and method - A method includes forming a transistor device on a first side of a semiconductor-on-insulator structure. The semiconductor-on-insulator structure includes a substrate, a dielectric layer, and a buried layer between the substrate and the dielectric layer. The method also includes forming a conductive plug through the semiconductor-on-insulator structure. The conductive plug is in electrical connection with the transistor device. The method further includes forming a field plate on a second side of the semiconductor-on-insulator structure, where the field plate is in electrical connection with the conductive plug. The transistor device could have a breakdown voltage of at least 600V, and the field plate could extend along at least 40% of a length of the transistor device.04-28-2011
20120061757SEMICONDUCTOR DEVICE - An ESD tolerance of an LDMOS transistor is improved. An N+ type source layer shaped in a ladder and having a plurality of openings in its center is formed in a surface of a P type base layer using a gate electrode and a resist mask. A P+ type contact layer is formed to be buried in the opening. At that time, a distance from an edge of the opening, that is an edge of the P+ type contact layer, to an edge of the N+ type source layer is set to a predetermined distance. The predetermined distance is equal to a distance at which an HBM+ESD tolerance of the LDMOS transistor, which increases as the distance increases, begins to saturate.03-15-2012
20120153390TRANSISTORS WITH ISOLATION REGIONS - A transistor device is described that includes a source, a gate, a drain, a semiconductor material which includes a gate region between the source and the drain, a plurality of channel access regions in the semiconductor material on either side of the gate, a channel in the semiconductor material having an effective width in the gate region and in the channel access regions, and an isolation region in the gate region. The isolation region serves to reduce the effective width of the channel in the gate region without substantially reducing the effective width of the channel in the access regions. Alternatively, the isolation region can be configured to collect holes that are generated in the transistor device. The isolation region may simultaneously achieve both of these functions.06-21-2012
20120211833SUPER-JUNCTION SEMICONDUCTOR DEVICE - A super-junction semiconductor device includes a drift layer including an alternating-conductivity-type layer that includes n-type region and p-type region arranged alternately in parallel to the first major surface of an n-type substrate. These alternating regions extend deep in a direction perpendicular to the first major surface. The first major surface includes a main device region with a gate electrode and a main source electrode and sensing device region with a gate electrode and a sensing source electrode. There is a common drain electrode on the second major surface of the substrate. There is a separation region between the main device region and the sensing device region. It includes an n-type region and p-type regions in the n-type region. The p-type regions are in an electrically floating state in the directions parallel and perpendicular to the first alternating-conductivity-type layer.08-23-2012
20120126322LDMOS SEMICONDUCTOR DEVICE - A Lateral Double Diffused Metal-Oxide-Semiconductor (LDMOS) semiconductor device includes a substrate; a gate region, a source region, and a drain region on and/or over the substrate, a well region at one side of the drain region, and a guardring region disposed at one side of the well region and connected electrically to the well region.05-24-2012
20120126321SEMICONDUCTOR DEVICE AND METHOD OF MAKING THE SAME - A substrate having semiconductor material and a surface that supports a gate electrode and defines a surface normal direction is provided. The substrate can include a drift region including a first dopant type. A well region can be disposed adjacent to the drift region and proximal to the surface, and can include a second dopant type. A termination extension region can be disposed adjacent to the well region and extend away from the gate electrode, and can have an effective concentration of second dopant type that is generally less than that in the well region. An adjust region can be disposed between the surface and at least part of the termination extension region. An effective concentration of second dopant type may generally decrease when moving from the termination extension region into the adjust region along the surface normal direction.05-24-2012
20120223384HIGH VOLTAGE DEVICE AND MANUFACTURING METHOD THEREOF - The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device includes: a first conductive type substrate in which isolation regions are formed for defining a device region; a gate formed on the first conductive type substrate; a source and a drain formed in the device region and located at both sides of the gate respectively, and doped with second conductive type impurities; a second conductive type well, which is formed in the first conductive type substrate, and surrounds the drain from top view; and a first deep trench isolation structure, which is formed in the first conductive type substrate, and is located in the second conductive type well between the source and the drain from top view, wherein the depth of the first deep trench isolation structure is deeper than the second conductive type well from the cross-sectional view.09-06-2012
20120228705LDMOS WITH IMPROVED BREAKDOWN VOLTAGE - An LDMOS is formed with a second gate stack over the n09-13-2012
20120267717ENHANCED HVPMOS - A p-channel LDMOS device with a controlled n-type buried layer (NBL) is disclosed. A Shallow Trench Isolation (STI) oxidation is defined, partially or totally covering the drift region length. The NBL layer, which can be defined with the p-well mask, connects to the n-well diffusion, thus providing an evacuation path for electrons generated by impact ionization. High immunity to the Kirk effect is also achieved, resulting in a significantly improved safe-operating-area (SOA). The addition of the NBL deep inside the drift region supports a space-charge depletion region which increases the RESURF effectiveness, thus improving BV. An optimum NBL implanted dose can be set to ensure fully compensated charge balance among n and p doping in the drift region (charge balance conditions). The p-well implanted dose can be further increased to maintain a charge balance, which leads to an Rdson reduction.10-25-2012
20120267716HIGH VOLTAGE METAL OXIDE SEMICONDUCTOR DEVICE WITH LOW ON-STATE RESISTANCE - A high voltage metal oxide semiconductor device with low on-state resistance is provided. A multi-segment isolation structure is arranged under a gate structure and beside a drift region for blocking the current from directly entering the drift region. Due to the multi-segment isolation structure, the path length from the body region to the drift region is increased. Consequently, as the breakdown voltage applied to the gate structure is increased, the on-state resistance is reduced.10-25-2012
20120280320High voltage device and manufacturing method thereof - The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device is formed in a first conductive type substrate, wherein the substrate includes isolation regions defining a device region. The high voltage device includes: a drift region, located in the device region, doped with second conductive type impurities; a gate in the device region and on the surface of the substrate; and a second conductive type source and drain in the device region, at different sides of the gate respectively. From top view, the concentration of the second conductive type impurities of the drift region is distributed substantially periodically along horizontal and vertical directions.11-08-2012
20120091526ULTRA HIGH VOLTAGE MOS TRANSISTOR DEVICE - An ultra high voltage MOS transistor device includes a substrate having a first conductivity type and a first recess formed thereon, a gate positioned on the first recess, and a pair of source region and drain region having a second conductivity type formed in two sides of the gate, respectively.04-19-2012
20120139041HIGH SIDE GATE DRIVER DEVICE - The present disclosure provides a semiconductor device. The semiconductor device includes: a drift region having a first doping polarity formed in a substrate; a doped extension region formed in the drift region and having a second doping polarity opposite the first doping polarity, the doped extension region including a laterally-extending component; a dielectric structure formed over the drift region, the dielectric structure being separated from the doped extension region by a portion of the drift region; a gate structure formed over a portion of the dielectric structure and a portion of the doped extension region; and a doped isolation region having the second doping polarity, the doped isolation region at least partially surrounding the drift region and the doped extension region.06-07-2012
20120241862LDMOS DEVICE AND METHOD FOR MAKING THE SAME - The embodiments of the present disclosure disclose a LDMOS device and the method for making the LDMOS device. The LDMOS device comprises at least one capacitive region formed in the drift region. Each capacitive region comprises a polysilicon layer and a thick oxide layer separating the polysilicon layer from the drift region. The LDMOS device in accordance with the embodiments of the present disclosure can improve the breakdown voltage while a low on-resistance is maintained.09-27-2012
20130134512Power MOSFETs and Methods for Forming the Same - A power MOSFET includes a semiconductor region extending from a top surface of a semiconductor substrate into the semiconductor substrate, wherein the semiconductor region is of a first conductivity type. A gate dielectric and a gate electrode are disposed over the semiconductor region. A drift region of a second conductivity type opposite the first conductivity type extends from the top surface of the semiconductor substrate into the semiconductor substrate. A dielectric layer has a portion over and in contact with a top surface of the drift region. A conductive field plate is over the dielectric layer. A source region and a drain region are on opposite sides of the gate electrode. The drain region is in contact with the first drift region. A bottom metal layer is over the field plate05-30-2013
20130175615LDMOS Transistors For CMOS Technologies And An Associated Production Method - In a semiconductor component or device, a lateral power effect transistor is produced as an LDMOS transistor in such a way that, in combination with a trench isolation region (07-11-2013
20130175616RESURF SEMICONDUCTOR DEVICE CHARGE BALANCING - Breakdown voltage BVdss is enhanced and ON-resistance reduced in RESURF devices, e.g., LDMOS transistors, by careful charge balancing, even when body and drift region charge balance is not ideal, by: (i) providing a plug or sinker near the drain and of the same conductivity type extending through the drift region at least into the underlying body region, and/or (ii) applying bias Viso to a surrounding lateral doped isolation wall coupled to the device buried layer, and/or (iii) providing a variable resistance bridge between the isolation wall and the drift region. The bridge may be a FET whose source-drain couple the isolation wall and drift region and whose gate receives control voltage Vc, or a resistor whose cross-section (X, Y, Z) affects its resistance and pinch-off, to set the percentage of drain voltage coupled to the buried layer via the isolation wall.07-11-2013
20130093015HIGH VOLTAGE MOS TRANSISTOR - A high voltage metal oxide semiconductor (HVMOS) transistor (04-18-2013
20130134511Semiconductor Device with Self-Biased Isolation - A device includes a semiconductor substrate including a surface, a drain region in the semiconductor substrate having a first conductivity type, a well region in the semiconductor substrate on which the drain region is disposed, the well region having the first conductivity type, a buried isolation layer in the semiconductor substrate extending across the well region, the buried isolation layer having the first conductivity type, a reduced surface field (RESURF) region disposed between the well region and the buried isolation layer, the RESURF region having a second conductivity type, and a plug region in the semiconductor substrate extending from the surface of the substrate to the RESURF region, the plug region having the second conductivity type.05-30-2013
20080197409SUPERJUNCTION POWER MOSFET - An embodiment of an MOS device includes a semiconductor substrate of a first conductivity type, a first region of the first conductivity type having a length L08-21-2008
20110220998Devices Containing Permanent Charge - An edge termination structure includes a final dielectric trench containing permanent charge. The final dielectric trench is surrounded by first conductivity type semiconductor material (doped by lateral outdiffusion from the trenches), which in turn is laterally surrounded by second conductivity type semiconductor material.09-15-2011
20120273882SHALLOW-TRENCH CMOS-COMPATIBLE SUPER JUNCTION DEVICE STRUCTURE FOR LOW AND MEDIUM VOLTAGE POWER MANAGEMENT APPLICATIONS - A novel lateral super junction device compatible with standard CMOS processing techniques using shallow trench isolation is provided for low- and medium-voltage power management applications. The concept is similar to other lateral super junction devices having N- and P-type implants to deplete laterally to sustain the voltage. However, the use of shallow trench structures provides the additional advantage of reducing the Rdson without the loss of the super junction concept and, in addition, increasing the effective channel width of the device to form a “FINFET” type structure, in which the conducting channel is wrapped around a thin silicon “fin” that forms the body of the device. The device is manufactured using standard CMOS processing techniques with the addition of super junction implantation steps, and the addition of polysilicon within the shallow trench structures to form fin structures.11-01-2012
20120273881DMOS Transistor with a Cavity that Lies Below the Drift Region - A lateral DMOS transistor formed on a silicon-on-insulator (SOI) structure has a higher breakdown voltage that results from a cavity that is formed in the bulk region of the SOI structure. The cavity exposes a portion of the bottom surface of the insulator layer of the SOI structure that lies directly vertically below the drift region of the DMOS transistor.11-01-2012
20120273883HIGH VOLTAGE DEVICES AND METHODS FOR FORMING THE SAME - A high voltage (HV) device includes a gate dielectric structure over a substrate. The gate dielectric structure has a first portion and a second portion. The first portion has a first thickness and is disposed over a first well region of a first dopant type in the substrate. The second portion has a second thickness and is disposed over a second well region of a second dopant type. The first thickness is larger than the second thickness. An isolation structure is disposed between the gate dielectric structure and a drain region disposed within the first well region. A gate electrode is disposed over the gate dielectric structure.11-01-2012
20110233672SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF - A semiconductor structure is provided. A second conductivity type well region is formed on a first conductivity type substrate. A second conductivity type diffused source and second conductivity type diffused drain are formed on the first conductivity type substrate. A gate structure is formed on the second conductivity type well region between the second conductivity type diffused source and the second conductivity type diffused drain. First conductivity type buried rings are arranged in a horizontal direction, and formed in the second conductivity type well region, and divide the second conductivity type well region into an upper drift region and a lower drift region.09-29-2011
20100314683SEMICONDUCTOR DEVICE - Provided is a semiconductor device which scarcely malfunctions even when the device is used as a high-side element, and can keep a high breakdown voltage. In a semiconductor substrate having a main surface, a first p12-16-2010
20110303979SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device, includes a semiconductor layer, a first base region of a first conductivity type, a first source region of a second conductivity type, a second base region of the first conductivity type, a back gate region of the first conductivity type, a drift region of the second conductivity type, a drain region of the second conductivity type, a first insulating region, a second insulating region, a gate oxide film, a first gate electrode, a second gate electrode, a first main electrode and a second main electrode. These constituent elements are provided on the surface of the semiconductor layer. The distance between the first base region and the first insulating region is not more than 1.8 μm. The distance between the first base region and the first insulating region is shorter than a distance between the second base region and the second insulating region.12-15-2011
20110303978Semiconductor Device Having an Enhanced Well Region - An apparatus is disclosed to increase a breakdown voltage of a semiconductor device. The semiconductor device includes an enhanced well region to effectively increase a voltage at which punch-through occurs when compared to a conventional semiconductor device. The enhanced well region includes a greater number of excess carriers when compared to a well region of the conventional semiconductor device. These larger number of excess carriers attract more carriers allowing more current to flow through a channel region of the semiconductor device before depleting the enhanced well region of the carriers. As a result, the semiconductor device may accommodate a greater voltage being applied to its drain region before the depletion region of the enhanced well region and a depletion region of a well region surrounding the drain region merge into a single depletion region.12-15-2011
20110303977LDPMOS STRUCTURE FOR ENHANCING BREAKDOWN VOLTAGE AND SPECIFIC ON RESISTANCE IN BICMOS-DMOS PROCESS - An LDPMOS structure having enhanced breakdown voltage and specific on-resistance is described, as is a method for fabricating the structure. A P-field implanted layer formed in a drift region of the structure and surrounding a lightly doped drain region effectively increases breakdown voltage while maintaining a relatively low specific on-resistance.12-15-2011
20110309442LATERALLY DOUBLE DIFFUSED METAL OXIDE SEMICONDUCTOR TRANSISTOR HAVING A REDUCED SURFACE FIELD STRUCTURE AND METHOD THEREFOR - An LDMOS transistor includes a substrate of semiconductor material, an insulator layer overlying the substrate, a semiconductor layer overlying the insulator layer, a RESURF region, and a gate. The semiconductor layer includes a first conductivity type well region, a second conductivity type source region in contact with the first conductivity type well region, a second conductivity type drain region. The RESURF region includes at least one first conductivity type material portion, and at least one portion of the at least one first conductivity type material portion electrically coupled to the first conductivity type well region. A semiconductor material having a second conductivity type is located below the RESURF region. The second conductivity type semiconductor material is also located over a part of the RESURF region. The gate is located over the first conductivity type well region and over the RESURF region.12-22-2011
20130187225HIGH VOLTAGE MOSFET DEVICE - A HV MOSFET device includes a substrate, a deep well region, a source/body region, a drain region, a gate structure, and a first doped region. The deep well region includes a boundary site and a middle site. The source/body region is formed in the deep well region and defines a channel region. The first doped region is formed in the deep well region and disposed under the gate structure, and having the first conductivity type. There is a first ratio between a dopant dose of the first doped region and a dopant dose of the boundary site of the deep well region. There is a second ratio between a dopant dose of the first doped region and a dopant dose of the middle site of the deep well region. A percentage difference between the first ratio and the second ratio is smaller than or equal to 5%.07-25-2013
20120074493FIELD EFFECT TRANSISTORS HAVING IMPROVED BREAKDOWN VOLTAGES AND METHODS OF FORMING THE SAME - Transistors having improved breakdown voltages and methods of forming the same are provided herein. In one embodiment, a method of forming a transistor comprises the steps of: forming a drain and a source by doping a semiconductor with a first dopant type to form a first type of semiconductor, the drain and source being separated from one another, wherein the drain comprises a first drain region of a first dopant concentration adjacent a second drain region, such that at least a portion of the second drain region is positioned between the first drain region and the source, and further comprising forming an intermediate region by doping the semiconductor so as to form a second type of semiconductor intermediate the drain and source, the intermediate region spaced apart from the second drain region.03-29-2012
20130207184SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate, a gate structure, a source structure and a drain structure. The substrate includes a deep well region, and the gate structure is disposed on the deep well region. The source structure is formed within the deep well and located at a first side of the gate structure. The drain structure is formed within the deep well region and located at a second side of the gate structure. The drain structure includes a first doped region of a first conductivity type, a first electrode and a second doped region of a second conductivity type. The first doped region is located in the deep well region; the first electrode is electrically connected to the first doped region. The second doped region is disposed within the first doped region and between the first electrode and the gate structure.08-15-2013

Patent applications in class With means to increase breakdown voltage