| Entries |
| Document | Title | Date |
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| 20130043534 | HIGH DENSITY LATERAL DMOS AND ASSOCIATED METHOD FOR MAKING - The present disclosure discloses a lateral DMOS with recessed source contact and method for making the same. The lateral DMOS comprises a recessed source contact which has a portion recessed into a source region to reach a body region of the lateral DMOS. The lateral DMOS according to various embodiments of the present invention may have greatly reduced size and may be cost saving for fabrication. | 02-21-2013 |
| 20130026567 | FINFET DRIVE STRENGTH MODIFICATION - A method and circuit in which the drive strength of a FinFET transistor can be selectively modified, and in particular can be selectively reduced, by omitting the LDD extension formation in the source and/or in the drain of the FinFET. | 01-31-2013 |
| 20130026566 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - A non-volatile semiconductor memory device according to an embodiment includes: a p-type semiconductor substrate; a p-type first p well which is formed in the semiconductor substrate and in which a bit line connecting transistor configured to connect a bit line of a memory cell and a sense amplifier unit is formed; and an n-type first N well which surrounds the first P well and which is configured to electrically isolate the first P well from the semiconductor substrate. | 01-31-2013 |
| 20130037883 | LDPMOS STRUCTURE FOR ENHANCING BREAKDOWN VOLTAGE AND SPECIFIC ON RESISTANCE IN BICMOS-DMOS PROCESS - An LDPMOS structure having enhanced breakdown voltage and specific on-resistance is described, as is a method for fabricating the structure. A P-field implanted layer formed in a drift region of the structure and surrounding a tightly doped drain region effectively increases breakdown voltage while maintaining a relatively low specific on-resistance. | 02-14-2013 |
| 20100102386 | Lateral double-diffused metal oxide semiconductor (LDMOS) transistors - Methods of making, structures, devices, and/or applications for lateral double-diffused metal oxide semiconductor (LDMOS) transistors are disclosed. In one embodiment, an LDMOS transistor can include: (i) an n-doped deep n-well (DNW) region on a substrate; (ii) a gate oxide and a drain oxide between a source region and a drain region of the LDMOS transistor, the gate oxide being adjacent to the source region, the drain oxide being adjacent to the drain region; (iii) a conductive gate over the gate oxide and a portion of the drain oxide; (iv) a p-doped p-body region in the source region; (v) an n-doped drain region in the drain region; (vi) a first n-doped n+ region and a p-doped p+ region adjacent thereto in the p-doped p-body region of the source region; and (vii) a second n-doped n+ region in the drain region. | 04-29-2010 |
| 20100096695 | HIGH STRESS FILM - A semiconductor device that includes a substrate having an active region prepared with a transistor is presented. The semiconductor device includes a stress structure adjacent to the substrate. The stress structure includes a dielectric layer having nanocrystals embedded therein. The nanocrystals induce a first or a second stress on a channel region of the transistor which improves carrier mobility of the transistor. | 04-22-2010 |
| 20100109082 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device, has forming a gate insulating film over a surface of a substrate, eliminating a portion of the gate insulating film in a region, forming a gate electrode over the gate insulating film and a drain electrode on the region, implanting first impurities into the substrate using the gate electrode and the drain electrode as a mask, forming an insulating film to fill the space between the gate electrode and the drain electrode, and implanting second impurities into the substrate to form a source region using the gate electrode, the drain electrode and the insulating film as a mask. | 05-06-2010 |
| 20100109081 | SEMICONDUCTOR DEVICE AND IC CHIP - A semiconductor device and an IC chip are described. The deep N-well region is configured in a substrate. The P-well region surrounds a periphery of the deep N-well region. The gate structure is disposed on the substrate of the deep N-well region. The P-body region is configured in the deep N-well region at one side of the gate structure. The first N-type doped region is configured in the P-body region. The second N-type doped region is configured pin the deep N-well region at the other side of the gate structure. The first isolation structure is disposed between the gate structure and the second N-type doped region. The N-type isolation ring is configured in the deep N-well region and corresponding to an edge of the deep N-well region, wherein a doping concentration of the N-type isolation ring is higher than that of the deep N-well region. | 05-06-2010 |
| 20130082327 | SEMICONDUCTOR DEVICE - A semiconductor device including a first conductive epitaxial layer, a second conductive type first well provided in the first conductive epitaxial layer, a first conductive body provided in the first conductive epitaxial layer, a second conductive type drain extension region provided in the first conductive epitaxial layer and interposed between the first conductive body and the second conductive type first well, a second conductive type second well provided in the second conductive type first well, and a gate provided in the first conductive epitaxial layer. | 04-04-2013 |
| 20120187482 | FABRICATION OF CMOS TRANSISTORS HAVING DIFFERENTIALLY STRESSED SPACERS - CMOS transistors are formed incorporating a gate electrode having tensely stressed spacers on the gate sidewalls of an n channel field effect transistor and having compressively stressed spacers on the gate sidewalls of a p channel field effect transistor to provide differentially stressed channels in respective transistors to increase carrier mobility in the respective channels. | 07-26-2012 |
| 20090267146 | STRUCTURE AND METHOD FOR SEMICONDUCTOR POWER DEVICES - A semiconductor device includes a semiconductor-on-insulator region on a substrate. The semiconductor-on-insulator region includes a first semiconductor region overlying a dielectric region. The device includes an MOS transistor and a bipolar transistor. The MOS transistor has a drain region, a body region, and a source region in the first semiconductor region. The MOS transistor also includes a gate. The device also includes a second semiconductor region overlying the substrate and adjacent to the drain region, and a third semiconductor region overlying the substrate and adjacent to the second semiconductor region. The bipolar transistor includes has the drain region of the MOS transistor as an emitter, the second semiconductor region as a base, and the third semiconductor region as a collector. Accordingly, the drain of the MOS transistor also functions as the emitter of the bipolar transistor. Additionally, the gate and the base are coupled by a resistive element. | 10-29-2009 |
| 20090267145 | MOSFET DEVICE HAVING DUAL INTERLEVEL DIELECTRIC THICKNESS AND METHOD OF MAKING SAME - A method of forming a metal-oxide-semiconductor (MOS) device includes the following steps: forming a semiconductor layer of a first conductivity type having source and drain regions of a second conductivity type, a channel region and a lightly-doped drain region formed therein; forming a gate over the channel region proximate an upper surface of the semiconductor layer; after the forming steps, depositing a first dielectric layer having a first thickness over an upper surface of the semiconductor layer; etching the first dielectric layer in a region over the lightly-doped drain proximate to the gate to reduce its thickness; conformably depositing a second dielectric layer having a second thickness over the first dielectric layer, including in the etched region, the second thickness being less than the first thickness; and forming a shielding electrode over the second dielectric layer. | 10-29-2009 |
| 20130119466 | High Voltage Device with Reduced Leakage - A semiconductor device is provided which includes a semiconductor substrate, a gate structure formed on the substrate, sidewall spacers formed on each side of the gate structure, a source and a drain formed in the substrate on either side of the gate structure, the source and drain having a first type of conductivity, a lightly doped region formed in the substrate and aligned with a side of the gate structure, the lightly doped region having the first type of conductivity, and a barrier region formed in the substrate and adjacent the drain. The barrier region is formed by doping a dopant of a second type of conductivity different from the first type of conductivity. | 05-16-2013 |
| 20110278670 | Apparatus, System, and Method for Tunneling Mosfets Using Self-Aligned Heterostructure Source and Isolated Drain - Apparatuses, systems, and methods for tunneling MOSFETs (TFETs) using a self-aligned heterostructure source and isolated drain. TFETs that have an abrupt junction between source and drain regions have an increased probability of carrier direct tunneling (e.g., electrons and holes). The increased probability allows a higher achievable on current in TFETs having the abrupt junction. | 11-17-2011 |
| 20110169078 | SWITCH MODE CONVERTER EMPLOYING DUAL GATE MOS TRANSISTOR - A disclosed power transistor, suitable for use in a switch mode converter that is operable with a switching frequency exceeding, for example, 5 MHz or more, includes a gate dielectric layer overlying an upper surface of a semiconductor substrate and first and second gate electrodes overlying the gate dielectric layer. The first gate electrode is laterally positioned overlying a first region of the substrate. The first substrate region has a first type of doping, which may be either n-type or p-type. A second gate electrode of the power transistor overlies the gate dielectric and is laterally positioned over a second region of the substrate. The second substrate region has a second doping type that is different than the first type. The transistor further includes a drift region located within the substrate in close proximity to an upper surface of the substrate and laterally positioned between the first and second substrate regions. | 07-14-2011 |
| 20110024836 | Field Effect Transistor With Trench-Isolated Drain - A MOS transistor includes a body region of a first conductivity type, a conductive gate and a first dielectric layer, a source region of a second conductivity type formed in the body region, a heavily doped source contact diffusion region formed in the source region, a lightly doped drain region of the second conductivity type formed in the body region where the lightly doped drain region is a drift region of the MOS transistor, a heavily doped drain contact diffusion region of the second conductivity type formed in the lightly doped drain region; and an insulating trench formed in the lightly doped drain region adjacent the drain contact diffusion region. The insulating trench blocks a surface current path in the drift region thereby forming vertical current paths in the drift region around the bottom surface of the trench. | 02-03-2011 |
| 20100032753 | MOS Transistor Including Extended NLDD Source-Drain Regions For Improved Ruggedness - A MOS transistor includes a conductive gate insulated from a semiconductor layer by a dielectric layer, first and second lightly-doped diffusion regions formed self-aligned to respective first and second edges of the conductive gate, a first diffusion region formed self-aligned to a first spacer, a second diffusion region formed a first distance away from the edge of a second spacer, a first contact opening and metallization formed above the first diffusion region, and a second contact opening and metallization formed above the second diffusion region. The first lightly-doped diffusion region remains under the first spacer. The second lightly-doped diffusion region remains under the second spacer and extends over the first distance to the second diffusion region. The distance between the first edge of the conductive gate to the first contact opening is the same as the distance between the second edge of the conductive gate to the second contact opening. | 02-11-2010 |
| 20080237703 | HIGH VOLTAGE SEMICONDUCTOR DEVICES AND METHODS FOR FABRICATING THE SAME - An exemplary embodiment of a semiconductor device capable of high-voltage operation includes a substrate with a well region therein. A gate stack with a first side and a second side opposite thereto, overlies the well region. Within the well region, a doped body region includes a channel region extending under a portion of the gate stack and a drift region is adjacent to the channel region. A drain region is within the drift region and spaced apart by a distance from the first side thereof and a source region is within the doped body region near the second side thereof. There is no P-N junction between the doped body region and the well region. | 10-02-2008 |
| 20080237702 | LDMOS TRANSISTOR AND METHOD OF MAKING THE SAME - An LDMOS transistor includes a substrate having first conductive type, a first well having second conductive type, an isolation structure disposed on the substrate, and a deep doped region having first conductive type disposed between the first well and the substrate. The deep doped region is heavily doped, a portion of the deep doped region is disposed in the bottom portion of the first well, and the other portion of the deep doped region is disposed in the substrate. | 10-02-2008 |
| 20100090277 | LATERAL TRENCH FETS (FIELD EFFECT TRANSISTORS) - A semiconductor structure and associated method of formation. The semiconductor structure includes a semiconductor substrate, a first doped transistor region of a first transistor and a first doped Source/Drain portion of a second transistor on the semiconductor substrate, a second gate dielectric layer and a second gate electrode region of the second transistor on the semiconductor substrate, a first gate dielectric layer and a first gate electrode region of the first transistor on the semiconductor substrate, and a second doped transistor region of the first transistor and a second doped Source/Drain portion of the second transistor on the semiconductor substrate. The first and second gate dielectric layers are sandwiched between and electrically insulate the semiconductor substrate from the first and second gate electrode regions, respectively. The first and second gate electrode regions are totally above and totally below, respectively, the top substrate surface. | 04-15-2010 |
| 20090309157 | MOS TYPE SEMICONDUCTOR DEVICE - A MOS type semiconductor device, in which both improvement in radiation resistance and increase in withstand voltage is achieved, includes a nitride film formed on a LOCOS film and a PBSG film formed on the nitride film. The refractive index of the nitride film is set in a range of from 2.0 to 2.1 and the thickness of the nitride film is set in a range of from 0.1 Am to 0.5 μm to thereby provide the nitride film as a semi-insulative thin film. Of electron-hole pairs produced in the LOCOS film by γ-ray irradiation, holes low in mobility are let away to a source electrode via the nitride film to thereby suppress the amount of plus fixed electric charges stored in the LOCOS film. The provision of such a three-layer structure permits improvement in radiation resistance and increase in withstand voltage. | 12-17-2009 |
| 20100264490 | LDMOS WITH SELF ALIGNED VERTICAL LDD BACKSIDE DRAIN - A field effect transistor includes a semiconductor region of a first conductivity type having an upper surface and a lower surface, the lower surface of the semiconductor region extending over and abutting a substrate. A well regions of a second conductivity type is disposed within the semiconductor region. The field effect transistor also includes source regions of the first conductivity type disposed in the well regions and a gate electrode extending over each well region and overlapping a corresponding one of the source regions. Each gate electrode is insulated from the underlying well region by a gate dielectric. At least one LDD region of the first conductivity type is disposed in the semiconductor region between every two adjacent well regions such that the at least one LDD region is in contact with the two adjacent well regions between which it is disposed. A sinker region is disposed in the semiconductor region directly underneath the at least one LDD region such that the at least one LDD region and the sinker region are positioned along a vertical orientation between the upper and lower surfaces of the semiconductor region. | 10-21-2010 |
| 20110133275 | STRUCTURE AND METHOD FOR SEMICONDUCTOR POWER DEVICES - A semiconductor device includes a semiconductor-on-insulator region on a substrate. The semiconductor-on-insulator region includes a first semiconductor region overlying a dielectric region. The device includes an MOS transistor and a bipolar transistor. The MOS transistor has a drain region, a body region, and a source region in the first semiconductor region. The MOS transistor also includes a gate. The device also includes a second semiconductor region overlying the substrate and adjacent to the drain region, and a third semiconductor region overlying the substrate and adjacent to the second semiconductor region. The bipolar transistor includes has the drain region of the MOS transistor as an emitter, the second semiconductor region as a base, and the third semiconductor region as a collector. Accordingly, the drain of the MOS transistor also functions as the emitter of the bipolar transistor. Additionally, the gate and the base are coupled by a resistive element. | 06-09-2011 |
| 20120187483 | Double diffused metal oxide semiconductor device and manufacturing method thereof - The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: an isolation structure for defining device regions; a gate with a ring-shaped structure; a drain located outside the ring; and a lightly doped drain, a source, and a body electrode located inside the ring. To increase the sub-threshold voltage at the corners of the gate, the corners are located completely on the isolation structure, or the lightly doped drain is apart from the corners by a predetermined distance. | 07-26-2012 |
| 20100006933 | Stabilizing Breakdown Voltages by Forming Tunnels for Ultra-High Voltage Devices - A semiconductor structure includes a semiconductor substrate of a first conductivity type; a pre-high-voltage well (pre-HVW) in the semiconductor substrate, wherein the pre-HVW is of a second conductivity type opposite the first conductivity type; a high-voltage well (HVW) over the pre-HVW, wherein the HVW is of the second conductivity type; a field ring of the first conductivity type occupying a top portion of the HVW; and a tunnel of the first conductivity type in the pre-HVW and the HVW, and electrically connecting the field ring and the semiconductor substrate. | 01-14-2010 |
| 20090283826 | Semiconductor Device and Method of Forming High Voltage SOI Lateral Double Diffused MOSFET with Shallow Trench Insulator - A semiconductor device has a buried oxide layer formed over a substrate. An active silicon layer is formed over the buried oxide layer. A drain region is formed in the active silicon layer. An LDD drift region is formed in the active silicon layer adjacent to the drain region. The drift region has a graded doping distribution. A co-implant region is formed in the active silicon. A source region is formed in the co-implant region. A shallow trench insulator is formed along a top surface of the LDD drift region. The shallow trench isolator has a length less than the LDD drift region. The shallow trench insulator terminates under the polysilicon gate and within the LDD drift region. A polysilicon gate is formed above the active silicon layer between the source region and LDD drift region and at least partially overlapping the shallow trench insulator. | 11-19-2009 |
| 20110169077 | Semiconductor device having a modified shallow trench isolation (STI) region and a modified well region - An apparatus is disclosed to increase a breakdown voltage of a semiconductor device. The semiconductor device includes a modified breakdown shallow trench isolation (STI) region to effectively reduce a drain to source resistance when compared to a conventional semiconductor device, thereby increasing the breakdown voltage of the semiconductor device when compared to the conventional semiconductor device. The modified breakdown STI region allows more current to pass from a source region to a drain region of the semiconductor device, thereby further increasing the break down voltage of the semiconductor device from that of the conventional semiconductor device. The semiconductor device may include a modified well region to further reduce the drain to source resistance of the semiconductor device. The modified breakdown STI region allows even more current to pass from a source region to a drain region of the semiconductor device, thereby further increasing the break down voltage of the semiconductor device from that of the conventional semiconductor device. | 07-14-2011 |
| 20110198690 | TRANSISTOR - A Metal Oxide Semiconductor (MOS) transistor comprising: a source; a gate; and a drain, the source, gate and drain being located in or on a well structure of a first doping polarity located in or on a substrate; wherein at least one of the source and the drain comprises a first structure comprising: a first region forming a first drift region, the first region being of a second doping polarity opposite the first doping polarity; a second region of the second doping polarity in or on the first region, the second region being a well region and having a doping concentration which is higher than the doping concentration of the first region; and a third region of the second doping polarity in or on the second region. Due to the presence of the second region the transistor may have a lower ON resistance when compared with a similar transistor which does not have the second region. The breakdown voltage may be influenced only to a small extent. | 08-18-2011 |
| 20090273029 | High Voltage LDMOS Transistor and Method - An LDMOS transistor structure and methods of making the same are provided. The structure includes a gate electrode extended on an upper boundary of an extension dielectric region that separates the gate electrode from the drain region of the LDMOS transistor. Moreover, at an area close to an edge of the extended gate electrode portion, the gate electrode further projects downwards into a convex-shaped recess or groove in the upper boundary of the extension dielectric region, forming a tongue. LDMOS transistors with this structure may provide improved suppression of hot carrier effects. | 11-05-2009 |
| 20080246083 | Recessed drift region for HVMOS breakdown improvement - A high-voltage metal-oxide-semiconductor (HVMOS) device having increased breakdown voltage and methods for forming the same are provided. The HVMOS device includes a semiconductor substrate; a gate dielectric on a surface of the semiconductor substrate; a gate electrode on the gate dielectric; a source/drain region adjacent and horizontally spaced apart from the gate electrode; and a recess in the semiconductor substrate and filled with a dielectric material. The recess is between the gate electrode and the source/drain region, and is horizontally spaced apart from the gate electrode. | 10-09-2008 |
| 20080283911 | High-voltage semiconductor device and method for manufacturing the same - A high-voltage semiconductor device and a method for manufacturing the same are disclosed. The disclosed high-voltage semiconductor device includes a semiconductor substrate, a first N type well in the semiconductor substrate, a first P type well in the first N type well, second N type wells in the first N type well along a periphery of the first P type well, a gate insulating film and a gate electrode on the first P type well, and first heavily-doped N type impurity regions in the first P type well at opposite sides of the gate electrode. | 11-20-2008 |
| 20100237412 | SEMICONDUCTOR DEVICES AND METHODS FOR MANUFACTURING A SEMICONDUCTOR DEVICE - In various embodiments, a semiconductor device is provided. The semiconductor device may include a first source/drain region, a second source/drain region, an active region electrically coupled between the first source/drain region and the second source/drain region, a trench disposed between the second source/drain region and at least a portion of the active region, a first isolation layer disposed over the bottom and the sidewalls of the trench, electrically conductive material disposed over the isolation layer in the trench, a second isolation layer disposed over the active region, and a gate region disposed over the second isolation layer. The electrically conductive material may be coupled to an electrical contact. | 09-23-2010 |
| 20080258214 | Semiconductor Device and Method of Fabricating the Same - Provided are a semiconductor device and a method of fabricating the semiconductor device. The semiconductor device can provide a trench MOS transistor having an up-drain structure. The semiconductor device can include a first conductive type well in a semiconductor substrate, a second conductive type well on the first conductive type well, trenches formed by removing portions of the second conductive type well and the first conductive type well; gates provided in the trenches with a gate dielectric being between each gate and the walls of the trench, a first conductive type source region and a second conductive type body region on the second conductive type well, the first conductive type source region surrounding a lateral surface of the gate, and a common drain between the gates, the common drain being connected to the first conductive type well. | 10-23-2008 |
| 20110186926 | Semiconductor device having a lightly doped semiconductor gate and method for fabricating same - According to one embodiment, a semiconductor device comprises a high-k gate dielectric overlying a well region having a first conductivity type formed in a semiconductor body, and a semiconductor gate formed on the high-k gate dielectric. The semiconductor gate is lightly doped so as to have a second conductivity type opposite the first conductivity type. The disclosed semiconductor device, which may be an NMOS or PMOS device, can further comprise an isolation region formed in the semiconductor body between the semiconductor gate and a drain of the second conductivity type, and a drain extension well of the second conductivity type surrounding the isolation region in the semiconductor body. In one embodiment, the disclosed semiconductor device is fabricated as part of an integrated circuit including one or more CMOS logic devices. | 08-04-2011 |
| 20090140334 | Transistor, display driver integrated circuit including a transistor, and a method of fabricating a transistor - A transistor, a display driver integrated circuit having the transistor, and a method for fabricating a transistor are provided. A transistor, according to example embodiments, may include a substrate with a device active region defined by an isolation layer, wherein the device active region may include a source active region, a channel active region, and a drain active region and the channel active region may include a pair of edges contacting the isolation layer. The transistor, according to example embodiments, may also include a gate electrode overlapping the channel active region, wherein the edges are exposed beyond a periphery of the gate electrode, a gate dielectric between the gate electrode and the channel active region, and source and drain impurity regions within the source and drain active regions. | 06-04-2009 |
| 20110220996 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a semiconductor substrate, an element isolation insulating film, a source layer, a drain layer, a gate electrode, a gate insulating film, a first punch-through stopper layer, and a second punch-through stopper layer. The semiconductor substrate is a first conductivity type. The element isolation insulating film divides an upper layer portion of the semiconductor substrate into a plurality of first active regions. The source layer and the drain layer are a second conductivity type and are formed in spaced to each other in an upper portion of each of the first active regions. The gate electrode is provided in a region directly above a channel region on the semiconductor substrate located between the source layer and the drain layer. The gate insulating film is provided between the semiconductor substrate and the gate electrode. The first punch-through stopper layer of the first conductivity type is formed in a region of the first active region directly below the source layer and the second punch-through stopper layer of the first conductivity type is formed in a region of the first active region directly below the drain layer. The first punch-through stopper layer and the second punch-through stopper layer each has an effective impurity concentration higher than the semiconductor substrate. The first punch-through stopper layer and the source layer are separated in the channel region. The second punch-through stopper layer and the drain layer are separated in the channel region. | 09-15-2011 |
| 20110140199 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A high voltage ESD protective diode having high avalanche withstand capability and capable of being formed by using manufacturing steps identical with those for a high voltage transistor to be protected, the device having a structure in which a gate oxide film is formed over a substrate surface at a PN junction formed of an N type low concentration semiconductor substrate constituting a cathode region and a P type low concentration diffusion region constituting an anode region, and a gate electrode which is disposed overriding the gate oxide film and a field oxide film is connected electrically by way of a gate plug with an anode electrode, whereby an electric field at the PN junction is moderated upon avalanche breakdown to obtain a high avalanche withstand capability. Further, the withstand voltage can be adjusted by changing the length of the field oxide film. | 06-16-2011 |
| 20090250752 | Methods of fabricating semiconductor device having a metal gate pattern - A method of fabricating a semiconductor device having a metal gate pattern is provided in which capping layers are used to control the relative oxidation rates of portions of the metal gate pattern during a oxidation process. The capping layer may be a multilayer structure and may be etched to form insulating spacers on the sidewalls of the metal gate pattern. The capping layer(s) allow the use of a selective oxidation process, which may be a wet oxidation process utilizing partial pressures of both H | 10-08-2009 |
| 20100148252 | SEMICONDUCTOR DEVICE HAVING TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - One embodiment of inventive concepts exemplarily described herein may be generally characterized as a semiconductor device including an isolation region within a substrate. The isolation region may define an active region. The active region may include an edge portion that is adjacent to an interface of the isolation region and the active region and a center region that is surrounded by the edge portion. The semiconductor device may further include a gate electrode on the active region and the isolation region. The gate electrode may include a center gate portion overlapping a center portion of the active region, an edge gate portion overlapping the edge portion of the active region, and a first impurity region of a first conductivity type within the center gate portion and outside the edge portion. The semiconductor device may further include a gate insulating layer disposed between the active region and the gate electrode. | 06-17-2010 |
| 20100181616 | Semiconductor device and method of manufacturing the same - A semiconductor device where a plurality of DMOS transistors formed in a distributed manner on a semiconductor substrate can operate without being destroyed and a method of manufacturing the same. The on/off threshold voltage of a DMOS transistor at the innermost position from among three or more DMOS transistors formed in a distributed manner on a semiconductor is greater than the on/off threshold voltage of a DMOS transistor at the outermost position. | 07-22-2010 |
| 20100237413 | Semiconductor device and method for manufacturing semiconductor device - A semiconductor device has a LOCOS film formed on at least one of a drain side and a source side of a semiconductor substrate surface. A gate oxide film connected to the LOCOS film is formed on the semiconductor substrate surface. A conductive film is formed to cover the gate oxide film and the LOCOS film. A gate electrode is formed by etching the conductive film such that an end portion of the conductive film is positioned above the LOCOS film. The LOCOS film is etched such that an end portion of the LOCOS film is in alignment with an end portion of the gate electrode, thereby forming a recessed portion in a part of the semiconductor substrate surface from which the LOCOS film has been removed. A side wall spacer is formed to cover a side surface of the gate electrode such that a bottom surface of the side wall spacer contacts a surface of the recessed portion. A drain region and a source region are formed by doping a impurity to the semiconductor substrate surface on either side of the gate electrode and the side wall spacer. | 09-23-2010 |
| 20100237411 | LDMOS with double LDD and trenched drain - A LDMOS with double LDD and trenched drain is disclosed. According to some preferred embodiment of the present invention, the structure contains a double LDD region, including a high energy implantation to form lightly doped region and a low energy implantation thereon to provide a low resistance path for current flow without degrading breakdown voltage. At the same time, a P+ junction made by source mask is provided underneath source region to avoid latch-up effect from happening. | 09-23-2010 |
| 20110108913 | LDMOS WITH DOUBLE LDD AND TRENCHED DRAIN - A LDMOS with double LDD and trenched drain is disclosed. According to some preferred embodiment of the present invention, the structure contains a double LDD region, including a high energy implantation to form lightly doped region and a low energy implantation thereon to provide a low resistance path for current flow without degrading breakdown voltage. At the same time, a P+ junction made by source mask is provided underneath source region to avoid latch-up effect from happening. | 05-12-2011 |
| 20100127326 | MOS transistor with a reduced on-resistance and area product - According to an exemplary embodiment, a MOS transistor, such as an LDMOS transistor, includes a gate having a first side situated immediately adjacent to at least one source region and at least one body tie region. The MOS transistor further includes a drain region spaced apart from a second side of the gate. The MOS transistor further includes a body region in contact with the at least one body tie region, where the at least one body tie region is electrically connected to the at least one source region. The MOS transistor further includes a lightly doped region separating the drain region from the second side of the gate. The lightly doped region can isolate the body region from an underlying substrate. | 05-27-2010 |
| 20100044789 | Integrated Circuit with a Laterally Diffused Metal Oxide Semiconductor Device and Method of Forming the Same - An integrated circuit with a transistor advantageously embodied in a laterally diffused metal oxide semiconductor device having a gate located over a channel region recessed into a semiconductor substrate and a method of forming the same. In one embodiment, the transistor includes a source/drain including a lightly or heavily doped region adjacent the channel region, and an oppositely doped well extending under the channel region and a portion of the lightly or heavily doped region of the source/drain. The transistor also includes a channel extension, within the oppositely doped well, under the channel region and extending under a portion of the lightly or heavily doped region of the source/drain. | 02-25-2010 |
| 20110233671 | THRESHOLD VOLTAGE ADJUSTMENT OF A TRANSISTOR - A threshold voltage adjusted long-channel transistor fabricated according to short-channel transistor processes is described. The threshold-adjusted transistor includes a substrate with spaced-apart source and drain regions formed in the substrate and a channel region defined between the source and drain regions. A layer of gate oxide is formed over at least a part of the channel region with a gate formed over the gate oxide. The gate further includes at least one implant aperture formed therein with the channel region of the substrate further including an implanted region within the channel between the source and drain regions. Methods for forming the threshold voltage adjusted transistor are also disclosed. | 09-29-2011 |
| 20090184368 | IC CHIP - An IC chip, including a switch LDMOS device and an analog LDMOS device, is configured on a substrate having a first conductive type. Components of the two LDMOS devices respectively include two gate conductive layers configured on two first active regions of the substrate. A common source contact region having a second conductive type is configured in a second active region, which is configured between the two first active regions. An isolation structure is included for isolating the second active region and the first active regions. The isolation structure between the first active regions and the second active region has a length “A” extending along a longitudinal direction of a channel under each gate conductive layer, and each gate conductive layer on each first active region has a length “L” extending along the longitudinal direction of the channel, the two LDMOS devices have different A/L values. | 07-23-2009 |
| 20090072308 | Laterally diffused metal-oxide-semiconductor device and method of making the same - A laterally diffused metal-oxide-semiconductor (LDMOS) device as well as a method of making the same is disclosed. A gate is formed on a semiconductor substrate between a source region and a drain region with one side laterally extending onto a part of a field oxide layer and the opposite side beside the source region. A gate dielectric layer is formed between the gate and the semiconductor substrate, wherein the gate dielectric layer comprises two or more portions having different thicknesses arranged laterally in a way that the thicknesses of the portions gradually increase from one side beside the source doping region to the opposite side bordering the field oxide layer. With such structure, the hot carrier impact is minimized and the gate length can be scaled down to gain I | 03-19-2009 |
| 20110024837 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a gate formed over a substrate, a junction region formed in the substrate at both sides of the gate, and a depletion region expansion prevention layer surrounding sidewalls of the junction region in the substrate. | 02-03-2011 |
| 20100163983 | Semiconductor Device and Method for Fabricating the Same - Semiconductor devices and methods for fabricating the same are disclosed. The semiconductor device includes gate electrodes having sidewall spacers on a semiconductor substrate, double diffusion drain regions in the semiconductor substrate adjacent to the sidewall spacers, double diffusion junction regions aligned with the gate electrodes, and source/drain regions in the double diffusion junction regions. | 07-01-2010 |
| 20090218620 | High power and high temperature semiconductor power devices protected by non-uniform ballasted sources - This invention discloses a semiconductor power device disposed on a semiconductor substrate supporting an epitaxial layer as a drift region composed of an epitaxial layer. The semiconductor power device further includes a super-junction structure includes a plurality of doped sidewall columns disposed in a multiple of epitaxial layers. The epitaxial layer have a plurality of trenches opened and filled with the multiple epitaxial layer therein with the doped columns disposed along sidewalls of the trenches disposed in the multiple of epitaxial layers. | 09-03-2009 |
| 20090032869 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device is provided, which comprises a first transistor and a second transistor formed in a semiconductor layer. The first transistor includes a first source region and a first drain region sandwiching a first gate electrode with the first source region. The second transistor includes an LDD region and a drift region sandwiching the second gate electrode with the LDD region, and a second drain region adjacent to the drift region to sandwich the second gate electrode with the second source region. The first gate electrode has a first sidewall formed on sides thereof and the second gate electrode has a second sidewall formed on sides thereof. The width of the former along the first insulator differs from the width of the latter along the second insulator. | 02-05-2009 |
| 20090032868 | HIGH PERFORMANCE POWER MOS STRUCTURE - A semiconductor device includes a source region and a drain region disposed in a substrate wherein the source and drain regions have a first type of dopant; a gate electrode formed on the substrate interposed laterally between the source and drain regions; a gate spacer disposed on the substrate and laterally between the source region and the gate electrode, adjacent a side of the gate electrode; and a conductive feature embedded in the gate spacer. | 02-05-2009 |
| 20090026539 | Method and Layout of Semiconductor Device with Reduced Parasitics - An semiconductor device is disclosed. The device includes a semiconductor body, a layer of insulating material disposed over the semiconductor body, and a region of gate electrode material disposed over the layer of insulating material. Also included are a source region adjacent to gate region and a drain region adjacent to the gate region. A gate connection is disposed over the semiconductor body, wherein the gate connection includes a region of gate electrode material electrically coupling a contact region to the gate electrode. An insulating region is disposed on the semiconductor body beneath the gate connection. | 01-29-2009 |
| 20100244130 | Structure and fabrication of field-effect transistor using empty well in combination with source/drain extensions or/and halo pocket - Insulated-gate field-effect transistors (“IGFETs”), both symmetric and asymmetric, suitable for a semiconductor fabrication platform that provides IGFETs for analog and digital applications, including mixed-signal applications, utilize empty-well regions in achieving high performance. A relatively small amount of semiconductor well dopant is near the top of each empty well. Each IGFET ( | 09-30-2010 |
| 20100244131 | Structure and fabrication of asymmetric field-effect transistor having asymmetric channel zone and differently configured source/drain extensions - An asymmetric insulated-gate field-effect transistor ( | 09-30-2010 |
| 20090321824 | SEMICONDUCTOR DEVICE - A semiconductor device includes a gate insulating film formed over a semiconductor substrate, a gate electrode formed over the gate insulating film, a source region formed in the semiconductor substrate, a first drain region formed on the other side of the gate electrode and formed in the semiconductor substrate, the first drain region having one end extending below the gate electrode, the first drain region having a first impurity concentration, a second drain region formed in the first drain region and spaced apart from the gate electrode by a first distance, the second drain region having a second impurity concentration higher than the first impurity concentration, a third drain region formed in the first drain region and spaced apart from the gate electrode by a second distance, the second distance being greater than the first distance, the third drain region having a third impurity concentration. | 12-31-2009 |
| 20080315304 | Thin silicon-on-insulator high voltage auxiliary gated transistor - A silicon (Si)-on-insulator (SOI) high voltage transistor is provided with an associated fabrication process. The method provides a SOI substrate with a Si top layer. A control channel and an adjacent auxiliary channel are formed in the Si top layer. A control gate overlies the control channel and an auxiliary gate overlies the auxiliary channel. A source region is formed adjacent the control channel, and a lightly doped drain (LDD) region is interposed between the auxiliary channel and the drain. An interior drain region is interposed between the control and auxiliary channels. Typically, the Si top layer has a thickness in the range of 20 to 1000 nm. In one aspect, the Si top layer in the source, control channel, interior drain, and auxiliary channel regions is thinned to a thickness in the range of 5 to 200 nm, and raised source, drain, LDD, and interior drain regions are formed. | 12-25-2008 |
| 20080315305 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A LDD layer of the second conduction type locates in the surface of a semiconductor layer beneath a sidewall insulator film. A source layer of the second conduction type is formed in the surface of the semiconductor layer at a position adjacent to the LDD layer. A resurf layer of the second conduction type is formed in the surface of the semiconductor layer at a position sandwiching the gate electrode with the LDD layer. A drain layer of the second conduction type is formed in the surface of the semiconductor layer at a position adjacent to the resurf layer. The resurf layer is formed in depth to have peaks of a first and a second impurity concentration in turn from the surface of the semiconductor layer. The peak of the first impurity concentration is smaller than the peak of the second impurity concentration. | 12-25-2008 |
| 20080290409 | HALO-FIRST ULTRA-THIN SOI FET FOR SUPERIOR SHORT CHANNEL CONTROL - Superior control of short-channel effects for an ultra-thin semiconductor-on-insulator field effect transistor (UTSOI-FET) is obtained by performing a halo implantation immediately after a gate reoxidation step. An offset is then formed and thereafter an extension implantation process is performed. This sequence of processing steps ensures that the halo implant is laterally separated from the extension implant by the width of the offset spacer. This construction produces equivalent or far superior short channel performance compared to conventional UTSOI-FETs. Additionally, the above processing steps permit the use of lower halo doses as compared to conventional processes. | 11-27-2008 |
| 20080265319 | METHOD OF PROVIDING ENHANCED BREAKDOWN BY DILUTED DOPING PROFILES IN HIGH-VOLTAGE TRANSISTORS - A method of fabricating high-voltage semiconductor devices, the semiconductor devices and a mask for implanting dopants in a semiconductor are described. | 10-30-2008 |
| 20080251841 | MOS TRANSISTOR AND MANUFACTURING METHOD THEREOF - The structure of the MOS transistor provided in this invention has LDD (lightly doped drain) and halo doped regions removed from the source, the drain or both regions in the substrate for improved linearity range when operated as a voltage-controlled resistor. The removal of the LDD and halo doped regions is performed by simply modifying the standard mask of the MOS process using a logic operation layer with no extra mask required. | 10-16-2008 |
| 20110133273 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device including a low-concentration impurity region formed on the drain side of an n-type MIS transistor, in a non-self-aligned manner with respect to an end portion of the gate electrode. A high-concentration impurity region is placed with a specific offset from the gate electrode and a sidewall insulating film. The semiconductor device enables the drain breakdown voltage to be sufficient and the on-resistance to decrease. A silicide layer is also formed on the surface of the gate electrode, thereby achieving gate resistance reduction and high frequency characteristics improvement. | 06-09-2011 |
| 20100308404 | Field-Effect Transistor and Method for Producing a Field-Effect Transistor - A semiconductor body ( | 12-09-2010 |
| 20110049620 | Method for fabricating a MOS transistor with source/well heterojunction and related structure - According to an exemplary embodiment, a method for fabricating a MOS transistor, such as an LDMOS transistor, includes forming a gate stack over a well. The method further includes forming a recess in the well adjacent to a first sidewall of the gate stack. The method further includes forming a source region in the recess such that a heterojunction is formed between the source region and the well. The method further includes forming a drain region spaced apart from a second sidewall of the gate stack. In one embodiment, the source region can comprise silicon germanium and the well can comprise silicon. In another embodiment, the source region can comprise silicon carbide and the well can comprise silicon. | 03-03-2011 |
| 20100059817 | POWER MOSFET WITH A GATE STRUCTURE OF DIFFERENT MATERIAL - A semiconductor device includes a semiconductor layer of a first conductivity type and a first doping concentration. A first semiconductor region, used as drain, of the first conductivity type has a lower doping concentration than the semiconductor layer and is over the semiconductor layer. A gate dielectric is over the first semiconductor region. A gate electrode over the gate dielectric has a metal-containing center portion and first and second silicon portions on opposite sides of the center portion. A second semiconductor region, used as a channel, of the second conductivity type has a first portion under the first silicon portion and the gate dielectric. A third semiconductor region, used as a source, of the first conductivity type is laterally adjacent to the first portion of the second semiconductor region. The metal-containing center portion, replacing silicon, increases the source to drain breakdown voltage. | 03-11-2010 |
| 20110133274 | LATERAL DOUBLE-DIFFUSED MOSFET - A LDMOS transistor is implemented in a first impurity region on a substrate. The LDMOS transistor has a source that includes a second impurity region. The second impurity region is implanted into the surface of the substrate within the first impurity region. Additionally, the LDMOS transistor has a drain that includes a third impurity region. The third impurity region is implanted into the surface of the substrate within the first impurity region. The third impurity region is spaced a predetermined distance away from a gate of the LDMOS transistor. The drain of the LDMOS transistor further includes a fourth impurity region within the third impurity region. The fourth impurity region provides an ohmic contact for the drain. | 06-09-2011 |
| 20110215403 | High Voltage Metal Oxide Semiconductor Device and Method for Making Same - The present invention discloses a high voltage metal oxide semiconductor (HVMOS) device and a method for making same. The high voltage metal oxide semiconductor device comprises: a substrate; a gate structure on the substrate; a well in the substrate, the well defining a device region from top view; a first drift region in the well; a source in the well; a drain in the first drift region, the drain being separated from the gate structure by a part of the first drift region; and a P-type dopant region not covering all the device region, wherein the P-type dopant region is formed by implanting a P-type dopant for enhancing the breakdown voltage of the HVMOS device (for N-type HVMOS device) or reducing the ON resistance of the HVMOS device (for P-type HVMOS device). | 09-08-2011 |
| 20100019318 | DEVICE FOR ESD PROTECTION CIRCUIT - A LDNMOS device for an ESD protection circuit including a P-type substrate and an N-type deep well region is provided. The P-type substrate includes a first area and a second area. The N-type deep well region is in the first and second areas of the P-type substrate. The LDNMOS device further includes a gate electrode disposed on the P-type substrate between the first and second areas, a P-type implanted region disposed in the first area of the P-type substrate, an N-type grade region disposed in the N-type deep well region of the first area, an N-type first doped region disposed in the N-type grade region, a P-type body region disposed in the N-type deep well region of the second area, an N-type second doped region disposed in the P-type body region, and a P-type doped region disposed in the P-type body region and adjacent to the N-type second doped region. | 01-28-2010 |
| 20110037121 | INPUT/OUTPUT ELECTROSTATIC DISCHARGE DEVICE WITH REDUCED JUNCTION BREAKDOWN VOLTAGE - An I/O electrostatic discharge (ESD) device having a gate electrode over a substrate, a gate dielectric layer between the gate electrode and the substrate, a pair of sidewall spacers respectively disposed on two opposite sidewalls of the gate electrode, a first lightly doped drain (LDD) region disposed under one of the sidewall spacers, a source region disposed next to the first LDD region, a second LDD region disposed under the other sidewall spacer, and a drain region disposed next to the second LDD region, wherein a doping concentration of the second LDD region is larger than a doping concentration of the first LDD region. | 02-17-2011 |
| 20080203474 | Semiconductor device having offset spacer and method of forming the same - A method of forming a semiconductor device having an offset spacer may include forming a gate electrode on a semiconductor substrate. An etch stop layer including a nitride may be formed on the entire surface of the semiconductor substrate having the gate electrode. First spacers may be formed on the sidewalls of the gate electrode. The first spacers may be formed of a material layer having an etch selectivity with respect to the etch stop layer. The etch stop layer may be exposed on the semiconductor substrate on both sides of the gate electrode. Lightly-doped drain (LDD) regions may be formed in the semiconductor substrate using the gate electrode and the first spacers as an ion implantation mask. Second spacers may be formed on the first spacers. Accordingly, a semiconductor device having an offset spacer may be provided. | 08-28-2008 |
| 20100155839 | LATERAL MOSFET WITH SUBSTRATE DRAIN CONNECTION - In one form a lateral MOSFET includes an active gate positioned laterally between a source region and a drain region, the drain region extending from an upper surface of a monocrystalline semiconductor body to a bottom surface of the monocrystalline semiconductor body, and a non-active gate positioned above the drain region. In another form the lateral MOSFET includes a gate positioned laterally between a source region and a drain region, the drain region extending from an upper surface of a monocrystalline semiconductor body to a bottom surface of the monocrystalline semiconductor body, the source region and the drain region being of a first conductivity type, a heavy body region of a second conductivity type in contact with and below the source region, and the drain region comprising a lightly doped drain (LDD) region proximate an edge of the gate and a sinker extending from the upper surface of the monocrystalline body to the bottom surface of the monocrystalline semiconductor body. | 06-24-2010 |
| 20110073943 | TRUE CSP POWER MOSFET BASED ON BOTTOM-SOURCE LDMOS - A semiconductor package may comprise a semiconductor substrate, a MOSFET device having a plurality cells formed on the substrate, and a source region common to all cells disposed on a bottom of the substrate. Each cell comprises a drain region on a top of the semiconductor device, a gate to control a flow of electrical current between the source and drain regions, a source contact proximate the gate; and an electrical connection between the source contact and source region. At least one drain connection is electrically coupled to the drain region. Source, drain and gate pads are electrically connected to the source region, drain region and gates of the devices. The drain, source and gate pads are formed on one surface of the semiconductor package. The cells are distributed across the substrate, whereby the electrical connections between the source contact of each device and the source region are distributed across the substrate. | 03-31-2011 |
| 20120306011 | Integrated Circuit With A Laterally Diffused Metal Oxide Semiconductor Device And Method Of Forming The Same - An integrated circuit with a transistor advantageously embodied in a laterally diffused metal oxide semiconductor device having a gate located over a channel region recessed into a semiconductor substrate and a method of forming the same. In one embodiment, the transistor includes a source/drain including a lightly or heavily doped region adjacent the channel region, and an oppositely doped well extending under the channel region and a portion of the lightly or heavily doped region of the source/drain. The transistor also includes a channel extension, within the oppositely doped well, under the channel region and extending under a portion of the lightly or heavily doped region of the source/drain. | 12-06-2012 |
| 20120037987 | Coupling Well Structure for Improving HVMOS Performance - A semiconductor structure includes a substrate, a first well region of a first conductivity type overlying the substrate, a second well region of a second conductivity type opposite the first conductivity type overlying the substrate, a cushion region between and adjoining the first and the second well regions, an insulation region in a portion of the first well region and extending from a top surface of the first well region into the first well region, a gate dielectric extending from over the first well region to over the second well region, wherein the gate dielectric has a portion over the insulation region, and a gate electrode on the gate dielectric. | 02-16-2012 |
| 20120037985 | APPARATUS WITH CAPACITIVE COUPLING AND ASSOCIATED METHODS - Transistors are described, along with methods and systems that include them. In one such transistor, a field plate is capacitively coupled between a first terminal and a second terminal. A potential in the field plate modulates dopant in a diffusion region in a semiconductor material of the transistor. Additional embodiments are also described. | 02-16-2012 |
| 20120043608 | Partially Depleted Dielectric Resurf LDMOS - An partially depleted Dieler LDMOSFET transistor ( | 02-23-2012 |
| 20120037986 | SEMICONDUCTOR DEVICE - A semiconductor device includes a body region of a first conductivity type and a gate pattern disposed on the body region. The gate pattern has a linear portion extending in a first direction and having a uniform width and a bending portion extending from one end of the linear portion. The portion of a channel region located beneath the bending portion constitutes a channel whose length is greater than the length of the channel constituted by the portion of the channel region located beneath the linear portion. | 02-16-2012 |
| 20110156143 | Parasitic Vertical PNP Bipolar Transistor And Its Fabrication Method In Bicmos Process - This invention published a parasitic vertical PNP bipolar transistor in BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) process; the bipolar transistor comprises a collector, a base and an emitter. Collector is formed by active region with p-type ion implanting layer. It connects a p-type buried layer which formed in the bottom region of STI (Shallow Trench Isolation). The collector terminal connection is through the p-type buried layer and the adjacent active region. The base is formed by active region with n type ion implanting which is on the collector. Its connection is through the original p-type epitaxy layer after converting to n-type. The emitter is formed by the p-type epitaxy layer on the base region with heavy p-type doped. This invention also comprises the fabrication method of this parasitic vertical PNP bipolar in BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) process. And this PNP bipolar transistor can be used as the IO (Input/Output) device in high speed, high current and power gain BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) circuits. It also provides a device option with low cost. | 06-30-2011 |
| 20110156142 | HIGH VOLTAGE DEVICE WITH PARTIAL SILICON GERMANIUM EPI SOURCE/DRAIN - A semiconductor device is provided which includes a semiconductor substrate, a gate structure formed on the substrate, sidewall spacers formed on each side of the gate structure, a source and a drain formed in the substrate on either side of the gate structure, the source and drain having a first type of conductivity, a lightly doped region formed in the substrate and aligned with a side of the gate structure, the lightly doped region having the first type of conductivity, and a barrier region formed in the substrate and adjacent the drain. The barrier region is formed by doping a dopant of a second type of conductivity different from the first type of conductivity. | 06-30-2011 |
| 20120112276 | ANTI PUNCH-THROUGH LEAKAGE CURRENT METAL-OXIDE-SEMICONDUCTOR TRANSISTOR AND MANUFACTURING METHOD THEREOF - An anti punch-through leakage current MOS transistor and a manufacturing method thereof are provided. A high voltage deep first type well region and a first type light doping region are formed in a second type substrate. A mask with a dopant implanting opening is formed on the second type substrate. An anti punch-through leakage current structure is formed by implanting the first type dopant through the dopant implanting opening. A doping concentration of the first type dopant of the high voltage deep first type well region is less than that of the anti punch-through leakage current structure and greater than that of the high voltage deep first type well region. A second type body is formed by implanting a second type dopant through the dopant implanting opening. A gate structure is formed on the second type substrate. | 05-10-2012 |
| 20120012931 | SOI MOS DEVICE HAVING BTS STRUCTURE AND MANUFACTURING METHOD THEREOF - The present invention discloses a SOI MOS device having BTS structure and manufacturing method thereof. The source region of the SOI MOS device comprises: two heavily doped N-type regions, a heavily doped P-type region formed between the two heavily doped N-type regions, a silicide formed above the heavily doped N-type regions and the heavily doped P-type region, and a shallow N-type region which is contact to the silicide; an ohmic contact is formed between the heavily doped P-type region and the silicide thereon to release the holes accumulated in body region of the SOI MOS device and eliminate floating body effects thereof without increasing the chip area and also overcome the disadvantages such as decreased effective channel width of the devices in the BTS structure of the prior art. The manufacturing method comprises steps of: forming a heavily doped P-type region via ion implantation, forming a metal layer above the source region and forming a silicide via the heat treatment between the metal layer and the Si underneath. The device in the present invention could be fabricated via simplified fabricating process with great compatibility with traditional CMOS technology. | 01-19-2012 |
| 20120012930 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a semiconductor substrate, and first and second transistors. The substrate has a first conductivity type. The first and second transistors are provided on the substrate. The first and second transistors each include a gate electrode provided on the substrate, a gate insulating film provided between the substrate and the gate electrode, a source and a drain region of a second conductivity type, and a high-concentration channel region of the first conductivity type. The source and drain regions are provided in regions of an upper portion of the substrate. A region directly under the gate electrode is interposed between the regions. The high-concentration channel region is formed on a side of the source region of the region of the upper portion directly under the gate electrode. The high-concentration channel region has an effective impurity concentration higher than that of the upper portion. | 01-19-2012 |
| 20120018803 | LATERAL DRAIN MOSFET WITH SUBSTRATE DRAIN CONNECTION - In one form a lateral MOSFET includes an active gate positioned laterally between a source region and a drain region, the drain region extending from an upper surface of a monocrystalline semiconductor body to a bottom surface of the monocrystalline semiconductor body, and a non-active gate positioned above the drain region. In another form the lateral MOSFET includes a gate positioned laterally between a source region and a drain region, the drain region extending from an upper surface of a monocrystalline semiconductor body to a bottom surface of the monocrystalline semiconductor body, the source region and the drain region being of a first conductivity type, a heavy body region of a second conductivity type in contact with and below the source region, and the drain region comprising a lightly doped drain (LDD) region proximate an edge of the gate and a sinker extending from the upper surface of the monocrystalline body to the bottom surface of the monocrystalline semiconductor body. | 01-26-2012 |
| 20110062516 | Semiconductor device - Provided is a LOCOS offset MOS field-effect transistor in which a first lightly-doped N-type drain offset region with a LOCOS oxide film and a second lightly-doped N-type drain offset region without a LOCOS oxide film are formed in a drain-side offset region, and both the regions are covered with a gate electrode. Provision of the first lightly-doped N-type drain offset region mitigates an electric field applied to the first lightly-doped N-type drain offset region to increase a breakdown voltage. Provision of the second lightly-doped N-type drain offset region increases carriers within the second lightly-doped N-type drain offset region to obtain a high current drivability. | 03-17-2011 |
| 20110089490 | Method for fabricating a MOS transistor with reduced channel length variation and related structure - According to an exemplary embodiment, a method for fabricating a MOS transistor, such as an LDMOS transistor, includes forming a self-aligned lightly doped region in a first well underlying a first sidewall of a gate. The method further includes forming a self-aligned extension region under a second sidewall of the gate, where the self-aligned extension region extends into the first well from a second well. The method further includes forming a drain region spaced apart from the second sidewall of the gate. The method further includes forming a source region in the self-aligned lightly doped region and the first well. The self-aligned lightly doped region and the self-aligned extension region define a channel length of the MOS transistor, such as an LDMOS transistor. | 04-21-2011 |
| 20120126319 | LATERAL DIFFUSION FIELD EFFECT TRANSISTOR WITH DRAIN REGION SELF-ALIGNED TO GATE ELECTRODE - A disposable structure displaced from an edge of a gate electrode and a drain region aligned to the disposable structure is formed. Thus, the drain region is self-aligned to the edge of the gate electrode. The disposable structure may be a disposable spacer, or alternately, the disposable structure may be formed simultaneously with, and comprise the same material as, a gate electrode. After formation of the drain regions, the disposable structure is removed. The self-alignment of the drain region to the edge of the gate electrode provides a substantially constant drift distance that is independent of any overlay variation of lithographic processes. | 05-24-2012 |
| 20120313165 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device and its manufacturing method are disclosed. The semiconductor device comprises a gate, and source and drain regions on opposite sides of the gate, wherein a portion of a gate dielectric layer located above the channel region is thinner than a portion of the gate dielectric layer located at the overlap region of the drain and the gate. The thicker first thickness portion may ensure that the device can endure a higher voltage at the drain to gate region, while the thinner second thickness portion may ensure excellent performance of the device. | 12-13-2012 |
| 20120168862 | HIGH-VOLTAGE METAL-OXIDE-SEMICONDUCTOR DEVICE - A high-voltage MOS transistor includes a gate overlying an active area of a semiconductor substrate; a drain doping region pulled back away from an edge of the gate by a distance L; a first lightly doped region between the gate and the drain doping region; a source doping region in a first ion well; and a second lightly doped region between the gate and the source doping region. | 07-05-2012 |
| 20100052052 | Integrated Circuit with a Laterally Diffused Metal Oxide Semiconductor Device and Method of Forming the Same - An integrated circuit with a transistor advantageously embodied in a laterally diffused metal oxide semiconductor device having a gate located over a channel region recessed into a semiconductor substrate and a method of forming the same. In one embodiment, the transistor includes a source/drain including a lightly or heavily doped region adjacent the channel region, and an oppositely doped well extending under the channel region and a portion of the lightly or heavily doped region of the source/drain. The transistor also includes a channel extension, within the oppositely doped well, under the channel region and extending under a portion of the lightly or heavily doped region of the source/drain. | 03-04-2010 |
| 20120313166 | Semiconductor Device Having A Modified Shallow Trench Isolation (STI) Region And A Modified Well Region - An apparatus is disclosed to increase a breakdown voltage of a semiconductor device. The semiconductor device can include a modified breakdown shallow trench isolation (STI) region to effectively reduce its drain to source resistance when compared to a conventional semiconductor device. This reduction in the drain to source resistance increases the breakdown voltage of the semiconductor device when compared to the conventional semiconductor device by allowing more current to pass from a source region to a drain region of the semiconductor device. The semiconductor device can include a modified well region to reduce its drain to source resistance. The modified well region allows more current to pass from a source region to a drain region of the semiconductor device, thereby further increasing the break down voltage of the semiconductor device from that of the conventional semiconductor device. | 12-13-2012 |
| 20120175703 | SEMICONDUCTOR DEVICE - A source region and a drain region are disposed in a substrate. A gate insulating film is disposed on the substrate. A gate electrode is disposed on the gate insulating film. The gate electrode may include a first gate portion adjacent to the source region and a second gate portion adjacent to the drain region. The first and second gate portions have different work functions from each other. | 07-12-2012 |
| 20080296677 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME AND DATA PROCESSING SYSTEM - A semiconductor device is provided with a silicon pillar formed substantially perpendicularly to a main surface of a substrate, a gate electrode covering side surface of the silicon pillar via a gate insulation film, a conductive layer provided on an upper part of the silicon pillar, a cylindrical sidewall insulation film intervening between the conductive layer and the gate electrode so as to insulate therebetween. An inner wall of the side wall insulation film is in contact with the conductive layer, and an outer wall of the side wall insulation film is in contact with the gate electrode. | 12-04-2008 |
| 20100327347 | ELECTRONIC DEVICE INCLUDING A WELL REGION - An electronic device including an integrated circuit can include a buried conductive region and a semiconductor layer overlying the buried conductive region, and a vertical conductive structure extending through the semiconductor layer and electrically connected to the buried conductive region. The integrated circuit can further include a doped structure having an opposite conductivity type as compared to the buried conductive region, lying closer to an opposing surface than to a primary surface of the semiconductor layer, and being electrically connected to the buried conductive region. The integrated circuit can also include a well region that includes a portion of the semiconductor layer, wherein the portion overlies the doped structure and has a lower dopant concentration as compared to the doped structure. In other embodiment, the doped structure can be spaced apart from the buried conductive region. | 12-30-2010 |
| 20120261751 | RECTIFIER WITH VERTICAL MOS STRUCTURE - A method for manufacturing a rectifier with a vertical MOS structure is provided. A first trench structure and a first mask layer are formed at a first side of the semiconductor substrate. A second trench structure is formed in the second side of the semiconductor substrate. A gate oxide layer, a polysilicon structure and a metal sputtering layer are sequentially formed on the second trench structure. The rectifier further includes a wet oxide layer and a plurality of doped regions. The wet oxide layer is formed on a surface of the first multi-trench structure and in the semiconductor substrate. The doping regions are formed on a region between the semiconductor substrate and the second trench structure, and located beside the mask layer. The metal sputtering layer is formed on the first mask layer corresponding to the first trench structure. | 10-18-2012 |
| 20120267715 | HIGH VOLTAGE SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A high voltage semiconductor device is provided. The device includes a semiconductor substrate having a high voltage well with a first conductivity type therein. A gate structure is disposed on the semiconductor substrate of the high voltage well. A source doped region and a drain doped region are in the high voltage well on both sides of the gate structure, respectively. A lightly doped region with the first conductivity type is between the source and drain doped regions and relatively near to the source doped region. The disclosure also presents a method for fabricating a high voltage semiconductor device. | 10-25-2012 |
| 20110215404 | Method and Apparatus of Forming ESD Protection Device - The present disclosure provides a semiconductor device having a transistor. The transistor includes a source region, a drain region, and a channel region that are formed in a semiconductor substrate. The channel region is disposed between the source and drain regions. The transistor includes a first gate that is disposed over the channel region. The transistor includes a plurality of second gates that are disposed over the drain region. | 09-08-2011 |
| 20120273880 | Structure and Fabrication of Field-effect Transistor for Alleviating Short-channel Effects and/or Reducing Junction Capacitance | 11-01-2012 |
| 20120080752 | HIGH VOLTAGE METAL-OXIDE-SEMICONDUCTOR TRANSISTOR WITH STABLE THRESHOLD VOLTAGE AND RELATED MANUFACTURING METHOD - A high voltage metal-oxide-semiconductor (HVMOS) transistor includes a gate poly, wherein a channel is formed in an area projected from the gate poly in a thickness direction when the HVMOS is activated; two carrier drain drift regions, adjacent to the area projected from the gate poly, wherein at least one of the carrier drain drift regions has a gradient doping concentration; and two carrier plus regions, respectively locate within the two carrier drain drift regions, wherein the two carrier plus regions and the two carrier drain drift regions are communicating with each other through the channel when the HVMOS is activated. | 04-05-2012 |
| 20110309439 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a semiconductor substrate, a first conductivity-type region, a second conductivity-type source region, a gate insulating film and a gate electrode. The first conductivity-type region is provided in an upper layer portion of the semiconductor substrate. The second conductivity-type source region and a second conductivity-type drain region are arranged by being separated from each other in an upper layer portion of the first conductivity-type region. The gate insulating film is provided on the semiconductor substrate. The gate electrode is provided on the gate insulating film. An effective concentration of impurities in a channel region corresponding to a region directly below the gate electrode in the first conductivity-type region has a maximum at an interface between the gate insulating film and the channel region, and decreases toward a lower part of the channel region. | 12-22-2011 |
| 20130009243 | LDMOS WITH ENHANCED SAFE OPERATING AREA (SOA) AND METHOD THEREFOR - A laterally double diffused metal oxide semiconductor device includes a well region having a first conductivity, a first carrier redistribution region having the first conductivity type, wherein the second well region is under the well region, and a highly doped buried layer under the second well region. The highly doped buried layer has the first conductivity type and has a dopant concentration less than that of the well region and less than that of the first carrier redistribution region, and the buried layer is tied to the first well region. In addition, a method for forming the laterally double diffused metal oxide semiconductor device, which may use epitaxial growth, is disclosed. | 01-10-2013 |
