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Active channel region has a graded dopant concentration decreasing with distance from source region (e.g., double diffused device, DMOS transistor)

Subclass of:

257 - Active solid-state devices (e.g., transistors, solid-state diodes)

257213000 - FIELD EFFECT DEVICE

257288000 - Having insulated electrode (e.g., MOSFET, MOS diode)

257327000 - Short channel insulated gate field effect transistor

Patent class list (only not empty are listed)

Deeper subclasses:

Class / Patent application numberDescriptionNumber of patent applications / Date published
257337000 In integrated circuit structure 138
257343000 All contacts on same surface (e.g., lateral structure) 116
257336000 With lightly doped portion of drain region adjacent channel (e.g., LDD structure) 105
257339000 With means to increase breakdown voltage 89
257341000 Plural sections connected in parallel (e.g., power MOSFET) 74
257340000 With means (other than self-alignment of the gate electrode) to decrease gate capacitance (e.g., shield electrode) 5
20110266619SEMICONDUCTOR TRANSISTOR COMPRISING TWO ELECTRICALLY CONDUCTIVE SHIELD ELEMENTS - It is disclosed a semiconductor transistor, comprising a semiconductor substrate (11-03-2011
20090065862SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device comprising: a base layer of a first conductivity type selectively formed above a semiconductor substrate; a gate electrode formed on the base layer via the insulating film; a source layer of a second conductivity type selectively formed at a surface of the base layer at one side of the gate electrode; an channel implantation layer selectively formed at the surface of the base layer so as to be adjacent to the source layer below the gate electrode, the channel implantation layer having a higher concentration than the base layer; a RESURF layer of the second conductivity type selectively formed at the surface of the base layer at the other side of the gate electrode; and a drain layer of a second conductivity type being adjacent to the RESURF layer, a portion of the drain layer overlapping the base layer, and the drain layer having a higher concentration than the RESURF layer.03-12-2009
20110254088Power MOSFET With Embedded Recessed Field Plate and Methods of Fabrication - Semiconductor power devices, and related methods, wherein a recessed contact makes lateral ohmic contact to the source diffusion, but is insulated from the underlying recessed field plate (RFP). Such an insulated RFP is here referred to as an embedded recessed field plate (ERFP).10-20-2011
20100327349SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In a semiconductor device having an LDMOSFET, a source electrode is at the back surface thereof. Therefore, to reduce electric resistance between a source contact region in the top surface and the source electrode at the back surface, a poly-silicon buried plug is provided which extends from the upper surface into a P12-30-2010
20130175617Semiconductor Device With an Oversized Local Contact as a Faraday Shield - This application is directed to a semiconductor device with an oversized local contact as a Faraday shield, and methods of making such a semiconductor device. One illustrative device disclosed herein includes a transistor comprising a gate electrode and a source region, a source region conductor that is conductively coupled to the source region, a Faraday shield positioned above the source region conductor and the gate electrode and a first portion of a first primary metallization layer for an integrated circuit device positioned above and electrically coupled to the Faraday shield.07-11-2013
Entries
DocumentTitleDate
20130043532LATERAL HIGH-VOLTAGE TRANSISTOR AND ASSOCIATED METHOD FOR MANUFACTURING - The present disclosure discloses a lateral high-voltage transistor and associated method for making the same. The lateral high-voltage transistor comprises a semiconductor layer of a first conductivity type; a source region of a second conductivity type opposite to the first conductivity type in the semiconductor layer; a drain region of the second conductivity type in the semiconductor layer separated from the source region; a first isolation layer atop the semiconductor layer between the source region and the drain region; a first well region of the second conductivity type surrounding the drain region, extending towards the source region and separated from the source region; a second well region of the first conductivity type surrounding the source region; a gate positioned atop the first isolation layer above the second well region and an adjacent portion of the first well region; and a first buried layer of the first conductivity type under the first well region adjacent to the source region side of the lateral high-voltage transistor. A JFET is formed using the gate as a JFET top gate and the first buried layer as a JFET bottom gate.02-21-2013
20130026565LOW RDSON RESISTANCE LDMOS - A device having a salicide block spacer on a second side of a gate is disclosed. The use of the salicide block spacer indirectly reduces the blocking effects during the implantation processes, thereby lowering the Rdson without compromising the breakdown voltage of the device.01-31-2013
20110204441LOW ON-RESISTANCE LATERAL DOUBLE-DIFFUSED MOS DEVICE - A lateral-double diffused MOS device is provided. The device includes: a first well having a first conductive type and a second well having a second conductive type disposed in a substrate and adjacent to each other; a drain and a source regions having the first conductive type disposed in the first and the second wells, respectively; a field oxide layer (FOX) disposed on the first well between the source and the drain regions; a gate conductive layer disposed over the second well between the source and the drain regions extending to the FOX; a gate dielectric layer between the substrate and the gate conductive layer; a doped region having the first conductive type in the first well below a portion of the gate conductive layer and the FOX connecting to the drain region. A channel region is defined in the second well between the doped region and the source region.08-25-2011
20110186925SEMICONDUCTOR DEVICE - According to an embodiment, a semiconductor device includes a gate electrode formed on a semiconductor substrate via an insulating layer, a source region formed in the semiconductor substrate and including an extension region in a side closer to the gate electrode and a conductive impurity, the extension region including a side surface facing a horizontal direction and a bottom surface facing a vertical direction, a drain region formed in the semiconductor substrate and including an extension region in a side closer to the gate electrode and the conductive impurity, the extension region including a side surface facing the horizontal direction and a bottom surface facing a vertical direction, a first diffusion restraining layer formed in the semiconductor substrate, configured to prevent a diffusion of the conductive impurity in the source region, and including an impurity other than the conductive impurity, the first diffusion restraining layer being in contact with the side surface of the extension region of the source region and not in contact with the bottom surface of the extension region of the source region, and a second diffusion restraining layer formed in the semiconductor substrate and configured to prevent a diffusion of the impurity in the drain region, and including the impurity other than the conductive impurity, the second diffusion restraining layer being in contact with the side surface of the extension region of the drain region and not in contact with the bottom surface of the extension region of the drain region.08-04-2011
20090159967SEMICONDUCTOR DEVICE HAVING VARIOUS WIDTHS UNDER GATE - One embodiment of the invention relates to a semiconductor device formed over a semiconductor body. In this device, source and drain regions are formed in the body about lateral edges of a gate electrode and are separated from one another by a gate length. A channel region, which is configured to allow charged carriers to selectively flow between the source and drain regions during operation of the device, has differing widths under the gate electrode. These widths are generally perpendicular to the gate length. Other devices, methods, and systems are also disclosed.06-25-2009
20100163979TRUE CSP POWER MOSFET BASED ON BOTTOM-SOURCE LDMOS - A semiconductor package may comprise a semiconductor substrate, a MOSFET device having a plurality cells formed on the substrate, and a source region common to all cells disposed on a bottom of the substrate. Each cell comprises a drain region on a top of the semiconductor device, a gate to control a flow of electrical current between the source and drain regions, a source contact proximate the gate; and an electrical connection between the source contact and source region. At least one drain connection is electrically coupled to the drain region. Source, drain and gate pads are electrically connected to the source region, drain region and gates of the devices. The drain, source and gate pads are formed on one surface of the semiconductor package. The cells are distributed across the substrate, whereby the electrical connections between the source contact of each device and the source region are distributed across the substrate.07-01-2010
20130075815SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a semiconductor substrate and a first semiconductor element provided on the semiconductor substrate. The first semiconductor element includes: a first semiconductor; a second semiconductor layer; a third semiconductor layer; a first insulating layer; a first base region; a first source region; a first gate electrode; a first drift layer; a first drain region; a first source; and a first drain electrode. A concentration of an impurity element of the first conductivity type included in the first drift layer is lower than a concentration of an impurity element of the first conductivity type included in the first semiconductor layer. The concentration of the impurity element of the first conductivity type included in the first drift layer is higher than a concentration of an impurity element of the first conductivity type included in the second semiconductor layer.03-28-2013
20100044788SEMICONDUCTOR DEVICE WITH A CHARGE CARRIER COMPENSATION STRUCTURE AND PROCESS - A semiconductor device with a charge carrier compensation structure. In one embodiment, the semiconductor device has a central cell field with a gate and source structure. At least one bond contact area is electrically coupled to the gate structure or the source structure. A capacitance-increasing field plate is electrically coupled to at least one of the near-surface bond contact areas.02-25-2010
20130043533TRANSISTOR HAVING WING STRUCTURE - A semiconductor device includes an active region having a channel region and at least a wing region adjoining the channel region under the gate dielectric layer. The at least one wing region may be two symmetrical wing regions across the channel region.02-21-2013
20100109080PSEUDO-DRAIN MOS TRANSISTOR - A pseudo-drain MOS transistor is disclosed. The transistor includes a semiconductor substrate; a gate structure disposed on the semiconductor substrate; a source, a pseudo-drain, a drain, and a shallow trench isolation disposed in the semiconductor substrate, a p-well disposed in the semiconductor substrate and under the source and the gate structure; and an n-well disposed under the drain. The source and the pseudo-drain are disposed adjacent to two sides of the gate structure and the shallow trench isolation is disposed between the pseudo-drain and the drain, and the n-well is extended toward the pseudo-drain while not reaching the area below the gate structure.05-06-2010
20130082326SUPERJUNCTION LDMOS AND MANUFACTURING METHOD OF THE SAME - A superjunction LDMOS and its manufacturing method are disclosed. The superjunction LDMOS includes a diffused well in which a superjunction structure is formed; the superjunction structure has a depth less than the depth of the diffused well. The manufacturing method includes: provide a semiconductor substrate; form a diffused well in the semiconductor substrate by photolithography and high temperature diffusion; form an STI layer above the diffused well; form a superjunction structure in the diffused well by ion implantation, wherein the superjunction structure has a depth less than the depth of the diffused well; and form the other components of the superjunction LDMOS by subsequent conventional CMOS processes. The method is compatible with conventional CMOS processes and do not require high-cost and complicated special processes.04-04-2013
20130082325One-Time Programmable Device Having an LDMOS Structure and Related Method - According to one embodiment, a one-time programmable (OTP) device having a lateral diffused metal-oxide-semiconductor (LDMOS) structure comprises a pass gate including a pass gate electrode and a pass gate dielectric, and a programming gate including a programming gate electrode and a programming gate dielectric. The programming gate is spaced from the pass gate by a drain extension region of the LDMOS structure. The LDMOS structure provides protection for the pass gate when a programming voltage for rupturing the programming gate dielectric is applied to the programming gate electrode. A method for producing such an OTP device comprises forming a drain extension region, fabricating a pass gate over a first portion of the drain extension region, and fabricating a programming gate over a second portion of the drain extension region.04-04-2013
20100133611Isolated transistor - A transistor is formed inside an isolation structure which includes a floor isolation region and a trench extending from the surface of the substrate to the floor isolation region. The trench may be filled with a dielectric material or may have a conductive material in a central portion with a dielectric layer lining the walls of the trench.06-03-2010
20130069156SEMICONDUCTOR DEVICE - A semiconductor device formed on a silicon-on-insulator substrate includes a gate electrode, a gate insulation film, a drain diffusion region, a drift region, a body region, a plurality of source diffusion regions, and a plurality of charge collection diffusion regions. The source diffusion regions and charge collection diffusion regions are of mutually opposite conductivity types, and alternate with one another in the direction paralleling the width of the gate electrode. The half-width of each source diffusion region is equal to or less than the length of the gate electrode plus the half-length of the drift region.03-21-2013
20130069155Termination for Superjunction VDMOSFET - A termination for silicon superjunction VDMOSFET comprises heavily doped N-type silicon substrate which also works as drain region; drain metal is disposed on the back surface of the heavily doped N-type silicon substrate; an N-type silicon epitaxial layer is disposed on the heavily doped N-type silicon substrate; P-type silicon columns and N-type silicon columns are formed in the N-type silicon epitaxial layer, alternately arranged; a continuous silicon oxide layer is disposed on a part of silicon surface in the termination; structures that block the drift of mobile ions (several discontinuous silicon oxide layers arranged at intervals) are disposed on the other part of silicon surface in the termination. The structures that block the drift of mobile ions disposed in the termination region are able to effectively prevent movement of the mobile ions and improve the capability of the power device against the contamination induced by the mobile ions.03-21-2013
20130069154SEMICONDUCTOR CHIP INTEGRATING HIGH AND LOW VOLTAGE DEVICES - The present invention is directed to a semiconductor chip comprising a high voltage device and a low voltage device disposed thereon. The chip may be formed in several different configurations. For example, the semiconductor chip may include a NPN bipolar transistor, PNP bipolar transistor, a diode, an N channel DMOS transistor and the like. the first doped well being configured as a base of the DMOS transistor, a P channel DMOS transistor and the like. These and other embodiments are described in further detail below.03-21-2013
201300691523D STRUCTURED MEMORY DEVICES AND METHODS FOR MANUFACTURING THEREOF - A 3D structured nonvolatile semiconductor memory devices and methods for manufacturing are disclosed. One such device includes an n+ region at a source/drain region; a p+ region at the source/drain region; and a diffusion barrier material between the n+ region and the p+ region. The n+ region is substantially isolated from the p+ region.03-21-2013
20130069153High Voltage Device and Manufacturing Method Thereof - The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device includes: a substrate, having an isolation structure for defining a device region; a drift region located in the device region, wherein from top view, the drift region includes multiple sub-regions separated from one another but are electrically connected with one another; a source and a drain in the device region; and a gate on the surface of the substrate and between the source and drain in the device region.03-21-2013
20120112275Drain Extended CMOS with Counter-Doped Drain Extension - An integrated circuit containing a diode with a drift region containing a first dopant type plus scattering centers. An integrated circuit containing a DEMOS transistor with a drift region containing a first dopant type plus scattering centers. A method for designing an integrated circuit containing a DEMOS transistor with a counter doped drift region.05-10-2012
20120112274SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - According to one embodiment, a semiconductor device, including a semiconductor layer including a first region and a second region isolated from the first region, a source in a surface of the first region, a drain in a surface of the second region, a back-gate in the surface of the first region, an end of a drain side of the back-gate being located closer to the drain side than an end of the drain side of the source, a gate insulator on a surface of the semiconductor layer between the first region and the second region, a gate electrode on the gate insulator, a source electrode being contacted to both the source and the back-gate, and a drain electrode being contacted to the drain area.05-10-2012
20130062692Half-FinFET Semiconductor Device and Related Method - According to one embodiment, a half-FinFET semiconductor device comprises a gate structure formed over a semiconductor body. The semiconductor body includes a source region comprised of a plurality of fins extending beyond a first side of the gate structure and a continuous drain region adjacent a second side of the gate structure opposite the plurality of fins. The continuous drain region causes the half-FinFET semiconductor device to have a reduced ON-resistance. A method for fabricating a semiconductor device having a half-FinFET structure comprises designating source and drain regions in a semiconductor body, etching the source region to produce a plurality of source fins while masking the drain region during the etching to provide a continuous drain region, thereby resulting in the half-FinFET structure having a reduced ON-resistance.03-14-2013
20130062691SEMICONDUCTOR DEVICE INCLUDING AN N-WELL STRUCTURE - A device comprising a p-type base region, and a p-type region formed over the p-type base region and in contact with the p-type base region is disclosed. The device also includes an n-well region surrounded by the p-type region, wherein the n-well is formed from an n-type epitaxial layer and the p-type region is formed by counter-doping the same n-type epitaxial layer.03-14-2013
20090236661DMOS-transistor having improved dielectric strength of drain source voltages - A DMOS-transistor having enhanced dielectric strength includes a first well region. A highly doped source region is located in the first well region and is complementarily doped thereto. A highly doped bulk connection region is located in the first well region and has the same type of doping as the first well region. A gate electrode and a gate insulation layer for forming a transistor channel are included on a surface of the first well region. The DMOS-transistor further comprises an isolation structure, a highly doped drain doping region, and a second well complementarily doped to the first well region. The second well accommodates the first well region and the drain doping region. A highly doped region is formed at least adjacent to the second well and has the same type of doping as the second well for enhancing the dielectric strength of the highly doped source region.09-24-2009
20110278669SEMICONDUCTOR DEVICE - Disclosed is a high-voltage diode structure which realizes high reverse recovery capability and high maximum allowable forward current. The distance between a longitudinal end of a p well layer in an anode region and an element isolation region formed to surround the diode is 5 μm or shorter so as to allow a depletion layer to reach the element isolation region when a maximum rated reverse voltage is applied. During reverse recovery, the electric field strength at an end portion of a p well layer is reduced, hole current is reduced, and local temperature rises are reduced.11-17-2011
20120235232Short Channel Lateral MOSFET - A short channel Lateral MOSFET (LMOS) and method are disclosed with interpenetrating drain-body protrusions (IDBP) for reducing channel-on resistance while maintaining high punch-through voltage. The LMOS includes lower device bulk layer; upper source and upper drain region both located atop lower device bulk layer; both upper source and upper drain region are in contact with an intervening upper body region atop lower device bulk layer; both upper drain and upper body region are shaped to form a drain-body interface; the drain-body interface has an IDBP structure with a surface drain protrusion lying atop a buried body protrusion while revealing a top body surface area of the upper body region; gate oxide-gate electrode bi-layer disposed atop the upper body region forming an LMOS with a short channel length defined by the horizontal length of the top body surface area delineated between the upper source region and the upper drain region.09-20-2012
20120286360Field Effect Transistor Device with Self-Aligned Junction and Spacer - A field effect transistor device includes a substrate including a source region, a drain region, and a channel region disposed between the source region and the drain region, wherein the source region is connected to the channel region with a source extension portion, and the drain region is connected to the channel region with a drain extension portion, a first spacer portion disposed on the source region, the drain region and a first portion of the source extension portion, and a first portion of the drain extension portion, a second spacer portion disposed on a second portion of the source extension portion, and a second portion of the drain extension portion, a gate stack portion disposed on the channel region.11-15-2012
20120286359LATERAL-DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICE (LDMOS) AND FABRICATION METHOD THEREOF - A lateral-diffused metal oxide semiconductor device (LDMOS) includes a substrate, a first deep well, at least a field oxide layer, a gate, a second deep well, a first dopant region, a drain and a common source. The substrate has the first deep well which is of a first conductive type. The gate is disposed on the substrate and covers a portion of the field oxide layer. The second deep well having a second conductive type is disposed in the substrate and next to the first deep well. The first dopant region having a second conductive type is disposed in the second deep well. The doping concentration of the first dopant region is higher than the doping concentration of the second deep well.11-15-2012
20110284956SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREOF - The semiconductor device comprises a first impurity region having a second conductivity type and formed in a semiconductor layer having a first conductivity type; a body region adjacent to and in contact with the first impurity region and having the first conductivity type; a second impurity region formed in the first impurity region, having the second conductivity type, and having a depth smaller than the first impurity region; a source region formed in the body region and having the second conductivity type; a drain region formed in the second impurity region and having the second conductivity type; and a gate electrode formed via a gate insulating film. In a preferable mode of the semiconductor device, the second impurity region has a higher impurity concentration than the first impurity region and the first impurity region has a depth of 1 μm or smaller.11-24-2011
20090283824COOL IMPACT-IONIZATION TRANSISTOR AND METHOD FOR MAKING SAME - In one embodiment, the disclosure relates to a low-power semiconductor switching device, having a substrate supporting thereon a semiconductor body; a source electrode coupled to the semiconductor body at a source interface region; a drain electrode coupled to the semiconductor body at a drain interface region; a gate oxide film formed over a region of the semiconductor body, the gate oxide film interfacing between a gate electrode and the semiconductor body; wherein at least one of the source interface region or the drain interface region defines a sharp junction into the semiconductor body.11-19-2009
20100213543HIGH VOLTAGE DEVICE - A method of forming a device is presented. The method includes providing a substrate prepared with an active device region. The active device region includes gate stack layers of a gate stack including at least a gate electrode layer over a gate dielectric layer. A first mask is provided on the substrate corresponding to the gate. The substrate is patterned to at least remove portions of a top gate stack layer unprotected by the first mask. A second mask is also provided on the substrate with an opening exposing a portion of the first mask and the top gate stack layer. A channel well is formed by implanting ions through the opening and gate stack layers into the substrate.08-26-2010
20100213542ALTERNATING-DOPING PROFILE FOR SOURCE/DRAIN OF A FET - A semiconductor device is provided. In an embodiment, the device includes a substrate and a transistor formed on the substrate. The transistor may include a gate structure, a source region, and a drain region. The drain region includes an alternating-doping profile region. The alternating-doping profile region may include alternating regions of high and low concentrations of a dopant. In an embodiment, the transistor is a high voltage transistor.08-26-2010
20120025308METHOD FOR FABRICATING SEMICONDUCTOR DEVICE, METHOD FOR FABRICATING BIPOLAR-CMOS-DMOS - A semiconductor device fabricating method is described. The semiconductor device fabricating method comprises forming an epitaxial layer on a substrate, wherein the epitaxial layer is the same conductive type as the substrate. A first doped region having the different conductive type from the epitaxial layer is formed in the epitaxial layer. An annealing process is performed to diffuse dopants in the first doped region. A second doped region and an adjacent third doped region are formed in the first doped region. The second doped region is a different conductive type from that of the first doped region, and the third doped region is the same conductive type as that of the first doped region. A gate structure is formed on the epitaxial layer covering a portion of the second and the third doped regions.02-02-2012
20120025307METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - According to one embodiment, a method is disclosed for manufacturing a semiconductor device. The method can include simultaneously forming a first field insulating film and at least one second field insulating film on a front face side of a semiconductor layer. The at least one second field insulating film is separated from the first field insulating film and thinner than the first field insulating film. The method can include forming a drift region of a first conductivity type in a region of the semiconductor layer including the first field insulating film and the second field insulating film. The method can include forming a drain region of the first conductivity type in the front face of the semiconductor layer on a side of the first field insulating film. In addition, the method can include forming a source region of the first conductivity type in the front face of the semiconductor layer on a side of the second field insulating film.02-02-2012
20090267144SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes: an n-type first well diffusion layer; an n-type second well diffusion layer; a p-type source diffusion layer; a p-type third well diffusion layer; a p-type drain diffusion layer; a gate insulating film; a gate electrode; a device isolation insulating film; and a buffer layer. The buffer layer is formed between the first well diffusion layer and the third well diffusion layer to be in contact with an end of the third well diffusion layer opposing the source diffusion layer, and extends from immediately below the gate insulating film to a position deeper than a peak of curvature of impurity concentration distribution of the third well diffusion layer. The buffer layer has an impurity concentration lower than an impurity concentration in the third well diffusion layer.10-29-2009
20100123195LATERAL DOUBLE DIFFUSED MOS DEVICE AND METHOD FOR MANUFACTURING THE SAME - A lateral double diffused metal oxide semiconductor (LDMOS) device and a method of manufacturing the same. A LDMOS device may include a high voltage well formed over a substrate, a reduced surface field region formed thereover which may be adjacent a body region, and/or an isolation layer. An isolation layer may include a predetermined area formed over a reduced surface field region, may be partially overlapped with a top surface of a substrate and/or may include an area formed adjacent a high voltage well. A low voltage well may be formed over a substrate. A gate electrode may extend from a predetermined top surface of a body region to a predetermined top surface of an isolation layer. A drain region may be formed over a low voltage well. A source region may be formed over a body region and may have at least a portion formed under a gate electrode.05-20-2010
20100123194SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - In a semiconductor substrate of a first conductivity type, first to third drain offset regions of a second conductivity type are formed in that order in a bottom up manner. A body region of the first conductivity type is formed partly in the second drain offset region and partly in the third drain offset region. The second drain offset region has a lower impurity concentration than the first and third drain offset regions. A curvature portion of the body region is located in the second drain offset region.05-20-2010
20100078720Semiconductor device and method for manufacturing the same - There is provided a semiconductor device including a field effect transistor. The field effect transistor includes a p-type low concentration region formed over a surface of a substrate, an n-type drain-side diffusion region and an n-type source-side diffusion region formed over a surface of the p-type low concentration region, an element isolation insulating layer, and another element isolation insulating layer. A p-type high concentration region, which has an impurity concentration higher than the impurity concentration of the p-type low concentration region, is formed below the n-type source-side diffusion region in the p-type low concentration region over a range at least from one end, which is opposite to the other end facing to the channel region, of the source-side diffusion region to one end, which is facing to the channel region, of the second element isolation insulating layer, when seen in a plan view.04-01-2010
20090045459SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - According to an aspect of an embodiment, a semiconductor device has a semiconductor substrate, a gate insulating film on the semiconductor substrate, a gate electrode formed on the gate insulating film, an impurity diffusion region formed in an area of the semiconductor substrate adjacent to the gate electrode to a first depth to the semiconductor substrate, the impurity diffusion region containing impurity, an inert substance containing region formed in the area of the semiconductor substrate to a second depth deeper than the first depth, the inert substance containing region containing an inert substance, and a diffusion suppressing region formed in the area of the semiconductor substrate to a third depth deeper than the second depth, the diffusion suppressing region containing a diffusion suppressing substance suppressing diffusion of the impurity.02-19-2009
20090108345LDMOS Device and Method of Fabrication - An LDMOS device and method of fabrication are provided. The LDMOS device has a substrate with a source region and a drain region formed in the substrate. An insulating layer is provided on a portion of the substrate between the source and the drain region, such that a planar interface is provided between the insulating layer and a surface of the substrate. An insulating member is then formed on a portion of the insulating layer, and a gate layer is formed over part of the insulating member and the insulating layer. By employing such a structure, it has been found that a flat current path exists which enables the on-resistance to be decreased while maintaining a high breakdown voltage.04-30-2009
20130099312SEMICONDUCTOR STRUCTURE HAVING A THROUGH SUBSTRATE VIA (TSV) AND METHOD FOR FORMING - A semiconductor device structure includes a substrate having a background doping of a first concentration and of a first conductivity type. A through substrate via (TSV) is through the substrate. A device has a first doped region of a second conductivity on a first side of the substrate. A second doped region is around the TSV. The second doped region has a doping of a second concentration greater than the first concentration and is of the first conductivity type.04-25-2013
20120292697SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - A semiconductor device includes a substrate having first and second regions, a device isolation layer on the substrate defining an active region in each of the first and second regions, a gate pattern on the active region of each of the first and second regions, and a first dopant region and a second dopant region in each of the first and second regions of the substrate, the gate pattern in each of the first and second regions being between respective first and second dopant regions. At least one of upper surfaces of the first and second dopant regions in the second region is lower in level than an upper surface of the substrate under the gate pattern in the second region, the first and second dopant regions in the second region having an asymmetric recessed structure with respect to the gate pattern in the second region.11-22-2012
20080290408Thin silicon-on-insulator double-diffused metal oxide semiconductor transistor - A method is provided for fabricating a silicon (Si)-on-insulator (SOI) double-diffused metal oxide semiconductor transistor (DMOST) with a stepped channel thickness. The method provides a SOI substrate with a Si top layer having a surface. A thinned area of the Si top layer is formed, and a source region is formed in the thinned Si top layer area. The drain region is formed in an un-thinned area of the Si top layer. The channel has a first thickness adjacent the source region with first-type dopant, and a second thickness, greater than the first thickness, adjacent the drain region. The channel also has a sloped thickness between the first and second thicknesses. The second and sloped thicknesses have a second-type dopant, opposite of the first-type dopant. A stepped gate overlies the channel.11-27-2008
20080277723Semiconductor Device - In one embodiment of the present invention, a high withstand voltage transistor is disclosed having small sizes including an element isolating region. The semiconductor device is provided with the element isolating region formed on a semiconductor substrate; an active region demarcated by the element isolating region; a gate electrode formed on the semiconductor substrate in the active region by having a gate insulating film in between; a channel region arranged in the semiconductor substrate under the gate electrode; a source region and a drain region positioned on the both sides of the gate electrode; and a drift region positioned between one of or both of the source region and the drain region and the channel region. One of or both of the source region and the drain region are at least partially positioned on the element isolating region, and are connected with the channel region through the drift region.11-13-2008
20080296676SOI FET With Source-Side Body Doping - An SOI FET device with improved floating body is proposed. Control of the body potential is accomplished by having a body doping concentration next to the source electrode higher than the body doping concentration next to the drain electrode. The high source-side dopant concentration leads to elevated forward leakage current between the source electrode and the body, which leakage current effectively locks the body potential to the source electrode potential. Furthermore, having the source-to-body junction capacitance larger than the drain-to-body junction capacitance has additional advantages in device operation. The device has no structure fabricated for the purpose of electrically connecting the body potential to other elements of the device.12-04-2008
20100200916SEMICONDUCTOR DEVICES - In an embodiment, a semiconductor device is provided. The semiconductor device may include a substrate having a main processing surface, a first source/drain region comprising a first material of a first conductivity type, a second source/drain region comprising a second material of a second conductivity type, wherein the second conductivity type is different from the first conductivity type, a body region electrically coupled between the first source/drain region and the second source/drain region, wherein the body region extends deeper into the substrate than the first source/drain region in a first direction that is perpendicular to the main processing surface of the substrate, a gate dielectric disposed over the body region, and a gate region disposed over the gate dielectric, wherein the gate region overlaps with at least a part of the first source/drain region and with a part of the body region in the first direction.08-12-2010
20100200915LATERAL TRENCH MOSFET HAVING A FIELD PLATE - One embodiment relates to an integrated circuit that includes a lateral trench MOSFET disposed in a semiconductor body. The lateral trench MOSFET includes source and drain regions having a body region therebetween. A gate electrode region is disposed in a trench that extends beneath the surface of the semiconductor body at least partially between the source and drain. A gate dielectric separates the gate electrode region from the semiconductor body. In addition, a field plate region in the trench is coupled to the gate electrode region, and a field plate dielectric separates the field plate region from the semiconductor body. Other integrated circuits and methods are also disclosed.08-12-2010
20090321822HIGH-VOLTAGE TRANSISTOR WITH IMPROVED HIGH STRIDE PERFORMANCE - A high voltage NMOS transistor is disclosed where the p-doped body is isolated against the p-doped substrate by a DN well having a pinch-off region where the depth of the DN-well is at minimum. By the forming space charge region at raising drain potentials a shielding of the drain potential results because the space charge region touches the field oxide between source and drain at the pinch-off region. An operation at the high side at enhanced voltage levels is possible.12-31-2009
20110220995Semiconductor Device Having Multi-Thickness Gate Dielectric - A semiconductor device is provided that, in an embodiment, is in the form of a high voltage MOS (HVMOS) device. The device includes a semiconductor substrate and a gate structure formed on the semiconductor substrate. The gate structure includes a gate dielectric which has a first portion with a first thickness and a second portion with a second thickness. The second thickness is greater than the first thickness. A gate electrode is disposed on the first and second portion. In an embodiment, a drift region underlies the second portion of the gate dielectric. A method of fabricating the same is also provided.09-15-2011
20090085110SEMICONDUCTOR DEVICE EMPLOYING PRECIPITATES FOR INCREASED CHANNEL STRESS - A method for fabricating a semiconductor device including implanting a selected material at a desired target depth below a surface of a silicon substrate, performing an annealing process to create a band of precipitates formed from the selected material and the silicon of the silicon substrate at the desired target depth, and forming a source region and a drain region in the substrate such that a channel region there between is positioned above the band of precipitates, wherein the desired target depth is such that a desired separation distance is achieved between the channel region and the band of precipitates, and wherein an average lattice constant of the band of precipitates is different from the average lattice constant of the silicon substrate so as to cause a stress in the channel region.04-02-2009
20090014790SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A semiconductor device includes a gate electrode formed through an insulating film in a groove having a first side surface adjacent to a source region and a base region, and a second conductive type first impurity region formed adjacent to a second side surface of the groove between the groove and a lead-out portion of a drain region existing below the base region so as to extend downward beyond a lower end of the groove.01-15-2009
20120104492LOW ON-RESISTANCE RESURF MOS TRANSISTOR - The present invention relates to a low on-resistance RESURF MOS transistor, comprising: a drift region; two isolation regions formed on the drift region; a first-doping-type layer disposed between the two isolation regions; and a second-doping-type layer disposed below the first-doping-type layer.05-03-2012
20090212360High-Voltage Transistor and Method for its Manufacture - A high-voltage transistor is provided with a well of a first conductivity type, which is arranged in a substrate (08-27-2009
20090242981SEMICONDUCTOR DEVICE - A semiconductor device includes: an epitaxial layer; a body layer, formed in the epitaxial layer, which includes a channel region; a source layer disposed in superposition on the body layer; a gate insulator, formed on the epitaxial layer, which is in a ring shape surrounding the source layer; a gate electrode formed through the gate insulator; a drift layer, formed in the epitaxial layer, which is in a ring shape surrounding the body layer; and a drain layer formed in the surface of the epitaxial layer and disposed opposite to the source layer. The body layer is disposed such that the boundary surface at an end in the gate-width direction is in contact with the undersurface of the gate insulator. The gate insulator has a thick film portion thicker than a part above the channel region in the gate-length direction at least in a part where the gate insulator is in contact with the boundary surface of the body layer at the end in the gate-width direction.10-01-2009
20090250751MOS DEVICE WITH LOW ON-RESISTANCE - Some of the embodiments of the present disclosure provide a metal oxide semiconductor (MOS) device comprising a drain region, a gate region surrounding the drain region and formed in a loop around the drain region, a plurality of source regions arranged around the gate region, wherein each source region is situated across from a corresponding side of the drain region, and a plurality of bulk regions arranged around the gate region, wherein one or more of the plurality of source regions separate one or more of the plurality of bulk regions from the gate region. Other embodiments are also described and claimed.10-08-2009
20120193707High voltage multigate device and manufacturing method thereof - The present invention discloses a high voltage multigate device and a manufacturing method thereof. The high voltage multigate device includes: a semiconductor fin doped with first conductive type impurities; a dielectric layer, which overlays a portion of the semiconductor fin; a gate which overlays the dielectric layer; a drain doped with second conductive type impurities, which is formed in the semiconductor fin or coupled to the semiconductor fin; a source doped with second conductive type impurities, which is formed in the semiconductor fin or coupled to the semiconductor fin, wherein the drain and the source are located at different sides of the gate; and a drift region or a well doped with second conductive type impurities, which is formed in the semiconductor fin at least between the drain and the gate.08-02-2012
20120193708Drive Current Increase in Field Effect Transistors by Asymmetric Concentration Profile of Alloy Species of a Channel Semiconductor Alloy - When forming sophisticated transistors, the channel region may be provided such that the gradient of the band gap energy of the channel material may result in superior charge carrier velocity. For example, a gradient in concentration of germanium, carbon and the like may be implemented along the channel length direction, thereby obtaining higher transistor performance.08-02-2012
20100148250METAL OXIDE SEMICONDUCTOR DEVICE - A metal oxide semiconductor device comprising a substrate, at least an isolation structure, a deep N-type well, a P-type well, a gate, a plurality of N-type extension regions, an N-type drain region, an N-type source region and a P-type doped region is provided. The N-type extension regions are disposed in the substrate between the isolation structures and either side of the gate, while the N-type drain region and the N-type source region are respectively disposed in the N-type extension regions at both sides of the gate. The P-type well surrounds the N-type extension regions, and the P-type doped region is disposed in the P-type well of the substrate and is isolated from the N-type source region by the isolation structure.06-17-2010
20130214352Dual Gate Lateral MOSFET - A dual gate lateral MOSFET comprises a drift region over a substrate, an isolation region formed in the drift region and a channel region formed in the drift region. The dual gate lateral MOSFET comprises a drain region formed in the drift region and a source region formed in the channel region, wherein the source region and drain region are formed on opposing sides of the isolation region. The dual gate lateral MOSFET further comprises a first gate and a second gate formed adjacent to the source region, wherein the first gate and the second gate are stacked together and separated by a dielectric layer.08-22-2013
20100176449SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device, includes: a semiconductor layer including a first semiconductor region of a first conductivity type and a second semiconductor region of the first conductivity type, the second semiconductor region having a first conductivity type impurity concentration lower than a first conductivity type impurity concentration of the first semiconductor region; a source region of a second conductivity type provided on the first semiconductor region; a drain region of the second conductivity type provided on the second semiconductor region; an insulating film provided on the semiconductor layer between the source region and the drain region; a gate electrode provided on the insulating film; and a drift region of the second conductivity type provided in a surface side portion of the semiconductor layer between the gate electrode and the drain region, the drift region being in contact with the drain region and having a second conductivity type impurity concentration lower than a second conductivity type impurity concentration of the drain region.07-15-2010
20100237410ULTRA-THIN SEMICONDUCTOR ON INSULATOR METAL GATE COMPLEMENTARY FIELD EFFECT TRANSISTOR WITH METAL GATE AND METHOD OF FORMING THEREOF - A method of forming a semiconductor device is provided that may include providing a semiconductor layer including a raised source and raised drain region that are separated by a recessed channel having a thickness of less than 20 nm, and forming a spacer on a sidewall of the raised source and drain region overlying a portion of the recessed channel. In a following process step, a channel implantation is performed that produces a dopant spike of opposite conductivity as the raised source and drain regions. Thereafter, the offset spacer is removed, and gate structure including a metal gate conductor is formed overlying the recessed channel.09-23-2010
20100148251SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes: a substrate on and/or over which a first conductive type well is formed; and an LDMOS device that includes a gate electrode and has a drain region formed in the substrate. The LDMOS device includes a trench formed on the substrate, a second conductive type body that is formed on one side of the trench and on the substrate therebeneath, and a first conductive type source region that is formed in the second conductive type body.06-17-2010
20100252881CMOS DIODES WITH DUAL GATE CONDUCTORS, AND METHODS FOR FORMING THE SAME - The present invention provides an improved CMOS diode structure with dual gate conductors. Specifically, a substrate comprising a first n-doped region and a second p-doped region is formed. A third region of either n-type or p-type conductivity is located between the first and second regions. A first gate conductor of n-type conductivity and a second gate conductor of p-type conductivity are located over the substrate and adjacent to the first and second regions, respectively. Further, the second gate conductor is spaced apart and isolated from the first gate conductor by a dielectric isolation structure. An accumulation region with an underlying depletion region can be formed in such a diode structure between the third region and the second or the first region, and such an accumulation region preferably has a width that is positively correlated with that of the second or the first gate conductor.10-07-2010
20100140698ELECTRONIC DEVICE INCLUDING A TRENCH AND A CONDUCTIVE STRUCTURE THEREIN AND A PROCESS OF FORMING THE SAME - An electronic device can include a first layer having a primary surface, a well region lying adjacent to the primary surface, and a buried doped region spaced apart from the primary surface and the well region. The electronic device can also include a trench extending towards the buried doped region, wherein the trench has a sidewall, and a sidewall doped region along the sidewall of the trench, wherein the sidewall doped region extends to a depth deeper than the well region. The first layer and the buried region have a first conductivity type, and the well region has a second conductivity type opposite that of the first conductivity type. The electronic device can include a conductive structure within the trench, wherein the conductive structure is electrically connected to the buried doped region and is electrically insulated from the sidewall doped region. Processes for forming the electronic device are also described.06-10-2010
20130126968HIGH VOLTAGE SEMICONDUCTOR DEVICE - A high voltage semiconductor device is provided. A first-polarity buried layer is formed in the substrate. A first high voltage second-polarity well region is located over the first-polarity buried layer. A second-polarity base region is disposed within the first high voltage second-polarity well region. A source region is disposed within the second-polarity base region. A high voltage deep first-polarity well region is located over the first-polarity buried layer and closely around the first high voltage second-polarity well region. A first-polarity drift region is disposed within the high voltage deep first-polarity well region. A gate structure is disposed over the substrate. A second high voltage second-polarity well region is located over the first-polarity buried layer and closely around the high voltage deep first-polarity well region. A deep first-polarity well region is located over the first-polarity buried layer and closely around the second high voltage second-polarity well region.05-23-2013
20090273028Short Channel Lateral MOSFET and Method - A short channel Lateral MOSFET (LMOS) and method are disclosed with interpenetrating drain-body protrusions (IDBP) for reducing channel-on resistance while maintaining high punch-through voltage. The LMOS includes: 11-05-2009
20090114987Semiconductor device and manufacturing method thereof - A semiconductor device includes a semiconductor layer with an impurity of a first conductivity type diffused therein, and a local insulating layer, source layer, and a drain layer formed therein. The drain layer has an impurity of a second conductivity type opposite to the first conductivity type. A gate electrode is formed over the semiconductor layer extending from over the local insulating layer to the source layer. A low-concentration diffusion layer is formed in the semiconductor layer below the drain layer. First and second gate insulating films are formed between the gate electrode and the semiconductor layer, and respectively extending from an end, on the source layer side, of the gate electrode to the local insulating layer without reaching the local insulating layer, and extending from an end on another side of the local insulting layer to the source layer.05-07-2009
20100219472Semiconductor device and method of manufacturing the same - In a method of manufacturing a high withstanding voltage MOSFET, a region to be doped with impurities and a region to be doped with no impurity are provided when ion implantation of the impurities is performed in the channel forming region, for controlling a threshold voltage. The region to be doped with no impurity is suitably patterned so that impurity concentration of the channel forming region near boundaries between a well region and a source region and between the well region and a drain region having the same conductivity type as the well region may be increased, to thereby induce a reverse short channel effect. By canceling a short channel effect with the reverse short channel effect induced by the above-mentioned method, the short channel effect of the high withstanding voltage MOSFET may be suppressed.09-02-2010
20130134509Semiconductor Device Arrangement Comprising a Semiconductor Device with a Drift Region and a Drift Control Region - A semiconductor device includes a source region, a drain region, a body region, and a drift region. The drift region is arranged between the body and the drain and the body is arranged between the source and the drift region in a semiconductor body. A gate electrode is adjacent the body and dielectrically insulated from the body by a gate dielectric. A drift control region is adjacent the drift region and dielectrically insulated from the drift region by a drift control region dielectric. A drain electrode adjoins the drain. The device also includes an injection control region of the same doping type as the drain, but more lowly doped. The injection control region adjoins the drift control region dielectric, extends in a first direction along the drift control region, and adjoins the drain in the first direction and an injection region in a second direction different from the first direction.05-30-2013
20110001188SEMICONDUCTOR APPARATUS AND METHOD OF MANUFACTURING THE SAME - An impact ionization MISFET includes: a gate insulating film which has one surface contacting the surface of a semiconductor substrate; a gate electrode that contacts the other surface of the gate insulating film; and a drain region, channel region, impact ionization region, and source region that are formed in one direction on the semiconductor substrate. The channel region is on the surface of the semiconductor substrate to which the gate insulating film is in contact, and a channel is generated when a voltage is applied to the gate electrode. When a voltage is applied between the drain region and the source region and when a channel is generated in the channel region, avalanche multiplication of carriers injected from the source region occurs in the impact ionization region. The flow path of the carriers between the channel and the source region occurs within the semiconductor substrate.01-06-2011
20110024835HIGH FREQUENCY FIELD-EFFECT TRANSISTOR - The invention relates to a field-effect transistor having a higher efficiency than the known field-effect transistors, in particular at higher operating frequencies. This is achieved by electrically connecting sources of a plurality of main current paths by means of a strap line (SL) being inductively coupled to a gate line (Gtl) and/or a drain line (Drnl) for forming an additional RF-return current path parallel to the RF-return current path in a semiconductor body (SB). The invention further relates to a field-effect transistor package, a power amplifier, a multi-stage power amplifier and a base station comprising such a field-effect transistor.02-03-2011
20110079846HIGH VOLTAGE DEVICES, SYSTEMS, AND METHODS FOR FORMING THE HIGH VOLTAGE DEVICES - A high voltage (HV) device includes a gate dielectric structure over a substrate. The gate dielectric structure has a first portion and a second portion. The first portion has a first thickness and is over a first well region of a first dopant type in the substrate. The second portion has a second thickness and is over a second well region of a second dopant type. The first thickness is larger than the second thickness. A gate electrode is disposed over the gate dielectric structure. A metallic layer is over and coupled with the gate electrode. The metallic layer extends along a direction of a channel under the gate dielectric structure. At least one source/drain (S/D) region is disposed within the first well region of the first dopant type.04-07-2011
20110095363Semiconductor Structures Employing Strained Material Layers with Defined Impurity Gradients and Methods for Fabricating Same - Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there is degradation in device performance. By employing semiconductor structures and devices (e.g., field effect transistors or “FETs”) that have the features described, or are fabricated in accordance with the steps described, device operation is enhanced.04-28-2011
20100163980SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes an isolation layer formed on and/or over a semiconductor substrate to define an isolation layer, a drift area formed in an active area separated by the isolation layer, a pad nitride layer pattern formed in a form of a plate on the drift area, and a gate electrode having step difference between lateral sides thereof due to the pad nitride layer pattern.07-01-2010
20100163982SEMICONDUCTOR DEVICE FOR HIGH VOLTAGE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device which may be for a high voltage and a method of manufacturing the same. A semiconductor device may include a first conductivity-type well formed on and/or over a substrate, a second conductivity-type drift region formed on and/or over a first conductivity-type well, an isolation layer formed on and/or over a first conductivity-type well, an isolation layer defining an isolation region and/or an active region, a gate pattern formed on and/or over a predetermined upper surface of a second conductivity-type drift region and/or a first conductivity-type well at an active region of a substrate, and/or second conductivity-type source and/or drain regions formed on and/or over second conductivity-type drift regions at two sides of a gate pattern. A gate pattern and/or a drift region of a semiconductor device may be formed substantially without gaps.07-01-2010
20100163981SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes: an active region defined by a device isolation layer on and/or over a substrate; a second conductive well on and/or over the active region; an extended drain formed at one side of the second conductive well; a gate electrode on and/or over the second conductive well and the extended drain; and a source and a drain formed at both sides of the gate electrode, in which extended regions are formed at the corners of the second conductive well under the gate electrode.07-01-2010
20090321823Semiconductor Device and Manufacturing Method Thereof - A high voltage semiconductor device and a manufacturing method thereof are provided. The high voltage semiconductor device comprises: second conductive type drift regions disposed spaced from each other on a first conductive type well region formed on a first conductive type semiconductor substrate; a gate electrode on a channel region between the second conductive type drift regions with a gate insulating film disposed therebetween; second conductive type high-concentration source and drain each disposed in the second conductive type drift regions, spaced from a side of a gate electrode; a gate spacer having a spacer part covering the side of the gate electrode and a spacer extending part to cover a spaced portion of the second conductive type high-concentration source and drain from the side of the gate electrode; and a silicide formed on the gate electrode and the second conductive type high-concentration source and drain.12-31-2009
20120146140HIGH-VOLTAGE SEMICONDUCTOR DEVICE WITH LATERAL SERIES CAPACITIVE STRUCTURE - A semiconductor device includes a semiconductor substrate, a source region extending along a top surface of the semiconductor substrate, a drain region extending along the top surface of the semiconductor substrate, and a field shaping region disposed within the semiconductor substrate between the source region and the drain region. A cross-section of the semiconductor substrate extending from the source region to the drain region through the field shaping region includes an insulating region. The semiconductor device also includes an active region disposed within the semiconductor substrate between the source region and the drain region. The active region is disposed adjacent to the field shaping region in a direction perpendicular to the cross-section of the semiconductor substrate extending from the source region to the drain region through the field shaping region.06-14-2012
20090032867DMOS TYPE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A DMOS type semiconductor device and a method for manufacturing the same are provided. An isolation oxide layer with an ion implantation opening is formed on a semiconductor. A gate oxide film is formed on the semiconductor within the ion implantation opening. A gate is formed on the isolation oxide layer and the gate oxide film. A body layer diffusively formed in the semiconductor by implanting ions of an impurity element having a first conduction type from the ion implantation opening. A regulation layer which is shallower than the body layer is diffusively formed in the body layer by implanting ions of an impurity element having a second conduction type opposite to the first conduction type from the ion implantation opening. A source layer is diffusively formed in the regulation layer by implanting ions of an impurity element having the second conduction type from the ion implantation opening. The regulation layer is formed so as to horizontally extend beyond a region in which a gate bird's beak occurs from an end of the gate toward underlying layers of the gate.02-05-2009
20110073942High-voltage transistor structure with reduced gate capacitance - In one embodiment, a high voltage field-effect transistor (HVFET) includes a field oxide layer that covers a first well region, the field oxide layer having a first thickness and extending in a second lateral direction from a drain region to near a second well region. A gate oxide covers a channel region and has a second dimension in a first lateral direction. A gate extends in the second lateral direction from the source region to over a portion of the field oxide layer, the gate being insulated from the channel region by the gate oxide, the gate extending in the first lateral dimension over an inactive area of the HVFET beyond the second dimension of the gate oxide, the gate being insulated from the first and second well regions over the inactive area by the field oxide layer.03-31-2011
20110024834Semiconductor Devices Including Electrodes with Integrated Resistances and Related Methods - A semiconductor device may include an insulating layer and a semiconductor electrode on the insulating layer. An area of increased electrical resistance may separate a contact area of the semiconductor electrode from an active area of the semiconductor electrode. In addition, a metal contact may be provided on the contact area of the semiconductor electrode opposite the insulating layer.02-03-2011
20100301411SEMICONDUCTOR DEVICE - The invention prevents a source-drain breakdown voltage of a DMOS transistor from decreasing due to dielectric breakdown in a portion of a N type drift layer having high concentration formed in an active region near field oxide film corner portions surrounding an gate width end portion. The field oxide film corner portions are disposed on the outside of the gate width end portion so as to be further away from a P type body layer formed in the gate width end portion by forming the active region wider on the outside of the gate width end portion than in a gate width center portion. By this, the N type drift layer having high concentration near the field oxide film corner portions are disposed further away from the P type body layer without increasing the device area.12-02-2010
20100244129Semiconductor device and method of manufacturing semiconductor device - Second-conductivity-type high dose impurity layers are formed in a device forming region, and function as the source and drain; a second-conductivity-type low dose impurity layer is provided around each of the second-conductivity-type high dose impurity layers so as to expand each second-conductivity-type high dose impurity layer in the depth-wise direction and in the direction of channel length, at least a part of the second-conductivity-type low dose impurity layer is positioned below the gate electrode, and the gate insulting film; and the gate insulating film has, at a portion thereof positioned above the second-conductivity-type low dose impurity layer, a sloped portion which continuously increases in the thickness from the center towards a side face of the gate electrode, without causing an inflection point.09-30-2010
20120199903SEMICONDUCTOR DEVICE HAVING A SUPER JUNCTION - A semiconductor device having a super junction includes: a substrate having a first electrical type; a main body including a base part that has the first electrical type, and a modified part that has a second electrical type opposite to the first electrical type; a source zone contacting the modified part oppositely of the substrate, and having the first electrical type; and a gate structure having a dielectric layer that contacts the source zone, and a conductive layer formed on the dielectric layer oppositely of the main body.08-09-2012
20100320535TRANSISTOR COMPONENT HAVING AN AMORPHOUS CHANNEL CONTROL LAYER - Disclosed is a semiconductor component, including: a drift zone arranged between a first and a second connection zone; a channel control layer of an amorphous semi-insulating material arranged adjacent to the drift zone.12-23-2010
20110079847Semiconductor Device - Provided is a semiconductor device capable of easily setting a holding voltage with a low trigger voltage by locally forming a P-type diffusion layer between N-type source and drain diffusion layers of an NMOS transistor having a conventional drain structure used as an electrostatic protective element of the semiconductor device.04-07-2011
20110133272SEMICONDUCTOR DEVICE WITH IMPROVED ON-RESISTANCE - A semiconductor device includes a source, a drain, and a gate configured to selectively enable a current to pass between the source and the drain. The semiconductor device includes a drift zone between the source and the drain and a first field plate adjacent the drift zone. The semiconductor device includes a dielectric layer electrically isolating the first field plate from the drift zone and charges within the dielectric layer close to an interface of the dielectric layer adjacent the drift zone.06-09-2011
20110068396METHOD AND STRUCTURE FOR FORMING HIGH-PERFOMANCE FETs WITH EMBEDDED STRESSORS - A high-performance semiconductor structure and a method of fabricating such a structure are provided. The semiconductor structure includes at least one gate stack, e.g., FET, located on an upper surface of a semiconductor substrate. The structure further includes a first epitaxy semiconductor material that induces a strain upon a channel of the at least one gate stack. The first epitaxy semiconductor material is located at a footprint of the at least one gate stack substantially within a pair of recessed regions in the substrate which are present on opposite sides of the at least one gate stack. A diffused extension region is located within an upper surface of said first epitaxy semiconductor material in each of the recessed regions. The structure further includes a second epitaxy semiconductor material located on an upper surface of the diffused extension region. The second epitaxy semiconductor material has a higher dopant concentration than the first epitaxy semiconductor material.03-24-2011
20100252880METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE, AND A SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device comprises the steps of, in sequence: depositing a first silicon layer; patterning the first silicon layer to obtain a first silicon region; implanting a first dopant into a first part of the first silicon region, the first part of the first silicon region defined using a first mask; depositing a second silicon layer; patterning the second silicon layer to obtain a second silicon region; and implanting a second dopant into a second part of the first silicon region, the second part of the first silicon region defined by the first mask and the second silicon region.10-07-2010
20100193865DMOS TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - The invention provides a DMOS transistor in which a leakage current is decreased and the source-drain breakdown voltage of the transistor in the off state is enhanced when a body layer is formed by oblique ion implantation. After a photoresist layer 08-05-2010
20110215402SEMICONDUCTOR DEVICE - A semiconductor device is provided. The semiconductor device includes a gate on a substrate, a source region at a first side of the gate, a first conductive type body region under the source region, a second conductive type drain region at a second side of the gate, a device isolation region in the substrate between the source region and the drain region and overlapping part of the gate, and a first buried layer extending in a direction from the source region to the drain region, the first buried layer under the body region, overlapping part of the device isolation region, and not overlapping the drain region.09-08-2011
20110215401Semiconductor Device and Its Manufacturing Method - In an LDMOS transistor, a channel length is reduced to increase a saturation current without causing an off-state breakdown voltage optimized in terms of trade-off between an on-resistance and the off-state breakdown voltage. A short channel region is selectively formed between an element isolation film and a low-concentration body region in which a channel is formed such that the short channel region is located immediately below a gate oxide film. The short channel region has a conduction type opposite to that of the low-concentration body region and has a carrier concentration higher than that of the low-concentration body region. The body region is retreated by the presence of the short channel region toward a high-concentration source region.09-08-2011
20100019317Managing Integrated Circuit Stress Using Stress Adjustment Trenches - Roughly described, methods and systems for improving integrated circuit layouts and fabrication processes in order to better account for stress effects. Dummy features can be added to a layout either in order to improve uniformity, or to relax known undesirable stress, or to introduce known desirable stress. The dummy features can include dummy diffusion regions added to relax stress, and dummy trenches added either to relax or enhance stress. A trench can relax stress by filling it with a stress-neutral material or a tensile strained material. A trench can increase stress by filling it with a compressive strained material. Preferably dummy diffusion regions and stress relaxation trenches are disposed longitudinally to at least the channel regions of N-channel transistors, and transversely to at least the channel regions of both N-channel and P-channel transistors. Preferably stress enhancement trenches are disposed longitudinally to at least the channel regions of P-channel transistors.01-28-2010
20090173997MOSFET AND METHOD FOR MANUFACTURING MOSFET - The present invention provides a MOSFET and so forth that offer high breakdown voltage and low on-state loss (high channel mobility and low gate threshold voltage) and that can easily achieve normally OFF. A drift layer 07-09-2009
20120068263Power Switching Semiconductor Devices Including Rectifying Junction-Shunts - A semiconductor device includes a drift layer and a body region that forms a p-n junction with the drift layer. A contactor region is in the body region, and a shunt channel region extends through the body region from the contactor region to the drift layer. The shunt channel region has a length, thickness and doping concentration selected such that: 1) the shunt channel region is fully depleted when zero voltage is applied across the first and second terminals, 2) the shunt channel becomes conductive at a voltages less than the built-in potential of the drift layer to body region p-n junction, and/or 3) the shunt channel is not conductive for voltages that reverse bias the p-n junction between the drift region and the body region.03-22-2012
20120306010DMOS TRANSISTOR HAVING AN INCREASED BREAKDOWN VOLTAGE AND METHOD FOR PRODUCTION - A depletion type DMOS transistor comprises a gap in electrode material allowing incorporation of a well dopant species into the underlying semiconductor material. During subsequent dopant diffusion a continuous well region is obtained having an extended lateral extension without having an increased depth. The source dopant species is implanted after masking the gap. Additional channel implantation is performed prior to forming the gate dielectric material.12-06-2012
20120037984LDMOS Structure - A LDMOS structure includes a gate, a source, a drain and a bulk. The gate includes a polycrystalline silicon layer, the source includes a P-implanted layer, the drain includes the P-implanted layer, a P-well layer, and a deep P-well layer. A bulk terminal is connected through the P-implanted layer, the P-well layer, the deep P-well layer, and a P-type buried layer to the bulk. The LDMOS structure is able to be produced without any extra masking step, and it has compact structure, low on-resistance, and is able to withstand high current and high voltage.02-16-2012
20120146141ELECTRONIC CIRCUIT CONTROL ELEMENT WITH TAP ELEMENT - A technique for controlling a power supply with power supply control element with a tap element. An example power supply control element includes a power transistor that has first and second main terminals, a control terminal and a tap terminal. A control circuit is coupled to the control terminal. The tap terminal and the second main terminal of the power transistor are to control switching of the power transistor. The tap terminal is coupled to provide a signal to the control circuit substantially proportional to a voltage between the first and second main terminals when the voltage is less than a pinch off voltage. The tap terminal is coupled to provide a substantially constant voltage that is less than the voltage between the first and second main terminals to the control circuit when the voltage between the first and second main terminals is greater than the pinch-off voltage.06-14-2012
20120146139HIGH VOLTAGE SEMICONDUCTOR DEVICE - A semiconductor device for a high voltage application includes a doped source base region, an N+ source region, a P+ source region and a gate structure. The doped source base region has P-type. The N+ source region extends downwards into the doped source base region. The P+ source region is close to the N+ source region, extends downwards into the doped source base region, and is doped heavier than the doped source base region. The gate structure is coupled to the N+ source region and is near to the P+ source region.06-14-2012
20100219471QUASI-RESURF LDMOS - A semiconductor device can include a drift region, at least a portion of the drift region located laterally between a drain region and a source region. The drift region can include a first layer having a first doping concentration and a second layer having a second higher doping concentration than the first layer. The second layer of the drift region be configured to allow drift current between the source region and the drain region when a depletion region is formed in at least a portion of the first layer between the source region and the drain region.09-02-2010
20120043607Tunneling Field-Effect Transistor with Low Leakage Current - Illustrative embodiments of a vertical tunneling field effect transistor are disclosed which may comprise a semiconductor body including a source region doped with a first dopant type and a pocket region doped with a second dopant type, where the pocket region is formed above the source region. The transistor may also comprise an insulated gate formed above the source and pocket regions, the insulated gate being configured to generate electron tunneling between the source and pocket regions if a voltage is applied to the insulated gate. The transistor may further comprise a lateral tunneling barrier formed to substantially prevent electron tunneling between the source region and a drain region of the semiconductor body, where the drain region is doped with the second dopant type.02-23-2012
20110156141TRANSISTOR AND METHOD THEREOF - An electronic device can include a first well region of a first conductivity-type and a second well region of a second conductivity-type and abutting the first well region. The first conductivity-type and the second conductivity type can be opposite conductivity types. In an embodiment, an insulator region can extend into the first well region, wherein the insulator region and the first well region abut and define an interface, and, from a top view, the insulator region can include a first feature extending toward the first interface, and the insulator region can define a first space bounded by the first feature, wherein a dimension from a portion of the first feature closest to the first interface is at least zero. A gate structure can overlie an interface between the first and second well regions.06-30-2011
20090283825HIGH SPEED ORTHOGONAL GATE EDMOS DEVICE AND FABRICATION - An orthogonal gate extended drain MOSFET (EDMOS) structure provides a low gate-to-drain capacitance (C11-19-2009
20120205739SEMICONDUCTOR DEVICE AND PROCESS FOR PRODUCTION THEREOF - The semiconductor device of this invention has unit cells, each of which includes: a substrate; a drift layer on the substrate; a body region in the drift layer; a first doped region of a first conductivity type in the body region; a second doped region of the first conductivity type arranged adjacent to the body region and in a surface region of the drift layer; a third doped region of the first conductivity type arranged between two adjacent unit cells' second doped region of the first conductivity type and in the surface region of the drift layer to contact with the second doped region of the first conductivity type; a gate insulating film arranged to contact with the surface of the drift layer at least between the first and second doped regions of the first conductivity type; a gate electrode on the gate insulating film; and first and second ohmic electrodes. The dopant concentration of the third doped region of the first conductivity type is lower than that of the second doped region of the first conductivity type and equal to or higher than that of the drift layer.08-16-2012
20120205738NEAR ZERO CHANNEL LENGTH FIELD DRIFT LDMOS - Adverse tradeoff between BVDSS and Rdson in LDMOS devices employing a drift space (08-16-2012
20120061756SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a channel formation region of first conductivity type, a first offset region of second conductivity type, a first insulating region, a first liner layer, a first semiconductor region of second conductivity type, a second semiconductor region of second conductivity type, a gate insulating film, and a gate electrode. The first liner layer is provided between the first offset region and the first insulating region. The first semiconductor region of second conductivity type is provided on the side opposite to the channel formation region sandwiching the first insulating region therebetween and having impurity concentration higher than that of the first offset region. The second semiconductor region of second conductivity type is provided on the side opposite to the first semiconductor region sandwiching the channel formation region therebetween and having impurity concentration higher than that of the first offset region.03-15-2012
20120153387TRANSISTORS WITH HIGH CONCENTRATION OF BORON DOPED GERMANIUM - Techniques are disclosed for forming transistor devices having source and drain regions with high concentrations of boron doped germanium. In some embodiments, an in situ boron doped germanium, or alternatively, boron doped silicon germanium capped with a heavily boron doped germanium layer, are provided using selective epitaxial deposition in the source and drain regions and their corresponding tip regions. In some such cases, germanium concentration can be, for example, in excess of 50 atomic % and up to 100 atomic %, and the boron concentration can be, for instance, in excess of 1E20 cm06-21-2012
20120161230MOS TRANSISTOR AND FABRICATION METHOD THEREOF - A disclosed MOS transistor has a drain region offset from a gate electrode structure, wherein the gate electrode structure includes at least a first gate electrode and a second gate electrode such that the second gate electrode is located at the drain side of the first gate electrode and the second gate electrode is isolated from the first gate electrode by an insulation film, and wherein the first and second gate electrodes are formed respectively on a first gate insulation film and a second gate insulation film having an increased thickness as compared with the first gate insulation film.06-28-2012
20120119293HIGH PERFORMANCE LDMOS DEVICE HAVING ENHANCED DIELECTRIC STRAIN LAYER - An LDMOS device includes a substrate having a surface and a gate electrode overlying the surface and defining a channel region in the substrate below the gate electrode. A drain region is spaced apart from the channel region by an isolation region. The isolation region includes a region of high tensile stress and is configured to induce localized stress in the substrate in close proximity to the drain region. The region of high tensile stress in the isolation region can be formed by high-stress silicon oxide or high-stress silicon nitride. In a preferred embodiment, the isolation region is a shallow trench isolation region formed in the substrate intermediate to the gate electrode and the drain region.05-17-2012
20120119292SEMICONDUCTOR DEVICE - A semiconductor device includes a p-type semiconductor substrate, an n-type drift region formed in the p-type semiconductor substrate, and a p-type body region formed in the n-type drift region. A circular gate electrode is formed over a pn junction between sides of the p-type body region and the n-type drift region along the pn junction. An n-type drain region and an n-type source region are formed in the n-type drift region and the p-type body region, respectively, with a part of the gate electrode between.05-17-2012
20120211832SPLIT-GTE LATERAL DIFFUSED METAL OXIDE SEMICONDUCTOR DEVISE - A semiconductor device comprises a source region, a drain region, and a drift region between the source and drain regions. A split gate is disposed over a portion of the drift region, and between the source and drain regions. The split gate includes first and second gate electrodes separated by a gate oxide layer. A self-aligned RESURF region is disposed within the drift region between the gate and the drain region. PI gate structures including an upper polysilicon layer are disposed near the drain region, such that the upper polysilicon layer can serve as a hard mask for the formation of the double RESURF structure, thereby allowing for self-alignment of the double RESURF structure.08-23-2012
20120161231SEMICONDUCTOR DEVICE - In a semiconductor power device such as a power MOSFET having a super-junction structure in each of an active cell region and a chip peripheral region, an outer end of a surface region of a second conductivity type coupled to a main junction of the second conductivity type in a surface of a drift region of a first conductivity type and having a concentration lower than that of the main junction is located in a middle region between an outer end of the main junction and an outer end of the super-junction structure in the chip peripheral region.06-28-2012
20120168861POWER TRANSISTOR WITH INCREASED AVALANCHE CURRENT AND ENERGY RATING - A field-effect transistor involves a drain electrode, a drift region, a body region, a source region, a gate insulator layer, and a gate electrode. The drift region is disposed above the drain electrode. The body region extends down into the drift region from a first upper semiconductor surface. The source region is ladder-shaped and extends down in the body region from a second upper semiconductor surface. The first and second upper semiconductor surfaces are substantially planar and are not coplanar. A first portion of the body region is surrounded laterally by a second portion of the body region. The second portion of the body region and the drift region meet at a body-to-drift boundary. The body-to-drift boundary has a central portion that is non-planar. A gate insulator layer is disposed over the source region and a gate electrode is disposed over the gate insulator.07-05-2012
20120217580SEMICONDUCTOR DEVICE WITH IMPROVED ON-RESISTANCE - A semiconductor device includes a source, a drain, and a gate configured to selectively enable a current to pass between the source and the drain. The semiconductor device includes a drift zone between the source and the drain and a first field plate adjacent the drift zone. The semiconductor device includes a dielectric layer electrically isolating the first field plate from the drift zone and charges within the dielectric layer close to an interface of the dielectric layer adjacent the drift zone.08-30-2012
20120217579High voltage device and manufacturing method thereof - The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device includes: a substrate, having a P (or N) type well and an isolation structure for defining a device region; a drift region, located in the device region, having a first region and a second region wherein the first region is an N (or P) type region, and the second region is a P (or N) type region or an N (or P) type region with different dopant concentration from the first region, and from top view, the first region and the second region include sub-regions distributed in the drift region; an N (or P) type source and drain; and a gate on a surface of the substrate, between the source and drain in the device region.08-30-2012
20100244128Configuration and fabrication of semiconductor structure using empty and filled wells - A semiconductor structure, which serves as the core of a semiconductor fabrication platform, has a combination of empty-well regions and filled-well regions variously used by electronic elements, particularly insulated-gate field-effect transistors (“IGFETs”), to achieve desired electronic characteristics. A relatively small amount of semiconductor well dopant is near the top of an empty well. A considerable amount of semiconductor well dopant is near the top of a filled well. Some IGFETs (09-30-2010
20120223383SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF - A method for fabrication of a semiconductor device is provided. A first type doped body region is formed in a first type substrate. A first type heavily-doped region is formed in the first type doped body region. A second type well region and second type bar regions are formed in the first type substrate with the second type bar regions between the second type well region and the first type doped body region. The first type doped body region, the second type well region, and each of the second type bar regions are separated from each other by the first type substrate. The second type bar regions are inter-diffused to form a second type continuous region adjoining the second type well region. A second type heavily-doped region is formed in the second type well region.09-06-2012
20120228703SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor device includes a semiconductor substrate, and an insulating member. The semiconductor substrate has a trench formed in a top surface. The insulating member is provided in the trench. A space is formed between the semiconductor substrate and the insulating member.09-13-2012
20120261749SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The semiconductor device according to one embodiment of the present invention includes: a semiconductor substrate; and a first area and a second area which are respectively provided on the semiconductor substrate. The first area includes: a first metal wiring formed in a first wiring layer above the semiconductor substrate and having a certain first width; a second metal wiring formed in a second wiring layer located in an upper layer of the first wiring layer and having the first width; and a first contact connecting the first metal wiring and the second metal wiring and having a second width equal to or less than the first width. The second area includes a third metal wiring having a film thickness from the first wiring layer to the second wiring layer and having a certain third width.10-18-2012
20120261750SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a drift diffusion region of a first conductivity type, a body diffusion region of a second conductivity type, a source diffusion region of the first conductivity type, an insulating film buried in a trench formed in an upper portion of the drift diffusion region and spaced apart from the body diffusion region, a drain diffusion region of the first conductivity type formed in an upper portion of the drift diffusion region and adjacent to the insulating film on the opposite side of the insulating film from the source diffusion region, and a gate electrode formed on a portion of the body diffusion region, the drift diffusion region, and a portion of the insulating film. The drift diffusion region includes a substrate inner region, and a surface region containing an impurity of the first conductivity type at a higher concentration than that of the substrate inner region.10-18-2012
20120299093SEMICONDUCTOR DEVICE - A semiconductor device comprising a substrate in which a first region and a second region are defined, a gate line which extends in a first direction and traverses the first region and the second region, a source region including a portion formed in the first region, a first part of a body region which is formed under the portion of the source region in the first region and has a first width, a first well which is formed under the first part of the body region in the first region and has a second width greater than the first width, a second part of the body region which is formed in the second region and has a third width, and a second well which is formed under the second part of the body region in the second region and has a fourth width smaller than the third width.11-29-2012
20120267714DOUBLE LAYER METAL (DLM) POWER MOSFET - This document discusses, among other things, a semiconductor device including a first metal layer coupled to a source region and a second metal layer coupled to a gate structure, wherein at least a portion of the first and second metal layers overlap vertically.10-25-2012
20110227154SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device comprising: a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type formed on the first semiconductor layer; a first buried layer of the first conductivity type selectively formed in the second semiconductor layer and having a first peak impurity concentration at a first depth; a second buried layer of a second conductivity type selectively formed in the second semiconductor layer and having a second peak impurity concentration at a second depth; a base layer of the second conductivity type selectively formed in the second semiconductor layer and overlapping with an upper portion of the second buried layer; a source layer of the first conductivity type selectively formed in the base layer; and a gate electrode formed on the base layer and on the second semiconductor layer above the first buried layer with a gate insulating film being interposed therebetween.09-22-2011
20100187604SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate of a first conductivity type, a first semiconductor region of the first conductivity type on the semiconductor substrate, and a plurality of second semiconductor regions of a second conductivity type disposed separately in the first semiconductor region. A difference between a charge quantity expressed by an integral value of a net activated doping concentration in the second semiconductor regions in the surface direction of the semiconductor substrate and a charge quantity expressed by an integral value of a net activated doping concentration in the first semiconductor region in the surface direction of the semiconductor substrate is always a positive quantity and becomes larger from the depth of the first junction plane to a depth of a second junction plane on an opposite side from the first junction plane.07-29-2010
20100230748Semiconductor device and method of manufacturing the same - A high breakdown voltage MOS transistor capable of reducing a leakage current while reducing an element size as compared with conventional ones is realized. On a P type well, with a channel area ch in between, an N type first impurity diffusion area including a drain area and drain side drift area, and an N type second impurity diffusion area including a source area and a source side drift area are formed. Moreover, a gate electrode is formed, via a gate oxide film, above a part of the first impurity diffusion area, above the channel area and above a part of the second impurity diffusion area. The gate electrode is doped with an N type, and an impurity concentration of portions located above the first and the second impurity diffusion areas is lower than an impurity concentration of a portion located above the channel area.09-16-2010
20120280318HIGH VOLTAGE DEVICE - A device is disclosed. The device includes s substrate prepared with an active device region. The active device region includes a gate. The device also includes a doped channel well disposed in the substrate adjacent to a first edge of the gate. The first edge of the gate overlaps the channel well with a channel edge of the channel well beneath the gate. The first edge of the gate and channel edge defines an effective channel length of the device. The effective channel length is self-aligned to the gate. A doped drift well adjacent to a second edge of the gate is also included.11-08-2012
20120280317RESURF STRUCTURE AND LDMOS DEVICE - A reduced surface field (RESURF) structure and a lateral diffused metal oxide semiconductor (LDMOS) device including the same are provided. The RESURF structure includes a substrate of a first conductivity type, a deep well region of a second conductivity type, an isolation structure, at least one trench insulating structure, and at least one doped region of the first conductivity type. The deep well region is disposed in the substrate. The isolation structure is disposed on the substrate. The trench insulating structure is disposed in the deep well region below the isolation structure. The doped region is disposed in the deep well region and surrounds a sidewall and a bottom of the trench insulating structure.11-08-2012
20110298048SEMICONDUCTOR DEVICE - The present teaching provides a semiconductor device capable of relaxing stress transferred to a contact region during wire bonding and improving reliability of wire bonding. A semiconductor device comprises contact regions, an interlayer insulating film, an emitter electrode, and a stress relaxation portion. The contact regions are provided at a certain interval in areas exposing at a surface of a semiconductor substrate. The interlayer insulating film is provided on the surface of the semiconductor substrate between adjacent contact regions. The emitter electrode is provided on an upper side of the semiconductor substrate and electrically connected to each of the contact regions. The stress relaxation portion is provided on an upper surface of the emitter electrode in an area only above the contact regions. The stress relaxation portion is formed of a conductive material. A Young's modulus of the material of the stress relaxation portion is lower than a Young's modulus of the material of the emitter electrode.12-08-2011
20120091525Split Gate Oxides for a Laterally Diffused Metal Oxide Semiconductor (LDMOS) - An apparatus is disclosed to increase a breakdown voltage of a semiconductor device. The semiconductor device includes a first heavily doped region to represent a source region. A second heavily doped region represents a drain region of the semiconductor device. A third heavily doped region represents a gate region of the semiconductor device. The semiconductor device includes a gate oxide positioned between the source region and the drain region, below the gate region. The semiconductor device uses a split gate oxide architecture to form the gate oxide. The gate oxide includes a first gate oxide having a first thickness and a second gate oxide having a second thickness.04-19-2012
20120091524LDMOS DEVICE STRUCTURE AND MANUFACTURING METHOD OF THE SAME - The present invention discloses an LDMOS device structure, including a MOS transistor cell, wherein an isolation region is formed on each outer side of both a source region and a drain region of the MOS transistor cell; each isolation region includes a plurality of isolation trenches and isolates the MOS transistor cell from its surroundings; the height of the isolation region is smaller than that of a gate of the MOS transistor cell. The present invention also discloses a manufacturing method of the LDMOS device structure, including forming isolation trenches by lithography and etching processes, then forming isolation regions of SiO04-19-2012
20120241858SEMICONDUCTOR DEVICE - A first semiconductor layer extends from the element region to the element-termination region, and functions as a drain of the MOS transistor. A second semiconductor layer extends, below the first semiconductor layer, from the element region to the element-termination region. A third semiconductor layer extends from the element region to the element-termination region, and is in contact with the second semiconductor layer to function as a drift layer of the MOS transistor. A distance between a boundary between the first semiconductor layer and the field oxide film, and the end portion of the third semiconductor layer on the fifth semiconductor layer side in the element region is smaller than that between a boundary between the first semiconductor layer and the field oxide layer and an end portion of the third semiconductor layer on the fifth semiconductor layer side in the element-termination region.09-27-2012
20090101972PROCESS FOR FABRICATING A FIELD-EFFECT TRANSISTOR WITH DOPING SEGREGATION USED IN SOURCE AND/OR DRAIN - Source and/or drain regions of a transistor are first doped with an appropriate dopant and a metal is subsequently deposited. After heating, a silicide will displace the dopant, creating an increased density of dopants at the border of the silicided region. The dopants that are adjacent to or in the gate region of the device will form a thin layer. The silicide or other reactant material is then removed and replaced with a desired source/drain material, while leaving the layer of dopant immediately adjacent to the newly deposited source/drain material.04-23-2009
20130168766DRAIN EXTENDED MOS TRANSISTOR AND METHOD FOR FABRICATING THE SAME - A drain extended MOS (DEMOS) transistor including at least one of: (1) A p-type epitaxial layer grown over an n-type semiconductor substrate. (2) An n-type well formed in a portion of the epitaxial layer. (3) A p-type drift region formed in another portion of the epitaxial layer. (4) A p-type source region formed in the well. (5) A p-type drain region formed in the drift region and spaced apart from the source region inside the epitaxial layer. (6) An n-type channel region extending between the drift region and the source region. (7) A gate structure formed over the channel region. (8) An n-type buried layer having a contact surface with the well and the drift region and formed in the epitaxial layer. A region of the buried layer has surface contact with the drift region and has a relatively low dopant concentration compared to other regions.07-04-2013
20130181285Lateral DMOS Device with Dummy Gate - An LDMOS transistor with a dummy gate comprises an extended drift region formed over a substrate, a drain region formed in the extended drift region, a channel region formed in the extended drift region, a source region formed in the channel region and a dielectric layer formed over the extended drift region. The LDMOS transistor with a dummy gate further comprises an active gate formed over the channel region and a dummy gate formed over the extended drift region. The dummy gate helps to reduce the gate charge of the LDMOS transistor while maintaining the breakdown voltage of the LDMOS transistor.07-18-2013
20130181286HIGH VOLTAGE DEVICE - A method of forming a device is presented. The method includes providing a substrate having a device region which includes a source region, a gate and a drain region defined thereon. The method also includes implanting the gate. The gate comprises one or more doped portions with different dopant concentrations. A source and a drain are formed in the source region and drain region. The drain is separated from the gate on a second side of the gate and the source is adjacent to a first side of the gate.07-18-2013
20130181287HIGH VOLTAGE DEVICE - A method of forming a device is disclosed. A substrate having a device region is provided. The device region comprises a source region, a gate and a drain region defined thereon. A drift well is formed in the substrate adjacent to a second side of the gate. The drift well underlaps a portion of the gate with a first edge of the drift well beneath the gate. A secondary portion is formed in the drift well. The secondary portion underlaps a portion of the gate with a first edge of the secondary portion beneath the gate. The first edge of the secondary portion is offset from the first edge of the drift well. A gate dielectric of the gate comprises a first portion having a first thickness and a second portion having a second thickness. The second portion is over the secondary portion.07-18-2013
20130093013HIGH VOLTAGE TRANSISTOR AND MANUFACTURING METHOD THEREFOR - A high-voltage transistor may include a semiconductor substrate, and a gate electrode formed on and/or over the semiconductor substrate. Further, the high-voltage transistor may include source/drain regions formed on and/or over the semiconductor substrate at one side of the gate electrode, and impurity layers having a super junction structure and formed on and/or over a boundary of a drift region disposed below the gate electrode.04-18-2013
20130093012HIGH VOLTAGE DEVICE - A method of forming a device is disclosed. The method includes providing a substrate having a device region. The device region includes a source region, a gate region and a drain region defined thereon. The substrate is prepared with gate layers on the substrate. The gate layers are patterned to form a gate in the gate region and a field structure surrounding the drain region. A source and a drain are formed in the source region and drain region respectively. The drain is separated from the gate on a second side of the gate and the source is adjacent to a first side of the gate. An interconnection to the field structure is formed. The interconnection is coupled to a potential which distributes the electric field across the substrate between the second side of the gate and the drain.04-18-2013
20130093010High-Voltage Mosfets Having Current Diversion Region in Substrate Near Fieldplate - To limit or prevent current crowding, various HV-MOSFET embodiments include a current diversion region disposed near a drain region of an HV-MOSFET and near an upper surface of the semiconductor substrate. In some embodiments, the current diversion region is disposed near a field plate of the HV-MOSFET, wherein the field plate can also help to reduce or “smooth” electric fields near the drain to help limit current crowding. In some embodiments, the current diversion region is a p-doped, n-doped, or intrinsic region that is at a floating voltage potential. This current diversion region can push current deeper into the substrate of the HV-MOSFET (relative to conventional HV-MOSFETs), thereby reducing current crowding during ESD events. By reducing current crowding, the current diversion region makes the HV-MOSFETs disclosed herein more impervious to ESD events and, therefore, more reliable in real-world applications.04-18-2013
20130093009METHOD OF MANUFACTURING NMOS TRANSISTOR WITH LOW TRIGGER VOLTAGE - A method for forming an NMOS transistor includes forming a P-substrate; forming an N-well on the P-substrate; forming an N-drift region on the N-well; forming an n+ drain on the N-drift region; forming a plurality of first contacts on the n+ drain along a longitudinal direction; forming a P-body on the N-well; forming a source on the P-body, the source including a plurality of n+ doped regions and at least one p+ doped region arranged along the longitudinal direction; forming a plurality of second contacts on the plurality of n+ doped regions and the at least one p+ doped region; forming a polygate on the P-body; and forming a gate oxide between the polygate and the source.04-18-2013
20130093011High Voltage Device and Manufacturing Method Thereof - The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device is formed in a substrate. The high voltage device includes: a gate, a source and drain, a drift region, and a mitigation region. The gate is formed on an upper surface of the substrate. The source and drain are located at both sides of the gate below the upper surface respectively, and the source and drain are separated by the gate. The drift region is located at least between the gate and the drain. The mitigation region is formed below the drift region, and the drift region has an edge closer to the source. A vertical distance between this edge of the drift region and the mitigation region is less than or equal to five times of a depth of the drift region.04-18-2013
20130113041SEMICONDUCTOR TRANSISTOR DEVICE WITH OPTIMIZED DOPANT PROFILE - Provided is a transistor and a method for forming a transistor in a semiconductor device. The method includes performing at least one implantation operation in the transistor channel area, then forming a silicon carbide/silicon composite film over the implanted area prior to introducing further dopant impurities. A halo implantation operation with a very low tilt angle is used to form areas of high dopant concentration at edges of the transistor channel to alleviate short channel effects. The transistor structure so-formed includes a reduced dopant impurity concentration at the substrate interface with the gate dielectric and a peak concentration about 10-50 nm below the surface. The dopant profile also includes the transistor channel having high dopant impurity concentration areas at opposed ends of the transistor channel.05-09-2013
20130126970CONFIGURATION AND FABRICATION OF SEMICONDUCTOR STRUCTURE USING EMPTY AND FILLED WELLS - A semiconductor structure, which serves as the core of a semiconductor fabrication platform, has a combination of empty-well regions and filled-well regions variously used by electronic elements, particularly insulated-gate field-effect transistors (“IGFETs”), to achieve desired electronic characteristics. A relatively small amount of semiconductor well dopant is near the top of an empty well. A considerable amount of semiconductor well dopant is near the top of a filled well. Some IGFETs (05-23-2013
20130126969LATERAL DOUBLE DIFFUSION METAL-OXIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - Disclosed is an LDMOS device, which is configured to reduce an electric field concentrated to a gate oxide film and lower an ON-resistance produced when the device conducts a forward action, and a method for manufacturing the same. More specifically, when an n-drift region is formed on a P-type substrate, a p-body is formed on the n-drift region through an epitaxial process, and then the p-body region is partially etched to form a plurality of p-epitaxial layers, so that when the device executes an action for blocking a reverse voltage, depletion layers are formed between the junction surfaces of the p-epitaxial layers and the n-drift region including the junction surfaces between the n-drift region and the p-body.05-23-2013
20130140632Lateral Transistor Component and Method for Producing Same - A transistor component includes an active transistor region arranged in the semiconductor body. And insulation region surrounds the active transistor region in the semiconductor body in a ring-shaped manner. A source zone, a drain zone, a body zone and a drift zone are disposed in the active transistor region. The source zone and the drain zone are spaced apart in a lateral direction of the semiconductor body and the body zone is arranged between the source zone and the drift zone and the drift zone is arranged between the body zone and the drain zone. A gate and field electrode is arranged over the active transistor region. The dielectric layer has a first thickness in in a region near the body zone and a second thickness in a region near the drift zone.06-06-2013
20130146973CUSTOMIZED SHIELD PLATE FOR A FIELD EFFECT TRANSISTOR - A customized shield plate field effect transistor (FET) includes a semiconductor layer, a gate dielectric, a gate electrode, and at least one customized shield plate. The shield plate includes a conductive layer overlying a portion of the gate electrode, one of the gate electrode sidewalls, and a portion of the substrate adjacent to the sidewall. The shield plate defines a customized shield plate edge at its lateral boundary. A distance between the customized shield plate edge and the sidewall of the gate electrode varies along a length of the sidewall. The customized shield plate edge may form triangular, curved, and other shaped shield plate elements. The configuration of the customized shield plate edge may reduce the area of the resulting capacitor and thereby achieve lower parasitic capacitance associated with the FET. The FET may be implemented as a lateral diffused MOS (LDMOS) transistor suitable for high power radio frequency applications.06-13-2013
20130146974SEMICONDUCTOR DEVICES AND METHODS OF FORMING THE SAME - A method of forming a semiconductor device is provided. The method includes preparing a substrate having a transistor region and an alignment region, forming a first trench and a second trench in the substrate of the transistor region and in the substrate of the alignment region, respectively, forming a drift region in the substrate of the transistor region, forming two third trenches respectively adjacent to two ends of the drift region, and forming an isolation pattern in the first trench, a buried dielectric pattern in the second trench, and dielectric patterns in the two third trenches, respectively. A depth of the first trench is less than a depth of the third trenches, and the depth of the first trench is equal or substantially equal to a depth of the second trench.06-13-2013
20080197408Isolated quasi-vertical DMOS transistor - Various integrated circuit devices, in particular a quasi-vertical DMOS transistor, are formed inside an isolation structure which includes a floor isolation region and a trench extending from the surface of the substrate to the floor isolation region. The trench may be filled with a dielectric material or may have a conductive material in a central portion with a dielectric layer lining the walls of the trench. Various techniques for terminating the isolation structure by extending the floor isolation region beyond the trench, using a guard ring, and a forming a drift region are described.08-21-2008
20110248341CONTINUOUS ASYMMETRICALLY SLOPED SHALLOW TRENCH ISOLATION REGION - This document discusses, among other things, a semiconductor device, and a method of forming a semiconductor device, having a shallow trench isolation (STI) region including a continuous, asymmetrically sloped sidewall.10-13-2011
20120273879TOP DRAIN LDMOS - In an embodiment, this invention discloses a top-drain lateral diffusion metal oxide field effect semiconductor (TD-LDMOS) device supported on a semiconductor substrate. The TD-LDMOS includes a source electrode disposed on a bottom surface of the semiconductor substrate. The TD-LDMOS further includes a source region and a drain region disposed on two opposite sides of a planar gate disposed on a top surface of the semiconductor substrate wherein the source region is encompassed in a body region constituting a drift region as a lateral current channel between the source region and drain region under the planar gate. The TD-LDMOS further includes at least a trench filled with a conductive material and extending vertically from the body region near the top surface downwardly to electrically contact the source electrode disposed on the bottom surface of the semiconductor substrate.11-01-2012
20120273878THROUGH SILICON VIA PROCESSING TECHNIQUES FOR LATERAL DOUBLE-DIFFUSED MOSFETS - The present invention features a field effect transistor forming on a semiconductor substrate having formed thereon gate, source and drain regions, with said gate region having a lateral gate channel. A plurality of spaced-apart trenches each having an electrically conductive plug formed therein in electrical communication with said gate, source and drain regions, with said trenches extend from a back surface of said semiconductor substrate to a controlled depth. A trench contact shorts the source region and a body region. A source contact is in electrical communication with said source region and a drain contact in electrical communication with said drain region, with said source and drain contacts being disposed on opposite sides of said gate channel.11-01-2012
20110233670METHOD OF FORMING A REGION OF GRADED DOPING CONCENTRATION IN A SEMICONDUCTOR DEVICE AND RELATED APPARATUS - A method for forming a doped region of a semiconductor device includes masking a portion of a substrate with a mask. The mask is configured to create a graded doping profile within the doped region. The method also includes performing an implant using the mask to create doped areas and undoped areas in the substrate. The method further includes diffusing the doped areas to create the graded doping profile in the doped region. The mask could include a first region having openings distributed throughout a photo-resist material, where the openings vary in size and spacing. The mask could also include a second region having blocks of photo-resist material distributed throughout an open region, where the photo-resist blocks vary in size and spacing. Diffusing the doped areas could include applying a high temperature anneal to smooth the doped and undoped areas to produce a linearly graded doping profile.09-29-2011
20110233669Semiconductor device having depletion type MOS transistor - Provided is an improved depletion type MOS transistor for a semiconductor device, including: a first conductivity type well region on a semiconductor substrate; a gate insulating film formed on the well region; a gate electrode formed on the gate insulating film; second conductivity type source/drain regions formed on both sides of the gate electrode; a low concentration second conductivity type impurity region formed below the gate insulating film between the source/drain regions; and a low concentration first conductivity type impurity region formed below the low concentration second conductivity type impurity region between the source/drain regions.09-29-2011
20110233668SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a base region of a second conductivity type, a drift region of a first conductivity type, an insulating layer, a drain region of the first conductivity type, a gate oxide film, a gate electrode, a first main electrode, and a second main electrode. The base region includes a source region of the first conductivity type. The drift region is adjacent to the base region. The insulating layer is provided from a surface to inside of the drift region. The drain region is provided in the surface of the drift region and opposed to the source region across the base region and the insulating layer. The gate oxide film is provided on a surface of the base region. The gate electrode is provided on the gate oxide film. The first main electrode is connected to the source region. The second main electrode is connected to the drain region. As viewed in a direction perpendicular to the surface of the base region, the source region and at least a part of the drain region extend generally parallel in a line shape, and a length of a portion of the drift region sandwiched between the insulating layer and the base region is shorter in the generally parallel extending direction than in a direction generally perpendicular to the generally parallel extending direction.09-29-2011
20120280316Semiconductor Structure and Manufacturing Method for the Same - A semiconductor structure and a manufacturing method for the same are provided. The semiconductor structure includes a first doped well, a first doped electrode, a second doped electrode, doped strips and a doped top region. The doped strips are on the first doped well between the first doped electrode and the second doped electrode. The doped strips are separated from each other. The doped top region is on the doped strips and extended on the first doped well between the doped strips. The first doped well and the doped top region have a first conductivity type. The doped strips have a second conductivity type opposite to the first conductivity type.11-08-2012
20110309438SEMICONDUCTOR APPARATUS AND MANUFACTURING METHOD THEREOF - The semiconductor apparatus according to the present invention includes: a second-conductivity-type first diffusion region formed on the semiconductor layer; a first-conductivity-type second diffusion region formed in the first diffusion region; a second-conductivity-type first high concentration diffusion region and a first-conductivity-type second high concentration diffusion region formed in the second diffusion region; a second-conductivity-type third high concentration diffusion region, separated by a given distance from the second diffusion region, in the first diffusion region; and a gate electrode formed above and between the first high concentration diffusion region and third high concentration diffusion region, with a gate insulation film interposed therebetween, where the gate electrode is formed overlapping the first high concentration diffusion region, and the gate electrode is electrically connected with the first high concentration diffusion region and second high concentration diffusion region, at the same potential.12-22-2011
20120012929SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of the first conductivity type, a third semiconductor layer of a second conductivity type, a fourth semiconductor layer of the second conductivity type, a fifth semiconductor layer of the first conductivity type, a control electrode, a first main electrode, a second main electrode, and a sixth semiconductor layer of the first conductivity type. The second semiconductor layer and the third semiconductor layer are alternately provided on the first semiconductor layer in a direction substantially parallel to a major surface of the first semiconductor layer. The fourth semiconductor layer is provided on the second semiconductor layer and the third semiconductor layer. The fifth semiconductor layer is selectively provided on a surface of the fourth semiconductor layer. The control electrode is provided in a trench via an insulating film. The trench penetrates through the fourth semiconductor layer from a surface of the fifth semiconductor layer and is in contact with the second semiconductor layer. The first main electrode is connected to the first semiconductor layer. The second main electrode is connected to the fourth semiconductor layer and the fifth semiconductor layer. The sixth semiconductor layer is provided between the fourth semiconductor layer and the second semiconductor layer. An impurity concentration of the sixth semiconductor layer is higher than an impurity concentration of the second semiconductor layer.01-19-2012

Patent applications in class Active channel region has a graded dopant concentration decreasing with distance from source region (e.g., double diffused device, DMOS transistor)

Patent applications in all subclasses Active channel region has a graded dopant concentration decreasing with distance from source region (e.g., double diffused device, DMOS transistor)