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In integrated circuit structure

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257 - Active solid-state devices (e.g., transistors, solid-state diodes)

257213000 - FIELD EFFECT DEVICE

257288000 - Having insulated electrode (e.g., MOSFET, MOS diode)

257327000 - Short channel insulated gate field effect transistor

257329000 - Gate controls vertical charge flow portion of channel (e.g., VMOS device)

257330000 - Gate electrode in groove

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DocumentTitleDate
20130043530DATA STORING DEVICES AND METHODS OF FABRICATING THE SAME - A data storing device may include a substrate, transistors on the substrate that include gate line structures, and conductive isolation patterns defining active regions of the transistors. Each conductive isolation pattern includes at least one portion buried in the substrate and the conductive isolation patterns are electrically connected with each other.02-21-2013
20130043531VERTICALLY STACKED FIN TRANSISTORS AND METHODS OF FABRICATING AND OPERATING THE SAME - A semiconductor device is disclosed having vertically stacked (also referred to as vertically offset) transistors in a semiconductor fin. The semiconductor fin may include lower transistors separated by a first trench and having a source and drain in a first doped region of the fin. The semiconductor fin also includes upper transistors vertically offset from the first transistors and separated by a second trench and having a source and drain in a second doped region of the fin. Upper and lower stacked gates may be disposed on the sidewalls of the fin, such that the lower transistors are activated by biasing the lower gates and upper transistors are activated by biasing the upper gates. Methods of manufacturing and operating the device are also disclosed.02-21-2013
20130043529Circuit Structure with Vertical Double Gate - A circuit structure including a semiconductor substrate having a depression; a first insulating layer positioned on the surface of the depression; a bottom conductor positioned in a bottom portion of the depression, wherein the bottom conductor is connected to an external bias through a plurality of longer vertical contact plugs; an upper conductor positioned in an upper portion of the depression, wherein the upper conductor is connected to a plurality of shorter vertical contact plugs, and a top surface of the upper conductor is higher than a depression-bearing surface of the semiconductor substrate; and a second insulating layer positioned between the bottom conductor and the upper conductor.02-21-2013
20100155838TRENCH TYPE MOSFET DEVICE AND METHOD OF MANUFACTURING THE SAME - A trench type Metal Oxide Silicon Field Effect Transistor (MOSFET) device and a method of manufacturing a trench type MOSFET device. A trench type MOSFET device may include a wide-trench source contact poly which may be formed on and/or over a space between deep-trench gate polys on and/or over a trench type power MOSFET device. An electric field may be formed around a source contact poly and/or a gate poly. A relatively strong electric field may be minimized at an edge between a trench gate and a source. Leakage may be minimized and/or reliability may be maximized.06-24-2010
20080296674TRANSISTOR, INTEGRATED CIRCUIT AND METHOD OF FORMING AN INTEGRATED CIRCUIT - A transistor, an integrated circuit and a method of forming an integrated circuit is disclosed. One embodiment includes a gate electrode. The gate electrode is disposed in a gate groove formed in a semiconductor substrate and includes a conductive carbon material.12-04-2008
20130026563STRUCTURES AND METHODS FOR FORMING HIGH DENSITY TRENCH FIELD EFFECT TRANSISTORS - A semiconductor structure comprises trenches extending into a semiconductor region. Portions of the semiconductor region extend between adjacent trenches forming mesa regions. A gate electrode is in each trench. Well regions of a first conductivity type extend in the semiconductor region between adjacent trenches. Source regions of a second conductivity type are in the well regions. Heavy body regions of the first conductivity type are in the well regions. The source regions and the heavy body regions are adjacent trench sidewalls, and the heavy body regions extend over the source regions along the trench sidewalls to a top surface of the mesa regions.01-31-2013
20130026564Methods of Fabricating Semiconductor Devices - A method of fabricating a semiconductor device using a recess channel array is disclosed. A substrate is provided having a first region and a second region, including a first transistor in the first region including a first gate electrode partially filling a trench, and source and drain regions that are formed at both sides of the trench, and covered by a first insulating layer. A first conductive layer is formed on the substrate. A contact hole through which the drain region is exposed is formed by patterning the first conductive layer and the first insulating layer. A contact plug is formed that fills the contact hole. A bit line is formed that is electrically connected to the drain region through the contact plug, and simultaneously a second gate electrode is formed in the second region by patterning the first conductive layer.01-31-2013
20130134507SEMICONDUCTOR DEVICE INCLUDING SHARED PILLAR LOWER DIFFUSION LAYER - A semiconductor device includes a high-breakdown voltage transistor in which at least first and second vertical transistor are connected in series to each other. The first vertical transistor includes a first unit transistor group having a plurality of unit transistors each having a semiconductor pillar. The second vertical transistor includes a second unit transistor group having a plurality of unit transistors each having a semiconductor pillar. The plurality of unit transistors constituting the first and the second unit transistor groups have pillar lower diffusion layers which are shared.05-30-2013
20130134508SEMICONDUCTOR DEVICE WITH SIDE-JUNCTION AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes forming a plurality of bodies that are each isolated from another by a trench and each include a diffusion barrier region with a sidewall exposed to the trench, forming a doped layer gap-filling the trench, forming a sidewall junction at the exposed sidewall of the diffusion barrier region by annealing the doped layer, and forming a conductive line coupled with the sidewall junction to fill the trench.05-30-2013
20100140695Trench-Based Power Semiconductor Devices With Increased Breakdown Voltage Characteristics - Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed.06-10-2010
20130026562VERTICAL MEMORY CELL - Methods of forming, devices, and apparatus associated with a vertical memory cell are provided. One example method of forming a vertical memory cell can include forming a semiconductor structure over a conductor line. The semiconductor structure can have a first region that includes a first junction between first and second doped materials. An etch-protective material is formed on a first pair of sidewalls of the semiconductor structure above the first region. A volume of the first region is reduced relative to a body region of the semiconductor structure in a first dimension.01-31-2013
20120175701SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method for manufacturing the same are disclosed, in which a gate formed over a device isolation film is an inner gate inserted into a recess so that device operation characteristics are improved. A semiconductor device includes a recess formed in a device isolation film of a semiconductor substrate including an active region and the device isolation film, a gate formed over the recess and having a width smaller than that of the recess, and a capping film formed over a sidewall of a gate including the recess exposed by the gate.07-12-2012
20100072546SEMICONDUCTOR DEVICE - Provided is a semiconductor device in which on-resistance is largely reduced. The semiconductor device includes an n type epitaxial layer (03-25-2010
20130075814SEMICONDUCTOR DEVICE WITH A SEMICONDUCTOR VIA - A semiconductor device includes a semiconductor body having a first surface and a second surface, at least one electrode arranged in at least one trench extending from the first surface into the semiconductor body, and a semiconductor via extending in a vertical direction of the semiconductor body within the semiconductor body to the second surface. The semiconductor via is electrically insulated from the semiconductor body by a via insulation layer. The at least one electrode extends in a first lateral direction of the semiconductor body through the via insulation layer and is electrically connected to the semiconductor via.03-28-2013
20100006931VERTICAL DRAIN EXTENDED MOSFET TRANSISTOR WITH VERTICAL TRENCH FIELD PLATE - A vertical drain extended metal-oxide semiconductor field effect (MOSFET) transistor or a vertical double diffused metal-oxide semiconductor (VDMOS) transistor includes: a buried layer having a first conductivity type in a semiconductor backgate having a second conductivity type; an epitaxial (EPI) layer having the first conductivity type and formed above the buried layer; a deep well having the first conductivity type in the EPI layer extending down to the buried layer; at least one shallow well having the second conductivity type in the EPI layer; a shallow implant region having the first conductivity type and formed in the shallow well; a gate electrode having a lateral component extending over an edge of the shallow well and stopping at some spacing from an edge of the shallow implant and having a vertical trench field plate extending vertically into the EPI layer.01-14-2010
20090159966High voltage semiconductor device, method of fabricating the same, and method of fabricating the same and a low voltage semiconductor device together on a substrate - A high voltage semiconductor device comprises a substrate, a well, a gate structure, and a source/drain structure in a grade region in a well in the substrate. The gate structure is disposed on the substrate with a portion vertically down into a trench in the well in the substrate and has a relatively small size. The method of fabricating the high voltage semiconductor device comprises forming a first trench for an STI structure and a second trench for a gate structure, depositing an oxide layer on the substrate to fill the first and the second trenches, wherein a void is formed in the second trench, performing a photolithography and etching process to remove a portion of the oxide layer in the second trench, and forming a gate on the gate dielectric layer in the second trench.06-25-2009
20100320534Structure and Method for Forming a Thick Bottom Dielectric (TBD) for Trench-Gate Devices - A semiconductor structure which includes a shielded gate FET is formed as follows. A plurality of trenches is formed in a semiconductor region using a mask. The mask includes (i) a first insulating layer over a surface of the semiconductor region, (ii) a first oxidation barrier layer over the first insulating layer, and (iii) a second insulating layer over the first oxidation barrier layer. A shield dielectric is formed extending along at least lower sidewalls of each trench. A thick bottom dielectric (TBD) is formed along the bottom of each trench. The first oxidation barrier layer prevents formation of a dielectric layer along the surface of the semiconductor region during formation of the TBD. A shield electrode is formed in a bottom portion of each trench. A gate electrode is formed over the shield electrode in each trench.12-23-2010
20120181606VERTICAL CHANNEL TRANSISTOR ARRAY AND MANUFACTURING METHOD THEREOF - A vertical channel transistor array includes a plurality of embedded bit lines, a plurality of bit line contacts, a plurality of embedded word lines, and a current leakage isolation structure. An active area of a vertical channel transistor is defined by the semiconductor pillars. The embedded bit lines are disposed in parallel in a semiconductor substrate and extended in a column direction. Each of the bit line contacts is respectively disposed at a side of one of the embedded bit lines. The embedded word lines are disposed in parallel above the embedded bit lines and extended in a row direction. Besides, the embedded word lines and the semiconductor pillars in the same row are connected but spaced by a gate dielectric layer. The current leakage isolation structure is disposed at ends of the embedded bit lines to prevent current leakage between the adjacent bit line contacts.07-19-2012
20090315106Integrated trench Mosfet and Schottky Rectifier with trench contact structure - A trench MOSFET in parallel with trench Schottky barrier rectifier is formed on a single substrate. The present invention solves the constrains brought by planar contact of Schottky, for example, the large area occupied by planar structure. As the size of present device is getting smaller and smaller, the trench Schottky structure of this invention is able to be shrink and, at the same time, to achieve low specific on-resistance. By applying a double epitaxial layer in trench Schottky barrier rectifier, the device performance is enhanced for lower Vf and lower reverse leakage current Ir is achieved.12-24-2009
20090302382Power Ic Device and Method of Manufacturing Same - In one embodiment of the present invention, a power IC device is disclosed containing a power MOS transistor with a low ON resistance and a surface channel MOS transistor with a high operation speed. There is also provided a method of manufacturing such a device. A chip has a surface of which the planar direction is not less than −8° and not more than +8° off a silicon crystal face. The p-channel trench power MOS transistor includes a trench formed vertically from the surface of the chip, a gate region in the trench, an inversion channel region on a side wall of the trench, a source region in a surface layer of the chip, and a drain region in a back surface layer of the chip. The surface channel MOS transistor has an inversion channel region fabricated so that an inversion channel current flows in a direction not less than −8° and not more than +8° off the silicon crystal direction.12-10-2009
20120112273SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor substrate; a vertical type trench gate MOS transistor; a Schottky barrier diode; multiple trenches having a stripe pattern to divide an inner region into first and second separation regions; and a poly silicon film in each trench. The first separation region includes a first conductive type region for providing a source and a second conductive type layer for providing a channel region. The first conductive type region is adjacent to a first trench. The poly silicon film in the first trench is coupled with a gate wiring. A second trench is not adjacent to the first conductive type region. The poly silicon film in the second trench is coupled with a source or gate wiring. The substrate in the second separation region is coupled with the source wiring for providing a Schottky barrier.05-10-2012
20120112272Semiconductor Device Comprising Transistor Structures and Methods for Forming Same - A method for forming an opening within a semiconductor material comprises forming a neck portion, a rounded portion below the neck portion and, in some embodiments, a protruding portion below the rounded portion. This opening may be filled with a conductor, a dielectric, or both. Embodiments to form a transistor gate, shallow trench isolation, and an isolation material separating a transistor source and drain are disclosed. Device structures formed by the method are also described.05-10-2012
20130056823SEMICONDUCTOR DEVICES - A device isolation layer is formed in a substrate to define spaced-apart linear active regions in the substrate. Buried gate patterns are formed in the substrate and extending along a first direction to cross the active regions. An etch stop layer and a first insulating layer are formed on the substrate. Bit line structures are formed on the first insulating layer and extending along a second direction transverse to the first direction to cross the active regions. A second insulating layer is formed on the bit line structures. Contact plugs are formed penetrating the second insulating layer, the first insulating layer, and the etch stop layer to contact one of the active regions between adjacent ones of the bit line structures.03-07-2013
20130062690SEMICONDUCTOR DEVICE, AND MANUFACTURING METHOD FOR SAME - A semiconductor device has a source region, channel region, and drain region disposed in order from the surface of the device in the thickness direction of a semiconductor substrate. The device includes a source metal embedded in a source contact groove penetrating the source region and reaching the channel region, a gate insulating film formed on the side wall of a gate trench that is formed to penetrate the source region and channel and reach the drain region, a polysilicon gate embedded in trench so that at least a region facing the channel region in the insulating film is covered with the gate and so that the entire gate is placed under a surface of the source region, and a gate metal that is embedded in a gate contact groove formed in the gate so as to reach the depth of the channel region and in contact with the gate.03-14-2013
20110012195SEMICONDUCTOR DEVICE - Between a source electrode (01-20-2011
20090250750TRENCH GATE POWER MOSFET - A trench gate power MOSFET (10-08-2009
20130161738SEMICONDUCTOR DEVICE - A semiconductor device 06-27-2013
20090236660Insulated-Gate Field-Effect Transistor and Method of Making the Same - An IGFET that can be turned off when a reverse voltage is applied. Included is a semiconductor substrate having formed therein an n-type drain region, p-type first body region, p09-24-2009
20090236659ISOLATION STRUCTURE FOR SEMICONDUCTOR DEVICE WITH MULTIPLE TERMINALS - A semiconductor device has a first region (09-24-2009
20100264488Low Qgd trench MOSFET integrated with schottky rectifier - An integrated circuit includes a plurality of trench MOSFET and a plurality of trench Schottky rectifier. The integrated circuit further comprises: tilt-angle implanted body dopant regions surrounding a lower portion of all trench gates sidewalls for reducing Qgd; a source dopant region disposed below a bottom surface of all trench gates for functioning as a current path for preventing a resistance increased caused by the body dopant regions.10-21-2010
20110278666Trench MOSFET with integrated Schottky diode in a single cell and method of manufacture - A trench MOSFET with integrated Schottky diode in a single cell includes a plurality of body regions extending to an epitaxial layer; a first trench extending through one of the body regions and reaching the epitaxial layer, the first trench being substantially filled by a conductive material that is separated from a sidewall of the first trench by a layer of dielectric material; and a second trench positioned between two adjacent body regions and extended into the epitaxial layer. Two source regions, two heavy body contact regions and the two adjacent body regions surround the second trench. The trench MOSFET further includes a Schottky diode having a metal layer formed along a sidewall and near a bottom of the second trench. In its manufacturing method, the spacer and self-alignment are processed two times, thus low cost and high reliability performance of the device are achieved at the same time.11-17-2011
20110278667SEMICONDUCTOR COMPONENT ARRANGEMENT AND METHOD FOR PRODUCING THEREOF - A semiconductor component arrangement and method for producing thereof is disclosed. One embodiment provides at least one power semiconductor component integrated in a semiconductor body and at least one logic component integrated in the semiconductor body. The logic component includes a trench extending into the semiconductor body proceeding from a first side, at least one gate electrode arranged in the trench and insulated from the semiconductor body by a gate dielectric, and at least one source zone and at least one drain zone of a first conduction type, which are formed in the semiconductor body in a manner adjacent to the gate dielectric and in a manner spaced apart from one another in a peripheral direction of the trench and between which at least one body zone of a second conduction type is arranged.11-17-2011
20100127323Trench MOSFET with trench source contact having copper wire bonding - A trench MOSFET with trench source contact structure having copper wire bonding is disclosed. By employing the proposed structure, die size can be shrunk into 30%˜70% with high cell density, and the spreading resistance is significantly reduce without adding expensive thick metal layer as prior art. To further reduce fabricating cost, copper wire bonding is used with requirement of thick Al alloys.05-27-2010
20110298047THREE-DIMENSIONAL SEMICONDUCTOR DEVICE STRUCTURES AND METHODS - A three-dimensional semiconductor device includes a first semiconductor device, a second semiconductor device, and a patterned conductive layer disposed between the first and the second semiconductor devices. The first semiconductor device has a first plurality of terminals on a front side of the first semiconductor device and a first metal substrate on its back side, wherein one of the first plurality of terminals in the first semiconductor device is electrically coupled to the first metal substrate. The second semiconductor device has a second plurality of terminals on a front side of the second semiconductor device and a second metal substrate on its back side, wherein the second semiconductor device further includes a second metal substrate on its back side. The patterned conductive layer includes a plurality of conductive regions. Each of the conductive regions is bonded to a conductor coupled to one of the first plurality of terminals and another conductor coupled to one of the second plurality of terminals.12-08-2011
20100171174SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A gate trench 07-08-2010
20120286358SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device includes a semiconductor substrate having a first groove. The first groove has a bottom and first and second side surfaces opposite to each other. A first gate insulator extends alongside the first side surface. A first gate electrode is formed in the first groove and on the first gate insulator. A second gate insulator extends alongside the second side surface. A second gate electrode is formed in the first groove and on the second gate insulator. The second gate electrode is separate from the first gate electrode.11-15-2012
20110284955FIELD EFFECT TRANSISTOR WITH TRENCH FILLED WITH INSULATING MATERIAL AND STRIPS OF SEMI-INSULATING MATERIAL ALONG TRENCH SIDEWALLS - In accordance with an embodiment of the present invention, a MOSFET includes a first semiconductor region having a first surface, a first insulation-filled trench region extending from the first surface into the first semiconductor region, and strips of semi-insulating material along the sidewalls of the first insulation-filled trench region. The strips of semi-insulating material may be insulated from the first semiconductor region.11-24-2011
20110291186Semiconductor power devices manufactured with self-aligned processes and more reliable electrical contacts - This invention discloses semiconductor power device that includes a plurality of top electrical terminals disposed near a top surface of a semiconductor substrate. Each and every one of the top electrical terminals comprises a terminal contact layer formed as a silicide contact layer near the top surface of the semiconductor substrate. The trench gates of the semiconductor power device are opened from the top surface of the semiconductor substrate and each and every one of the trench gates comprises the silicide layer configured as a recessed silicide contact layer disposed on top of every on of the trench gates slightly below a top surface of the semiconductor substrate surround the trench gate.12-01-2011
20110291185Semiconductor Device Having an Edge Termination Structure and Method of Manufacture Thereof - A semiconductor device having a semiconductor body (12-01-2011
20100213541SEMICONDUCTOR DEVICE HAVING RECESS CHANNEL STRUCTURE - An integrated circuit device includes a semiconductor substrate including an active region defined by an isolation region and having at least one trench therein, a gate insulating layer formed in the at least one trench, a gate electrode layer having a nano-crystalline structure disposed on the gate insulating layer and a word line on the gate electrode layer in the at least one trench. The device may further include a capping layer on the word line.08-26-2010
20110101452TRENCH GATE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF - A trench-gate semiconductor device configuration is provided which is suitable for incorporation in integrated circuits, together with methods for its manufacture. A self-aligned drain region (05-05-2011
20120098061Structure and Method for Forming a Planar Schottky Contact - A monolithically integrated trench FET and Schottky diode includes a plurality of trenches extending into a FET region and a Schottky region of a semiconductor layer. A trench in the Schottky region includes a dielectric layer lining the trench sidewalls, and a conductive electrode having a top surface that is substantially coplanar with a top surface of the semiconductor layer adjacent the trench. An interconnect layer electrically contacts the semiconductor layer in the Schottky region so as to form a Schottky contact with the semiconductor layer.04-26-2012
20100264489SEMICONDUCTOR DEVICE - A transistor contains a first semiconductor layer of a first conductivity type and a drift layer having a pillar structure in which a second semiconductor layer of the first conductivity type and a third semiconductor layer of a second conductivity type are alternately disposed in a direction parallel to a surface of the first semiconductor layer. The fourth semiconductor layer of the first conductivity type and the fifth semiconductor layer of the second conductivity type are alternately disposed and parallel to the drift layer. The fifth semiconductor layer has a larger amount of impurities than the fourth semiconductor layer. The sixth semiconductor layer of the first conductivity type and the seventh semiconductor layer of the second conductivity type are alternately disposed and parallel to the fourth and the fifth semiconductor layers. The seventh semiconductor layer has a smaller amount of impurities than the sixth semiconductor layer.10-21-2010
20120025306SEMICONDUCTOR DEVICE - In general, according to one embodiment, a semiconductor device includes a first electrode, a first and a second semiconductor layer of a first conductivity type, a third semiconductor layer of a second conductivity type, a fourth semiconductor layer of the first conductivity type in this order. A device region includes a gate electrode inside a first trench. A second trench having a ring-shaped structure forms a first region penetrating through the fourth and third semiconductor layers to the second semiconductor layer and including the device region inside and a second region surrounding the first region outside. A first opening is provided between adjacent ones of the first trenches. A second opening having a wider width than the first opening is provided in the first region outside the device region. A second electrode is electrically connected to the third and fourth semiconductor layers through the first and second openings.02-02-2012
20120025305BIDIRECTIONAL SWITCH - An ON resistance of a bidirectional switch with a trench gate structure composed of two MOS transistors sharing a common drain is reduced. A plurality of trenches is formed in an N type well layer. Then a P type body layer is formed in every other column of the N type well layer interposed between a pair of the trenches. A first N+ type source layer and a second N+ type source layer are formed alternately in each of a plurality of the P type body layers. A first gate electrode is formed in each of a pair of the trenches interposing the first N+ type source layer, and a second gate electrode is formed in each of a pair of the trenches interposing the second N+ type source layer. A portion of the N type well layer interposed between a sidewall on an opposite side of the body layer of the trench in which the first gate electrode is formed and a sidewall on an opposite side of the body layer of the trench in which the second gate electrode is formed makes an N type drain layer serving as an electric field relaxation layer. A cross-sectional area of the N type drain layer makes a path of the ON current.02-02-2012
20090014789Semiconductor device and method for manufacturing the same - A semiconductor device comprising a recessed transistor coexists with P-N gate planar-type transistors, wherein high-concentration impurity-diffused material 01-15-2009
20090014788SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A type semiconductor device includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type; a third semiconductor layer of the first conductivity type; a plurality of gate electrodes which are formed in gate trenches via gate insulating films, the gate trenches being formed through the second semiconductor layer and the third semiconductor layer; a plurality of impurity regions of the second conductivity type which are formed at regions below bottoms of contact trenches, the contact trenches being formed at the third semiconductor layer in a thickness direction thereof between corresponding ones of the gate trenches and longitudinal cross sections of the contact trenches being shaped in ellipse, respectively; first electrodes which are formed so as to embed the contact trenches and contacted with the impurity regions, respectively; and a second electrode formed on a rear surface of the semiconductor substrate.01-15-2009
20090189219SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - The present invention provides a technique capable of attaining an improvement in current detection accuracy in a trench gate type power MISFET equipped with a current detection circuit. Inactive cells are disposed so as to surround the periphery of a sense cell. That is, the inactive cell is provided between the sense cell and an active cell. All of the sense cell, active cell and inactive cells are respectively formed of a trench gate type power MISFET equipped with a dummy gate electrode. At this time, the depth of each trench extends through a channel forming region and is formed up to the deep inside (the neighborhood of a boundary with a semiconductor substrate) of an n-type epitaxial layer. Further, a p-type semiconductor region is provided at a lower portion of each trench. The p-type semiconductor region is formed so as to contact the semiconductor substrate.07-30-2009
20090146209SEMICONDUCTOR DEVICE - A semiconductor device includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type provided on a main surface of the first semiconductor layer and having a lower impurity concentration than that of the first semiconductor layer; a third semiconductor layer of a second conductivity type provided on the second semiconductor layer; a fourth semiconductor layer of the first conductivity type selectively provided on the third semiconductor layer; a gate electrode provided in a trench passing through the third semiconductor layer and reaching the second semiconductor layer; a first main electrode contacting the fourth semiconductor layer and contacting the third semiconductor layer through a contact groove provided to pass through the fourth semiconductor layer between the contiguous gate electrodes; a second main electrode provided on an opposite surface to the main surface of the first semiconductor layer; and a fifth semiconductor layer of the second conductivity type provided in an interior portion of the second semiconductor layer corresponding to a part under the contact groove. An uppermost portion of the fifth semiconductor layer contacts the third semiconductor layer, a lowermost portion of the fifth semiconductor layer has a higher impurity concentration than that of the other portion in the fifth semiconductor layer and is located in the second semiconductor layer and not contacting the first semiconductor layer, and the fifth semiconductor layer is narrower from the uppermost portion to the lower most portion.06-11-2009
20080296675SEMICONDUCTOR DEVICE - The invention realizes low on-resistance and high current flow in a semiconductor device in which a current flows in a thickness direction of a semiconductor substrate. A first MOS transistor having first gate electrodes and first source layers is formed on a front surface of a semiconductor substrate, and a second MOS transistor having second gate electrodes and second source layers is formed on a back surface thereof. A drain electrode connected to the semiconductor substrate, a first source electrode connected to the first source layers, a second source electrode connected to the second source layers, and a first penetration hole penetrating the semiconductor substrate are further formed. A first wiring connecting the first source electrode and the second source electrode is formed in the first penetration hole. The semiconductor substrate serves as a common drain region of the first and second MOS transistors.12-04-2008
20080265318SEMICONDUCTOR COMPONENT AND METHOD FOR PRODUCING IT - A semiconductor component includes a surface region. A modified doping region is provided in the edge region of the cell array. In the surface region or modified doping region the doping concentration is lowered and/or in the surface region or modified doping region the conductivity type is formed such that it is opposite to the conductivity type of the actual semiconductor material region, or in which a field plate region is provided.10-30-2008
20100123193SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE - A semiconductor component that includes gate electrodes and shield electrodes and a method of manufacturing the semiconductor component. A semiconductor material has a device region, a gate contact region, a termination region, and a drain contact region. One or more device trenches is formed in the device region and one or more termination trenches is formed in the edge termination region. Shielding electrodes are formed in portions of the device trenches that are adjacent their floors. A gate dielectric material is formed on the sidewalls of the trenches in the device region and gate electrodes are formed over and electrically isolated from the shielding electrodes. The gate electrodes in the trenches in the device region are connected to the gate electrodes in the trenches in the gate contact region. The shielding electrodes in the trenches in the device region are connected to the shielding electrodes in the termination region.05-20-2010
20120187481Vertical Trench LDMOS Transistor - A vertical trench LDMOS transistor includes a semiconductor layer of a first conductivity type; a first trench formed in the semiconductor layer and filled with a trench dielectric and a trench gate is formed in the first trench; a body region of a second conductivity type formed in the semiconductor layer adjacent the first trench; a source region formed in the body region and adjacent the first trench; a planar gate insulated from the semiconductor layer by a second gate dielectric layer and overlying the body region; and a drain drift region formed in the semiconductor layer. The planar gate forms a lateral channel in the body region between the source region and the drain drift region, and the trench gate in the first trench forms a vertical channel in the body region along the sidewall of the first trench between the source region and the semiconductor layer.07-26-2012
20120187480PROCESS FOR MANUFACTURING A POWER SEMICONDUCTOR DEVICE HAVING CHARGE-BALANCE COLUMNAR STRUCTURES ON A NON-PLANAR SURFACE, AND CORRESPONDING POWER SEMICONDUCTOR DEVICE - An embodiment of a process for manufacturing a power semiconductor device envisages the steps of: providing a body of semiconductor material having a top surface and having a first conductivity; forming columnar regions having a second type of conductivity within the body of semiconductor material, and surface extensions of the columnar regions above the top surface; and forming doped regions having the second type of conductivity, in the proximity of the top surface and in contact with the columnar regions. The doped regions are formed at least partially within the surface extensions of the columnar regions; the surface extensions and the doped regions have a non-planar surface pattern, in particular with a substantially V-shaped groove.07-26-2012
20120187479PROCESS FOR MANUFACTURING A POWER SEMICONDUCTOR DEVICE HAVING CHARGE-BALANCE COLUMNAR STRUCTURES ON A NON-PLANAR SURFACE, AND CORRESPONDING POWER SEMICONDUCTOR DEVICE - An embodiment of a process for manufacturing a power semiconductor device envisages the steps of: providing a body of semiconductor material having a top surface and having a first conductivity; forming columnar regions having a second type of conductivity within the body of semiconductor material, and surface extensions of the columnar regions above the top surface; and forming doped regions having the second type of conductivity, in the proximity of the top surface and in contact with the columnar regions. The doped regions are formed at least partially within the surface extensions of the columnar regions; the surface extensions and the doped regions have a non-planar surface pattern, in particular with a substantially V-shaped groove.07-26-2012
20110147836Charged balanced devices with shielded gate trench - This invention discloses a semiconductor power device disposed on a semiconductor substrate includes a plurality of deep trenches with an epitaxial layer filling said deep trenches and a simultaneously grown top epitaxial layer covering areas above a top surface of said deep trenches over the semiconductor substrate. A plurality of trench MOSFET cells disposed in said top epitaxial layer with the top epitaxial layer functioning as the body region and the semiconductor substrate acting as the drain region whereby a super-junction effect is achieved through charge balance between the epitaxial layer in the deep trenches and regions in the semiconductor substrate laterally adjacent to the deep trenches. Each of the trench MOSFET cells further includes a trench gate and a gate-shielding dopant region disposed below and substantially aligned with each of the trench gates for each of the trench MOSFET cells for shielding the trench gate during a voltage breakdown.06-23-2011
20090242980Semiconductor device including capacitor element and method of manufacturing the same - In a semiconductor device, a memory region and a logic region are provided on one silicon substrate. A trench is provided in the silicon substrate in the memory region, a memory cell transistor is provided in the memory region and a logic transistor is provided in the logic region. The memory cell transistor includes a first gate electrode constituted by a metal material. The first gate electrode is provided to be buried in the trench and to protrude outside of the trench. The logic transistor includes a second gate electrode constituted by same material as the metal material constituting the first gate electrode.10-01-2009
20110062515SEMICONDUCTOR DEVICE - A first gate electrode surrounding the periphery of the first gate insulating film, a second gate insulating film surrounding the periphery of the first gate electrode, a first columnar silicon layer surrounding the periphery of the second gate insulating film, a first upper part high concentration semiconductor layer of the first conductivity type formed in the upper part of the first island-shaped silicon layer, a second lower part high concentration semiconductor layer of the first conductivity type formed in the lower part of the first island-shaped silicon layer, a first upper part high concentration semiconductor layer of the second conductivity type formed in the upper part of the first columnar silicon layer, and a second lower part high concentration semiconductor layer of the second conductivity type formed in the lower part of the first columnar silicon layer.03-17-2011
20110062514SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A first semiconductor element portion for switching a first current includes a first channel surface having a first plane orientation. A first region of a semiconductor layer includes a first trench having the first channel surface. A first gate insulating film covers the first channel surface with a first thickness. A second semiconductor element portion for switching a second current smaller than the first current includes a second channel surface having a second plane orientation different from the first plane orientation. A second region of the semiconductor layer includes a second trench having the second channel surface. A second gate insulating film covers the second channel surface with a second thickness larger than the first thickness.03-17-2011
20100127325Recessed channel transistors, and semiconductor devices including a recessed channel transistor - A recessed channel transistor, a semiconductor device including a transistor and methods of manufacturing the same are provided, the recessed channel transistor includes a gate structure, a second impurity region and a first impurity region. The gate structure may be formed on a substrate and filling a recess. The first impurity region, including first impurities, may be formed at a first upper portion of the substrate adjacent to the gate structure. The second impurity region, including second impurities, may be formed at a second upper portion of the substrate contacting the gate structure. The first impurity region may surround the second impurity region. The first impurities have a conductive type different from that of the second impurities.05-27-2010
20100006932Semiconductor device and method of manufacturing the same - A semiconductor device, including: a first transistor formed on a substrate and including an Hf contained film as its gate insulating film; and a second transistor formed on said substrate and having the same conductive type as that of said first transistor, said second transistor including a silicon oxide film and not including an Hf contained film as its gate insulating film is provided.01-14-2010
20120193706VERTICAL TRANSISTOR FOR RANDOM-ACCESS MEMORY AND MANUFACTURING METHOD THEREOF - A manufacturing method for a vertical transistor of random-access memory, having the steps of: defining an active region on a semiconductor substrate; forming a shallow trench isolation structure outside of the active region; etching the active region and forming a gate dielectric layer and a positioning gate thereon, forming a word line perpendicular to the positioning gate; forming spacing layers on the outer surfaces of the word line; implanting ions to the formed structure in forming an n-type and a p-type region on opposite sides of the word line with the active region; forming an n-type and a p-type floating body respectively on the n-type and p-type region; forming a source line perpendicular to the word line and connecting to the n-type floating body; forming a bit line perpendicular to the source line and connecting to the p-type floating body. Hence, a vertical transistor with steady threshold voltage is achieved.08-02-2012
20080211019FIELD-EFFECT TRANSISTOR AND METHOD FOR MANUFACTURING A FIELD-EFFECT TRANSISTOR - A field-effect transistor and a method for manufacturing a field-effect transistor is disclosed. One embodiment includes a substrate having a surface along which a trench is implemented, wherein the trench has a trench bottom and a trench edge. A source area is implemented at the trench edge and a gate electrode at least partially implemented in the trench and separated from the substrate by an insulation layer. The field-effect transistor includes a drain electrode at a side of the substrate facing away from the surface. An additional electrode is implemented between the gate electrode and the trench bottom and electrically insulated from the substrate and an electrical connection between the additional electrode and the gate electrode, wherein the electrical connection has a predetermined ohmic resistance value.09-04-2008
20090114985Semiconductor apparatus and method for manufacturing the same - A semiconductor apparatus is disclosed. The semiconductor apparatus includes a semiconductor substrate that has a first surface and a second surface opposite to each other. The semiconductor apparatus further includes multiple double-sided electrode elements each having a pair of electrodes located respectively on the first and second surfaces of the semiconductor substrate. A current flows between the first and second electrode. Each double-sided electrode element has a PN column region located in the semiconductor substrate. The semiconductor apparatus further includes an insulation trench that surrounds each of multiple double-sided electrode elements, and that insulates and separates the multiple double-sided electrode elements from each other.05-07-2009
20090273027Power IC Device and Method for Manufacturing Same - In a power IC device, a surface layer channel CMOS transistor and a trench power MOS transistor are formed on the same chip. In one embodiment, a source region of the trench power MOS transistor is arranged at the same level as a gate electrode of the surface layer channel CMOS transistor. Thus, the power IC device and a method for manufacturing the power IC device are provided for reducing manufacturing cost in the case of forming the trench power MOS transistor and the surface layer channel CMOS transistor on the same chip.11-05-2009
20100219470SEMICONDUCTOR DEVICE HAVING A SADDLE FIN SHAPED GATE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device having a saddle fin gate and a method for manufacturing the same are presented. The semiconductor device includes a semiconductor substrate, an isolation structure, and gates. The semiconductor substrate is defined with first grooves in gate forming areas. The isolation structure is formed in the semiconductor substrate and is defined with second grooves which expose front and rear surfaces of the gate forming areas. The gates are formed within the first grooves in the gate forming areas. Gates are also formed in the second grooves of the isolation structure to cover the exposed front and rear surfaces of the gate forming areas. The second grooves are wider at the lower portions that at the upper portions.09-02-2010
20130099311INTEGRATED GATE RUNNER AND FIELD IMPLANT TERMINATION FOR TRENCH DEVICES - In one general aspect, an apparatus can include a plurality of trench metal-oxide-semiconductor field effect transistors (MOSFET) devices formed within an epitaxial layer of a substrate, and a gate-runner trench disposed around the plurality of trench MOSFET devices and disposed within the epitaxial layer. The apparatus can also include a floating-field implant defined by a well implant and disposed around the gate-runner trench.04-25-2013
20090294847Plasma Display Apparatus - A plasma display apparatus which in its driving circuit mounts at least one of IGBTs having diodes built-in which are reverse conducting in a driving device which supplies a light emitting current and IGBTs having diodes built-in which have a reverse blocking function in a driving device which collects and charges the power.12-03-2009
20120292696SEMICONDUCTOR DEVICE HAVING REDUCED GATE CHARGES AND SUPERIOR FIGURE OF MERIT - A semiconductor device includes a first group of trench-like structures and a second group of trench-like structures. Each trench-like structure in the first group includes a gate electrode contacted to gate metal and a source electrode contacted to source metal. Each of the trench-like structures in the second group is disabled. The second group of disabled trench-like structures is interleaved with the first group of trench-like structures.11-22-2012
20120292695MONOLITHIC METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR-SCHOTTKY DIODE DEVICE - A monolithic metal oxide semiconductor field effect transistor (MOSFET)-Schottky diode device including a chip, a MOSFET, a Schottky diode and a termination structure is provided. The chip is divided into a transistor region, a diode region and a termination region. The MOSFET is disposed on the transistor region. The Schottky diode is disposed on the diode region. The termination structure is disposed on the termination region. The transistor region and the diode region are divided by the termination region. The MOSFET and Schottky diode share the termination structure.11-22-2012
20130119465DUAL CHANNEL TRENCH LDMOS TRANSISTORS AND TRANSISTORS INTEGRATED THEREWITH - A dual channel trench LDMOS transistor includes a semiconductor layer of a first conductivity type formed on a substrate; a first trench formed in the semiconductor layer where a trench gate is formed in an upper portion of the first trench; a body region of the second conductivity type formed in the semiconductor layer adjacent the first trench; a source region of the first conductivity type formed in the body region and adjacent the first trench; a planar gate overlying the body region; a drain drift region of the first conductivity type formed in the semiconductor layer and in electrical contact with a drain electrode. The planar gate forms a lateral channel in the body region, and the trench gate in the first trench forms a vertical channel in the body region of the LDMOS transistor.05-16-2013
20100140696Trench-Based Power Semiconductor Devices With Increased Breakdown Voltage Characteristics - Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed.06-10-2010
20090127619DEEP TRENCH SEMICONDUCTOR STRUCTURE AND METHOD - An electrical structure and method of forming. The electrical structure includes a semiconductor substrate comprising a deep trench, an oxide liner layer is formed over an exterior surface of the deep trench, and a field effect transistor (FET) formed within the semiconductor substrate. The first FET includes a source structure, a drain structure, and a gate structure. The gate structure includes a gate contact connected to a polysilicon fill structure. The polysilicon fill structure is formed over the oxide liner layer and within the deep trench. The polysilicon fill structure is configured to flow current laterally across the polysilicon fill structure such that the current will flow parallel to a top surface of the semiconductor substrate.05-21-2009
20120299092SEMICONDUCTOR COMPONENT ARRANGEMENT AND METHOD FOR PRODUCING THEREOF - A semiconductor component arrangement and method for producing thereof is disclosed. One embodiment provides at least one power semiconductor component integrated in a semiconductor body and at least one logic component integrated in the semiconductor body. The logic component includes a trench extending into the semiconductor body proceeding from a first side, at least one gate electrode arranged in the trench and insulated from the semiconductor body by a gate dielectric, and at least one source zone and at least one drain zone of a first conduction type, which are formed in the semiconductor body in a manner adjacent to the gate dielectric and in a manner spaced apart from one another in a peripheral direction of the trench and between which at least one body zone of a second conduction type is arranged.11-29-2012
20090072307Semiconductor integrated circuit and method of manufacturing the same - A semiconductor integrated circuit includes a semiconductor substrate, a plurality of trenches formed to extend in one direction in the semiconductor substrate, at least one connecting trench connecting at least two of the plurality of trenches to each other, a plurality of trench transistors including a plurality of gate electrodes, each gate electrode partially filling a corresponding trench, and a capping layer filling the at least one connecting trench.03-19-2009
20090085109Semiconductor device and method of manufacturing semiconductor device - A semiconductor device according to the present invention includes: a semiconductor layer of a first conductivity type; a body region of a second conductivity type formed in a surface layer portion of the semiconductor layer; a trench dug from the surface of the semiconductor layer to penetrate the body region; a source region of a first conductivity type formed on a side portion of the trench in a surface layer portion of the body region; a gate insulating film formed on the bottom surface and the side surface of the trench; a gate electrode embedded in the trench through the gate insulating film and so formed that the surface thereof is lower by one stage than the surface of the source region; and a peripheral wall film formed on a peripheral edge portion of the surface of the gate electrode to be opposed to an upper end portion of the side surface of the trench.04-02-2009
20090085108SEMICONDUCTOR DEVICE HAVING CELL TRANSISTOR WITH RECESS CHANNEL STRUCTURE - The present invention provides a semiconductor device comprising: a dual-gate peripheral transistor having a transistor structure of surface channel nMOSFET and a transistor structure of surface channel pMOSFET; and a cell transistor having an nMOSFET structure with a recess channel structure, a gate electrode of the cell transistor having an N-type polysilicon layer which contains of N-type impurities at an approximately constant concentration.04-02-2009
20120104491Memory Cells, Arrays Of Memory Cells, And Methods Of Forming Memory Cells - A memory cell includes a vertically oriented transistor having an elevationally outer source/drain region, an elevationally inner source/drain region, and a channel region elevationally between the inner and outer source/drain regions. The inner source/drain region has opposing laterally outer sides. One of a pair of data/sense lines is electrically coupled to and against one of the outer sides of the inner source/drain region. The other of the pair of data/sense lines is electrically coupled to and against the other of the outer sides of the inner source/drain region. An access gate line is elevationally outward of the pair of electrically coupled data/sense lines and is operatively adjacent the channel region. A charge storage device is electrically coupled to the outer source/drain region. Other embodiments and additional aspects, including methods, are disclosed.05-03-2012
20110227153Vertical Mosfet with Through-Body Via for Gate - In an embodiment, set forth by way of example and not limitation, a MOSFET power chip includes a first vertical MOSFET and a second vertical MOSFET. The first vertical MOSFET includes a semiconductor body having a first surface defining a source and a second surface defining a drain and a gate structure formed in the semiconductor body near the second surface. A via is formed within the semiconductor body and is substantially perpendicular to the first surface and the second surface. The via has a first end electrically coupled to the first surface and a second end electrically coupled to the gate structure. The second vertical MOSFET includes a semiconductor body having a first surface defining a source, a second surface defining a drain and a gate structure formed in the semiconductor body near the first surface. The first surface of the first vertical MOSFET and the second surface of the second vertical MOSFET are substantially co-planar and an electrically conductive can substantially surrounds the MOSFETS and shorts the first surface of the first vertical MOSFET to the second surface of the second vertical MOSFET.09-22-2011
20110227152TRENCH DMOS DEVICE WITH IMPROVED TERMINATION STRUCTURE FOR HIGH VOLTAGE APPLICATIONS - A termination structure for a power transistor includes a semiconductor substrate having an active region and a termination region. The substrate has a first type of conductivity. A termination trench is located in the termination region and extends from a boundary of the active region to within a certain distance of an edge of the semiconductor substrate. A doped region has a second type of conductivity disposed in the substrate below the termination trench. A MOS gate is formed on a sidewall adjacent the boundary. The doped region extends from below a portion of the MOS gate spaced apart from the boundary toward a remote sidewall of the termination trench. A termination structure oxide layer is formed on the termination trench and covers a portion of the MOS gate and extends toward the edge of the substrate. A first conductive layer is formed on a backside surface of the semiconductor substrate. A second conductive layer is formed atop the active region, an exposed portion of the MOS gate, and extends to cover at least a portion of the termination structure oxide layer.09-22-2011
20090230467SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - In a power MISFET having a trench gate structure with a dummy gate electrode, a technique is provided for improving the performance of the power MISFET, while preventing electrostatic breakdown of a gate insulating film therein. A power MISFET having a trench gate structure with a dummy gate electrode, and a protective diode are formed on the same semiconductor substrate. The protective diode is provided between a source electrode and a gate interconnection. In a manufacturing method of such a semiconductor device, a polycrystalline silicon film for the dummy gate electrode and a polycrystalline silicon film for the protective diode are formed simultaneously. A source region of the power MISFET and an n09-17-2009
20090200608SEMICONDUCTOR DEVICE - To attain reduction in size of a semiconductor device having a power transistor and an SBD, a semiconductor device according to the present invention comprises a first region and a second region formed on a main surface of a semiconductor substrate; plural first conductors and plural second conductors formed in the first and second regions respectively; a first semiconductor region and a second semiconductor region formed between adjacent first conductors in the first region, the second semiconductor region lying in the first semiconductor region and having a conductivity type opposite to that of the first semiconductor region; a third semiconductor region formed between adjacent second conductors in the second region, the third semiconductor region having the same conductivity type as that of the second semiconductor region and being lower in density than the second semiconductor region; a metal formed on the semiconductor substrate in the second region, the third semiconductor region having a metal contact region for contact with the metal, the metal being electrically connected to the second semiconductor region, and a center-to-center distance between adjacent first conductors in the first region being smaller than that between adjacent second conductors in the second region.08-13-2009
20080315302Method of Forming Nanotube Vertical Field Effect Transistor - A nanotube field effect transistor and a method of fabrication are disclosed. The method includes electrophoretic deposition of a nanotube to contact a region of a conductive layer defined by an aperture.12-25-2008
20090256198SEMICONDUCTOR DEVICES HAVING LINE TYPE ACTIVE REGIONS AND METHODS OF FABRICATING THE SAME - In a semiconductor device having line type active regions and a method of fabricating the semiconductor device, the semiconductor device includes a device isolation layer which defines the line type active regions in a in a semiconductor substrate. Gate electrodes which are parallel to each other and intersect the line type active regions are disposed over the semiconductor substrate. Here, the gate electrodes include both a device gate electrode and a recessed device isolation gate electrode. Alternatively, each of the gate electrodes is constituted of a device gate electrode and a plan type device isolation gate electrode, and a width of the plan type device isolation gate electrode greater than a width of the device gate electrode.10-15-2009
20090315107INTEGRATED TRENCH MOSFET AND JUNCTION BARRIER SCHOTTKY RECTIFIER WITH TRENCH CONTACT STRUCTURES - A trench MOSFET in parallel with trench junction barrier Schottky rectifier with trench contact structures is formed in single chip. The present invention solves the drawback brought by some prior arts, for example, the large area occupied by planar contact structure and high gate-source capacitance. As the electronic devices become more miniaturized, the trench contact structures of this invention are able to be shrunk to achieve low specific on-resistance of Trench MOSFET, and low Vf and reverse leakage current of the Schottky Rectifier.12-24-2009
20090256196THREE-DIMENSIONAL SEMICONDUCTOR DEVICE STRUCTURES AND METHODS - A three-dimensional semiconductor device structure includes a first semiconductor device and a second semiconductor device bonded together using a patterned conductive layer according to an embodiment of the invention. The first semiconductor device includes a first plurality of terminals on its front side, and the second semiconductor device includes a second plurality of terminals on its front side. The patterned conductive layer includes a plurality of conductive regions. Each of the conductive regions is bonded to a conductor coupled to one of the first plurality of terminals and bonded to another conductor coupled to one of the second plurality of terminals, providing electrical coupling between the first semiconductor device and the second semiconductor device. In a specific embodiment, each terminal of the first semiconductor device is bonded to a corresponding terminal of the second semiconductor device, providing a parallel combination of the first and the second semiconductor devices.10-15-2009
20090256197SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Provided is a technology, in a semiconductor device having a power MISFET and a Schottky barrier diode on one semiconductor substrate, capable of suppressing a drastic increase in the on-resistance of the power MISFET while making the avalanche breakdown voltage of the Schottky barrier diode greater than that of the power MISFET. In the present invention, two epitaxial layers, one having a high doping concentration and the other having a low doping concentration, are formed over a semiconductor substrate and the boundary between these two epitaxial layers is located in a region equal in depth to or shallower than the bottom portion of a trench.10-15-2009
20100013010POWER SEMICONDUCTOR DEVICE - An impurity concentration profile in a vertical direction of a p type base contact layer of a power semiconductor device has a two-stage configuration. In other word, the impurity concentration profile is highest at an upper face of the p type base contact layer, has a local minimum value at a position other than the upper face and a lower face of the base contact layer, and has a local maximum value at a position lower than the position of the local minimum value.01-21-2010
20100155836CO-PACKAGING APPROACH FOR POWER CONVERTERS BASED ON PLANAR DEVICES, STRUCTURE AND METHOD - A voltage converter includes an output circuit having a high-side device and a low-side device which can be formed on a single die (a “PowerDie”). The high-side device can include a lateral diffused metal oxide semiconductor (LDMOS) while the low-side device can include a planar vertical diffused metal oxide semiconductor (VDMOS). The voltage converter can further include a controller circuit on a different die which can be electrically coupled to, and co-packaged with, the power die.06-24-2010
20100155837SINGLE DIE OUTPUT POWER STAGE USING TRENCH-GATE LOW-SIDE AND LDMOS HIGH-SIDE MOSFETS, STRUCTURE AND METHOD - A voltage converter includes an output circuit having a high-side device and a low-side device which can be formed on a single die (a “PowerDie”). The high-side device can include a lateral diffused metal oxide semiconductor (LDMOS) while the low-side device can include a trench-gate vertical diffused metal oxide semiconductor (VDMOS). The voltage converter can further include a controller circuit on a different die which can be electrically coupled to, and co-packaged with the output circuit.06-24-2010
20110127605SEMICONDUCTOR DEVICE WITH BURIED BIT LINES AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes: a semiconductor substrate configured to include a plurality of trenches therein; a plurality of buried bit lines each configured to fill a portion of each trench; a plurality of active pillars each formed in an upper portion of each buried bit line; a plurality of vertical gates each configured to surround each active pillar; and a plurality of word lines configured to couple neighboring vertical gates with each other.06-02-2011
20100148248SEMICONDUCTOR DEVICE HAVING GATE TRENCHES AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a first gate trench, a second gate trench, and a dummy gate trench provided in an active region extending in an X direction; and a first gate electrode, a second gate electrode, and a dummy gate electrode extending in a Y direction crossing the active region, at least a part of which are buried in the first gate trench, the second gate trench, and the dummy gate trench, respectively. The dummy gate electrode arranged between second and third diffusion layers isolates and separates a transistor constituted by the first gate electrode and first and second diffusion layers provided on both sides of the first gate electrode, respectively, from a transistor constituted by the second gate electrode and third and fourth diffusion layers provided on both sides of the second gate electrode, respectively.06-17-2010
20130214350INTEGRATED TRENCH MOSFET WITH TRENCH SCHOTTKY RECTIFIER - An integrated circuit comprising trench MOSFET having trenched source-body contacts and trench Schottky rectifier having trenched anode contacts is disclosed. By employing the trenched contacts in trench MOSFET and trench Schottky rectifier, the integrated circuit is able to be shrunk to achieve low specific on-resistance for trench MOSFET, and low V08-22-2013
20130214351SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device having a VDMOSFET (Vertical Double-diffused Metal Oxide Semiconductor Field-Effect Transistor) and a planar gate MOSFET (Metal Oxide Semiconductor Field-Effect Transistor), including forming a semiconductor layer of a first conductivity type by epitaxy, forming a body region recess for forming a body region of the VDMOSFET on the semiconductor layer, and embedding a semiconductor material of a second conductivity type in the body region recess by epitaxy or CVD (Chemical Vapor Deposition).08-22-2013
20120032261TRENCH MOSFET HAVING FLOATING DUMMY CELLS FOR AVALANCHE IMPROVEMENT - A trench MOSFET comprising source regions having a doping profile of a Gaussian-distribution along the top surface of epitaxial layer and floating dummy cells formed between edge trench and active area is disclosed. A SBR of n region existing at cell corners renders the parasitic bipolar transistor difficult to turn on, and the floating dummy cells having no parasitic bipolar transistor act as buffer cells to absorb avalanche energy when gate bias is increasing for turning on channel, therefore, the UIS failure issue is avoided and the avalanche capability of the trench MOSFET is enhanced.02-09-2012
20100193864SEMICONDUCTOR DEVICE - A semiconductor device includes a plurality of first gate electrodes that are arranged above a semiconductor substrate in a first direction, and a plurality of second gate electrodes that are arranged above the semiconductor substrate in a second direction. The semiconductor device further includes a first gate lead-out electrode to which the first gate electrodes are connected, a second gate lead-out electrode to which the second gate electrodes are connected, and a third gate lead-out electrode to which the first gate lead-out electrode and the second gate lead-out electrode are connected. In the semiconductor device according to the present invention, a punched pattern is formed in the third gate lead-out electrode.08-05-2010
20100176447SEMICONDUCTOR DEVICE - Provided is a semiconductor device in which on-resistance is largely reduced. The semiconductor device includes an n type epitaxial layer (07-15-2010
20100176446MOSFET with source contact in trench and integrated schottky diode - A trench semiconductor power device with integrated Schottky diode is disclosed. P+ regions and n+ source regions are alternately arranged in mesa and on top of trench sidewall along stripe source-body contact area between two adjacent trenches. By employing this structure, cell density increased remarkably without increasing contact resistance because top portion of gate trench sidewall is provided as source-body contact area.07-15-2010
20100230747PROCESS FOR MANUFACTURING A POWER DEVICE WITH A TRENCH-GATE STRUCTURE AND CORRESPONDING DEVICE - An embodiment for realizing a power device with trench-gate structure integrated on a semiconductor substrate, and including etching the semiconductor substrate to make a first trench having first side walls and a first bottom; and further etching said semiconductor substrate to make a second trench inside the first trench, realized in a self-aligned way and below this first trench, the first trench and the second trench defining the trench-gate structure with a bird beak-like transition profile suitable for containing a gate region.09-16-2010
20100001341SEMICONDUCTOR DEVICE - A semiconductor device of the present invention has a first-conductivity-type substrate having second-conductivity-type base regions exposed to a first surface thereof; trench gates provided to a first surface of the substrate; first-conductivity-type source regions formed shallower than the base regions; a plurality of second-conductivity-type column regions located between two adjacent trench gates in a plan view, while being spaced from each other in a second direction normal to the first direction; the center of each column region and the center of each base contact region fall on the center line between two trench gates; and has no column region formed below the trench gates.01-07-2010
20100001340SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a step-type recess pattern formed in a substrate, a gate electrode buried in the recess pattern and having a gap disposed between the gate electrode and upper sidewalls of the recess pattern, an insulation layer filling the gap, and a source and drain region formed in a portion of the substrate at two sides of the recess pattern. The semiconductor device is able to secure a required data retention time by suppressing the increase of leakage current caused by the reduction of a design rule.01-07-2010
20120139040INSULATED GATE TYPE SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.06-07-2012
20100140697Trench-Based Power Semiconductor Devices with Increased Breakdown Voltage Characteristics - Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed.06-10-2010
20110057261SEMICONDUCTOR DEVICE HAVING RECESS CHANNEL STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device having a recess channel structure includes a semiconductor substrate having a recess formed in a gate forming area in an active area; an insulation layer formed in the semiconductor substrate so as to define the active area and formed so as to apply a tensile stress in a channel width direction; a stressor formed in a surface of the insulation layer and formed so as to apply a compressive stress in a channel height direction; a gate formed over the recess in the active area; and source/drain areas formed in a surface of the active area at both side of the gate.03-10-2011
20110057260SEMICONDUCTOR DEVICE - A dummy transistor and a field effect transistor are arranged in a second direction. The dummy transistor is located at least at one end in a second direction.03-10-2011
20100127324Trench MOSFET with terrace gate and self-aligned source trench contact - A trench MOSFET with terrace gate is disclosed for self-aligned contact. When refilling the gate trenches, the deposited polysilicon layer is higher than the sidewalls of the trenches to be used as a terrace gate of the MOSFET. The source contact width is determined by mesa width between two adjacent trenches minus 2 times of the oxide thickness deposited on the mesa instead of contact mask width which is wider than silicon contact width. Therefore, the position of source contact is still unchanged even if the misalignment of trench mask happens. At the same time, by using terrace gates, the Rg is thus reduced because the terrace gate provides more polysilicon as gate material than the conventional trench gate.05-27-2010
20130126967SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A vertical super junction MOSFET and a lateral MOSFET are integrated on the same semiconductor substrate. The lateral MOSFET is electrically isolated from the vertical super junction MOSFET by an n-buried isolating layer and an n-diffused isolating layer. The lateral MOSFET is formed of a p-well region formed in an n05-23-2013
20090140333Method for preventing gate oxide damage of a trench MOSFET during wafer processing while adding an ESD protection module atop - A method and device structure are disclosed for preventing gate oxide damage of a trench MOSFET during wafer processing while adding an ESD protection module atop the trench MOSFET. The ESD protection module has a low temperature oxide (LTO) bottom layer whose patterning process is found to cause the gate oxide damage. The method includes:06-04-2009
20090039423SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device with first and second groups of transistors, the second group transistors each having a lower operating voltage than that of each of said transistors in said first group, the first group transistors have first gate electrodes formed from a silicon based material layer on a semiconductor substrate through a first gate insulating film, the second group transistors have second gate electrodes formed such that metal based gate materials are respectively filled in gate formation trenches formed in an interlayer insulating film on the semiconductor substrate through a second gate insulating film, and a resistor on the substrate has a resistor main body utilizing the silicon based material layer and is formed on the substrate through an insulating film.02-12-2009
20090114986FIELD PLATE TRENCH TRANSISTOR AND METHOD FOR PRODUCING IT - A field plate trench transistor having a semiconductor body. In one embodiment the semiconductor has a trench structure and an electrode structure embedded in the trench structure. The electrode structure being electrically insulated from the semiconductor body by an insulation structure and having a gate electrode structure and a field electrode structure. The field plate trench transistor has a voltage divider configured such that the field electrode structure is set to a potential lying between source and drain potentials.05-07-2009
20090114984POWER DEVICE AND A METHOD FOR PRODUCING A POWER DEVICE - A power device with improved reliability and a method for producing the same is disclosed. One embodiment provides an active area having an electrical power dissipation characteristic, a metallization layer portion configured with respect to the active area so that the dissipation characteristic of the active area results in heating the metallization layer portion, the metallization layer portion being formed as a connected region. The metallization layer portion has at least one hole, fully extending through the metal layer and having a dielectric. The at least one hole is arranged so that each location of the metal layer portion is connected electrically to each other location via the metallization material of the metal layer portion.05-07-2009
20080290407SEMICONDUCTOR DEVICE - A semiconductor device has a semiconductor substrate, an insulating film, a semiconductor element and a resistance element. The semiconductor substrate has a first trench. The insulating film covers an inner surface of the first trench. The semiconductor element has an electrode. The resistance element is electrically connected to the electrode to form a resistance to a current flowing through the electrode, and is arranged in the first trench with the insulating film therebetween. Thereby, the semiconductor device can have a resistance element that has a small footprint and can pass a large current with high reliability.11-27-2008
20090050960Stacked Trench Metal-Oxide-Semiconductor Field Effect Transistor Device - Embodiments of the present invention are directed toward a trench metal-oxide-semiconductor field effect transistor (TMOSFET) device. The TMOSFET device includes a source-side-gate TMOSFET coupled to a drain-side-gate TMOSFET 02-26-2009
20100301410SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - A semiconductor device having a semiconductor body, a source metallization arranged on a first surface of the semiconductor body and a trench including a first trench portion and a second trench portion and extending from the first surface into the semiconductor body is provided. The semiconductor body further includes a pn-junction formed between a first semiconductor region and a second semiconductor region. The first trench portion includes an insulated gate electrode which is connected to the source metallization, and the second trench portion includes a conductive plug which is connected to the source metallization and to the second semiconductor region.12-02-2010
20100133610METHOD OF FORMING AN INTEGRATED POWER DEVICE AND STRUCTURE - In one embodiment, a vertical power transistor is formed on a semiconductor substrate with other transistors. A portion of the semiconductor layer underlying the vertical power transistor is doped to provide a low on-resistance for the vertical power transistor.06-03-2010
20110024833SEMICONDUCTOR DEVICE WITH BURIED GATE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a first region and a second region, a buried gate arranged in the first region, and an oxidation prevention barrier surrounding the first region.02-03-2011
20110042742STRUCTURES OF AND METHODS OF FABRICATING TRENCH-GATED MIS DEVICES - In a trench-gated MIS device contact is made to the gate within the trench, thereby eliminating the need to have the gate material, typically polysilicon, extend outside of the trench. This avoids the problem of stress at the upper corners of the trench. Contact between the gate metal and the polysilicon is normally made in a gate metal region that is outside the active region of the device. Various configurations for making the contact between the gate metal and the polysilicon are described, including embodiments wherein the trench is widened in the area of contact. Since the polysilicon is etched back below the top surface of the silicon throughout the device, there is normally no need for a polysilicon mask, thereby saving fabrication costs.02-24-2011
20110018059Shield Contacts in a Shielded Gate MOSFET - A semiconductor structure comprises an active region comprising trenches extending into a semiconductor region. Each trench includes a shield electrode and a gate electrode. The semiconductor structure also comprises a shield contact region adjacent to the active region. The shield contact region comprises at least one contact trench extending into the semiconductor region. The shield electrode from at least one of the trenches in the active region extends along a length of the contact trench. The semiconductor structure also comprises an interconnect layer extending over the active region and the shield contact region. In the active region the interconnect layer is isolated from the gate electrode in each trench by a dielectric layer and contacts mesa surfaces of the semiconductor region adjacent to the trenches. In the shield contact region the interconnect layer contacts the shield electrode and the mesa surfaces of the semiconductor region adjacent to the contact trench.01-27-2011
20110115015TRENCH DEVICES HAVING IMPROVED BREAKDOWN VOLTAGES AND METHOD FOR MANUFACTURING SAME - In one embodiment, the present invention includes a semiconductor power device. The semiconductor power device comprises a trenched gate and a trenched field region. The trenched gate is disposed vertically within a trench in a semiconductor substrate. The trenched field region is disposed vertically within the trench and below the trenched gate. A lower portion of the trenched field region tapers to disperse an electric field.05-19-2011
20100163978METHOD FOR MANUFACTURING AN INTEGRATED POWER DEVICE ON A SEMICONDUCTOR SUBSTRATE AND CORRESPONDING DEVICE - An embodiment of a method for manufacturing a power device being integrated on a semiconductor substrate comprising at least the steps of making, in the semiconductor substrate, at least a trench having sidewalls and a bottom, covering the sidewalls and the bottom of said at least one trench with a first insulating coating layer and making, inside said at least one trench, a conductive gate structure. An embodiment of the method provides the formation of the conductive gate structure comprising the steps of covering at least the sidewalls with a second conductive coating layer of a first conductive material; making a conductive central region of a second conductive material having a different resistivity than the first conductive material; and making a plurality of conductive bridges between said second conductive coating layer and said conductive central region.07-01-2010
20100148249Method Of Manufacturing A Memory Device - A memory device comprises an active area comprising a source and at least two drains defining a first axis. At least two substantially parallel word lines are defined by a first pitch, with one word line located between each drain and the source. Digit lines are defined by a second pitch, one of the digit lines being coupled to the source and forming a second axis. The active areas of the memory array are tilted at 45° to the grid defined by the word lines and digit lines. The word line pitch is about 1.5F, while the digit line pitch is about 3F.06-17-2010
20110133271Trench MOS Device with Schottky Diode and Method for Manufacturing Same - In one embodiment the present invention includes a semiconductor device. The semiconductor device comprises a first semiconductor region, a second semiconductor region and a trench region. The first semiconductor region is of a first conductivity type and a first conductivity concentration. The trench region includes a metal layer in contact with the first semiconductor region to form a metal-semiconductor junction. The second semiconductor region is adjacent to the first semiconductor region that has a second conductivity type and a second conductivity concentration. The second semiconductor region forms a PN junction with the first semiconductor region, and the trench region has a depth such that the metal-semiconductor junction is proximate to the PN junction.06-09-2011
20090242979Vertical Transistor of Semiconductor Device and Method of Forming the Same - A vertical transistor of a semiconductor device has a channel area formed in a vertical direction to a semiconductor substrate. After semiconductor poles corresponding to the length of semiconductor channels and gate electrodes surrounding sidewalls of the semiconductor poles are formed, subsequent processes of forming silicon patterns corresponding to junction areas, etc. are performed. The gate electrodes support the semiconductor poles during these subsequent processes. The height of the semiconductor poles corresponding to the length of the channel is increased, yet the semiconductor poles do not collapse or incline since the gate electrodes support the semiconductor poles.10-01-2009
20100072545Recessed Channel Array Transistors, and Semiconductor Devices Including a Recessed Channel Array Transistor - A recessed channel array transistor may include a substrate, a gate oxide layer, a gate electrode and source/drain regions. The substrate may have an active region and an isolation region. A recess may be formed in the active region. The gate oxide layer may be formed on the recess and the substrate. The gate oxide layer may include a first portion on an intersection between a side end of the recess and a sidewall of the active region and a second portion on a side surface of the recess. The first portion may include a thickness greater than about 70% of a thickness of the second portion. The gate electrode may be formed on the gate oxide layer. The source/drain regions may be formed in the substrate. Thus, the recessed channel array transistor may have a decreased leakage current and an increased on-current.03-25-2010
20100059816TRENCH GATE TYPE TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - The invention provides a trench gate type transistor in which the gate capacitance is reduced, the crystal defect is prevented and the gate breakdown voltage is enhanced. Trenches are formed in an N− type semiconductor layer. A uniformly thick silicon oxide film is formed on the bottom of each of the trenches and near the bottom, being round at corner portions. A silicon oxide film is formed on the upper portion of the sidewall of each of the trenches, which is thinner than the silicon oxide film and round at corner portions. Gate electrodes are formed from inside the trenches onto the outside thereof. The thick silicon oxide film reduces the gate capacitance, and the thin silicon oxide film on the upper portion provides good transistor characteristics. Furthermore, with the round corner portions, the crystal defect does not easily occur, and the gate electric field is dispersed to enhance the gate breakdown voltage.03-11-2010
20100123192SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE - A semiconductor component that includes gate electrodes and shield electrodes and a method of manufacturing the semiconductor component. A semiconductor material has a device region, a gate contact region, a termination region, and a drain contact region. One or more device trenches is formed in the device region and one or more termination trenches is formed in the edge termination region. Shielding electrodes are formed in portions of the device trenches that are adjacent their floors. A gate dielectric material is formed on the sidewalls of the trenches in the device region and gate electrodes are formed over and electrically isolated from the shielding electrodes. The gate electrodes in the trenches in the device region are connected to the gate electrodes in the trenches in the gate contact region. The shielding electrodes in the trenches in the device region are connected to the shielding electrodes in the termination region.05-20-2010
20110248340Trench mosfet with body region having concave-arc shape - A trench Metal Oxide Semiconductor Field Effect Transistor with improved body region structures is disclosed. By forming the inventive body region structures with concave-arc shape with respect to epitaxial layer, a wider interfaced area between the body region and the epitaxial layer is achieved, thus increasing capacitance between drain and source Cds. Moreover, the invention further comprises a Cds enhancement doped region interfaced with said body region having higher doping concentration than the epitaxial layer to further enhancing Cds without significantly impact breakdown voltage.10-13-2011
20120267713POWER SEMICONDUCTOR STRUCTURE WITH SCHOTTKY DIODE AND FABRICATION METHOD THEREOF - A power semiconductor structure with schottky diode is provided. In the step of forming the gate structure, a separated first polysilicon structure is also formed on the silicon substrate. Then, the silicon substrate is implanted with dopants by using the first polysilicon structure as a mask to form a body and a source region. Afterward, a dielectric layer is deposited on the silicon substrate and an open penetrating the dielectric layer and the first polysilicon structure is formed so as to expose the source region and the drain region below the body. The depth of the open is smaller than the greatest depth of the body. Then, a metal layer is filled into the open to electrically connect to the source region and the drain region.10-25-2012
20100078719SEMICONDUCTOR DEVICE - A semiconductor device in which a desired device is formed, comprising a semiconductor substrate having a first impurity region of a first conductivity type provided around an edge of a region in which the desired device is formed, and a second impurity region of the first conductivity type provided in a scribe region of the semiconductor substrate; wherein a channel stopper is formed between the first impurity region and the second impurity region.04-01-2010
20110163375High-Voltage MOS Devices Having Gates Extending into Recesses of Substrates - An integrated circuit structure includes a high-voltage well (HVW) region in a semiconductor substrate; a first double diffusion (DD) region in the HVW region; and a second DD region in the HVW region. The first DD region and the second DD region are spaced apart from each other by an intermediate portion of the HVW region. A recess extends from a top surface of the semiconductor substrate into the intermediate portion of the HVW region and the second DD region. A gate dielectric extends into the recess and covers a bottom of the recess. A gate electrode is over the gate dielectric. A first source/drain region is in the first DD region. A second source/drain region is in the second DD region.07-07-2011
20090294846TRENCH-TYPE POWER MOS TRANSISTOR AND INTEGRATED CIRCUIT UTILIZING THE SAME - A power MOS transistor comprises a drain region, a trench gate, a source region, a well region, a deep well region and a substrate region. The drain region has a doping region of a first conductivity type connected to a drain electrode. The trench gate has an insulating layer and extends into the drain region. The source region has a doping region of the first conductivity type connected to a source electrode. The well region is doped with a second conductivity type, formed under the source region, and connected to the source electrode. The deep well region is doped with the first conductivity type and is formed under the drain region and the well region. The substrate region is doped with the second conductivity type and is formed under the deep well region. The drain region is formed at one side of the trench gate and the source region is formed at the opposing side of the trench gate such that the trench gate laterally connects the source region and the drain region.12-03-2009
20080315303METHOD OF FORMING A SEMICONDUCTOR STRUCTURE COMPRISING INSULATING LAYERS WITH DIFFERENT THICKNESSES - The method of forming a semiconductor structure in a substrate comprises, forming a first trench with a first width W12-25-2008
20100308403TRANSISTOR HAVING VERTICAL CHANNEL - A semiconductor device including vertical channel transistor and a method for forming the transistor, which can significantly decrease the resistance of a word line is provided. A vertical channel transistor includes a substrate including pillars each of which has a lower portion corresponding to a channel region. A gate insulation layer is formed over the substrate including the pillars. A metal layer having a low resistance is used for forming a surrounding gate electrode to decrease resistance of a word line. A barrier metal layer is formed between a gate insulation layer and a surrounding gate electrode so that deterioration of characteristics of the insulation layer is prevented. A world line is formed connecting gate electrodes formed over the barrier layer to surround the lower portion of each pillar.12-09-2010
20110084335SEMICONDUCTOR DEVICE WITH DRAIN VOLTAGE PROTECTION AND MANUFACTURING METHOD THEREOF - A power semiconductor device with drain voltage protection includes a semiconductor substrate, at least a trench gate transistor device and at least a trench ESD protection device. An upper surface of the semiconductor substrate has a first trench and a second trench. The trench gate transistor device is disposed in the first trench and the semiconductor substrate. The trench ESD protection device is disposed in the second trench, and includes a first doped region, a second doped region and a third doped region. The first doped region and the third doped region are respectively electrically connected to a drain and a gate of the trench gate transistor device.04-14-2011
20110095362FIELD PLATE TRENCH TRANSISTOR AND METHOD FOR PRODUCING IT - A field plate trench transistor having a semiconductor body. In one embodiment the semiconductor has a trench structure and an electrode structure embedded in the trench structure. The electrode structure being electrically insulated from the semiconductor body by an insulation structure and having a gate electrode structure and a field electrode structure. The field plate trench transistor has a voltage divider configured such that the field electrode structure is set to a potential lying between source and drain potentials.04-28-2011
20110095361MULTIPLE LAYER BARRIER METAL FOR DEVICE COMPONENT FORMED IN CONTACT TRENCH - A semiconductor device formed on a semiconductor substrate may include a component formed in a contact trench located in an active cell region. The component may comprise a barrier metal deposited on a bottom and portions of sidewalls of the contact trench and a tungsten plug deposited in a remaining portion of the contact trench. The barrier metal may comprise first and second metal layers. The first metal layer may be proximate to the sidewall and the bottom of the contact trench. The first metal layer may include a nitride. The second metal layer may be between the first metal layer and the tungsten plug and between the tungsten plug and the sidewall. The second metal layer covers portions of the sidewalls of not covered by the first metal layer.04-28-2011
20110095360METHOD AND DEVICE INCLUDING TRANSISTOR COMPONENT HAVING A FIELD ELECTRODE - A transistor component and method of forming a transistor component. One embodiment provides a semiconductor arrangement including a semiconductor body having a at least one first trench, a first field electrode arranged in the lower trench section of the at least one first trench and being insulated from the semiconductor body by a field electrode dielectric. A dielectric layer is formed on the first field electrode in the at least one first trench, including depositing a dielectric material on a first side of the semiconductor body and on the field plate at a higher deposition rate than on sidewalls of the at least one first trench.04-28-2011
20110260244RECESSED CHANNEL ARRAY TRANSISTOR (RCAT) IN REPLACEMENT METAL GATE (RMG) LOGIC FLOW - Embodiments of the invention relate to a method of fabricating logic transistors using replacement metal gate (RMG) logic flow with modified process to form recessed channel array transistors (RCAT) on a common semiconductor substrate. An embodiment comprises forming an interlayer dielectric (ILD) layer on a semiconductor substrate, forming a first recess in the ILD layer of a first substrate region, forming a recessed channel in the ILD layer and in the substrate of a second substrate region, depositing a first conformal high-k dielectric layer in the first recess and a second conformal high-k dielectric layer in the recessed channel, and filling the first recess with a first gate metal and the recessed channel with a second gate metal.10-27-2011
20080217684Semiconductor device and manufacturing method thereof and power supply apparatus using the same - A semiconductor device comprises a trench-gate type field-effect transistor on a semiconductor substrate having a first main surface and a second main surface oppositely positioned in a thickness direction, wherein the trench-gate type field-effect transistor comprises a first semiconductor region at the first main surface side; a second semiconductor region at the second main surface; a semiconductor well region between the first semiconductor region and the second semiconductor region; a trench formed so as to protrude in a first direction intersecting the second main surface; a gate electrode formed on an inner surface of the trench via a gate insulating film, and a bottom of the gate electrode is in the first semiconductor region, and a well bottom has a well deep portion and a well shallow portion, and the well deep portion is in a region more distant from the gate insulating film compared to the well shallow portion.09-11-2008
20100025760SEMICONDUCTOR DEVICE - A semiconductor device includes a MOSFET cell having a super junction structure and a diode cell connected in parallel with the MOSFET cell and having the same plan shape as the MOSFET cell. The MOSFET cell includes an epitaxial layer of a first conductivity type formed on a semiconductor substrate, a gate electrode and a first column region of a second conductivity type formed in the epitaxial layer, a first base region of the second conductivity type formed on a surface of the epitaxial layer, and a source region of the first conductivity type formed on a surface of the first base region. The diode cell includes a second column region of the second conductivity type formed in the epitaxial layer and having a larger width than the first column region, and a second base region of the second conductivity type formed on the surface of the epitaxial layer.02-04-2010
20110215400SEMICONDUCTOR DEVICE - To improve the performance and reliability of semiconductor devices. For the semiconductor chip CP09-08-2011
20100090276Shielded gate trench (SGT) MOSFET devices and manufacturing processes - This invention discloses a semiconductor power device that includes a plurality of power transistor cells surrounded by a trench opened in a semiconductor substrate. At least one of the cells constituting an active cell has a source region disposed next to a trenched gate electrically connecting to a gate pad and surrounding the cell. The trenched gate further has a bottom-shielding electrode filled with a gate material disposed below and insulated from the trenched gate. At least one of the cells constituting a source-contacting cell surrounded by the trench with a portion functioning as a source connecting trench is filled with the gate material for electrically connecting between the bottom-shielding electrode and a source metal disposed directly on top of the source connecting trench. The semiconductor power device further includes an insulation protective layer disposed on top of the semiconductor power device having a plurality of source openings on top of the source region and the source connecting trench provided for electrically connecting to the source metal and at least a gate opening provided for electrically connecting the gate pad to the trenched gate.04-15-2010
20120306009INTEGRATION OF SUPERJUNCTION MOSFET AND DIODE - A semiconductor structure comprises a semiconductor layer of a first conductivity type, trenches extending into the semiconductor layer, and a conductive layer of a second conductivity type lining sidewalls and bottom of each trench and forming PN junctions with the semiconductor layer. A first plurality of the trenches are disposed in a field effect transistor region that comprises a body region of the first conductivity type, source regions of the second conductivity type in the body region, and gate electrodes isolated from the body region and the source regions by a gate dielectric. A second plurality of the trenches are disposed in a Schottky region that comprises a conductive material contacting mesa surfaces of the semiconductor layer between adjacent ones of the second plurality of the trenches to form Schottky contacts. The conductive material also contacts the conductive layer proximate an upper portion of the second plurality of the trenches.12-06-2012
20110079845Planar TMBS rectifier - A monolithically integrated trench FET and Schottky diode includes a plurality of trenches extending into a FET region and a Schottky region of a semiconductor layer. A trench in the Schottky region includes a dielectric layer lining the trench sidewalls, and a conductive electrode having a top surface that is substantially coplanar with a top surface of the semiconductor layer adjacent the trench. An interconnect layer electrically contacts the semiconductor layer in the Schottky region so as to form a Schottky contact with the semiconductor layer.04-07-2011
20120146138POWER DEVICE WITH LOW PARASITIC TRANSISTOR AND METHOD OF MAKING THE SAME - The power device with low parasitic transistor comprises a recessed transistor and a heavily doped region at a side of a source region of the recessed transistor. The conductive type of the heavily doped region is different from that of the source region. In addition, a contact plug contacts the heavily doped region and connects the heavily doped region electrically. A source wire covers and contacts the source region and the contact plug to make the source region and the heavily doped region have the same electrical potential.06-14-2012
20120037983Trench mosfet with integrated schottky rectifier in same cell - A semiconductor power device comprising a plurality of trench MOSFETs integrated with Schottky rectifier in same cell is disclosed. The invented semiconductor power device comprises a tilt-angle implanted drift region having higher doping concentration than epitaxial layer to reduce Vf in Schottky rectifier portion and to reduce Rds in trench MOSFET portion while maintaining a higher breakdown voltage by implementation of thick gate oxide in trench bottom of trenched gates. Furthermore, the invented semiconductor power device further comprises a Schottky barrier height enhancement region to enhance the barrier layer covered in trench bottom of trenched source-body-Schottky contact in Schottky rectifier portion.02-16-2012
20100295123Phase Change Memory Cell Having Vertical Channel Access Transistor - Memory devices are described along with methods for manufacturing. A device as described herein includes a substrate having a first region and a second region. The first region comprises a first field effect transistor comprising first and second doped regions separated by a horizontal channel region within the substrate, a gate overlying the horizontal channel region, and a first dielectric covering the gate of the first field effect transistor. The second region of the substrate includes a second field effect transistor comprising a first terminal extending through the first dielectric to contact the substrate, a second terminal overlying the first terminal and having a top surface, and a vertical channel region separating the first and second terminals. The second field effect transistor also includes a gate on the first dielectric and adjacent the vertical channel region, the gate having a top surface that is co-planar with the top surface of the second terminal. A second dielectric separates the gate of the second field effect transistor from the vertical channel region.11-25-2010
20120153385SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device that secures a contact margin between a storage node contact plug and an active region and a method for fabricating the same. A method for fabricating a semiconductor device includes forming a device isolation layer defining active regions extending in a first direction a substrate, forming a first trench extending across the active regions and the device isolation layer by selectively etching the substrate, forming a second trench under the first trench to isolate the active regions which are adjacent in the first direction by selectively etching the substrate, and forming a gate electrode filling the first and second trenches.06-21-2012
20110316077POWER SEMICONDUCTOR STRUCTURE WITH SCHOTTKY DIODE AND FABRICATION METHOD THEREOF - A power semiconductor structure with schottky diode is provided. In the step of forming the gate structure, a separated first polysilicon structure is also formed on the silicon substrate. Then, the silicon substrate is implanted with dopants by using the first polysilicon structure as a mask to form a body and a source region. Afterward, a dielectric layer is deposited on the silicon substrate and an open penetrating the dielectric layer and the first polysilicon structure is formed so as to expose the source region and the drain region below the body. The depth of the open is smaller than the greatest depth of the body. Then, a metal layer is filled into the open to electrically connect to the source region and the drain region.12-29-2011
20120043606SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor device includes a first semiconductor region, a second semiconductor region, a third semiconductor region, a fourth semiconductor region, a gate region, a gate insulating film, and an electric field relaxation region. The first semiconductor region includes a first portion and a second portion. The second semiconductor region includes a third portion and a fourth portion. The third semiconductor region includes a fifth portion and a sixth portion. The fourth semiconductor region is adjacent to the sixth portion. The gate region is provided inside a trench made in a second direction orthogonal to the first direction. The gate insulating film is provided between the gate region and an inner wall of the trench. The electric field relaxation region is provided between the third portion and the fifth portion and has an impurity concentration lower than an impurity concentration of the third semiconductor region.02-23-2012
20110156140METHOD FOR MANUFACTURING A POWER DEVICE BEING INTEGRATED ON A SEMICONDUCTOR SUBSTRATE, IN PARTICULAR HAVING A FIELD PLATE VERTICAL STRUCTURE AND CORRESPONDING DEVICE - An embodiment of a method for manufacturing a power device integrated on a semiconductor substrate comprising the steps of: growth on said substrate of an epitaxial layer; photo-lithography and etching of said epitaxial layer for the formation of at least one deep trench; deposition of a dielectric layer with partial filling of the at least one trench; complete filling of the at least one trench with a layer of sacrificial material; selective etching of the dielectric layer with consequent retrocession below the layer of sacrificial material; selective etching of the layer of sacrificial material with consequent formation of an empty region within the at least one trench; growth of a layer of gate oxide; formation of at least one gate region, of at least one buried source region, of at least one body region and of at least one source region; deposition of a dielectric layer; simultaneous formation of at least one gate contact, at least one body/source contact and at least one buried source contact; formation of a source contact region and of a gate contact region through deposition, masking and etching of a metallisation layer. An embodiment of the method also comprises the step of formation of the at least one gate region and of the at least one buried source region, electrically insulated, through a single deposition of a conductive filling material on the epitaxial layer, on the vertical walls of the trench and within the empty region; and through etching of the conductive filling material forming a first spacer and a second spacer, suitable for serving as a gate electrode and forming a buried source electrode within the empty region.06-30-2011
20120007178SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device having trench gates in element regions R01-12-2012
20120007176High-Voltage Bipolar Transistor with Trench Field Plate - A bipolar transistor structure includes an epitaxial layer on a semiconductor substrate, a bipolar transistor device formed in the epitaxial layer and a trench structure formed in the epitaxial layer adjacent at least two opposing lateral sides of the bipolar transistor device. The trench structure includes a field plate spaced apart from the epitaxial layer by an insulating material. The bipolar transistor structure further includes a base contact connected to a base of the bipolar transistor device, an emitter contact connected to an emitter of the bipolar transistor device and isolated from the base contact and an electrical connection between the emitter contact and the field plate.01-12-2012
20120007177SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate including a cell area and a peripheral circuit area, a first trench for device isolation formed in the cell area of the semiconductor substrate and a second trench for device isolation formed within the semiconductor substrate of the peripheral circuit area to be deeper than the first trench, a device isolation layer buried within the first and second trenches for device isolation and having the same surface level as the semiconductor substrate in the cell area, a buried gate buried in the semiconductor substrate of the cell area, and a peripheral circuit gate which is in contact with the semiconductor substrate of the peripheral circuit area, is buried within the device isolation layer of the peripheral circuit area, and has the same surface level as the buried gate. It can prevent the same effect from affecting the cell area and the peripheral circuit area so that the number of masks is reduced and the process is simplified so that cost can be reduced and characteristics of the semiconductor device can be improved.01-12-2012
20100065908ALIGNMENT OF TRENCH FOR MOS - Manufacturing a power transistor by forming a gate structure on a first layer, forming a trench in the first layer, self aligned with the gate structure, and forming part of the transistor in the trench. By forming a spacer next to the gate, the spacer and gate can be used as a mask when forming the trench, to allow space for a source region next to the gate. The self-aligning rather than forming the gate after the trench means the alignment is more accurate, allowing size reduction. Another aspect involves forming a trench in a first layer, filling the trench, forming a second layer on either side of the trench with lateral overgrowth over the trench, and forming a source region in the second layer to overlap the trench. This overlap can enable the chip area to be reduced.03-18-2010
20090278199Method for Preventing Gate Oxide Damage of a Trench MOSFET during Wafer Processing while Adding an ESD Protection Module Atop - A method and device structure are disclosed for preventing gate oxide damage of a trench MOSFET during wafer processing while adding an ESD protection module atop the trench MOSFET. The ESD protection module has a low temperature oxide (LTO) bottom layer whose patterning process is found to cause the gate oxide damage. The method includes: 11-12-2009
20120061755Checkerboarded high-voltage vertical transistor layout - In one embodiment, a transistor fabricated on a semiconductor die includes a first section of transistor segments disposed in a first area of the semiconductor die, and a second section of transistor segments disposed in a second area of the semiconductor die adjacent the first area. Each of the transistor segments in the first and second sections includes a pillar of a semiconductor material that extends in a vertical direction. First and second dielectric regions are disposed on opposite sides of the pillar. First and second field plates are respectively disposed in the first and second dielectric regions. Outer field plates of transistor segments adjoining first and second sections are either separated or partially merged.03-15-2012
20120153386SEMICONDUCTOR COMPONENT WITH A SPACE SAVING EDGE STRUCTURE - A semiconductor component is disclosed. One embodiment includes a semiconductor body including a first semiconductor layer having at least one active component zone, a cell array with a plurality of trenches, and at least one cell array edge zone. The cell array edge zone is only arranged in an edge region of the cell array, adjoining at least one trench of the cell array, and being at least partially arranged below the at least one trench in the cell array.06-21-2012
20110073941Semiconductor Devices Including Elevated Source and Drain Regions - Methods of fabricating semiconductor devices are provided. A substrate having active patterns and isolating layer patterns is prepared. Each of the isolating layer patterns has an upper surface higher than that of each of the active patterns. A spacer layer having a uniform thickness is formed on the substrate. The spacer layer is etched to form a spacer on a sidewall of each of the isolating layer patterns. A gate structure is formed on each of the active patterns. A selective epitaxial growth (SEG) process is performed on the active patterns having the gate structure to form isolated epitaxial layers that have upper surfaces higher than those of the isolating layer patterns, on the active patterns. Related semiconductor devices are also provided.03-31-2011
20110079844Trench mosfet with high cell density - A trench MOSFET with high cell density is disclosed where there is a heavily doped contact region on the top surface of mesas between a pair of gate trenches. The present invention can prevent the degradation of avalanche capability when shrinking the device in prior art.04-07-2011
20090134457Segmented pillar layout for a high-voltage vertical transistor - In one embodiment, a transistor fabricated on a semiconductor die includes a first section of transistor segments disposed in a first area of the semiconductor die, and a second section of transistor segments disposed in a second area of the semiconductor die adjacent the first area. Each of the transistor segments in the first and second sections includes a pillar of a semiconductor material that extends in a vertical direction. First and second dielectric regions are disposed on opposite sides of the pillar. First and second field plates are respectively disposed in the first and second dielectric regions. Outer field plates of transistor segments adjoining first and second sections are either separated or partially merged. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.05-28-2009
20110089489Semiconductor device including capacitor element and method of manufacturing the same - A semiconductor device includes a memory region, and a logic region formed on a substrate, in which a trench recess is provided in the substrate in the memory region. A first transistor is provided in the memory region and a second transistor is provided in the logic region. The first transistor includes a first gate electrode. The first gate electrode is provided to be buried in the recess and to protrude to outside of the recess. The second transistor includes a second gate electrode having a same material as that of the first gate electrode.04-21-2011
20120211831TRENCH MOSFET WITH TRENCHED FLOATING GATES IN TERMINATION - A trench MOSFET comprising multiple trenched floating gates in termination area is disclosed. The trenched floating gates have trench depth equal to or deeper than body junction of body regions in active area. The trench MOSFET further comprise an EPR surrounding outside the multiple trenched floating gates in the termination area.08-23-2012
20120211830SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device and a method of fabricating the same are provided, in which a full overlap between a storage node contact and an active region to solve an overlay in an etching process and an etching width of a storage node is increased to improve a processing margin. The semiconductor device includes a main gate and a device isolation structure disposed in a semiconductor device, an isolation pattern disposed over the device isolation structure, and contact plugs disposed at each side of the isolation pattern.08-23-2012
20100289077DUAL GATE OF SEMICONDUCTOR DEVICE CAPABLE OF FORMING A LAYER DOPED IN HIGH CONCENTRATION OVER A RECESSED PORTION OF SUBSTRATE FOR FORMING DUAL GATE WITH RECESS CHANNEL STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A dual gate of a semiconductor device includes a semiconductor substrate divided into a cell region with a recessed gate forming area and a peripheral region with PMOS and NMOS forming areas; first and second conductive type SiGe layers, the first conductive type SiGe layer being formed over the cell region and the PMOS forming area of the peripheral region, and the second conductive type SiGe layer being formed over the NMOS forming area of the peripheral region; first and second conductive type polysilicon layers, the first conductive type polysilicon layer being formed over the first conductive type SiGe layer and the second conductive type polysilicon layer being formed over the second conductive type SiGe layer; and a metallic layer and a hard mask layer stacked over the first and second conductive type polysilicon layers.11-18-2010
20100289076SEMICONDUCTOR DEVICE - A technique is presented for further reducing on-resistance (or on-voltage) in a vertical semiconductor device provided with a carrier shielding layer.11-18-2010
20100289075SEMICONDUCTOR DEVICE HAVING INTEGRATED MOSFET AND SCHOTTKY DIODE AND MANUFACTURING METHOD THEREOF - A semiconductor device having integrated MOSFET and Schottky diode includes a substrate having a MOSFET region and a Schottky diode region defined thereon; a plurality of first trenches formed in the MOSFET region; and a plurality of second trenches formed in the Schottky diode region. The first trenches respectively including a first insulating layer formed over the sidewalls and bottom of the first trench and a first conductive layer filling the first trench serve as a trenched gate of the trench MOSFET. The second trenches respectively include a second insulating layer formed over the sidewalls and bottom of the second trench and a second conductive layer filling the second trench. A depth and a width of the second trenches are larger than that of the first trenches; and a thickness of the second insulating layer is larger than that of the first insulating layer.11-18-2010
20120126318Integrated Circuit Including Field Effect Transistor - An integrated circuit includes a semiconductor carrier including a first side and a second side opposite the first side. An FET is in a first area of the semiconductor carrier, and has a drain electrically coupled to a drain contact area at the first side and a source electrically coupled to a source contact area at the second side. First circuit elements are in a second area of the semiconductor carrier. The second area is electrically insulated from the semiconductor carrier surrounding the second area via a trench insulation extending through the semiconductor carrier from the first side to the second side. An interconnection level electrically interconnects the first circuit elements at the second side, and is electrically insulated from the source contact area in the entire second area via an insulating layer at the second side. A conductive pathway extends through the semiconductor carrier from the first side to the second side, and is electrically insulated from the semiconductor carrier surrounding the conductive pathway. At least one of the first circuit elements is electrically coupled to a contact area at the first side via the conductive pathway.05-24-2012
20100207205Structures and Methods for Improving Trench-Shielded Semiconductor Devices and Schottky Barrier Rectifier Devices - Various structures and methods for improving the performance of trench-shielded power semiconductor devices and the like are described.08-19-2010
20110180869SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCTION THEREOF - A semiconductor device contains a first transistor including a single trench which is formed on a substrate between a source region and a drain region and a gate electrode which is formed in the single trench, a second transistor including at least two trenches which are formed on the substrate between a source region and a drain region and a gate electrode which is formed in the at least two trenches, and also contains a device isolation insulating which isolates the region in which the transistor is formed. The first transistor has first distance between the single trench and the device isolation insulating film and the second transistor has second distance between the adjoining trenches, such the first distance is less than the second distance in a gate width direction.07-28-2011
20120132988OXIDE TERMINATED TRENCH MOSFET WITH THREE OR FOUR MASKS - An oxide termination semiconductor device may comprise a plurality of gate trenches, a gate runner, and an insulator termination trench. The gate trenches are located in an active region. Each gate trench includes a conductive gate electrode. The insulator termination trench is located in a termination region that surrounds the active region. The insulator termination trench is filled with an insulator material to form an insulator termination for the semiconductor device. The device can be made using a three-mask or four-mask process.05-31-2012
20100176448Intergrated trench mosfet with trench schottky rectifier - An integrated circuit comprising trench MOSFET having trenched source-body contacts and trench Schottky rectifier having trenched anode contacts is disclosed. By employing the trenched contacts in trench MOSFET and trench Schottky rectifier, the integrated circuit is able to be shrunk to achieve low specific on-resistance for trench MOSFET, and low V07-15-2010
20120248531INSULATED GATE SEMICONDUCTOR DEVICE - A gate lead wiring and an electrical conductor connecting the gate lead wiring to a protective diode are arranged in a straight line without bending along one and the same side of the chip. A first gate electrode layer extending on the gate lead wiring and the electrical conductor, which connects them to the protective diode, has one bent portion or no bent portion. Further, the protective diode is arranged adjacent to the electrical conductor or the gate lead wiring, and a portion of the protective diode is arranged in close proximity to a gate pad portion.10-04-2012
20100052051Integrated Circuit with a Laterally Diffused Metal Oxide Semiconductor Device and Method of Forming the Same - An integrated circuit with a transistor advantageously embodied in a laterally diffused metal oxide semiconductor device having a gate located over a channel region recessed into a semiconductor substrate and a method of forming the same. In one embodiment, the transistor includes a source/drain including a lightly or heavily doped region adjacent the channel region, and an oppositely doped well extending under the channel region and a portion of the lightly or heavily doped region of the source/drain. The transistor also includes a channel extension, within the oppositely doped well, under the channel region and extending under a portion of the lightly or heavily doped region of the source/drain.03-04-2010
20100052050Integrated Circuit with a Laterally Diffused Metal Oxide Semiconductor Device and Method of Forming the Same - An integrated circuit with a transistor advantageously embodied in a laterally diffused metal oxide semiconductor device having a gate located over a channel region recessed into a semiconductor substrate and a method of forming the same. In one embodiment, the transistor includes a source/drain including a lightly or heavily doped region adjacent the channel region, and an oppositely doped well extending under the channel region and a portion of the lightly or heavily doped region of the source/drain. The transistor also includes a channel extension, within the oppositely doped well, under the channel region and extending under a portion of the lightly or heavily doped region of the source/drain.03-04-2010
20100052049Integrated Circuit with a Laterally Diffused Metal Oxide Semiconductor Device and Method of Forming the Same - An integrated circuit with a transistor advantageously embodied in a laterally diffused metal oxide semiconductor device having a gate located over a channel region recessed into a semiconductor substrate and a method of forming the same. In one embodiment, the transistor includes a source/drain including a lightly or heavily doped region adjacent the channel region, and an oppositely doped well extending under the channel region and a portion of the lightly or heavily doped region of the source/drain. The transistor also includes a channel extension, within the oppositely doped well, under the channel region and extending under a portion of the lightly or heavily doped region of the source/drain.03-04-2010
20120175702METAL-OXIDE-SEMICONDUCTOR DEVICE HAVING TRENCHED DIFFUSION REGION AND METHOD OF FORMING SAME - An MOS device includes a semiconductor layer of a first conductivity type and first and second source/drain regions of a second conductivity type formed in the semiconductor layer proximate an upper surface of the semiconductor layer. The first and second source/drain regions are spaced apart relative to one another. A gate is formed above and electrically isolated from the semiconductor layer, at least partially between the first and second source/drain regions. At least a given one of the first and second source/drain regions is configured having an effective width that is substantially greater than a width of a junction between the semiconductor layer and the given source/drain region.07-12-2012
20120175700TRENCH MOS RECTIFIER - A semiconductor device comprising trench MOSFET as MOS rectifier is disclosed. For ESD capability enhancement and reverse recovery charge reduction, a built-in resistor in the semiconductor device is introduced according to the present invention between gate and source. The built-in resistor is formed by a doped poly-silicon layer filled into multiple trenches.07-12-2012
20120074491POWER SEMICONDUCTOR DEVICE - In general, according to one embodiment, a power semiconductor device includes a first pillar region, a second pillar region, and an epitaxial layer of a first conductivity type on a first semiconductor layer. The first pillar region is composed of a plurality of first pillar layers of a second conductivity type and a plurality of second pillar layers of the first conductivity type alternately arranged along a first direction. The second pillar region is adjacent to the first pillar region along the first direction and includes a third pillar layer of the second conductivity type, a fourth pillar layer of the first conductivity type, and a fifth pillar layer of the second conductivity type in this order along the first direction. A plurality of second base layers of the second conductivity type electrically connected, respectively, onto the third pillar layer and the fifth pillar layer and spaced from each other.03-29-2012
20120256259SINGLE-SIDED ACCESS DEVICE AND FABRICATION METHOD THEREOF - The present invention provides a single-sided access device including an active fin structure comprising a source region and a drain region; an insulating layer interposed between the source region and the drain region; a trench isolation structure disposed at one side of the active fin structure; a single-sided sidewall gate electrode disposed on the other side of the active fin structure opposite to the trench isolation structure so that the active fin structure is sandwiched by trench isolation structure and the single-sided sidewall gate electrode; and a gate protrusion laterally and electrically extended from the single-sided sidewall gate electrode and embedded between the source region and the drain region under the insulating layer.10-11-2012
20080303087Semiconductor device with integrated trench lateral power MOSFETs and planar devices - Gate electrodes of a TLPM and gate electrodes of planar devices are formed by patterning a same polysilicon layer. Drain electrode(s) and source electrode(s) of the TLPM and drain electrodes and source electrodes of the planar devices are formed by patterning a same metal layer. Therefore, the TLPM and the planar devices can be connected electrically to each other by resulting metal wiring layers and polysilicon layers without the need for performing wire bonding on a printed circuit board.12-11-2008
20110121387INTEGRATED GUARDED SCHOTTKY DIODE COMPATIBLE WITH TRENCH-GATE DMOS, STRUCTURE AND METHOD - A plurality of transistor cells, each of which can include a transistor P-body region and a Schottky diode, wherein the transistor P-body region can be formed below the Schottky diode to provide a semiconductor device having desirable electrical characteristics.05-26-2011
20110121388SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a device isolation structure, a recess channel structure, a first lower gate conductive layer conformal to the recess channel structure and defining a recess, a holding layer over the first lower gate conductive layer to fill the recess defined by the first lower gate conductive layer, and a second lower gate conductive layer over the first lower gate conductive layer and the holding layer. The holding layer is configured to hold a shift of the seam occurring in the recess channel structure.05-26-2011
20110121386Trench MOSFET with trenched floating gates as termination - A trench MOSFET comprising a plurality of transistor cells with a plurality of wide trenched floating gates as termination region is disclosed. The trenched floating gates have trench depth equal to or deeper than body junction depth of body regions in termination area. Each body region between two adjacent said trenched floating gates has floating voltage.05-26-2011
20120299091TRENCHED POWER SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A trenched power semiconductor device on a lightly doped substrate is provided. Firstly, a plurality of trenches including at least a gate trench and a contact window are formed on the lightly doped substrate. Then, at least two trench-bottom heavily doped regions are formed at the bottoms of the trenches. These trench-bottom heavily doped regions are then expanded to connect with each other by using thermal diffusion process so as to form a conductive path. Afterward, the gate structure and the well are formed above the trench-bottom heavily doped regions, and then a conductive structure is formed in the contact window to electrically connect the trench-bottom heavily doped regions to an electrode.11-29-2012
20120319199Trench Gated Power Device With Multiple Trench Width and its Fabrication Process - Power devices, and related process, where both gate and field plate trenches have multiple stepped widths, using self-aligned process steps.12-20-2012
20110227151TRENCH DMOS DEVICE WITH IMPROVED TERMINATION STRUCTURE FOR HIGH VOLTAGE APPLICATIONS - A termination structure is provided for a power transistor. The termination structure includes a semiconductor substrate having an active region and a termination region. The substrate has a first type of conductivity. A termination trench is located in the termination region and extends from a boundary of the active region toward an edge of the semiconductor substrate. A doped region having a second type of conductivity is disposed in the substrate below the termination trench. A MOS gate is formed on a sidewall adjacent the boundary. The doped region extends from below a portion of the MOS gate spaced apart from the boundary toward the edge of the semiconductor substrate. A termination structure oxide layer is formed on the termination trench covering a portion of the MOS gate and extends toward the edge of the substrate. A first conductive layer is formed on a backside surface of the semiconductor substrate and a second conductive layer is formed atop the active region, an exposed portion of the MOS gate, and extends to cover a portion of the termination structure oxide layer.09-22-2011
20120080751MOS DEVICE WITH VARYING CONTACT TRENCH LENGTHS - A semiconductor device is formed on a semiconductor substrate. The device comprises a drain; an epitaxial layer overlaying the drain; a body disposed in the epitaxial layer, having a body top surface and a body bottom surface; a source embedded in the body, extending from the body top surface into the body; a first gate trench extending into the epitaxial layer; a first gate disposed in the first gate trench; an active region contact trench extending through the source and at least part of the body into the drain; an active region contact electrode disposed within the active region contact trench; a second gate trench extending into the epitaxial layer; a second gate disposed in the gate trench; a gate contact trench formed within the second gate; and a gate contact electrode disposed within the gate contact trench.04-05-2012
20120080750SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes: a semiconductor substrate comprising a word line decoder region and a memory cell region; a basic word line formed in the memory cell region in a buried gate type; and an additional word line formed to extend from the word line decoder region across the memory cell region, wherein the additional word line is formed over the basic word line in parallel to the basic word line and is coupled to the basic word line through two or more vias.04-05-2012
20120080749UMOS SEMICONDUCTOR DEVICES FORMED BY LOW TEMPERATURE PROCESSING - UMOS (U-shaped trench MOSFET) semiconductor devices that have been formed using low temperature processes are described. The source region of the UMOS structure can be formed before the etch processes that are used to create the trench, allowing low-temperature materials to be incorporated into the semiconductor device from the creation of the gate oxide layer oxidation forward. Thus, the source drive-in and activation processing that are typically performed after the trench etch can be eliminated. The resulting UMOS structures contain a trench structure with both a gate insulting layer comprising a low temperature dielectric material and a gate conductor comprising a low temperature conductive material. Forming the source region before the trench etch can reduce the problems resulting from high temperature processes, and can reduce auto doping, improve threshold voltage control, reduce void creation, and enable incorporation of materials such as silicides that cannot survive high temperature processing. Other embodiments are described.04-05-2012
20110278668Semiconductor Devices Having Bit Line Interconnections with Increased Width and Reduced Distance from Corresponding Bit Line Contacts and Methods of Fabricating Such Devices - A semiconductor device has a bit line interconnection with a greater width and a reduced level on a bit line contact is provided, as are methods of fabricating such devices. These method includes forming a buried gate electrode to intersect an active region of a substrate. Source and drain regions are formed in the active region. A first conductive pattern is formed on the substrate. The first conductive pattern has a first conductive layer hole configured to expose the drain region. A second conductive pattern is formed in the first conductive layer hole to contact the drain region. A top surface of the second conductive pattern is at a lower level than a top surface of the first conductive pattern. A third conductive layer and a bit line capping layer are formed on the first conductive pattern and the second conductive pattern and patterned to form a third conductive pattern and a bit line capping pattern. The second conductive pattern, the third conductive pattern, and the bit line capping pattern, which are sequentially stacked on the drain region, constitute first bit line structures, and the first conductive pattern, the third conductive pattern, and the bit line capping pattern, which are sequentially stacked on the isolation region, constitute second bit line structures.11-17-2011
20130015521CROSS-HAIR CELL DEVICES AND METHODS FOR MANUFACTURING THE SAME - Systems and methods are disclosed for manufacturing grounded gate cross-hair cells and standard cross-hair cells of fin field-effect transistors (finFETs). In one embodiment, a process may include forming gate trenches and gates on and parallel to row trenches in a substrate, wherein the gate trenches and gates are pitch-doubled such that four gate trenches are formed for every two row trenches. In another embodiment, a process may include forming gate trenches, gates, and grounded gates in a substrate, wherein the gate trenches and gates are formed such that three gate trenches are formed for every two row trenches.01-17-2013
20130020635Semiconductor device with field threshold MOSFET for high voltage termination - This invention discloses a semiconductor power device disposed in a semiconductor substrate comprising a lightly doped layer formed on a heavily doped layer and having an active cell area and an edge termination area. The edge termination area comprises a plurality P-channel MOSFETs. By connecting the gate to the drain electrode, the P-channel MOSFET transistors formed on the edge termination are sequentially turned on when the applied voltage is equal to or greater than the threshold voltage Vt of the P-channel MOSFET transistors, thereby optimizing the voltage blocked by each region.01-24-2013
20130168765TRENCH DMOS DEVICE WITH IMPROVED TERMINATION STRUCTURE FOR HIGH VOLTAGE APPLICATIONS - A termination structure is provided for a semiconductor device. The termination structure includes a semiconductor substrate having an active region and a termination region. A termination trench is located in the termination region and extends from a boundary of the active region toward an edge of the semiconductor substrate. A MOS gate is formed on a sidewall of the termination trench adjacent the boundary. At least one guard ring trench is formed in the termination region on a side of the termination trench remote from the active region. A termination structure oxide layer is formed on the termination trench and the guard ring trench. A first conductive layer is formed on a backside surface of the semiconductor substrate. A second conductive layer is formed atop the active region and the termination region.07-04-2013
20080224209Semiconductor device and method for fabricating the same - A semiconductor device includes a semiconductor substrate including an NMOS region and a PMOS region, active regions of the semiconductor substrate defined by a device isolation structure formed in the semiconductor substrate, the active regions including an NMOS active region defined in the NMOS region and a PMOS active region defined in the PMOS region, a gate insulating film disposed over the active regions, and a dual poly gate including an amorphous titanium layer formed over the gate insulating film in the NMOS region and the PMOS region. The dual poly gate includes a stacked structure having a lower gate electrode formed of an impurity doped polysilicon layer, a barrier layer including the amorphous titanium layer, and an upper gate electrode formed of a tungsten layer.09-18-2008
20080224208Semiconductor device and method for fabricating the same - A semiconductor device includes a semiconductor substrate including an NMOS region and a PMOS region, a device isolation structure formed on the semiconductor substrate to define an active region, a recess channel structure formed in the active region, a gate insulating film disposed in the recess channel structure, and a gate including an undoped amorphous silicon layer formed over the gate insulating film, the gate filling the recess channel structure.09-18-2008
20120248532SEMICONDUCTOR DEVICE - Plural island-form emitter cells (10-04-2012
20120248530APPROACH TO INTERGRATE SCHOTTKY IN MOSFET - An integrated structure combines field effect transistors and a Schottky diode. Trenches formed into a substrate composition extend along a depth of the substrate composition forming mesas therebetween. Each trench is filled with conductive material separated from the trench walls by dielectric material forming a gate region. Two first conductivity type body regions inside each mesa form wells partly into the depth of the substrate composition. An exposed portion of the substrate composition separates the body regions. Second conductivity type source regions inside each body region are adjacent to and on opposite sides of each well. Schottky barrier metal inside each well forms Schottky junctions at interfaces with exposed vertical sidewalls of the exposed portion of the substrate composition separating the body regions.10-04-2012
20120248529METHODS OF FORMING VERTICAL FIELD-EFFECT TRANSISTOR WITH SELF-ALIGNED CONTACTS FOR MEMORY DEVICES WITH PLANAR PERIPHERY/ARRAY AND INTERMEDIATE STRUCTURES FORMED THEREBY - Methods of forming a memory device having an array portion including a plurality of array transistors and a periphery region including peripheral circuit transistor structures of the memory device, where an upper surface of the periphery region and an upper surface of the array portion are planar (or nearly planar) after formation of the peripheral circuit transistor structures and a plurality of memory cells (formed over the array transistors). The method includes forming the peripheral circuit transistor structures in the periphery region, forming the plurality of array transistors in the array portion and forming a plurality of memory cells over respective vertical transistors. Structures formed by the method have planar upper surfaces of the periphery and array regions.10-04-2012
20130175611SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - An area in a top view of a region where a low-voltage field effect transistor is formed is reduced, and an area in a top view of a region where a high-voltage field effect transistor is formed is reduced. An active region where the low-voltage field effect transistors (first nMIS and first pMIS) are formed is constituted by a first convex portion of a semiconductor substrate that projects from a surface of an element isolation portion, and an active region where the high-voltage field effect transistors (second nMIS and second pMIS) are formed is constituted by a second convex portion of the semiconductor substrate that projects from the surface of the element isolation portion, and a trench portion formed in the semiconductor substrate.07-11-2013
20130175612DUAL GATE OXIDE TRENCH MOSFET WITH CHANNEL STOP TRENCH - A semiconductor device and fabrication methods are disclosed. The device includes a plurality of gate electrodes formed in trenches located in an active region of a semiconductor substrate. A first gate runner is formed in the substrate and electrically connected to the gate electrodes, wherein the first gate runner surrounds the active region. A second gate runner is connected to the first gate runner and located between the active region and a termination region. A termination structure surrounds the first and second gate runners and the active region. The termination structure includes a conductive material in an insulator-lined trench in the substrate, wherein the termination structure is electrically shorted to a source or body layer of the substrate thereby forming a channel stop for the device.07-11-2013
20110266618SEMICONDUCTOR DEVICE - A semiconductor device of the present invention has a first-conductivity-type substrate having second-conductivity-type base regions exposed to a first surface thereof; trench gates provided to a first surface of the substrate; first-conductivity-type source regions formed shallower than the base regions; a plurality of second-conductivity-type column regions located between two adjacent trench gates in a plan view, while being spaced from each other in a second direction normal to the first direction; the center of each column region and the center of each base contact region fall on the center line between two trench gates; and has no column region formed below the trench gates.11-03-2011
20110272761SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a source metallization, a source region of a first conductivity type in contact with the source metallization, a body region of a second conductivity type which is adjacent to the source region. The semiconductor device further includes a first field-effect structure including a first insulated gate electrode and a second field-effect structure including a second insulated gate electrode which is electrically connected to the source metallization. The capacitance per unit area between the second insulated gate electrode and the body region is larger than the capacitance per unit area between the first insulated gate electrode and the body region.11-10-2011
20130140631SEMICONDUTOR ISOLATION STRUCTURE AND METHOD OF MANUFACTURE - A method of formation of an isolation structure for vertical semiconductor devices, the resulting isolation structure, and a memory device to prevent leakage among adjacent vertical semiconductor devices are described.06-06-2013
20100276751INTEGRATED CIRCUIT UTILIZING TRENCH-TYPE POWER MOS TRANSISTOR - An integrated circuit includes a power MOS transistor which comprises a drain region, a trench gate, a source region, a well region, a deep well region and a substrate region. The drain region has a doping region of a first conductivity type connected to a drain electrode. The trench gate has an insulating layer and extends into the drain region. The source region has a doping region of the first conductivity type connected to a source electrode. The well region is doped with a second conductivity type, formed under the source region, and connected to the source electrode. The deep well region is doped with the first conductivity type and is formed under the drain region and the well region. The substrate region is doped with the second conductivity type and is formed under the deep well region. The drain region is formed at one side of the trench gate and the source region is formed at the opposing side of the trench gate such that the trench gate laterally connects the source region and the drain region.11-04-2010
20110220994Method of Forming a DRAM Array of Devices with Vertically Integrated Recessed Access Device and Digitline - A method is disclosed for forming a memory device having buried access lines (e.g., wordlines) and buried data/sense lines (e.g., digitlines) disposed below vertical cell contacts. The buried wordlines may be formed trenches in a substrate extending in a first direction, and the buried digitlines may be formed from trenches in a substrate extending in a second direction perpendicular to the first direction. The buried digitlines may be coupled to a silicon sidewall by a digitline contact disposed between the digitlines and the silicon substrate.09-15-2011
20130146970Semiconductor Device Including First and Second Semiconductor Elements - A semiconductor device includes a first semiconductor element including a first pn junction between a first terminal and a second terminal. The semiconductor device further includes a semiconductor element including a second pn junction between a third terminal and a fourth terminal. The semiconductor element further includes a semiconductor body including the first semiconductor element and the second semiconductor element monolithically integrated. The first and third terminals are electrically coupled to a first device terminal. The second and fourth terminals are electrically coupled to a second device terminal. A temperature coefficient α06-13-2013
20130146971Semiconductor Device Including First and Second Semiconductor Elements - A semiconductor device includes a first semiconductor element including a first pn junction between a first terminal and a second terminal. The semiconductor device further includes a semiconductor element including a second pn junction between a third terminal and a fourth terminal. The semiconductor element further includes a semiconductor body including the first semiconductor element and the second semiconductor element monolithically integrated. The first and third terminals are electrically coupled to a first device terminal. The second and fourth terminals are electrically coupled to a second device terminal. A temperature coefficient α06-13-2013
20130146972SEMICONDUCTOR DEVICE HAVING ISOLATION TRENCHES - A semiconductor uses an isolation trench, and one or more additional trenches to those required for isolation are provided. These additional trenches can be connected between a transistor gate and the drain to provide additional gate-drain capacitance, or else they can be used to form series impedance coupled to the transistor gate. These measures can be used separately or in combination to reduce the switching speed and thereby reduce current spikes.06-13-2013
20120273877SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A trench is formed so as to reach a p11-01-2012
20110233667DUAL GATE OXIDE TRENCH MOSFET WITH CHANNEL STOP TRENCH AND THREE OR FOUR MASKS PROCESS - A semiconductor device and fabrication methods are disclosed. The device includes a plurality of gate electrodes formed in trenches located in an active region of a semiconductor substrate. A first gate runner is formed in the substrate and electrically connected to the gate electrodes, wherein the first gate runner surrounds the active region. A second gate runner is connected to the first gate runner and located between the active region and a termination region. A termination structure surrounds the first and second gate runners and the active region. The termination structure includes a conductive material in an insulator-lined trench in the substrate, wherein the termination structure is electrically shorted to a source or body layer of the substrate thereby forming a channel stop for the device.09-29-2011
20110233666OXIDE TERMINATED TRENCH MOSFET WITH THREE OR FOUR MASKS - An oxide termination semiconductor device may comprise a plurality of gate trenches, a gate runner, and an insulator termination trench. The gate trenches are located in an active region. Each gate trench includes a conductive gate electrode. The insulator termination trench is located in a termination region that surrounds the active region. The insulator termination trench is filled with an insulator material to form an insulator termination for the semiconductor device. The device can be made using a three-mask or four-mask process.09-29-2011
20130153999TRENCH GATE MOSFET DEVICE - A trench gate MOSFET device has a drain region, a drift region, a trench gate having a gate electrode and a poly-silicon region, a super junction pillar juxtaposing the trench gate, a body region and a source region. By the interaction among the trench gate, the drift region and the super junction pillar, the break down voltage of the trench gate MOSFET device may be relatively high while the on-state resistance of the trench gate MOSFET device may be maintained relatively small.06-20-2013
20130153996HYBRID CMOS NANOWIRE MESH DEVICE AND PDSOI DEVICE - A method of forming a hybrid semiconductor structure on an SOI substrate. The method includes an integrated process flow to form a nanowire mesh device and a PDSOI device on the same SOI substrate. Also included is a semiconductor structure which includes the nanowire mesh device and the PDSOI device on the same SOI substrate.06-20-2013
20130153997HYBRID CMOS NANOWIRE MESH DEVICE AND BULK CMOS DEVICE - A method of forming a hybrid semiconductor structure on an SOI substrate. The method includes an integrated process flow to form a nanowire mesh device and a bulk CMOS device on the same SOI substrate. Also included is a semiconductor structure which includes the nanowire mesh device and the bulk CMOS device on the same SOI substrate.06-20-2013
20130153998DATA STORAGE DEVICE AND METHODS OF MANUFACTURING THE SAME - Provided are data storage devices and methods of manufacturing the same. The device may include a plurality of cell selection parts formed in a substrate, a plate conductive pattern covering the cell selection parts and electrically connected to first terminals of the cell selection parts, a plurality of through-pillars penetrating the plate conductive pattern and insulated from the plate conductive pattern, and a plurality of data storage parts directly connected to the plurality of through-pillars, respectively. The data storage parts may be electrically connected to second terminals of the cell selection parts, respectively.06-20-2013
20130154000SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - The present invention provides a technique capable of attaining an improvement in current detection accuracy in a trench gate type power MISFET equipped with a current detection circuit. Inactive cells are disposed so as to surround the periphery of a sense cell. That is, the inactive cell is provided between the sense cell and an active cell. All of the sense cell, active cell and inactive cells are respectively formed of a trench gate type power MISFET equipped with a dummy gate electrode. At this time, the depth of each trench extends through a channel forming region and is formed up to the deep inside (the neighborhood of a boundary with a semiconductor substrate) of an n-type epitaxial layer. Further, a p-type semiconductor region is provided at a lower portion of each trench. The p-type semiconductor region is formed so as to contact the semiconductor substrate.06-20-2013
20120280315SEMICONDUCTOR DEVICE - A semiconductor device for use in a power supply circuit has first and second MOSFETS. The source-drain path of one of the MOSFETS are coupled to the source-drain path of the other, and a load element is coupled to a connection node of the source-drain paths. The second MOSFET is formed on a semiconductor substrate with a Schottky barrier diode. First gate electrodes of the second MOSFET are formed in trenches in a first region of the semiconductor substrate, while second gate electrodes of the second MOSFET are formed in trenches in a second region of the semiconductor substrate. The first and second gate electrodes are electrically connected together. Portions of the Schottky barrier diode are formed between adjacent ones of the second gate electrodes. A center-to-center spacing between adjacent first gate electrodes is smaller than a center-to-center spacing between adjacent second gate electrodes.11-08-2012
20110309437SEMICONDUCTOR DEVICE - To attain reduction in size of a semiconductor device having a power transistor and an SBD, a semiconductor device according to the present invention comprises a first region and a second region formed on a main surface of a semiconductor substrate; plural first conductors and plural second conductors formed in the first and second regions respectively; a first semiconductor region and a second semiconductor region formed between adjacent first conductors in the first region, the second semiconductor region lying in the first semiconductor region and having a conductivity type opposite to that of the first semiconductor region; a third semiconductor region formed between adjacent second conductors in the second region, the third semiconductor region having the same conductivity type as that of the second semiconductor region and being lower in density than the second semiconductor region; a metal formed on the semiconductor substrate in the second region, the third semiconductor region having a metal contact region for contact with the metal, the metal being electrically connected to the second semiconductor region, and a center-to-center distance between adjacent first conductors in the first region being smaller than that between adjacent second conductors in the second region.12-22-2011
20120018802Ultra-low-cost three mask layers trench MOSFET and method of manufacture - An ultra-low-cost three mask layers trench MOSFET and its method of manufacture, wherein the method includes posting a uniform-covering dielectric layer deposition, and then the topography of trenches with different open size is quite different, wherein the smaller open size trench is fully filled, while only bottom and sidewall are covered for the bigger one. After a patterned dry etch process, the bottom of the bigger trench is opened with dielectric spacer left on sidewall, and the smaller one is still filled with dielectric material. The remained dielectric material is used as masks for following N+ source implantation and/or P-body implantation. A self-aligned source contact process is performed using the remained dielectric material in the trench as hard mask, so the limitation coming from source contact trench to gate trench mis-alignment during photo process is eliminated. Therefore, the much higher cell density, means high device performance, could be achieved.01-26-2012
20120018801VERTICAL CHANNEL TRANSISTOR ARRAY AND MANUFACTURING METHOD THEREOF - A vertical channel transistor array has an active region formed by a plurality of semiconductor pillars. A plurality of embedded bit lines are arranged in parallel in a semiconductor substrate and extended along a column direction. A plurality of bit line contacts are respectively disposed on a side of one of the embedded bit lines. A plurality of embedded word lines are arranged in parallel above the embedded bit lines and extended along a row direction. Besides, the embedded word lines connect the semiconductor pillars in the same row with a gate dielectric layer sandwiched between the embedded word lines and the semiconductor pillars. The current leakage isolation structure is disposed at terminals of the embedded bit lines to prevent current leakage between the adjacent bit line contacts.01-26-2012
20130193511VERTICAL TRANSISTOR STRUCTURE - A vertical transistor structure comprises a substrate, a plurality of pillars formed on the substrate and spaced from each other, a plurality of trenches each formed between two adjacent pillars, a protection layer formed on the surface of a first side wall and the surface of a second side wall of the trench, a first gate and a second gate respectively formed on the protection layer of the first side wall and the second side wall, and a separation layer covering a bottom wall of the trench. The present invention uses the separation layer functioning as an etch stopping layer to the first gate and the second gate while being etched. Further, thickness of the separation layer is used to control the distance between the bottom wall and the first and second gates and define widths of the drain and the source formed in the pillar via ion implantation.08-01-2013
20120086075DEVICE WITH ALUMINUM SURFACE PROTECTION - A semiconductor structure with a metal gate structure includes a first type field-effect transistor having a first gate including: a high k dielectric material on a substrate, a first metal layer on the high k dielectric material layer and having a first work function, and a first aluminum layer on the first metal layer. The first aluminum layer includes an interfacial layer including aluminum, nitrogen and oxygen. The device also includes a second type field-effect transistor having a second gate including: the high k dielectric material on the substrate, a second metal layer on the high k dielectric material layer and having a second work function different from the first work function, and a second aluminum layer on the second metal layer.04-12-2012
20120086074Semiconductor Devices And Methods of Forming The Same - Semiconductor devices and methods of forming the same may be provided. The semiconductor devices may include a trench in a substrate. The semiconductor devices may also include a bulk electrode within opposing sidewalls of the trench. The semiconductor devices may further include a liner electrode between the bulk electrode and the opposing sidewalls of the trench. The liner electrode may include a sidewall portion between a sidewall of the bulk electrode and one of the opposing sidewalls of the trench.04-12-2012

Patent applications in class In integrated circuit structure