Entries |
Document | Title | Date |
20080197407 | Power Semiconductor Devices with Barrier Layer to Reduce Substrate Up-Diffusion and Methods of Manufacture - A method for controlling the thickness of an expitaxially grown semiconductor material includes providing a semiconductor substrate that is doped by dopants of a first type; forming a buffer layer atop the semiconductor substrate, the buffer layer being doped with dopants of a second type that has much less diffusivity relative to that of dopants of the first type and forming the expitaxially grown layer atop the buffer layer to a desired thickness. The buffer layer, which acts to counter an up-diffusion of the dopants of the first type from the substrate into the epitaxially grown layer, can be doped with arsenic or carbon or both arsenic and carbon. A semiconductor device includes the buffer layer to counter an up-diffusion of the dopants of the first type from the substrate into the epitaxially grown layer. | 08-21-2008 |
20080203472 | LATERAL MOSFET AND MANUFACTURING METHOD THEREOF - A lateral MOSFET according to the present invention has a trench gate structure having a cross sectional shape spreading toward an open end. | 08-28-2008 |
20080211014 | ULTRA DENSE TRENCH-GATED POWER DEVICE WITH THE REDUCED DRAIN-SOURCE FEEDBACK CAPACITANCE AND MILLER CHARGE - The cellular structure of the power device includes a substrate that has a highly doped drain region. Over the substrate there is a more lightly doped epitaxial layer of the same doping. Above the epitaxial layer is a well region formed of an opposite type doping. Covering the wells is an upper source layer of the first conductivity type that is heavily doped. The trench structure includes a sidewall oxide or other suitable insulating material that covers the sidewalls of the trench. The bottom of the trench is filled with a doped polysilicon shield. An interlevel dielectric such as silicon nitride covers the shield. The gate region is formed by another layer of doped polysilicon. A second interlevel dielectric, typically borophosphosilicate glass (BPSG) covers the gate. In operation, current flows vertically between the source and the drain through a channel in the well when a suitable voltage is applied to the gate. | 09-04-2008 |
20080211015 | METHOD OF MANUFACTURING A SEMICONDUCTOR POWER DEVICE - A trench is formed in a semiconductor body, the side walls and the bottom of the trench covered with a first dielectric material layer, the trench filled with a second dielectric material layer, the first and the second dielectric material layers are etched via a partial, simultaneous, and controlled etching such that the dielectric materials have similar etching rates, a gate-oxide layer having a thickness smaller than the first dielectric material layer deposited on the walls of the trench, a gate region of conductive material formed within the trench, and body regions and source regions formed within the semiconductor body at the sides of and insulated from the gate region. Thereby, the gate region extends only on top of the remaining portions of the first and second dielectric material layers. | 09-04-2008 |
20080211016 | TRENCH MOSGATED DEVICE WITH DEEP TRENCH BETWEEN GATE TRENCHES - A trench gated MOSFET especially for operation in high radiation environments has a deep auxiliary trench located between the gate trenches. A boron implant is formed in the walls of the deep trench (in an N channel device); a thick oxide is formed in the bottom of the trench, and boron doped polysilicon which is connected to the source electrode fills the trench. The structure has reduced capacitance and improved resistance to single event rupture and single event breakdown and improved resistance to parasitic bipolar action. | 09-04-2008 |
20080224206 | METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTORS (MOSFETS) INCLUDING RECESSED CHANNEL REGIONS AND METHODS OF FABRICATING THE SAME - Unit cells of metal oxide semiconductor (MOS) transistors are provided having an integrated circuit substrate and a MOS transistor on the integrated circuit substrate. The MOS transistor includes a source region, a drain region and a gate. The gate is between the source region and the drain region. A channel region is provided between the source and drain regions. The channel region has a recessed region that is lower than bottom surfaces of the source and drain regions. Related methods of fabricating transistors are also provided. | 09-18-2008 |
20080230833 | SEMICONDUCTOR COMPONENT AND METHOD FOR PRODUCING A SEMICONDUCTOR COMPONENT - A semiconductor component having a semiconductor body having first and second semiconductor regions of a first conduction type, and a third semiconductor region of a second conduction type, which is complementary to the first conduction type. The second semiconductor region is arranged between the first and third semiconductor region and together with the first semiconductor region forms a first junction region and together with the third semiconductor region forms a second junction region. In the second semiconductor region the dopant concentration is lower than the dopant concentration in the first semiconductor region. The dopant concentration in the second semiconductor region along a straight connecting line between the first and third semiconductor regions is inhomogeneous and has at least one minimum between the first and second junction regions, wherein the minimum is at a distance from the first and second junction regions. | 09-25-2008 |
20080251838 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor substrate, at least a surface portion thereof serving as a low-resistance drain layer of a first conductivity type; a first main electrode connected to the low-resistance drain layer; a high-resistance epitaxial layer of a second-conductivity type formed on the low-resistance drain layer; a second-conductivity type base layer selectively formed on the high-resistance epitaxial layer; a first-conductivity type source layer selectively formed in a surface portion of the second-conductivity type base layer; a trench formed in a region sandwiched by the second-conductivity type base layers with a depth extending from the surface of the high-resistance epitaxial layer to the semiconductor substrate; a jfet layer of the first conductivity type formed on side walls of the trench; an insulating layer formed in the trench; an LDD layer of the first-conductivity type formed in a surface portion of the second-conductivity type base layer so as to be connected to the first-conductivity type jfet layer around a top face of the trench; a control electrode formed above the semiconductor substrate so as to be divided into a plurality of parts, and formed on a gate insulating film formed on a part of the surface of the LDD layer, on surfaces of end parts of the first-conductivity type source layer facing each other across the trench, and on a region of the surface of the second-conductivity type base layer sandwiched by the LDD layer and the first-conductivity type source layer; and a second main electrode in ohmic contact with the first-conductivity type source layer and the second-conductivity type base layer so as to sandwich the control electrode. | 10-16-2008 |
20080258210 | SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE - A semiconductor component resistant to the formation of a parasitic bipolar transistor and a method for manufacturing the semiconductor component using a reduced number of masking steps. A semiconductor material of N-type conductivity having a region of P-type conductivity is provided. A doped region of N-type conductivity is formed in the region of P-type conductivity. Trenches are formed in a semiconductor material and extend through the regions of N-type and P-type conductivities. A field oxide is formed from the semiconductor material such that portions of the trenches extend under the field oxide. The field oxide serves as an implant mask in the formation of source regions. Body contact regions are formed from the semiconductor material and an electrical conductor is formed in contact with the source and body regions. An electrical conductor is formed in contact with the backside of the semiconductor material. | 10-23-2008 |
20080258211 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - In a MIS-type semiconductor device having a trench gate structure, a withstand voltage is ensured without changing the thickness of a drift layer and on-resistance can be reduced without applying a high gate drive voltage. The lower half of a trench extending through a p-base region into an n-drift region is filled with a high-permittivity dielectric having a relative permittivity that is higher than that of a silicon oxide film, preferably a silicon nitride film, and an insulated gate structure including a gate insulator and a gate electrode is fabricated on the high-permittivity dielectric. The depth d | 10-23-2008 |
20080258212 | TRENCH METAL OXIDE SEMICONDUCTOR WITH RECESSED TRENCH MATERIAL AND REMOTE CONTACTS - Remote contacts to the polysilicon regions of a trench metal oxide semiconductor (MOS) barrier Schottky (TMBS) device, as well as to the polysilicon regions of a MOS field effect transistor (MOSFET) section and of a TMBS section in a monolithically integrated TMBS and MOSFET (SKYFET) device, are employed. The polysilicon is recessed relative to adjacent mesas. Contact of the source metal to the polysilicon regions of the TMBS section is made through an extension of the polysilicon to outside the active region of the TMBS section. This change in the device architecture relieves the need to remove all of the oxides from both the polysilicon and silicon mesa regions of the TMBS section prior to the contact step. As a consequence, encroachment of contact metal into the sidewalls of the trenches in a TMBS device, or in a SKYFET device, is avoided. | 10-23-2008 |
20080258213 | Shielded Gate Field Effect Transistor - A FET includes a trench in a semiconductor region. The trench has a lower portion with a shield electrode therein, and an upper portion with a gate electrode therein, where the upper portion is wider than the lower portion. The semiconductor region includes a substrate of a first conductivity type and a first silicon region of a second conductivity type over the substrate. The first silicon region has a first portion extending to a depth intermediate top and bottom surfaces of the gate electrode. The first silicon region has a second portion extending to a depth intermediate top and bottom surfaces of the shield electrode. The semiconductor region further includes a second silicon region of the first conductivity type between the lower trench portion and the second portion of the first silicon region that has a laterally-graded doping concentration decreasing in a direction away from the sidewalls of the lower trench portion. | 10-23-2008 |
20080265314 | Semiconductor device having vertical MOSFET and method of manufacturing the same - An ON-resistance of a semiconductor device including a vertical MOSFET whose source electrode, gate electrode, and drain electrode are formed on a single surface is reduced. A drift region which is lower in impurity concentration than a drain region is formed over the drain region. A gate trench and a drain contact trench are simultaneously formed in the drift region. A gate insulating film and a gate electrode are formed in the gate trench. A drain electrode is formed in the drain contact trench. A drain contact region which is higher in impurity concentration than the drift region is formed immediately under the drain contact trench. | 10-30-2008 |
20080265315 | SEMICONDUCTOR DEVICE WITH A SEMICONDUCTOR BODY AND METHOD FOR PRODUCING IT - A semiconductor device with a semiconductor body and to a method for producing it. In one embodiment, the semiconductor body has first electrodes which contact first highly doped semiconductor zones and complementary-conduction body zones surrounding the first semiconductor zones. The semiconductor body has a second electrode which contacts a second highly doped semiconductor zone. Between the second semiconductor zone and the body zones, a drift zone is arranged. Control electrodes which are insulated from the semiconductor body by a gate oxide and act on the body zones for controlling the semiconductor device are arranged on the semiconductor body. The body zones have minority charge carrier injector zones with complementary conduction to the body zones, arranged between the first semiconductor zones and the drift zone. | 10-30-2008 |
20080265316 | SEMICONDUCTOR STRUCTURE WITH FIELD SHIELD AND METHOD OF FORMING THE STRUCTURE - Disclosed is semiconductor structure that incorporates a field shield below a semiconductor device (e.g., a field effect transistor (FET) or a diode). The field shield is sandwiched between upper and lower isolation layers on a wafer. A local interconnect extends through the upper isolation layer and connects the field shield to a selected doped semiconductor region of the device (e.g., a source/drain region of a FET or a cathode or anode of a diode). Current that passes into the device, for example, during back-end of the line charging, is shunted by the local interconnect away from the upper isolation layer and down into the field shield. Consequently, an electric charge is not allowed to build up in the upper isolation layer but rather bleeds from the field shield into the lower isolation layer and into the substrate below. This field shield further provides a protective barrier against any electric charge that becomes trapped within the lower isolation layer or substrate | 10-30-2008 |
20080265317 | TECHNIQUE FOR FORMING THE DEEP DOPED COLUMNS IN SUPERJUNCTION - A method of manufacturing a semiconductor device is disclosed and starts with a semiconductor substrate having a heavily doped N region at the bottom main surface and having a lightly doped N region at the top main surface. There are a plurality of trenches in the substrate, with each trench having a first extending portion extending from the top main surface towards the heavily doped region. Each trench has two sidewall surfaces in parallel alignment with each other. A blocking layer is formed on the sidewalls and the bottom of each trench. Then a P type dopant is obliquely implanted into the sidewall surfaces to form P type doped regions. The blocking layer is then removed. The bottom of the trenches is then etched to remove any implanted P type dopants. The implants are diffused and the trenches are filled. | 10-30-2008 |
20080272428 | Semiconductor Device Structure With a Tapered Field Plate and Cylindrical Drift Region Geometry - A vertically oriented self terminating discrete trench MOS device ( | 11-06-2008 |
20080272429 | SUPERJUNCTION DEVICES HAVING NARROW SURFACE LAYOUT OF TERMINAL STRUCTURES AND METHODS OF MANUFACTURING THE DEVICES - Superjunction semiconductor devices having narrow surface layout of terminal structures and methods of manufacturing the devices are provided. The narrow surface layout of terminal structures is achieved, in part, by connecting a source electrode to a body contact region within a semiconductor substrate at a body contact interface comprising at least a first side of the body contact region other than a portion of a first main surface of the semiconductor substrate. | 11-06-2008 |
20080272430 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device includes an active region defined in a substrate, the active region having a trench extending below a surface of the substrate; an impurity region provided along a bottom surface and a lower sidewall of the trench, wherein an upper portion of the impurity region is spaced apart from the surface of the substrate and an upper portion of the trench; a gate insulating layer provided along an inner surface of the trench; and a gate electrode provided in the trench. | 11-06-2008 |
20080272431 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING RECESS GATE STRUCTURE WITH VARYING RECESS WIDTH FOR INCREASED CHANNEL LENGTH - A varying-width recess gate structure having a varying-width recess formed in a semiconductor device can sufficiently increase the channel length of the transistor having a gate formed in the varying-width recess, thereby effectively reducing the current leakage and improving the refresh characteristics. In the method of manufacturing the recess gate structure, etching is performed twice or more, so as to form a gate recess having varying width in the substrate, and a gate is formed in the gate recess. | 11-06-2008 |
20080277722 | Semiconductor device and method of manufacturing the semiconductor device - A method of manufacturing a semiconductor. A first epitaxial layer is formed on a gate nitride layer, and a protection nitride layer is formed on the first epitaxial and gate nitride layers. A first gate insulation layer is formed on a drain silicide, a gate oxide layer is formed on a portion of the first epitaxial layer exposed by a trench. A second epitaxial layer is formed on the first layer. Polysilicon fills the trench to form a gate electrode. Ion-implanting impurities on the second epitaxial layer forms a source region. A second gate insulation layer is formed on the gate electrode and the gate oxide layer, a source silicide is formed on the second gate insulation layer, and an interlayer insulation layer is formed on the second epitaxial layer, source region and source silicide. Source, gate and drain contact holes expose the source silicide, gate electrode and drain silicide. | 11-13-2008 |
20080283909 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device includes a second-conductivity-type base region provided on a first-conductivity-type semiconductor layer, a first-conductivity-type source region provided on the second-conductivity-type base region, a gate insulating film covering an inner wall of a trench which passes through the second-conductivity-type base region and reaching the first-conductivity-type semiconductor layer, a gate electrode buried in the trench via the gate insulating film, and a second-conductivity-type region being adjacent to the second-conductivity-type base region below the first-conductivity-type source region, spaced from the gate insulating film, and having a higher impurity concentration than the second-conductivity-type base region. c≧d is satisfied, where d is a depth from an upper surface of the first-conductivity-type source region to a lower end of the gate electrode, and c is a depth from an upper surface of the first-conductivity-type source region to a lower surface of the second-conductivity-type base region. | 11-20-2008 |
20080290404 | SEMICONDUCTOR DEVICE AND A METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate provided with an active region including a gate forming area, a source forming area and a drain forming area. A recess is formed in the gate forming area. A gate is formed over the gate forming area that is formed with the recess and includes an insulation layer formed at an upper end portion of a side wall of the recess that is in contact with the source forming area. A source area and a drain area are formed in the active region on opposite sides of the gate. | 11-27-2008 |
20080290405 | Power mosfet diode - A power MOSFET diode includes a plurality of unit elements, each of which has a gate and a drain that are connected to each other by the structure and the process of UMOS, VMOS, VDMOS, and etc., so as to integrate the unit elements into a PMD without any body diode of the traditional UMOS, VMOS, or VDMOS for providing a one-way electrical conductivity. The PMD is different from traditional diodes or Schottky diodes, because a forward bias is existed when the traditional diodes or Schottky diodes conduct the electricity on one-way. However, a drain-source on-state resistance (RDS) is used to replace the consumption of the forward bias when the PMD conducts the electricity on one-way. Due to the RDS of the PMD is lower and easy to be parallel connected to each other, the PMD can be used to substantially lower the power consumption and applied to various industries. | 11-27-2008 |
20080290406 | METHOD FOR PRODUCING A VERTICAL FIELD EFFECT TRANSISTOR - A method for producing a field effect transistor, in which a plurality of layers are in each case deposited, planarized and etched back, in particular a gate electrode layer, is disclosed. This method allows the manufacturing of transistors having outstanding electrical properties and having outstanding reproducibility. | 11-27-2008 |
20080296670 | Semiconductor Devices Including Transistors Having a Recessed Channel Region and Methods of Fabricating the Same - Some embodiments of the present invention provide semiconductor devices including a gate trench in an active region of a semiconductor substrate and a gate electrode in the gate trench. A low-concentration impurity region is provided in the active region adjacent to a sidewall of the gate trench. A high-concentration impurity region is provided between the low-concentration impurity region and the sidewall of the gate trench and along the sidewall of the gate trench. Related methods of fabricating semiconductor devices are also provided herein. | 12-04-2008 |
20080296671 | SEMICONDUCTOR MEMORY DEVICE, MANUFACTURING METHOD THEREOF, AND DATA PROCESSING SYSTEM - A semiconductor memory device includes a silicon pillar, a gate electrode covering a side surface of the silicon pillar via a gate insulation film, diffusion layers ( | 12-04-2008 |
20080296672 | TRANSISTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A transistor device includes a recess in a surface of semiconductor substrate, a gate insulation layer formed over an inner side of the recess, a gate conductor filling the recess in which the gate insulation layer is formed, and source and drain regions located over the substrate adjacent the recess. Among the advantages: the gate structure lowers overall gate resistance and reduces the short channel effect. | 12-04-2008 |
20080303085 | SEMICONDUCTOR DEVICE INCLUDING ACTIVE PATTERN WITH CHANNEL RECESS, AND METHOD OF FABRICATING THE SAME - A semiconductor device including an active pattern having a channel recess portion, and a method of fabricating the same, are disclosed. In one embodiment, the semiconductor device includes an active pattern including first active regions and a second active region interposed between the first active regions. The active pattern protrudes above a surface of a semiconductor substrate and includes a channel recess portion above the second active region and between the first active regions. A device isolation layer surrounds the active pattern and has a groove exposing side walls of the recessed second active region. A distance between opposing side walls of the first active regions exposed by the channel recess portion is greater than a distance between side walls of the groove. A gate pattern is located in the channel recess portion and extends along the groove. | 12-11-2008 |
20080303086 | Semiconductor apparatus and method for fabricating the same - A semiconductor apparatus including a trench gate transistor having at least an active region surrounded by a device isolation insulating film; a trench provided by bringing both ends thereof into contact with the device isolation insulating film in the active region; a gate electrode formed in the trench via a gate insulating film; and a diffusion layer formed close to the trench; on a semiconductor substrate, and also includes an opening portion positioned on one surface of the semiconductor substrate; a pair of first inner walls positioned in a side of the device isolation insulating film and connected with the opening portion; a pair of second inner walls positioned in a side of the active region and connected with the opening portion; and a bottom portion positioned opposite to the opening portion and connected with the first inner walls and the second inner walls, wherein a cross sectional outline of the second inner wall is substantially linear, and a burr generated inside the trench is removed or reduced. | 12-11-2008 |
20080308863 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a buried isolation pattern between an active pattern on which transistors are formed and a substrate. The active pattern has adjacent sections each extending longitudinally in a first direction. A field isolation pattern is interposed between the adjacent sections of the active pattern. The buried isolation pattern has sections spaced apart from each other in the first direction under each section of the active pattern. Each section of the buried isolation pattern extends from a lower portion of the field isolation pattern in a second direction perpendicular to the first direction. At least one gate structure is disposed on each section of the active pattern, and an impurity region is located adjacent to the gate structure at the upper surface of the active pattern. The impurity region is spaced from the buried isolation pattern in a third direction perpendicular to the first and second directions. The buried isolation pattern offers a control on the body effect caused by a bias applied to the substrate. | 12-18-2008 |
20090001456 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes a transistor having a recessed gate, contact plugs formed in a region of a plurality of trenches, which are formed by recessing a semiconductor substrate. Further, a metal line and a source/drain region can be connected through the contact plug, so that on-current can be increased as much as an increased channel area. | 01-01-2009 |
20090001457 | Semiconductor structure - The present invention discloses a semiconductor structure comprising a semiconductor substrate having a U-shape trench, a U-shape gate dielectric layer on the U-shape trench, a U-shape gate region on the U-shape gate dielectric layer, a conducting matter in the U-shape gate region, and a cover dielectric layer on the conducting matter. The semiconductor structure may have a minimized size and when recess channels are formed thereby, the integration is accordingly improved without suffering from the short channel effect. | 01-01-2009 |
20090001458 | SEMICONDUCTOR DEVICE WITH SUBSTANTIAL DRIVING CURRENT AND DECREASED JUNCTION LEAKAGE CURRENT - The semiconductor device includes an active region, a stepped recess channel region including vertical channel structures, a gate insulating film, and a gate structure. The active region is defined by a device isolation structure formed in a semiconductor substrate. The stepped recess channel region is formed in the active region. The vertical silicon-on-insulator (SOI) channel structures are disposed at sidewalls of both device isolation structures in a longitudinal direction of a gate region. The gate insulating film is disposed over the active region including the stepped recess channel region. The gate structure is disposed over the stepped recess channel region of the gate region. | 01-01-2009 |
20090008708 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - The characteristics of a semiconductor device including a trench-gate power MISFET are improved. The semiconductor device includes a substrate having an active region where the power MISFET is provided and an outer circumferential region which is located circumferentially outside the active region and where a breakdown resistant structure is provided, a pattern formed of a conductive film provided over the substrate in the outer circumferential region with an insulating film interposed therebetween, another pattern isolated from the pattern, and a gate electrode terminal electrically coupled to the gate electrodes of the power MISFET and provided in a layer over the conductive film. The conductive film of the pattern is electrically coupled to the gate electrode terminal, while the conductive film of another pattern is electrically decoupled from the gate electrode terminal. | 01-08-2009 |
20090014784 | VERTICAL MOS TRANSISTOR AND METHOD THEREFOR - In one embodiment, a vertical MOS transistor is formed without a thick field oxide and particularly without a thick field oxide in the termination region of the transistor. | 01-15-2009 |
20090014785 | SEMICONDUCTOR DEVICE WITH IMPROVED BREAKDOWN PROPERTIES AND MANUFACTURING METHOD THEREOF - The present invention provides a semiconductor device ( | 01-15-2009 |
20090014786 | Field Effect Transistors Having Protruded Active Regions and Methods of Fabricating Such Transistors - Provided are a field effect transistor, a method of manufacturing the same, and an electronic device including the field effect transistor. The field effect transistor may have a structure in which a double gate field effect transistor and a recess channel array transistor are formed in a single transistor in order to improve a short channel effect which occurs as field effect transistors become more highly integrated, a method of manufacturing the same, and an electronic device including the field effect transistor. The field effect transistor can exhibit stable device characteristics even when more highly integrated in such a manner that both the length and width of a channel increase and particularly the channel can be significantly long, and can be manufactured simply. | 01-15-2009 |
20090020808 | Semiconductor integrated circuit devices and fabrication methods thereof - A memory cell of memory device, comprises an active region of a memory cell defined in a semiconductor substrate, and a conductive gate electrode in a trench of the active region. The gate electrode is isolated from the semiconductor substrate. An insulation layer is on the active region and on the conductive gate electrode. A conductive contact is in the insulation layer on the active region at a side of the gate electrode and isolated from the gate electrode. The contact has a first width at a top portion thereof and a second width at a bottom portion thereof, the first width being greater than the second width. The contact is formed of a single-crystal material. | 01-22-2009 |
20090020809 | Semiconductor device including trench gate transistor and method of forming the same - A semiconductor device includes an active region having a groove, a gate insulating film, and a gate electrode. The gate electrode may include first and second layers. The first layer extends along the gate insulating film. The first layer is electrically conductive. The second layer extends along the first layer. The second layer is separate from the gate insulating film by the first layer. | 01-22-2009 |
20090026531 | METHOD FOR INSULATING A SEMICONDUCTING MATERIAL IN A TRENCH FROM A SUBSTRATE - A method for insulating a semiconducting material in a trench from a substrate, wherein the trench is formed in the substrate and comprising an upper portion and a lower portion, the lower portion being lined with a first insulating layer and filled, at least partially, with a semiconducting material, comprises an isotropic etching of the substrate and the semiconducting material, and forming a second insulating layer in the trench, wherein the second insulating layer covers, at least partially, the substrate and the semiconducting material. | 01-29-2009 |
20090026532 | SHORT CIRCUIT LIMITING IN POWER SEMICONDUCTOR DEVICES - A power semiconductor device includes a semiconductor body. The semiconductor body includes a body region of a first conductivity type for forming therein a conductive channel of a second conductivity type; a gate electrode arranged next to the body region; and a floating electrode arranged between the gate electrode and the body region. | 01-29-2009 |
20090026533 | Trench MOSFET with multiple P-bodies for ruggedness and on-resistance improvements - A vertical semiconductor power device includes a plurality of semiconductor power cells having a drain disposed at a bottom of a semiconductor substrate. Each of the cells includes a gate surrounded by a body region encompassing a source region. The body region further includes multiple body-dopant implanted regions having a non-Gaussian distribution dopant profile for reducing a width of a transition region transitioning between the multiple body-dopant implanted regions and an epitaxial region underneath having a different conductivity type from the multiple body-dopant implanted regions. | 01-29-2009 |
20090026534 | Trench MOSFET and method of making the same - A trench MOSFET structure formed in a semiconductor substrate and method of forming the same are disclosed. The trench MOSFET includes a capacitor having a capacitor dielectric layer formed of an oxide-un-doped poly-oxide in the trench bottom. Firstly, the trenches are formed in a p-well of the epi-layer of an n-type impurity doped substrate through a lithographic and an etch step. Next, a gate oxide layer and an intrinsic polysilicon layer are successively formed, and a HTO layer is deposited on the trench bottom to form the oxide-un-doped poly-oxide dielectric layer. Subsequently a doped polysilicon layer is filled into the trench as a trench gate. Then, processes of source contact regions and gate contacts are followed. Finally a drain contact is formed on a rear surface of the substrate. | 01-29-2009 |
20090026535 | SEMICONDUCTOR DEVICE - The technology of preventing lowering of the element breakdown voltage of a trench gate control type semiconductor element is offered. n | 01-29-2009 |
20090026536 | TRENCH GATE SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A trench gate semiconductor device and a method for fabricating the same, which are capable of securing a sufficient margin for a photo process while achieving an enhancement in gate-source leakage characteristics, are disclosed. Embodiments relate to a method for fabricating a trench gate semiconductor device including forming a trench in an upper surface of an epitaxial layer formed over a semiconductor substrate. N type impurity ions may be implanted into a bottom surface of the trench, to form a diffusion layer. To form a well, P-type impurity ions may be implanted into a region beneath the diffusion layer. To form an oxide film buffer, the trench may be filled with an oxide. To form a gate trench, the resulting structure obtained after the filling of the oxide may be etched from the oxide film buffer to the epitaxial layer, in a region where a gate will be formed. NPN junctions may be formed beneath the oxide film buffer at opposite sides of the gate poly. Poly plugs may be formed to electrically connect P type portions of the NPN junctions to upper metal electrodes by filling the source trenches with polysilicon. The upper metal electrodes may be formed over the gate poly and over the poly plugs. | 01-29-2009 |
20090026537 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is a semiconductor device formed with a trench portion for providing a concave portion in a gate width direction and with a gate electrode provided within and on a top surface of the trench portion via a gate insulating film. At least a part of a surface of each of the source region and the drain region is made lower than other parts of the surface by removing a thick oxide film formed in the vicinity of the gate electrode. Making lower the part of the surface of each of the source region and the drain region allows current flowing through a top surface of the concave portion of the gate electrode at high concentration to flow uniformly through the entire trench portion, which increase an effective gate width of the concave portion formed so as to have a varying depth in a gate width direction. | 01-29-2009 |
20090026538 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is a semiconductor device formed with a trench portion for providing a concave portion having a continually varying depth in a gate width direction and with a gate electrode provided within the trench portion and on a top surface thereof via a gate insulating film. Before the formation of the gate electrode, an impurity is added to at least a part of the source region and the drain region by ion implantation from an inner wall of the trench portion, and then heat treatment is performed for diffusion and activation to form a diffusion region from the surface of the trench portion down to a bottom portion thereof. Current flowing through a top surface of the concave portion of the gate electrode at high concentration can flow uniformly through the entire trench portion. | 01-29-2009 |
20090032866 | METHODS OF FABRICATING DUAL FIN STRUCTURES AND SEMICONDUCTOR DEVICE STRUCTURES WITH DUAL FIN STRUCTURES - Fin-FET devices and methods of fabrication are disclosed. The Fin-FET devices include dual fins that may be used to provide a trench region between a source region and a drain region. In some embodiments, the dual fins may be formed by forming a trench with fin structures on opposite sides in a protruding region of a substrate. The dual fins may be useful in forming single-gate, double-gate or triple-gate fin-FET devices. Electronic systems including such fin-FET devices are also disclosed. | 02-05-2009 |
20090039422 | RECESS GATE OF SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A method for fabricating a semiconductor device, and more particularly, a method for forming a recess gate is disclosed. The method for forming a recess gate includes forming a first nitride layer over a semiconductor substrate, forming a first nitride layer pattern by selectively etching the first nitride layer to expose a portion of the substrate, forming a spacer over a sidewall of the first nitride layer pattern, forming a recess for a gate channel region by etching the substrate using the first nitride layer pattern and the spacer as an etching mask, forming a gate oxide layer over a sidewall and a bottom surface of the recess, forming a gate poly-silicon layer pattern to bury the recess and a space defined by the spacer, and removing the first nitride layer pattern. | 02-12-2009 |
20090045458 | MOS TRANSISTORS FOR THIN SOI INTEGRATION AND METHODS FOR FABRICATING THE SAME - MOS transistors for thin SOI integration and methods for fabricating such MOS transistors are provided. One exemplary method includes the steps of providing a silicon layer overlying a buried insulating layer and epitaxially growing a silicon-comprising material layer overlying the silicon layer. A trench is etched within the silicon-comprising material layer and exposing the silicon layer. An MOS transistor gate stack is formed within the trench. The MOS transistor gate stack comprises a gate insulator and a gate electrode. Ions of a conductivity-determining type are implanted within the silicon-comprising material layer using the gate stack as an implantation mask. | 02-19-2009 |
20090050958 | SEMICONDUCTOR DEVICE HAVING A SPACER LAYER DOPED WITH SLOWER DIFFUSING ATOMS THAN SUBSTRATE - A semiconductor device includes a silicon substrate heavily-doped with phosphorous. A spacer layer is disposed over the substrate and is doped with dopant atoms having a diffusion coefficient in the spacer layer material that is less than the diffusion coefficient of phosphorous in silicon. An epitaxial layer is also disposed over the substrate. A device layer is disposed over the substrate, and over the spacer layer. | 02-26-2009 |
20090057756 | Trench MOSFET with Trench Termination and manufacture thereof - A trench MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) with a trench termination, including a substrate including a drain region which is strongly doped and a doping epi layer region, which is weekly doped the same type as the drain region, on the drain region; a plurality of source and body regions formed in the epi layer; a metal layer including a plurality of metal layer regions which are connected to respective source and body, and gate regions forming metal connections of the MOSFET; a plurality of metal contact plugs connected to respective metal layer regions; a plurality of gate trenches filled with polysilicon to form a plurality of trenched gates on top of epi layer; an insulating layer deposited on the epi layer formed underneath the metal layer with a plurality of metal contact holes therein for contacting respective source and body regions; a margin terminating gate trench which is around the gate trenches; and a margin terminating active region which is formed underneath the margin terminating gate trench. | 03-05-2009 |
20090057757 | TRENCH GATE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Disclosed is a trench gate semiconductor device including: a semiconductor layer having a first conductivity type; a first diffusion region having a second conductivity type having a planar structure on the semiconductor layer; a second diffusion region having the first conductivity type positioned selectively on the first diffusion region; a gate electrode provided via a gate insulation film in each first trench facing the second diffusion region and penetrating through the first diffusion region to reach the semiconductor layer; a first semiconductor region of the second conductivity type provided at a position, in the semiconductor layer, apart in a lateral direction from the first diffusion region; a second semiconductor region of the second conductivity type provided at a position, in the first diffusion region, between the adjacent first trenches; and a main electrode in contact with the semiconductor layer and the second diffusion region. | 03-05-2009 |
20090065858 | DMOS TRANSISTOR AND FABRICATION METHOD THEREOF - In one example embodiment, a method of fabricating a DMOS transistor includes various steps. First, a P-type well or an N-type well is formed on a semiconductor substrate by an impurity injection. Next, a drift region is formed on the portion of the semiconductor substrate in which the well region is formed by injecting conductive impurities reverse to those of the well region. Then, a trench for forming a gate on the semiconductor substrate is formed within the drift region. Next, a gate oxide and a gate electrode are formed in the trench. Finally, source/drain regions are formed by injecting the same conductive impurities as those of the drift region at both sides of the gate electrode. | 03-12-2009 |
20090065859 | TRENCH TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME - A trench transistor and a manufacturing method for the same are disclosed. The manufacturing method includes preparing a semiconductor substrate, forming a trench in the semiconductor substrate, forming a gate oxide layer over an inner wall of the trench, forming a gate having a first conductivity type by embedding polysilicon in the trench, the gate including a protruding portion protruding over a surface of the semiconductor substrate, forming a barrier layer by implanting second conductivity type ions in the protruding portion, and forming a second conductivity type source region over the surface of the semiconductor substrate. | 03-12-2009 |
20090065860 | Semiconductor device and method for manufacturing the same - An exemplary object of the invention is to simultaneously achieve, in a semiconductor device which includes a trench gate structure formed by recessing a portion of a diffusion layer and an inter-diffusion-layer isolation insulating film which are formed on the a semiconductor substrate, good embeddability of the inter-diffusion-layer isolation insulating film and a reduction in channel resistance. In an exemplary embodiment, the diffusion layer which comprises a projecting structure is formed by selectively wet-etching the inter-diffusion-layer isolation insulating film with respect to the diffusion layer in the trench, and an overhanging structure is formed at a projecting portion of the diffusion layer further by selectively epitaxially growing the projecting structure of the diffusion layer. | 03-12-2009 |
20090072303 | NROM MEMORY CELL, MEMORY ARRAY, RELATED DEVICES AND METHODS - An array of memory cells configured to store at least one bit per one F | 03-19-2009 |
20090072304 | Trench misfet - In one embodiment of the present invention, trench sections cause regions where source diffusion sections and body diffusion sections are formed to be partitioned into line regions. The trench sections are formed not in a straight line shape but in a zigzag shape. Two adjacent trench sections are provided to be axisymmetric, having an axis of symmetry in a longitudinal direction of the trench sections. A wide region and a narrow region are alternately formed in each of the regions, partitioned by the trench sections, in which regions the source diffusion sections and the body diffusion sections are formed. Each of the body diffusion sections is formed in the wide region. This makes it possible to realize an improved power MOSFET that achieves a reduction in an ON resistance per unit cell and an increase in a layout effect. | 03-19-2009 |
20090072305 | Semiconductor device and method for manufacturing the same - A semiconductor device according to the present invention includes: a semiconductor layer made of silicon; a trench formed by digging in from a top surface of the semiconductor layer; a gate insulating film formed on an inner wall surface of the trench and made of silicon oxide; a gate electrode embedded in the trench via the gate insulating film and made of a polysilicon doped with an impurity; and an oxidation-resistant metal film disposed on a top surface of the gate electrode and covering the top surface. | 03-19-2009 |
20090078994 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - Disclosed is a semiconductor device having an n-type drain region, a low concentration p-type body region formed on the n-type drain region, an n-type source region formed on the low concentration p-type body region, a high concentration p-type body region formed on the low concentration p-type body region, a gate insulating film, and a gate electrode, wherein a plurality of trenches T which extend in a same direction and each of which forms a continuous concavo-convex shape when viewed from above are formed from top faces of the source region and the high concentration body region and pass through the low concentration body region to reach into the drain region, and wherein the gate electrode is buried in each of the plurality of trenches. A maximum distance between two adjacent trenches T of the n-type source region is greater than a maximum distance between the two adjacent trenches T of the high concentration p-type body region. | 03-26-2009 |
20090078995 | Semiconductor device and method of manufacturing semiconductor device - A semiconductor device includes a first conductivity type layer of a first conductivity type, a body layer of a second conductivity type formed on the first conductivity type layer, a gate trench passing through the body layer so that the deepest portion thereof reaches the first conductivity type layer, a source region of the first conductivity type formed around the gate trench on the surface layer portion of the body layer, a gate insulating film formed on the bottom surface and the side surface of the gate trench, and a gate electrode embedded in the gate trench through the gate insulating film, and the bottom surface of the gate electrode and the upper surface of the first conductivity type layer are flush with each other. | 03-26-2009 |
20090085103 | SEMICONDUCTOR DEVICE AND METHOD - A semiconductor device and production method is disclosed. In one embodiment, the semiconductor device includes a first electrode and a second electrode, located on surfaces of a semiconductor body, and an insulated gate electrode. The semiconductor body has a contact groove for the first electrode in an intermediate oxide layer. Highly doped zones of a first conduction type are located in edge regions of the source connection zone. Below the highly doped zones of the first conduction type, there are highly doped zones of a body zone with a complementary conduction type. In a central region of the source connection zone, the body zone has a net charge carrier concentration with a complementary conduction type which is lower than the charge carrier concentration in the edge regions of the source connection zone. | 04-02-2009 |
20090085104 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING - A method for manufacturing a semiconductor device includes providing a semiconductor substrate including a first surface and a second surface which is arranged opposite to the first surface. The semiconductor substrate includes a plurality of trench structures extending from the first surface into the semiconductor substrate. The thickness of the semiconductor substrate is then reduced by removing semiconductor material at the second surface to obtain a processed second surface with exposed bottom portions of the trench structures. At least a first mask is formed on the processed second surface in a self-aligned manner with respect to the bottom portions of the trench structures, and doping regions are formed in the semiconductor substrate between the trench structures. | 04-02-2009 |
20090085105 | TRENCH MOSFET AND METHOD OF MANUFACTURE UTILIZING TWO MASKS - A method for manufacturing a trench MOSFET semiconductor device comprises: providing a heavily doped N+ silicon substrate; forming an N type epitaxial layer; forming a thick SiO2 layer; creating P body and source area formations by ion implantation without any masks; utilizing a first mask to define openings for a trench gate and a termination; thermally growing a gate oxide layer followed by formation of a thick poly-Silicon refill layer without a mask to define a gate bus area; forming sidewall spacers; forming P+ areas; removing the sidewall spacers; depositing tungsten to fill contacts and vias; depositing a first thin barrier metal layer; depositing a first thick metal layer; utilizing a second metal mask to open a gate bus area; forming second sidewall spacers; depositing a second thin barrier metal layer; depositing a second thick metal layer; and planarizing at least the second thick metal layer and the second thin metal layer to isolate the source metal portions from gate metal portions, whereby the trench MOSFET semiconductor device is manufactured utilizing only first and second masks. | 04-02-2009 |
20090085106 | Semiconductor device and semiconductor device manufacturing method - A semiconductor device having a low on resistance and high integration level with respect to the surface area of a substrate is provided. In the semiconductor device, a first trench, a second trench, and a third trench are provided in an element formation region provided on a semiconductor substrate. Metal is deposited within the first trench and second trench, to form a drain electrode and a source electrode, respectively. Polysilicon is deposited inside the third trench with a gate insulating film intervening, and a gate electrode is formed. | 04-02-2009 |
20090090967 | MOSFET ACTIVE AREA AND EDGE TERMINATION AREA CHARGE BALANCE - A method for fabricating a MOSFET having an active area and an edge termination area is disclosed. The method includes forming a first plurality of implants at the bottom of trenches located in the active area and in the edge termination area. A second plurality of implants is formed at the bottom of the trenches located in the active area. The second plurality of implants formed at the bottom of the trenches located in the active area causes the implants formed at the bottom of the trenches located in the active area to reach a predetermined concentration. In so doing, the breakdown voltage of both the active and edge termination areas can be made similar and thereby optimized while maintaining advantageous RDson. | 04-09-2009 |
20090101970 | Semiconductor Device and Method for Manufacturing the Same - A method for manufacturing a semiconductor device including a vertical cell transistor structure may include forming a vertical cell transistor structure over a semiconductor substrate of a cell region; forming an insulating film over the vertical cell transistor structure; planarizing the insulating film to expose a hard mask film disposed at a top portion of the vertical cell transistor structure; and forming a storage node contact by removing the hard mask film. | 04-23-2009 |
20090101971 | SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, AND DATA PROCESSING SYSTEM - A bottom of a gate trench has a first bottom relatively far from an STI and a second bottom relatively near from the STI A portion, in an active region, configuring the second bottom of the gate trench configures a side-wall channel region, and has a thin-film SOI structure sandwiched between the gate electrode and the STI. On the other hand, a portion configuring the first bottom of the gate trench functions as a sub-channel region. A curvature radius of the second bottom is larger than a curvature radius of the first bottom. In an approximate center in a width direction of the gate trench, a bottom of a trench is approximately flat, and on the other hand, in ends of the width direction, a nearly whole bottom of the trench is curved. | 04-23-2009 |
20090108342 | SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE - A semiconductor component that includes a field plate and a semiconductor device and a method of manufacturing the semiconductor component. A semiconductor material includes an epitaxial layer disposed on a semiconductor substrate. A trench having an upper portion and a lower portion is formed in the epitaxial layer. A portion of a field plate is formed in the lower portion of the trench, wherein the field plate is electrically isolated from trench sidewalls. A gate structure is formed in the upper portion of the trench, wherein a gate oxide is formed from opposing sidewalls of the trench. Gate electrodes are formed adjacent to the gate oxide formed from the opposing sidewalls and a dielectric material is formed adjacent to the gate electrode. Another portion of the field plate is formed in the upper portion of the trench and cooperates with the portion of the field plate formed in the lower portion of the trench to form the field plate. | 04-30-2009 |
20090108343 | SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE - A semiconductor component that includes a field plate and a semiconductor device and a method of manufacturing the semiconductor component. A semiconductor material includes an epitaxial layer disposed on a semiconductor substrate. Field plate trenches extend into the semiconductor material and field plates are formed in the field plate trenches. A gate trench is formed between two adjacent field plate trenches and another gate trench is formed adjacent one of the field plate trenches. Gate structures are formed in the gate trenches, wherein each gate structure includes a gate oxide and a gate conductor. A conductor electrically couples the field plates together. | 04-30-2009 |
20090108344 | SEMICONDUCTOR APPARATUS - The present invention provides a semiconductor apparatus having high reliability with respect to a withstand voltage, leakage characteristics, etc. by disposing a structure of preventing stress occurring by metal wiring from directly acting on a trench relating to the semiconductor apparatus having a trench gate. The semiconductor apparatus of the invention includes a semiconductor substrate including a semiconductor layer having a predetermined impurity concentration, a trench gate formed in the semiconductor layer by filling a stripe-shaped trench by a conductor layer on which surface and interface a gate oxide film is formed, an insulating film covering a surface of the semiconductor layer and having a source contact opening, a source region formed in the semiconductor layer, a source electrode formed on the surface of the semiconductor layer so as to electrically connect to the source region through the source contact opening, a gate peripheral wiring connected to the trench gate at a peripheral edge part of the trench gate, a gate electrode separately formed from the source electrode, formed above the surface of the semiconductor layer and connected to the gate peripheral wiring and a drain electrode formed on an surface of the semiconductor substrate opposite to the surface of the semiconductor layer, wherein the trench gate is formed so as to avoid a corner portion of the source contact opening of the source electrode. | 04-30-2009 |
20090114982 | Semiconductor device and manufacturing method thereof - A disclosed semiconductor device provided with a power MOSFET includes: a semiconductor substrate constituting a drain; a trench formed on a surface of the semiconductor substrate; a gate electrode in the trench; a body diffusion layer on a surface side of the semiconductor substrate, the body diffusion layer being positioned adjacently to the trench and formed shallower than the trench; a source diffusion layer on the surface of the semiconductor substrate; a first interlayer insulating film formed on the gate electrode; and a source electrode film made of a metallic material and formed on the semiconductor substrate. A top surface of the gate electrode and a top surface of the first interlayer insulating film are formed in a recessed manner in the trench relative to the surface of the semiconductor substrate, and a surface portion of the semiconductor substrate for the trench is formed into a tapered shape. | 05-07-2009 |
20090121285 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor layer, a first semiconductor region provided on a major surface of the semiconductor layer, a second semiconductor region provided in a surface portion of the first semiconductor region, a trench extending through the second semiconductor region and the first semiconductor region to the semiconductor layer, a first insulating film provided on an inner wall of the trench, a third semiconductor region filling the trench below an interface between the semiconductor layer and the first semiconductor region, a second insulating film provided on the third semiconductor region, a gate electrode filling the trench above the second insulating film. A portion of the first insulating film in contact with the semiconductor layer is opened. The semiconductor layer is in contact with the third semiconductor region through the opened portion. | 05-14-2009 |
20090127615 | Semiconductor device and method for manufacture - A semiconductor device is formed by forming a second trench | 05-21-2009 |
20090127616 | POWER SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A vertical power semiconductor device includes a first semiconductor layer of a first conductivity type formed in both a cell section and a termination section, the termination section surrounding the cell section, a second semiconductor layer of a second conductivity type formed on the first semiconductor layer in the cell section, a third semiconductor layer of the first conductivity type formed in part on the second semiconductor layer, and a guard ring layer of the second conductivity type formed on the first semiconductor layer in the termination section. Net impurity concentration in the guard ring layer is generally sloped so as to be relatively high on its lower side and relatively low on its upper side. Alternatively, the net impurity concentration in the guard ring layer is constant. | 05-21-2009 |
20090127617 | Trench mosfet and manufacturing method thereof - This invention relates to a trench MOSFET, which can lower parasitic capacitance, thereby increasing a switching speed, and to a method of manufacturing the trench MOSFET. The trench MOSFET includes a substrate having an epi layer and a body layer sequentially formed thereon, a trench formed vertically in the central portion of the epi layer and the body layer, a first gate oxide film formed on the inner wall of the trench, a diffusion oxide film formed in the epi layer between the lower surface of the trench and the upper surface of the substrate to have a thickness greater than a thickness of the first gate oxide film and a width greater than a width of the trench, a gate formed in the trench having the first gate oxide film, a second gate oxide film formed on the gate, and a source region formed at both sides of the upper portion may be of the gate, thus reducing the generation of parasitic capacitance between the epi layer corresponding to a drain region and the gate, thereby improving a switching speed. | 05-21-2009 |
20090127618 | MULTI-FIN FIELD EFFECT TRANSISTOR - A multi-fin field effect transistor includes a substrate, an oxide layer, a conductive layer, a gate oxide layer, and a doped region. The substrate is surrounded by a trench, and there are at least two fin-type silicon layers formed in the substrate in a region prepared to form a gate thereon. The oxide layer is disposed in the trench and the top surface of the oxide layer is lower than that of the fin-type silicon layers. The conductive layer is disposed in the region prepared to form a gate. The top surface of the conductive layer is higher than that of the fin-type silicon layers. The gate oxide layer is disposed between the conductive layer and the fin-type silicon layers and disposed between the conductive layer and the substrate. The doped region is disposed in the substrate on both sides of the conductive layer. | 05-21-2009 |
20090140329 | Semiconductor Device - A semiconductor device (such as a MOSFET) can prevent a lowering in the reliability of a gate insulating film and can cope with a finer trench pattern. The MOSFET has a plurality of trenches penetrating a p | 06-04-2009 |
20090140330 | Semiconductor device and method of manufacturing semiconductor device - The semiconductor device according to the present invention includes a semiconductor layer, a trench formed by digging the semiconductor layer from the surface thereof, a gate insulating film formed on the inner surface of the trench, and a gate electrode made of silicon embedded in the trench through the gate insulating film. The gate electrode has a high-conductivity portion formed to cover the gate insulating film with a relatively high conductivity and a low-conductivity portion formed on a region inside the high-conductivity portion with a relatively low conductivity. | 06-04-2009 |
20090140331 | METHOD OF FABRICATING HIGH VOLTAGE DEVICE - A method of fabricating a high voltage device by which an area due to isolation between a source and a drain can be reduced by planarizing a gate in forming a symmetric high voltage device having vertical-type drift regions. Accordingly, the gate is formed in a trench at a height lower than an oxide spacer to reduce an area for isolation between source and drain. | 06-04-2009 |
20090140332 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device and a method of fabricating the same includes a groove formed in a semiconductor substrate, a gate electrode formed in the groove, source/drain regions disposed adjacent sidewalls of the gate electrode, and spacers interposed between the gate electrode and the source/drain regions such that the uppermost surface of the source/drain regions, the uppermost surface of the gate electrode and the uppermost surface of the spacers are formed on the same plane. | 06-04-2009 |
20090152624 | INTEGRATED CIRCUIT DEVICE WITH A SEMICONDUCTOR BODY AND METHOD FOR THE PRODUCTION OF AN INTEGRATED CIRCUIT DEVICE - An integrated circuit device with a semiconductor body and a method for the production of a semiconductor device a provided. The semiconductor body comprises a cell field with a drift zone of a first conduction type. In addition, the semiconductor device comprises an edge region surrounding the cell field. Field plates with a trench gate structure are arranged in the cell field, and an edge trench surrounding the cell field is provided in the edge region. The front side of the semiconductor body is in the edge region provided with an edge zone of a conduction type complementing the first conduction type with doping materials of body zones of the cell field. The edge zone of the complementary conduction type extends both within and outside the edge trench. | 06-18-2009 |
20090152625 | Recessed channel transistor - A recessed channel transistor includes a single crystalline silicon substrate having a recessed portion, a bottom surface of the recessed portion including an elevated central portion, a channel doping region in the single crystalline silicon substrate, the channel doping region being under the bottom surface of the recessed portion, a gate structure in the recessed portion, and source/drain regions in the single crystalline silicon substrate at both sides of the recessed portion, the source/drain regions being spaced apart from the bottom surface of the recessed portion. | 06-18-2009 |
20090166728 | Structure and Method for Forming Shielded Gate Trench FET with Multiple Channels - A field effect transistor (FET) includes a pair of trenches extending into a semiconductor region. Each trench includes a first shield electrode in a lower portion of the trench and a gate electrode in an upper portion of the trench over but insulated from the shield electrode. First and second well regions of a first conductivity type laterally extend in the semiconductor region between the pair of trenches and abut sidewalls of the pair of trenches. The first and second well regions are vertically spaced from one another by a first drift region of a second conductivity type. The gate electrode and the first shield electrode are positioned relative to the first and second well regions such that a channel is formed in each of the first and second well regions when the FET is biased in the on state. | 07-02-2009 |
20090166729 | POWER SEMICONDUCTOR HAVING A LIGHTLY DOPED DRIFT AND BUFFER LAYER - A power semiconductor element having a lightly doped drift and buffer layer is disclosed. One embodiment has, underneath and between deep well regions of a first conductivity type, a lightly doped drift and buffer layer of a second conductivity type. The drift and buffer layer has a minimum vertical extension between a drain contact layer on the adjacent surface of a semiconductor substrate and the bottom of the deepest well region which is at least equal to a minimum lateral distance between the deep well regions. The vertical extension can also be determined such that a total amount of dopant per unit area in the drift and buffer layer is larger then a breakdown charge amount at breakdown voltage. | 07-02-2009 |
20090166730 | SiC semiconductor device having bottom layer and method for manufacturing the same - A SiC semiconductor device includes: a substrate; a drift layer on the substrate; a trench on the drift layer; a base region in the drift layer sandwiching the trench; a channel between the base region and the trench; a source region in the base region sandwiching the trench via the channel; a gate electrode in the trench via a gate insulation film; a source electrode coupled with the source region; a drain electrode on the substrate opposite to the drift layer; and a bottom layer under the trench. An edge portion of the bottom layer under a corner of a bottom of the trench is deeper than a center portion of the bottom layer under a center portion of the bottom of the trench. | 07-02-2009 |
20090166731 | VERTICAL-TYPE FIELD-EFFECT TRANSISTOR AND MANUFACTURING METHOD THEREOF - A vertical-type FET includes: a semiconductor layer having a plurality of trenches; a gate electrode partially embedded in the trenches; and a base region and a source region that are formed in the semiconductor layer between adjacent trenches. The gate electrode includes: a plurality of first gate structures respectively formed in the plurality of trenches, wherein each first gate structure has a protruding portion protruding from the trench and an embedded portion embedded in the trench; and a second gate structure formed to connect between the protruding portions of adjacent first gate structures. The embedded portion is formed on a side wall of the trench through a first insulating film. The second gate structure is formed on the source region through a second insulating film thicker than the first insulating film. | 07-02-2009 |
20090166732 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device according to an embodiment of the present invention has a transistor section which includes a trench gate type transistor, and a gate line section which includes a part provided between transistor sections. The device includes a semiconductor substrate, a semiconductor layer formed on the semiconductor substrate, a base layer formed in the semiconductor layer, and provided with trenches in the transistor section and the gate line section, the trenches in the transistor section extending in a first direction parallel to a direction in which the transistor extends, the trenches in the bit line section extending in a second direction perpendicular to the first direction, and the trenches in the transistor section penetrating the base layer to reach the semiconductor layer, a source layer formed in the semiconductor layer in the transistor section, the source layer being located on the base layer, a gate insulator formed on surfaces of the base layer and the semiconductor layer exposed to the trenches in the transistor section and the gate line section, and on an upper surface of the base layer between the trenches in the gate line section, a gate line layer formed on the gate insulator, and including a part buried in the trenches in the transistor section, an inter layer dielectric formed on the gate line layer, and a source line layer formed on the inter layer dielectric, and electrically connected to the source layer in the transistor section. | 07-02-2009 |
20090166733 | Semiconductor Device and Manufacturing Method Thereof - A method of manufacturing a semiconductor device including forming a first conductive-type buried layer in a substrate; forming a first conductive-type drift area on the first conductive-type buried layer; forming a gate insulating layer and gate electrodes by selectively removing the first conductive-type drift area; forming a first oxide layer on the substrate and gate electrodes; implanting second conductive-type impurity ions into the substrate; forming a nitride layer on the first oxide layer; forming a second conductive-type well by diffusing the second conductive-type impurity ions while forming a second oxide layer; removing the nitride layer, the second oxide layer, and portions of the first oxide layer; forming first conductive-type source areas at sides of the gate electrode(s); forming a dielectric layer on the oxide layer; forming a trench in the dielectric layer and the oxide layer; forming a source contact in the trench; and forming a drain. | 07-02-2009 |
20090173993 | Structure and Method of Forming a Topside Contact to a Backside Terminal of a Semiconductor Device - A vertically conducting semiconductor device includes a semiconductor substrate having a topside surface and a backside surface. The semiconductor substrate serves as a terminal of the vertically conducting device for biasing the vertically conducting device during operation. An epitaxial layer extends over the topside surface of the semiconductor substrate but terminates prior to reaching an edge of the semiconductor substrate so as to form a recessed region along a periphery of the semiconductor substrate. An interconnect layer extends into the recessed region but terminates prior to reaching an edge of the semiconductor substrate. The interconnect layer electrically contacts the topside surface of the semiconductor substrate in the recessed region to thereby provide a topside contact to the semiconductor substrate. | 07-09-2009 |
20090173994 | RECESS GATE TRANSISTOR - A recess gate of a semiconductor device is provided, comprising: a substrate having a recess formed therein; a metal layer formed at the bottom of the recess; a polysilicon layer formed over the metal layer; and a source region and a drain region formed adjacent to the polysilicon layer and spaced from the metal layer. A method of forming a semiconductor device is also provided, comprising forming a substrate and a source and drain layer; forming a recess and depositing a gate insulation layer therein; forming a first conductive layer on the gate insulation layer; forming a first conductive layer pattern by recessing the first conductive layer; forming a second conductive layer on the first conductive layer pattern; forming a second conductive layer pattern by patterning the second conductive layer to overlap the source and drain layer; depositing an insulating layer on the second conductive layer pattern and the source and drain layer; and planarizing the insulating layer to form a cap on the second conductive layer pattern. | 07-09-2009 |
20090173995 | TRENCH SEMICONDUCTOR DEVICE OF IMPROVED VOLTAGE STRENGTH, AND METHOD OF FABRICATION - A trench IGBT is disclosed which includes a semiconductor substrate having formed therein a set of cell trenches formed centrally and a set of annular guard trenches concentrically surrounding the cell trenches. The cell trenches receive cell trench conductors via cell trench insulators for providing IGBT cells. The guard trenches receive guard trench conductors via guard trench insulators for enabling the IGBT to withstand higher voltages through mitigation of field concentrations. Capacitive coupling conductors overlie the guard trench conductors via a dielectric layer, each for capacitively coupling together two neighboring ones of the guard trench conductors. The capacitive coupling conductors are easily adjustably variable in shape, size and placement relative to the guard trench conductors for causing the individual guard trench conductors to possess potentials for an optimal contour of the depletion layer. | 07-09-2009 |
20090173996 | Recess Gate Type Transistor - A semiconductor device having recess gates and a method for fabricating the same. The semiconductor device includes a semiconductor substrate having inverse triangular recesses formed therein; a gate insulating film having a designated thickness formed on the semiconductor substrate; gate electrodes formed on the gate insulating film so that the gate electrodes fill the inverse triangular recesses and protrude from the surface of the semiconductor substrate; and first and second junction regions formed in the semiconductor substrate and opposed to each other so that the corresponding one of the gate electrodes is interposed therebetween. | 07-09-2009 |
20090179259 | SEMICONDUCTOR DEVICE WITH (110)-ORIENTED SILICON - A method of forming a semiconductor device on a heavily doped P-type (110) semiconductor layer over a metal substrate includes providing a first support substrate and forming a P-type heavily doped (110) silicon layer overlying the first support substrate. At least a top layer of the first support substrate is removable by a selective etching process with respect to the P-type heavily doped (110) silicon layer. A vertical semiconductor device structure is formed in and over the (110) silicon layer. The vertical device structure includes a top metal layer and is characterized by a current conduction in a <110> direction. The method includes bonding a second support substrate to the top metal layer and removing the first support substrate using a mechanical grinding and a selective etching process to expose a surface of the P-type heavily doped (110) silicon layer and to allow a metal layer to be formed on the surface | 07-16-2009 |
20090179260 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device, includes: forming a first and a second trench regions adjacent from each other in a first conductivity type semiconductor base; forming a second conductivity type semiconductor region in the semiconductor base between the first and second trench regions; forming a mask on the second conductivity type semiconductor region, the mask covering a central portion between the first and second trench regions; performing ion implantation of a first conductivity type impurity in the second conductivity type semiconductor region with the mask to form a first conductivity type first region and a first conductivity type second region separated from the first conductivity type first region; and performing heat treatment to diffuse the impurity in the first and second regions and to form a connection region between the first and second regions, connection region being shallower than the first and second regions after the heat treatment. | 07-16-2009 |
20090179261 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - Provided is a manufacturing method of a semiconductor device wherein the generation of voids is prevented in aluminum-based electrodes or the like. The method is suitable for manufacturing a semiconductor device adapted for vehicles, which is required to have a high reliability. However, it is very difficult that power semiconductor devices such as power MOSFETs, in particular, trench gate type power MOS devices are formed without having any void since the thickness of aluminum-based electrodes thereof is as large as about 3500 to 5500 nm (2.5 μm or more). In the present invention, a method is provided wherein at the time of forming an aluminum-based electrode metal film positioned over a wafer and having a thickness of 2.5 μm or more over a highland/lowland-repeated region in a line and space form by sputtering, the temperature of the wafer is set to 400° C. or higher and lower than 500° C. | 07-16-2009 |
20090189218 | Structure and Method for Forming Power Devices with High Aspect Ratio Contact Openings - A field effect transistor (FET) includes body regions of a first conductivity type over a semiconductor region of a second conductivity type. Source regions of the second conductivity type extend over the body regions. Gate electrodes extend adjacent to but are insulated from the body regions by a gate dielectric layer. Contact openings extend into the body regions between adjacent gate electrodes. A seed layer extends along the bottom of each contact opening. The seed layer serves as a nucleation site for promoting growth of conductive fill material. A conductive fill material fills a lower portion of each contact opening. An interconnect layer fills an upper portion of each contact opening and is in direct contact with the conductive fill material. The interconnect layer is also in direct contact with corresponding source regions along upper sidewalls of the contact openings. | 07-30-2009 |
20090194811 | Structure and Method for Forming Field Effect Transistor with Low Resistance Channel Region - A trench-gate field effect transistor includes trenches extending into a silicon region of a first conductivity type, and a gate electrodes in each trench. Body regions of second conductivity type extend over the silicon region between adjacent trenches. Each body region forms a first PN junction with the silicon region, and each body region includes a silicon-germanium layer of the second conductivity type laterally extending between adjacent trenches. Source regions of the first conductivity flank the trenches, and each source region forms a second PN junction with one of the body regions. Channel regions extend in the body regions along sidewalls of the trenches between the source regions and a bottom surface of the body regions. The silicon-germanium layers extend into corresponding channel regions to thereby reduce the channel resistance. | 08-06-2009 |
20090194812 | Structure for Making a Top-side Contact to a Substrate - A semiconductor structure includes a starting semiconductor substrate having a recessed portion. A semiconductor material is formed in the recessed portion and has a higher resistivity than the starting semiconductor substrate. A body region extends in the semiconductor material, and has a conductivity type opposite that of the semiconductor material. Source regions extend in the body region, and have a conductivity type opposite that of the body region. A gate electrode extends adjacent to but is insulated from the body region. A first interconnect layer extends over and is in contact with a non-recessed portion of the starting semiconductor substrate. The first interconnect layer and the non-recessed portion provide a top-side electrical contact to portions of the starting semiconductor substrate underlying the semiconductor material. | 08-06-2009 |
20090194813 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - The semiconductor device comprises a word line and a bit line. The word line comprises a gate electrode and a first metal interconnect. The first metal interconnect has contact with the gate electrode and extends into a region upper than a first impurity-diffused region in a first direction. The bit line comprises a connecting part and a second metal interconnect. The connecting part is formed so as to have contact with at least part of the side surface of the first impurity-diffused region. The second metal interconnect has contact with the connecting part and extends into a region lower than the semiconductor region in a second direction orthogonal to the first direction. | 08-06-2009 |
20090200605 | Metal-Oxide-Semiconductor Device Including an Energy Filter - A MOS device includes first and second source/drains spaced apart relative to one another. A channel is formed in the device between the first and second source/drains. A gate is formed in the device between the first and second source/drains and proximate the channel, the gate being electrically isolated from the first and second source/drains and the channel. The gate is configured to control a conduction of the channel as a function of a potential applied to the gate. The MOS device further includes an energy filter formed between the first source/drain and the channel. The energy filter includes an impurity band operative to control an injection of carriers from the first source/drain into the channel. | 08-13-2009 |
20090200606 | Power Device Edge Termination Having a Resistor with One End Biased to Source Voltage - A field effect transistor (FET) includes a source electrode for receiving an externally-provided source voltage. The FET further includes an active region and a termination region surrounding the active region. A resistive element is coupled to the termination region, wherein upon occurrence of avalanche breakdown in the termination region an avalanche current starts to flow in the termination region, and the resistive element is configured to induce a portion of the avalanche current to flow through the termination region and a remaining portion of the avalanche current to flow through the active region. During operation, one end of the resistive element is biased to the source voltage. | 08-13-2009 |
20090206397 | Lateral Trench MOSFET with Conformal Depletion-Assist Layer - A lateral trench DMOS device formed in a substrate of a first conductivity type includes a vertical trench lined with a dielectric layer and containing a gate electrode. A source region of a second conductivity is adjacent the surface of the substrate and a sidewall of the trench. A drain region of the second conductivity type is adjacent the surface of the substrate and spaced apart from the source region. A field oxide region is disposed at the surface of the substrate between the source region and the drain region and a drift region of the second conductivity type extends laterally from the trench sidewall to the drain region. A body region of a first conductivity type is disposed between the source region and the drift region, the body region adjacent the trench sidewall where the body region has a profile that is conformal to the field oxide region. | 08-20-2009 |
20090206398 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SEMICONDUCTOR DEVICE - A semiconductor device including an n-type semiconductor substrate, a p-type channel region and a junction layer provided between the n-type semiconductor substrate and the p-type channel region is disclosed. The junction layer has n-type drift regions and p-type partition regions alternately arranged in the direction in parallel with the principal surface of the n-type semiconductor substrate. The p-type partition region forming the junction layer is made to have a higher impurity concentration than the n-type drift region. This enables the semiconductor device to have an enhanced breakdown voltage and, at the same time, have a reduced on-resistance. | 08-20-2009 |
20090206399 | METHOD OF FORMING A RECESS CHANNEL TRENCH PATTERN, AND FABRICATING A RECESS CHANNEL TRANSISTOR - A method of forming a recess channel trench pattern for forming a recess channel transistor is provided. A mask layer is formed on a semiconductor substrate, which is then patterned to expose an active region and a portion of an adjacent device isolating layer with an isolated hole type pattern. Using this mask layer the semiconductor substrate and the device isolating layer portion are selectively and anisotropically etched, thereby forming a recess channel trench with an isolated hole type pattern. The mask layer may be patterned to be a curved line type. In this case, the once linear portion is curved to allow the device isolating layer portion exposed by the patterned mask layer to be spaced apart from an adjacent active region. The semiconductor substrate and the device isolating layer portion are then etched, thereby forming a recess channel trench with a curved line type pattern. | 08-20-2009 |
20090212358 | Semiconductor device and a method of manufacturing the same - A technology is provided to reduce ON-resistance, and the prevention of punch through is achieved with respect to a trench gate type power MISFET. Input capacitance and a feedback capacitance are reduced by forming a groove in which a gate electrode is formed so as to have a depth as shallow as about 1 μm or less, a p | 08-27-2009 |
20090218616 | TRANSISTOR HAVING VERTICAL CHANNEL AND METHOD FOR FABRICATING THE SAME - A semiconductor device including vertical channel transistor and a method for forming the transistor, which can significantly decrease the resistance of a word line is provided. A vertical channel transistor includes a substrate including pillars each of which has a lower portion corresponding to a channel region. A gate insulation layer is formed over the substrate including the pillars. A metal layer having a low resistance is used for forming a surrounding gate electrode to decrease resistance of a word line. A barrier metal layer is formed between a gate insulation layer and a surrounding gate electrode so that deterioration of characteristics of the insulation layer is prevented. A world line is formed connecting gate electrodes formed over the barrier layer to surround the lower portion of each pillar. | 09-03-2009 |
20090218617 | SUPERJUNCTION POWER SEMICONDUCTOR DEVICE - A superjunction power semiconductor device which includes spaced drift regions each extending from the bottom of a respective gate trench to the substrate of the device. | 09-03-2009 |
20090224314 | SEMICONDUCTOR DEVICE AND THE METHOD OF MANUFACTURING THE SAME - A power MOSFET exhibits a high breakdown voltage and low ON-state resistance. The device includes a trench formed in a semiconductor substrate, a gate electrode located along a side wall of the trench and a bottom wall of the trench near a side wall thereof, a pillar section, a first drain region of a first conductivity type in the pillar section, a base region of a second conductivity type in contact with the side wall of the trench in a bottom portion thereof and the bottom wall of the trench, a source region of the first conductivity type in a surface portion of the base region, a RESURF region of the second conductivity type in the pillar section, the RESURF region being formed in contact with the first drain region; and a second drain region of the first conductivity type in a side wall surface portion of the pillar section. | 09-10-2009 |
20090230464 | SEMICONDUCTOR DEVICE INCLUDING TRENCH GATE TRANSISTOR AND METHOD OF FORMING THE SAME - A semiconductor device may include at least one active region that has at least one trench groove. A fin channel region is deposed in the active region and between the at least one trench groove and an isolation region of the semiconductor substrate. The gate insulating film is disposed on inside walls of the at least one trench groove. The gate electrode is disposed on the gate insulating film and in the at least one trench groove. The gate electrode is separated by the gate insulating film from the fin channel region. The source and drain regions are disposed in the active region, and are connected to the fin channel region. The junction of each of the source and drain regions with the semiconductor substrate is deeper than the bottom of the fin channel region. | 09-17-2009 |
20090230465 | Trench-Gate Field Effect Transistors and Methods of Forming the Same - A field effect transistor includes a body region of a first conductivity type over a semiconductor region of a second conductivity type. A gate trench extends through the body region and terminates within the semiconductor region. At least one conductive shield electrode is disposed in the gate trench. A gate electrode is disposed in the gate trench over but insulated from the at least one conductive shield electrode. A shield dielectric layer insulates the at lease one conductive shield electrode from the semiconductor region. A gate dielectric layer insulates the gate electrode from the body region. The shield dielectric layer is formed such that it flares out and extends directly under the body region. | 09-17-2009 |
20090236657 | IMPACT IONIZATION DEVICES AND METHODS OF MAKING THE SAME - Impact ionization devices including vertical and recessed impact ionization metal oxide semiconductor field effect transistor (MOSFET) devices and methods of forming such devices are disclosed. The devices require lower threshold voltage than conventional MOSET devices while maintaining a footprint equal to or less than conventional MOSFET devices. | 09-24-2009 |
20090242973 | SOURCE AND BODY CONTACT STRUCTURE FOR TRENCH-DMOS DEVICES USING POLYSILICON - A semiconductor device includes a gate electrode, a top source region disposed next to the gate electrode, a drain region disposed below the bottom of the gate electrode, a oxide disposed on top of the source region and the gate electrode, and a doped polysilicon spacer disposed along a sidewall of the source region and a sidewall of the oxide. Methods for manufacturing such device are also disclosed. | 10-01-2009 |
20090242974 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a plurality of trench patterns formed over a substrate; gate insulation layers formed over sidewalls of the trench patterns; gate electrodes formed over the trench patterns; line patterns coupling the gate electrodes; and source and drain regions formed in upper and lower portions of the substrate adjacent to the sidewalls of the trench patterns. | 10-01-2009 |
20090242975 | Vertical pillar transistor - A vertical pillar transistor may include a plurality of lower pillars, a plurality of upper pillars, a first insulation part, a second insulation part and a word line. The plurality of lower pillars protrudes substantially perpendicular to a substrate and is defined by a plurality of trenches. The plurality of lower pillars extends along a second direction and may be separated from each other along a first direction substantially perpendicular to the second direction. The plurality of upper pillars may be formed on the plurality of lower pillars. The plurality of upper pillars has a width substantially smaller than that of the plurality of lower pillars. The first insulation part has a substantially uniform thickness on a sidewall of each of the plurality of lower pillars. The second insulation part may be formed on the first insulation part to fill a gap between the adjacent upper pillars. The word line may be formed on the second insulation part and may extend between facing sidewalls of the adjacent pair of upper pillars along the first direction. | 10-01-2009 |
20090242976 | Semiconductor device - The semiconductor device of the present invention includes a first conductive type semiconductor layer; a second conductive type source region formed in a surface layer portion of the semiconductor layer; a groove formed by digging in the source region from a surface thereof; an insulating film laminated on the semiconductor layer to cover a surface of the semiconductor layer; a contact hole penetrating through the insulating film in a layer thickness direction at least at a position facing the groove; a wiring formed on the insulating film; and a contact plug embedded in the contact hole so that a bottom portion thereof enters the groove to electrically connect the wiring and the source. | 10-01-2009 |
20090242977 | SEMICONDUCTOR DEVICE AND DC-DC CONVERTER - A semiconductor device includes: a semiconductor substrate of a first conductivity type; a semiconductor region provided in the semiconductor substrate; a first trench formed in the semiconductor region; a second trench formed in the semiconductor substrate; a trench gate electrode provided in the first trench; and a trench source electrode provided in the second trench. The trench source electrode is shaped like a stripe and connected to the source electrode through its longitudinal portion. | 10-01-2009 |
20090242978 | Termination Structure for Power Devices - A semiconductor power device includes an active region configured to conduct current when the semiconductor device is biased in a conducting state, and a termination region along a periphery of the active region. The termination region includes a first silicon region of a first conductivity type extending to a first depth within a second silicon region of a second conductivity type, the first and second silicon regions forming a PN junction therebetween. The second silicon region has a recessed portion extending below the first depth and out to an edge of a die housing the semiconductor power device. The recessed portion forms a vertical wall at which the first silicon region terminates. A first conductive electrode extends into the recessed portion and is insulated from the second silicon region. | 10-01-2009 |
20090250749 | Methods of Forming Asymmetric Recesses and Gate Structures that Fill such Recesses and Related Methods of Forming Semiconductor Devices that Include such Recesses and Gate Structures - In a method of forming an asymmetric recess, an asymmetric recessed gate structure filling the asymmetric recess, a method of forming the asymmetric recessed gate structure, a semiconductor device having the asymmetric recessed gate structure and a method of manufacturing the semiconductor device, a semiconductor substrate is etched to form a first sub-recess having a first central axis. A second sub-recess is formed under the first sub-recess. The second sub-recess is in communication with the first sub-recess. The second sub-recess has a second central axis substantially parallel with the first central axis. The second central axis is spaced apart from the first central axis. | 10-08-2009 |
20090256194 | SEMICONDUCTOR DEVICE WITH REDUCED RESISTANCE OF BIT LINES AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device comprises buried bit lines which are formed to be brought into contact with drain areas of vertical pillar transistors. The buried bit lines are arranged along a first direction in a silicon substrate. The buried bit lines are formed of epi-silicon to reduce the resistance of the buried bit lines. | 10-15-2009 |
20090256195 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device in which current flows in a vertical direction includes a structure that decreases resistance between a source electrode and a drain electrode along with a current path at a position different from a position having highest electric field intensity between the source electrode and the drain electrode. | 10-15-2009 |
20090261408 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device includes a semiconductor substrate, a first diffusion region, a gate insulating film, a gate electrode, a second diffusion region and a contact plug. The semiconductor substrate includes a base and at least a pillar. The first diffusion region is disposed in the base. The gate insulating film covers a side surface of the pillar. The gate electrode is separated from the pillar by the gate insulating film. The second diffusion region is disposed in an upper portion of the pillar. The contact plug is connected to the second diffusion region. The contact plug is connected to the entirety of the top surface of the pillar. | 10-22-2009 |
20090267142 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - A semiconductor device according to the present invention includes a plurality of trenches, a plurality of gate electrodes, a plurality of diffusion Layers, an insulating film, an electrode layer, a plurality of first concave portions and a plurality second concave portions formed in the electrode layer, a solder layer, and an electrically conducting board. The gate electrode is located in each of the plurality of trenches. The plurality of diffusion layers is adjacent to the respective trenches. The insulating films are selectively formed on the respective gate electrodes. The first concave portions are located above spaces between the gate electrodes. The second concave portions are located between the first concave portions. The electrically conducting board is connected to the electrode layer through the solder layers. | 10-29-2009 |
20090273024 | METHOD FOR PRODUCING A TRANSISTOR COMPONENT HAVING A FIELD PLATE - A method for producing a transistor component having a field plate. One embodiment includes providing a semiconductor body having a first side, and including a first trench extending into the semiconductor body. A field plate dielectric layer is produced on the first side and at uncovered areas of the first trench such that a residual trench remains. A field plate layer is produced in the residual trench. The first side of the semiconductor body is uncovered using a polishing method. The field plate dielectric layer is partially removed from the at least one first trench proceeding from the first side. | 11-05-2009 |
20090273025 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - Disclosed herein are a semiconductor device and a method for manufacturing the same. The method includes forming a gate structure using a carbon nano tube (CNT). In order to prevent reduction of the gate resistance and the short channel effect, a CNT gate having a grown CNT pattern with a half-cylinder shape is formed over a recess of a semiconductor substrate. The CNT gate has the same effect as a recess gate, and can prevent the short channel effect, improve the speed, and the lower power characteristic of semiconductor devices. | 11-05-2009 |
20090273026 | TRENCH-GATE LDMOS STRUCTURES - MOSFET devices for RF applications that use a trench-gate in place of the lateral gate conventionally used in lateral MOSFET devices. A trench-gate provides devices with a single, short channel for high frequency gain. Embodiments of the present invention provide devices with an asymmetric oxide in the trench gate, as well as LDD regions that lower the gate-drain capacitance for improved RF performance. Refinements to these TG-LDMOS devices include placing a source-shield conductor below the gate and placing two gates in a trench-gate region. These improve device high-frequency performance by decreasing gate-to-drain capacitance. Further refinements include adding a charge balance region to the LDD region and adding source-to-substrate or drain-to-substrate vias. | 11-05-2009 |
20090278197 | MIS FIELD EFFECT TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME - The MIS field-effect transistor includes: a substrate; a nitride semiconductor multilayer structure portion formed on the substrate, including a first group III-V nitride semiconductor layer of a first conductivity type, a second group III-V nitride semiconductor layer of a second conductivity type stacked thereon and a third group III-V nitride semiconductor layer of the first conductivity type stacked thereon; a gate insulating film formed on a wall surface formed over the first, second and third group III-V nitride semiconductor layers to extend over these first, second and third group III-V nitride semiconductor layers; a gate electrode made of a conductive material formed as being opposed to the second group III-V nitride semiconductor layer via the gate insulating film; a drawn portion electrically connected to the first group III-V nitride semiconductor layer and drawn from the nitride semiconductor multilayer structure portion in a direction parallel to the substrate; a drain electrode formed in contact with the drawn portion; and a source electrode electrically connected to the third group III-V nitride semiconductor layer. | 11-12-2009 |
20090278198 | Deep source electrode MOSFET - A power semiconductor device that includes a plurality of source trenches that extend to a depth below the gate electrodes and a termination region that includes a termination trench that is as deep as the source trenches. | 11-12-2009 |
20090294843 | ENCLOSED VOID CAVITY FOR LOW DIELECTRIC CONSTANT INSULATOR - Field effect devices and ICs ( | 12-03-2009 |
20090294844 | SEMICONDUCTOR DEVICE - A semiconductor device has a substrate, a source region formed on the surface portion of the substrate, a first insulating layer formed on the substrate, a gate electrode formed on the first insulating layer, a second insulating layer formed on the gate electrode, a body section connected with the source region, penetrating through the first insulating layer, the gate electrode and the second insulating layer, and containing a void, a gate insulating film surrounding the body section, and formed between the body section and the gate electrode, and a drain region connected with the body section. | 12-03-2009 |
20090302379 | Semiconductor Device - A trench semiconductor device is provided which ensures a reduced turn-on time. The semiconductor device ( | 12-10-2009 |
20090302380 | Word Line to Bit Line Spacing Method and Apparatus - In one embodiment, a memory cell includes a bit line arranged in a semiconductor substrate and a bit line contact region arranged adjacent the bit line. A word line is arranged above the bit line contact region in a trench formed in the semiconductor substrate. A generally U-shaped insulating layer is arranged in a bottom region of the trench and separates the bit line and the bit line contact region from the word line. | 12-10-2009 |
20090315103 | TRENCH MOSFET WITH SHALLOW TRENCH FOR GATE CHARGE REDUCTION - A power MOS device includes shallow trench structure for reduction of gate charge. To counteract the increase of Rds may caused by decreasing the depth of trench, the power MOS device further includes an arsenic Ion Implantation area underneath each trench bottom when N+ red phosphorus substrate is applied, and the concentration of said arsenic doped area is higher than that of epitaxial layer. As the shallow trench is performed, the gate contact trench could be easily etched over to penetrate the gate oxide, which will lead to a shortage of tungsten plug filled in gate contact trench to epitaixial layer. To prevent from this problem, a terrace poly gate is designed in a preferred embodiment of present invention. By using this method, the gate contact trench is lifted to avoid the shortage problem. | 12-24-2009 |
20090315104 | Trench MOSFET with shallow trench structures - A trench MOSFET with shallow trench structure is disclosed. The improved structure resolves the problem of degradation of BV caused by the As Ion Implantation in termination surface and no additional mask is needed which further enhance the avalanche capability and reduce the manufacture cost. | 12-24-2009 |
20090321817 | Structure and Method for Forming a Shielded Gate Trench FET with an Inter-Electrode Dielectric Having a Nitride Layer Therein - A shielded gate field effect transistor (FET) comprises a plurality of trenches extending into a semiconductor region. A shield electrode is disposed in a bottom portion of each trench, and a gate electrode is disposed over the shield electrode in each trench. An inter-electrode dielectric (IED) extends between the shield electrode and the gate electrode. The IED comprises a first oxide layer and a nitride layer over the first oxide layer. | 12-31-2009 |
20090321818 | SEMICONDUCTOR COMPONENT WITH TWO-STAGE BODY ZONE - A semiconductor component with a two-stage body zone. One embodiment provides semiconductor component including a drift zone, and a compensation zone of a second conduction type. The compensation zone is arranged in the drift zone. A source zone and a body zone is provided. The body zone is arranged between the source zone and the drift zone. A gate electrode is arranged adjacent to the body zone. The body zone has a first body zone section and a second body zone section, which are adjacent to one another along the gate dielectric and of which the first body zone section is doped more highly than the second body zone section. | 12-31-2009 |
20090321819 | Semiconductor device having super junction - A semiconductor device includes: a first semiconductor layer; a PN column layer having first and second column layers; and a second semiconductor layer. Each of the first and second column layers includes first and second columns alternately arranged along with a horizontal direction. The first and second column layers respectively have first and second impurity amount differences defined at a predetermined depth by subtracting an impurity amount in the second column from an impurity amount in the first column. The first impurity amount difference is constant and positive. The second impurity amount difference is constant and negative. | 12-31-2009 |
20090321820 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCTION OF SEMICONDUCTOR DEVICE - Disclosed herein is a semiconductor device including: a gate electrode formed in a recess dug in the surface of a semiconductor substrate, with a gate insulating film interposed between the gate electrode and the semiconductor substrate; a source-drain diffusion layer formed on that surface of the semiconductor substrate which is adjacent to both sides of the gate electrode; and a stress applying layer which is formed deep from the surface of the semiconductor substrate in such a way as to cover the surface of the source-drain diffusion layer. | 12-31-2009 |
20090321821 | SEMICONDUCTOR DEVICE HAVING RECESS GATE AND METHOD OF FABRICATING THE SAME - A semiconductor device having a recess gate includes a semiconductor substrate having a recess, a conductive pattern for a gate electrode filled into the recess, and having an extension portion protruding higher than a surface of the semiconductor substrate, an epitaxial semiconductor layer having a top surface disposed over the semiconductor substrate, and a gate insulating layer disposed between the epitaxial semiconductor layer and the conductive pattern, and between the semiconductor substrate and the conductive pattern. Further, a method of fabricating the same is disclosed. | 12-31-2009 |
20100006928 | Structure and Method for Forming a Shielded Gate Trench FET with an Inter-electrode Dielectric Having a Low-k Dielectric Therein - A shielded gate trench field effect transistor (FET) comprises trenches extending into a semiconductor region. A shield electrode is disposed in a bottom portion of each trench. The shield electrode is insulated from the semiconductor region by a shield dielectric. A gate electrode is disposed in each trench over the shield electrode, and an inter-electrode dielectric (IED) comprising a low-k dielectric extends between the shield electrode and the gate electrode. | 01-14-2010 |
20100006929 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device contains a semiconductor substrate having a p-type semiconductor layer and an n-type channel layer formed thereon; gate trenches extended through the channel layer so as to reach the p-type semiconductor layer; oxide films formed over the bottom and inner wall of the gate trenches, the oxide films being formed thicker over the bottom of the gate trenches than over the inner wall; gate electrodes formed so as to fill the gate trenches; n-type regions formed at the bottom of the gate trenches, and containing arsenic as a major n-type impurity component; low concentration p-type regions formed under the n-type regions, and having a low p-type impurity concentration; and a drain electrode formed on the back surface of the substrate. | 01-14-2010 |
20100013009 | Structure and Method for Forming Trench Gate Transistors with Low Gate Resistance - A field effect transistor includes body regions of a first conductivity type over a semiconductor region of a second conductivity type such that the body regions form p-n junctions with the semiconductor region. Trenches extend through the body region and terminate within the semiconductor region. Source regions of the second conductivity type extend over the body regions adjacent the trenches such that the source regions form p-n junctions with the body regions. A gate dielectric layer lines sidewalls of each trench. A metal liner lines the gate dielectric layer in each trench. A gate electrode comprising metallic material is disposed in each trench. | 01-21-2010 |
20100019314 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE - Generally, a power MOSFET mainly includes an active region occupying most of an internal region (a region where a gate electrode made of polysilicon or the like is integrated), and a surrounding gate contact region (where the gate electrode made of polysilicon or the like is derived outside a source metal covered region to make contact with a gate metal) (see FIG. | 01-28-2010 |
20100019315 | SEMICONDUCTOR DEVICE HAVING A DEVICE ISOLATION TRENCH - A method for manufacturing a semiconductor device includes forming a semiconductor substrate to have a SOI structure by an epitaxial process for forming a gate while forming an insulating film pattern in a bottom where a device isolation trench is formed. The method thereby increases the process margin for forming a device isolation film and prevents the punch-through phenomenon to improve electrical characteristics of semiconductor devices and increase product yield. | 01-28-2010 |
20100019316 | Method of fabricating super trench MOSFET including buried source electrode - A method of fabricating a trench MOSFET, the lower portion of the trench containing a buried source electrode which is insulated from the epitaxial layer and semiconductor substrate but in electrical contact with the source region. When the MOSFET is in an “off” condition, the bias of the buried source electrode causes the “drift” region of the mesa to become depleted, enhancing the ability of the MOSFET to block current. The doping concentration of the drift region can therefore be increased, reducing the on-resistance of the MOSFET. The buried source electrode also reduces the gate-to-drain capacitance of the MOSFET, improving the ability of the MOSFET to operate at high frequencies. The substrate may advantageously include a plurality of annular trenches separated by annular mesas and a gate metal layer that extends outward from a central region in a plurality of gate metal legs separated by source metal regions. | 01-28-2010 |
20100025759 | TRENCH TYPE SEMICONDUCTOR DEVICE AND FABRICATION METHOD FOR THE SAME - The trench type semiconductor device includes a gate insulating film placed on the bottom surface and the sidewall surface of the trench formed from the surface of a first base layer; a gate electrode placed on the gate insulating film and fills up into a trench; an interlayer insulating film covering the gate electrode; a second base layer placed on the surface of the first base layer, and is formed more shallowly than the bottom surface of the trench; a source layer placed on the surface of the second base layer; a source electrode connected to the second base layer in the bottom surface of a self-aligned contact trench formed in the second base layer by applying the interlayer insulating film as a mask, and is connected to the source layer in the sidewall surface; a drain layer placed at the back side of the first base layer; and a drain electrode placed at the drain layer, for achieving the minute structure by the self-alignment, reducing the on resistance, and improving the breakdown capability, and providing a fabrication method for the same. | 02-04-2010 |
20100032751 | SUPER-SELF-ALIGNED TRENCH-DMOS STRUCTURE AND METHOD - A semiconductor device includes a P-body layer formed in an N-epitaxial layer; a gate electrode formed in a trench in the P-body and N-epitaxial layer; a top source region formed from the P-body layer next to the gate electrode; a gate insulator disposed along a sidewall of the gate electrode between the gate electrode and the source, between the gate electrode and the P-body and between the gate electrode and the N-epitaxial layer; a cap insulator disposed on top of the gate electrode; and an N+ doped spacer disposed along a sidewall of the source and a sidewall of the gate insulator. The source includes N+ dopants diffused from the spacer. A body contact region containing P-type dopants is formed from the N-epitaxial layer. The contact region touches one or more P-doped regions of the P-body layer and the source. Methods for manufacturing such a device are also disclosed. Embodiments of this invention may also be applied to P-channel devices. | 02-11-2010 |
20100038710 | Vertical power MOSFET semiconductor apparatus having separate base regions and manufacturing method thereof - A semiconductor apparatus according to the present invention includes a first semiconductor layer of a first conductive type, a low concentration base region of a second conductive type formed on the first semiconductor layer, a gate electrode formed in a trench with insulating film on an inner surface of the trench that is formed to reach the first semiconductor layer from a surface of the low concentration base region, a source region of the first conductive type formed, contacting the insulating film, on a surface of the low concentration base region, a first high concentration base region, a second high concentration base region provided below and separated from the first concentration base region, and a third high concentration base region of the second conductive type included inside the low concentration base region, provided below and separated from the second high concentration base region. | 02-18-2010 |
20100044785 | HIGH ASPECT RATIO TRENCH STRUCTURES WITH VOID-FREE FILL MATERIAL - A field effect transistor (FET) includes a trench extending into a semiconductor region. A conductive electrode is disposed in the trench, and the conductive electrode is insulated from the semiconductor region by a dielectric layer. The conductive electrode includes a conductive liner lining the dielectric layer along opposite sidewalls of the trench. The conductive liner has tapered edges such that a thickness of the conductive liner gradually increases from a top surface of the conductive electrode to a point in lower half of the conductive electrode. The conductive electrode further includes a conductive fill material sandwiched by the conductive liner. The FET further includes a drift region of a first conductivity type in the semiconductor region, and a body region of a second conductivity type extending over the drift region. Source regions of the first conductivity type extend in the body region adjacent the trench. | 02-25-2010 |
20100044786 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor layer of a first conductivity type; a base region of a second conductivity type formed on a surface of the semiconductor layer of the first conductivity type; a plurality of first column regions of the second conductivity type formed in a matrix fashion in the semiconductor layer when seen in a plan view; a trench gate formed in a grid fashion in the semiconductor layer so that each of the first column regions is surrounded by the trench gate when seen in a plan view, the trench gate penetrating through the base region to reach the semiconductor layer of the first conductivity type; and a plurality of second column regions of the second conductivity type selectively formed below each intersection of the grid of the trench gate except line section of the trench gate. | 02-25-2010 |
20100052047 | SEMICONDUCTOR DEVICE AND METHOD FOR THE PRODUCTION OF A SEMICONDUCTOR DEVICE - The semiconductor device has a semiconductor body with a semiconductor device structure. The semiconductor device structure has a first electrode, a second electrode and a gate electrode. The gate electrode is designed to form a conductive channel region. An insulating layer at least partially surrounds the gate electrode. A semi-insulating layer is provided between the gate electrode and at least one of the first electrode and the second electrode. The semi-insulating layer is located outside the conductive channel region and has an interface state density which is greater than the quotient of the breakdown charge and the band gap of the material of the semiconductor body. | 03-04-2010 |
20100052048 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device and a method of manufacturing the same includes forming trenches in a semiconductor substrate, and then forming spacers composed of a first polysilicon layer in the trench, and then forming a second polysilicon layer over the spacers and filling the trench. Therefore, even in case of a power MOSFET device having a small line width and a high aspect ratio, generation of voids in the polysilicon when forming a gate is prevented, and thus, device reliability is enhanced. | 03-04-2010 |
20100059814 | SEMICONDUCTOR DEVICE HAVING VERTICAL CHARGE-COMPENSATED STRUCTURE AND SUB-SURFACE CONNECTING LAYER AND METHOD - In one embodiment, a semiconductor device is formed having vertical localized charge-compensated trenches, trench control regions, and sub-surface doped layers. The vertical localized charge-compensated trenches include at least a pair of opposite conductivity type semiconductor layers. The trench control regions are configured to provide a generally vertical channel region electrically coupling source regions to the sub-surface doped layers. The sub-surface doped layers are further configured to electrically connect the drain-end of the channel to the vertical localized charge compensation trenches. Body regions are configured to isolate the sub-surface doped layers from the surface of the device. | 03-11-2010 |
20100059815 | SEMICONDUCTOR TRENCH STRUCTURE HAVING A SEALING PLUG AND METHOD - In one embodiment, a semiconductor device is formed having a trench structure. The trench structure includes a single crystalline semiconductor plug formed along exposed upper surfaces of the trench. In one embodiment, the single crystalline semiconductor plug seals the trench to form a sealed core. | 03-11-2010 |
20100065904 | High density trench field effect transistor - A semiconductor structure comprises trenches extending into a semiconductor region. Portions of the semiconductor region extend between adjacent trenches forming mesa regions. A gate electrode is in each trench. Well regions of a first conductivity type extend in the semiconductor region between adjacent trenches. Source regions of a second conductivity type are in the well regions. Heavy body regions of the first conductivity type are in the well regions. The source regions and the heavy body regions are adjacent trench sidewalls, and the heavy body regions extend over the source regions along the trench sidewalls to a top surface of the mesa regions. | 03-18-2010 |
20100065905 | Structures and Methods for Reducing Dopant Out-diffusion from Implant Regions in Power Devices - A semiconductor structure comprises a drift region of a first conductivity type in a semiconductor region. A well region of a second conductivity type is over the drift region. A source region of the first conductivity type is in an upper portion of the well region. A heavy body region of the second conductivity type extends in the well region. The heavy body region has a higher doping concentration than the well region. A first diffusion barrier region at least partially surrounds the heavy body region. A gate electrode is insulated from the semiconductor region by a gate dielectric. | 03-18-2010 |
20100065906 | SYSTEM FOR VERTICAL DMOS WITH SLOTS - A device for providing a high power, low resistance, efficient vertical DMOS device is disclosed. The device comprises providing a semiconductor substrate with a source body structure thereon. The device further comprises a plurality of slots in the source/body structure and providing a metal within the plurality of slots to form a plurality of structures. A slotted PowerFET array is disclosed. This slotted approach results in a dense PowerFET, a low Ron due to the slotted design, an oxide isolated process without any due extra steps other than the slots, lower capacitance, lower leakage, smaller die, improved heat transfer, improved electro-migration, lower ground resistance, less cross talk, drops the isolation diffusion and the sinker diffusion, mostly low temperature processing and provides double metal with single metal processing. Also disclosed is a method for integrating this vertical DMOS with CMOS, bipolar and BCD to provide an optimized small, efficient die using the buried power buss approach and these technologies. | 03-18-2010 |
20100065907 | FIN FET AND METHOD OF FABRICATING SAME - A fin field effect transistor (fin FET) is formed using a bulk silicon substrate and sufficiently guarantees a top channel length formed under a gate, by forming a recess having a predetermined depth in a fin active region and then by forming the gate in an upper part of the recess. A device isolation film is formed to define a non-active region and a fin active region in a predetermined region of the substrate. In a portion of the device isolation film a first recess is formed, and in a portion of the fin active region a second recess having a depth shallower than the first recess is formed. A gate insulation layer is formed within the second recess, and a gate is formed in an upper part of the second recess. A source/drain region is formed in the fin active region of both sides of a gate electrode. | 03-18-2010 |
20100072541 | SEMICONDUCTOR DEVICE WITH INCREASED CHANNEL AREA AND DECREASED LEAKAGE CURRENT - The semiconductor device includes an active region, a recess channel region including vertical channel structures, a gate insulating film, and a gate structure. The active region is defined by a device isolation structure formed in a semiconductor substrate. The recess channel region is formed in the active region. The vertical silicon-on-insulator (SOI) channel structures are disposed at sidewalls of both device isolation structures in a longitudinal direction of a gate region. The gate insulating film is disposed over the active region including the recess channel region. The gate structure is disposed over the recess channel region of the gate region. | 03-25-2010 |
20100072542 | SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING THE SAME, AND DATA PROCESSING SYSTEM - Modification of an SOD film is promoted in a hot oxidizing atmosphere. Elements under a liner film and a semiconductor substrate are prevented from being damaged by oxidation. | 03-25-2010 |
20100078713 | SEMICONDUCTOR COMPONENT STRUCTURE WITH VERTICAL DIELECTRIC LAYERS - A method for producing a semiconductor structure and a semiconductor component are described. | 04-01-2010 |
20100078714 | TRENCH METAL OXIDE-SEMICONDUCTOR TRANSISTOR AND FABRICATION METHOD THEREOF - A fabrication method of a trench metal oxide-semiconductor (MOS) transistor is provided. After the gate trenches are formed in the epitaxial layer, impurities of a first conductive type are implanted into the epitaxial layer by using a blanket implantation process. A polysilicon pattern filling the gate trenches and covering a predetermined range of epitaxial layer surrounding the gate trenches is formed on the epitaxial layer. Impurities of a second conductive type are implanted through the polysilicon pattern into the epitaxial layer to form a well. Impurities of the first conductive type are implanted to form a plurality of first doping regions. A portion of the polysilicon layer above the upper surface of the epitaxial layer is removed by etching to form a plurality of polysilicon gates. Impurities in the first doping regions are driven in to form a plurality of source regions adjacent to the gate trenches. | 04-01-2010 |
20100078715 | LATERAL DMOS TRANSISTOR AND METHOD FOR FABRICATING THE SAME - A LDMOS transistor and a method for fabricating the same. A LDMOS transistor may include a P-type body region formed over a N-well. A LDMOS transistor may include a source region and a source contact region formed over a P-type body region. A LDMOS transistor may include a drain region spaced a distance from a P-type body region. A LOCOS may be formed over a surface of a N-well between a P-type body region and a drain region. A LDMOS transistor may include a main gate electrode formed over at least a portion of a LOCOS and a N-well. A LDMOS transistor may include a sub-gate electrode formed between a source region and a source contact region. A method for fabricating a LDMOS transistor is described herein. | 04-01-2010 |
20100078716 | Semiconductor component and method for producing a semiconductor component - A semiconductor component comprises a semiconductor body with at least one protective trench in the semiconductor body. An insulation layer is situated at least at the bottom of the protective trench. An electrically conductive layer having a thickness D is formed on the insulation layer in the protective trench, wherein the electrically conductive layer only partly fills the protective trench. | 04-01-2010 |
20100078717 | VERTICAL MOS TRANSISTOR AND METHOD THEREFOR - In one embodiment, a vertical MOS transistor is formed without a thick field oxide and particularly without a thick field oxide in the termination region of the transistor. | 04-01-2010 |
20100084704 | Devices Containing Permanent Charge - An edge termination structure includes a final dielectric trench containing permanent charge. The final dielectric trench is surrounded by first conductivity type semiconductor material (doped by lateral outdiffusion from the trenches), which in turn is laterally surrounded by second conductivity type semiconductor material. | 04-08-2010 |
20100084705 | SEMICONDUCTOR DEVICES HAVING REDUCED GATE-DRAIN CAPACITANCE AND METHODS FOR THE FABRICATION THEREOF - Embodiments of a method for fabricating a semiconductor device having a reduced gate-drain capacitance are provided. In one embodiment, the method includes the steps of etching a trench in a semiconductor substrate utilizing an etch mask, widening the trench to define overhanging regions of the etch mask extending partially over the trench, and depositing a gate electrode material into the trench and onto the overhanging regions. The gate electrode material merges between the overhanging regions prior to the filling of the trench to create an empty fissure within the trench. A portion of the semiconductor substrate is removed through the empty fissure to form a void cavity proximate the trench. | 04-08-2010 |
20100084706 | Power Semiconductor Devices and Methods of Manufacture - A method for forming power semiconductor devices having an inter-electrode dielectric (IPD) layer inside a trench includes providing a semiconductor substrate with a trench, lining the sidewalls and bottom of the trench with a first layer of dielectric material, filling the trench with a first layer of conductive material to form a first electrode, recessing the first layer of dielectric material and the first layer of conductive material to a first depth inside the trench, forming a layer of polysilicon material on a top surface of the dielectric material and conductive material inside the trench, oxidizing the layer of polysilicon material, and forming a second electrode inside the trench atop the oxidized layer and isolated from trench sidewalls by a second dielectric layer. The oxidation step can be enhanced by either chemically or physically altering the top portion polysilicon such as by implanting impurities. | 04-08-2010 |
20100084707 | Polysilicon control etch-back indicator - This invention discloses a semiconductor wafer for manufacturing electronic circuit thereon. The semiconductor substrate further includes an etch-back indicator that includes trenches of different sizes having polysilicon filled in the trenches and then completely removed from some of the trenches of greater planar trench dimensions and the polysilicon still remaining in a bottom portion in some of the trenches having smaller planar trench dimensions. | 04-08-2010 |
20100096692 | SEMICONDUCTOR DEVICE - A semiconductor device of the invention includes: a super junction structure of an n-type pillar layer and a p-type pillar layer; a base layer provided on the p-type pillar layer; a source layer selectively provided on a surface of the base layer; a gate insulating film provided on a portion being in contact with the base layer, a portion being in contact with the source layer and a portion being in contact with the n-type pillar layer on a portion of a junction between the n-type pillar layer and the p-type pillar layer; a control electrode provided opposed to the base layer, the source layer and the n-type pillar layer through the gate insulating film; and a source electrode electrically connected to the base layer, the source layer and the n-type layer. The source electrode is contact with the surface of the n-type pillar layer located between the control electrodes to form a Schottky junction. | 04-22-2010 |
20100102382 | TRENCH GATE TYPE TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - The invention provides a trench gate type transistor in which the gate leakage current is prevented and the gate capacitance is reduced. A trench is formed in an N− type semiconductor layer. A thin silicon oxide film is formed on a region of the N− type semiconductor layer for the active region of the transistor in the trench. On the other hand, a silicon oxide film which is thicker than the silicon oxide film is formed on a region not for the active region. Furthermore, a leading portion extending from inside the trench onto the outside thereof forms a gate electrode contacting the silicon oxide film. This provides a long distance between the gate electrode at the leading portion and the corner portion of the N− type semiconductor layer, thereby preventing the gate leakage current and reducing the gate capacitance. | 04-29-2010 |
20100102383 | Semiconductor device - An inventive semiconductor device includes: a body region of a second conductivity type provided on the drift region of a first conductivity type in a semiconductor layer; a trench extending from a surface of the body region in the semiconductor layer with its bottom located in the drift region; a gate electrode provided in the trench with the intervention of a gate insulation film; a source region of the first conductivity type provided in a surface layer portion of the body region; a first impurity region of the second conductivity type provided around the bottom of the trench in spaced relation from the body region; and a second impurity region of the second conductivity type provided on a lateral side of the body region in the semiconductor layer, the second impurity region being isolated from the body region and electrically connected to the first impurity region. | 04-29-2010 |
20100102384 | METAL OXIDE SEMICONDUCTOR (MOS) TRANSISTORS HAVING A RECESSED GATE ELECTRODE - A metal oxide semiconductor (MOS) includes an isolation layer disposed in a semiconductor substrate to define an active region. A source region and a drain region are disposed on both sides of the active region such that a first direction is defined from the source region to the drain region. A channel recess is disposed in the active region between the source and drain regions. The channel recess has a convex surface when viewed from a cross-sectional view taken along a second direction orthogonal to the first direction. A gate electrode fills the channel recess and crosses the active region in the second direction. A gate insulating layer is interposed between the gate electrode and the active region. | 04-29-2010 |
20100117144 | SEMICONDUCTOR DEVICE AND METHOD FOR THE PRODUCTION OF A SEMICONDUCTOR DEVICE - In one embodiment, a field effect transistor has a semiconductor body, a drift region of a first conductivity type and a gate electrode. At least one trench extends into the drift region. A field plate is arranged at least in a portion of the at least one trench. A dielectric material at least partially surrounds both the gate electrode and the field plate. The field plate includes a first semiconducting material. | 05-13-2010 |
20100117145 | Configuration of trenched semiconductor power device to reduce masked process - A semiconductor power device formed on a semiconductor substrate of a first conductivity type wherein the semiconductor power device includes trench gates surrounded by body regions of a second conductivity type encompassing source regions of the first conductivity type therein. The semiconductor power device further includes trench contact structure having a plurality of trench contacts with trenches extended into the body regions for as source-body contacts and extended into the trench gates as gate contact. The semiconductor power device further includes a termination area wherein a plurality of the trench gate contacts are electrically connected to the source-body contacts. | 05-13-2010 |
20100117146 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - There is provided a semiconductor device and a method for fabricating the same whose withstanding characteristic may be enhanced and whose ON resistance may be reduced. A MIS-type HEMT includes a carrier traveling layer made of a group-III nitride semiconductor and formed on a supporting substrate, a carrier supplying layer made of a group-III nitride semiconductor and formed on the carrier traveling layer, source and drain electrodes formed on the carrier supplying layer, insulating films formed on the carrier supplying layer and a gate electrode formed on the insulating films. The insulating film is formed in a region interposed between the source and drain electrodes and has a trench whose cross-section is inverted trapezoidal and whose upper opening is wider than a bottom thereof. The gate electrode is formed at least from the bottom of the trench onto the insulating films on the side of the drain electrode. | 05-13-2010 |
20100117147 | Capacitor-Less DRAM Device - Provided is a capacitor-less DRAM device including: an insulating layer formed on a semiconductor substrate; a silicon layer formed on the insulating layer, wherein a trench is formed inside the silicon layer; and an offset spacer formed on both sidewalls of the trench and protruded upward through the silicon layer. A gate insulating layer is formed on a bottom of the trench, and a gate electrode is formed to be buried in the gate insulating layer and in the trench and the offset spacer. A source region and a drain region are formed in the silicon layer on both sides of the offset spacer so as not to overlap with the gate electrode. A channel region is formed in the silicon layer below the gate insulating layer to be self-aligned with the gate electrode. | 05-13-2010 |
20100117148 | SEMICONDUCTOR DEVICES HAVING A RECESSED ACTIVE EDGE AND METHODS OF FABRICATING THE SAME - A semiconductor device having a recessed active edge is provided. The semiconductor devices include an isolation layer disposed in a substrate to define an active region. A gate electrode is disposed to cross over the active region. A source region and a drain region are disposed in the active region on both sides of the gate electrode. A recessed region is disposed under the gate electrode and on an edge of the active region adjacent to the isolation layer. A bottom of the recessed region may be sloped down toward the isolation layer. The gate electrode may further extend into and fill the recessed region. That is, a gate extension may be disposed in the recessed region. A method of fabricating the semiconductor device is also provided. | 05-13-2010 |
20100123187 | CONTACT STRUCTURE FOR SEMICONDUCTOR DEVICE HAVING TRENCH SHIELD ELECTRODE AND METHOD - In one embodiment, a contact structure for a semiconductor device having a trench shield electrode includes a gate electrode contact portion and a shield electrode contact portion within a trench structure. Contact is made to the gate electrode and the shield electrode within or inside of the trench structure. A thick passivating layer surrounds the shield electrode in the contact portion. | 05-20-2010 |
20100123188 | SEMICONDUCTOR DEVICE HAVING TRENCH SHIELD ELECTRODE STRUCTURE - In one embodiment, a structure for a semiconductor device having a trench shield electrode includes a control pad, control runners, shield runners, and a control/shield electrode contact structure. The structure is configured to use a single level of metal to connect the various components. In another embodiment, a shield runner is placed in an offset from center configuration. | 05-20-2010 |
20100123189 | SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE - A semiconductor component that includes an edge termination structure and a method of manufacturing the semiconductor component. A semiconductor material has a semiconductor device region and an edge termination region. One or more device trenches may be formed in the semiconductor device region and one or more termination trenches is formed in the edge termination region. A source electrode is formed in a portion of a termination trench adjacent its floor and a floating electrode termination structure is formed in the portion of the termination trench adjacent its mouth. A second termination trench may be formed in the edge termination region and a non-floating electrode may be formed in the second termination trench. Alternatively, the second termination trench may be omitted and a trench-less non-floating electrode may be formed in the edge termination region. | 05-20-2010 |
20100123190 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - Provided are a semiconductor device and a method for manufacturing the same. In the method, a first conductive type buried layer and a first conductive type drift region are formed on a semiconductor substrate. A gate dielectric and gate electrode are formed in a first trench that extends into the first conductive type drift region. An oxide layer is formed on the semiconductor substrate, and first conductive type source regions are formed at sides of the gate electrode in a second conductive type well on the first conductive type drift region. An interlayer dielectric, the oxide layer, and the second conductive type well are selectively etched, forming a second trench. A tungsten plug is formed on a barrier layer in the second trench. Aluminum is buried on the tungsten plug to form a source contact. A drain electrode layer is formed connected to the first conductive type buried layer. | 05-20-2010 |
20100127322 | VERTICAL TRENCH GATE TRANSISTOR SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A first region functioning as a transistor includes a drain region, a body region formed over the drain region, a source region formed over the body region and a trench formed through the body region and having a gate electrode buried therein. A source region is formed over the body region extending in a second region. The source region forming an upper edge of the trench is rounded. | 05-27-2010 |
20100133607 | Recessed Channel Negative Differential Resistance-Based Memory Cell - Disclosed herein is an improved recessed thyristor-based memory cell. The disclosed cell comprises in one embodiment a conductive plug recessed into the bulk of the substrate, which is coupled to or comprises the enable gate of the cell. Vertically disposed around this recessed gate is a thyristor, whose anode (source; p-type region) is connected to the bit line and cathode (drain; n-type region) is connected to the word line. Aside from the recessed enable gate, the disclosed cell comprises no other gate, such as an access transistor, and hence is essentially a one-transistor device. As a result, and as facilitated by the vertical disposition of the thyristor, the disclosed cell takes up a small amount of area on an integrated circuit when compared to a traditional DRAM cell. Moreover, the disclosed cell is simple to manufacture in its various embodiments, and is easy to configure into an array of cells. Isolation underneath the cell, while not required in all useful embodiments, assists in improving the data retention of the cell and extends the time needed between cell refresh. | 06-03-2010 |
20100133608 | METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE - An embodiment of the invention provides a method for forming a semiconductor device comprising providing a substrate with a pad layer formed thereon. The pad layer and the substrate are patterned to form a plurality of trenches. A trench top insulating layer is formed in each trench. Wherein the trench top insulating layer protrudes from the substrate and has an extension portion extending to the pad layer. The pad layer and the substrate are etched by using the trench top insulating layers and the extension portions as a mask to form a recess in the substrate. And a recess gate is formed in the recess. | 06-03-2010 |
20100133609 | METHODS OF PROVIDING ELECTRICAL ISOLATION AND SEMICONDUCTOR STRUCTURES INCLUDING SAME - Methods of isolating gates in a semiconductor structure. In one embodiment, isolation is achieved using a spacer material in combination with fins having substantially vertical sidewalls. In another embodiment, etch characteristics of various materials utilized in fabrication of the semiconductor structure are used to increase an effective gate length (“L | 06-03-2010 |
20100140689 | Trench-Based Power Semiconductor Devices with Increased Breakdown Voltage Characteristics - Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed. | 06-10-2010 |
20100140690 | GATE OF TRENCH TYPE MOSFET DEVICE AND METHOD FOR FORMING THE GATE - A gate of a trench type MOSFET device and a method of forming a gate. A gate of a trench type MOSFET device may include a gate oxide film formed on and/or over a trench type gate poly such that parasitic capacitance may be produced in a gate poly. An electric field may be substantially uniformly formed in a MESA region surrounding a gate poly. An overcurrent may be substantially prevented from flowing into a MOS channel around a gate. A gate oxide film may be substantially prevented from being destroyed and/or leakage may be substantially prevented. Reliability of a device may be maximized. | 06-10-2010 |
20100148247 | SEMICONDUCTOR DEVICE - A semiconductor device includes a gate electrode GE electrically connected to a gate portion which is made of a polysilicon film provided in the inside of a plurality of grooves formed in a striped form along the direction of T of a chip region CA wherein the gate electrode GE is formed as a film at the same layer level as a source electrode SE electrically connected to a source region formed between adjacent stripe-shaped grooves and the gate electrode GE is constituted of a gate electrode portion G | 06-17-2010 |
20100155832 | METHOD FOR FABRICATING SEMICONDUCTOR MEMORY DEVICE - A method for manufacturing a semiconductor device comprises forming a first spacer layer at sidewalls of one or more gate electrodes, forming a trench by etching an isolation insulating layer exposed between the gate electrodes, forming a second spacer layer on sidewalls of the gate electrodes and an inner surface of the trench and forming an interlayer insulating layer between the gate electrodes. | 06-24-2010 |
20100155833 | Semiconductor device having vertical type MOSFET and manufacturing method thereof - A method (and resultant structure) includes forming a semiconductor layer having plural stripe-like trenches, forming a gate electrode buried partially in each of the plural trenches, and introducing an impurity into the semiconductor layer by ion implantation after forming the gate electrode. The gate electrode has a buried portion formed in each of the trenches and a protruding portion situating above the buried portion and having a width larger than that of the buried portion. The introducing the impurity includes introducing an impurity into the semiconductor layer below the protruding portion by oblique ion implantation. | 06-24-2010 |
20100155834 | SEMICONDUCTOR DEVICE AND A METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate provided with an active region including a gate forming area, a source forming area and a drain forming area. A recess is formed in the gate forming area. A gate is formed over the gate forming area that is formed with the recess and includes an insulation layer formed at an upper end portion of a side wall of the recess that is in contact with the source forming area. A source area and a drain area are formed in the active region on opposite sides of the gate. | 06-24-2010 |
20100163975 | Trench metal oxide semiconductor field effect transistor (MOSFET) with low gate to drain coupled charges (Qgd) structures - A trenched semiconductor power device includes a plurality of trenched gates surrounded by source regions near a top surface of a semiconductor substrate encompassed in body regions. The trenched semiconductor power device further comprises tilt-angle implanted body dopant regions surrounding a lower portion of trench sidewalls for reducing a gate-to-drain coupling charges Qgd between the trenched gates and a drain disposed at a bottom of the semiconductor substrate. The trenched semiconductor power device further includes a source dopant region disposed below a bottom surface of the trenched gates for functioning as a current path between the drain to the source for preventing a resistance increase caused by the body dopant regions surrounding the lower portions of the trench sidewalls. | 07-01-2010 |
20100163976 | Semiconductor Device Having Saddle Fin Transistor and Method for Fabricating the Same - A method for fabricating a semiconductor device includes forming a pad nitride layer that exposes an isolation region over a cell region of a semiconductor substrate; forming a trench in the isolation region of the semiconductor substrate; forming an isolation layer within the trench; etching an active region of the semiconductor substrate by a certain depth to form a recessed isolation region; etching the isolation layer by a certain depth to form a recessed isolation region; depositing a gate metal layer in the recessed active region and the recessed isolation region to form a gate of a cell transistor; forming an insulation layer over an upper portion of the gate; removing the pad nitride layer to expose a region of the semiconductor substrate to be formed with a contact plug; and depositing a conductive layer in the region of the semiconductor substrate to form a contact plug. | 07-01-2010 |
20100171171 | Trench mosfet device with low gate charge and the manfacturing method thereof - A method for manufacturing trench MOSFET device with low gate charge includes the steps of providing a substrate of first conductivity type; forming an epitaxial layer of first conductivity type on the substrate; forming a body region of second conductivity type in the epitaxial layer, the body region extends downwards from the surface of the epitaxial layer; forming a plurality of trenches in the epitaxial layer, the body region having the trenches formed therethrough; forming a first insulating layer on the body region and on an inner surface of each trench; forming a ploy-silicon spacer on the first insulating layer on an inner side-wall of each trench; filling a dielectric structure in the lower portion of each trench; and filling a ploy-silicon structure on top of the dielectric structure in each trench. Through the trench MOSFET device, the gate capacitance and resistance thereof are reduced so the performance is increased. | 07-08-2010 |
20100171172 | Semiconductor device and method for manufacturing the same - A semiconductor device, includes a semiconductor layer of a second conductive type, a first diffused region of a first conductive type formed in the semiconductor layer, a second diffused region of the second conductive type selectively formed in the first diffused region, a trench formed in the semiconductor layer, a polysilicon formed in the trench with an insulator intervening, a first oxide film formed on the polysilicon so that the first oxide film is buried in the trench, a second oxide film formed on the first oxide film so that the second oxide film is buried in the trench, and a flowable insulator film formed on the second oxide film so that the flowable insulator film is buried in the trench. | 07-08-2010 |
20100176444 | POWER MOSFET AND METHOD OF FABRICATING THE SAME - A power MOSFET including a substrate of first conductivity type, an epitaxial layer of first conductivity type on the substrate, a body layer of second conductivity type in the epitaxial layer, a first insulating layer, a second insulating layer, a first conductive layer and two source regions of first conductivity type is provided. The body layer has a first trench therein. The epitaxial layer has a second trench therein. The second trench is below the first trench, and the width of the second trench is much smaller than that of the first trench. The first insulating layer is at least in the second trench. The first conductive layer is in the first trench. The second insulating layer is at least between the sidewall of the first trench and the first conductive layer. The source regions are disposed in the body layer beside the first trench respectively. | 07-15-2010 |
20100187602 | METHODS FOR MAKING SEMICONDUCTOR DEVICES USING NITRIDE CONSUMPTION LOCOS OXIDATION - Semiconductor devices and methods for making such devices using nitride consumption LOCOS oxidation are described. The semiconductor devices contain a planar field oxide structure that has been grown using a nitride layer as an oxidation mask. Once the field oxide structure has been grown, the nitride mask is not etched away, but rather converted to an oxide layer by an oxidation process using radicals of hydrogen and oxygen. The semiconductor devices also contain a shielded gate trench MOSFET that can be created using an oxide layer with an overlying nitride layer as the channel (sidewall) gate dielectric. An inter-poly-dielectric (IPD) layer can be formed from a thermally grown oxide which uses the nitride layer as a oxidation mask. The thickness of the IPD layer can be adjusted to any thickness needed with minimal effect of the channel gate dielectric layer. An oxidation process using radicals of hydrogen and oxygen can be preformed to consume the nitride layer and form the gate oxide in the channel region. Since the gate channel nitride acts as a barrier to the oxidation, the IPD oxide layer can be grown to any needed thickness with minimal oxidation to the channel gate and the nitride layer can be removed without any etching processes. Other embodiments are described. | 07-29-2010 |
20100187603 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device which can relax the electric field in the junction termination region, and can achieve a high breakdown voltage. | 07-29-2010 |
20100193862 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing according to the present invention includes forming a trench to a semiconductor substrate, depositing an insulating film to the trench, etching the insulating film of a bottom part of the trench by plasma etching and thereby forming to an opening part of the trench, an inclined surface at an angle of inclination a to a principal surface of the semiconductor substrate, forming a gate insulating film from a top surface of the semiconductor substrate to the insulating film of the bottom part of the trench, and forming a gate electrode on the gate insulating film. | 08-05-2010 |
20100193863 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - Described is a method for fabricating a semiconductor device having an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. In addition, the conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. Moreover, after etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate equal to or higher than the main surface of the semiconductor substrate, a channel region and a source region are formed by ion implantation. The semiconductor device thus fabricated according to the present invention is free from occurrence of a source offset. | 08-05-2010 |
20100200914 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A source layer | 08-12-2010 |
20100207203 | SEMICONDUCTOR DEVICE WITH BURIED GATE AND METHOD FOR FABRICATING THE SAME - A Semiconductor device includes a substrate having an active region defined by a device isolation layer, a trench formed by etching the active region and the device isolation layer, a buried gate filling a portion of the trench, an interlayer insulation layer formed over the buried gate and filling a remainder of the trench, and an oxidation protecting layer formed between the buried gate and the device isolation layer. | 08-19-2010 |
20100207204 | Semiconductor device and method of fabricating the same - A semiconductor device comprises a recessed trench in a substrate, a gate insulating layer including a first portion and a second portion, the first portion having a first thickness and covering lower portions of sidewalls of the recessed trench and a bottom surface of the recessed trench, and the second portion having a second thickness and covering upper portions of the sidewalls of the recessed trench, the second thickness being greater than the first thickness, a gate electrode filling the recessed trench, a first impurity region having a first concentration and disposed at opposing sides of the gate electrode, and a second impurity region having a second concentration greater than the first concentration and disposed on the first impurity region to correspond to the second portion of the gate insulating layer. | 08-19-2010 |
20100213540 | SEMICONDUCTOR DEVICE WITH A GATE HAVING A BULBOUS AREA AND A FLATTENED AREA UNDERNEATH THE BULBOUS AREA AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device with a gate having a bulbous area and a flattened area underneath the bulbous are is presented. The semiconductor device includes a semiconductor substrate, an isolation layer, a gate insulation layer, and gates. The semiconductor substrate has recess parts that have first grooves which have bulbous-shaped profiles and second vertically flattened profile grooves which extend downward from the first grooves. The gates are formed in the recess parts in which the gate insulation layer is double layered in the bulbous profile areas and is single layered in the flattened profile areas. | 08-26-2010 |
20100219467 | SEMICONDUCTOR DEVICE HAVING SADDLE FIN TRANSISTOR AND MANUFACTURING METHOD OF THE SAME - The present invention discloses a transistor having the saddle fin structure. The saddle fin transistor of the present invention has a structure in which a landing plug contact region, particularly, a landing plug contact region on an isolation layer is elevated such that the landing plug contact SAC (Self Aligned Contact) fail can be prevented. | 09-02-2010 |
20100219468 | POWER DEVICE STRUCTURES AND METHODS - Vertical power devices which include an insulated trench containing insulating material and a gate electrode, and related methods. A body region is positioned so that a voltage bias on the gate electrode will cause an inversion layer in the body region. A layer of permanent charge, at or near the sidewall of the trench, provides charge balancing for the space charge in the depleted semiconductor material during the OFF state. A conductive shield layer is positioned below the gate electrode in the insulating material, and reduces capacitive coupling between the gate and the lower part of the trench. This reduces switching losses. In other embodiments, a planar gate electrode controls horizontal carrier injection into the vertical conduction pathway along the trench, while a shield plate lies over the trench itself to reduce capacitive coupling. | 09-02-2010 |
20100219469 | MASK ROM CELL STRUCTURE AND METHOD OF FABRICATING THE SAME - A mask read-only memory (ROM) cell structure includes buried gate electrodes, common source regions under the gate electrodes, common drain regions extending between upper portions of adjacent ones of the gate electrodes, and two vertical channel regions on opposite sides, respectively, of each of the gate electrodes. The channel regions are selectively coded such that the cell transistors are on or off depending on whether the channel region of the transistor is coded. To this end, selected ones of the channel regions of the mask ROM structure are coded by forming ion implantation regions that differentiate the threshold voltages of the thus coded channel regions from the non-coded channel regions. The coding process may thus be carried out using a shallow ion implantation process. Accordingly, a relatively thin mask for coding may be used, and the ion implantation process may be carried out at a relatively low energy level. | 09-02-2010 |
20100224932 | Insulated Gate-Type Semiconductor Device and Manufacturing Method Thereof - A semiconductor | 09-09-2010 |
20100230746 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes an epitaxial layer having a first conduction type, a base layer formed adjacent and on the epitaxial layer and having an opposite second conduction type to the first conduction type, a source layer formed selectively on the base layer and having the first conduction type, a trench which passes through the base layer and the source layer and which reaches the epitaxial layer, an insulation film formed along an interior wall of the trench, a control electrode formed within the trench via the insulation film, and a semiconductor region formed along the bottom part of the trench at the epitaxial layer and having the first conduction type. | 09-16-2010 |
20100237408 | Recessed channel transistor - A recessed channel transistor includes an isolation layer provided in a semiconductor substrate to define an active region. A trench is provided in the semiconductor substrate to extend across the active region. A gate insulation layer covers a sidewall and a bottom face of the trench and an upper face of the semiconductor substrate adjacent to an upper edge of the trench, wherein a portion of the gate insulation layer on the upper surface of the semiconductor substrate adjacent to the upper edge of the trench and on the sidewall of the trench extending to a first distance downwardly from the upper edge of the trench has a thickness greater than that of a portion of the gate insulation layer on the remaining sidewall and the bottom face of the trench. A gate electrode fills up the trench having the gate insulation layer formed therein. | 09-23-2010 |
20100244125 | POWER SEMICONDUCTOR DEVICE STRUCTURE FOR INTEGRATED CIRCUIT AND METHOD OF FABRICATION THEREOF - A power semiconductor device comprises a conductive gate, provided in an upper part of a trench ( | 09-30-2010 |
20100244126 | Structure and Method for Forming a Salicide on the Gate Electrode of a Trench-Gate FET - A method for forming a trench-gate FET includes the following steps. A plurality of trenches is formed extending into a semiconductor region. A gate dielectric is formed extending along opposing sidewalls of each trench and over mesa surfaces of the semiconductor region between adjacent trenches. A gate electrode is formed in each trench isolated from the semiconductor region by the gate dielectric. Well regions of a second conductivity type are formed in the semiconductor region. Source regions of the first conductivity type are formed in upper portions of the well regions. After forming the source regions, a salicide layer is formed over the gate electrode in each trench abutting portions of the gate dielectric. The gate dielectric prevents formation of the salicide layer over the mesa surfaces of the semiconductor region between adjacent trenches. | 09-30-2010 |
20100244127 | BANDGAP ENGINEERED MOS-GATED POWER TRANSISTORS - Devices, methods, and processes that improve immunity to transient voltages and reduce parasitic impedances. Immunity to unclamped inductive switching events is improved. For example, a trench-gated power MOSFET device having a SiGe source is provided, where the SiGe source reduces parasitic npn transistor gain by reducing hole current in the body or well region, thereby decreasing the likelihood of a latch-up condition. A body tie on this device can also be eliminated to reduce transistor cell size. A trench-gated power MOSFET device having a SiGe body or well region is also provided. A SiGe body reduces hole current when the body diode is turned on, thereby reducing reverse recovery power losses. Device characteristics are also improved. For example, parasitic gate impedance is reduced through the use of a poly SiGe gate, and channel resistance is reduced through the use of a SiGe layer near the device's gate. | 09-30-2010 |
20100258858 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - Provided are a structure for reducing a parasitic capacitance generated between a gate electrode and a bit line in a highly integrated semiconductor memory apparatus, and a fabrication method thereof. The method of fabricating a semiconductor device according to the invention comprises: providing a substrate including an active region and an isolation region; forming a recess over the active region and the isolation region; etching the active region and the isolating region under the recess to form a fin structure; forming a buried gate over the fin structure in a lower portion of the recess; and forming an insulating layer filling in an upper portion of the recess. | 10-14-2010 |
20100258859 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE HAVING LOW CONTACT RESISTANCE - Disclosed herein is a method for forming a semiconductor device capable of reducing contact resistance in a highly integrated semiconductor device. The semiconductor device according to an exemplary embodiment of the invention includes an active region defined by an isolation film, the active region having porous regions therein, and gate patterns formed over the active region. | 10-14-2010 |
20100258860 | Semiconductor device including protrusion type isolation layer - A semiconductor device may include a semiconductor layer having a convex portion and a concave portion surrounding the convex portion. The semiconductor device may further include a protrusion type isolation layer filling the concave portion and extending upward so that an uppermost surface of the isolation layer is a at level higher that an uppermost surface of the convex portion. | 10-14-2010 |
20100258861 | SEMICONDUCTOR DEVICE WITH RECESS GATE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a substrate with a recess pattern, a gate electrode filling the recess pattern, a threshold voltage adjusting layer formed in the substrate under the recess pattern, a source/drain region formed in the substrate on both sides of the gate electrode and a gate insulation layer, with the recess pattern being disposed between the gate electrode and the substrate, wherein the thickness of the gate insulation layer formed in a region adjacent to the source/drain region is greater than the thickness of the gate insulation layer formed in a region adjacent to the threshold voltage adjusting layer. | 10-14-2010 |
20100258862 | TRENCH-GATE FIELD EFFECT TRANSISTOR WITH CHANNEL ENHANCEMENT REGION AND METHODS OF FORMING THE SAME - A field effect transistor includes a body region of a first conductivity type in a semiconductor region of a second conductivity type. A gate trench extends through the body region and terminating within the semiconductor region. A source region of the second conductivity type extends in the body region adjacent the gate trench. The source region and an interface between the body region and the semiconductor region define a channel region therebetween which extends along the gate trench sidewall. A channel enhancement region of the second conductivity type is formed adjacent the gate trench. The channel enhancement region partially extends into a lower portion of the channel region to thereby reduce a resistance of the channel region. | 10-14-2010 |
20100258863 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device according to the present invention having a vertical MOSFET that includes a first trench that is formed in a semiconductor substrate and includes a gate electrode of the vertical MOSFET embedded therein with a gate insulating film interposed therebetween, a second trench that is connected with the first trench and has a trench width wider than the first trench, a gate pad that is connected with the gate electrode and formed to a sidewall of the second trench with the gate insulating film interposed therebetween, and a gate line that is connected with a sidewall of the gate pad and electrically connects with the gate electrode via the gate pad. | 10-14-2010 |
20100258864 | Method of Forming a FET Having Ultra-low On-resistance and Low Gate Charge - In accordance with an exemplary embodiment of the invention, a substrate of a first conductivity type silicon is provided. A substrate cap region of the first conductivity type silicon is formed such that a junction is formed between the substrate cap region and the substrate. A body region of a second conductivity type silicon is formed such that a junction is formed between the body region and the substrate cap region. A trench extending through at least the body region is then formed. A source region of the first conductivity type is then formed in an upper portion of the body region. An out-diffusion region of the first conductivity type is formed in a lower portion of the body region as a result of one or more temperature cycles such that a spacing between the source region and the out-diffusion region defines a channel length of the field effect transistor. | 10-14-2010 |
20100258865 | TRANSISTOR HAVING RECESS CHANNEL AND FABRICATING METHOD THEREOF - A transistor includes a substrate including a trench, an insulation layer filled in a portion of the trench, the insulation layer having a greater thickness over an edge portion of a bottom surface of the trench than over a middle portion of the bottom surface of the trench, a gate insulation layer formed over inner sidewalls of the trench, the gate insulation layer having a thickness smaller than the insulation layer, and a gate electrode filled in the trench. | 10-14-2010 |
20100258866 | Method for Forming Shielded Gate Trench FET with Multiple Channels - A method of forming a field effect transistor (FET) includes the following steps. A pair of trenches extending into a semiconductor region of a first conductivity type is formed. A shield electrode is formed in a lower portion of each trench. A gate electrode is formed in an upper portion of each trench over but insulated from the shield electrode. First and second well regions of a second conductivity type are formed in the semiconductor region between the pair of trenches such that the first and second well regions are vertically spaced from one another and laterally abut sidewalls of the pair of trenches. The gate electrode and the first shield electrode are formed relative to the first and second well regions such that a channel is formed in each of the first and second well regions when the FET is biased in the on state. | 10-14-2010 |
20100264486 | FIELD PLATE TRENCH MOSFET TRANSISTOR WITH GRADED DIELECTRIC LINER THICKNESS - An electronic device has a plurality of trenches formed in a semiconducting layer. A vertical drift region is located between and adjacent the trenches. An electrode is located within each trench, the electrode having a gate electrode section and a field plate section. A graded field plate dielectric is located between the field plate section and the vertical drift region. | 10-21-2010 |
20100264487 | Method of Manufacturing a Trench Transistor Having a Heavy Body Region - A trenched field effect transistor is provided that includes (a) a semiconductor substrate, (b) a trench extending a predetermined depth into the semiconductor substrate, (c) a pair of doped source junctions, positioned on opposite sides of the trench, (d) a doped heavy body positioned adjacent each source junction on the opposite side of the source junction from the trench, the deepest portion of the heavy body extending less deeply into said semiconductor substrate than the predetermined depth of the trench, and (e) a doped well surrounding the heavy body beneath the heavy body. | 10-21-2010 |
20100270612 | Method for producing a vertical transistor component - A method for producing a vertical transistor component includes providing a semiconductor substrate, applying an auxiliary layer to the semiconductor substrate, and patterning the auxiliary layer for the purpose of producing at least one trench which extends as far as the semiconductor substrate and which has opposite sidewalls. The method further includes producing a monocrystalline semiconductor layer on at least one of the sidewalls of the trench, producing an electrode insulated from the monocrystalline semiconductor layer on the at least one sidewall of the trench and the semiconductor substrate. | 10-28-2010 |
20100276750 | Metal Oxide Semiconductor (MOS) Structure and Manufacturing Method Thereof - The manufacturing method includes the steps of: providing a semiconductor base of a first conduction type; forming a first epitaxial layer with a plurality of epitaxial pillars of therein on a first surface of the semiconductor base, wherein the epitaxial pillars have a conduction type opposite to the first epitaxial layer; forming a plurality of first shallow trenches and a plurality of second shallow trenches alternately on the epitaxial pillars and the first epitaxial layer, wherein the first shallow trench has a width greater than the width of the second shallow trench and the first shallow trench is extended downward to the epitaxial pillar; and forming a plurality of gate regions in the first shallow trenches respectively; forming a plurality of source regions on both sides of the first shallow trench; and forming a source metal conducting wire to connect the source regions. | 11-04-2010 |
20100289074 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device is provided. The semiconductor device includes a semiconductor substrate, at least a doped region, an electrical contact layer and a metal oxide semiconductor cell. The semiconductor substrate includes opposing first and second surfaces and at least a trench extending from the second surface into interior portion thereof. The doped region is located in the semiconductor substrate under the bottom of the trench. The dopant concentration of the doped region is higher than that of the semiconductor substrate. The electrical contact layer is located on the second surface of the semiconductor substrate and connects to the doped region. The metal oxide semiconductor cell is located on the semiconductor substrate adjacent the first surface thereof. | 11-18-2010 |
20100295122 | MOSFET HAVING RECESSED CHANNEL - A MOSFET having a recessed channel and a method of fabricating the same. The critical dimension (CD) of a recessed trench defining the recessed channel in a semiconductor substrate is greater than the CD of the gate electrode disposed on the semiconductor substrate. As a result, the misalignment margin for a photolithographic process used to form the gate electrodes can be increased, and both overlap capacitance and gate induced drain leakage (GIDL) can be reduced. | 11-25-2010 |
20100301408 | SEMICONDUCTOR DEVICE - A semiconductor device is disclosed. One embodiment includes a trench within a semiconductor body and a gate insulating structure at opposing sidewalls within the trench. A gate electrode structure adjoins the gate insulating structure within the trench and a dielectric structure adjoins the gate electrode structure within the trench. The gate electrode structure is in contact with the semiconductor body at a bottom side of the trench and is electrically coupled to a drain zone over an element having a voltage blocking capability. | 12-02-2010 |
20100308400 | Semiconductor Power Switches Having Trench Gates - A method of fabricating a trench device includes forming a first trench and forming a hardmask layer on sidewalls of the trench. A second trench may be etched narrower than the first trench, into the bottom of the first trench. A dielectric material may be grown to substantially fill the second trench, using a reaction process to which the hardmask material is substantially inert. The growing action also grows tapered portions of the dielectric material upwardly under part of the hardmask. A conductive layer may be formed over said dielectric material. The dielectric material in the second trench, in combination with the tapered portions which extend upward from the dielectric material may provide smooth gradation of voltage differences within the semiconductor material. The gradation may be caused by potential differences between the gate and various portions of the semiconductor material. | 12-09-2010 |
20100308401 | POWER SEMICONDUCTOR DEVICE - A semiconductor layer has a first layer of first conductive type, a second layer of second conductive type, and a third layer. The third layer has a first region of first conductive type, and a second region of second conductive type. A second electrode is in contact with each of the first and second regions. A trench is formed on the semiconductor layer at a surface opposite to its surface facing a first electrode. A gate electrode is embedded in the trench with a gate insulating film interposed therebetween. The gate electrode includes a first portion projecting into the first layer through the first region and the second layer, a second portion projecting into the first layer through the second region and the second layer. The second portion projects into the first layer deeper than a depth in which the first portion projects into the first layer. | 12-09-2010 |
20100320532 | TRENCH GATE MOSFET AND METHOD OF MANUFACTURING THE SAME - A Trench gate MOS field-effect transistor having a narrow, lightly doped, region extending from a channel accommodating region ( | 12-23-2010 |
20100327344 | Power Semiconductor Devices and Methods - The present inventors have realized that manufacturability plays into optimization of power semiconductor devices in some surprising new ways. If the process window is too narrow, the maximum breakdown voltage will not be achieved due to doping variations and the like normally seen in device fabrication. Thus, among other teachings, the present application describes some ways to improve the process margin, for a given breakdown voltage specification, by actually reducing the maximum breakdown voltage. In one class of embodiments, this is done by introducing a vertical gradation in the density of fixed electrostatic charge, or in the background doping of the drift region, or both. Several techniques are disclosed for achieving this. | 12-30-2010 |
20100327345 | SEMICONDUCTOR DEVICE - A semiconductor device includes a transistor with a substrate on which source and drain regions, both of a first conductivity type, and a channel region of a second conductivity type between the source and drain are formed, and a gate electrode formed in the channel region to bury a trench formed so the depth thereof changes intermittently in the width direction of the gate. In the channel region, each on a surface of the substrate and in a bottom portion of the trench, there are formed a second high-concentration region and a first high-concentration region, and the dopant concentration of the second conductivity type is higher than the dopant concentration of the second conductivity type in portions sideward from the trench. The dopant concentration of the second conductivity type in the first high-concentration region is higher than the dopant concentration of the second conductivity type in the second high-concentration region. | 12-30-2010 |
20110001186 | SEMICONDUCTOR DEVICE WITH BURIED GATE AND METHOD FOR FABRICATING THE SAME - A semiconductor device and method for fabricating the same is provided. The semiconductor device includes a trench formed in a substrate, a junction region formed in the substrate on both sides of the trench, a first gate insulation layer formed on the surface of the trench, a first buried conductive layer formed over the first gate insulation layer to fill a portion of the trench, a second buried conductive layer formed between the first buried conductive layer and the first gate insulation layer to provide a gap between the first buried conductive layer and the first gate insulation layer, and a second gate insulation layer buried in the gap. | 01-06-2011 |
20110001187 | Configurations and methods for manufacturing charge balanced devices - This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of deep trenches. The deep trenches are filled with an epitaxial layer thus forming a top epitaxial layer covering areas above a top surface of the deep trenches covering over the semiconductor substrate. The semiconductor power device further includes a plurality of transistor cells disposed in the top epitaxial layer whereby a device performance of the semiconductor power device is dependent on a depth of the deep trenches and not dependent on a thickness of the top epitaxial layer. Each of the plurality of transistor cells includes a trench DMOS transistor cell having a trench gate opened through the top epitaxial layer and filled with a gate dielectric material. | 01-06-2011 |
20110006362 | Trench MOSFET with on-resistance reduction - A trench MOSFET with on-resistance reduction comprises a trenched gate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate, wherein the said MOSFET further comprises a plurality of source-body contact trenches opened relative to a top surface into said source and body regions and each of the source-body contact trenches is filled with a contact metal plug as a source-body contact; a insulation layer covered over the top of the trenched gate, the body region and the source region; a front metal layer formed on a top surface of the MOSFET; wherein a low-resistivity phosphorus substrate and retrograded P-body formed by medium or high energy Ion Implantation to reduce Rds contribution from substrate and drift region. | 01-13-2011 |
20110006363 | Trench MOSFET structures using three masks process - A trench MOSFET structure having improved avalanche capability is disclosed, wherein the source region is formed by performing source Ion Implantation through contact open region of a contact interlayer, and further diffused to optimize a trade-off between Rds and the avalanche capability. Thus, only three masks are needed in fabrication process, which are trench mask, contact mask and metal mask. Furthermore, said source region has a doping concentration along channel region lower than along contact trench region, and source junction depth along channel region shallower than along contact trench, and source doping profile along surface of epitaxial layer has Guassian-distribution from trenched source-body contact to channel region. | 01-13-2011 |
20110006364 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a first-conductivity-type semiconductor layer, a first and second-conductivity-type semiconductor pillar regions, a second and first-conductivity-type semiconductor regions, a first and second main electrodes, and a control electrode. Each of the first and second-conductivity-type pillar regions extends in a first direction and is alternately provided along a second direction generally perpendicular to the first direction. The second-conductivity-type semiconductor region is provided in a cell region and connected to the second-conductivity-type semiconductor pillar region. The first-conductivity-type semiconductor region is selectively provided in a surface of the second-conductivity-type semiconductor region. The first main electrode is connected to the first-conductivity-type semiconductor layer. The second main electrode is connected to the first and second-conductivity-type semiconductor region. The control electrode is configured to control a current path between the first-conductivity-type semiconductor region and the first-conductivity-type semiconductor pillar region. | 01-13-2011 |
20110006365 | Semiconductor Device Comprising Transistor Structures and Methods for Forming Same - A method for forming an opening within a semiconductor material comprises forming a neck portion, a rounded portion below the neck portion and, in some embodiments, a protruding portion below the rounded portion. This opening may be filled with a conductor, a dielectric, or both. Embodiments to form a transistor gate, shallow trench isolation, and an isolation material separating a transistor source and drain are disclosed. Device structures formed by the method are also described. | 01-13-2011 |
20110018057 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A manufacturing method of a semiconductor device comprises forming a semiconductor substrate including an active region and an element isolation film, forming a first recess on the semiconductor substrate, forming an oxide film on a sidewall of the first recess, forming a second recess by etching a lower part of the first recess, and forming a gate in a lower part of the second recess. | 01-27-2011 |
20110024829 | SEMICONDUCTOR DEVICE HAVING VOIDS ALONG BURIED GATES AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device having voids along buried gates and a method of manufacturing the same is presented. The semiconductor device includes recesses, a first gate electrode, a second gate electrode, and a gate protection layer. The first gate electrode fills in a lower portion of the recess. The second gate electrode is formed on the first gate electrode and partially fills in the upper portion of the recess such that the second gate electrode has a downwardly tapered width. The gate protection layer fills in the remaining portion of the recess while leaving voids next to the second gate electrode. Accordingly, it is thought that the voids reduce gate resistance and improve the gate-induced drain leakage (GIDL) characteristics of the resultant device. | 02-03-2011 |
20110024830 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device comprises a buried gate formed by being buried under a surface of a semiconductor substrate, a dummy gate formed on the buried gate, and a landing plug formed on a junction region of the semiconductor substrate being adjacent to the dummy gate. | 02-03-2011 |
20110024831 | SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device (A | 02-03-2011 |
20110031551 | Structure and Method For Forming Laterally Extending Dielectric Layer in a Trench-Gate FET - A FET is formed as follows. A trench is formed in a silicon region. A shield electrode is formed in a bottom portion of the trench. The shield electrode is insulated from adjacent silicon region by a shield dielectric. A silicon nitride layer is formed over a surface of the silicon region adjacent the trench, along the trench sidewalls, and over the shield electrode and shield dielectric. A layer of LTO is formed over the silicon nitride layer such that those portions of the LTO layer extending over the surface of the silicon region adjacent the trench are thicker than the portion of the LTO layer extending over the shield electrode. The LTO layer is uniformly etched back such that a portion of the silicon nitride layer becomes exposed while portions of the silicon nitride layer remain covered. | 02-10-2011 |
20110042741 | Semiconductor device having semiconductor chip and metal plate and method for manufacturing the same - A semiconductor device includes a first protection film for covering a first metal wiring. A second protection film is disposed on the first protection film, which is covered with a solder layer. Even if a crack is generated in the second protection film before the solder layer is formed on the second protection film, the crack is restricted from proceeding into the first protection film. | 02-24-2011 |
20110049618 | FABRICATION OF TRENCH DMOS DEVICE HAVING THICK BOTTOM SHIELDING OXIDE - Semiconductor device fabrication method and devices are disclosed. A device may be fabricated by forming in a semiconductor layer; filling the trench with an insulating material; removing selected portions of the insulating material leaving a portion of the insulating material in a bottom portion of the trench; forming one or more spacers on one or more sidewalls of a remaining portion of the trench; anisotropically etching the insulating material in the bottom portion of the trench using the spacers as a mask to form a trench in the insulator; removing the spacers; and filling the trench in the insulator with a conductive material. Alternatively, an oxide-nitride-oxide (ONO) structure may be formed on a sidewall and at a bottom of the trench and one or more conductive structures may be formed in a portion of the trench not occupied by the ONO structure. | 03-03-2011 |
20110049619 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method for manufacturing the same are disclosed. The method for manufacturing the semiconductor device forms a recess gate region on a semiconductor substrate, forms an isolation layer isolated from the recess gate region using a high-temperature thermal process, and guarantees a larger channel region by filling the isolation layer with a gate electrode material, so that a cell current is increased and on/off characteristics of a transistor are improved. | 03-03-2011 |
20110057257 | Semiconductor device and method for manufacturing the same - The present invention provides a semiconductor device including: a base substrate; a semiconductor layer which is disposed on the base substrate and has a recess structure formed thereon; a gate structure covering the recess structure; a source electrode and a drain electrode which are disposed to be spaced apart from each other with respect to the gate structure interposed therebetween, on the semiconductor layer, wherein the semiconductor layer having an upper layer whose thickness is increased toward a first direction facing the drain electrode from the gate structure. | 03-10-2011 |
20110068389 | Trench MOSFET with high cell density - A trench MOSFET with high cell density is disclosed where there is a heavily doped contact region on the top surface of mesas between a pair of gate trenches. The present invention can prevent the degradation of avalanche capability when shrinking the device in prior art. | 03-24-2011 |
20110068390 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor device includes a semiconductor substrate, a drain layer provided thereon, a first body layer provided thereon, source layers and a gate electrode buried in each of a plurality of trenches. The source layers are discretely arranged in a staggered pattern on a surface of the first body layer in a first direction and in a second direction orthogonal to the first direction. The trenches extend in a third direction on the surface of the first body layer, are arranged in a fourth direction orthogonal to the third direction, and pierce through the source layer and the first body layer into the drain layer. The gate electrode is buried in each of the trenches via a gate insulating film. Sum of the width of the source layer and the spacing between the source layer and the adjacent source layer is smaller than spacing between the adjacent trenches. | 03-24-2011 |
20110068391 | SEMICONDUCTOR DEVICE AND PROCESS FOR PRODUCING THE SAME - A trench gate transistor whose gate changes depth intermittently in the gate width direction, has a first offset region and a second offset region formed below the source and drain, respectively. The first offset region and the second offset region are shallower where they contact the device isolation film than is the device isolation film in those areas. The first and second offset regions nevertheless extend below the bottom of the trench. | 03-24-2011 |
20110068392 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A gate trench | 03-24-2011 |
20110073939 | SEMICONDUCTOR DEVICE - A semiconductor device may include, but is not limited to: a semiconductor substrate; a first insulating film; a conductive film; and a semiconductor film. The semiconductor substrate has a first hole. The semiconductor substrate has a first region into which a first impurity is introduced. The first region is adjacent to a side surface of the first hole. The first insulating film covers at least the side surface and a bottom surface of the first hole. The first insulating film has a second hole adjacent to the side surface of the first hole. The conductive film fills a bottom portion of the first hole. The semiconductor film is positioned over the conductive film. The semiconductor film fills the second hole and is in contact with the first region. | 03-31-2011 |
20110079842 | SEMICONDUCTOR DEVICE - A semiconductor device includes a gate electrode GE electrically connected to a gate portion which is made of a polysilicon film provided in the inside of a plurality of grooves formed in a striped form along the direction of T of a chip region CA wherein the gate electrode GE is formed as a film at the same layer level as a source electrode SE electrically connected to a source region formed between adjacent stripe-shaped grooves and the gate electrode GE is constituted of a gate electrode portion G | 04-07-2011 |
20110084332 | TRENCH TERMINATION STRUCTURE - A trench MOS device includes a base semiconductor substrate, an epitaxial layer grown on the base semiconductor substrate, a first trench in the epitaxial layer, and a stepped trench comprising a second trench and a third trench in the epitaxial layer. There is a mesa between the first trench and the stepped trench. There is a spacer on a the sidewall of the second trench, wherein the third trench having a depth below the spacer. There is a dielectric layer extending along sidewalls and bottom walls of the second trench and the third trench. There is also a metal layer extending over the first trench, over a sidewall of the stepped trench and a portion of the bottom of the stepped trench. | 04-14-2011 |
20110084333 | POWER DEVICES WITH SUPER JUNCTIONS AND ASSOCIATED METHODS MANUFACTURING - Power devices with super junctions and associated methods of manufacturing are disclosed herein. In one embodiment, a method for forming a power device includes forming an epitaxial layer on a substrate material and forming a trench in the epitaxial layer. The trench has a first sidewall, a second sidewall, and a bottom between the first and second sidewalls. The method also includes forming an insulation material on at least one of the first and second sidewalls of the trench and diffusing a dopant into the epitaxial layer via at least one of the first and second sidewalls of the trench via the insulation material. | 04-14-2011 |
20110089484 | METHOD AND SYSTEM FOR METAL GATE FORMATION WITH WIDER METAL GATE FILL MARGIN - A method includes providing a semiconductor substrate having a gate trench and depositing a metal layer, using a physical vapor deposition (PVD) process, over the substrate to partially fill the trench. The metal layer includes a bottom portion and a sidewall portion that is thinner than the bottom portion. The method also includes forming a coating layer on the metal layer, etching back the coating layer such that a portion of the coating layer protects a portion of the metal layer within the trench, and removing the unprotected portion of the metal layer. A different aspect involves a semiconductor device that includes a gate that includes a trench having a top surface, and a metal layer formed over the trench, wherein the metal layer includes a sidewall portion and a bottom portion, and wherein the sidewall portion is thinner than the bottom portion. | 04-21-2011 |
20110089485 | SPLIT GATE SEMICONDUCTOR DEVICE WITH CURVED GATE OXIDE PROFILE - A split gate semiconductor device includes a trench gate having a first electrode region and a second electrode region that are separated from each other by a gate oxide layer and an adjacent dielectric layer. The boundary of the gate oxide layer and the dielectric layer is curved to avoid a sharp corner where the gate oxide layer meets the sidewalls of the trench. | 04-21-2011 |
20110089486 | SUPER-HIGH DENSITY TRENCH MOSFET - A method, in one embodiment, can include forming a plurality of trenches in a body region for a vertical metal-oxide semiconductor field-effect transistor (MOSFET). In addition, the method can include angle implanting source regions into the body region. Furthermore, dielectric material can be grown within the plurality of trenches. Gate polysilicon can be deposited within the plurality of trenches. Moreover, the method can include chemical mechanical polishing the gate polysilicon. The method can also include etching back the gate polysilicon within the plurality of trenches. | 04-21-2011 |
20110089487 | SEMICONDUCTOR DEVICE - A semiconductor device includes a base layer that has a first conductivity type, a source layer that is formed on the base layer and has a second conductivity type, and an insulating film that is formed on the source layer. The semiconductor device further includes a plurality of gate structures that penetrate the base layer, and a plurality of conductive parts that penetrate the insulating film and the source layer and electrically connect the source layer and the base layer to each other. The gate structures are formed in a strip shape in plan view. Parts in which the conductive portion is connected to the base layer are formed in a stripe shape in plan view, and are formed between the gate structures. Further, a dimension of the part in which the source layer and the base layer are in contact with each other between the gate structure and the conductive portion is 0.36 μm or more. | 04-21-2011 |
20110101450 | SEMICONDUCTOR DEVICE WITH BURIED GATES AND BURIED BIT LINES AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes: a plurality of first trenches formed inside a plurality of active regions; a plurality of buried gates configured to partially fill insides of the plurality of the first trenches; a plurality of second trenches formed to be extended in a direction crossing the plurality of the buried gates; and a plurality of buried bit lines configured to fill the plurality of the second trenches. | 05-05-2011 |
20110101451 | SEMICONDUCTOR COMPONENT STRUCTURE WITH VERTICAL DIELECTRIC LAYERS - A semiconductor component having a semiconductor body having a first and a second side, an edge and an edge region adjacent to the edge in a lateral direction is described. | 05-05-2011 |
20110108911 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a first and a second semiconductor layer of a first conductivity type, a third semiconductor layer of a second conductivity type, a source region of the first conductivity type, a first and a second main electrode, trench gates, a first and a second contact region. The third semiconductor layer is provided on the second semiconductor layer provided on the first semiconductor layer. The first main electrode is electrically connected to the first semiconductor layer. The second main electrode is electrically connected to the source region provided on the third semiconductor layer. The trench gates are provided from the third semiconductor layer to the second semiconductor layer. The first and second contact regions electrically connect the second main electrode and the third semiconductor layer. An opening area of the second contact hole is smaller than that of the first contact hole. | 05-12-2011 |
20110121384 | TRENCH-GATE SEMICONDUCTOR DEVICE - A trench-gate semiconductor device is disclosed, in which the p-layer ( | 05-26-2011 |
20110127601 | Semiconductor Devices and Methods for Making the Same - Semiconductor devices and methods for making such devices that are especially suited for high-frequency applications are described. The semiconductor devices combine a SIT (or a junction field-effect transistor [JFET]) architecture with a PN super-junction structure. The SIT architecture can be made using a trench formation containing a gate that is sandwiched between thick dielectric layers. While the gate is vertically sandwiched between the two isolating regions in the trench, it is also connected to a region of one conductivity type of the super-junction structure, thereby allowing control of the current path of the semiconductor device. Such semiconductor devices have a lower specific resistance and capacitance relative to conventional planar gate and recessed gate SIT semiconductor devices. Other embodiments are described. | 06-02-2011 |
20110140197 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer, a third semiconductor layer, a fourth semiconductor layer, first trenches, a second trench, an insulating film, a gate electrode, a first main electrode, a second main electrode, a channel stopper layer and a channel stopper electrode. The second semiconductor layer of the first conductivity type is provided on the first semiconductor layer. The third semiconductor layer of a second conductivity type is provided on the second semiconductor layer. The fourth semiconductor layer of the first conductivity type is provided on the third semiconductor layer. The gate electrode is provided in the first trenches via the insulating film. The first main electrode is provided on the first semiconductor layer. The second main electrode is provided to contact the element part. The channel stopper electrode is provided on the termination part. | 06-16-2011 |
20110140198 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - Described is a method for fabricating a semiconductor device having an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. In addition, the conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. Moreover, after etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate equal to or higher than the main surface of the semiconductor substrate, a channel region and a source region are formed by ion implantation. The semiconductor device thus fabricated according to the present invention is free from occurrence of a source offset. | 06-16-2011 |
20110147830 | METHOD OF FORMING A SELF-ALIGNED CHARGE BALANCED POWER DMOS - Self-aligned charge balanced semiconductor devices and methods for forming such devices are disclosed. One or more planar gates are formed over a semiconductor substrate of a first conductivity type. One or more deep trenches are etched in the semiconductor self-aligned to the planar gates. The trenches are filled with a semiconductor material of a second conductivity type such that the deep trenches are charge balanced with the adjacent regions of the semiconductor substrate This process can form self-aligned charge balanced devices with a cell pitch less than 12 microns. | 06-23-2011 |
20110147831 | METHOD FOR REPLACEMENT METAL GATE FILL - An exemplary embodiment of a method for forming a gate for a planar-type or a finFET-type transistor comprises forming a gate trench that includes an interior surface. A first work-function metal is formed on the interior surface of the gate trench, and a low-resistivity material is deposited on the first work-function metal using a chemical vapor deposition (CVD) technique, or an atomic layer deposition (ALD) technique, or combinations thereof. Another exemplary embodiment provides that a second work-function metal is formed on the first work-function metal, and then the low-resistivity material is deposited on the first work-function metal using a chemical vapor deposition (CVD) technique, or an atomic layer deposition (ALD) technique, or combinations thereof. | 06-23-2011 |
20110147832 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device, the method comprising: forming a mask pattern over a semiconductor substrate including a device isolation film; etching the semiconductor substrate with the mask pattern as a barrier to form a recess having a semi-circular shape; filling a sacrificial material in the semi-circular shaped recess and between the mask pattern; removing the mask pattern; forming a silicon layer in a portion where the mask pattern is removed; removing the sacrificial material to form a gate region; and providing to gate electrode material in the gate region to form a gate pattern thereby enlarging the radius of curvature of the lower portion of the buried gate to improve a DIBL characteristic and enlarging the area of the part connected to a gate junction to improve contact resistance. | 06-23-2011 |
20110147833 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A semiconductor device includes a semiconductor substrate including an active area defined by an device isolation region, a buried gate formed on both side walls of a trench formed in the semiconductor substrate, and a storage node contact which is buried between the buried gates, and is connected to the active region of a middle portion of the trench and the device isolation region. | 06-23-2011 |
20110147834 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes a semiconductor substrate, an impurity region in the semiconductor substrate, and a conductive layer contacting a top surface of the impurity region and at least a side surface of the impurity region. | 06-23-2011 |
20110156135 | BURIED GATE IN SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A buried gate in a semiconductor device and a method for fabricating the same are presented. The method includes: forming a gate trench in an active region of a semiconductor substrate; filling the gate trench with a barrier metal film and a metal film; recessing the metal film and the barrier metal film to form buried gate electrodes that partially fill the gate trench; recessing the barrier metal film of the buried gate electrode below the surface of the metal film; and filling an exposed part of the buried gate electrode and the gate trench with a capping film. | 06-30-2011 |
20110156136 | SEMICONDUCTOR COMPONENT AND MANUFACTURING METHOD THEREOF - A semiconductor component includes: a semiconductor substrate; and a semiconductor device provided thereon, the device being a field-effect transistor that includes: a gate insulating film provided on the substrate; a gate electrode provided via the film; and a pair of source-drain regions provided to sandwich the electrode, the substrate including a patterned surface in a portion where the electrode is provided, the patterned surface of the substrate including a raised portion where the film is formed to cover a surface that lies on the same plane as a surface of the pair of source-drain regions, and the electrode is formed on a top surface of the film, and the patterned surface of the substrate including a recessed portion where the film is formed to cover surfaces of a groove formed toward the interior than the surface of the pair of source-drain regions, and the electrode is formed so as to fill the groove provided with the film. | 06-30-2011 |
20110156137 | TRENCH GATE SEMICONDUCTOR DEVICE AND THE METHOD OF MANUFACTURING THE SAME - A trench gate semiconductor device is disclosed which has a trench gate structure including an insulator in the upper portion of a first trench, the insulator being on a gate electrode; a source region having a lower end surface positioned lower than the upper surface of the gate electrode; a second trench in the surface portion of a semiconductor substrate between the first trenches, the second trench having a slanted inner surface providing the second trench with the widest trench width at its opening and a bottom plane positioned lower than the lower end surface of the source region, the slanted inner surface being in contact with the source region; and a p-type body-contact region in contact with the slanted inner surface of the second trench. The trench gate semiconductor device and its manufacturing method facilitate increasing the channel density and lowering the body resistance of the parasitic BJT. | 06-30-2011 |
20110156138 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In a well region, an irregular structure is formed in a gate width direction, and a gate electrode is formed in concave portions and on top surfaces of convex portions via an insulating film. Upper and lower source regions are formed on one side of the gate electrode in a gate length direction, and upper and lower drain regions are formed on the other side thereof. By thus forming the lower source and drain regions in the source and drain regions, current concentration occurring in an upper portion of a channel region, which is generated as the gate length becomes shorter, may be suppressed and a current may be allowed to flow uniformly in the entire channel region, and hence an effective gate width is made wider owing to the irregular structure formed in the well region. Accordingly, an on-resistance of a semiconductor device is reduced to enhance driving performance. | 06-30-2011 |
20110163373 | Semiconductor device including a voltage controlled termination structure and method for fabricating same - According to one embodiment, a semiconductor device including a voltage controlled termination structure comprises an active area including a base region of a first conductivity type formed in a semiconductor body of a second conductivity type formed over a first major surface of a substrate of the second conductivity type, a termination region formed in the semiconductor body adjacent the active area and including the voltage controlled termination structure. The voltage controlled termination structure includes an electrode electrically connected to a terminal of the semiconductor device. In one embodiment, the electrode of the voltage controlled termination structure is electrically connected to a gate terminal of the semiconductor device. In one embodiment, the electrode of the voltage controlled termination structure is electrically connected to a source terminal of the semiconductor device. | 07-07-2011 |
20110163374 | TRENCH-TYPED POWER MOS TRANSISTOR AND METHOD FOR MAKING THE SAME - A trench-typed power MOS transistor comprises a trench-typed gate area, which includes a gate conductor and an isolation layer. A thin sidewall region of the isolation layer is formed between the gate conductor and a well region. A thick sidewall region of the isolation layer is formed between the gate conductor and a double diffusion region. A thick bottom region of the isolation layer is formed between the gate conductor and a deep well region. | 07-07-2011 |
20110169075 | Trench mosfet with ultra high cell density and manufacture thereof - A trench MOSFET structure with ultra high cell density is disclosed, wherein the source regions and the body regions are located in different regions to save the mesa area between every two adjacent gate trenches in the active area. Furthermore, the inventive trench MOSFET is composed of stripe cells to further increase cell packing density and decrease on resistance Rds between the drain region and the source region. | 07-14-2011 |
20110175162 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor memory device includes: forming a trench in a substrate; forming a gate insulation layer along the trench, wherein the gate insulation layer is thicker at an upper region of the trench than at a lower region thereof; forming a gate pattern on the gate insulation layer to fill the trench; forming a first active region over a first region of the gate pattern to overlap the gate pattern at the thicker region of the gate insulation layer; and forming a second active region formed over a second region of the gate pattern and spaced apart from the first active region by a floating body formed therebetween, wherein the second region is vertically lower than the first region. | 07-21-2011 |
20110180868 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - The present invention relates to a semiconductor device and a method for manufacturing the same. According to the present invention, a method of manufacturing a semiconductor device includes: forming a recess on a semiconductor substrate; forming a first gate electrode material and a hard mask layer on an entire surface including the recess; etching the hard mask layer and the first gate electrode material to form the first gate electrode pattern on a lower portion of inside of the recess; forming a second gate electrode material on an entire surface including the recess; and etching the second gate electrode material and separating the second gate electrode material. | 07-28-2011 |
20110186923 | SEMICONDUCTOR MEMORY DEVICE HAVING VERTICAL CHANNEL TRANSISTOR AND METHOD FOR FABRICATING THE SAME - Channels of two transistors are vertically formed on portions of two opposite side surfaces of one active region, and gate electrodes are vertically formed on a device isolation layer contacting the channels of the active region. A common bit line contact plug is formed in the central portions of the active region, two storage node contact plugs are formed on both sides of the bit line contact plug, and an insulating spacer is formed on a side surface of the bit line contact plug. A word line, a bit line, and a capacitor are sequentially stacked on the semiconductor substrate, like a conventional semiconductor memory device. Thus, effective space arrangement of a memory cell is possible such that a 4F | 08-04-2011 |
20110193158 | Semiconductor Devices With Sealed, Unlined Trenches and Methods of Forming Same - A semiconductor device includes unlined and sealed trenches and methods for forming the unlined and sealed trenches. More particularly, a superjunction semiconductor device includes unlined, and sealed trenches. The trench has sidewalls formed of the semiconductor material. The trench is sealed with a sealing material such that the trench is air-tight. First and second regions are separated by the trench. The first region may include a superjunction Schottky diode or MOSFET. In an alternative embodiment, a plurality of regions are separated by a plurality of unlined and sealed trenches. | 08-11-2011 |
20110204436 | Shielded Gate Trench FET with the Shield and Gate Electrodes Connected Together in Non-active Region - A field effect transistor (FET) in a semiconductor die including an active region housing active cells, a non-active region with no active cells therein, a drift region of a first conductivity type, a body region of a second conductivity type over the drift region, and a plurality of trenches extending through the body region and into the drift region. Each trench includes a shield electrode and a gate electrode, the shield electrode being disposed below the gate electrode. The FET further includes source regions of the first conductivity type in the body region adjacent to each trench, heavy body regions of the second conductivity type in the body regions adjacent the source regions, and a source interconnect layer contacting the source regions and heavy body regions. The shield electrode and the gate electrode extend out of each trench and into the non-active region where the shield electrode and gate electrode are electrically connected together by a gate interconnect layer. | 08-25-2011 |
20110204437 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device having a low on resistance and high integration level with respect to the surface area of a substrate is provided. In the semiconductor device, a first trench, a second trench, and a third trench are provided in an element formation region provided on a semiconductor substrate. Metal is deposited within the first trench and second trench, to form a drain electrode and a source electrode, respectively. Polysilicon is deposited inside the third trench with a gate insulating film intervening, and a gate electrode is formed. | 08-25-2011 |
20110210389 | Transistor Comprising a Buried High-K Metal Gate Electrode Structure - A buried gate electrode structures may be formed in the active regions of sophisticated transistors by providing a recess in the active region and incorporating appropriate gate materials, such as a high-k dielectric material and a metal-containing electrode material. Due to the recessed configuration, the channel length and thus the channel controllability may be increased, without increasing the overall lateral dimensions of the transistor structure. | 09-01-2011 |
20110210390 | MOS DEVICE WITH VARYING TRENCH DEPTH - A semiconductor device includes a drain region comprising an epitaxial layer, a body disposed in the epitaxial layer, a source embedded in the body, a gate trench extending into the epitaxial layer, a gate disposed in the gate trench, an active region contact trench extending through the source, and an active region contact electrode disposed within the active region contact trench. The active region contact trench has a first width associated with a first region that is in proximity to a bottom portion of the body and a second width associated with a second region that is in proximity to a bottom portion of the source. The first width is substantially different from the second width. | 09-01-2011 |
20110215397 | HIGH CELL DENSITY TRENCHED POWER SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF - The fabrication method of a high cell density trenched power semiconductor structure is provided. The fabrication method comprises the steps of: a) forming at least a gate trench in a substrate with a silicon oxide patterned layer formed thereon, said silicon oxide patterned layer having at least an open aligned to the gate trench; b) forming a polysilicon gate in the gate trench; c) forming a dielectric structure in the open, the dielectric structure has a sidewall thereof being lined with an etching protection layer; d) removing the silicon oxide patterned layer by selective etching; and e) forming a spacer on a side surface of the dielectric structure to define at least a contact window. | 09-08-2011 |
20110215398 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region. | 09-08-2011 |
20110220990 | SHIELDED GATE TRENCH MOS WITH IMPROVED SOURCE PICKUP LAYOUT - A method for fabricating a semiconductor device includes forming a plurality of trenches using a first mask. The trenches include source pickup trenches located in outside a termination area and between two adjacent active areas. First and second conductive regions separated by an intermediate dielectric region are formed using a second mask. A first electrical contact to the first conductive region and a second electrical contact to the second conductive region are formed using a third mask and forming a source metal region. Contacts to a gate metal region are formed using a fourth mask. A semiconductor device includes a source pickup contact located outside a termination region and outside an active region of the device. | 09-15-2011 |
20110220991 | SEMICONDUCTOR DEVICE - A semiconductor device | 09-15-2011 |
20110220992 | SEMICONDUCTOR DEVICE - In one aspect, a semiconductor device includes a semiconductor substrate; and a transistor element including a parallel structure of a first-conductivity-type drift region and a second-conductivity-type column region, and a second-conductivity-type base region, the transistor element being formed on the semiconductor substrate. An outer peripheral region located outside an element forming region has a parallel structure of a first-conductivity-type drift region and a second-conductivity-type column region, and a second-conductivity-type annular diffusion region which is formed at a side of the base region and which is spaced apart from the base region. An innermost end and a neighboring portion thereof of the annular diffusion region are located on the column region, and an outermost end of the annular diffusion region is located outside an outermost peripheral column region. A field insulating film that covers the annular diffusion region is stacked on the semiconductor layer in the outer peripheral region. | 09-15-2011 |
20110220993 | METHOD FOR FABRICATING SEMICONDUCTOR MEMOERY DEVICE - A method for manufacturing a semiconductor device comprises forming a first spacer layer at sidewalls of one or more gate electrodes, forming a trench by etching an isolation insulating layer exposed between the gate electrodes, forming a second spacer layer on sidewalls of the gate electrodes and an inner surface of the trench and forming an interlayer insulating layer between the gate electrodes. | 09-15-2011 |
20110227149 | CLOSED CELL TRENCH POWER MOSFET STRUCTURE AND METHOD TO FABRICATE THE SAME - A closed cell trench MOSFET structure having a drain region of a first conductivity type, a body of a second conductivity type, a trenched gate, and a plurality of source regions of the first conductivity type is provided. The body is located on the drain region. The trenched gate is located in the body and has at least two stripe portions and a cross portion. A bottom of the stripe portions is located in the drain region and a bottom of the cross portion is in the body. The source regions are located in the body and at least adjacent to the stripe region of the trenched gate. | 09-22-2011 |
20110227150 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a semiconductor layer of a first conductivity type, a first semiconductor region, a second semiconductor region, a gate electrode, a first electrode layer, an insulating member and a second electrode layer. The first semiconductor region of a second conductivity type is provided on a surface of the semiconductor layer. The second semiconductor region of the first conductivity type is selectively provided on a surface of the first semiconductor region. The gate electrode opposes the first semiconductor region and the second semiconductor region via a gate insulating film. The first electrode layer is electrically connected to the first semiconductor region and the second semiconductor region. The insulating member is embedded in a recess formed in a surface of the first electrode layer. The second electrode layer is provided on the first electrode layer and the insulating member. | 09-22-2011 |
20110233659 | SEMICONDUCTOR POWER DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor power device is provided, and a manufacturing method thereof includes the following steps. First, a substrate is provided, and an epitaxial layer is formed on the substrate. Then, at least a first trench and at least a second trench are formed in the epitaxial layer. Subsequently, a shield electrode and a termination electrode are respectively formed in the first trench and the second trench, and upper sidewalls of the first trench and the second trench are exposed. Following that, a gate dielectric layer is covered. Then, a second conductive layer is deposited to fill up the first trench and partially fill in the second trench. Subsequently, the second conductive layer is etched to remove the second conductive layer in the second trench and form a gate electrode in the first trench. Accordingly, the present invention can reduce the number of masks. | 09-29-2011 |
20110233660 | SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF - A downwardly convex bowed shape is given to an upper edge Tw | 09-29-2011 |
20110233661 | SEMICONDUCTOR MEMORY DEVICE WITH FIN - According to one embodiment, a semiconductor memory device includes a fin-shaped active area, a gate electrode, a silicide layer, and a contact. The fin-shaped active area is provided in a semiconductor substrate and has a first side, a second side parallel to the first side, and a top face connecting the first and second sides. The gate electrode is formed in a trench formed in the active area such that it crosses the trench and is a part of a word line insulated from the active area. The silicide layer is located in the active area on either side of the gate electrode and is formed at least on the first side of the active area serving as a source and a drain region. The contact is connected to the silicide layer and connects at least a storage element. | 09-29-2011 |
20110233662 | SEMICONDUCTOR DEVICE - A semiconductor device may include, but is not limited to: a semiconductor substrate; a bit line; and a contact portion. The semiconductor substrate has a first groove having at least first and second side surfaces facing each other. The bit line is positioned in the first groove. The bit line is insulated from the semiconductor substrate. The contact portion is positioned in the first groove. The contact portion is electrically connected to the bit line. The contact portion contacts the first side surface of the first groove. The contact portion is insulated from the second side surface of the first groove. | 09-29-2011 |
20110241105 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device positioned on an SOI substrate. A semiconductor memory device includes two transistors with three terminals which serve as a source, a reading drain and a writing drain, respectively. The writing drain is heavily-doped for high writing efficiency. A floating body region for storing charges is also heavily-doped to reach long data retention time. | 10-06-2011 |
20110241106 | SEMICONDUCTOR DEVICE WITH BURIED GATES AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a supplementary layer and a silicon layer stacked over a substrate, a trench penetrating the supplementary layer and the silicon layer and formed over the substrate, a gate insulation layer formed along a surface of the trench, and a buried gate formed over the gate insulation layer and filling a portion of the trench. | 10-06-2011 |
20110241107 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Disclosed are a semiconductor device with a metal gate and a method of manufacturing the same. The method of the present invention includes: preparing a semiconductor substrate having a isolation layer to define an active region; forming a gate insulation layer on the semiconductor substrate; sequentially forming a polysilicon layer, a first metal silicide layer, a metal nitride layer and a metal layer on the gate insulation layer including the isolation layer; etching the metal layer and the metal nitride layer so that the metal layer and the metal nitride layer have a narrower width than that of a desired gate; forming a second metal silicide layer on the first metal silicide layer including the etched metal nitride layer and the metal layer; forming a hard mask on the second metal silicide layer so that the hard mask has a desired gate width; and etching the second metal silicide layer, the first metal silicide layer, the polysilicon layer and the gate insulation layer by using the hard mask as an etching barrier, so as to form a metal gate with a structure in. which the metal nitride and the metal layer are enclosed with the first and second metal silicide layers. | 10-06-2011 |
20110248336 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A gate formed in a peripheral region is buried in a semiconductor device such that bit line contact plugs respectively coupled to an active region and the gate are simultaneously formed and a short-circuit between the gate and the bit line contact plug is prevented, thereby improving the characteristics of the device. The method of manufacturing the semiconductor device includes forming a gate buried in a semiconductor substrate, and forming a first bit line contact plug coupled to the gate and a second bit line contact plug coupled to the semiconductor substrate. | 10-13-2011 |
20110248337 | Field effect transistor - A material of a gate electrode is a conductive oxide having a higher work function than that of conventionally used Pd and so on, thereby achieving a normally-off transistor without reducing the sheet carrier concentration of a heterojunction. It is thus possible to achieve a normally-off operation while reducing an increase in the specific on-state resistance. | 10-13-2011 |
20110248338 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a substrate where an isolation region and an active region are defined, an anti-interference layer formed over the substrate in the isolation region, and a gate line simultaneously crossing the active region and the anti-interference layer. | 10-13-2011 |
20110254082 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A semiconductor device includes a conductive pattern formed on the substrate; an interlayer dielectric layer formed on the conductive pattern; a contact plug connected to the conductive pattern extending through the interlayer dielectric layer; a semiconductor layer and an insulating layer sequentially formed on the interlayer dielectric layer; an electrode pattern formed on the insulating layer; and a capping insulating layer pattern covering upper portions of neighboring electrode patterns with the contact plug. An additional process is not needed to define an active region. An active region apart from the gate patter is not needed. A storage electrode contact line does not need to be formed. A height of a landing plug is reduced to reduce the landing plug resistance. A junction region does not need to be formed. | 10-20-2011 |
20110254083 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A semiconductor device including a buried gate and a method for forming the same are disclosed. The semiconductor device includes a buffer layer formed on a surface of a trench in a semiconductor substrate, and a gate electrode configured to partially bury the trench and formed of the same material as in the buffer layer. | 10-20-2011 |
20110254084 | STRUCTURES AND METHODS OF FABRICATING DUAL GATE DEVICES - First polysilicon (poly-1) is deposited into deep trenches that have been formed in a substrate. A first polysilicon polishing process is performed to planarize the exposed surfaces of the poly-1 so that the surfaces are flush with adjacent surfaces. Then, shallow trenches are formed in the substrate between the deep trenches, and second polysilicon (poly-2) is deposited into the shallow trenches. A second polysilicon polishing process is performed to planarize the exposed surface of the poly-2 so that the surface is flush with adjacent surfaces. Metal contacts to the poly-1 and the poly-2 are then formed. | 10-20-2011 |
20110254085 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING REDUCED UNIT CELL AREA AND METHOD FOR MANUFACTURING THE SAME - A semiconductor integrated circuit device includes a semiconductor substrate; a plurality of word lines extending parallel to one another on the semiconductor substrate; a plurality of bit lines extending parallel to one another on the semiconductor substrate and arranged to intersect the word lines, thereby delimiting a plurality of crossing regions and a plurality of unit memory cells; a plurality of gate electrodes formed to control respective pairs of unit memory cells adjacent to each other with the word lines interposed therebetween and to contact corresponding word lines on one sides of the crossing regions; storage node contacts respectively formed in spaces of the unit memory cells; and a plurality of bit line contacts formed to contact the respective bit lines on one sides of the crossing regions. | 10-20-2011 |
20110254086 | SHIELDED TRENCH MOSFET WITH MULTIPLE TRENCHED FLOATING GATES AS TERMINATION - A trench MOSFET comprising a plurality of transistor cells having shielded trenched gates and multiple trenched floating gates as termination region is disclosed. The trenched floating gates have trench depth equal to or deeper than body junction depth of body regions in termination area. In some preferred embodiments, the trenched floating gates in the termination area are implemented by using shielded electrode structure. | 10-20-2011 |
20110260238 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURINMG THE SAME - A semiconductor device comprises: a semiconductor substrate including an active region defined as a device isolation film; a bit line contact hole obtained by etching the semiconductor substrate; a bit line contact plug having a smaller width than that of the bit line contact hole; and a bit line connected to the upper portion of the bit line contact plug, thereby preventing a short of the bit line contact plug and the storage node contact plug to improve characteristics of the semiconductor device. | 10-27-2011 |
20110260239 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes a first capacitive insulating film, a semiconductor region, a gate insulating film, and a gate electrode. The semiconductor region has a groove. The gate insulating film covers a surface of the groove. The gate electrode is in the groove. The gate electrode includes first and second conductive films. The first conductive film is in contact with the gate insulating film. The first conductive film has an upper surface which is higher than a close portion of the second conductive film. The close portion is closer to the upper surface of the first conductive film. | 10-27-2011 |
20110260240 | Semiconductor Device - Disclosed herein are a semiconductor device and a method for manufacturing the same. The method includes forming a gate structure using a carbon nano tube (CNT). In order to prevent reduction of the gate resistance and the short channel effect, a CNT gate having a grown CNT pattern with a half-cylinder shape is formed over a recess of a semiconductor substrate. The CNT gate has the same effect as a recess gate, and can prevent the short channel effect, improve the speed, and the lower power characteristic of semiconductor devices. | 10-27-2011 |
20110260241 | Semiconductor Power Device Having a Top-side Drain Using a Sinker Trench - A semiconductor power device includes a plurality of groups of stripe-shaped gate trenches extending in a silicon region over a substrate, and a plurality of stripe-shaped sinker trenches each extending between two adjacent groups of the plurality of groups of stripe-shaped gate trenches. The plurality of stripe-shaped sinker trenches extend from a top surface of the silicon region through the silicon region and terminate within the substrate. The plurality of stripe-shaped sinker trenches are lined with an insulator along the sinker trench sidewalls so that a conductive material filling each sinker trench makes electrical contact with the substrate along the bottom of the sinker trench and makes electrical contact with an interconnect layer along the top of the sinker trench. | 10-27-2011 |
20110266616 | TRENCHED POWER SEMICONDUCTOR STRUCTURE WITH REDUCED GATE IMPEDANCE AND FABRICATION METHOD THEREOF - A trenched power semiconductor structure with reduced gate impedance and a fabrication method thereof is provided. The trenched power semiconductor structure has a silicon base, a gate trench, a gate oxide layer, and a gate polysilicon structure. The gate trench is formed in the silicon base and extended to an upper surface of the silicon base. The gate oxide layer is formed at least on the inner surface of the gate trench. The gate polysilicon structure is formed in the gate trench with a protruding portion extended form the upper surface of the semiconductor substrate upward. A concave is formed on a sidewall of the protruding portion to expose the upper surface of the silicon base adjacent to the gate trench. | 11-03-2011 |
20110266617 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Provided is a technology, in a semiconductor device having a power MISFET and a Schottky barrier diode on one semiconductor substrate, capable of suppressing a drastic increase in the on-resistance of the power MISFET while making the avalanche breakdown voltage of the Schottky barrier diode greater than that of the power MISFET. In the present invention, two epitaxial layers, one having a high doping concentration and the other having a low doping concentration, are formed over a semiconductor substrate and the boundary between these two epitaxial layers is located in a region equal in depth to or shallower than the bottom portion of a trench. | 11-03-2011 |
20110272759 | Vertical LDMOS device and method for fabricating same - A vertically arranged laterally diffused metal-oxide-semiconductor (LDMOS) device comprises a trench extending into a semiconductor body toward a semiconductor substrate. The trench includes sidewalls, a bottom portion connecting the sidewalls, a dielectric material lining the trench and a diffusion agent layer lining the dielectric material. A lightly doped drain region adjoins the trench and extends laterally around the sidewalls from the diffusion agent layer into the semiconductor body. In one embodiment, a method for fabricating a vertically arranged LDMOS device comprises forming a trench extending into a semiconductor body toward a semiconductor substrate, the trench including sidewalls, a bottom portion connecting the sidewalls, a dielectric material lining the trench and a diffusion agent layer lining the dielectric material. The method further comprises diffusing impurities from the diffusion agent layer through the dielectric material to form a lightly doped drain region extending laterally around the sidewalls into the semiconductor body. | 11-10-2011 |
20110272760 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes, on a semiconductor substrate, an active region surrounded by an STI region, a gate trench formed in one direction transverse to the active region, a gate insulating film formed on a side surface of the gate trench, an insulating film formed on a bottom of the gate trench and thicker than the gate insulating film, and a gate electrode having at least a part of the gate electrode formed in the gate trench. Portions of the semiconductor substrate present in the active region and located on both sides of the gate trench in an extension direction of the gate trench function as a source region and a drain region, respectively. A portion of the semiconductor substrate located between the side surface of the active region (the side of the STI region) and the side surface of the gate trench functions as a channel region. | 11-10-2011 |
20110278662 | SEMICONDUCTOR DEVICE INCLUDING RECESSED CHANNEL TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - A semiconductor device including a recessed channel transistor, and a method of manufacturing the same, provide: a substrate in which an isolation trench is provided; an isolation layer provided in the isolation trench so as to define a pair of source/drain regions in the substrate; a gate pattern provided in the isolation trench between the pair of source/drain regions, the gate pattern having a top surface at a same level as a top surface of the isolation layer and having a bottom surface at a lower depth than the pair of source/drain regions with respect to a top surface of the substrate; and a gate insulating layer provided between the substrate and the gate pattern at a bottom surface of the isolation trench. | 11-17-2011 |
20110278663 | Semiconductor device - The semiconductor device of the present invention includes a first conductive type semiconductor layer; a second conductive type source region formed in a surface layer portion of the semiconductor layer; a groove formed by digging in the source region from a surface thereof; an insulating film laminated on the semiconductor layer to cover a surface of the semiconductor layer; a contact hole penetrating through the insulating film in a layer thickness direction at least at a position facing the groove; a wiring formed on the insulating film; and a contact plug embedded in the contact hole so that a bottom portion thereof enters the groove to electrically connect the wiring and the source. | 11-17-2011 |
20110278664 | Semiconductor device - An inventive semiconductor device includes: a semiconductor layer; a drift region of a first conductivity type provided in the semiconductor layer; a body region of a second conductivity type provided on the drift region in the semiconductor layer; a trench extending from a surface of the body region in the semiconductor layer with its bottom located in the drift region; a gate insulation film provided on an interior surface of the trench; a gate electrode provided in the trench with the intervention of the gate insulation film; a source region of the first conductivity type provided in the surface of the body region; a first impurity region of the second conductivity type provided around the bottom of the trench in spaced relation from the body region; and a second impurity region of the second conductivity type provided on a lateral side of the body region in the semiconductor layer, the second impurity region being isolated from the body region and electrically connected to the first impurity region. | 11-17-2011 |
20110278665 | HIGH-MOBILITY TRENCH MOSFETS - High-mobility vertical trench DMOSFETs and methods for manufacturing are disclosed. A source region, a drain region or a channel region of a high-mobility vertical trench DMOSFET may comprise silicon germanium (SiGe) that increases the mobility of the charge carriers in the channel region. In some embodiments the channel region may be strained to increase channel charge carriers mobility. | 11-17-2011 |
20110284950 | Method for fabricating a shallow and narrow trench FETand related structures - Disclosed is a method for fabricating a shallow and narrow trench field-effect transistor (trench FET). The method includes forming a trench within a semiconductor substrate of a first conductivity type, the trench including sidewalls and a bottom portion. The method further includes forming a substantially uniform gate dielectric in the trench, and forming a gate electrode within said trench and over said gate dielectric. The method also includes doping the semiconductor substrate to form a channel region of a second conductivity type after forming the trench. In one embodiment, the doping step is performed after forming the gate dielectric and after forming the gate electrode. In another embodiment, the doping step is performed after forming the gate dielectric, but prior to forming the gate electrode. Structures formed by the invention's method are also disclosed. | 11-24-2011 |
20110284951 | Semiconductor device and method of manufacturing the semiconductor device - A semiconductor device includes a transistor that has a trench formed in an element forming region of a substrate, a gate insulating film formed on side faces and a bottom face of the trench, a gate electrode formed on the gate insulating film so as to bury the trench, a source region formed on one side in the gate longitude direction, which is formed on the surface of the substrate, and a drain region formed on the other side in the gate longitude direction. Here, the gate electrode is formed so as to be exposed also on the substrate outside the trench, and the gate electrode is disposed so as to cover upper portions of both ends of the trench and so as to form at least one concave portion having a depth reaching the substrate in a center portion. | 11-24-2011 |
20110284952 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a transistor having multiple trenches with the thickness thereof being intermittently changed in the lateral direction of a gate, a gate insulating film formed on the side walls and at the bottom of each of the trenches, a gate electrode formed over the gate insulating film, a source region formed in the surface of the substrate on one side in the longitudinal direction of the gate, and a drain region formed in the surface of the substrate on the other side in the longitudinal direction of the gate. The thickness of the gate insulating film in the lower portion of the side wall of the trench from an intermediate position directing from the surface of the substrate to the bottom of the trench to the bottom thereof is larger than the thickness of the gate insulating film in the upper portion on the side wall of the trench from the intermediate position directing from the surface of the substrate to the bottom of the trench and equal with or larger than the thickness of the gate insulating film at the bottom of the trench. | 11-24-2011 |
20110291183 | POWER SEMICONDUCTOR DEVICE HAVING LOW GATE INPUT RESISTANCE AND MANUFACTURING METHOD THEREOF - A power semiconductor device having low gate input resistance and a manufacturing method thereof are provided. The power semiconductor device includes a substrate, at least a trench transistor, a conductive layer, a metal contact plug, an insulating layer, an interlayer dielectric, a gate metal layer, and a source metal layer. The metal contact plug can serve as a buried gate metal bus line, and the metal contact plug can pass under the source metal layer and keeps the area of the source metal layer complete. Accordingly, the present invention can provide a lower gate input resistance without dividing the source metal layer, so the source metal layer can have a larger and complete area for the following packaging and bonding process. | 12-01-2011 |
20110291184 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - The present application discloses a semiconductor structure and a method for manufacturing the same. The semiconductor structure comprises a semiconductor substrate; an epitaxial semiconductor layer formed on two side portions of the semiconductor substrate; a gate stack formed at a central position on the semiconductor substrate and abutting the epitaxial semiconductor layer, the gate comprising a gate conductor layer and a gate dielectric layer which is sandwiched between the gate conductor layer and the semiconductor substrate and surrounding the lateral surfaces of the gate conductor layer; and a sidewall spacer formed on the epitaxial semiconductor layer and surrounding the gate. The method for manufacturing the above semiconductor structure comprises forming raised source/drain regions in the epitaxial semiconductor layer utilizing the sacrificial gate. The semiconductor structure and the method for manufacturing the same can simplify the fabrication process for an ultra-thin SOI transistor and reduce the ON-state resistance and power consumption of the transistor. | 12-01-2011 |
20110298041 | SINGLE-GATE FINFET AND FABRICATION METHOD THEREOF - A single-gate FinFET structure includes an active fin structure having two enlarged head portions and two respective tapered neck portions that connect the enlarged head portions with an underlying ultra-thin body. Two source/drain regions are doped in the two enlarged head portions respectively. An insulation region is interposed between the two source/drain regions. A trench isolation structure is disposed at one side of the tuning fork-shaped fin structure. A single-sided sidewall gate electrode is disposed on a vertical sidewall of the active fin structure opposite to the trench isolation structure. | 12-08-2011 |
20110298042 | POWER SEMICONDUCTOR DEVICE WITH TRENCH BOTTOM POLYSILICON AND FABRICATION METHOD THEREOF - A power semiconductor device comprising a base, a trench, a heavily doped polysilicon structure, a polysilicon gate, a gate dielectric layer, and a heavily doped region is provided. The trench is formed in the base. The heavily doped polysilicon structure is formed in the lower portion of the trench. At least a side surface of the heavily doped polysilicon structure touches the naked base. The polysilicon gate is located in the upper portion of the trench. The gate dielectric layer is interposed between the polysilicon gate and the heavily doped polysilicon structure. The dopants in the heavily doped polysilicon structure are diffused outward to form a heavily doped region. | 12-08-2011 |
20110298043 | Semiconductor Device Structures and Related Processes - Improved highly reliable power RFP structures and fabrication and operation processes. The structure includes plurality of localized dopant concentrated zones beneath the trenches of RFPs, either floating or extending and merging with the body layer of the MOSFET or connecting with the source layer through a region of vertical doped region. This local dopant zone decreases the minority carrier injection efficiency of the body diode of the device and alters the electric field distribution during the body diode reverse recovery. | 12-08-2011 |
20110298044 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The semiconductor device according to the present invention includes a semiconductor layer, a trench formed by digging the semiconductor layer from the surface thereof, a gate insulating film formed on the inner surface of the trench, and a gate electrode made of silicon embedded in the trench through the gate insulating film. The gate electrode has a high-conductivity portion formed to cover the gate insulating film with a relatively high conductivity and a low-conductivity portion formed on a region inside the high-conductivity portion with a relatively low conductivity. | 12-08-2011 |
20110303975 | Field effect transistor with self-aligned source and heavy body regions - A field effect transistor includes a plurality of trenches extending into a semiconductor region of a first conductivity type. The plurality of trenches includes a plurality of gated trenches and a plurality of non-gated trenches. A body region of a second conductivity extends in the semiconductor region between adjacent trenches. A dielectric material fills a bottom portion of each of the gated and non-gated trenches. A gate electrode is disposed in each gated trench. A conductive material of the second conductivity type is disposed in each non-gated trench such that the conductive material and contacts corresponding body regions along sidewalls of the non-gated trench. | 12-15-2011 |
20110309435 | BURIED GATE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a buried gate in a semiconductor substrate, and a nitride layer, over at least the buried gate, whose upper portion is at substantially the same height as an upper portion of a peripheral bit line, where the peripheral bit line is over an interlayer insulating layer. The thickness of the nitride layer is substantially equal to the stacked thickness of the peripheral bit line and the interlayer insulating layer. | 12-22-2011 |
20110309436 | POWER SEMICONDUCTOR DEVICE - A gate electrode is provided for controlling a current flowing through a semiconductor layer. A gate insulating film electrically insulates the semiconductor layer and the gate electrode from each other. A conductor portion is provided on the semiconductor layer, and electrically connected with the semiconductor layer. An interlayer insulating film is provided on the gate electrode such that the conductor portion is electrically insulated from the gate electrode. A buffer insulating film covers a partial region on the conductor portion and the interlayer insulating film, and is made of an insulator. An electrode layer has a wiring portion located on a region from which the conductor portion is exposed, and a pad portion located on the buffer insulating film. Thereby, damage to an IGBT caused when a wire is connected to the pad portion can be suppressed. Further, larger electric power can be handled, while preventing occurrence of breakage due to current concentration. | 12-22-2011 |
20110316074 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A shape of an upper edge of a trench is realized as an upwardly-open tapered surface T | 12-29-2011 |
20110316075 | TRENCH MOSFET WITH TRENCHED FLOATING GATES HAVING THICK TRENCH BOTTOM OXIDE AS TERMINATION - A power semiconductor power device having composite trench bottom oxide and multiple trench floating gates is disclosed. The gate charge is reduced by forming a pad oxide surrounding a HDP oxide on trench bottom. The multiple trenched floating gates are applied in termination for saving body mask. | 12-29-2011 |
20120001257 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A downsized semiconductor device having an excellent reverse characteristic, and a method of manufacturing the semiconductor device is sought to improve. The semiconductor device comprises a semiconductor body having a polygonal contour. An active area is formed in the semiconductor body. An EQR electrode is formed so as to surround the active area and to have curved portions of the EQR electrode along the corners of the semiconductor body. An interlayer insulating film is formed to cover the active area and the EQR electrode. The EQR electrode is embedded in the interlayer insulating film around the active area. EQR contacts are in contact with the curved portions of the EQR electrode and the semiconductor body outside the curved portions, and have at least side walls covered with the interlayer insulating film. | 01-05-2012 |
20120001258 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a gate metal buried within a trench included in a semiconductor substrate including an active region defined by an isolation layer, a spacer pattern disposed on an upper portion of a sidewall of a gate metal, a first gate oxide layer disposed between the spacer pattern and the trench, a second gate oxide layer disposed below the first gate oxide layer and the gate metal, and a junction region disposed in the active region to overlap the first gate oxide layer. | 01-05-2012 |
20120007170 | High source to drain breakdown voltage vertical field effect transistors - An increase source to drain breakdown voltage vertical channel transistors device having a structure that is similar to that of a conventional metal oxide semiconductor field effect transistor (MOSFET), in that it includes a source, a drain, a gate and a body. According the N+N− and P+P− junction theory of semiconductor, add to N− junction between the source N+ junction to P junction of N-Channel MOSFET; add to P− junction between the source P+ junction to n junction of P-Channel MOSFET; With the proposed MOSFET of which the source to drain breakdown voltage are increase may be achieved. | 01-12-2012 |
20120007171 | SEMICONDUCTOR MEMORY DEVICE HAVING VERTICAL TRANSISTOR AND BURIED BIT LINE AND METHOD FOR FABRICATING THE SAME - A semiconductor memory device includes an active region protruding upward from a substrate, wherein the active region is arranged next to a trench on the substrate, a first impurity region formed at an upper portion of the active region, a second impurity region formed at a lower portion of the active region, a gate dielectric layer formed along a side of the active region between the first impurity region and the second impurity region, a gate electrode layer formed on the gate dielectric layer, a buried bit line formed at a lower portion of the trench, and a polysilicon layer formed over the buried bit line, wherein the polysilicon layer electrically connects the buried bit line with the second impurity region. | 01-12-2012 |
20120007172 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes an active region formed to be sloped or tilted by α° (where 0°<α°<90°) from the bottom of a semiconductor substrate, at least one gate that is formed over the sloped active region and has a surface parallel to the bottom of the semiconductor substrate, and a landing plug that is coupled to the active region and is located between the gates. As a result, the area of the active region is increased thus increasing a channel width, so that the operation of the semiconductor device can be improved as the integration degree of the semiconductor device is rapidly increased. | 01-12-2012 |
20120007173 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor device includes: a substrate; multiple first and second conductive type regions on the substrate for providing a super junction structure; a channel layer on the super junction structure; a first conductive type layer in the channel layer; a contact second conductive type region in the channel layer; a gate electrode on the channel layer via a gate insulation film; a surface electrode on the channel layer; a backside electrode on the substrate opposite to the super junction structure; and an embedded second conductive type region. The embedded second conductive type region is disposed in a corresponding second conductive type region, protrudes into the channel layer, and contacts the contact second conductive type region. The embedded second conductive type region has an impurity concentration higher than the channel layer, and has a maximum impurity concentration at a position in the corresponding second conductive type region. | 01-12-2012 |
20120007174 | Semiconductor device and method of manufacturing the same - The semiconductor device includes a trench having a depth of a distance equal to or shorter than the L length of the transistor, and a buried layer is used in a bottom portion of the trench, whereby an effective channel length from each of a lower end of a high concentration source diffusion layer and a lower end of a high concentration drain diffusion layer to a bottom surface of the trench is made shorter than the shortest length L on a top surface of the trench. Accordingly, a current path is held on the bottom surface of the trench from a side surface thereof which contacts with the source or high concentration drain diffusion layer with a use of the buried layer, whereby the driving performance is enhanced. An effect of suppressing the decrease of the driving performance is obtained for the reduced gate length. | 01-12-2012 |
20120007175 | Metal Oxide Semiconductor (MOS) Transistors Having a Recessed Gate Electrode - A metal oxide semiconductor (MOS) includes an isolation layer disposed in a semiconductor substrate to define an active region. A source region and a drain region are disposed on both sides of the active region such that a first direction is defined from the source region to the drain region. A channel recess is disposed in the active region between the source and drain regions. The channel recess has a convex surface when viewed from a cross-sectional view taken along a second direction orthogonal to the first direction. A gate electrode fills the channel recess and crosses the active region in the second direction. A gate insulating layer is interposed between the gate electrode and the active region. | 01-12-2012 |
20120012924 | Vertical Transistor Component - A vertical transistor component is produced by providing a semiconductor body with a first surface and a second surface, producing at least one gate contact electrode in a trench, the trench extending from the first surface through the semiconductor body to the second surface, and producing at least one gate electrode connected to the at least one gate contact electrode in the region of the first surface. | 01-19-2012 |
20120012925 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method for manufacturing the same are provided. The method etches a gate metal material of a sidewall of the active region connected to the storage node contact deeper than a gate metal material of a sidewall of the active region connected to the bit line contact in a buried gate structure to prevent GILD and to reduce resistance of a buried gate, thereby improving refresh characteristics of the semiconductor device. | 01-19-2012 |
20120012926 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor memory device includes defining an active region having a shape protruding upward by forming a trench in a semiconductor substrate; forming an open region obtained by selectively exposing a lower side portion of the active region while forming a sidewall layer along the shape of the active region; covering the open region with a silicon layer; forming an impurity region in the lower side portion of the active region; forming a barrier metal layer on the silicon layer and the active region; forming a bit line metal layer buried in the entire active region; and forming a buried bit line having the barrier metal layer, the bit line metal layer and a silicide metal layer formed between the silicon layer and the barrier metal layer by etching the bit line metal layer up to a portion at which the impurity region is formed. | 01-19-2012 |
20120012927 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes: a cell gate trench with a bottom face and first/second side faces; a field-shield gate trench narrower than the cell gate trench; a first upper diffusion layer between the cell gate trench and the field-shield gate trench; a second upper diffusion layer on the opposite side of the cell gate trench from the first upper diffusion layer; a third upper diffusion layer on the opposite side of the field-shield gate trench from the first upper diffusion layer; a lower diffusion layer on the bottom face of the cell gate trench; first and second storage elements electrically connected to the first and second upper diffusion layers, respectively; a bit line electrically connected to the lower diffusion layer; a word line covering first and second side faces via a gate insulating film; and a field-shield gate electrode in the field-shield gate trench via a gate insulating film. | 01-19-2012 |
20120012928 | TRANSISTOR INCLUDING BULB-TYPE RECESS CHANNEL AND METHOD FOR FABRICATING THE SAME - A method for fabricating a transistor including a bulb-type recess channel includes forming a bulb-type recess pattern in a substrate, forming a gate insulating layer over the substrate and the bulb-type recess pattern, forming a first gate conductive layer over the gate insulating layer, forming a void movement blocking layer over the first gate conductive layer in the bulb-type recess pattern, and forming a second gate conductive layer over the void movement blocking layer and the first gate conductive layer. | 01-19-2012 |
20120018800 | Trench Superjunction MOSFET with Thin EPI Process - Methods for fabricating MOSFET devices with superjunction having high breakdown voltages (>600 volts) with competitively low specific resistance include growing an epitaxial layer of a second conductivity type on a substrate of a first conductivity type, forming a trench in the epitaxial layer, and growing a second epitaxial layer along the sidewalls and bottom of the trench. The second epitaxial layer is doped with a dopant of first conductivity type. MOSFET devices with superjunction having high breakdown voltages include a first epitaxial layer of a second conductivity type disposed over a substrate of a first conductivity type and a trench formed in the epitaxial layer. The trench includes a second epitaxial layer grown along the sidewalls and bottom of the trench. | 01-26-2012 |
20120025299 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH BURIED GATES - A method for fabricating a semiconductor device includes forming an insulation layer, hydroxylating a surface of the insulation layer by performing a pre-treatment, forming an adhesive layer over the insulation layer, performing a post-treatment, and forming a conductive layer over the adhesive layer. | 02-02-2012 |
20120025300 | Semiconductor Devices Including Vertical Channel Transistors And Methods Of Manufacturing The Same - A semiconductor device including a plurality of buried word lines extending in a first direction and a plurality of buried bit lines extending in a second direction. Upper surfaces of the plurality of buried word lines and the plurality of buried bit lines are lower than an upper surface of a substrate. The distance between two active regions that constitute a pair of first active regions from among a plurality of first active regions included in a first group of active regions is less than the distance between two adjacent active regions having the plurality of buried bit lines therebetween. A method of manufacturing a semiconductor device includes forming a plurality of first trenches in a substrate, forming a plurality of first conductive patterns in the plurality of first trenches in such a manner that a pair of first conductive patterns is disposed in each of the plurality of first trenches, forming a plurality of first buried patterns in the plurality of first trenches to cover the plurality of first conductive patterns, forming a plurality of second trenches by etching the substrate between the plurality of first trenches, and forming a plurality of second buried patterns in the plurality of second trenches. | 02-02-2012 |
20120025301 | Inverted-trench grounded-source FET structure with trenched source body short electrode - This invention discloses bottom-source lateral diffusion MOS (BS-LDMOS) device. The device has a source region disposed laterally opposite a drain region near a top surface of a semiconductor substrate supporting a gate thereon between the source region and a drain region. The BS-LDMOS device further has a combined sinker-channel region disposed at a depth in the semiconductor substrate entirely below a body region disposed adjacent to the source region near the top surface wherein the combined sinker-channel region functioning as a buried source-body contact for electrically connecting the body region and the source region to a bottom of the substrate functioning as a source electrode. A drift region is disposed near the top surface under the gate and at a distance away from the source region and extending to and encompassing the drain region. The combined sinker-channel region extending below the drift region and the combined sinker-channel region that has a dopant-conductivity opposite to and compensating the drift region for reducing the source-drain capacitance. | 02-02-2012 |
20120025302 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device according to the present invention includes: a semiconductor layer made of silicon; a trench formed by digging in from a top surface of the semiconductor layer; a gate insulating film formed on an inner wall surface of the trench and made of silicon oxide; a gate electrode embedded in the trench via the gate insulating film and made of a polysilicon doped with an impurity; and an oxidation-resistant metal film disposed on a top surface of the gate electrode and covering the top surface. | 02-02-2012 |
20120025303 | SEMICONDUCTOR DEVICE AND METHOD FOR THE PRODUCTION OF A SEMICONDUCTOR DEVICE - In one embodiment, a field effect transistor has a semiconductor body, a drift region of a first conductivity type and a gate electrode. At least one trench extends into the drift region. A field plate is arranged at least in a portion of the at least one trench. A dielectric material at least partially surrounds both the gate electrode and the field plate. The field plate includes a first semiconducting material. | 02-02-2012 |
20120032256 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device includes a first island and a first electrode. The first island includes a first semiconductor region, a first insulation region, and a first insulating film. The first semiconductor region has first and second side surfaces adjacent to the first insulation region and the first insulating film, respectively. The first electrode is adjacent to the first insulation region and the first insulating film. The first insulating film is between the first electrode and the first semiconductor region. | 02-09-2012 |
20120032257 | Dual Work Function Recessed Access Device and Methods of Forming - A recessed access device having a gate electrode formed of two or more gate materials having different work functions may reduce the gate-induced drain leakage current losses from the recessed access device. The gate electrode may include a first gate material having a high work function disposed in a bottom portion of the recessed access device and a second gate material having a lower work function disposed over the first gate material and in an upper portion of the recessed access device. | 02-09-2012 |
20120032258 | Semiconductor Device Structures and Related Processes - Improved highly reliable power RFP structures and fabrication and operation processes. The structure includes plurality of localized dopant concentrated zones beneath the trenches of RFPs, either floating or extending and merging with the body layer of the MOSFET or connecting with the source layer through a region of vertical doped region. This local dopant zone decreases the minority carrier injection efficiency of the body diode of the device and alters the electric field distribution during the body diode reverse recovery. | 02-09-2012 |
20120032259 | BOTTOM SOURCE POWER MOSFET WITH SUBSTRATELESS AND MANUFACTURING METHOD THEREOF - A bottom source power metal-oxide-semiconductor field-effect transistor (MOSFET) device includes a gate electrode and a source electrode formed on an initial insulation layer on a first surface of a semiconductor chip and a drain electrode formed on a second surface of the semiconductor chip. The source electrode includes a source metal, a source electrode bump formed on the source metal and a source electrode metal layer on top of the source electrode bump. A first insulation layer covers the gate electrode. A through via aligned to the gate electrode is formed from the second surface of the chip to expose a portion of the gate electrode from the second surface. | 02-09-2012 |
20120032260 | ELECTRONIC DEVICE WITH CONNECTING STRUCTURE - A semiconductor device including a connecting structure includes an edge region, a first trench and a second trench running toward the edge region, a first electrode within the first trench, and a second electrode within the second trench, the first and second electrodes being arranged in a same electrode plane with regard to a main surface of a substrate of the electronic device within the trenches, and the first electrode extending, at an edge region side end of the first trench, farther toward the edge region than the second electrode extends, at an edge region side end of the second trench, toward the edge region. | 02-09-2012 |
20120037979 | METHOD FOR PRODUCING AN INSULATION LAYER BETWEEN TWO ELECTRODES - Method for producing an insulation layer between a first electrode and a second electrode in a trench of a semiconductor body, wherein the method comprises the following features: providing a semiconductor body with a trench formed therein, wherein a first electrode is formed in a lower part of the trench, producing an insulation layer on the first electrode and at the sidewalls of the trench in an upper part of the trench in such a way that the insulation layer is formed in a U-shaped fashion in the trench, producing a protective layer on the insulation layer at least at the bottom of the remaining void in the trench, removing the insulation layer at the sidewalls of the trench in the upper part of the trench, removing the protective layer, producing a second electrode at least on the insulation layer above the first electrode. | 02-16-2012 |
20120037980 | EDGE TERMINATION REGION - An isolation region ( | 02-16-2012 |
20120037981 | Power Semiconductor Chip with a Formed Patterned Thick Metallization Atop - A method is disclosed for forming a patterned thick metallization atop a semiconductor chip wafer. The method includes fabricating a nearly complete semiconductor chip wafer ready for metallization; depositing a bottom metal layer of sub-thickness TK | 02-16-2012 |
20120037982 | REDUCED PROCESS SENSITIVITY OF ELECTRODE-SEMICONDUCTOR RECTIFIERS - Disclosed are semiconductor devices and methods of making semiconductor devices. An exemplary embodiment comprises a semiconductor layer of a first conductivity type having a first surface, a second surface, and a graded net doping concentration of the first conductivity type within a portion of the semiconductor layer. The graded portion is located adjacent to the top surface of the semiconductor layer, and the graded net doping concentration therein decreasing in value with distance from the top surface of the semiconductor layer. The exemplary device also comprises an electrode disposed at the first surface of the semiconductor layer and adjacent to the graded portion. | 02-16-2012 |
20120043602 | Power MOSFET and Its Edge Termination - Improved MOSFET structures and processes, where multiple polysilicon embedded regions are introduced into the n+ source contact area. A top poly Field Plate is used to shield the electric field from penetrating into the channel, so that a very short channel can be used without jeopardizing the device drain-source leakage current. A bottom poly Field Plate is used to modulate the electric field distribution in the drift region such that a more uniform field distribution can be obtained. | 02-23-2012 |
20120043603 | Method of manufacturing semiconductor device, and semiconductor device - A semiconductor device includes a first-conductivity-type semiconductor layer, a base region of a second-conductivity-type formed in an upper portion of the first-conductivity-type semiconductor layer, first though third trenches penetrating through the base region and reaching to the first-conductivity-type semiconductor layer, the first through third trenches being linked to one another, a source interconnect layer buried in the first through third trenches, the source interconnect layer including a protruding portion, a gate electrode buried in the first trench and the third trench, and formed over the source interconnect layer, a source metal contacting the protruding portion of the source interconnect layer, and a gate metal contacting the gate electrode in the third trench. A contact face between the source metal and the protruding portion at the second trench is formed higher than a contact face between the gate metal and the gate electrode at the third trench. | 02-23-2012 |
20120043604 | Semiconductor device and method for manufacturing the same - A semiconductor device includes a semiconductor layer, a first diffused region formed in the semiconductor layer, a second diffused region formed in the first diffused region, a trench formed in the semiconductor layer, a gate electrode disposed in the trench, a top surface of the gate electrode being lower than a top surface of the semiconductor layer and sagging downwards in a center thereof, a non-doped silicate glass film disposed in the trench and formed over the gate electrode, a top surface of the silicate glass film sagging downwards in a center thereof, an oxide film disposed in the trench and formed over the non-doped silicate glass film, a top surface of the oxide film sagging downwards in a center, and a source electrode formed over the semiconductor layer so that the source electrode contacts the first and second diffusion regions, and the oxide film at the top surface thereof. | 02-23-2012 |
20120056262 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a third semiconductor layer of the first conductivity type, an embedded electrode, a control electrode, a fourth semiconductor layer of the second conductivity type, a first main electrode, and a second main electrode. The second semiconductor layer is provided on the first semiconductor layer. The third semiconductor layer is provided on the second semiconductor layer. The embedded electrode is provided in a first trench via a first insulating film. The first trench penetrates through the second semiconductor layer from a surface of the third semiconductor layer to reach the first semiconductor layer. The control electrode is provided above the embedded electrode via a second insulating film in the first trench. The fourth semiconductor layer is selectively provided in the first semiconductor layer and is connected to a lower end of a second trench. The second trench penetrates through the second semiconductor layer from the surface of the third semiconductor layer to reach the first semiconductor layer. The first main electrode is electrically connected to the first semiconductor layer. The second main electrode is provided in the second trench and connected to the second semiconductor layer, the third semiconductor layer and the fourth semiconductor layer. The embedded electrode is electrically connected to one of the second main electrode and the control electrode. A Schottky junction formed of the second main electrode and the first semiconductor layer is formed at a sidewall of the second trench. | 03-08-2012 |
20120056263 | SEMICONDUCTOR TRENCH ISOLATION INCLUDING POLYSILICON AND NITRIDE LAYERS - A semiconductor device includes a device isolation pattern in which a polysilicon layer pattern doped with oxygen, carbon or nitrogen is interposed between an inner wall of a trench and a nitride liner. The semiconductor device includes a semiconductor substrate including a trench, a polysilicon layer pattern on a surface of the trench, a nitride layer pattern on the polysilicon layer pattern, and an insulation layer pattern on the nitride layer pattern and filling the trench. The polysilicon layer pattern may be doped with oxygen, carbon and/or nitrogen. Related manufacturing methods are also disclosed. | 03-08-2012 |
20120061748 | Semiconductor device and method of manufacturing the same - Provided is a method of manufacturing a vertical MOSFET having a trench structure, which is capable of performing stable processing. While leaving a silicon nitride film ( | 03-15-2012 |
20120061749 | POWER SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - In general, according to one embodiment, a power semiconductor device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a trench, a gate insulating film, and a gate electrode. The second semiconductor layer is provided on the first semiconductor layer. The trench is provided from the second semiconductor layer to the first semiconductor layer. The gate insulating film is composed of an oxide film and a protective layer formed on the oxide film. The protective layer is opposed to the second semiconductor layer across the oxide film in the trench. The oxide film covers the second semiconductor layer exposed at a sidewall of the trench and includes at least one of aluminum and yttrium. The gate electrode is made of n-type polysilicon buried in the trench in direct contact with the gate insulating film. | 03-15-2012 |
20120061750 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method for manufacturing the same are disclosed. A recess gate structure is formed between an overlapping region between a gate and a source/drain so as to suppress increase in gate induced drain leakage (GIDL), and a gate insulation film is more thickly deposited in a region having weak GIDL, thereby reducing GIDL and thus improving refresh characteristics due to leakage current. | 03-15-2012 |
20120061751 | RECESSED MEMORY CELL ACCESS DEVICES AND GATE ELECTRODES - Recessed access transistor devices used with semiconductor devices may include gate electrodes having materials with multiple work functions, materials that are electrically isolated from each other and supplied with two or more voltage supplies, or materials that create a diode junction within the gate electrode. | 03-15-2012 |
20120061752 | SINGLE TRANSISTOR FLOATING-BODY DRAM DEVICES HAVING VERTICAL CHANNEL TRANSISTOR STRUCTURES - Single transistor floating-body DRAM devices have a vertical channel transistor structure. The DRAM devices include a substrate, and first and second floating bodies disposed on the substrate and isolated from each other. A source region and a drain region are disposed under and above each of the first and second floating bodies. A gate electrode is disposed between the first and second floating bodies. Methods of fabricating the single transistor floating-body DRAM devices are also provided. | 03-15-2012 |
20120068260 | Method for producing a structure element and semiconductor component comprising a structure element - A semiconductor component includes a semiconductor body having a surface and a cutout in the semiconductor body. The cutout extends from the surface of the semiconductor body into the semiconductor body in a direction perpendicular to the surface. The cutout has a base and at least one sidewall. The component further includes a layer on the surface of the semiconductor body and in the cutout. The layer forms a well above the cutout. The well has a well base, a well edge and at least one well sidewall. The at least one well sidewall forms an angle α in the range of 20° to 80° with respect to the surface of the semiconductor body. The layer has at least one edge which, proceeding from the well edge, extends in the direction of the surface of the semiconductor body. | 03-22-2012 |
20120074489 | SUPER-JUNCTION TRENCH MOSFET WITH RESURF STEPPED OXIDES AND TRENCHED CONTACTS - A super-junction trench MOSFET with Resurf Stepped Oxide and trenched contacts is disclosed. The inventive structure can apply additional freedom for better optimization and manufacturing capability by tuning thick oxide thickness to minimize influence of charge imbalance, trapped charges, etc. . . . Furthermore, the fabrication method can be implemented more reliably with lower cost. | 03-29-2012 |
20120080747 | Semiconductor Device - A vertical transistor of a semiconductor device has a channel area formed in a vertical direction to a semiconductor substrate. After semiconductor poles corresponding to the length of semiconductor channels and gate electrodes surrounding sidewalls of the semiconductor poles are formed, subsequent processes of forming silicon patterns corresponding to junction areas, etc. are performed. The gate electrodes support the semiconductor poles during these subsequent processes. The height of the semiconductor poles corresponding to the length of the channel is increased, yet the semiconductor poles do not collapse or incline since the gate electrodes support the semiconductor poles. | 04-05-2012 |
20120086073 | POWER SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A vertical power semiconductor device includes a first semiconductor layer of a first conductivity type formed in both a cell section and a termination section, the termination section surrounding the cell section, a second semiconductor layer of a second conductivity type formed on the first semiconductor layer in the cell section, a third semiconductor layer of the first conductivity type formed in part on the second semiconductor layer, and a guard ring layer of the second conductivity type formed on the first semiconductor layer in the termination section. Net impurity concentration in the guard ring layer is generally sloped so as to be relatively high on its lower side and relatively low on its upper side. Alternatively, the net impurity concentration in the guard ring layer is constant. | 04-12-2012 |
20120091522 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a first semiconductor layer formed over a substrate, a second semiconductor layer formed over the first semiconductor layer, a source electrode and a drain electrode formed over the second semiconductor layer, an insulating film formed over the second semiconductor layer, a gate electrode formed over the insulating film, and a protection film covering the insulating film, the protection film being formed by thermal CVD, thermal ALD, or vacuum vapor deposition. | 04-19-2012 |
20120091523 | TRENCH MOSFET WITH TRENCH CONTACT HOLES AND METHOD FOR FABRICATING THE SAME - A trench MOSFET with trench contact holes and a method for fabricating the same are disclosed. The MOSFET includes an N type substrate, an N type epitaxial layer on the substrate; a P well region on top of the epitaxial layer; a source region formed on the P well region; an oxide layer on the source region; a plurality of trenches which traverse the source region and the P well region and contact the epitaxial layer; a gate oxide layer and polysilicon formed in the trenches; a source contact hole and a gate contact hole, wherein the source contact hole and the gate contact hole have a titanium metal layer, a titanium nitride layer, and tungsten metal sequentially, respectively; a P+ implanted region; a source electrode formed above the source contact hole and a gate electrode formed above the gate contact hole. | 04-19-2012 |
20120098055 | Power Semiconductor Devices, Structures, and Related Methods - Power semiconductor devices, and related methods, where majority carrier flow is divided into paralleled flows through two drift regions of opposite conductivity types. | 04-26-2012 |
20120098056 | TRENCH DEVICE STRUCTURE AND FABRICATION - A vertical-current-flow device includes a trench which includes an insulated gate and which extends down into first-conductivity-type semiconductor material. A phosphosilicate glass layer is positioned above the insulated gate and a polysilicon layer is positioned above the polysilicate glass layer. Source and body diffusions of opposite conductivity types are positioned adjacent to a sidewall of the trench. A drift region is positioned to receive majority carriers which have been injected by the source, and which have passed through the body diffusion. A drain region is positioned to receive majority carriers which have passed through the drift region. The gate is capacitively coupled to control inversion of a portion of the body region. As an alternative, a dielectric layer may be used in place of the doped glass where permanent charge is positioned in the dielectric layer. | 04-26-2012 |
20120098057 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - Provided are a semiconductor device and a method of fabricating the same. The method includes: forming a trench in a semiconductor substrate of a first conductive type; forming a trench dopant containing layer including a dopant of a second conductive type on a sidewall and a bottom surface of the trench; forming a doping region by diffusing the dopant in the trench dopant containing layer into the semiconductor substrate; and removing the trench dopant containing layer. | 04-26-2012 |
20120098058 | Semiconductor Device and Associated Fabrication Method - A semiconductor device and a method for forming the semiconductor device wherein the semiconductor comprises: a trench MOSFET, formed on a semiconductor initial layer, comprising a well region, wherein the semiconductor initial layer has a first conductivity type and wherein the well region has a second conductivity type; an integrated Schottky diode next to the trench MOSFET, comprising a anode metal layer contacted to the semiconductor initial layer; a trench isolation structure, coupled between the trench MOSFET and integrated Schottky diode, configured to resist part of lateral diffusion from the well region; wherein the well region comprises an overgrowth part which laterally diffuses under the trench isolation structure and extends out of it. | 04-26-2012 |
20120098059 | DIRECT CONTACT IN TRENCH WITH THREE-MASK SHIELD GATE PROCESS - A semiconductor substrate may be etched to form trenches with three different widths. A first conductive material is formed at the bottom of the trenches. A second conductive material separated by an insulator is formed over the first conductive material. A first insulator layer is formed on the trenches. A body layer is formed in the substrate. A source is formed in the body layer. A second insulator layer is formed on the trenches and source. Source and gate contacts are formed through the second insulator layer. Source and gate metal are formed on the second insulator layer. This abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. | 04-26-2012 |
20120104490 | Trench-Gate Field Effect Transistors and Methods of Forming the Same - A field effect transistor includes a body region of a first conductivity type over a semiconductor region of a second conductivity type. A gate trench extends through the body region and terminates within the semiconductor region. At least one conductive shield electrode is disposed in the gate trench. A gate electrode is disposed in the gate trench over but insulated from the at least one conductive shield electrode. A shield dielectric layer insulates the at lease one conductive shield electrode from the semiconductor region. A gate dielectric layer insulates the gate electrode from the body region. The shield dielectric layer is formed such that it flares out and extends directly under the body region. | 05-03-2012 |
20120112268 | TERMINATION STRUCTURE OF POWER SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The present invention provides a termination structure of a power semiconductor device and a manufacturing method thereof. The power semiconductor device has an active region and a termination region. The termination region surrounds the active region, and the termination structure is disposed in the termination region. The termination structure includes a semiconductor substrate, an insulating layer and a metal layer. The semiconductor substrate has a trench disposed in the termination region. The insulating layer is partially filled into the trench and covers the semiconductor substrate, and a top surface of the insulating layer has a hole. The metal layer is disposed on the insulating layer, and is filled into the hole. | 05-10-2012 |
20120112269 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A technology is a semiconductor device and a method of manufacturing the same, capable of reducing capacitance with a storage node contact plug while maintaining a height and resistance of a bit line, by thickly forming a spacer between a bit line and the storage node contact plug. A semiconductor device includes a device isolation layer defining a plurality of active regions formed in a semiconductor substrate, a storage node contact hole exposing two neighboring active regions, a storage node contact plug material provided in the storage node contact hole, a bit line region that divides the storage node contact plug material into two parts and that has a convex portion at a lower portion of a sidewall, a spacer formed over a sidewall of the bit line region including the convex portion and a bit line formed in the bit line region. | 05-10-2012 |
20120112270 | VERTICAL TRANSISTOR HAVING BURIED JUNCTION AND METHOD FOR MANUFACTURING THE SAME - A buried junction is formed in a vertical transistor of a semiconductor device. Wall bodies are formed from a semiconductor substrate, the wall bodies protruding while having a first side surface and a second side surface in the opposite side of the first side surface; forming a one side contact mask having an opening which selectively opens a portion of the first side surface of the wall body; and forming a first impurity layer and a second impurity layer surrounding the first impurity layer by diffusing impurities having different diffusivities into the portion of the first side surface exposed to the opening. | 05-10-2012 |
20120112271 | SEMICONDUCTOR DEVICE, METHOD OF FORMING SEMICONDUCTOR DEVICE, AND DATA PROCESSING SYSTEM - A semiconductor device includes the following elements. A semiconductor substrate includes an isolation region. The semiconductor substrate has a groove in the isolation region. A pad electrode is disposed in the groove. A pad contact plug is disposed in the groove. The pad contact plug is disposed on the pad electrode. A gate contact plug is disposed on the pad contact plug. The gate contact plug is electrically coupled through the pad contact plug to the pad electrode. An insulating side wall is disposed in the groove. The insulating side wall covers side surfaces of the pad contact plug and a lower portion of the gate contact plug, and the insulating side wall covers a part of an upper surface of the pad electrode. | 05-10-2012 |
20120119289 | SEMICONDUCTOR DEVICE WITH VERTICAL CHANNEL TRANSISTOR AND METHOD OF OPERATING THE SAME - Provided is a semiconductor device including a substrate having active patterns extending between first trenches and between second trenches (the first and second trenches intersecting each other), and gate patterns disposed within the first trenches, wherein each of the active patterns includes lower and upper impurity regions, and a channel region between the lower and upper impurity regions, the lower and upper impurity regions being vertically spaced apart from each other and having a conductivity type different from the substrate, and the channel region having the same conductivity type as the substrate, and a bottom surface of the gate pattern is closer to a bottom surface of the first trench than the lower impurity region. | 05-17-2012 |
20120126316 | SEMICONDUCTOR DEVICE - Provided is a method of manufacturing a semiconductor device, that buried gate electrodes are formed in a pair of trenches in a substrate, so as to be recessed from the level of the top end of the trenches, a base region is formed between a predetermined region located between the pair of trenches, and a source region is formed over the base region. | 05-24-2012 |
20120139037 | DEPLETION MODE TRENCH SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A manufacturing method of a depletion mode trench semiconductor device includes following steps. Firstly, a substrate including a drift epitaxial layer disposed thereon is provided. A trench is disposed in the drift epitaxial layer. A gate dielectric layer is formed on an inner sidewall of the trench and an upper surface of the drift epitaxial layer. A base doped region is formed in the drift epitaxial layer and adjacent to a side of the trench. A thin doped region is formed and conformally contacts the gate dielectric layer. A gate material layer is formed to fill the trench. A source doped region is formed in the base doped region, and the source doped region overlaps the thin doped region at a side of the trench. Finally, a contact doped region is formed to overlap the thin doped region, and the contact doped region is adjacent to the source doped region. | 06-07-2012 |
20120139038 | COMPOUND SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A first AlGaN layer formed over a substrate, a second AlGaN layer formed over the first AlGaN layer, an electron transit layer formed over the second AlGaN layer, and an electron supply layer formed over the electron transit layer are provided. A relationship of “0≦x106-07-2012 | |
20120139039 | Semiconductor Device Comprising a Transistor Gate Having Multiple Vertically Oriented Sidewalls - A method used in fabrication of a recessed access device transistor gate has increased tolerance for mask misalignment. One embodiment of the invention comprises forming a vertical spacing layer over a semiconductor wafer, then etching the vertical spacing layer and the semiconductor wafer to form a recess in the wafer. A conductive transistor gate layer is then formed within the trench and over the vertical spacing layer. The transistor gate layer is etched, which exposes the vertical spacing layer. A spacer layer is formed over the etched conductive gate layer and over the vertical spacing layer, then the spacer layer and the vertical spacing layer are anisotropically etched. Subsequent to anisotropically etching the vertical spacing layer, a portion of the vertical spacing layer is interposed between the semiconductor wafer and the etched conductive transistor gate layer in a direction perpendicular to the plane of a major surface of the semiconductor wafer. | 06-07-2012 |
20120146133 | Method for Producing a Semiconductor Component with Insulated Semiconductor Mesas - A method for producing a semiconductor component is provided. The method includes providing a semiconductor body with a first surface and a second surface opposite to the first surface, etching an insulation trench from the first surface partially into the semiconductor body, forming a first insulation layer on one or more sidewalls of the insulation trench, processing the second surface by at least one of grinding, polishing and a CMP-process to expose the first insulation layer, and depositing on the processed second surface a second insulation layer which extends to the first insulation layer. | 06-14-2012 |
20120146134 | COMPOUND SEMICONDUCTOR DEVICE AND MANUFACTURE PROCESS THEREOF - A compound semiconductor device includes a compound semiconductor layer, a gate electrode disposed above the compound semiconductor layer, and a gate insulation film. The gate insulation film is interposed between the compound semiconductor layer and the gate electrode. The gate insulation film contains a fluorine compound at least in the vicinity of the interface with the compound semiconductor layer. | 06-14-2012 |
20120146135 | METHOD AND A STRUCTURE FOR ENHANCING ELECTRICAL INSULATION AND DYNAMIC PERFORMANCE OF MIS STRUCTURES COMPRISING VERTICAL FIELD PLATES - In an MIS structure a field plate electrode is incorporated below a buried gate electrode by using an insulating oxide layer, which is formed concurrently with the gate dielectric layer. In order to obtain superior dynamic behavior and enhanced dielectric strength the oxidation behavior of the field plate electrode is modified, for instance by incorporating a desired high concentration of arsenic. | 06-14-2012 |
20120153380 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes forming a first trench by etching a substrate, forming first spacers on sidewalls of the first trench, forming a second trench by etching the substrate under the first trench, forming second spacers on sidewalls of the second trench, forming a third trench, which has a wider width than a width between the second spacers, by etching the substrate under the second trench, forming a liner layer on the surface of the third trench, and exposing one of the sidewalls of the second trench by selectively removing the second spacers. | 06-21-2012 |
20120153381 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A semiconductor device and a method for forming the same are disclosed. A method for forming a semiconductor device includes forming a trench by etching a semiconductor substrate, forming a barrier metal layer having a thickness of 100 Å or less over a surface of the trench, forming a nucleation layer over the barrier metal layer, configured to include a β-tungsten (β-W) structure, and forming a bulk layer over the nucleation layer so as to bury the bottom of the trench. As a result, resistivity can be reduced and a stable-phase barrier metal layer can be obtained. In addition, productivity is improved so that gate resistance is prevented from increasing. | 06-21-2012 |
20120153382 | SEMICONDUCTOR DEVICE - A semiconductor device includes a trench extending from a surface of a P-base layer to a surface of a P-well layer. The trench has a trench end portion defined in the surface of the P-well layer and in a direction in which the trench extends. The trench has first and second regions. The first region extends from the trench end portion to get into the surface of the P-base layer near a boundary between the P-base layer and the P-well layer. The second region extends in the surface of the P-base layer from an end portion of the first region. A trench width is greater in the first region than in the second region. | 06-21-2012 |
20120161226 | Semiconductor Device - A semiconductor device includes a semiconductor layer of a first conductivity type and a semiconductor layer of a second conductivity type formed thereon. The semiconductor layer of the second conductivity type is characterized by a first thickness. The semiconductor device includes a set of trenches having a predetermined depth and extending into the semiconductor layer of the second conductivity type, thereby defining interfacial regions disposed between the semiconductor layer of the second conductivity type and each of the trenches. The trenches comprises a distal portion consisting essentially of a dielectric material disposed therein and a proximal portion comprising the dielectric material and a gate material disposed interior to the dielectric material in the proximal portion of the trench. The semiconductor device further includes a source region coupled to the semiconductor layer of the second conductivity type. | 06-28-2012 |
20120161227 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device may include, but is not limited to, a semiconductor substrate, a word line, and an isolation region. The semiconductor substrate has an active region and first and second grooves. Each of the first and second grooves extends across the active region. The first groove is wider in width than the second groove. The word line is disposed in the first groove. The isolation region is disposed in the second groove. The isolation region is narrower in width than the word line. | 06-28-2012 |
20120168856 | TRENCH-TYPE SEMICONDUCTOR POWER DEVICES - The present invention relates to a semiconductor device. The device comprises a semiconductor substrate. A semiconductor drift region is on the semiconductor substrate. The semiconductor drift region comprises a semiconductor region of a first conduction type and a semiconductor region of a second conduction type. The semiconductor region of the first conduction type and the semiconductor region of the second conduction type form a superjunction structure. A high-K dielectric is on the semiconductor substrate. The high-K dielectric is adjacent to the semiconductor region of the second conduction type. An active region is on the semiconductor drift region. A trench gate structure is on the high-K dielectric, the trench gate structure being adjacent to the active region. The semiconductor region of the second conduction type is formed by shallow angle ion implantation, thus its width is narrow and its concentration is high. | 07-05-2012 |
20120168857 | Memory structure having a floating body and method for fabricating the same - A memory structure having a floating body is provided, which includes a substrate including an active area and an isolation structure surrounding the active area, a first source/drain region in the substrate in the active area, a first floating body in the substrate above the first source/drain region, a second floating body on the first floating body, a second source/drain region on the second floating body, and a trench-type gate structure in the substrate and beside the first floating body. A method of fabricating a memory structure having a floating body is also provided. | 07-05-2012 |
20120168858 | NON-VOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A method of fabricating a non-volatile memory device includes providing a substrate with a cell region where a plurality of memory cells that are stacked vertically are to be formed and a peripheral circuit region where a peripheral circuit device is to be formed. Forming a gate structure where an inter-layer dielectric layer and a gate electrode layer are alternately stacked over the substrate of the cell region and the peripheral circuit region. Forming a first trench that isolates the gate electrode layers in one direction by selectively etching the gate structure of the cell region and forming a trench by selectively etching the gate structure corresponding to a contact formation region of the peripheral circuit region. | 07-05-2012 |
20120168859 | VERTICAL TRANSISTOR MANUFACTURING METHOD AND VERTICAL TRANSISTOR - A method is disclosed of manufacturing a vertical transistor which comprises providing a substrate including a vertical stack of regions including a source region separated from a drain region by a channel region; forming a trench in said substrate, said trench at least partially extending into said vertical stack of regions; lining said trench with a stack comprising a gate dielectric liner, an etch protection layer and a further insulating layer; filling the remainder of the trench with a shield electrode material; exposing a top portion of the shield electrode material by removing the further insulating layer to a first depth in said trench; forming a inter electrode dielectric on the exposed shield electrode material; removing the etch protection layer to the first depth from said trench; and forming a gate electrode in said trench between the inter electrode dielectric liner and the exposed portion of the gate dielectric liner. | 07-05-2012 |
20120175698 | SEMICONDUCTOR DEVICE - A semiconductor device which includes a gate electrode electrically connected to a gate portion made of a polysilicon film provided inside of a plurality of grooves formed in a striped form along a direction of a chip region. The gate electrode is formed as a film at the same layer level as a source electrode electrically connected to a source region formed between adjacent stripe-shaped grooves. The gate electrode is constituted of a gate electrode portion formed along a periphery of the chip region and a gate finger portion arranged to divide the chip region into halves. The source electrode is constituted of an upper portion and a lower portion relative to the gate finger portion, and the gate electrode and the source electrode are connected to a lead frame via a bump electrode. | 07-12-2012 |
20120181604 | FIN FET AND METHOD OF FABRICATING SAME - A fin field effect transistor (fin FET) is formed using a bulk silicon substrate and sufficiently guarantees a top channel length formed under a gate, by forming a recess having a predetermined depth in a fin active region and then by forming the gate in an upper part of the recess. A device isolation film is formed to define a non-active region and a fin active region in a predetermined region of the substrate. In a portion of the device isolation film a first recess is formed, and in a portion of the fin active region a second recess having a depth shallower than the first recess is formed. A gate insulation layer is formed within the second recess, and a gate is formed in an upper part of the second recess. A source/drain region is formed in the fin active region of both sides of a gate electrode. | 07-19-2012 |
20120181605 | METHODS OF PROVIDING ELECTRICAL ISOLATION AND SEMICONDUCTOR STRUCTURES INCLUDING SAME - Methods of isolating gates in a semiconductor structure. In one embodiment, isolation is achieved using a spacer material in combination with fins. In another embodiment, etch characteristics of various materials utilized in fabrication of the semiconductor structure are used to increase an effective gate length (“L | 07-19-2012 |
20120187474 | Trench Power MOSFET With Reduced On-Resistance - A semiconductor device includes a drift region, a well region extending above the drift region, an active trench including sidewalls and a bottom, the active trench extending through the well region and into the drift region and having at least portions of its sidewalls and bottom lined with dielectric material. The device further includes a shield disposed within the active trench and separated from the sidewalls of the active trench by the dielectric material, a gate disposed within the active trench above the first shield and separated therefrom by inter-electrode dielectric material, and source regions formed in the well region adjacent the active trench. The gate is separated from the sidewalls of the active trench by the dielectric material. The shield and the gate are made of materials having different work functions. | 07-26-2012 |
20120187475 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A conventional DRAM needs to be refreshed at an interval of several tens of milliseconds to hold data, which results in large power consumption. In addition, a transistor therein is frequently turned on and off; thus, deterioration of the transistor is also a problem. These problems become significant as the memory capacity increases and transistor miniaturization advances. A transistor is provided which includes a wide-gap semiconductor and has a trench structure including a trench for a gate electrode and a trench for element isolation. Even when the distance between a source electrode and a drain electrode is decreased, the occurrence of a short-channel effect can be suppressed by setting the depth of the trench for the gate electrode as appropriate. | 07-26-2012 |
20120187476 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Trench portions ( | 07-26-2012 |
20120193705 | VERTICAL NONVOLATILE MEMORY DEVICES HAVING REFERENCE FEATURES - A memory device includes a substrate having a cell array region defined therein. A dummy structure is disposed on or in the substrate near a boundary of the cell array region. The memory device also includes a vertical channel region disposed on the substrate in the cell array region. The memory device further includes a plurality of vertically stacked conductive gate lines with insulating layers interposed therebetween, the conductive gate lines and interposed insulating layers disposed laterally adjacent the vertical channel region and extending across the dummy structure, at least an uppermost one of the conductive gate lines and insulating layers having a surface variation at the crossing of the dummy structure configured to serve as a reference feature. The dummy structure may include a trench, and the surface variation may include an indentation overlying the trench. | 08-02-2012 |
20120199899 | SEMICONDUCTOR DEVICE HAVING FIELD PLATE ELECTRODE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, in a semiconductor device, a first semiconductor layer of a first conductivity type has a first impurity concentration. A second semiconductor layer of the first conductivity type is formed on the first semiconductor layer and has a second impurity concentration lower than the first impurity concentration. A field plate electrode is formed in a lower portion of a trench formed in the second semiconductor layer through a first insulating film so as to bury the lower portion of the trench. A second insulating film is formed in the upper portion of the trench so as to be in contact with the top surface of the field plate electrode. A gate electrode is formed in the upper portion of the trench through a gate insulating film so as to bury the upper portion of the trench to sandwich the second insulating film. | 08-09-2012 |
20120199900 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes: a semiconductor substrate; an interlayer film on the substrate; a surface electrode on the interlayer film; a surface pad on the surface electrode; a backside electrode on the substrate; an element area including a cell portion having a vertical semiconductor element and a removal portion having multiple contact regions; and an outer periphery area. The surface electrode in the removal portion is electrically coupled with each contact region through a first contact hole in the interlayer film. The surface electrode in the cell portion is electrically coupled with the substrate through a second contact hole in the interlayer film. A part of the surface electrode in the removal portion facing each contact region is defined as a contact portion. The surface electrode includes multiple notches on a shortest distance line segment between each contact portion and the surface pad. | 08-09-2012 |
20120199901 | SEMICONDUCTOR DEVICE - A semiconductor device includes an active region, a gate conductor and a source electrode. The active region includes a drain region, a channel region stacked on the drain region, and a source region stacked on the channel region. The active region is formed of a silicon semiconductor layer. The gate conductor is embedded within a trench, which is formed from the source region to the drain region penetrating through the channel region. The source electrode is formed to come in contact with the source region and includes an adhesion layer. The source electrode is formed of a metal layer having a film thickness of 150 Å or smaller. The interface between the source electrode and the source region is silicidized. | 08-09-2012 |
20120211825 | Trench MOSFET and Method for Fabricating Same - According to an exemplary embodiment, a trench field-effect transistor (trench FET) includes a trench formed in a semiconductor substrate, the trench including a gate dielectric disposed therein. A source region is disposed adjacent the trench. The trench FET also has a gate electrode including a lower portion disposed in the trench and a proud portion extending laterally over the source region. A silicide source contact can extend vertically along a sidewall of the source region. Also, a portion of the gate dielectric can extend laterally over the semiconductor substrate. The trench FET can further include a silicide gate contact formed over the proud portion of the gate electrode. | 08-23-2012 |
20120211826 | Trench DMOS Transistor with Reduced Gate-to-Drain Capacitance - A trench DMOS transistor with a very low on-state drain-to-source resistance and a high gate-to-drain charge includes one or more floating islands that lie between the gate and drain to reduce the charge coupling between the gate and drain, and effectively lower the gate-to-drain capacitance. | 08-23-2012 |
20120211827 | METHOD OF FORMING AN INTEGRATED POWER DEVICE AND STRUCTURE - In one embodiment, a vertical power transistor is formed on a semiconductor substrate with other transistors. A portion of the semiconductor layer underlying the vertical power transistor is doped to provide a low on-resistance for the vertical power transistor. | 08-23-2012 |
20120211828 | HYBRID SPLIT GATE SEMICONDUCTOR - In an embodiment in accordance with the present invention, a semiconductor device includes a vertical channel region, a gate at a first depth on a first side of the vertical channel region, a shield electrode at a second depth on the first side of the vertical channel region, and a hybrid gate at the first depth on a second side of the vertical channel region. The region below the hybrid gate on the second side of the vertical channel region is free of any electrodes. | 08-23-2012 |
20120217575 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - According to one embodiment, a method is disclosed for manufacturing semiconductor device. The method can include preparing a semiconductor layer having a drain layer, and a drift region provided from a surface to an inside of the drain layer, the drift region having a first trench extending from a surface to an inside of the drift region. The method can include implanting impurities into the drift region through an opening of the first trench to form a source region for an exposed face of the drift region exposed on an inside wall of the first trench, and implanting impurities into the drift region through the opening of the first trench to form a base region between the source region and the drift region. The method can include forming gate electrode. | 08-30-2012 |
20120217576 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A semiconductor device and a method for forming the same are disclosed. According to the semiconductor device and the method for forming the same, a contact hole spacer is formed only over a contact hole sidewall such that a lower part of a contact plug is formed to have large critical dimension and therefore contact resistance is increased, and an upper spacer is not lost in a process of forming a contact hole sidewall spacer so as to prevent a Self Align Contact (SAC) failure from occurring. The semiconductor device includes a contact hole formed over a semiconductor substrate, a first conductive layer formed at a bottom region of the contact hole and a lower part of sidewalls of the contact hole, a spacer formed over the sidewalls of the contact hole, and a second conductive layer buried in the contact hole including the first conductive layer and the spacer. | 08-30-2012 |
20120217577 | SEMICONDUCTOR DEVICE - A trench-gate vertical-channel type power MOSFET has an advantage of a low on-state resistance. With increasing miniaturization, fluctuations in on-state resistance have posed a problem. In addition, a structural limitation in miniaturization also has posed a problem. These problems are not only those of a single power MOSFET but also are important ones in integrated circuit devices, such as IGBT using a similar structure, obtained by integrating CMOS and such a power active device on a single chip. The invention provides a semiconductor device having a trench-gate vertical-channel type power active device, such as trench-gate vertical-channel type power MOSFET, in which the width of the interlayer insulating film is made almost equal to that of the trench and a portion of the source region is comprised of a polysilicon member. | 08-30-2012 |
20120217578 | METHOD AND SYSTEM FOR METAL GATE FORMATION WITH WIDER METAL GATE FILL MARGIN - A method includes providing a semiconductor substrate having a gate trench and depositing a metal layer, using a physical vapor deposition (PVD) process, over the substrate to partially fill the trench. The metal layer includes a bottom portion and a sidewall portion that is thinner than the bottom portion. The method also includes forming a coating layer on the metal layer, etching back the coating layer such that a portion of the coating layer protects a portion of the metal layer within the trench, and removing the unprotected portion of the metal layer. A different aspect involves a semiconductor device that includes a gate that includes a trench having a top surface, and a metal layer formed over the trench, wherein the metal layer includes a sidewall portion and a bottom portion, and wherein the sidewall portion is thinner than the bottom portion. | 08-30-2012 |
20120228699 | METHODS FOR FABRICATING TRANSISTORS INCLUDING ONE OR MORE CIRCULAR TRENCHES - A transistor and a method of fabricating a transistor, including a metal oxide deposited on an epitaxial layer, a photo resist deposited and patterned over the metal oxide and the metal oxide and epitaxial layer are etched to form at least one circular trench, wherein the trench surfaces are defined by the epitaxial layer. An oxide layer is grown on the trench surfaces of each trench, and a gate conductor is formed within the at least one trench. | 09-13-2012 |
20120228700 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes: an N-type drift layer; a P-type anode layer on the N-type drift layer; a trench penetrating the P-type anode layer; a conductive substance embedded in the trench via an insulating film; and an N-type buffer layer between the N-type drift layer and the P-type anode layer and having impurity concentration which is higher than that of the N-type drift layer. | 09-13-2012 |
20120228701 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - In accordance with an embodiment, a semiconductor device includes a semiconductor layer of a first conductivity type with a recess in the surface of the semiconductor layer, a pocket region of the first conductivity type in the semiconductor layer, a source region of a second conductivity type in the semiconductor layer, a drain region of the first conductivity type in the semiconductor layer, a gate insulating film over the surface of the recess, and a gate electrode. The second conductivity type is different from the first conductivity type. The pocket region includes a part under the surface of the recess. The source region is located adjacent to the pocket region. The drain region is located away from the source region and the pocket region. The gate electrode is configured to fill the recess via the gate insulating film. | 09-13-2012 |
20120228702 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device includes a semiconductor substrate having a groove and an active region adjacent to the groove; a buried gate electrode in the groove; and a capacitive contact including a first portion and a second portion over the first portion. The first portion is greater in horizontal dimension than the second portion. The first portion has a bottom surface that is in contact with an upper surface of the active region. | 09-13-2012 |
20120235228 | TRANSISTOR STRUCTURE AND METHOD FOR PREPARING THE SAME - A buried channel transistor structure includes a semiconductor substrate; a conductive block positioned in the semiconductor substrate; a gate dielectric layer positioned between the conductive block and the semiconductor substrate; and a bulge-shaped dielectric structure positioned on the conductive block and the gate dielectric layer. | 09-20-2012 |
20120235229 | INTER-POLY DIELECTRIC IN A SHIELDED GATE MOSFET DEVICE - In one general aspect, an apparatus can include a shield dielectric disposed within a trench aligned along an axis within an epitaxial layer of a semiconductor, and a shield electrode disposed within the shield dielectric and aligned along the axis. The apparatus can include a first inter-poly dielectric having a portion intersecting a plane orthogonal to the axis where the plane intersects the shield electrode, and a second inter-poly dielectric having a portion intersecting the plane and disposed between the first inter-poly dielectric and the shield electrode. The apparatus can also include a gate dielectric having a portion disposed on the first inter-poly dielectric. | 09-20-2012 |
20120241848 | SEMICONDUCTOR ELEMENT AND METHOD OF MANUFACTURING SEMICONDUCTOR ELEMENT - A semiconductor element includes a drain layer, a drift region selectively provided in the drain layer, a base region selectively provided in the drift region, a source region selectively provided in the base region, first and/or second metal layers selectively provided in at least one of the source region and the drain layer from the front surface to the inside of at least one of the source region and the drain layer, a gate electrode in a trench shape extending in a direction substantially parallel to the front surface of the drain layer from a part of the source region through the base region adjacent to at least the part of the source region to a part of the drift region, a source electrode connected to the first metal layer, and a drain electrode connected to the drain layer or the second metal layer. | 09-27-2012 |
20120241849 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor device includes a first semiconductor region, a second semiconductor region, a third semiconductor region, a control electrode, a first main electrode, an internal electrode, and an insulating region. The control electrode is provided inside a trench. The first main electrode is in conduction with the third semiconductor region. The internal electrode is provided in the trench and in conduction with the first main electrode. The insulating region is provided between an inner wall of the trench and the internal electrode. The internal electrode includes a first internal electrode part included in a first region of the trench and a second internal electrode part included in a second region between the first region and the first main electrode. A spacing between the first internal electrode part and the inner wall is wider than a spacing between the second internal electrode part and the inner wall. | 09-27-2012 |
20120241850 | SEMICONDUCTOR DEVICE - A semiconductor device includes a drain layer, a drift region provided from a surface inside of the drain layer, a base region provided from a surface inside of the drift region, a source region provided in a trench form from a surface inside of the base region, and a gate electrode provided via a gate insulating film in a first trench. The gate electrode is extended from a part of the source region to a part of the drift region in a direction approximately parallel to a rear face of the drain layer. The semiconductor device further includes a first resistive body layer provided via a first insulating film in at least one of second trenches provided from a surface inside of the drain layer. | 09-27-2012 |
20120241851 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor device includes a drift layer. The device includes a base layer. The device includes a source layer selectively provided on a surface of the base layer. The device includes a gate electrode provided via a gate insulating film in a trench penetrating the source layer and the base layer to reach the drift layer. The device includes a field plate electrode provided under the gate electrode in the trench. The device includes a drain electrode electrically connected to the drift layer. The device includes a source electrode. The field plate electrode is electrically connected to the source electrode. An impurity concentration of a first conductivity type contained in the base layer is lower than an impurity concentration of the first conductivity type contained in the drift layer. And the impurity concentration of the first conductivity type contained in the drift layer is not less than 1×10 | 09-27-2012 |
20120248526 | Wafer Level MOSFET Metallization - Systems and methods of fabricating Wafer Level Chip Scale Packaging (WLCSP) devices with transistors having source, drain and gate contacts on one side of the transistor while still having excellent electrical performance with low drain-to-source resistance R | 10-04-2012 |
20120248527 | SEMICONDUCTOR MEMORY DEVICE AND ITS MANUFACTURING METHOD - According to one embodiment, a semiconductor memory device includes a semiconductor substrate having a gate groove and first to third grooves, the first to third grooves being formed on a bottom surface of the gate groove and the third groove being formed between the first and second grooves, and a gate electrode having a first gate portion formed in the first groove, a second gate portion formed in the second groove, a third gate portion formed in the third groove, and a fourth gate portion formed in the gate groove. A cell transistor having the gate electrode has a first channel region formed in the semiconductor substrate between the first and third gate portions and a second channel region formed in the semiconductor substrate between the second and third gate portions. | 10-04-2012 |
20120248528 | TRENCH-GATE LDMOS STRUCTURES - MOSFET devices for RF applications that use a trench-gate in place of the lateral gate conventionally used in lateral MOSFET devices. A trench-gate provides devices with a single, short channel for high frequency gain. Embodiments of the present invention provide devices with an asymmetric oxide in the trench gate, as well as LDD regions that lower the gate-drain capacitance for improved RF performance. Refinements to these TG-LDMOS devices include placing a source-shield conductor below the gate and placing two gates in a trench-gate region. These improve device high-frequency performance by decreasing gate-to-drain capacitance. Further refinements include adding a charge balance region to the LDD region and adding source-to-substrate or drain-to-substrate vias. | 10-04-2012 |
20120256255 | RECESSED TRENCH GATE STRUCTURE AND METHOD OF FABRICATING THE SAME - A recessed trench gate structure is provided. The recessed trench gate structure includes a substrate with a recessed trench, a gate dielectric layer disposed around an inner surface of the recessed trench, a lower gate conductor disposed at a lower portion of the recessed trench and on the gate dielectric layer. Specially, the lower gate conductor has a convex top surface. A spacer is disposed along an inner side wall of a upper portion of the recessed trench and a upper gate conductor is disposed on the lower gate conductor. The convex top surface can prevent the electric field from distributing not uniformly, so that the GIDL can be prevented. | 10-11-2012 |
20120256256 | RECESSED GATE TRANSISTOR WITH CYLINDRICAL FINS - A recessed gate transistor with cylindrical fins is disclosed. The recessed gate transistor is disposed in an active region of a semiconductor substrate. Two isolation regions disposed in the semiconductor substrate to define an active region therebetween. The recessed gate transistor includes a gate structure, a source doping region and a drain doping region. The gate structure has at least three fins forms a concave and convex bottom of the gate structure. The front fin is disposed in one of the two isolation regions, the middle fin is disposed in the active region and a last fin disposed in the other one of the two isolation regions. The front fin and the last fin are both cylindrical. A lower part of the gate structure is M-shaped when view from the source doping region to the drain doping region direction. | 10-11-2012 |
20120256257 | TRANSISTOR WITH BURIED FINS - The present invention disclosed a recessed gate transistor with buried fins. The recessed gate transistor with buried fins is disposed in an active region on a semiconductor substrate. Two isolation regions disposed in the semiconductor substrate, and sandwich the active region. A gate structure is disposed in the semiconductor substrate, wherein the gate structure includes: an upper part and a lower part. The upper part is disposed in the active region and a lower part having a front fin disposed in one of the two isolation regions, at least one middle fin disposed in the active region, and a last fin disposed in the other one of the two isolation regions, wherein the front fin are both elliptic cylindrical. | 10-11-2012 |
20120256258 | TRENCH POWER MOSFET STRUCTURE WITH HIGH CELL DENSITY AND FABRICATION METHOD THEREOF - A fabrication method of a high cell density trench power MOSFET structure is provided. Form at least a gate trench in a silicon substrate and a gate dielectric layer on the silicon substrate. Form a gate polysilicon structure in the gate trench and cover by a passivation layer. Form a first-conductive-type body region in the silicon substrate and implant impurities with a second conductive type thereof to form a source doped region. Expose the gate polysilicon structure and the source doped region. Form a dielectric spacer having a predetermined thickness on a sidewall of the gate trench. Deposit metal on the gate polysilicon structure and the source doped region. A first and a second self-aligned silicide layer are respectively formed on the gate polysilicon structure and the source doped region. The dielectric spacer forms an appropriate distance between the first and the second self-aligned silicide layer. | 10-11-2012 |
20120261746 | Double-Trench Vertical Devices and Methods with Self-Alignment Between Gate and Body Contact - Methods and resulting device structures for power trench transistor fabrication, wherein a reachup pillar from the field plate trench is left in place to define the location of a self-aligned contact to the field plate. | 10-18-2012 |
20120261747 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - A semiconductor device includes a word line and a bit line on a substrate and the word line intersects the bit line, an insulating layer on the substrate and the insulating layer includes voids therein, and a passivation layer on the insulating layer and the passivation layer includes hydrogen atoms therein. The voids define diffusion pathways through which the hydrogen atoms in the passivation layer diffuse in a direction toward the substrate. | 10-18-2012 |
20120261748 | SEMICONDUCTOR DEVICE WITH RECESS GATE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a substrate with a recess pattern, a gate electrode filling the recess pattern, a threshold voltage adjusting layer formed in the substrate under the recess pattern, a source/drain region formed in the substrate on both sides of the gate electrode and a gate insulation layer, with the recess pattern being disposed between the gate electrode and the substrate, wherein the thickness of the gate insulation layer formed in a region adjacent to the source/drain region is greater than the thickness of the gate insulation layer formed in a region adjacent to the threshold voltage adjusting layer. | 10-18-2012 |
20120267708 | TERMINATION STRUCTURE FOR POWER DEVICES - A termination structure for a power MOSFET device includes a substrate, an epitaxial layer on the substrate, a trench in the epitaxial layer, a first insulating layer within the trench, a first conductive layer atop the first insulating layer, and a column doping region in the epitaxial layer and in direct contact with the first conductive layer. The first conductive layer is in direct contact with the first insulating layer and is substantially level with a top surface of the epitaxial layer. The first conductive layer comprises polysilicon, titanium, titanium nitride or aluminum. | 10-25-2012 |
20120267709 | SEMICONDUCTOR DEVICE - To provide a highly reliable semiconductor device. To provide a semiconductor device which prevents a defect and achieves miniaturization. An oxide semiconductor layer in which the thickness of a region serving as a source region or a drain region is larger than the thickness of a region serving as a channel formation region is formed in contact with an insulating layer including a trench. In a transistor including the oxide semiconductor layer, variation in threshold voltage, degradation of electric characteristics, and shift to normally on can be suppressed and source resistance or drain resistance can be reduced, so that the transistor can have high reliability. | 10-25-2012 |
20120267710 | Semiconductor Device - Provided is a semiconductor device in which on-resistance is largely reduced. In a region ( | 10-25-2012 |
20120273874 | MEMORY DEVICE HAVING BURIED BIT LINE AND VERTICAL TRANSISTOR AND FABRICATION METHOD THEREOF - A method of forming a buried bit line is provided. A substrate is provided and a line-shaped trench region is defined in the substrate. A line-shaped trench is formed in the line-shaped trench region of the substrate. The line-shaped trench includes a sidewall surface and a bottom surface. Then, the bottom surface of the line-shaped trench is widened to form a curved bottom surface. Next, a doping area is formed in the substrate adjacent to the curved bottom surface. Lastly, a buried conductive layer is formed on the doping area such that the doping area and the buried conductive layer together constitute the buried bit line. | 11-01-2012 |
20120273875 | Superjunction Structures for Power Devices and Methods of Manufacture - A power device includes a semiconductor region which in turn includes a plurality of alternately arranged pillars of first and second conductivity type. Each of the plurality of pillars of second conductivity type further includes a plurality of implant regions of the second conductivity type arranged on top of one another along the depth of pillars of second conductivity type, and a trench portion filled with semiconductor material of the second conductivity type directly above the plurality of implant regions of second conductivity type. | 11-01-2012 |
20120273876 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes a semiconductor substrate that includes a cell region and a peripheral circuit area. The method for forming the semiconductor includes forming a guard pattern of an insulation material. The guard pattern is located at an edge part between the cell region and the peripheral circuit region and is buried in the semiconductor substrate. As a result, the semiconductor device prevents oxidation of the guard pattern, such that a cell gate oxidation integrity (GOI) failure is improved and an IDD failure is prevented from being generated. | 11-01-2012 |
20120280310 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device including an isolation layer structure including a doped polysilicon layer pattern doped with first and second impurities of first and second conductivity types at lower and upper portions thereof, the doped polysilicon layer pattern being on an inner wall of a first trench on a substrate including an active region in which the first trench is not formed and a field region including the first trench, and an insulation structure filling a remaining portion of the first trench; a gate structure on the active region; a well region at a portion of the active region adjacent to lower portions of the doped polysilicon layer pattern and being doped with third impurities of the second conductivity type; and a source/drain at a portion of the active region adjacent to upper portions of the doped polysilicon layer pattern and being doped with fourth impurities of the first conductivity type. | 11-08-2012 |
20120280311 | TRENCH-GATE MOSFET DEVICE AND METHOD FOR MAKING THE SAME - The embodiments of the present disclosure disclose a trench-gate MOSFET device and the method for making the trench-gate MOSFET device. The trench-gate MOSFET device comprises a curving dopant profile formed between the body region and the epitaxial layer so that the portion of the body region under the source metal contact has a smaller vertical thickness than the other portion of the body region. The trench-gate MOSFET device in accordance with the embodiments of the present disclosure has improved UIS capability compared with the traditional trench-gate MOSFET device. | 11-08-2012 |
20120280312 | STRUCTURE AND METHOD FOR FORMING SHIELDED GATE TRENCH FET WITH MULTIPLE CHANNELS - In one embodiment, an apparatus can include a trench extending into a semiconductor region of a first conductivity type, an electrode disposed in the trench, and a source region of the first conductivity type abutting a sidewall of the trench. The apparatus can include a first well region of a second conductivity type disposed in the semiconductor region below the source region and abutting the sidewall of the trench lateral to the electrode where the second conductivity type is opposite the first conductivity type. The apparatus can also include a second well region of the second conductivity type disposed in the semiconductor region and abutting the sidewall of the trench, and a third well region of the first conductivity type disposed between the first well region and the second well region. | 11-08-2012 |
20120280313 | SEMICONDUCTOR DEVICE WITH BURIED GATE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes forming landing plugs over a substrate, forming a trench by etching the substrate between the landing plugs, forming a buried gate to partially fill the trench, forming a gap-fill layer to gap-fill an upper side of the buried gate, forming protruding portions of the landing plugs, and trimming the protruding portions of the landing plugs. | 11-08-2012 |
20120286352 | TRENCH MOS STRUCTURE AND METHOD FOR MAKING THE SAME - A trench MOS structure is provided. The trench MOS structure includes a substrate, an epitaxial layer, a trench, a gate isolation, a trench gate, a guard ring and a reinforcement structure within the guard ring. The substrate has a first conductivity type, a first side and a second side opposite to the first side. The epitaxial layer has the first conductivity type and is disposed on the first side. The trench is disposed in the epitaxial layer. The gate isolation covers the inner wall of the trench. The trench gate is disposed in the trench and has the first conductivity type. The guard ring has a second conductivity type and is disposed within the epitaxial layer. The reinforcement structure has an electrically insulating material and is disposed within the guard ring. | 11-15-2012 |
20120286353 | TRENCH MOS STRUCTURE AND METHOD FOR FORMING THE SAME - A trench MOS structure is disclosed. The trench MOS structure includes a substrate, an epitaxial layer, a doping well, a doping region and a trench gate. The substrate has a first conductivity type, a first side and a second side opposite to the first side. The epitaxial layer has the first conductivity type and is disposed on the first side. The doping well has a second conductivity type and is disposed on the epitaxial layer. The doping region has the first conductivity type and is disposed on the doping well. The trench gate is partially disposed in the doping region. The trench gate has a bottle shaped profile with a top section smaller than a bottom section, both are partially disposed in the doping well. The bottom section of two adjacent trench gates results in a higher electrical field around the trench MOS structures. | 11-15-2012 |
20120286354 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device having a buried gate is provided. The semiconductor device is formed in a structure in which a plurality of contacts having small step differences are stacked without forming a metal contact applying an operation voltage to the buried gate in a single contact and a contact pad is formed between the contacts so that failure due to misalignment can be prevented without a separate additional process for forming the contacts. | 11-15-2012 |
20120286355 | Power Semiconductor Device and a Method for Forming a Semiconductor Device - A power semiconductor device has a semiconductor body which includes an active area and a peripheral area which both define a horizontal main surface of the semiconductor body. The semiconductor body further includes an n-type semiconductor layer, a pn junction and at least one trench. The n-type semiconductor layer is embedded in the semiconductor body and extends to the main surface in the peripheral area. The pn junction is arranged between the n-type semiconductor layer and the main surface in the active area. The at least one trench extends in the peripheral area from the main surface into the n-type semiconductor layer and includes a dielectric layer with fixed negative charges. In the vertical direction, the dielectric layer is arranged both below and above the pn junction. The dielectric layer with fixed negative charges typically has a negative net charge. Further, a method for forming a semiconductor device is provided. | 11-15-2012 |
20120286356 | SOURCE AND BODY CONTACT STRUCTURE FOR TRENCH-DMOS DEVICES USING POLYSILICON - A semiconductor device includes a gate electrode, a top source region disposed next to the gate electrode, a drain region disposed below the bottom of the gate electrode, a oxide disposed on top of the source region and the gate electrode, and a doped polysilicon spacer disposed along a sidewall of the source region and a sidewall of the oxide. Methods for manufacturing such device are also disclosed. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. | 11-15-2012 |
20120292689 | Semiconductor Structure and Method for Operating the Same - A semiconductor structure and a method for operating the same are provided. The semiconductor structure includes a substrate, a first doped region, a second doped region, a third doped region, a first trench structure and a second gate structure. The first doped region is in the substrate. The first doped region has a first conductivity type. The second doped region is in the first doped region. The second doped region has a second conductivity type opposite to the first conductivity type. The third doped region having the first conductivity type is in the second doped region. The first trench structure has a first gate structure. The first gate structure and the second gate structure are respectively on different sides of the second doped region. | 11-22-2012 |
20120292690 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a storage node contact plug, a bit line in communication with to the storage node contact plug, and an expansion unit formed on a sidewall of the bit line. Thermal expansion of the expansion unit serves to increase capacitance by ensuring a distance between the bit line and the storage node contact plug, thereby improving a sensing margin. A cell characteristic such as a record recovery time (tWR) may be enhanced. | 11-22-2012 |
20120292691 | VERTICAL MOSFET WITH THROUGH-BODY VIA FOR GATE - A MOSFET power chip includes a first vertical MOSFET and a second vertical MOSFET. The first vertical MOSFET includes a semiconductor body having a first surface defining a source and a second surface defining a drain and a gate structure formed in the semiconductor body near the second surface. A via is formed within the semiconductor body and is substantially perpendicular to the first surface and the second surface. The via has a first end electrically coupled to the first surface and a second end electrically coupled to the gate structure. The second vertical MOSFET includes a semiconductor body having a first surface defining a source, a second surface defining a drain and a gate structure formed in the semiconductor body near the first surface. | 11-22-2012 |
20120292692 | Power MOSFET Device with Self-Aligned Integrated Schottky Diode - A power MOSFET device and manufacturing method thereof, includes the steps of selectively depositing a first conductive material in the middle region at the bottom of a contact trench and contacting with light-doped N-type epitaxial layer to form a Schottky junction and depositing a second conductive material at the side wall and bottom corner of the contact trench and contacting with P-type heavy-doped body region to form an ohmic junction. The first and second conductive materials can respectively optimize the performance of the ohmic contact and the Schottky contact without compromise. Meanwhile, the corner of the contact trench is surrounded by P-type heavy-doped region thereby effectively reducing the leakage currents accumulated at the corner of the contact trench. | 11-22-2012 |
20120292693 | FABRICATION OF TRENCH DMOS DEVICE HAVING THICK BOTTOM SHIELDING OXIDE - Semiconductor device fabrication method and devices are disclosed. A device may be fabricated by forming in a semiconductor layer; filling the trench with an insulating material; removing selected portions of the insulating material leaving a portion of the insulating material in a bottom portion of the trench; forming one or more spacers on one or more sidewalls of a remaining portion of the trench; anisotropically etching the insulating material in the bottom portion of the trench using the spacers as a mask to form a trench in the insulator; removing the spacers; and filling the trench in the insulator with a conductive material. Alternatively, an oxide-nitride-oxide (ONO) structure may be formed on a sidewall and at a bottom of the trench and one or more conductive structures may be formed in a portion of the trench not occupied by the ONO structure. | 11-22-2012 |
20120299089 | Semiconductor Device and Method for Manufacturing the same - It is disclosed a semiconductor device and a method for manufacturing the same. One method comprises providing a semiconductor layer that is formed on an insulating layer; forming a mask pattern on the semiconductor layer, which exposes a portion of the semiconductor layer; removing the exposed portion of the semiconductor layer of a predetermined thickness, thereby forming a groove; forming a gate stack in the mask pattern and the groove; removing the mask pattern to expose a portion of sidewalls of the gate stack. The method not only meets the requirement for a precise thickness of the SOI, but also increases the thickness of the source/drain regions as compared to a device having a uniform SOI thickness at the gate stack, thereby facilitating a reduction of the parasitic resistance of the source/drain regions. | 11-29-2012 |
20120306005 | Trough channel transistor and methods for making the same - The present invention relates to transistor devices having a trough channel structure through which electrical current flows and methods for making the same. A transistor device having a semiconductor trough structure comprises a semiconductor substrate of a first conductivity type having a top surface; a semiconductor trough protruded from the top surface of the substrate along a first direction and having two top surfaces, two outer lateral surfaces, and an inner surface; a layer of isolation insulator disposed on the substrate and abutting the outer lateral surfaces of the semiconductor trough; a gate dielectric layer lining the inner surface and the top surfaces of the semiconductor trough; and a gate electrode disposed on top of the isolation insulator and extending over and filling the semiconductor trough with the gate dielectric layer interposed therebetween. The gate electrode extends along a second direction not parallel to the first direction provided in the semiconductor trough. Regions of the semiconductor trough not directly beneath the gate electrode have a second conductivity type opposite to the first conductivity type provided in the substrate. | 12-06-2012 |
20120306006 | SEMICONDUCTOR POWER DEVICE - A semiconductor power device includes a substrate, a first semiconductor layer on the substrate, a second semiconductor layer on the first semiconductor layer, and a third semiconductor layer on the second semiconductor layer. At least a recessed epitaxial structure is disposed within a cell region and the recessed epitaxial structure may be formed in a pillar or stripe shape. A first vertical diffusion region is disposed in the third semiconductor layer and the recessed epitaxial structure is surrounded by the first vertical diffusion region. A source conductor is disposed on the recessed epitaxial structure and a trench isolation is disposed within a junction termination region surrounding the cell region. In addition, the trench isolation includes a trench, a first insulating layer on an interior surface of the trench, and a conductive layer filled into the trench, wherein the source conductor connects electrically with the conductive layer. | 12-06-2012 |
20120306007 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor device includes a substrate, a gate electrode, source/drain regions, and a gate insulating film. The substrate is made of monocrystalline silicon, an upper surface of the substrate is a (100) plane, and a trench is made in the upper surface. The gate electrode is provided in at least an interior of the trench. The source/drain regions are formed in regions of the substrate having the trench interposed. The gate insulating film is provided between the substrate and the gate electrode. The trench includes a bottom surface made of a (100) plane, a pair of oblique surfaces made of (111) planes contacting the bottom surface, and a pair of side surfaces made of (110) planes contacting the oblique surfaces. The source/drain regions are in contact with the side and oblique surfaces and are apart from a central portion of the bottom surface. | 12-06-2012 |
20120313161 | SEMICONDUCTOR DEVICE WITH ENHANCED MOBILITY AND METHOD - In one embodiment, a vertical insulated-gate field effect transistor includes a feature embedded within a control electrode. The feature is placed within the control electrode to induce stress within predetermined regions of the transistor. | 12-13-2012 |
20120313162 | SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING METAL FILM, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes: a semiconductor substrate; an arsenic diffusion layer formed in the semiconductor substrate and containing arsenic; and a metal film formed on the arsenic diffusion layer. The metal film includes at least one metal selected from the group consisting of tungsten, titanium, ruthenium, hafnium, and tantalum, and arsenic. | 12-13-2012 |
20120313163 | SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING THE SAME - The generation of a variation in properties of vertical transistors is restrained. A vertical MOS transistor is formed in a semiconductor substrate. A first interlayer dielectric film and a first source wiring are formed over the front surface of the substrate. The first source wiring is formed over the first interlayer dielectric film, and is overlapped with the vertical MOS transistor as viewed in plan. Contacts are buried in the first interlayer dielectric film. Through the contacts, an n-type source layer of vertical MOS transistor is coupled with the first source wiring. Openings are made in the first source wiring. | 12-13-2012 |
20120313164 | SEMICONDUCTOR DEVICES - An object of the present application is to reduce the gate capacitance without lowering the withstand voltage of a semiconductor device and prevent generation of a leak current between main electrodes even when an oxide film is formed poorly. A semiconductor device of the present application comprises a gate electrode and a dummy gate electrode. The gate electrode is insulated from an emitter electrode and faces a part of a body region via an insulating film, the part of the body region separating a drift region and an emitter region from each other. The dummy gate electrode is electrically connected with the emitter electrode and is connected with the drift region and the body region via the insulating film. At least a part of the dummy gate electrode comprises a first conductive region of the same type as the drift region. In the dummy gate electrode, the emitter electrode is separated from the drift region by the first conductive region. | 12-13-2012 |
20120319193 | MANUFACTURING OF A SEMICONDUCTOR DEVICE AND CORRESPONDING SEMICONDUCTOR DEVICE - The disclosed method of manufacturing ( | 12-20-2012 |
20120319194 | SEMICONDUCTOR DEVICE AND PROCESS FOR PRODUCING THE SAME - A trench gate transistor whose gate changes depth intermittently in the gate width direction, has a first offset region and a second offset region formed below the source and drain, respectively. The first offset region and the second offset region are shallower where they contact the device isolation film than is the device isolation film in those areas. The first and second offset regions nevertheless extend below the bottom of the trench. | 12-20-2012 |
20120319195 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - The present invention relates to a semiconductor device and a method for manufacturing the same. According to the present invention, a method of manufacturing a semiconductor device includes: forming a recess on a semiconductor substrate; forming a first gate electrode material and a hard mask layer on an entire surface including the recess; etching the hard mask layer and the first gate electrode material to form the first gate electrode pattern on a lower portion of inside of the recess; forming a second gate electrode material on an entire surface including the recess; and etching the second gate electrode material and separating the second gate electrode material. | 12-20-2012 |
20120319196 | SEMICONDUCTOR DEVICE - A semiconductor device includes a transistor with a substrate on which source and drain regions, both of a first conductivity type, and a channel region of a second conductivity type between the source and drain are formed, and a gate electrode formed in the channel region to bury a trench formed so the depth thereof changes intermittently in the width direction of the gate. In the channel region, each on a surface of the substrate and in a bottom portion of the trench, there are formed a second high-concentration region and a first high-concentration region, and the dopant concentration of the second conductivity type is higher than the dopant concentration of the second conductivity type in portions sideward from the trench. The dopant concentration of the second conductivity type in the first high-concentration region is higher than the dopant concentration of the second conductivity type in the second high-concentration region. | 12-20-2012 |
20120326227 | METHOD OF MAKING AN INSULATED GATE SEMICONDUCTOR DEVICE AND STRUCTURE - In one embodiment, a vertical insulated-gate field effect transistor includes a shield electrode formed in trench structure within a semiconductor material. A gate electrode is isolated from the semiconductor material using gate insulating layers. Before the shield electrode is formed, spacer layers can be used form shield insulating layers along portions of the trench structure. The shield insulating layers are thicker than the gate insulating layers. In another embodiment, the shield insulating layers have variable thickness. | 12-27-2012 |
20120326228 | SELF-ALIGNED CARBON ELECTRONICS WITH EMBEDDED GATE ELECTRODE - A device and method for device fabrication includes forming a buried gate electrode in a dielectric substrate and patterning a stack comprising a high dielectric constant layer, a carbon-based semi-conductive layer and a protection layer over the buried gate electrode. An isolation dielectric layer formed over the stack is opened to define recesses in regions adjacent to the stack. The recesses are etched to form cavities and remove a portion of the high dielectric constant layer to expose the carbon-based semi-conductive layer on opposite sides of the buried gate electrode. A conductive material is deposited in the cavities to form self-aligned source and drain regions. | 12-27-2012 |
20130001676 | THROUGH SILICON VIA DIRECT FET SIGNAL GATING - A system comprises a first integrated circuit (IC) chip that includes a first electronic component; a second IC chip that includes a second electronic component; a through silicon via (TSV) in the second IC chip that electrically couples the first electronic component to the second electronic component; and a signal gating transistor that fully occludes the TSV. | 01-03-2013 |
20130001677 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE, AND ELECTRONIC DEVICE - The upper end of a gate electrode is situated below the surface of a semiconductor substrate. An insulating layer is formed over the gate electrode and over the semiconductor substrate situated at the periphery thereof. The insulating layer has a first insulating film and a low oxygen permeable insulating film. The first insulating film is, for example, an NSG film and the low oxygen permeable insulating film is, for example, an SiN film. Further, a second insulating film is formed over the low oxygen permeable insulating film. The second insulating film is, for example, a BPSG film. The TDDB resistance of a vertical MOS transistor is improved by processing with an oxidative atmosphere after forming the insulating layer. Further since the insulating layer has the low oxygen permeable insulating film, fluctuation of the threshold voltage of the vertical MOS transistor can be suppressed. | 01-03-2013 |
20130001678 | HIGH BREAKDOWN VOLTAGE SEMICONDUCTOR DEVICE WITH AN INSULATED GATE FORMED IN A TRENCH, AND MANUFACTURING PROCESS THEREOF - A semiconductor device includes: a semiconductor body; a trench having side walls and a bottom; a gate region made of conductive material, extending within the trench; an insulating region, extending along bottom portions of the side walls of the trench and on the bottom of the trench; a gate insulating layer, extending along top portions of the side walls of the trench, laterally with respect to the gate region; a conductive region, extending within the trench, surrounded at the top and laterally by the gate region and surrounded at the bottom and laterally by the insulating region; and a field insulating layer, arranged between the gate region and the conductive region. The gate insulating layer includes thickened portions, each of which contacts the insulating region and has a thickness that increases as the depth increases. | 01-03-2013 |
20130001679 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a semiconductor layer, a gate trench formed in the semiconductor layer, a source region exposed at a front surface of the semiconductor layer and forming a curved portion of the gate trench, a channel region forming a planar portion of the gate trench, a drain region forming a bottom surface of the gate trench, a gate oxide film formed on an inner surface of the gate trench, a gate electrode embedded inside the gate trench in the planar portion, an embedding insulator film embedded inside the gate trench in the curved portion, a contact trench formed in the semiconductor layer in self-alignment with the curved portion of the gate trench, and a channel contact region formed on a bottom surface of the contact trench. | 01-03-2013 |
20130001680 | SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device (A | 01-03-2013 |
20130001681 | MOS-DRIVEN SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING MOS-DRIVEN SEMICONDUCTOR DEVICE - A mask used to form an n | 01-03-2013 |
20130009237 | CHARGE BALANCE SEMICONDUCTOR DEVICES WITH INCREASED MOBILITY STRUCTURES - Charge balanced semiconductor devices with increased mobility structures and methods for making and using such devices are described. The semiconductor devices contain a substrate heavily doped with a dopant of a first conductivity type, a strained region containing a strain dopant in an upper portion of the substrate, an epitaxial layer being lightly doped with a dopant of a first or second conductivity type on the strained region, a trench formed in the epitaxial layer with the trench containing a MOSFET structure having a drift region overlapping the strained region, a source layer contacting an upper surface of the epitaxial layer and an upper surface of the MOSFET structure, and a drain contacting a bottom portion of the substrate. Since the drift region of the MOSFET structure is formed from the strained region in the substrate, the mobility of the drift region is improved and allows higher current capacity for the trench MOSFET devices. Other embodiments are described. | 01-10-2013 |
20130009238 | ENHANCING SCHOTTKY BREAKDOWN VOLTAGE (BV) WITHOUT AFFECTING AN INTEGRATED MOSFET-SCHOTTKY DEVICE LAYOUT - This invention discloses a semiconductor power device that includes an active cell area having a plurality of power transistor cells. Each of said power transistor cells has a planar Schottky diode that includes a Schottky junction barrier metal covering areas above gaps between separated body regions between two adjacent power transistor cells. The separated body regions further provide a function of adjusting a leakage current of said Schottky diode in each of said power transistor cells. Each of the planar Schottky diodes further includes a Shannon implant region disposed in a gap between the separated body regions of two adjacent power transistor cells for further adjusting a leakage current of said Schottky diode. Each of the power transistor cells further includes heavy body doped regions in the separated body regions next to source regions surrounding said Schottky diode forming a junction barrier Schottky (JBS) pocket region. | 01-10-2013 |
20130009239 | 3-D NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A 3-D non-volatile memory device includes a pipe gate having a first trench formed therein, word lines stacked in multiple layers over the pipe gate, second trenches coupled to the first trench and formed to penetrate the word lines, a first channel layer formed within the first trench, and second channel layers formed within the second trenches, respectively, and coupled to the first channel layer, wherein the width or depth of the first trench is smaller than the diameter of each of the second trenches. | 01-10-2013 |
20130009240 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device including a drain region of a first conductivity type formed on a semiconductor substrate; an element forming region that is provided on the drain region and that has a concave portion reaching the drain region; a gate electrode disposed in the concave portion; a superjunction structure portion that is disposed in the element forming region and that is formed by alternately arranging a drift layer of the first conductivity type penetrated by the concave portion and a resurf layer of a second conductivity type being in contact with the drift layer on the semiconductor substrate; and a base region of the second conductivity type that is disposed on the superjunction structure portion so as to be in contact with the drift layer in the element forming region, that is penetrated by the concave portion, and that faces the gate electrode with the gate insulating film therebetween. | 01-10-2013 |
20130020634 | Semiconductor Device and Electric Power Conversion System Using The Same - A semiconductor device includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type on the first semiconductor layer; trenches in the first semiconductor layer; a semiconductor protruding part on the first semiconductor layer; a third semiconductor layer on the semiconductor protruding part; a fourth semiconductor layer on the third semiconductor layer; a gate insulating layer disposed along the trench; a first interlayer insulating layer disposed along the trench; a first conductive layer facing to the fourth semiconductor layer; a second conductive layer on the first interlayer insulating layer; a second interlayer insulating layer covering the second conductive layer; a third conductive layer on the third semiconductor layer and fourth semiconductor layer; a contacting part connecting the third conductive layer and third semiconductor layer; and a fourth conductive layer formed on the second semiconductor layer. | 01-24-2013 |
20130037879 | VERTICAL DEVICES AND METHODS OF FORMING - Vertical devices and methods of forming the same are provided. One example method of forming a vertical device can include forming a trench in a semiconductor structure, and partially filling the trench with an insulator material. A dielectric material is formed over the insulator material. The dielectric material is modified into a modified dielectric material having an etch rate greater than an etch rate of the insulator material. The modified dielectric material is removed from the trench via a wet etch. | 02-14-2013 |
20130037880 | TRENCH-GATE METAL OXIDE SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF - A trench-gate metal oxide semiconductor device includes a substrate, a first gate dielectric layer, a first gate electrode and a first source/drain structure. The substrate has a first doping region, a second doping region and at least one trench. A P/N junction is formed between the first doping region and the second doping region. The trench extends from a surface of the substrate to the first doping region through the second doping region and the P/N junction. The first gate dielectric layer is formed on a sidewall of the second trench. The first gate electrode is disposed within the trench. A height difference between the top surface of the first gate electrode and the surface of the substrate is substantially smaller than 1500 Å. The first source/drain structure is formed in the substrate and adjacent to the first gate dielectric layer. | 02-14-2013 |
20130037881 | SEMICONDUCTOR DEVICE WITH VERTICAL GATE AND METHOD OF MANUFACTURING THE SAME - A gate electrode is formed in a trench reaching a drain region so as to leave a concave portion on the top of the trench. A first insulating film is formed, which fills the concave portion and of which the thickness increases as the distance from an end of the trench increases on the substrate surface on both sides of the trench. First and second source regions are formed in a self-alignment manner by introduction of impurities through the first insulating film. | 02-14-2013 |
20130043526 | METHOD OF MAKING AN INSULATED GATE SEMICONDUCTOR DEVICE WITH SOURCE-SUBSTRATE CONNECTION AND STRUCTURE - In one embodiment, a source-down vertical insulated gate field effect transistor includes a source contact that is buried within a trench gate structure. Dopant of a first conductivity type is diffused from the conductive source contact into an adjacent semiconductor layer that has a second and opposite conductivity type to form source regions. A self-aligned metal contact is formed within the trench gate structure to short the source contact and the source regions to an underlying substrate. | 02-21-2013 |
20130043527 | SHIELDED GATE TRENCH MOSFET PACKAGE - A shielded gate trench field effect transistor can be formed on a substrate having an epitaxial layer on the substrate and a body layer on the epitaxial layer. A trench formed in the body layer and epitaxial layer is lined with a dielectric layer. A shield electrode is formed within a lower portion of the trench. The shield electrode is insulated by the dielectric layer. A gate electrode is formed in the trench above the shield electrode and insulated from the shield electrode by an additional dielectric layer. One or more source regions formed within the body layer is adjacent a sidewall of the trench. A source pad formed above the body layer is electrically connected to the one or more source regions and insulated from the gate electrode and shield electrode. The source pad provides an external contact to the source region. A gate pad provides an external contact to the gate electrode. A shield electrode pad provides an external contact to the shield electrode. A resistive element can be electrically connected between the shield electrode pad and the source lead in the package. | 02-21-2013 |
20130043528 | Power transistor device and fabricating method thereof - The present invention provides a power transistor device including a substrate, a first epitaxial layer, a doped diffusion region, a second epitaxial layer, a doped base region, and a doped source region. The substrate, the first epitaxial layer, the second epitaxial layer and the doped source region have a first conductive type, and the doped diffusion region and the doped base region have a second conductive type. The first epitaxial layer and the second epitaxial layer are sequentially disposed on the substrate, and the doped diffusion region is disposed in the first epitaxial layer. The doped base region is disposed in the second epitaxial layer and contacts the doped diffusion region, and the doped source region is disposed in the doped base region. A doping concentration of the second epitaxial layer is less than a doping concentration of the first epitaxial layer. | 02-21-2013 |
20130049102 | Buried field ring field effect transistor (BUF-FET) integrated with cells implanted with hole supply path - This invention discloses a semiconductor power device formed in a semiconductor substrate comprises a highly doped region near a top surface of the semiconductor substrate on top of a lightly doped region. The semiconductor power device further comprises a body region, a source region and a gate disposed near the top surface of the semiconductor substrate and a drain disposed at a bottom surface of the semiconductor substrate. The semiconductor power device further comprises source trenches opened into the highly doped region filled with a conductive trench filling material in electrical contact with the source region near the top surface. The semiconductor power device further comprises a buried field ring regions disposed below the source trenches and doped with dopants of opposite conductivity from the highly doped region. In an alternate embodiment, the semiconductor power device further comprises doped regions surrounded the sidewalls of the source trenches and doped with a dopant of a same conductivity type of the buried field ring regions to function as a charge supply path. | 02-28-2013 |
20130056821 | TRENCHED POWER SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A trenched power semiconductor device on a lightly doped substrate is provided. The device has a base, a plurality of trenches including at least a gate trench, a plurality of first heavily doping regions, a body region, a source doped region, a contact window, a second heavily doped region, and a metal layer. The trenches are formed in the base. The first heavily doped regions are beneath the trenches respectively and spaced from the bottom of the respective trench with a lightly doped region. The body region encircles the trenches and is away from the first heavily doped region with a predetermined distance. The source doped region is in an upper portion of the body region. The contact window is adjacent to the edge of the base. The second heavily doped region is below the contact window filled by the metal layer for electrically connecting the second heavily doped region. | 03-07-2013 |
20130056822 | SEMICONDUCTOR DEVICE - A first semiconductor device comprising: a first conductivity type drift region formed in a semiconductor substrate; a second conductivity type body region formed at an upper surface of the semiconductor substrate on an upper surface side of the drift region; a first conductivity type first semiconductor region formed on a part of an upper surface of the body region; and a trench gate type insulated gate penetrating the first semiconductor region and the body region, and formed to a depth at which the insulated gate contacts the drift region. A part of the insulated gate on a drift region side relative to the body region is deeper at a center portion than at both end portions in a longitudinal direction of the insulated gate. | 03-07-2013 |
20130062687 | SRAM CELL HAVING RECESSED STORAGE NODE CONNECTIONS AND METHOD OF FABRICATING SAME - An SRAM cell and a method of forming an SRAM cell. The SRAM cell includes a first pass gate field effect transistor (FET) and a first pull-down FET sharing a first common source/drain (S/D) and a first pull-up FET having first and second S/Ds; a second pass gate FET and a second pull-down FET sharing a second common S/D and a second pull-up FET having first and second S/Ds; a first gate electrode common to the first pull-down FET and the first pull-up FET and physically and electrically contacting the first S/D of the first pull-up FET; a second gate electrode of the first pull-up FET; a third gate electrode common to the second pull-down FET and the second pull-up FET and physically and electrically contacting the first S/D of the second pull-up FET; and a fourth gate electrode of the first pull-up FET. | 03-14-2013 |
20130062688 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to an embodiment, a semiconductor device includes a semiconductor layer, a first semiconductor region provided on the semiconductor layer, a second semiconductor region, a first control electrode and a second control electrode. The first control electrode faces the first and second semiconductor regions through an insulating film in a trench, the trench piercing through the first semiconductor region, the trench having a bottom face at a position deeper than the first semiconductor region. The second control electrode extends to the bottom face of the trench and has a portion between the bottom face and the first control electrode. The semiconductor layer includes a first portion between an end of the first semiconductor region and an end of the second control electrode, a first conductive type carrier concentration in the first portion being lower than a first conductive type carrier concentration in other portions in the semiconductor layer. | 03-14-2013 |
20130062689 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a semiconductor layer of a second conductive type, a first diffused region of a first conductive type formed in the semiconductor layer, a second diffused region of the second conductive type selectively formed in the first diffused region, a trench formed in the semiconductor layer, a gate electrode housed in the trench with a gate insulator intervening, a top surface of the gate electrode being lower than a top surface of the second diffused region, a first oxide film housed in the trench and formed over the gate electrode, a second oxide film housed in the trench and formed over the first oxide film, a third oxide film housed in the trench and formed over the second oxide film, and a source electrode formed over the third oxide film and electrically connecting to the first and second diffused regions. | 03-14-2013 |
20130069143 | TRENCH TYPE POWER TRANSISTOR DEVICE AND METHOD OF FABRICATING THE SAME - The present invention provides a trench type power transistor device including a semiconductor substrate, at least one transistor cell, a gate metal layer, a source metal layer, and a second gate conductive layer. The semiconductor substrate has at least one trench. The transistor cell includes a first gate conductive layer disposed in the trench. The gate metal layer and the source metal layer are disposed on the semiconductor substrate. The second gate conductive layer is disposed between the first gate conductive layer and the source metal layer. The second gate conductive layer electrically connects the first gate conductive layer to the gate metal layer, and the second gate conductive layer is electrically insulated from the source metal layer and the semiconductor substrate. | 03-21-2013 |
20130069144 | TRENCH TRANSISTOR - A method of forming a device is disclosed. A substrate defined with a device region is provided. A buried doped region is formed in the substrate in the device region. A gate is formed in a trench in the substrate in the device region. A channel of the device is disposed on a sidewall of the trench. The buried doped region is disposed below the gate. A distance from the buried doped region to the channel is a drift length L | 03-21-2013 |
20130069145 | POWER SEMICONDUCTOR DEVICE - A power semiconductor device according to one embodiment includes a first electrode, a semiconductor substrate provided on the first electrode, and an insulating member. A terminal trench is made in the upper surface of the semiconductor substrate in a region including a boundary between a cell region and a terminal region. The semiconductor substrate includes a first portion of a first conductivity type and connected to the first electrode, a second portion of the first conductivity type, a third portion of a second conductivity type provided on the second portion in the cell region and connected to the second electrode, and a fourth portion of the first conductivity type selectively provided on the third portion and connected to the second electrode. The insulating member is disposed between the third portion and the second portion in a direction from the cell region toward the terminal region. | 03-21-2013 |
20130069146 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a method for manufacturing a semiconductor device includes: forming a plurality of trenches; forming a gate insulating film; burying a gate electrode; burying an insulating member; projecting the insulating member; forming a base layer; forming a mask film; forming a first semiconductor layer; forming a carrier ejection layer; forming a first electrode; and forming a second electrode. The projecting includes projecting the insulating member from the upper surface of the semiconductor substrate by removing an upper layer portion of the semiconductor substrate. The mask film is formed so as to cover the projected insulating member. The forming the first semiconductor layer includes forming a first semiconductor layer of the first conductivity type in an upper layer portion of the base layer by doping the base layer with impurity, the upper layer portion having a lower surface below an upper end of the gate electrode. | 03-21-2013 |
20130069147 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to an embodiment, a semiconductor device includes a semiconductor layer of a first conductive type, a base region of a second conductive type provided on the semiconductor layer and a first contact region of a second conductive type provided on the base region. The device includes a gate electrode provided in a trench piercing through the first contact region and the base region, and an interlayer insulating film provided on the gate electrode and containing a first conductive type impurity element. The device further includes a source region of a first conductive type provided between the interlayer insulating film and the first contact region, the source region being in contact with a side face of the interlayer insulating film and extending in the base region. | 03-21-2013 |
20130069148 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - According to one embodiment, a semiconductor device includes an element region partitioned by an isolation region in a semiconductor substrate, and a source region and a drain region formed in a surface layer of the element region by being isolated by a gate trench along a predetermined direction across the element region. The semiconductor device includes a gate electrode formed to reach a position deeper than the source region and the drain region by embedding at least part thereof in the gate trench with a gate dielectric film interposed therebetween. An interface in the drain region, which is in contact with the gate dielectric film, includes a projection projecting toward the gate electrode side. | 03-21-2013 |
20130069149 | METHOD FOR PRODUCING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method for producing a semiconductor device includes the steps of forming first and second pillar-shaped semiconductors on a substrate at the same time so as to have the same height; forming a first semiconductor layer by doping a bottom region of the first pillar-shaped semiconductor with a donor or acceptor impurity to connect the first semiconductor layer to the second pillar-shaped semiconductor; forming a circuit element including an upper semiconductor region formed by doping an upper region of the first pillar-shaped semiconductor with a donor or acceptor impurity; forming a first conductor layer in the second pillar-shaped semiconductor; forming first and second contact holes that are respectively connected to the first and second pillar-shaped semiconductors; and forming a wiring metal layer that is connected to the upper semiconductor region and the first conductor layer through the first and second contact holes, respectively. | 03-21-2013 |
20130069150 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - According to one embodiment, a semiconductor device includes a semiconductor layer; a plurality of semiconductor regions; second semiconductor region; a first electrode being positioned between the plurality of first semiconductor regions, the first electrode contacting with the semiconductor layer, each of the plurality of first semiconductor regions, and the second semiconductor region via a first insulating film; a second electrode provided below the first electrode, and contacting with the semiconductor layer via a second insulating film; an insulating layer interposed between the first electrode and the second electrode; a third electrode electrically connected to the semiconductor layer; and a fourth electrode connected to the second semiconductor region. The first electrode has a first portion and a pair of second portions. And each of the pair of second portions is provided along the first insulating film. | 03-21-2013 |
20130075812 | SINGLE-SIDED ACCESS DEVICE AND FABRICATION METHOD THEREOF - A single-sided access device includes an active fin structure comprising a source contact area and a drain contact area separated from each other by an isolation region therebetween; a trench isolation structure disposed at one side of the active fin structure, wherein the trench isolation structure intersects with the isolation region between the source contact area and the drain contact area; a sidewall gate disposed under the isolation region and on the other side of the active fin structure opposite to the trench isolation structure so that the active fin structure is sandwiched by the trench isolation structure and the sidewall gate, wherein the sidewall gate has multi-fingers that engage with the active fin structure; and a gate dielectric layer between the sidewall gate and the active fin structure. | 03-28-2013 |
20130075813 | SEMICONDUCTOR DEVICE - A method of forming a semiconductor device includes the following processes. A first semiconductor structure is formed, which extends upwardly in a direction perpendicular to a main surface from a surface of a semiconductor substrate. A first insulating film is formed which extends on a surface of the first semiconductor structure. A gate electrode is formed which extends on the first insulating film. The gate electrode has a top surface which is lower than a top surface of the first semiconductor structure. A liner film is formed, which may include, but is not limited to, first and second liner portions. The first liner portion covers the gate electrode. The second liner portion extends upwardly from the top surface of the gate electrode. The liner film includes nitrogen and oxygen. | 03-28-2013 |
20130087852 | EDGE TERMINATION STRUCTURE FOR POWER SEMICONDUCTOR DEVICES - Edge termination structures for power semiconductor devices and methods for making such structures are described. The power semiconductor devices (or power devices) contain a substrate with an epitaxial layer thereon, an array of substantially-parallel, active trenches formed in the epitaxial layer, with the active trenches containing a transistor structure with an insulated gate conducting layer, a superjunction or shielded region adjacent the active trenches; a peripheral trench surrounding the active trenches, and a source contact area within an upper surface of the epitaxial layer, where the gate conducting layer extends over the superjunction or shielded region and over the surrounding peripheral trench. Such a configuration allows the edge termination structure to be used with a wide range of breakdown voltages in power MOSFET devices containing PN superjunction structures. Other embodiments are described. | 04-11-2013 |
20130087853 | SEMICONDUCTOR DEVICE HAVING SADDLE FIN TRANSISTOR AND MANUFACTURING METHOD OF THE SAME - The present invention discloses a transistor having the saddle fin structure. The saddle fin transistor of the present invention has a structure in which a landing plug contact region, particularly, a landing plug contact region on an isolation layer is elevated such that the landing plug contact SAC (Self Aligned Contact) fail can be prevented. | 04-11-2013 |
20130093006 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a semiconductor layer, an insulating film, a gate electrode, a drain electrode, and a source electrode. The semiconductor layer includes an active layer and is formed on a semi-insulating semiconductor substrate, and a tapered recess area having an inclined sidewall is formed on a surface of the semiconductor layer. The insulating film is formed on the semiconductor layer and has a through hole for exposing the recess area. The through hole has a tapered sidewall which is inclined at an angle smaller than the sidewall of the recess area. The gate electrode is formed so as to fill the recess area and the through hole. The drain electrode and the source electrode are formed at positions on opposite sides of the recess area on the semiconductor layer. | 04-18-2013 |
20130093007 | SEMICONDUCTOR MEMORY APPARATUS AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor memory apparatus is provided to minimize failure of the semiconductor memory apparatus and to secure a processing margin. The method also provides for minimizing the deterioration of an operating speed and the operational stability, and minimizing the increase of resistance occurring as a result of a reduced processing margin when forming a gate pattern in a peripheral region of the semiconductor memory apparatus. The method includes forming a connection pad in a peripheral region while forming a buried word line in a cell region, and forming a gate pattern in the peripheral region while forming a bit line in the cell region. | 04-18-2013 |
20130093008 | TRENCH MOSFET DEVICE AND METHOD FOR FABRICATING THE SAME - A trench Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) device is disclosed. The trench MOSFET device includes a substrate, a body region, a source region, a dielectric layer, a metal layer, a contact hole, and a trench structure. The substrate includes a substrate layer and an epitaxial layer formed on the substrate layer; the body region is formed in the epitaxial layer; and the source region is formed in the body region of the epitaxial layer. Further, the dielectric layer is formed on the epitaxial layer; the metal layer is formed on the dielectric layer; and the contact hole is formed in the dielectric layer to connect the source region with the metal layer. In addition, the trench structure is formed in the epitaxial layer, and the trench structure includes a first trench that is a pectinate trench including a plurality of tooth trenches and a bar trench interconnecting the plurality of tooth trenches. | 04-18-2013 |
20130099307 | SEMICONDUCTOR DEVICE HAVING METAL GATE AND MANUFACTURING METHOD THEREOF - A manufacturing method of a semiconductor device having metal gate includes providing a substrate having a first semiconductor device and a second semiconductor device formed thereon, the first semiconductor device having a first gate trench and the second semiconductor device having a second gate trench, forming a first work function metal layer in the first gate trench, forming a second work function metal layer in the first gate trench and the second gate trench, forming a first patterned mask layer exposing portions of the second work function metal layer in the first gate trench and the second gate trench, and performing an etching process to remove the exposed second work function metal layer. | 04-25-2013 |
20130099308 | Semiconductor Device Having a Through Contact and a Manufacturing Method Therefor - According to an embodiment, a method of forming a semiconductor device includes: providing a wafer having a semiconductor substrate with a first side a second side opposite the first side, and a dielectric region arranged on the first side; mounting the wafer with the first side on a carrier system; etching a deep vertical trench from the second side through the semiconductor substrate to the dielectric region, thereby insulating a mesa region from the remaining semiconductor substrate; and filling the deep vertical trench with a dielectric material. | 04-25-2013 |
20130099309 | VERTICAL MOSFET ELECTROSTATIC DISCHARGE DEVICE - A vertical MOSFET electrostatic discharge device is disclosed, including a substrate comprising a plurality of trenches, a recessed gate disposed in each trench, a drain region disposed between each of the two neighboring recessed gates, an electrostatic discharge implant region disposed under each drain region, and a source region surrounding and disposed under the recessed gates and the electrostatic discharge implant regions. | 04-25-2013 |
20130099310 | Trench MOS Device with Schottky Diode and Method for Manufacturing Same - In one embodiment the present invention includes a semiconductor device. The semiconductor device comprises a first semiconductor region, a second semiconductor region and a trench region. The first semiconductor region is of a first conductivity type and a first conductivity concentration. The trench region includes a metal layer in contact with the first semiconductor region to form a metal-semiconductor junction. The second semiconductor region is adjacent to the first semiconductor region that has a second conductivity type and a second conductivity concentration. The second semiconductor region forms a PN junction with the first semiconductor region, and the trench region has a depth such that the metal-semiconductor junction is proximate to the PN junction. | 04-25-2013 |
20130105885 | CANYON GATE TRANSISTOR AND METHODS FOR ITS FABRICATION | 05-02-2013 |
20130105886 | TWO-DIMENSIONAL SHIELDED GATE TRANSISTOR DEVICE AND METHOD OF MANUFACTURE | 05-02-2013 |
20130105887 | Vertical Gate LDMOS Device | 05-02-2013 |
20130105888 | Transistor with Buried P+ and Source Contact | 05-02-2013 |
20130105889 | SWITCHING DEVICE AND METHOD FOR MANUFACTURING THE SAME | 05-02-2013 |
20130113038 | TRENCH MOSFET WITH SPLIT TRENCHED GATE STRUCTURES IN CELL CORNERS FOR GATE CHARGE REDUCTION - A trench MOSFET with closed cells having split trenched gates structure in trenched gates intersection area in cell corner is disclosed. The invented split trenched gates structure comprises an insulation layer between said split trenched gates with thick thermal oxide layer in center portion of the trenched gates intersection area, therefore further reducing Qgd of the trench MOSFET without increasing additional Rds. | 05-09-2013 |
20130113039 | SEMICONDUCTOR DEVICE - A semiconductor device provides a MOSFET having first and second regions. In the first region, a plurality of unit cells of the MOSFET device are provided. At the end of the plurality of the unit cells, a termination cell is provided. An n type layer underlies the unit cells, between the unit cells and an underlying electrode. In the unit cell region, this n doped layer is dually doped with impurities at two different densities, whereas, adjacent the termination cell, a different paradigm is provided. In one aspect, only one of the two n doped layers extends along a side of the termination cell. In a second aspect, the termination unit is in contact with an oppositely doped layer as compared to the impurities in the dual doped layer. In this way, breakdown voltage may be maintained while on-resistance is simultaneously reduced. | 05-09-2013 |
20130113040 | Semiconductor Device Comprising Transistor Structures and Methods for Forming Same - A method for forming an opening within a semiconductor material comprises forming a neck portion, a rounded portion below the neck portion and, in some embodiments, a protruding portion below the rounded portion. This opening may be filled with a conductor, a dielectric, or both. Embodiments to form a transistor gate, shallow trench isolation, and an isolation material separating a transistor source and drain are disclosed. Device structures formed by the method are also described. | 05-09-2013 |
20130119460 | TRENCH TYPE POWER TRANSISTOR DEVICE AND FABRICATING METHOD THEREOF - The present invention provides a trench type power transistor device including a substrate, an epitaxial layer, a doped diffusion region, a doped source region, and a gate structure. The substrate, the doped diffusion region, and the doped source region have a first conductivity type, and the substrate has an active region and a termination region. The epitaxial layer is disposed on the substrate, and has a second conductivity type. The epitaxial layer has a through hole disposed in the active region. The doped diffusion region is disposed in the epitaxial layer at a side of the through hole, and is in contact with the substrate. The doped source region is disposed in the epitaxial layer disposed right on the doped diffusion region, and the gate structure is disposed in the through hole between the doped diffusion region and the doped source region. | 05-16-2013 |
20130119461 | SEMICONDUCTOR DEVICE HAVING A BURIED GATE AND METHOD FOR FORMING THEREOF - A semiconductor device includes: a first interlayer insulating layer in first and second regions of a semiconductor substrate, a second interlayer insulating layer over the first interlayer insulating layer in first and second regions, a hard mask provided between the first and the second interlayer insulating layers in the second region and not extending to the first region, a first metal contact formed through the second interlayer insulating layer and the hard mask in the second region, and a first storage node contact formed through the first interlayer insulating layer in the first region. | 05-16-2013 |
20130126965 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device has an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. The conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. After etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate, a channel region and a source region are formed by ion implantation so that the semiconductor device is free from occurrence of a source offset. | 05-23-2013 |
20130126966 | OXIDE TERMINATED TRENCH MOSFET WITH THREE OR FOUR MASKS - An oxide termination semiconductor device may comprise a plurality of gate trenches, a gate runner, and an insulator termination trench. The gate trenches are located in an active region. Each gate trench includes a conductive gate electrode. The insulator termination trench is located in a termination region that surrounds the active region. The insulator termination trench is filled with an insulator material to form an insulator termination for the semiconductor device. The device can be made using a three-mask or four-mask process. | 05-23-2013 |
20130134504 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In one embodiment, a semiconductor device includes a substrate including a trench, and a gate electrode disposed at a position adjacent to the trench on the substrate, the gate electrode having a first side surface located on an opposite side of the trench, and a second side surface located on the same side as the trench. The device further includes a first sidewall insulator disposed on the first side surface, and a second sidewall insulator disposed on the second side surface and a side surface of the trench. The device further includes a source region of a first conductivity type disposed in the substrate on the same side as the first sidewall insulator with respect to the first side surface, and a drain region of a second conductivity type disposed in the substrate on the same side as the second sidewall insulator with respect to the second side surface. | 05-30-2013 |
20130134505 | SEMICONDUCTOR DEVICE FOR POWER AND METHOD OF MANUFACTURE THEREOF - According to one embodiment, a semiconductor device for power is provided with a first conductive type a first semiconductor layer, a field insulating film, a field plate electrode, a first insulating film, an electric conductor, a second insulating film, a gate insulating film, and a gate electrode. The field plate electrode is installed in a trench of the first semiconductor layer over the field insulating film. The first insulating film is formed on the field plate electrode and encloses the field plate electrode along with the field insulating film. The electric conductor is formed on the first insulating film and is insulated from the field plate electrode. The gate electrode is installed on the upper end of the field insulating film, adjacently makes contact with the electric conductor via the second insulating film, and is installed in the trench over the gate insulating film. | 05-30-2013 |
20130134506 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SAME - A fin type semiconductor layer is formed on a substrate with a source and a drain. A dummy gate is formed crossing the fin type semiconductor layer. After depositing an insulating film on the dummy gate, the upper surface of the dummy gate is exposed. The dummy gate is then removed to form a gate trench. On the surface of the fin type semiconductor layer in the gate trench, a gate insulating film is formed. Material for a gate electrode is filled in the gate trench and etched to form the gate electrode. The height of the upper surface of the gate electrode is equal to or lower than the height of the upper surface of the fin type semiconductor layer at the source and the drain, and is equal to or higher than the height of the upper surface of the fin type semiconductor layer in the gate trench. | 05-30-2013 |
20130140630 | TRENCH SCHOTTKY DIODE AND MANUFACTURING METHOD THEREOF - A trench Schottky diode and a manufacturing method thereof are provided. The manufacturing method includes the following steps. Firstly, a semiconductor substrate is provided. A multi-trench structure including a wide trench and a plurality of narrow trenches is formed in the semiconductor substrate, a gate oxide layer is formed on a surface of the multi-trench structure, and a polysilicon structure is formed over the gate oxide layer and the first oxide layer. The polysilicon structure is etched to partially expose the first oxide layer and the gate oxide layer on a bottom surface of the wide trench. The semiconductor substrate, the polysilicon structure and the gate oxide layer are partially exposed by a photolithography and etching process. A metal sputtering layer is formed. Afterwards, the metal sputtering layer is etched to expose a part of the second oxide layer. | 06-06-2013 |
20130146966 | SEMICONDUCTOR STRUCTURE WITH ENHANCED CAP AND FABRICATION METHOD THEREOF - A semiconductor structure includes a substrate, a feature on the substrate, a spacer on a sidewall surface of the feature, and an enhanced cap disposed on an upper surface of the spacer. The enhanced cap compensates the thinner upper portion of the spacer. | 06-13-2013 |
20130146967 | Trench-Gate Resurf Semiconductor Device and Manufacturing Method - A trench-gate device with lateral RESURF pillars has an additional implant beneath the gate trench. The additional implant reduces the effective width of the semiconductor drift region between the RESURF pillars, and this provides additional gate shielding which improves the electrical characteristics of the device. | 06-13-2013 |
20130146968 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - In the semiconductor device, a line-type buried gate is formed by burying a non-operating gate (isolation gate) with a polysilicon material to reduce a work function and a Gate Induced Drain Leakage (GIDL) caused by the non-operating gate, resulting in improvement of refresh characteristics of the semiconductor device. Operating gates including a metal conductive material may be formed in a separate step. | 06-13-2013 |
20130146969 | SWITCHING ELEMENT AND MANUFACTURING METHOD THEREOF - A switching element is provided having a semiconductor substrate. A trench gate electrode is formed in the upper surface of the semiconductor substrate. An n-type first semiconductor region, a p-type second semiconductor region, and an n-type third semiconductor region are formed in a region in contact with a gate insulating film in the semiconductor substrate. At a position below the second semiconductor region, there is formed a p-type fourth semiconductor region connected to the second semiconductor region and opposing the gate insulating film via the third semiconductor region and containing boron. A high-concentration-carbon containing region having a carbon concentration higher than that of a semiconductor region exposed on the lower surface of the semiconductor substrate is formed in at least a part of the portion of the third semiconductor region, positioned between the fourth semiconductor region and the gate insulating film, that is in contact with the fourth semiconductor region. | 06-13-2013 |
20130153991 | ELECTRONIC DEVICE COMPRISING CONDUCTIVE STRUCTURES AND AN INSULATING LAYER BETWEEN THE CONDUCTIVE STRUCTURES AND WITHIN A TRENCH AND A PROCESS OF FORMING THE SAME - An electronic device can include a substrate including an underlying doped region and a semiconductor layer overlying the substrate. A trench can have a sidewall and extend at least partly through the semiconductor layer. The electronic device can further include a first conductive structure adjacent to the underlying doped region, an insulating layer, and a second conductive structure within the trench. The insulating layer can be disposed between the first and second conductive structures, and the first conductive structure can be disposed between the insulating layer and the underlying doped region. Processes of forming the electronic device may be performed such that the first conductive structure includes a conductive fill material or a doped region within the semiconductor layer. The first conductive structure can allow the underlying doped region to be farther from the channel region and allow R | 06-20-2013 |
20130153992 | ELECTRONIC DEVICE INCLUDING A TAPERED TRENCH AND A CONDUCTIVE STRUCTURE THEREIN AND A PROCESS OF FORMING THE SAME - An electronic device can include a semiconductor layer, and a trench extending into the semiconductor layer and having a tapered shape. In an embodiment, the trench includes a wider portion and a narrower portion. The electronic device can include a doped semiconductor region that extends to a narrower portion of the trench and has a dopant concentration greater than a dopant concentration of the semiconductor layer. In another embodiment, the electronic device can include a conductive structure within a relatively narrower portion of the trench, and a conductive electrode within a relatively wider portion of the trench. In another embodiment, a process of forming the electronic device can include forming a sacrificial plug and may allow insulating layers of different thicknesses to be formed within the trench. | 06-20-2013 |
20130153993 | HYBRID CMOS NANOWIRE MESH DEVICE AND FINFET DEVICE - A method of forming a hybrid semiconductor structure on an SOI substrate. The method includes an integrated process flow to form a nanowire mesh device and a FINFET device on the same SOI substrate. Also included is a semiconductor structure which includes the nanowire mesh device and the FINFET device on the same SOI substrate. | 06-20-2013 |
20130153994 | TRENCH TYPE POWER TRANSISTOR DEVICE WITH SUPER JUNCTION AND MANUFACTURING METHOD THEREOF - The present invention provides a manufacturing method of a trench type power transistor device with a super junction. First, a substrate of a first conductivity type is provided, and then an epitaxial layer of a second conductive type is formed on the substrate. Next, a through hole is formed in the epitaxial layer, and the through hole penetrates through the epitaxial layer. Two doped drain regions of the first conductivity type are then formed in the epitaxial layer respectively at two sides of the through hole, and the doped drain regions extend from a top surface of the epitaxial layer to be in contact with the substrate. | 06-20-2013 |
20130153995 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a first region with second conductivity type formed over a semiconductor layer with first conductivity type. On this first region, the second region of the first conductivity type is selectively provided. On the same first region, a third region of second conductivity type is also selectively provided and is adjoined to the second region. The first control electrode is provided within a trench located deeper than the first side of the second region compared to the first region. The first control electrode includes a part opposed to the first and second regions separated by a first insulator, and a second part opposed to the semiconductor layer separated by a thicker second insulator. Inside the trench, the second control electrode is provided between the trench bottom and the first control electrode. The second control electrode is opposed to the semiconductor layer through a third insulator. | 06-20-2013 |
20130161734 | TRANSISTOR STRUCTURE AND METHOD FOR PREPARING THE SAME - A buried channel transistor has a semiconductor substrate, a trench and a doped region. The semiconductor substrate has a first surface and a well under the first surface. The trench is disposed in the semiconductor substrate and extends from the first surface into the well. The trench includes a buried gate structure inside the trench. The buried gate structure has a first workfunction layer, a second workfunction layer with a dopant type opposite to that of the first workfunction layer. The second workfunction layer is disposed adjacent to the first workfunction layer. The buried gate structure further includes a dielectric layer adjacent to the trench inner sidewall. The dielectric layer separates the workfunction layers from the semiconductor substrate. The doped region is disposed in the semiconductor substrate and located above the well. The dopant type of the doped region is opposite to that of the first workfunction layer. | 06-27-2013 |
20130161735 | TRANSISTOR STRUCTURE AND METHOD FOR PREPARING THE SAME - A transistor structure includes a semiconductor substrate; a conductor having a lower block in the semiconductor substrate and an upper block on the semiconductor substrate; a metal layer positioned on the upper block; a cap layer positioned on the metal layer; an upper insulation layer positioned at least on sidewalls of the metal layer and the cap layer; and a lower insulation layer positioned on sidewalls of the upper block of the conductor. | 06-27-2013 |
20130161736 | TRENCH METAL OXIDE SEMICONDUCTOR TRANSISTOR DEVICE AND MANUFACTURING METHOD THEREOF - A trench metal oxide semiconductor transistor device and a manufacturing method thereof are described. The trench metal oxide semiconductor transistor device includes a substrate of a first conductivity type, a drift region of the first conductivity type, a deep trench doped region of a second conductivity type, an epitaxial region of the second conductivity type, a trench gate, a gate insulating layer, a source region, a drain electrode and a source electrode. The drift region has at least one deep trench therein, and the deep trench doped region is disposed in the deep trench. The trench gate passes through the epitaxial region, and a distance between a bottom of the trench gate and a bottom of the deep trench doped region is 0.5˜3 um. | 06-27-2013 |
20130161737 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - There are provided a semiconductor device and a method of manufacturing the same, capable of removing a shoot-through phenomenon by forming capacitance between an electrode and a lateral surface of a protrusion region of a gate and increasing a gate-source capacitance. The semiconductor device may include: a semiconductor body having a predetermined volume; a source formed on an upper surface of the semiconductor body; a gate formed in a groove of the semiconductor body and having a protrusion region protruded upwardly of the upper surface of the semiconductor body, the groove having a predetermined depth and the protrusion region having a protrusion height altered depending on a level of capacitance to be set; and an electrode electrically connected to the source to form capacitance together with a lateral surface of the protrusion region of the gate. | 06-27-2013 |
20130168760 | TRENCH MOSFET WITH RESURF STEPPED OXIDE AND DIFFUSED DRIFT REGION - A trench MOSFET with split gates and diffused drift region for on-resistance reduction is disclosed. Each of the split gates is symmetrically disposed in the middle of the source electrode and adjacent trench sidewall of a deep trench. The inventive structure can save a mask for definition of the location of the split gate electrodes. Furthermore, the fabrication method can be implemented more reliably with lower cost. | 07-04-2013 |
20130168761 | SEMICONDUCTOR POWER DEVICE HAVING IMPROVED TERMINATION STRUCTURE FOR MASK SAVING - A improved termination structure for semiconductor power devices is disclosed, comprising a trenched field plate formed not only along trench sidewall but also on trench bottom of the wide termination trench by doing poly-silicon CMP so that body ion implantation is blocked by the trenched field plate on the trench bottom to prevent a body region formation underneath the trench bottom of the wide termination trench, degrading avalanche voltage. | 07-04-2013 |
20130168762 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor layer of a first conductivity type having a first surface and a second surface, a source region disposed on the first surface, a gate region disposed on the first surface adjacent the source region, and a drain region disposed on the first surface. The semiconductor device also includes a pair of charge control trenches disposed between the gate region and the drain region. Each of the pair of charge control trenches is characterized by a width and includes a first dielectric material disposed therein and a second material disposed internal to the first dielectric material. Additionally, a concentration of doping impurities present in the semiconductor layer of the first conductivity type and a distance between the pair of charge control trenches define an electrical characteristic of the semiconductor device that is independent of the width of each of the pair of charge control trenches. | 07-04-2013 |
20130168763 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - An oxide film is formed by STI in a silicon surface region in which a substrate potential heavily doped diffusion layer and a source heavily doped diffusion layer are to be provided later between trenches at predetermined intervals. The oxide film is removed after the trench is formed, to thereby form a region which is lower than a surrounding surface. Thus, in the vertical MOS transistor having a trench structure which includes a side spacer, a silicide on a gate electrode embedded in the trench and a silicide on the substrate potential heavily doped diffusion layer and the source heavily doped diffusion layer can be separated from each other. | 07-04-2013 |
20130175610 | TRANSISTOR WITH STRESS ENHANCED CHANNEL AND METHODS FOR FABRICATION - A transistor device and methods for its fabrication are provided. In an embodiment, the transistor is fabricated within and on a surface of a semiconductor substrate. The method includes forming a gate structure with a dummy gate electrode material overlying the semiconductor substrate. Recesses are etched into the semiconductor substrate adjacent the gate structure to define a narrow region between the recesses at a selected depth under the surface. The recesses are filled with a stress-inducing material and the dummy gate electrode material is removed to expose the semiconductor substrate. The method further provides for etching the exposed semiconductor substrate to form a recessed gate surface and defining a channel under the recessed gate surface in the narrow region. | 07-11-2013 |
20130181281 | Semiconductor Transistor Having Trench Contacts and Method for Forming Therefor - Embodiments described herein relate to semiconductor transistors having trench contacts, in particular to semiconductor transistors having a field electrode below a gate electrode, and to related methods for producing semiconductor transistors having trench contacts. | 07-18-2013 |
20130181282 | FIELD EFFECT TRANSISTOR WITH SELF-ALIGNED SOURCE AND HEAVY BODY REGIONS - A field effect transistor includes a plurality of trenches extending into a semiconductor region of a first conductivity type. The plurality of trenches includes a plurality of gated trenches and a plurality of non-gated trenches. A body region of a second conductivity extends in the semiconductor region between adjacent trenches. A dielectric material fills a bottom portion of each of the gated and non-gated trenches. A gate electrode is disposed in each gated trench. A conductive material of the second conductivity type is disposed in each non-gated trench such that the conductive material and contacts corresponding body regions along sidewalls of the non-gated trench. | 07-18-2013 |
20130181283 | SWITCHING ELEMENT - In a switching element, a first region that is exposed on an upper surface of a semiconductor substrate, a second region that is exposed on the upper surface of the substrate and extends to below the first region, and a third region that is formed below the second region, are formed on the substrate. A trench is formed in the upper surface of the substrate. A gate electrode has a first portion that extends from a depth of the first region to a depth of the third region at at least a portion in the trench formed in an area where the first region is exposed, and a second portion that is formed to a depth of the second region, and does not reach the depth of the third region, at at least a portion in the trench formed in an area where the second region is exposed. | 07-18-2013 |
20130187223 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A gate trench | 07-25-2013 |
20130193509 | SOI LATERAL MOSFET DEVICES - The present invention relates to a semiconductor power device and power integrated circuits (ICs). The lateral SOI MOSFET in the present comprises a trench gate extended to the dielectric buried layer, one or multiple dielectric trenches in the drift region, and a buried gate in said dielectric trench. The permittivity of the dielectric in said dielectric trench is lower than that of said active layer. Firstly, said dielectric trench not only greatly improves breakdown voltage, but also reduces pitch size. Secondly, the trench gate widens the effective conductive region in the vertical direction. Thirdly, dual gates of said trench gate and buried gate increase channel and current densities. Thereby, specific on-resistance and the power loss are reduced. The device of the present invention has many advantages, such as high voltage, high speed, low power loss, low cost and ease of integration. The device in the present invention is particularly suitable for power integrated circuits and RF power integrated circuits. | 08-01-2013 |
20130214348 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - In a vertical transistor, to raise a drain withstand voltage while lowering an on-resistance. A drift layer | 08-22-2013 |
20130214349 | Trench MOSFET Structure and Method of Making the Same - A trench MOSFET sidewall structure includes a heavily doped substrate, a lightly doped epitaxial layer, a lightly doped well and a heavily doped source adjacent to one another to form a semiconductor substrate. Multiple trenches as well as multiple contact holes are defined in the substrate and each contact hole respectively is defined between two adjacent trenches. A top portion of the contact hole has a size larger than that of a bottom portion of the contact hole. | 08-22-2013 |
20130221427 | Semiconductor Device With Improved Robustness - A semiconductor device includes a first contact in low Ohmic contact with a source region of the device and a first portion of a body region of the device formed in an active area of the device, and a second contact in low Ohmic contact with a second portion of the body region formed in a peripheral area of the device. The minimum width of the second contact at a first surface of the device is larger than the minimum width of the first contact at the first surface so that maximum current density during commutating the semiconductor device is reduced and thus the risk of device damage during hard commutating is also reduced. | 08-29-2013 |
20130221428 | PROCESS OF FORMING AN ELECTRONIC DEVICE INCLUDING A TRENCH AND A CONDUCTIVE STRUCTURE THEREIN - An electronic device can include a transistor structure, including a patterned semiconductor layer overlying a substrate and having a primary surface, wherein the patterned semiconductor layer defines a first trench and a second trench that extend from the primary surface towards the substrate. The electronic device can further include a first conductive electrode and a gate electrode within the first trench. The electronic device can still further include a second conductive electrode within the second trench. The electronic device can include a source region within the patterned semiconductor layer and disposed between the first and second trenches. The electronic device can further include a body contact region within the patterned semiconductor layer and between the first and second trenches, wherein the body contact region is spaced apart from the primary surface. Processes of forming the electronic device can take advantage of forming all trenches during processing sequence. | 08-29-2013 |
20130221429 | METHOD AND APPARATUS RELATED TO A JUNCTION FIELD-EFFECT TRANSISTOR - In a general aspect, a semiconductor device can include a gate having a first trench portion disposed within a first trench of a junction field-effect transistor device, a second trench portion disposed within a second trench of the junction field-effect transistor device, and a top portion coupled to both the first trench portion and to the second trench portion. The semiconductor device can include a mesa region disposed between the first trench and the second trench, and including a single PN junction defined by an interface between a substrate dopant region having a first dopant type and a channel dopant region having a second dopant type. | 08-29-2013 |
20130221430 | NANO-TUBE MOSFET TECHNOLOGY AND DEVICES - This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of trenches. Each of the trenches is filled with a plurality of epitaxial layers of alternating conductivity types constituting nano tubes functioning as conducting channels stacked as layers extending along a sidewall direction with a “Gap Filler” layer filling a merging-gap between the nano tubes disposed substantially at a center of each of the trenches. The “Gap Filler” layer can be very lightly doped Silicon or grown and deposited dielectric layer. In an exemplary embodiment, the plurality of trenches are separated by pillar columns each having a width approximately half to one-third of a width of the trenches. | 08-29-2013 |
20130221431 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE THEREOF - A method for manufacturing a semiconductor device includes forming a first insulating film on inner surfaces of trenches arranged in parallel in a semiconductor layer, forming a control electrode on the first insulating film, and forming a second insulating film on the control electrode, where the upper surface of the second insulating film is lower than the upper end of the first insulating film. In addition, the method includes etching the semiconductor layer to a depth near the upper end of the control electrode and forming a first semiconductor region. The method further includes forming a conductive film and then a second semiconductor region in the upper portion of the first semiconductor region by diffusion of impurities from the conductive film into the upper portion of the first semiconductor region, and forming a contact hole by etching back the conductive layer. | 08-29-2013 |
20130221432 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is a semiconductor device having a vertical MOS transistor and a method of manufacturing the same. The vertical MOS transistor has a trench gate, a distance between a gate electrode and an N-type high concentration buried layer below the gate electrode is formed longer than that in the conventional structure, and a P-type trench bottom surface lower region ( | 08-29-2013 |
20130221433 | Vertical Semiconductor Device with Thinned Substrate - A vertical semiconductor device is formed in a semiconductor layer having a first surface, a second surface and background doping. A first doped region, doped to a conductivity type opposite that of the background, is formed at the second surface of the semiconductor layer. A second doped region of the same conductivity type as the background is formed at the second surface of the semiconductor layer, inside the first doped region. A portion of the semiconductor layer is removed at the first surface, exposing a new third surface. A third doped region is formed inside the semiconductor layer at the third surface. Electrical contact is made at least to the second doped region (via the second surface) and the third doped region (via the new third surface). In this way, vertical DMOS, IGBT, bipolar transistors, thyristors, and other types of devices can be fabricated in thinned semiconductor, or SOI layers. | 08-29-2013 |
20130221434 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SAME - It is an object to improve the breakdown voltage characteristics of a vertical semiconductor device having an opening and including a channel formed of two-dimensional electron gas in the opening. The vertical semiconductor device includes a GaN-based stacked layer | 08-29-2013 |
20130228857 | METHOD OF FORMING AN ASSYMETRIC POLY GATE FOR OPTIMUM TERMINATION DESIGN IN TRENCH POWER MOSFETS - A semiconductor device having a plurality of transistors includes a termination area that features a transistor with an asymmetric gate. | 09-05-2013 |
20130228858 | POWER MOSFET SEMICONDUCTOR - A semiconductor device includes a source metallization, a source region of a first conductivity type in contact with the source metallization, a body region of a second conductivity type which is adjacent to the source region. The semiconductor device further includes a first field-effect structure including a first insulated gate electrode and a second field-effect structure including a second insulated gate electrode which is electrically connected to the source metallization. The capacitance per unit area between the second insulated gate electrode and the body region is larger than the capacitance per unit area between the first insulated gate electrode and the body region. | 09-05-2013 |
20130234241 | SHIELDED GATE MOSFET DEVICE WITH A FUNNEL-SHAPED TRENCH - A MOSFET device has a funnel-shaped trench etched in a semiconductor substrate. The funnel-shaped trench has flared rim extending from a wider cross section trench mouth at the surface of the semiconductor substrate to a narrower cross section trench body portion which terminates in an epilayer portion of the semiconductor substrate. A gate electrode is disposed in the trench on the flared rim. Source and gate regions of the device abut upper and lower portions of the flared rim, respectively. A drain region of the device, which abuts the narrower cross section trench body portion, is self-aligned with a lower edge of a gate electrode. | 09-12-2013 |
20130234242 | SEMICONDUCTOR DEVICE WITH BURIED BIT LINE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes trenches defined in a substrate, buried bit lines partially filling the trenches, a first source/drain layer filling remaining portions of the trenches on the buried bit lines, stack patterns having a channel layer and a second source/drain layer stacked therein and bonded to the first source/drain layer, wherein the channel layer contacts with the first source/drain layer, and word lines crossing with the buried bit lines and disposed adjacent to sidewalls of the channel layer. | 09-12-2013 |
20130240984 | TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - A manufacture includes a doped layer, a body structure over the doped layer, a trench defined in the doped layer, an insulator partially filling the trench, and a first conductive feature buried in, and separated from the doped layer and the body structure by, the insulator. The doped layer has a first type doping. The body structure has an upper surface and includes a body region. The body region has a second type doping different from the first type doping. The trench has a bottom surface. The first conductive feature extends from a position substantially leveled with the upper surface of the body structure toward the bottom surface of the trench. The first conductive feature overlaps the doped layer for an overlapping distance, and the overlapping distance ranging from 0 to 2 μm. | 09-19-2013 |
20130240985 | Semiconductor Device Including Auxiliary Structure and Methods for Manufacturing A Semiconductor Device - A semiconductor device includes a trench region extending into a drift zone of a semiconductor body from a surface. The semiconductor device further includes a dielectric structure including a first step and a second step along a lateral side of the trench region. The semiconductor device further includes an auxiliary structure of a first conductivity type between the first step and the second step, a gate electrode in the trench region and a body region of a second conductivity type other than the first conductivity type of the drift zone. The auxiliary structure adjoins each one of the drift zone, the body region and the dielectric structure. | 09-19-2013 |
20130240986 | Semiconductor Device Including Charged Structure and Methods for Manufacturing A Semiconductor Device - A semiconductor device includes a trench region extending into a drift zone of a semiconductor body from a surface. The semiconductor device further includes a dielectric structure extending along a lateral side of the trench region, wherein a part of the dielectric structure is a charged insulating structure. The semiconductor device further includes a gate electrode in the trench region and a body region of a conductivity type other than the conductivity type of the drift zone. The charged insulating structure adjoins each one of the drift zone, the body region and the dielectric structure and further adjoins or is arranged below a bottom side of a gate dielectric of the dielectric structure. | 09-19-2013 |
20130248985 | METHODS OF FORMING REPLACEMENT GATE STRUCTURES WITH A RECESSED CHANNEL - Disclosed herein are various methods of forming replacement gate structures with a recessed channel region. In one example, the method includes forming a sacrificial gate structure above a semiconducting substrate, removing the sacrificial gate structure to thereby define an initial gate opening having sidewalls and to expose a surface of the substrate and performing an etching process on the exposed surface of the substrate to define a recessed channel in the substrate. The method includes the additional steps of forming a sidewall spacer within the initial gate opening on the sidewalls of the initial gate opening to thereby define a final gate opening and forming a replacement gate structure in the final gate opening. | 09-26-2013 |
20130248986 | POWER MOSFET - A power MOSFET includes an epitaxy substrate, conductive trenches, well regions and a dielectric layer. The power MOSFET further has at least one termination structure including at lest one of the conductive trenches, some of the well regions within a termination area and mutually insulated by the conductive trench, a field plate, a contact plug and a heavily-doped region. The field plate including a plate metal and the dielectric layer is on the well regions and the conductive trench within the termination area. The contact plug penetrates through the dielectric layer and connects the plate metal and one of the well regions, so the plate metal has equal potential with the connected well region through the contact plug. The well regions and the conductive trench are electrically coupled to the plate metal by the dielectric layer. The heavily-doped region is between the contact plug and the connected well region. | 09-26-2013 |
20130248987 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type which is provided on the first semiconductor layer, a third semiconductor layer of the first conductivity type which is selectively provided on a surface of the second semiconductor layer, an insulating film which is provided to cover an inner wall of a trench running into the first semiconductor layer from an upper face of the third semiconductor layer, a field plate electrode which is provided in a lower portion of the trench, a gate electrode which is provided on the field plate electrode via the insulating film, and a fourth semiconductor layer of the second conductivity type which is provided at least in a region direct below the trench, and comes into contact with the insulating film. | 09-26-2013 |
20130248988 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate and a plurality of gate electrodes including a part extended in a first direction in a plane parallel with the semiconductor substrate. The semiconductor substrate has a second semiconductor layer including a plurality of first conductive type pillars and second conductive type second pillars that are disposed on the first semiconductor layer, extending in the first direction in the plane parallel with the semiconductor substrate and in a third direction intersecting with a second direction orthogonal to the first direction, and arranged adjacent to each other in an alternate manner. | 09-26-2013 |
20130248989 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method for manufacturing the same are disclosed, which include a gate electrode material in a recess or a buried gate cell structure, a polysilicon material doped with impurities over a sidewall of a recess located over the gate electrode material, and a junction formed by an annealing or a rapid thermal annealing (RTA) process, thereby establishing a degree overlap between a gate electrode material of a buried gate and a junction. | 09-26-2013 |
20130248990 | SEMICONDUCTOR DEVICES AND METHOD FOR FABRICATING THE SAME - Semiconductor devices, and a method for fabricating the same, include an interlayer dielectric film pattern over a substrate, a first wiring within the interlayer dielectric film pattern and having a first length in a first direction, a second wiring within the interlayer dielectric film pattern and separated from the first wiring, and a spacer contacting the first wiring and the second wiring. The spacer electrically separates the first wiring and the second wiring from each other. The second wiring has a second length different from the first length in the first direction. | 09-26-2013 |
20130248991 | STRUCTURE AND METHOD FOR FORMING TRENCH-GATE FIELD EFFECT TRANSISTOR - A field effect transistor (FET) includes a body region of a first conductivity type disposed within a semiconductor region of a second conductivity type and a gate trench extending through the body region and terminating within the semiconductor region. The FET also includes a flared shield dielectric layer disposed in a lower portion of the gate trench, the flared shield dielectric layer including a flared portion that extends under the body region. The FET further includes a conductive shield electrode disposed in the trench and disposed, at least partially, within the flared shield dielectric. | 09-26-2013 |
20130256786 | TRENCH MOSFET WITH SHIELDED ELECTRODE AND AVALANCHE ENHANCEMENT REGION - A trench MOSFET with shielded electrode and improved avalanche enhancement region is disclosed. The inventive structure can achieve a better avalanche capability by applying an improved avalanche enhancement region having a same doping concentration as the epitaxial layer where said trench MOSFET is formed without increasing Rds. | 10-03-2013 |
20130256787 | MULTI-LANDING CONTACT ETCHING - A method for contacting MOS devices. First openings in a photosensitive material are formed over a substrate having a top dielectric in a first die area and a second opening over a gate stack in a second die area having the top dielectric, a hard mask, and a gate electrode. The top dielectric layer is etched to form a semiconductor contact while etching at least a portion the hard mask layer thickness over a gate contact area exposed by the second opening. An inter-layer dielectric (ILD) is deposited. A photosensitive material is patterned to generate a third opening in the photosensitive material over the semiconductor contact and a fourth opening inside the gate contact area. The ILD is etched through to reopen the semiconductor contact while etching through the ILD and residual hard mask if present to provide a gate contact to the gate electrode. | 10-03-2013 |
20130256788 | SEMICONDUCTOR DEVICE - A semiconductor device comprises an isolation region formed by filling a trench with an insulator, an active region surrounded with the sidewall of the trench, a combined pillar including a semiconductor pillar in the active region and an insulator pillar in the isolation region, a gate electrode covering a side surface surrounding the combined pillar; and a transistor including the combined pillar and the gate electrode. The trench has a sidewall in a semiconductor substrate. The insulator pillar contacts the semiconductor pillar with the sidewall of the trench interposed therebetween. | 10-03-2013 |
20130264636 | Trench FET with Ruggedness Enhancement Regions - According to an exemplary implementation, a field-effect transistor (FET) includes first and second gate trenches extending to a drift region of a first conductivity type. The FET also includes a base region of a second conductivity type that is situated between the first and second gate trenches. A ruggedness enhancement region is situated between the first and second gate trenches, where the ruggedness enhancement region is configured to provide an enhanced avalanche current path from a drain region to the base region when the FET is in an avalanche condition. The enhanced avalanche current path is away from the first and second gate trenches. The ruggedness enhancement region can be of the second conductivity type that includes a higher dopant concentration than the base region. Furthermore, the ruggedness enhancement region can be extending below the first and second gate trenches. | 10-10-2013 |
20130270630 | METHOD FOR MANUFACTURING A POWER DEVICE BEING INTEGRATED ON A SEMICONDUCTOR SUBSTRATE, IN PARTICULAR HAVING A FIELD PLATE VERTICAL STRUCTURE AND CORRESPONDING DEVICE - An embodiment of a method for manufacturing a power device integrated on a semiconductor substrate comprising the steps of: growth on said substrate of an epitaxial layer; photo-lithography and etching of said epitaxial layer for the formation of at least one deep trench; deposition of a dielectric layer with partial filling of the at least one trench; complete filling of the at least one trench with a layer of sacrificial material; selective etching of the dielectric layer with consequent retrocession below the layer of sacrificial material; selective etching of the layer of sacrificial material with consequent formation of an empty region within the at least one trench; growth of a layer of gate oxide; formation of at least one gate region, of at least one buried source region, of at least one body region and of at least one source region; deposition of a dielectric layer; simultaneous formation of at least one gate contact, at least one body/source contact and at least one buried source contact; formation of a source contact region and of a gate contact region through deposition, masking and etching of a metallisation layer. An embodiment of the method also comprises the step of formation of the at least one gate region and of the at least one buried source region, electrically insulated, through a single deposition of a conductive filling material on the epitaxial layer, on the vertical walls of the trench and within the empty region; and through etching of the conductive filling material forming a first spacer and a second spacer, suitable for serving as a gate electrode and forming a buried source electrode within the empty region. | 10-17-2013 |
20130277734 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor device includes a first semiconductor region; a second semiconductor region having a side face and a lower face, and the faces surrounded by the first semiconductor region; a third semiconductor region provided between the second semiconductor region and the first semiconductor region; a fourth semiconductor region being in contact with an outer side face of the first semiconductor region; a plurality of first electrodes being in contact with the second semiconductor region, the third semiconductor region, and the first semiconductor region via an insulating film; a plurality of pillar areas extending from the third semiconductor region toward the fourth semiconductor region, each of the plurality of pillar areas being provided between adjacent ones of the plurality of first electrodes. An impurity density of each of the pillar areas and an impurity density of the third semiconductor region is substantially the same. | 10-24-2013 |
20130277735 | WAFER LEVEL MOSFET METALLIZATION - Systems and methods of fabricating Wafer Level Chip Scale Packaging (WLCSP) devices with transistors having source, drain and gate contacts on one side of the transistor while still having excellent electrical performance with low drain-to-source resistance R | 10-24-2013 |
20130277736 | SELF-ALIGNED CONTACT FOR TRENCH MOSFET - A trench metal oxide semiconductor field effect transistor (MOSFET) includes an epitaxial layer over a substrate a first trench in the epitaxial layer and a second trench in the epitaxial layer. A depth of the first trench is different from a depth of the second trench. The trench MOSFET further includes a source region surrounding the self-aligned source contact, wherein the source region is convex-shaped. The trench MOSFET further includes a self-aligned source contact between the first trench and the second trench; wherein the self-aligned source contact is connected to the source region. | 10-24-2013 |
20130285138 | Method of Fabricating Tunnel Transistors With Abrupt Junctions - A method of manufacturing a tunnel field effect transistor (TFET) includes forming on a substrate covered by an epitaxially grown source material a dummy gate stack surrounded by sidewall spacers; forming doped source and drain regions followed by forming an inter-layer dielectric surrounding the sidewall spacers; removing the dummy gate stack, etching a self-aligned cavity; epitaxially growing a thin channel region within the self-aligned etch cavity; conformally depositing gate dielectric and metal gate materials within the self-aligned etch cavity; and planarizing the top surface of the replacement metal gate stack to remove the residues of the gate dielectric and metal gate materials. | 10-31-2013 |
20130285139 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method for manufacturing the same are disclosed. A recess gate structure is formed between an overlapping region between a gate and a source/drain so as to suppress increase in gate induced drain leakage (GIDL), and a gate insulation film is more thickly deposited in a region having weak GIDL, thereby reducing GIDL and thus improving refresh characteristics due to leakage current. | 10-31-2013 |
20130285140 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - A trench-gate type semiconductor device that can prevent breakdown of a gate insulating film caused by a displacement current flowing into a protective diffusion layer at a portion of a trench underlying a gate electrode at a turn-off time and simultaneously improves a current density by narrowing a cell pitch. The semiconductor device includes a gate electrode embedded into a trench penetrating a base region. The gate electrode is disposed into a lattice shape in a planar view, and a protective diffusion layer is formed in a drift layer at the portion underlying thereof. At least one of blocks divided by the gate electrode is a protective contact region on which the trench is entirely formed. A protective contact for connecting the protective diffusion layer at a bottom portion of the trench and a source electrode is disposed on the protective contact region. | 10-31-2013 |
20130292759 | TRENCH TRANSISTOR - A method of forming a device is disclosed. A substrate defined with a device region is provided. A buried doped region is formed in the substrate in the device region. A gate is formed in a trench in the substrate in the device region. A channel of the device is disposed on a sidewall of the trench. The buried doped region is disposed below the gate. A distance from the buried doped region to the channel is a drift length LD of the device. A surface doped region is formed adjacent to the gate. | 11-07-2013 |
20130299897 | INVERTED THIN CHANNEL MOSFET WITH SELF-ALIGNED EXPANDED SOURCE/DRAIN - After formation of a gate electrode, a source trench and a drain trench are formed down to an upper portion of a bottom semiconductor layer having a first semiconductor material of a semiconductor-on-insulator (SOI) substrate. The source trench and the drain trench are filled with at least with a second semiconductor material that is different from the first semiconductor material to form source and drain regions. A planarized dielectric layer is formed and a handle substrate is attached over the source and drain regions. The bottom semiconductor layer is thinned, and remaining portions of the bottom semiconductor layer are removed selective to the second semiconductor material, the buried insulator layer, and a shallow trench isolation structure. A contact level dielectric layer is deposited on surfaces of the source and drain regions that are distal from the gate electrode, and contact vias are formed through the contact level dielectric layer. | 11-14-2013 |
20130299898 | POWER MOSFET STRUCTURE AND METHOD - A power MOSFET includes a semiconductor substrate with an upper surface, a cavity of a first depth in the substrate whose sidewall extends to the upper surface, a dielectric liner in the cavity, a gate conductor within the dielectric liner extending to or above the upper surface, body region(s) within the substrate of a second depth, separated from the gate conductor in a lower cavity region by first portion(s) of the dielectric liner of a first thickness, and source region(s) within the body region(s) extending to a third depth that is less than the second depth. The source region(s) are separated from the gate conductor by a second portion of the dielectric liner of a second thickness at least in part greater than the first thickness. The dielectric liner has a protrusion extending laterally into the gate conductor away from the body region(s) at or less than the third depth. | 11-14-2013 |
20130299899 | Power Semiconductor Devices and Methods - The present inventors have realized that manufacturability plays into optimization of power semiconductor devices in some surprising new ways. If the process window is too narrow, the maximum breakdown voltage will not be achieved due to doping variations and the like normally seen in device fabrication. Thus, among other teachings, the present application describes some ways to improve the process margin, for a given breakdown voltage specification, by actually reducing the maximum breakdown voltage. In one class of embodiments, this is done by introducing a vertical gradation in the density of fixed electrostatic charge, or in the background doping of the drift region, or both. Several techniques are disclosed for achieving this. | 11-14-2013 |
20130299900 | SUPERJUNCTION DEVICES HAVING NARROW SURFACE LAYOUT OF TERMINAL STRUCTURES, BURIED CONTACT REGIONS AND TRENCH GATES, AND METHODS OF MANUFACTURING THE DEVICES - Superjunction semiconductor devices having narrow surface layout of terminal structures and methods of manufacturing the devices are provided. The narrow surface layout of terminal structures is achieved, in part, by connecting a source electrode to a body contact region within a semiconductor substrate at a body contact interface comprising at least a first side of the body contact region other than a portion of a first main surface of the semiconductor substrate. | 11-14-2013 |
20130299901 | TRENCH MOSFET STRUCTURES USING THREE MASKS PROCESS - A trench MOSFET comprising a plurality of trenched gates surrounded by source regions encompassed in body regions in active area. A plurality of trenched source-body contact structure penetrating through the source regions and extending into the body regions, are filled with tungsten plugs padded with a Ti layer, a first and a second TiN layer, wherein the second TiN layer is deposited after Ti silicide formation to avoid W spiking occurrence. | 11-14-2013 |
20130307058 | Semiconductor Devices Including Superjunction Structure and Method of Manufacturing - A semiconductor device includes a semiconductor body having a first surface and a second surface opposite to the first surface. A superjunction structure in the semiconductor body includes drift regions of a first conductivity type and compensation structures alternately disposed in a first direction parallel to the first surface. Each of the charge compensation structures includes a first semiconductor region of a second conductivity type complementary to the first conductivity type and a first trench including a second semiconductor region of the second conductivity type adjoining the first semiconductor region. The first semiconductor region and the first trench are disposed one after another in a second direction perpendicular to the first surface. | 11-21-2013 |
20130307059 | Semiconductor Device and Method for Manufacturing a Semiconductor Device - A semiconductor device includes a first region of a first conductivity type and a body region of a second conductivity type, the first conductivity type being different from the second conductivity type. The body region is disposed on a side of a first surface of the semiconductor substrate. The semiconductor device further includes a plurality of trenches arranged in the first surface of the substrate, the trenches extending in a first direction having a component perpendicular to the first surface. Doped portions of the second conductivity type are adjacent to a lower portion of a sidewall of the trenches. The doped portions are electrically coupled to the body region via contact regions. The semiconductor device further includes a gate electrode disposed in an upper portion of the trenches. | 11-21-2013 |
20130307060 | TRENCH SEMICONDUCTOR DEVICES WITH EDGE TERMINATION STRUCTURES, AND METHODS OF MANUFACTURE THEREOF - Embodiments of semiconductor devices and methods of their formation include providing a semiconductor substrate having a top surface, a bottom surface, an active region, and an edge region, and forming a gate structure in a first trench in the active region of the semiconductor substrate. A termination structure is formed in a second trench in the edge region of the semiconductor substrate. The termination structure has an active region facing side and a device perimeter facing side. The method further includes forming first and second source regions of the first conductivity type are formed in the semiconductor substrate adjacent both sides of the gate structure. A third source region is formed in the semiconductor substrate adjacent the active region facing side of the termination structure. The semiconductor device may be a trench metal oxide semiconductor device, for example. | 11-21-2013 |
20130307061 | SEMICONDUCTOR DEVICE - The substrate is made of a compound semiconductor, and has a recess, which opens at one main surface and has side wall surfaces when viewed in a cross section along a thickness direction. The gate insulating film is disposed on and in contact with each of the side wall surfaces. The substrate includes a source region having first conductivity type and disposed to be exposed at the side wall surface; and a body region having second conductivity type and disposed in contact with the source region at a side opposite to the one main surface so as to be exposed at the side wall surface, when viewed from the source region. The recess has a closed shape when viewed in a plan view. The side wall surfaces provide an outwardly projecting shape in every direction when viewed from an arbitrary location in the recess. | 11-21-2013 |
20130307062 | Vertical Transistor Component - A vertical transistor component includes a semiconductor body with first and second surfaces, a drift region, and a source region and body region arranged between the drift region and the first surface. The body region is also arranged between the source region and the drift region. The vertical transistor component further includes a gate electrode arranged adjacent to the body zone, a gate dielectric arranged between the gate electrode and the body region, and a drain region arranged between the drift region and the second surface. A source electrode electrically contacts the source region, is electrically insulated from the gate electrode and arranged on the first surface. A drain electrode electrically contacts the drain region and is arranged on the second surface. A gate contact electrode is electrically insulated from the semiconductor body, extends in the semiconductor body to the second surface, and is electrically connected with the gate electrode. | 11-21-2013 |
20130307063 | MANUFACTURING METHOD OF GaN-BASED SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - Provided is a method of manufacturing a gallium-nitride-based semiconductor device, comprising forming a first semiconductor layer of a gallium-nitride-based semiconductor; and forming a recessed portion by dry etching a portion of the first semiconductor layer via a microwave plasma process using a bromine-based gas. | 11-21-2013 |
20130307064 | POWER TRANSISTOR DEVICE AND FABRICATING METHOD THEREOF - The present invention provides a power transistor device including a substrate, a first epitaxial layer, a doped diffusion region, a second epitaxial layer, a doped base region, and a doped source region. The substrate, the first epitaxial layer, the second epitaxial layer and the doped source region have a first conductive type, and the doped diffusion region and the doped base region have a second conductive type. The first epitaxial layer and the second epitaxial layer are sequentially disposed on the substrate, and the doped diffusion region is disposed in the first epitaxial layer. The doped base region is disposed in the second epitaxial layer and contacts the doped diffusion region, and the doped source region is disposed in the doped base region. A doping concentration of the second epitaxial layer is less than a doping concentration of the first epitaxial layer. | 11-21-2013 |
20130313633 | Semiconductor Device and Method of Forming Junction Enhanced Trench Power Mosfet having Gate Structure Embedded within Trench - A semiconductor device has a substrate and trench formed partially through the substrate. A drain region is formed in the substrate as a second surface of the substrate. An epitaxial region is formed in the substrate over the drain region. A vertical drift region is formed along a sidewall of the trench. An insulating material is deposited within the trench. A channel region is formed along the sidewall of the trench above the insulating material. The channel region is separated from the insulating material. A gate structure is formed within the trench adjacent to the channel region. The gate structure includes an insulating layer formed along the sidewall of the trench adjacent to the channel region and polysilicon layer formed within the trench over the insulating layer. A source region is formed in a first surface of the substrate contacting the channel region. | 11-28-2013 |
20130313634 | POWER SEMICONDUCTOR DEVICE AND EDGE TERMINAL STRUCTURE THEREOF - An edge terminal structure of a power semiconductor device is provided that includes a substrate, a first and a second electrodes disposed on a surface and a back of the substrate respectively, a first field plate, and a second field plate. The power semiconductor device includes an active area and an edge termination area, and there is a trench in a surface of the substrate in the edge terminal area beside the active area. The first field plate is disposed on a sidewall of the trench and extends on a tail of the trench, and it includes at least a L-shaped electric-plate, a gate insulation layer under the L-shaped electric-plate, and the first electrode on the L-shaped electric-plate. The second field plate includes at least an insulation layer and the first electrode thereon. The insulation layer covers the tail of the trench and a tail of the L-shaped electric-plate further. | 11-28-2013 |
20130313635 | SEMICONDUCTOR DEVICE - A semiconductor device of the present invention is a semiconductor device having a semiconductor layer comprising a wide band gap semiconductor, wherein the semiconductor layer includes: a first conductivity-type source region, a second conductivity-type channel region and a first conductivity-type drain region, which are formed in this order from the surface side of the semiconductor layer; a source trench lying from the surface of the semiconductor layer through the source region and the channel region to the drain region; a gate insulating film formed so as to contact the channel region; a gate electrode facing the channel region with the gate insulating film interposed therebetween; and a first breakdown voltage holding region of a second conductivity type formed selectively on the side face or the bottom face of the source trench, and the semiconductor device includes a barrier formation layer, which is joined with the drain region in the source trench, for forming, by junction with the drain region, a junction barrier lower than a diffusion potential of a body diode formed by p-n junction between the channel region and the drain region. | 11-28-2013 |
20130320435 | Trench Power MOSFET - A device includes a semiconductor region of a first conductivity type, a trench extending into the semiconductor region, and a conductive field plate in the trench. A first dielectric layer separates a bottom and sidewalls of the field plate from the semiconductor region. A main gate is disposed in the trench and overlapping the field plate. A second dielectric layer is disposed between and separating the main gate and the field plate from each other. A Doped Drain (DD) region of the first conductivity type is under the second dielectric layer, wherein an edge portion of the main gate overlaps the DD region. A body region includes a first portion at a same level as a portion of the main gate, and a second portion at a same level as, and contacting, the DD region, wherein the body region is of a second conductivity type opposite the first conductivity type. | 12-05-2013 |
20130320436 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a substrate including an active region, an insulation layer formed over the substrate, a plurality of openings formed in the insulation layer, a plurality of contact plugs filling the plurality of openings, a silicide layer formed over the substrate and between the substrate and each contact plug of the contact plugs in order to cover a bottom of each contact plug. The semiconductor device may decrease contact resistance by forming a silicide layer before the formation of openings regardless of the linewidth and aspect ratio of the openings. Also, because it does not have to consider step coverage based on the aspect ratio of openings, there is no limitation in the method of depositing a metal layer. Therefore, productivity may be improved. | 12-05-2013 |
20130320437 | Power MOSFET and Methods for Forming the Same - A device includes a trench extending into a semiconductor region and having a first conductivity type, and a conductive field plate in the trench. A first dielectric layer separates a bottom and sidewalls of the field plate from the semiconductor region. A main gate is disposed in the trench and overlapping the field plate. A second dielectric layer is disposed between and separating the main gate and the field plate from each other. A Doped Drain (DD) region of the first conductivity type is under the second dielectric layer and having an edge portion overlapping the DD region. A body region includes a first portion at a same level as a portion of the main gate, and a second portion contacting the DD region, wherein the body region is of a second conductivity type opposite the first conductivity type. A MOS-containing device is at a surface of the semiconductor region. | 12-05-2013 |
20130320438 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device comprises a gate electrode buried in a trench within a semiconductor substrate, a first sealing insulating film disposed over the gate electrode and the semiconductor substrate, an ion-implanting region disposed in portions of the semiconductor substrate adjacent to sidewalls of the trench, and a second sealing insulating film formed over the first sealing insulating film to bury the trench. | 12-05-2013 |
20130320439 | DEVICE - A semiconductor device has a first and second transistors formed on an active region defined by an insulating region. The active region is divided into a first and second portions arranged in a first direction, and into a third and fourth portions interposed between the first portion and the second portion, and provided adjacent to each other in a second direction orthogonal to the first direction. The first transistor is provided in the first and third portions, and the second transistor is provided in the second and fourth portions. | 12-05-2013 |
20130320440 | Floating Body Transistor Constructions, Semiconductor Constructions, And Methods Of Forming Semiconductor Constructions - The invention includes floating body transistor constructions containing U-shaped semiconductor material slices. The U-shapes have a pair of prongs joined to a central portion. Each of the prongs contains a source/drain region of a pair of gatedly-coupled source/drain regions, and the floating bodies of the transistors are within the central portions. The semiconductor material slices can be between front gates and back gates. The floating body transistor constructions can be incorporated into memory arrays, which in turn can be incorporated into electronic systems. The invention also includes methods of forming floating body transistor constructions, and methods of incorporating floating body transistor constructions into memory arrays. | 12-05-2013 |
20130328121 | MOSFET WITH IMPROVED PERFORMANCE THROUGH INDUCED NET CHARGE REGION IN THICK BOTTOM INSULATOR - A semiconductor power device includes a thick bottom insulator formed in a lower portion of a trench in a semiconductor epitaxial region. An electrically conductive gate electrode is formed in the trench above the bottom insulator. The gate electrode is electrically insulated from the epitaxial region by the bottom insulator and a gate insulator. Charge is deliberately induced in the thick bottom insulator proximate an interface between the bottom insulator and the epitaxial semiconductor region. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. | 12-12-2013 |
20130334595 | STRUCTURE AND METHOD FOR A FIELD EFFECT TRANSISTOR - Provided is one embodiment of a semiconductor structure that includes a STI feature, wherein the STI feature is a continuous feature and includes a first portion in a first region and a second portion in a second region, and the first portion is recessed relative to the second portion; an active region bordered by the STI feature; a gate stack disposed on the active region and extended in a first direction to the first region of the STI feature; source and drain features formed in the active region and interposed by the gate stack; and a channel formed in the active region and spanned between the source and drain features in a second direction being different from the first direction. The channel includes top portion having a width W in the first direction and two side portions each having a height H less than the width W. | 12-19-2013 |
20130341708 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - A low concentration P-type impurity (LCPI) layer situated over a drain layer has an impurity concentration lower than the drain layer. An N-type impurity base layer is situated over the LCPI layer. A gate insulating film is formed on the lateral side of a trench. A bottom insulation film formed to the bottom and lower portion on the lateral side of the trench has a larger thickness than the gate insulating film. A gate electrode is filled in the trench. At a cross section in the direction of the thickness including the bottom of the trench, a profile of the P-type impurity concentration is substantially constant and the difference between the maximum and minimum values is 10% or less of the average value for the maximum and minimum values. Further, the profile has a maximal value and a minimal value situated from the maximal value to the drain layer. | 12-26-2013 |
20130341709 | SEMICONDUCTOR DEVICE WITH ELECTRODE INCLUDING INTERVENTION FILM - In a semiconductor device including a semiconductor substrate, a trench formed on the semiconductor substrate, an insulating film formed on a side wall of the trench, and an electrode formed on the insulating film. The electrode includes a first film made of first metal nitride, an intervention film made of silicon or of second metal silicide, and a second film made of third metal in this order. | 12-26-2013 |
20130341710 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device includes forming a first preliminary gate barrier layer and a first preliminary gate electrode recessed to have a first depth from the surface of the substrate within a gate trench, removing an upper portion of the first preliminary gate electrode by means of a first wet etching process using a first etchant to form a second preliminary gate electrode recessed to have a second depth greater than the first depth, and removing an upper portion of the first preliminary gate barrier layer and an upper portion of the second preliminary gate electrode by means of a second wet etching process using a second etchant to form a gate electrode and a gate barrier layer recessed to a third depth greater than the second depth. | 12-26-2013 |
20130341711 | SEMICONDUCTOR DEVICE - A technique for improving the characteristics of a semiconductor device (UMOSFET) is provided. In the UMOSFET in order to grow an epitaxial growth film on a trench side wall with an even film thickness, a channel is arranged in an optimum direction as a growth surface. For example, a trench is formed on an SiC substrate having a {0001} surface 4° off in a <11-20> direction as a main surface so that a channel surface becomes a {1-100} surface. With this configuration, an epitaxial growth with the even thickness can be conducted on the side wall from which the {1-100} surface of the trench is exposed. As a result, the unevenness of a channel resistance, and the insulation failure of a gate insulating film do not occur, and the yield is improved. | 12-26-2013 |
20140001541 | TRANSISTOR WITH RECESS GATE AND METHOD FOR FABRICATING THE SAME | 01-02-2014 |
20140001542 | PASSIVATION OF CARBON NANOTUBES WITH MOLECULAR LAYERS | 01-02-2014 |
20140001543 | Integrated circuit device with metal gates including diffusion barrier layers and fabricating methods thereof | 01-02-2014 |
20140001544 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE | 01-02-2014 |
20140008718 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a vertical trench gate element portion and a lateral n-channel element portion for control which includes a well diffusion region, and a junction edge termination region which surrounds the vertical trench gate element portion and the lateral n-channel element portion for control. The junction edge termination region includes an oxide layer, a sustain region in contact with a trench provided at the end, and a diffusion region in contact with the sustain region. The diffusion region is deeper than the base region and has low concentration. The sustain region is shallower than the diffusion region and has high concentration. The well diffusion region is deeper than the base region and the sustain region and has low concentration. The breakdown voltage of the junction edge termination region and the well diffusion region is higher than that of the vertical trench gate element portion. | 01-09-2014 |
20140008719 | SEMICONDUCTOR DEVICE AND A BIT LINE AND THE WHOLE OF A BIT LINE CONTACT PLUG HAVING A VERTICALLY UNIFORM PROFILE - A semiconductor device comprises: a semiconductor substrate including a cell region and a peripheral region; an insulating film formed on the top portion of the semiconductor substrate of the cell region; a bit line contact hole including the etched insulating film to expose the semiconductor substrate; a bit line contact plug buried in the bit line contact plug; and a bit line formed on the top portion of the bit line contact plug to have the same width as that of the bit line contact plug. The thickness of the insulating film around a cell bit line is minimized so as to vertically form a profile of the cell bit line, thereby improving an overlay margin of a storage node contact and an active region. | 01-09-2014 |
20140015037 | Novel Metal/Polysilicon Gate Trench Power Mosfet - The present disclosure relates to a power MOSFET device having a relatively low resistance hybrid gate electrode that enables good switching performance. In some embodiments, the power MOSFET device has a semiconductor body. An epitaxial layer is disposed on the semiconductor body. A hybrid gate electrode, which controls the flow of electrons between a source electrode and a drain electrode, is located within a trench extending into the epitaxial layer. The hybrid gate electrode has an inner region having a low resistance metal, an outer region having a polysilicon material, and a barrier region disposed between the inner region and the outer region. The low resistance of the inner region provides for a low resistance to the hybrid gate electrode that enables good switching performance for the power MOSFET device. | 01-16-2014 |
20140015038 | Apparatus and Method for Power MOS Transistor - A MOS transistor comprises a substrate, a first region formed over the substrate, a second region grown from the first region, a third region of formed in the second region, a first drain/source region formed in the third region, a first gate electrode formed in a first trench, a second drain/source region formed in the second region and on an opposite side of the first trench from the first drain/source region and a second trench coupled between the second drain/source region and the second region, wherein the second trench is of a same depth as the first trench. | 01-16-2014 |
20140015039 | METHOD OF MAKING AN INSULATED GATE SEMICONDUCTOR DEVICE HAVING A SHIELD ELECTRODE STRUCTURE AND STRUCTURE THEREFOR - In one embodiment, a semiconductor device includes a multi-portion shield electrode structure formed in a drift region. The shield electrode includes a wide portion formed in proximity to a channel side of the drift region, and a narrow portion formed deeper in the drift region. The narrow portion is separated from the drift region by a thicker dielectric region, and the wide portion is separated from the drift region by a thinner dielectric region. That portion of the drift region in proximity to the wide portion can have a higher dopant concentration than other portions of the drift region. | 01-16-2014 |
20140015040 | POWER SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A power semiconductor device includes a substrate, a semiconductor layer grown on the substrate, a plurality of alternately arranged first conductivity type doping trenches and second conductivity type doping trenches in the semiconductor substrate, a first diffusion region of the first conductivity type around each of the first conductivity type doping trenches, and a second diffusion region of the second conductivity type around each of the second conductivity type doping trenches, wherein distance between an edge of the first conductivity type doping trench and PN junction between the first and second diffusion regions substantially equals to a distance between an edge of the second conductivity type doping trench and the PN junction. | 01-16-2014 |
20140015041 | TRENCH GATE MOSFET - A trench gate MOSFET is provided. An epitaxial layer is disposed on a substrate. A body layer is disposed in the epitaxial layer. The epitaxial layer has a first trench therein, the body layer has a second trench therein, and the first trench is disposed below the second trench. A first conductive layer is disposed in the first trench. A first insulating layer is disposed between the first conductive layer and the epitaxial layer. A second conductive layer is disposed on a sidewall of the second trench. A second insulating layer is disposed between the second conductive layer and the body layer, and between the second conductive layer and the first conductive layer. A dielectric layer is disposed on the epitaxial layer and fills up the second trench. Two doped regions are disposed in the body layer respectively beside the second trench. | 01-16-2014 |
20140015042 | SEMICONDUCTOR DEVICE AND THE METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a p-type well region | 01-16-2014 |
20140021534 | INTEGRATION OF HIGH VOLTAGE TRENCH TRANSISTOR WITH LOW VOLTAGE CMOS TRANSISTOR - A method of forming a device is disclosed. A substrate defined with a device region is provided. A gate having an upper and a lower portion is formed in a trench in the substrate in the device region. The upper portion forms a gate electrode and the lower portion forms a gate field plate. First and second surface doped regions are formed adjacent to the gate. The gate field plate introduces vertical reduced surface (RESURF) effect in a drift region of the device. | 01-23-2014 |
20140021535 | SEMICONDUCTOR DEVICE HAVING VERTICAL GATES AND FABRICATION THEREOF - A method for forming a semiconductor device with a vertical gate is disclosed, including providing a substrate, forming a recess in the substrate, forming a gate dielectric layer on a sidewall and a bottom of the recess, forming an adhesion layer in the recess and on the gate dielectric layer, wherein the adhesion layer is a metal silicide nitride layer, and forming a gate layer in the recess and on the adhesion layer. | 01-23-2014 |
20140021536 | LATERAL DEVICES CONTAINING PERMANENT CHARGE - A lateral device includes a gate region connected to a drain region by a drift layer. An insulation region adjoins the drift layer between the gate region and the drain region. Permanent charges are embedded in the insulation region, sufficient to cause inversion in the insulation region. | 01-23-2014 |
20140021537 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method for forming the same includes a pillar formed over a semiconductor substrate, a buried bit line formed below the semiconductor substrate, a vertical gate formed over a sidewall of the pillar, an insulation film pattern formed to expose one side of the vertical gate disposed between the pillars, and a word line coupled to the exposed vertical gate. The vertical gate is formed to cover a portion of a sidewall of the pillar with a metal material, a word line overlaps with some parts of the vertical gate, and some parts of the pillar are shifted to be coupled to the vertical gate. | 01-23-2014 |
20140027840 | TERMINATION DESIGN FOR HIGH VOLTAGE DEVICE - The present disclosure describes a termination structure for a high voltage semiconductor transistor device. The termination structure is composed of at least two termination zones and an electrical disconnection between the body layer and the edge of the device. A first zone is configured to spread the electric field within the device. A second zone is configured to smoothly bring the electric field back up to the top surface of the device. The electrical disconnection prevents the device from short circuiting the edge of the device. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. | 01-30-2014 |
20140027841 | HIGH VOLTAGE FIELD BALANCE METAL OXIDE FIELD EFFECT TRANSISTOR (FBM) - A semiconductor power device formed in a semiconductor substrate comprising a highly doped region near a top surface of the semiconductor substrate on top of a lightly doped region supported by a heavily doped region. The semiconductor power device further comprises source trenches opened into the highly doped region filled with conductive trench filling material in electrical contact with the source region near the top surface. The semiconductor power device further comprises buried P-regions disposed below the source trenches and doped with dopants of opposite conductivity from the highly doped region. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. | 01-30-2014 |
20140027842 | POWER SEMICONDUCTOR DEVICE - A problem associated with n-channel power MOSFETs and the like that the following is caused even by relatively slight fluctuation in various process parameters is solved: source-drain breakdown voltage is reduced by breakdown at an end of a p-type body region in proximity to a portion in the vicinity of an annular intermediate region between an active cell region and a chip peripheral portion, arising from electric field concentration in that area. To solve this problem, the following measure is taken in a power semiconductor device having a superjunction structure in the respective drift regions of a first conductivity type of an active cell region, a chip peripheral region, and an intermediate region located therebetween: the width of at least one of column regions of a second conductivity type comprising the superjunction structure in the intermediate region is made larger than the width of the other regions. | 01-30-2014 |
20140027843 | Techniques Providing High-K Dielectric Metal Gate CMOS - A method for manufacturing a semiconductor device includes forming a first dummy gate on a substrate, performing a doping process to the substrate, thereby forming a source and a drain at sides of the first dummy gate, performing a first high temperature annealing to activate the source and drain, forming an inter-layer dielectric (ILD) material on the substrate, removing the first dummy gate to create an ILD trench, forming a first high-k dielectric layer within the ILD trench, forming a first dummy cap portion within the ILD trench over the first high-k dielectric layer, performing a second high-temperature annealing to reduce defects in the first high-k dielectric layer, and thereafter, replacing the first dummy cap portion with a first metal gate electrode. | 01-30-2014 |
20140035030 | SEMICONDUCTOR DEVICE - According to one embodiment, in a semiconductor device, a semiconductor laminated body includes a first semiconductor region of a first conductivity type and a second semiconductor region of the first conductivity type provided on the first semiconductor region and having a higher concentration of impurities than that of the first semiconductor region. A third semiconductor region includes a side surface and a lower end, the side surface and the lower end are surrounded by the semiconductor laminated body. A fourth semiconductor region of a second conductivity type is provided between the semiconductor laminated body and the third semiconductor region. A fifth semiconductor region of the first conductivity type is in contact with an outside surface of the semiconductor laminated body opposite to an inside surface of the semiconductor laminated body, the inside surface is in contact with the fourth semiconductor region. | 02-06-2014 |
20140042527 | HIGH VOLTAGE METAL-OXIDE-SEMICONDUCTOR TRANSISTOR DEVICE - A high voltage metal-oxide-semiconductor transistor device includes a substrate, at least an isolation structure formed in the substrate, a gate formed on the substrate, and a source region and a drain region formed in the substrate at respective sides of the gate. The isolation structure further includes a recess. The gate includes a first gate portion formed on a surface of the substrate and a second gate portion downwardly extending from the first gate portion and formed in the recess. | 02-13-2014 |
20140042528 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device and a method for fabricating the same are provided. The semiconductor device includes a device isolation region, a trench formed in the device isolation region, a void connected to the trench in the device isolation region, a first mask pattern formed along sidewalls of the trench and protruding inwardly with respect to the void, a gate insulating film formed along the sidewall of the void, and a gate electrode filling the trench and at least a portion of the void. | 02-13-2014 |
20140042529 | SEMICONDUCTOR DEVICE AND MANUFACTRUING METHOD OF THE SAME - A semiconductor device is manufactured by using an SOI substrate having an insulating layer on a substrate and a semiconductor layer on the insulating layer. The semiconductor device is provided with a gate electrode formed on the semiconductor layer via a gate insulating film, a sidewall spacer formed on a sidewall of the gate electrode, a semiconductor layer for source/drain that is epitaxially grown on the semiconductor layer, and a sidewall spacer formed on a sidewall of the semiconductor layer. | 02-13-2014 |
20140042530 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes a substrate including a first region and a second region, a trench-gate transistor in the first region, the trench-gate transistor including a first trench in the substrate, a gate filling at least part of the first trench, and a source in the substrate and on each sidewall of the first trench, a first field diffusion junction in the second region, an interlayer insulating film on the substrate, the interlayer insulating film covering the trench-gate transistor and the first field diffusion junction, a first contact in the first region, the first contact passing through the interlayer insulating film and contacting the source, and a second contact in the second region, the second contact passing through the interlayer insulating film and contacting the first field diffusion junction, the first contact and the second contact having an equal height and including a same material. | 02-13-2014 |
20140042531 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a trench in a substrate, a gate filling a part of the trench, a tilted source on a side wall of the trench, the tilted source partially overlapping the gate, an interlayer insulating film on the substrate and filling the trench, and a contact hole penetrating parts of the interlayer insulating film and the substrate and contacting the tilted source, the contact hole having a tilted surface at an angle that is equal to or larger than 80 degrees and smaller than 90 degrees. | 02-13-2014 |
20140042532 | TRENCH-BASED POWER SEMICONDUCTOR DEVICES WITH INCREASED BREAKDOWN VOLTAGE CHARACTERISTICS - Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed. | 02-13-2014 |
20140048869 | TRENCH-BASED POWER SEMICONDUCTOR DEVICES WITH INCREASED BREAKDOWN VOLTAGE CHARACTERISTICS - Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed. | 02-20-2014 |
20140048870 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A semiconductor device includes a trench defined by etching a semiconductor substrate including a device isolation film and an active region, an active region protruded from a side and bottom of the trench, and a gate electrode surrounding the active region simultaneously while being buried in the trench. | 02-20-2014 |
20140048871 | Trench Connection Between a Transistor and a Further Component - A semiconductor component arrangement includes a semiconductor body, a transistor structure, a further component, and at least a first electrode structure. The semiconductor body has a first side and a second side. The transistor structure is integrated in the semiconductor body, and includes a source and a drain. The further component is also integrated in the semiconductor body. The first electrode structure is disposed in at least a first trench, and includes at least one electrode. The first electrode structure electrically connects at least one of the source and the drain to the further component. | 02-20-2014 |
20140054682 | BIDIRECTIONAL FIELD EFFECT TRANSISTOR AND METHOD - In one embodiment, a structure for a semiconductor device has trench shield electrodes formed above and below a gate electrode. The structure can be configured to function as a bidirectional power field effect transistor. | 02-27-2014 |
20140054683 | TRENCH DEVICES HAVING IMPROVED BREAKDOWN VOLTAGES AND METHOD FOR MANUFACTURING SAME - In one embodiment, the present invention includes a semiconductor power device. The semiconductor power device comprises a trenched gate and a trenched field region. The trenched gate is disposed vertically within a trench in a semiconductor substrate. The trenched field, region is disposed vertically within the trench and below the trenched gate. A lower portion of the trenched field region tapers to dispose an electric field. | 02-27-2014 |
20140054684 | Power Semiconductor Devices, Structures, and Related Methods - Power semiconductor devices, and related methods, where majority carrier flow is divided into paralleled flows through two drift regions of opposite conductivity types. | 02-27-2014 |
20140054685 | SEMICONDUCTOR DEVICE WITH IMPROVED LINEAR AND SWITCHING OPERATING MODES - A semiconductor device that includes a semiconductor body, having a front side and a back side opposite to one another in a first direction of extension; a drift region, which extends in the semiconductor body, faces the front side, and has a first type of conductivity and a first value of doping; a body region, which has a second type of conductivity opposite to the first type of conductivity, extends in the drift region, and faces the front side of the semiconductor body; a first control terminal, which extends on the front side of the semiconductor body, at least partially overlapping, in the first direction of extension, the body region; and a second control terminal, which extends to a first depth in the semiconductor body, inside the body region, and is staggered with respect to the first control terminal. | 02-27-2014 |
20140054686 | DEVICES, COMPONENTS AND METHODS COMBINING TRENCH FIELD PLATES WITH IMMOBILE ELECTROSTATIC CHARGE - N-channel power semiconductor devices in which an insulated field plate is coupled to the drift region, and immobile electrostatic charge is also present at the interface between the drift region and the insulation around the field plate. The electrostatic charge permits OFF-state voltage drop to occur near the source region, in addition to the voltage drop which occurs near the drain region (due to the presence of the field plate). | 02-27-2014 |
20140054687 | MOSFET DEVICE WITH REDUCED BREAKDOWN VOLTAGE - A semiconductor device includes a drain region, an epitaxial layer overlaying the drain region, and an active region. The active region includes: a body disposed in the epitaxial layer; a source embedded in the body; a gate trench extending into the epitaxial layer; a gate disposed in the gate trench; a contact trench extending through the source and at least part of the body; a contact electrode disposed in the contact trench; and an implant disposed at least in part along a contact trench wall; and an epitaxial enhancement portion disposed below the contact trench and in contact with the implant. | 02-27-2014 |
20140054688 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device capable of reducing a temperature-dependent variation of a current sense ratio and accurately detecting current In the semiconductor device, at least one of an impurity concentration and a thickness of each semiconductor layer is adjusted such that a value calculated by a following equation is less than a predetermined value: | 02-27-2014 |
20140061779 | SEMICONDUCTOR DEVICE COMPRISING BURIED GATE AND METHOD FOR FABRICATING THE SAME - The present invention provides a semiconductor device including a buried gate and a method for fabricating the same, in which the width of a contact plug may not exceed a predetermined width. The method including forming a plurality of trenches over a substrate using the mask pattern, forming a gate insulating film in each of the plurality of trenches, forming a plurality of gate electrodes filling portions of the plurality of trenches, removing an exposed gate insulating film formed over each of the plurality of gate electrodes in each of the plurality of the trenches, forming a plurality of sealing films filling remaining portions of the plurality of trenches, and forming a plurality of contact plugs over the substrate between the trenches. | 03-06-2014 |
20140061780 | SEMICONDUCTOR DEVICE INCLUDING A GATE DIELECTRIC LAYER - A semiconductor device is fabricated by, inter alia, forming a sacrificial liner on an active portion of a semiconductor substrate, oxidizing the sacrificial liner to transform the sacrificial liner into a gate dielectric layer, and forming a gate on the gate dielectric layer. | 03-06-2014 |
20140070307 | MULTI-LAYER WORK FUNCTION METAL REPLACEMENT GATE - Embodiments relate to a field-effect transistor (FET) replacement gate apparatus. The apparatus includes a channel structure including a base and side walls defining a trench. A high-dielectric constant (high-k) layer is formed on the base and side walls of the trench. The high-k layer has an upper surface conforming to a shape of the trench. A first layer is formed on the high-k layer and conforms to the shape of the trench. The first layer includes an aluminum-free metal nitride. A second layer is formed on the first layer and conforms to the shape of the trench. The second layer includes aluminum and at least one other metal. A third layer is formed on the second layer and conforms to the shape of the trench. The third layer includes aluminum-free metal nitride. | 03-13-2014 |
20140070308 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor layer of a first conductivity type and a semiconductor layer of a second conductivity type formed thereon. The semiconductor layer of the second conductivity type is characterized by a first thickness. The semiconductor device includes a set of trenches having a predetermined depth and extending into the semiconductor layer of the second conductivity type, thereby defining interfacial regions disposed between the semiconductor layer of the second conductivity type and each of the trenches. The trenches comprises a distal portion consisting essentially of a dielectric material disposed therein and a proximal portion comprising the dielectric material and a gate material disposed interior to the dielectric material in the proximal portion of the trench. The semiconductor device further includes a source region coupled to the semiconductor layer of the second conductivity type. | 03-13-2014 |
20140077290 | TRENCH METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR WITH EMBEDDED SCHOTTKY RECTIFIER USING REDUCED MASKS PROCESS - A trench MOSFET with embedded schottky rectifier having at least one anti-punch through implant region using reduced masks process is disclosed for avalanche capability enhancement and cost reduction. The source regions have a higher doping concentration and a greater junction depth along sidewalls of the trenched source-body contacts than along adjacent channel regions near the gate trenches. | 03-20-2014 |
20140077291 | SEMICONDUCTOR DEVICE - A semiconductor device includes a channel layer formed on a substrate, an insulating layer formed in contact with the channel layer, an impurity-doped first semiconductor layer formed on an opposite side of the insulating layer from the channel layer, an impurity-doped second semiconductor layer formed on an opposite side of the first semiconductor layer from the insulating layer, and a gate electrode formed on an opposite side of the second semiconductor layer from the first semiconductor layer. A quotient of an impurity density of the first semiconductor layer divided by a relative permittivity of the first semiconductor layer is greater than a quotient of an impurity density of the second semiconductor layer divided by a relative permittivity of the second semiconductor layer. | 03-20-2014 |
20140077292 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - According to one embodiment, a semiconductor device includes a semiconductor substrate including a drain layer of a first conductivity type and a base layer of a second conductivity type provided on the drain layer, a gate electrode including a first portion formed in the semiconductor substrate, a gate insulating layer provided between the gate electrode and the semiconductor substrate, an upper insulating layer formed on the gate electrode, a source layer of the first conductivity type that is provided on a sidewall of the upper insulating layer and whose width increases towards the base layer, and a source electrode provided on the source layer. | 03-20-2014 |
20140077293 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of the first conductivity type, a third semiconductor region of a second conductivity type, a fourth semiconductor region of the first conductivity type, a fifth semiconductor region of the second conductivity type, a first electrode, a second electrode, and a third electrode. The first electrode is provided together with the first region in a first direction, provided together with the third region in a second direction, and has an end portion of the first region side located nearer to the first semiconductor side than a boundary between the second region and the third region. The second electrode is provided between the first electrode and the first region and is in electrical continuity with the fourth region. The third electrode contacts with the fourth region. | 03-20-2014 |
20140077294 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - Provided are a semiconductor device and a method of fabricating the same. The semiconductor device comprises a first trench formed in a substrate; a first insulating film formed on sidewalls and a bottom surface of the first trench and not formed on a top surface of the substrate; and a first conductive film formed on the first insulating film to partially fill the first trench, wherein the first insulating film comprises a first portion which overlaps the first conductive film and a second portion which does not overlap the first conductive film, wherein the second portion comprises first fixed charges. | 03-20-2014 |
20140084362 | Semiconductor Device and Method for Manufacturing a Semiconductor Device - A semiconductor device includes a transistor including a source region, a drain region, and a gate electrode. The gate electrode is disposed in a first trench arranged in a top surface of the semiconductor substrate. The device further includes a control electrode. The control electrode is disposed in a second trench arranged in the top surface of the semiconductor substrate. The second trench has a second shape that is different from a first shape of the first trench. | 03-27-2014 |
20140084363 | MOS TRANSISTOR STRUCTURE - In one embodiment, an MOS transistor is formed to have an active region and a termination region. Within the termination region a plurality of conductors are formed to make electrical contact to conductors that are within a plurality of trenches. The plurality of conductors in the termination region are formed to be substantially coplanar. | 03-27-2014 |
20140084364 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device according to one embodiment includes a semiconductor substrate, a back-gate layer formed above the semiconductor substrate, and a stacked body formed above the back-gate layer and comprising a plurality of insulating layers alternately formed between a plurality of electrode layers. The lowermost electrode layer of the plurality of electrode layers contains metal, and remaining electrode layers of the plurality of electrode layers other than the lowermost electrode layer do not contain the metal. Furthermore, the semiconductor device includes a pair of columnar semiconductor layers penetrating the stacked body and a semiconductor layer connecting lower portions of the pair of columnar semiconductor layers, the semiconductor layer embedded in the surface of the back-gate layer. | 03-27-2014 |
20140084365 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a drain layer; a drift layer provided on the drain layer; a base region provided on the drift layer; a source region selectively provided on a surface of the base region; a first gate; a field-plate; a second gate; a drain electrode; and a source electrode. The first gate electrode is provided in each of a plurality of first trenches via a first insulating film. The first trenches penetrate from a surface of the source region through the base region and contact the drift layer. The field-plate electrode is provided in the first trench under the first gate electrode via a second insulating film. The second gate electrode is provided in a second trench via a third insulating film. The second trench penetrates from the surface of the source region through the base region and contacts the drift layer between the first trenches. | 03-27-2014 |
20140091386 | MOSFET DEVICE AND FABRICATION - A semiconductor device includes a substrate, an active gate trench in the substrate; a source polysilicon pickup trench in the substrate; a polysilicon electrode disposed in the source polysilicon pickup trench; and a body region in the substrate. The top surface of the polysilicon electrode is below the bottom of the body region. | 04-03-2014 |
20140091387 | SEMICONDUCTOR DEVICE - In a transistor including a trench gate, a gate contact hole for connecting a gate electrode and a gate wiring to each other is provided on a trench. In a transistor in which the trench gate is formed in a grid pattern and a plurality of source regions are surrounded by the trench gate, the gate contact hole is formed at an intersection portion of the trench gate. | 04-03-2014 |
20140091388 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - Provided are a semiconductor device and a method of fabricating the same. The method includes: forming a trench in a semiconductor substrate of a first conductive type; forming a trench dopant containing layer including a dopant of a second conductive type on a sidewall and a bottom surface of the trench; forming a doping region by diffusing the dopant in the trench dopant containing layer into the semiconductor substrate; and removing the trench dopant containing layer. | 04-03-2014 |
20140097488 | Method for Producing a Semiconductor Device and Field-Effect Semiconductor Device - A method for producing a semiconductor device is provided. The method includes providing a wafer including a main surface and a silicon layer arranged at the main surface and having a nitrogen concentration of at least about 3*10 | 04-10-2014 |
20140097489 | SEMICONDUCTOR DEVICE HAVING LOCALIZED CHARGE BALANCE STRUCTURE AND METHOD - In one embodiment, a semiconductor device has a superjunction structure formed adjoining a low-doped n-type region. A low-doped p-type region is formed adjoining the superjunction structure above the low-doped n-type region and is configured to improve Eas characteristics. A body region is formed adjacent the low-doped p-type region and a control electrode structure is formed adjacent the body region for controlling a channel region within the body region. | 04-10-2014 |
20140097490 | SEMICONDUCTOR DEVICE - A semiconductor substrate of a semiconductor device includes a body region of a first conductivity type, a drift region of a second conductivity type coming into contact with a lower surface of the body region, a gate electrode that is provided in a gate trench passing through the body region and extending to the drift region and faces the body region, and a gate insulator that is provided between the gate electrode and a wall surface of the gate trench. An inverted U-shaped section is formed in a lower surface of the gate insulator, and a floating region of the first conductivity type is formed in the inverted U-shaped section. The floating region protrudes under a portion that is located at a lowermost portion in the lower surface of the gate insulator. | 04-10-2014 |
20140103426 | TRENCH METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR WITH MULTIPLE TRENCHED SOURCE-BODY CONTACTS FOR REDUCING GATE CHARGE - A trench MOSFET with multiple trenched source-body contacts is disclosed for reducing gate charge by applying multiple trenched source-body contacts in unit cell. Furthermore, source regions are only formed along channel regions near the gate trenches, not between adjacent trenched source-body contacts for UIS (Unclamped Inductance Switching) current enhancement. | 04-17-2014 |
20140103427 | SEMICONDUCTOR TRANSISTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor device includes a drift layer. The device includes a base layer. The device includes a source layer selectively provided on a surface of the base layer. The device includes a gate electrode provided via a gate insulating film in a trench penetrating the source layer and the base layer to reach the drift layer. The device includes a field plate electrode provided under the gate electrode in the trench. The device includes a drain electrode electrically connected to the drift layer. The device includes a source electrode. The field plate electrode is electrically connected to the source electrode. An impurity concentration of a first conductivity type contained in the base layer is lower than an impurity concentration of the first conductivity type contained in the drift layer. And the impurity concentration of the first conductivity type contained in the drift layer is not less than 1×10 | 04-17-2014 |
20140103428 | TRENCH SUPERJUNCTION MOSFET WITH THIN EPI PROCESS - Methods for fabricating MOSFET devices with superjunction having high breakdown voltages (>600 volts) with competitively low specific resistance include growing an epitaxial layer of a second conductivity type on a substrate of a first conductivity type, forming a trench in the epitaxial layer, and growing a second epitaxial layer along the sidewalls and bottom of the trench. The second epitaxial layer is doped with a dopant of first conductivity type. MOSFET devices with superjunction having high breakdown voltages include a first epitaxial layer of a second conductivity type disposed over a substrate of a first conductivity type and a trench formed in the epitaxial layer. The trench includes a second epitaxial layer grown along the sidewalls and bottom of the trench. | 04-17-2014 |
20140110777 | TRENCH GATE METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR AND FABRICATING METHOD THEREOF - A trench gate metal oxide semiconductor field effect transistor includes a substrate and a gate. The substrate has a trench. The trench is extended downwardly from a surface of the substrate. The gate includes an insertion portion and a symmetrical protrusion portion. The insertion portion is embedded in the trench. The symmetrical protrusion portion is symmetrically protruded over the surface of the substrate. | 04-24-2014 |
20140110778 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The present invention discloses a semiconductor device and a method for manufacturing the semiconductor device. The semiconductor device includes a gate insulating layer formed on an inner wall of a substrate recess, a work function material layer formed on the gate insulating layer so as to apply a tensile stress or a compressive stress to a channel of a MOS field-effect transistor, and a gate metal formed on the work function material layer. The method for manufacturing the semiconductor device includes forming a work function material layer on a gate insulating layer so as to apply a tensile stress or a compressive stress to a channel of a MOS field-effect transistor, wherein the gate insulating layer is formed on an inner wall of a substrate recess, and depositing a gate metal on the work function material layer. | 04-24-2014 |
20140110779 | VERTICAL POWER MOSFET - Vertical power MOSFETs having a super junction are devices capable of having a lower on resistance than other vertical power MOSFETs. Although they have the advantage of high-speed switching due to rapid depletion of an N type drift region at the time of turn off in switching operation, they are likely to cause ringing. A vertical power MOSFET having a super junction structure provided by the present invention has, in the surface region of a first conductivity type drift region under a gate electrode, an undergate heavily doped N type region having a depth shallower than that of a second conductivity type body region and having a concentration higher than that of the first conductivity type drift region. | 04-24-2014 |
20140110780 | INSULATED GATE TYPE SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer. | 04-24-2014 |
20140110781 | SEMICONDUCTOR DEVICE WITH BURIED BIT LINE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes trenches defined in a substrate, buried bit lines partially filling the trenches, a first source/drain layer filling remaining portions of the trenches on the buried bit lines, stack patterns having a channel layer and a second source/drain layer stacked therein and bonded to the first source/drain layer, wherein the channel layer contacts with the first source/drain layer, and word lines crossing with the buried bit lines and disposed adjacent to sidewalls of the channel layer. | 04-24-2014 |
20140117438 | Semiconductor Device and Method for Manufacturing a Semiconductor Device - A semiconductor device is at least partially formed in a semiconductor substrate, the substrate including first and second opposing main surfaces. The semiconductor device includes a cell field portion and a contact area, the contact area being electrically coupled to the cell field portion, the cell field portion including at least a transistor. The contact area includes a connection substrate portion insulated from other substrate portions and including a part of the semiconductor substrate, an electrode adjacent to the second main surface and in contact with the connection substrate portion, and a metal layer disposed over the first main surface, the connection substrate portion being electrically coupled to the metal layer to form an ohmic contact between the electrode and metal layer. The connection substrate portion is not electrically coupled to a component of the cell field portion by a conductive material disposed between the first and second main surfaces. | 05-01-2014 |
20140117439 | MOS-Gated Power Devices, Methods, and Integrated Circuits - MOS-gated devices, related methods, and systems for vertical power and RF devices including an insulated trench and a gate electrode. A body region is positioned so that a voltage bias on the gate electrode will cause an inversion layer in the body region. Permanent electrostatic charges are included in said insulation material. A conductive shield layer is positioned above the insulated trench, to reduce parasitic capacitances. | 05-01-2014 |
20140117440 | SEMICONDUCTOR DEVICE WITH IMPURITY REGION WITH INCREASED CONTACT AREA - A semiconductor device includes a semiconductor substrate, an impurity region in the semiconductor substrate, and a conductive layer contacting a top surface of the impurity region and at least a side surface of the impurity region. | 05-01-2014 |
20140124852 | SEMICONDUCTOR DEVICE WITH REDUCED MILLER CAPACITANCE AND FABRICATION METHOD THEREOF - A semiconductor transistor device includes an epitaxial layer grown on a semiconductor substrate; an ion well with a junction depth in the epitaxial layer; a gate trench with a depth shallower than the junction depth in the ion well; a recess at the bottom of the gate trench; a gate oxide layer at surface of the gate trench and in the recess to form a protruding tip structure; a gate in the gate trench; and a drain extension region between the gate trench and the epitaxial layer. | 05-08-2014 |
20140124853 | SEMICONDUCTOR DEVICE WITH REDUCED MILLER CAPACITANCE AND FABRICATION METHOD THEREOF - A semiconductor transistor device includes an epitaxial layer grown on a semiconductor substrate; an ion well with a junction depth in the epitaxial layer; a gate trench with a depth shallower than the junction depth in the ion well; a recess at the bottom of the gate trench; a gate oxide layer at surface of the gate trench and in the recess to form a protruding tip structure; a gate in the gate trench; and a drain extension region between the gate trench and the epitaxial layer. | 05-08-2014 |
20140124854 | SEMICONDUCTOR DEVICES AND METHODS OF FORMING THE SAME - Semiconductor devices and methods of forming the same may be provided. The semiconductor devices may include a trench in a substrate. The semiconductor devices may also include a bulk electrode within opposing sidewalls of the trench. The semiconductor devices may further include a liner electrode between the bulk electrode and the opposing sidewalls of the trench. The liner electrode may include a sidewall portion between a sidewall of the bulk electrode and one of the opposing sidewalls of the trench. | 05-08-2014 |
20140131792 | Semiconductor Device with Metal-Filled Groove in Polysilicon Gate Electrode - A semiconductor device includes a semiconductor substrate, a body region of a first conductivity type in the substrate, a source region of a second conductivity type opposite the first conductivity type adjacent the body region, and a trench extending into the substrate adjacent the source and body regions. The trench contains a polysilicon gate electrode insulated from the substrate. The device further includes a dielectric layer on the substrate, a gate metallization on the dielectric layer and covering part of the substrate and a source metallization on the dielectric layer and electrically connected to the source region. The source metallization is spaced apart from the gate metallization and covers a different part of the substrate than the gate metallization. A metal-filled groove in the polysilicon gate electrode is electrically connected to the gate metallization, and extends along a length of the trench underneath at least part of the source metallization. | 05-15-2014 |
20140138764 | TRENCH-BASED DEVICE WITH IMPROVED TRENCH PROTECTION - A semiconductor device includes a semiconductor substrate having a first type of conductivity. A first layer is formed on the substrate having the first type of conductivity and is more lightly doped than the substrate. At least one trench is formed in the first layer. A dielectric layer lines the bottom surface and the sidewalls of the trench. A conducting material fills the trench. A lightly doped region is formed in the first layer having the second conductivity type. The lightly doped region is disposed below the bottom surface of the trench. A metal layer is disposed over the first layer and the conducting material. A first electrode is formed over the metal layer and a second electrode is formed on a backside of the substrate. | 05-22-2014 |
20140138765 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes at least one first conductive layer stacked on a substrate where a cell region and a contact region are defined; at least one first slit passing through the first conductive layer, second conductive layers stacked on the first conductive layer; a second slit passing through the first and second conductive layers and connected with one side of the first slit, and a third slit passing through the first and second conductive layers and connected with the other side of the first slit. | 05-22-2014 |
20140138766 | IMPACT IONIZATION DEVICES, AND METHODS OF FORMING IMPACT IONIZATION DEVICES - Impact ionization devices including vertical and recessed impact ionization metal oxide semiconductor field effect transistor (MOSFET) devices and methods of forming such devices are disclosed. The devices require lower threshold voltage than conventional MOSFET devices while maintaining a footprint equal to or less than conventional MOSFET devices. | 05-22-2014 |
20140138767 | OXIDE TERMINATED TRENCH MOSFET WITH THREE OR FOUR MASKS - An oxide termination semiconductor device may comprise a plurality of gate trenches, a gate runner, and an insulator termination trench. The gate trenches are located in an active region. Each gate trench includes a conductive gate electrode. The insulator termination trench is located in a termination region that surrounds the active region. The insulator termination trench is filled with an insulator material to form an insulator termination for the semiconductor device. Source and body regions inside the active region are at source potential and source and body regions outside the isolation trench are at drain potential. The device can be made using a three-mask or four-mask process. | 05-22-2014 |
20140138768 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING REDUCED UNIT CELL AREA AND METHOD FOR MANUFACTURING THE SAME - A semiconductor integrated circuit device includes a semiconductor substrate; a plurality of word lines extending parallel to one another on the semiconductor substrate; a plurality of bit lines extending parallel to one another on the semiconductor substrate and arranged to intersect the word lines, thereby delimiting a plurality of crossing regions and a plurality of unit memory cells; a plurality of gate electrodes formed to control respective pairs of unit memory cells adjacent to each other with the word lines interposed therebetween and to contact corresponding word lines on one sides of the crossing regions; storage node contacts respectively formed in spaces of the unit memory cells; and a plurality of bit line contacts formed to contact the respective bit lines on one sides of the crossing regions. | 05-22-2014 |
20140145257 | SEMICONDUCTOR DEVICE HAVING A METAL RECESS - Provided is a semiconductor device (e.g., transistor such as a FinFET or planar device) having a a liner layer and a metal layer (e.g., Tungsten (W)) in a trench (e.g., via CVD and/or ALD). A single chamber (e.g., an extreme fill chamber) will be utilized to separately etch back the liner layer and the metal layer. In general, the liner layer may be etched back further than the metal layer to provide for larger contact and lower resistance. After etching is complete, a bottom-up fill/growth of metal (e.g., W) will be performed (e.g., via CVD in a W chamber or the like) to increase the presence of gate metal in the trench. | 05-29-2014 |
20140145258 | SEMICONDUCTOR DEVICE WITH REDUCED MILLER CAPACITANCE AND FABRICATION METHOD THEREOF - A semiconductor power device includes an epitaxial layer grown on a semiconductor substrate; an ion well with a junction depth in the epitaxial layer; a gate trench with a depth deeper than the junction depth in the ion well; a gate oxide layer in the gate trench; a gate embedded the gate trench; and a pocket doping region in the epitaxial layer. The pocket doping region is adjacent to and covers at least a corner of the gate trench. | 05-29-2014 |
20140151786 | NON-VOLATILE GRAPHENE NANOMECHANICAL SWITCH - Non-volatile switches and methods for making the same include a gate material formed in a recess of a substrate; a flexible conductive element disposed above the gate material, separated from the gate material by a gap, where the flexible conductive element is supported on at least two points across the gap, and where a voltage above a gate threshold voltage causes a deformation in the flexible conductive element such that the flexible conductive element comes into contact with a drain in the substrate, thereby closing a circuit between the drain and a source terminal. The gap separating the flexible conductive element and the gate material is sized to create a negative threshold voltage at the gate material for opening the circuit. | 06-05-2014 |
20140151787 | ELECTRONIC DEVICE INCLUDING A TRENCH AND A CONDUCTIVE STRUCTURE THEREIN - An electronic device can include a transistor structure, including a patterned semiconductor layer overlying a substrate and having a primary surface, wherein the patterned semiconductor layer defines a first trench and a second trench that extend from the primary surface towards the substrate. The electronic device can further include a first conductive electrode and a gate electrode within the first trench. The electronic device can still further include a second conductive electrode within the second trench. The electronic device can include a source region within the patterned semiconductor layer and disposed between the first and second trenches. The electronic device can further include a body contact region within the patterned semiconductor layer and between the first and second trenches, wherein the body contact region is spaced apart from the primary surface. Processes of forming the electronic device can take advantage of forming all trenches during processing sequence. | 06-05-2014 |
20140151788 | TRENCH POWER FIELD EFFECT TRANSISTOR DEVICE AND METHOD - In one embodiment, a structure for a trench power field effect transistor device with controlled, shallow, abrupt, body contact regions. | 06-05-2014 |
20140159142 | Recessed Channel Insulated-Gate Field Effect Transistor with Self-Aligned Gate and Increased Channel Length - A metal-oxide-semiconductor transistor (MOS) and method of fabricating the same, in which the effective channel length is increased relative to the width of the gate electrode. A dummy gate electrode overlying dummy gate dielectric material is formed at the surface of the structure, with self-aligned source/drain regions, and dielectric spacers on the sidewalls of the dummy gate structure. The dummy gate dielectric underlies the sidewall spacers. Following removal of the dummy gate electrode and the underlying dummy gate dielectric material, including from under the spacers, a silicon etch is performed to form a recess in the underlying substrate. This etch is self-limiting on the undercut sides, due to the crystal orientation, relative to the etch of the bottom of the recess. The gate dielectric and gate electrode material are then deposited into the remaining void, for example to form a high-k metal gate MOS transistor. | 06-12-2014 |
20140159143 | SUPER JUNCTION SEMICONDUCTOR DEVICE AND ASSOCIATED FABRICATION METHOD - A semiconductor device with a substrate, an epitaxy layer formed on the substrate, a plurality of deep wells formed in the epitaxy layer, a plurality of trench gate MOSFET units each of which is formed in top of the epitaxy layer between two adjacent deep well, wherein a trench gate of the trench gate MOSFET unit is shallower than half of the distance between two adjacent deep wells, which may reduce the product of on-state resistance and the gate charge of the semiconductor device. | 06-12-2014 |
20140159144 | TRENCH GATE MOSFET AND METHOD OF FORMING THE SAME - A trench gate MOSFET is provided. An N-type epitaxial layer on an N-type substrate has a wider first trench and a narrower second trench below the first trench. A first insulating layer is in the second trench. First and second conductive layers are respectively in lower and upper portions of the first trench. A thicker second insulating layer is between the first conductive layer and N-type epitaxial layer and between the first insulating layer and first conductive layer, and a thinner third insulating layer is between the second conductive layer and N-type epitaxial layer. A P-type first doped region is in the N-type epitaxial layer below the first trench and surrounds the top of the second trench. A P-type second doped region is in the N-type epitaxial layer below the second trench. A source region is in the N-type epitaxial layer and surrounds the top of the first trench. | 06-12-2014 |
20140159145 | SEMICONDUCTOR DEVICE - A semiconductor device includes a gate trench across an active region of a semiconductor substrate, a gate structure filling the gate trench, and source/drain regions formed in the active region at respective sides of the gate structure. The gate structure includes a sequentially stacked gate electrode and insulating capping pattern, and a gate dielectric layer between the gate electrode and the active region. The gate electrode is located at a lower level than an upper surface of the active region and includes a barrier conductive pattern and a gate conductive pattern. The gate conductive pattern includes a first part having a first width and a second part having a second width greater than the first width. The barrier conductive pattern is interposed between the first part of the gate conductive pattern and the gate dielectric layer. | 06-12-2014 |
20140159146 | TRENCH GATE TRANSISTOR AND METHOD OF FABRICATING SAME - A trench gate transistor is formed from a semiconductor substrate with its upper surface covered in an oxide dielectric layer. The trench gate transistor has a drain region, a body region, source region and a trench lined with a gate insulator that electrically insulates a conductive gate electrode formed in the trench from the body region. The body region has a sloping upper surface that extends away from the trench towards the drain region. The sloping upper surface is formed by exposing the oxide dielectric layer to an oxidized atmosphere, through an opening in a mask, so as to form a dielectric region. The dielectric region includes the oxide dielectric layer and a sacrificial area of the semiconductor substrate. | 06-12-2014 |
20140159147 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor substrate having a drift layer of a first conductivity type, a body layer of a second conductivity type formed on a surface of the drift layer, and a source layer formed on a portion of a surface of the body layer; a gate insulation film formed on an inner wall of a trench that extends from the surface of the semiconductor substrate through the source layer and the body layer to the drift layer; and a gate electrode housed in the trench and covered with the gate insulation film, the gate electrode including, in a region located at a drift layer side of a boundary between the body and drift layers, at least one first semiconductor layer of the first conductivity type and at least one second semiconductor layer of the second conductivity type that are alternately disposed and joined to each other. | 06-12-2014 |
20140159148 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A method of manufacturing a semiconductor device includes forming device isolation layer in a substrate to define active regions of which each has first regions and a second region between the first regions, forming a first trench and a pair of second trenches in the substrate, and forming gates in the second trenches, respectively. The first trench extends in a first direction and crosses the active regions and the device isolation layer. The second trenches are connected to a bottom of the first trench and extend in the first direction at both sides of the second regions. | 06-12-2014 |
20140167149 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device includes a gate electrode formed on a sidewall of a structure extending from a semiconductor substrate. A junction region is form in the structure to a first depth from a top of the structure and formed to overlap the gate electrode. A protection layer is formed between an outer wall of the structure and the gate electrode to a second depth less than the first depth from the top of the structure. | 06-19-2014 |
20140167150 | POWER SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - There is provided a power semiconductor device including a contact formed in an active region, a trench gate extendedly formed from the first region into a first termination region and formed alternately with the contact, a first conductive well formed between the contact of the active region and the trench gate, a first conductive well extending portion formed in the first termination region and a part of a second termination region, and a first conductive field limiting ring formed in the second termination region and contacting the well extending portion. | 06-19-2014 |
20140167151 | STEPPED TRENCH MOSFET AND METHOD OF FABRICATING THE SAME - A step trench metal-oxide-semiconductor field-effect transistor comprises a drift layer, a first semiconductor region, a stepped gate and a floating region. The drift layer is of a first conductivity type. The first semiconductor region is of a second conductivity type and located on the drift layer, wherein the drift layer and the first semiconductor region have a stepped gate trench therein. The stepped gate trench at least comprises a first recess located in the first semiconductor region and extending into the drift layer and a second recess located below a bottom of the first recess, wherein a width of the second recess is smaller than a width of the first recess. A floating region is of the second conductivity type and located in the drift layer below the second recess. | 06-19-2014 |
20140167152 | Reduced Gate Charge Trench Field-Effect Transistor - In one implementation, a trench field-effect transistor (trench FET) can include a semiconductor substrate including a drain region, a drift zone over the drain region, and first and second gate trenches including a gate dielectric and respective gate electrodes disposed therein, also over the drain region. The trench FET can further include a depletion trench situated between the first and second gate trenches, the depletion trench including a trench insulator. The trench insulator adjoins the gate electrodes and the gate dielectric so as to reduce a gate charge of the trench FET. | 06-19-2014 |
20140167153 | Trench Fet Having Merged Gate Dielectric - In one implementation, a trench field-effect transistor (trench FET) includes a semiconductor substrate having a drain region, a drift zone over the drain region, and depletion trenches formed over the drain region. Each depletion trench includes a depletion trench dielectric and a depletion electrode. The trench FET can further include a respective bordering gate trench situated alongside each depletion trench, each bordering gate trench having a gate electrode and a gate dielectric. The gate dielectric is merged with the depletion trench dielectric between the depletion electrode and the gate electrode. | 06-19-2014 |
20140175539 | CANYON GATE TRANSISTOR AND METHODS FOR ITS FABRICATION - Lithographic limitations on gate and induced channel length in MOSFETS are avoided by forming non-planar MOSFETS in a cavity extending into a semiconductor substrate. The gate insulator and channel region lie proximate a cavity sidewall having angle α preferably about ≧90 degrees with respect to the semiconductor surface. The channel length depends on the bottom depth of the cavity and the depth from the surface of a source or drain region adjacent the cavity. The corresponding drain or source lies at the cavity bottom. The cavity sidewall extends therebetween. Neither depth is lithographic dependent. Very short channels can be consistently formed, providing improved performance and manufacturing yield. Source, drain and gate connections are brought to the same surface so that complex circuits can be readily constructed. The source and drain regions are preferably formed epitaxially and strain inducing materials can be used therein to improve channel carrier mobility. | 06-26-2014 |
20140183624 | Adaptive Charge Balanced MOSFET Techniques - An adaptive charge balanced MOSFET device includes a field plate stacks, a gate structure, a source region, a drift region and a body region. The gate structure includes a gate region surrounded by a gate insulator region. The field plate stack includes a plurality of field plate insulator regions, a plurality of field plate regions, and a field ring region. The plurality of field plates are separated from each other by respective field plate insulators. The body region is disposed between the gate structure, the source region, the drift region and the field ring region. Each of two or more field plates are coupled to the field ring. | 07-03-2014 |
20140183625 | Semiconductor Device - A semiconductor device includes a semiconductor layer of a first conductivity type having a first surface and a second surface, a source region disposed on the first surface, a gate region disposed on the first surface adjacent the source region, and a drain region disposed on the first surface. The semiconductor device also includes a pair of charge control trenches disposed between the gate region and the drain region. Each of the pair of charge control trenches is characterized by a width and includes a first dielectric material disposed therein and a second material disposed internal to the first dielectric material. Additionally, a concentration of doping impurities present in the semiconductor layer of the first conductivity type and a distance between the pair of charge control trenches define an electrical characteristic of the semiconductor device that is independent of the width of each of the pair of charge control trenches. | 07-03-2014 |
20140191311 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - Provided is a semiconductor structure and a method for manufacturing the same. By the channel reestablishment, the tops of the source/drain regions located on both sides of the spacers are higher than bottoms of the gate stack structure and the spacers, and the source/drain regions laterally extend below the bottoms of the gate stack structure and the spacers and exceed the spacers, thereby reaching the right below of the gate stack structure. Thus, the elevated source/drain MOSFET is obtained. The semiconductor structure reduces the number of process steps, improves efficiency and decreases the cost. | 07-10-2014 |
20140191312 | Semiconductor Device and Method of Forming the Same - A semiconductor device includes a substrate having an active region and a device isolation layer defining the active region, a gate electrode on the active region, source/drain regions at the active region at both sides of the gate electrode, a buffer insulating layer on the device isolation layer, an etch stop layer formed on the buffer insulating layer and extending onto the gate electrode and the source/drain region, a first interlayer insulating layer on the etch stop layer, a first contact and a second contact penetrating the first interlayer insulating layer and the etch stop layer. The first contact and the second contact are spaced apart from each other and are in contact with the source/drain region and the buffer insulating layer, respectively. | 07-10-2014 |
20140191313 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is a semiconductor device formed with a trench portion for providing a concave portion in a gate width direction and with a gate electrode provided within and on a top surface of the trench portion via a gate insulating film. At least a part of a surface of each of the source region and the drain region is made lower than other parts of the surface by removing a thick oxide film formed in the vicinity of the gate electrode. Making lower the part of the surface of each of the source region and the drain region allows current flowing through a top surface of the concave portion of the gate electrode at high concentration to flow uniformly through the entire trench portion, which increase an effective gate width of the concave portion formed so as to have a varying depth in a gate width direction. | 07-10-2014 |
20140197479 | SEMICONDUCTOR DEVICE HAVING DUAL PARALLEL CHANNEL STRUCTURE AND METHOD OF FABRICATING THE SAME - A semiconductor device may include a substrate having a drift region doped to a first conduction type. A trench may be etched into an upper surface of the substrate. A gate may be arranged along side walls of the trench. A gate oxide layer may be between the side walls of the trench and gate and between a bottom surface of the trench and gate. A first source region of the first conduction type may be on the upper surface of the substrate. A second source region of the first conduction type may be on the bottom surface of the trench. A first well region may be between the first source region and drift region, and a second well region may be between the second source region and drift region, the first and second well regions being doped to a second conduction type (electrically opposite to the first conduction type). | 07-17-2014 |
20140197480 | SEMICONDUCTOR STRUCTURE HAVING COMMON GATE AND FABRICATION METHOD THEREOF - Various embodiments provide a semiconductor structure having a common gate and fabrication method of the semiconductor structure. In an exemplary method, after forming a first metal gate and a second metal gate, a conductive material layer can be formed at least at the boundary between the first metal gate and the second metal gate. Thus, one end of the conductive material layer can be connected to a first metal gate electrode, and the other end of the conductive material layer can be connected to a second metal gate electrode. The resistance between the first metal gate electrode and the second metal gate electrode can be effectively reduced. Gate voltages of an NMOS transistor and a PMOS transistor of the common gate can be the same. | 07-17-2014 |
20140197481 | VERTICAL TYPE SEMICONDUCTOR DEVICES - A vertical type semiconductor device includes first and second word line structures that include first and second word lines. The word lines surround a plurality of pillar structures, which are provided to connect the word lines to corresponding string select lines. Connecting patterns electrically connect pairs of adjacent first and second word lines in a same plane. The device may be a nonvolatile memory device or a different type of device. | 07-17-2014 |
20140197482 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device includes a semiconductor substrate having a first gate groove having first and second side walls facing to each other. A first gate insulating film covers the first and second side walls. A first gate electrode is disposed on the first gate insulating film and in a lower portion of the first gate groove. A first burying insulating film buries the first gate groove and covers the first gate electrode. A first diffusion region is adjacent to a first upper portion of the first gate insulating film. The first upper portion is positioned on an upper portion of the first side wall of the first gate groove. A second diffusion region is in contact with an upper portion of the second side wall of the first gate groove. | 07-17-2014 |
20140197483 | TRENCH SHIELDING STRUCTURE FOR SEMICONDUCTOR DEVICE AND METHOD - A shielding structure for a semiconductor device includes a plurality of trenches. The trenches include passivation liners and shield electrodes, which are formed therein. In one embodiment, the shielding structure is placed beneath a control pad. In another embodiment, the shielding structure is placed beneath a control runner. | 07-17-2014 |
20140197484 | Dual Work Function Recessed Access Device and Methods of Forming - A recessed access device having a gate electrode formed of two or more gate materials having different work functions may reduce the gate-induced drain leakage current losses from the recessed access device. The gate electrode may include a first gate material having a high work function disposed in a bottom portion of the recessed access device and a second gate material having a lower work function disposed over the first gate material and in an upper portion of the recessed access device. | 07-17-2014 |
20140203355 | FIELD EFFECT TRANSISTOR AND SCHOTTKY DIODE STRUCTURES - In accordance with an embodiment a structure can include a monolithically integrated trench field-effect transistor (FET) and Schottky diode. The structure can include a first gate trench extending into a semiconductor region, a second gate trench extending into the semiconductor region, and a source region flanking a side of the first gate trench. The source region can have a substantially triangular shape, and a contact opening extending into the semiconductor region between the first gate trench and the second gate trench. The structure can include a conductor layer disposed in the contact opening to electrically contact the source region along at least a portion of a slanted sidewall of the source region, and the semiconductor region along a bottom portion of the contact opening. The conductor layer can form a Schottky contact with the semiconductor region. | 07-24-2014 |
20140203356 | SEMICONDUCTOR DEVICE INCLUDING VERTICAL SEMICONDUCTOR ELEMENT - A semiconductor device including a vertical semiconductor element has a trench gate structure and a dummy gate structure. The trench gate structure includes a first trench that penetrates a first impurity region and a base region to reach a first conductivity-type region in a super junction structure. The dummy gate structure includes a second trench that penetrates the base region reach the super junction structure and is formed to be deeper than the first trench. | 07-24-2014 |
20140209999 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first conductivity-type drain layer, a first conductivity-type drift layer formed on the drain layer, a second conductivity-type base layer formed on the drift layer, a first conductivity-type source layer which is selectively formed on a surface of the base layer, a trench region formed through a surface of the source layer such that the trench region reaches the drift layer from the surface of the source layer, a gate electrode formed adjacent to the base layer and inside the trench region, and surrounded by a first insulation film, a field plate electrode formed in the trench region below the gate electrode and surrounded by a second insulation film having a higher dielectric constant than the first insulation film, a drain electrode which is electrically connected to the drain layer, and a source electrode electrically connected to the source layer. | 07-31-2014 |
20140210000 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A first lower insulating film (LIL | 07-31-2014 |
20140210001 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor substrate formed with an element region; a first conductive type first region formed in the element region and located on a surface side of the semiconductor substrate; a second conductive type second region located in a deeper position than the first region in the element region and contacting the first region; a first conductive type third region located in a deeper position than the second region in the element region, contacting the second region, and separated from the first region by the second region; and a gate disposed in a trench extending from the surface to reach the third region, and contacting a range of the second region via the insulation film. A thickness of the second region in a depth direction is gradually increased from the peripheral part of the element region to the central part thereof | 07-31-2014 |
20140217496 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - To realize a semiconductor device having a power MOSFET satisfying both a low conduction resistance and a high junction breakdown voltage by a simple and easy manufacturing method. Over an n-type substrate, a p-type epitaxial layer of a low concentration is formed, and, in an active part, a plurality of active regions is defined by a plurality of trenches that is formed in the epitaxial layer and extends in a first direction with first intervals in a second direction orthogonal to the first direction. In the epitaxial layer between the adjacent trenches, an n-type diffusion region that functions as a drain offset layer is formed, and, in the epitaxial layer between a side wall of the trench and the n-type diffusion region, a p-type diffusion region connected with a channel region (the p-type diffusion region) is formed, to constitute a super junction structure. Further, by forming an n-type diffusion region in the epitaxial layer, having a prescribed width from a side wall of a trench lying in the end part of the active part toward an outer periphery part, to achieve the improvement of a drain breakdown voltage. | 08-07-2014 |
20140217497 | MOSFET WITH CURVED TRENCH FEATURE COUPLING TERMINATION TRENCH TO ACTIVE TRENCH - A metal oxide semiconductor field effect transistor (MOSFET) in and on a semiconductor surface provides a drift region of a first conductivity type. A plurality of active area trenches in the drift region, and first and second termination trenches are each parallel to and together sandwiching the active area trenches. The active area trenches and termination trenches include a trench dielectric liner and electrically conductive filler material filled field plates. A gate is over the drain drift region between active area trenches. A body region of a second conductivity abuts the active region trenches. A source of the first conductivity type is in the body region on opposing sides of the gate. A vertical drain drift region uses the drift region below the body region. A first and second curved trench feature couples the field plate of the first and second termination trench to field plates of active area trenches. | 08-07-2014 |
20140231903 | Semiconductor Device with a Super Junction Structure Having a Vertical Impurity Distribution - A super junction semiconductor device includes a semiconductor portion with parallel first and second surfaces. An impurity layer of a first conductivity type is formed in the semiconductor portion. Between the first surface and the impurity layer a super junction structure includes first columns of the first conductivity type and second columns of a second conductivity type. A sign of a compensation rate between the first and second columns may change along a vertical extension of the columns perpendicular to the first surface. A body zone of the second conductivity type is formed between the first surface and one of the second columns. A field extension zone of the second conductivity type may be electrically connected to the body zone or a field extension zone of the first conductivity type may be connected to the impurity layer. The field extension zone improves the avalanche characteristics of the semiconductor device. | 08-21-2014 |
20140231904 | Super Junction Semiconductor Device with Overcompensation Zones - According to an embodiment, a super junction semiconductor device may be manufactured by introducing impurities of a first impurity type into an exposed surface of a first semiconductor layer of the first impurity type, thus forming an implant layer. A second semiconductor layer of the first impurity type may be provided on the exposed surface and trenches may be etched through the second semiconductor layer into the first semiconductor layer. Thereby first columns with first overcompensation zones obtained from the implant layer are formed between the trenches. Second columns of the second conductivity type may be provided in the trenches. The first and second columns form a super junction structure with a vertical first section in which the first overcompensation zones overcompensate a corresponding section in the second columns. | 08-21-2014 |
20140231905 | SEMICONDUCTOR DEVICE - A trench MOSFET including: an epitaxial layer; a body region on the epitaxial layer, the body region and the epitaxial layer forming a first interface; a trench; a trench bottom oxide in the trench; and polysilicon in the trench, the trench bottom oxide and the polysilicon forming a second interface; where the first and second interfaces are substantially aligned or are at substantially the same level. | 08-21-2014 |
20140239386 | Trench Gated Power Device With Multiple Trench Width and its Fabrication Process - Power devices, and related process, where both gate and field plate trenches have multiple stepped widths, using self-aligned process steps. | 08-28-2014 |
20140246718 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - In a manufacturing method of a semiconductor device, a trench is defined in a semiconductor substrate, and an adjuster layer having a first conductivity type impurity concentration higher than a drift layer is formed at a portion of the semiconductor substrate adjacent to a bottom wall of the trench. A channel layer is formed by introducing second conductivity type impurities to a portion of the semiconductor substrate adjacent to a sidewall of the trench and between the adjustment layer and a main surface of the semiconductor substrate while restricting the channel layer from extending in a depth direction of the trench by the adjustment layer. | 09-04-2014 |
20140252459 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - Provided is a method for fabricating a semiconductor device, which includes the following steps. A substrate having a plurality of pillars is provided, wherein a plurality of trenches are formed around each pillar, and a doped region is disposed at a bottom of each pillar. An insulation layer is formed below each doped region. | 09-11-2014 |
20140252460 | High Density MOSFET Array with Self-Aligned Contacts Delimited by Nitride-Capped Trench Gate Stacks and Method - A high density trench-gated MOSFET array and method are disclosed. It comprises semiconductor substrate partitioned into MOSFET array area and gate pickup area; epitaxial region, body region and source region; numerous precisely spaced active nitride-capped trench gate stacks (ANCTGS) embedded till the epitaxial region. Each ANCTGS comprises a stack of polysilicon trench gate with gate oxide shell and silicon nitride cap covering top of polysilicon trench gate and laterally registered to gate oxide shell. The ANCTGS forms, together with the source, body, epitaxial region, a MOSFET device in the MOSFET array area. Over MOSFET array area and gate pickup area, a patterned dielectric region atop the MOSFET array and a patterned metal layer atop the patterned dielectric region. Thus, the patterned metal layer forms, with the MOSFET array and the gate pickup area, self-aligned source and body contacts through the inter-ANCTGS separations. | 09-11-2014 |
20140252461 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device and a fabricating method thereof are provided. The semiconductor device include: a trench disposed within a substrate, the trench comprising an upper trench part that is wider than a lower trench part in width; a gate disposed in the trench; an interlayer insulating layer pattern disposed above the gate in the trench; a source region disposed within the substrate and contacting a sidewall of the upper trench part; a body region disposed below the source region in the substrate; and a contact trench disposed above the body region and filled with a conductive material. | 09-11-2014 |
20140252462 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device and a fabricating method thereof are provided. The semiconductor device includes: a trench disposed within a substrate, the trench comprising an upper trench part that is wider than a lower trench part in width; a gate disposed in the trench; an interlayer insulating layer pattern disposed above the gate in the upper trench part; a source region disposed within the substrate and contacting a sidewall of the upper trench part; a body region disposed below the source region in the substrate; and a contact trench disposed above the body region and filled with a conductive material. | 09-11-2014 |
20140252463 | SCHOTTKY AND MOSFET+SCHOTTKY STRUCTURES, DEVICES, AND METHODS - Power devices which include trench Schottky barrier diodes and also (preferably) trench-gate transistors. Isolation trenches flank both the gate regions and the diode mesas, and have an additional diffusion below the bottom of the isolation trenches. The additional diffusion helps to reduce the electric field (and leakage), when the device is in the OFF state, at both the Schottky barrier and at the body diode. | 09-11-2014 |
20140252464 | METHOD OF FORMING STACKED TRENCH CONTACTS AND STRUCTURES FORMED THEREBY - Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a structure comprising a first contact metal disposed on a source/drain contact of a substrate, and a second contact metal disposed on a top surface of the first contact metal, wherein the second contact metal is disposed within an IID disposed on a top surface of a metal gate disposed on the substrate. | 09-11-2014 |
20140252465 | SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING THE SAME - A semiconductor device has a semiconductor substrate including a body region, a drift region, a trench that extends from a surface of the semiconductor substrate into the drift region through the body region, and a source region located adjacent to the trench in a range exposed to the surface of the semiconductor substrate, the source region being isolated from the drift region by the body region. A specific layer is disposed on a bottom of the trench, and it has a characteristic of forming a depletion layer at a junction between the specific layer and the drift region. An insulating layer covers an upper surface of the specific layer and a sidewall of the trench. A conductive portion is formed on a part of the side wall of the trench. The conductive portion is joined to the specific layer, and reaches the surface of the semiconductor substrate. | 09-11-2014 |
20140264562 | Field Effect Transistor Devices with Regrown P-Layers - A transistor device includes a drift layer having a first conductivity type, a body layer on the drift layer, the body layer having a second conductivity type opposite the first conductivity type, and a source region on the body layer, the source region having the first conductivity type. The device further includes a trench extending through the source region and the body layer and into the drift layer, a channel layer on the inner sidewall of the trench, the channel layer having the second conductivity type and having an inner sidewall opposite an inner sidewall of the trench, a gate insulator on the inner sidewall of the channel layer, and a gate contact on the gate insulator. | 09-18-2014 |
20140264563 | Field Effect Transistor Devices with Protective Regions - A transistor device includes a first conductivity type drift layer, a second conductivity type first region in the drift layer, a body layer having the second conductivity type on the drift layer including the first region, a source layer on the body layer, and a body contact region that extends through the source layer and the body layer and into the first region. The transistor device further includes a trench through the source layer and the body layer and extending into the drift layer adjacent the first region. The trench has an inner sidewall facing away from the first region. A gate insulator is on the inner sidewall of the trench, and a gate contact is on the gate insulator. | 09-18-2014 |
20140264564 | Field Effect Transistor Devices with Buried Well Protection Regions - A method of forming a transistor device includes providing a drift layer having a first conductivity type, forming a first region in the drift layer, the first region having a second conductivity type that is opposite the first conductivity type, forming a body layer on the drift layer including the first region, forming a source layer on the body layer, forming a trench in the source layer and the body layer above the first region and extending into the first region, forming a gate insulator on the inner sidewall of the trench, and forming a gate contact on the gate insulator. | 09-18-2014 |
20140264565 | METHOD OF FORMING A TRANSISTOR AND STRUCTURE THEREFOR - In one embodiment, a semiconductor device is formed to include a gate structure extending into a semiconductor material that is underlying a first region of semiconductor material. The gate structure includes a conductor and also a gate insulator that has a first portion positioned between the gate conductor and a first portion of the semiconductor material that underlies the gate conductor. The first portion of the semiconductor material is configured to form a channel region of the transistor which underlies the gate conductor. The gate structure may also include a shield conductor overlying the gate conductor and having a shield insulator between the shield conductor and the gate conductor. The shield insulator may also have a second portion positioned between the shield conductor and a second portion of the gate insulator and a third portion overlying the shield conductor. | 09-18-2014 |
20140264566 | SEMICONDUCTOR ELEMENT AND MANUFACTURING METHOD AND OPERATING METHOD OF THE SAME - A memory device and a manufacturing method of the same are provided. The memory device includes a substrate, a memory material layer, a first dielectric layer, a first gate layer, a second gate layer, and a source/drain (S/D) region. The substrate has a trench, and the memory material layer is formed on a sidewall of the trench. The first gate layer, the second gate layer, and the first dielectric layer, which is formed between the first gate layer and the second gate layer, are filled in the trench. The source/drain region is formed in the substrate and adjacent to the memory material layer. The first gate layer is extended in a direction perpendicular to a direction in which the source/drain region is extended. | 09-18-2014 |
20140264567 | DIRECT-DRAIN TRENCH FET WITH SOURCE AND DRAIN ISOLATION - In a general aspect, an apparatus can include a semiconductor layer of a first conductivity type, the semiconductor layer having a top-side surface. The apparatus can also include a well region of a second conductivity type opposite the first conductivity type, the well region being disposed in an upper portion of the semiconductor layer. The apparatus can further include a gate trench disposed in the semiconductor layer, the gate trench extending through the well region, and a drain contact disposed, at least in part, on the top-side surface of the semiconductor layer, the drain contact being adjacent to the well region. The apparatus can still further include an isolation trench disposed between the drain contact and the gate trench in the semiconductor layer, the isolation trench extending through the well region. | 09-18-2014 |
20140264568 | SEMICONDUCTOR DEVICE AND METHODS OF MANUFACTURING THE SAME - In a method of manufacturing a semiconductor device, a trench is formed by removing an upper portion of a substrate. A gate insulation layer pattern is formed on an inner wall of the trench. A gate electrode is formed on the gate insulation layer pattern. The gate electrode fills a lower portion of the trench. A capping layer is formed on the gate electrode and the gate insulation layer pattern. The capping layer is partially oxidized to form a first capping layer pattern and a second capping layer pattern. The first capping layer pattern is not oxidized, and the second capping layer pattern is oxidized. A third capping layer pattern is formed on the second capping layer pattern, the third capping layer pattern filling an upper portion of the trench. | 09-18-2014 |
20140264569 | METHODS AND APPARATUS RELATED TO TERMINATION REGIONS OF A SEMICONDUCTOR DEVICE - In one general aspect, an apparatus can include a semiconductor region, and a trench defined within the semiconductor region. The trench can have a depth aligned along a vertical axis and have a length aligned along a longitudinal axis orthogonal to the vertical axis. The trench can have a first portion of the length included in a termination region of the semiconductor region and can have a second portion of the length included in an active region of the semiconductor region. | 09-18-2014 |
20140264570 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes a first junction region formed at the bottom of a vertical pillar, a bit line formed below the first junction region, and an insulation film formed below the bit line. As a result, the 4F2-sized semiconductor device is provided and the bit line is configured in the form of a laminated structure of a conductive layer and a polysilicon layer, so that bit line resistance is reduced. In addition, the semiconductor device reduces ohmic contact resistance by forming silicide between the conductive layer and the polysilicon layer, and includes an insulation film at a position between the semiconductor substrate and the bit line, resulting in reduction of bit line capacitance. Therefore, the sensing margin of the semiconductor device is increased and the data retention time is also increased. | 09-18-2014 |
20140264571 | SHIELDED GATE TRENCH MOSFET PACKAGE - A trench formed in a body layer and epitaxial layer of a substrate is lined with a dielectric layer. A shield electrode formed within a lower portion of the trench is insulated by the dielectric layer. A gate electrode formed in the trench above the shield electrode is insulated from the shield electrode by another dielectric layer. One or more source regions formed within the body layer is adjacent a sidewall of the trench. A source pad formed above the body layer is electrically connected to the source regions and insulated from the gate electrode and shield electrode. The source pad provides an external contact to the source region. A gate pad provides an external contact to the gate electrode. A shield electrode pad provides an external contact to the shield electrode. A resistive element is electrically connected between the shield electrode pad and a source lead. | 09-18-2014 |
20140284707 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor memory device includes a first semiconductor layer, a second semiconductor layer, a first electrode, and a second electrode. The first semiconductor layer is a first conductivity type. The second semiconductor layer is provided in a surface region of the first semiconductor layer and is the first conductivity type. The first electrode is provided inside a first trench extending in the first direction and opened to a surface of the second semiconductor layer. The second electrode is provided in a second trench extending in a second direction crossing the first direction and opened to the surface of the second semiconductor layer. A dimension from the surface of the second semiconductor layer to a lower end of the second electrode is shorter than a dimension from the surface of the second semiconductor layer to a lower end of the first electrode. | 09-25-2014 |
20140284708 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to an embodiment, a method for manufacturing a semiconductor device includes forming a gate trench extending into a first semiconductor layer; forming a gate insulating film on an internal wall of the gate trench; forming a polysilicon in the gate trench; etching the polysilicon into the gate trench; forming an interlayer insulating film on the polysilicon; etching the first semiconductor layer so as to project the interlayer insulating film from the first semiconductor layer; forming a second semiconductor layer on the first semiconductor layer; forming a third semiconductor layer on the second semiconductor layer; forming a sidewall contacting a side face of the interlayer insulating film; forming a fourth semiconductor layer of the second conductivity type in the second semiconductor layer; and forming a first electrode electrically connected to the third semiconductor layer and the fourth semiconductor layer. | 09-25-2014 |
20140284709 | SEMICONDUCTOR DEVICE - A buried layer of a second conductivity type and a lower layer of a second conductivity type are formed in a drift layer. A boundary insulating film is formed in the boundary between the lateral portion of the buried layer of a second conductivity type and the drift layer. The lower layer of a second conductivity type is in contact with the lower end of the buried layer of a second conductivity type and the lower end of the boundary insulating film. The buried layer of a second conductivity type is electrically connected to a source electrode. A high-concentration layer of a second conductivity type is formed in the surface layer of the buried layer of a second conductivity type. | 09-25-2014 |
20140284710 | INSULATED GATE SEMICONDUCTOR DEVICE HAVING SHIELD ELECTRODE STRUCTURE - In one embodiment, a semiconductor device includes a multi-portion shield electrode structure formed in a drift region. The shield electrode includes a wide portion formed in proximity to a channel side of the drift region, and a narrow portion formed deeper in the drift region. The narrow portion is separated from the drift region by a thicker dielectric region, and the wide portion is separated from the drift region by a thinner dielectric region. That portion of the drift region in proximity to the wide portion can have a higher dopant concentration than other portions of the drift region. | 09-25-2014 |
20140291753 | TRENCH MOSFET STRUCTURE HAVING SELF-ALIGNED FEATURES FOR MASK SAVING AND ON-RESISTANCE REDUCTION - A trench MOSFET structure having self-aligned features for mask saving and on-resistance reduction is disclosed, wherein the source region is formed by performing source Ion Implantation through contact opening of a contact interlayer, and further source diffusion. A dielectric sidewall spacer is formed on sidewalls of the contact interlayer in the contact open areas to define trenched source-body contacts for on-resistance reduction and avalanche capability improvement. | 10-02-2014 |
20140291754 | SEMICONDUCTOR STRUCTURE HAVING BURIED WORD LINE AND METHOD OF MANUFACTURING THE SAME - A semiconductor structure having buried word line formed in a trench in a semiconductor substrate includes a gate oxide layer, a gate conductor, a gate cap layer, a blocking layer, and an isolation structure. The gate oxide layer is formed on the inner surface of the trench, the gate conductor is formed in the trench, and the gate cap layer is formed on the gate conductor. The blocking layer surrounds a bottom portion of the gate conductor, and the bottom portion of the gate conductor is isolated from the gate oxide layer by the blocking layer. The isolation structure surrounds a top portion of the gate conductor and in contact with the top end of the blocking layer. The top portion of the gate conductor is isolated from the gate oxide layer and the from the gate cap layer by the isolation structure. | 10-02-2014 |
20140291755 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MODULE - A semiconductor device includes a first source/drain region and a second source/drain region disposed in an active region of a semiconductor substrate, and a gate structure crossing the active region and disposed between the first and second source/drain regions, the gate structure including a gate electrode having a first part and a second part on the first part, the gate electrode being at a lower level than an upper surface of the active region, an insulating capping pattern on the gate electrode, a gate dielectric between the gate electrode and the active region, and an empty space between the active region and the second part of the gate electrode. | 10-02-2014 |
20140291756 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a first n-type semiconductor layer, a p-type semiconductor layer, a second n-type semiconductor layer and a trench. The first n-type semiconductor layer includes a first interface and a second interface. The second interface forms an upper surface of a convex protruded from the first interface. The p-type semiconductor layer is stacked on the first n-type semiconductor layer and includes a first region stacked on the first interface and a second region stacked on the second interface. The first region is uniformly continuous with the second region. The second n-type semiconductor layer is stacked on the p-type semiconductor layer. The trench is depressed from the second n-type semiconductor layer through the p-type semiconductor layer into the convex of the first n-type semiconductor layer. | 10-02-2014 |
20140291757 | SEMICONDUCTOR DEVICE - A semiconductor device disclosed herein includes an insulated gate, a main and a sub trench conductors. The main and sub trench conductors are formed in the cell region, and have a conductor that is covered with an insulation film and fills a trench extending in a first direction. The sub trench is located, with respect to the main trench conductor, in a second direction perpendicularly crossing the first direction and extending from the cell region side to the non-cell region. Length of the sub trench conductor in the first direction is shorter than a length of the insulated gate in the first direction. Distance between the main and sub trench conductors is shorter than a distance between the main trench conductor and the insulated gate. At least a part of the sub trench conductor reaches a position deeper than a boundary between the first and second semiconductor regions. | 10-02-2014 |
20140299932 | Semiconductor Device Including a Gate Trench and a Source Trench - A semiconductor device includes a source trench extending into a semiconductor body from a first surface of the semiconductor body. A source trench dielectric and a source trench electrode are in the source trench. A gate trench dielectric and a gate trench electrode are in a gate trench extending into the semiconductor body from the first surface. A body region of a first conductivity type is between the gate and source trenches. A source region of a second conductivity type different from the first conductivity type is between the gate and source trenches. An interconnection electrically couples the body region and the source trench electrode. The interconnection adjoins a lateral face of the source trench electrode and the body region. A source contact is on the source trench electrode at the first surface. | 10-09-2014 |
20140299933 | Semiconductor Component Having a Semiconductor Body with a Cutout - A semiconductor component includes a semiconductor body having a surface and a cutout in the semiconductor body. The cutout extends from the surface of the semiconductor body into the semiconductor body in a direction perpendicular to the surface. The cutout has a base and at least one sidewall. The component further includes a layer on the surface of the semiconductor body and in the cutout. The layer forms a well above the cutout. The well has a well base, a well edge and at least one well sidewall. The at least one well sidewall forms an angle α in the range of 20° to 80° with respect to the surface of the semiconductor body. The layer has at least one edge which, proceeding from the well edge, extends in the direction of the surface of the semiconductor body. | 10-09-2014 |
20140306284 | Semiconductor Device and Method for Producing the Same - A trench gate MOS transistor is provided. It includes a semiconductor substrate with a trench including a gate electrode, a source region, a body contact region adjacent to a channel region, wherein the dopant concentration in the channel region varies in a lateral direction and has at least one minimal value in a direction from the gate electrode to the body contact region, which is distanced from the gate electrode. Further, a method for producing the transistor is provided. | 10-16-2014 |
20140312412 | SELF ALIGNED EMBEDDED GATE CARBON TRANSISTORS - Transistors with self-aligned source/drain regions and methods for making the same. The methods include forming a gate structure embedded in a recess in a substrate; removing substrate material around the gate structure to create self-aligned source and drain recesses; forming a channel layer over the gate structure and the source and drain recesses; and forming source and drain contacts in the source and drain recesses, wherein the source and drain contacts extend above the channel layer. | 10-23-2014 |
20140312413 | SELF ALIGNED EMBEDDED GATE CARBON TRANSISTORS - Transistors with self-aligned source/drain regions a gate structure embedded in a substrate; self-aligned source and drain contacts embedded in the substrate around the gate structure; and a channel layer over the gate structure and self-aligned source and drain contacts. The source and drain contacts extend above the channel layer. | 10-23-2014 |
20140319600 | TSV Structure With A Built-In U-Shaped FET Transistor For Improved Characterization - A through-the silicon via (TSV) structure providing a built-in TSV U-shaped FET that includes an annular gate shaped as a TSV partially embedded in a substrate, the annular gate having an inner and an outer surface bound by an oxide layer; a drain formed on an isolated epitaxial layer on top of the substrate conformally connecting the gate oxide layer surrounding the inner annular surface of the TSV; a source partially contacting said gate oxide layer conformally contacting gate oxide layer surrounding the outer surface of the TSV. | 10-30-2014 |
20140319601 | BOTTOM SOURCE SUBSTRATELESS POWER MOSFET - A bottom source power metal-oxide-semiconductor field-effect transistor (MOSFET) device includes a gate electrode and a source electrode formed on an initial insulation layer on a first surface of a semiconductor chip and a drain electrode formed on a second surface of the semiconductor chip. The source electrode includes a source metal, a source electrode bump formed on the source metal and a source electrode metal layer on top of the source electrode bump. A first insulation layer covers the gate electrode. A through via aligned to the gate electrode is formed from the second surface of the chip to expose a portion of the gate electrode from the second surface. | 10-30-2014 |
20140319602 | Power Transistor with At Least Partially Integrated Driver Stage - A semiconductor die includes a semiconductor substrate having a first region and a second region isolated from the first region. A power transistor disposed in the first region of the semiconductor substrate has a gate, a source and a drain. A gate driver transistor disposed in the second region of the semiconductor substrate has a gate, a source and a drain. The gate driver transistor is electrically connected to the gate of the power transistor and operable to turn the power transistor off or on responsive to an externally-generated control signal applied to the gate of the gate driver transistor. A first contact pad is electrically connected to the source of the power transistor, and a second contact pad is electrically connected to the drain of the power transistor. A third contact pad is electrically connected to the gate of the gate driver transistor for receiving the externally-generated control signal. | 10-30-2014 |
20140319603 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type; a first electrode electrically connected to the first semiconductor layer; a second semiconductor layer of a second conductivity type provided on the first semiconductor layer; a third semiconductor layer of the first conductivity type selectively provided on the second semiconductor layer; a second electrode electrically connected to the second semiconductor layer and the third semiconductor layer; a third electrode and a floating electrode provided from an upper surface side of the third semiconductor layer through the third semiconductor layer and the second semiconductor layer to the first semiconductor layer via a first insulating film; a second insulating film provided between the second electrode and the third electrode, the second electrode and the floating electrode. | 10-30-2014 |
20140319604 | HIGH VOLTAGE FIELD BALANCE METAL OXIDE FIELD EFFECT TRANSISTOR (FBM) - A semiconductor power device formed in a semiconductor substrate comprising a highly doped region near a top surface of the semiconductor substrate on top of a lightly doped region supported by a heavily doped region. The semiconductor power device further comprises source trenches opened into the highly doped region filled with conductive trench filling material in electrical contact with the source region near the top surface. The semiconductor power device further comprises buried P-regions disposed below the source trenches and doped with dopants of opposite conductivity from the highly doped region. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. | 10-30-2014 |
20140327072 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes: an N-type drift layer; a P-type anode layer on the N-type drift layer; a trench penetrating the P-type anode layer; a conductive substance embedded in the trench via an insulating film; and an N-type buffer layer between the N-type drift layer and the P-type anode layer and having impurity concentration which is higher than that of the N-type drift layer. | 11-06-2014 |
20140332879 | Power Semiconductor Device with Reduced On-Resistance and Increased Breakdown Voltage - In one implementation, a power semiconductor device includes an active region and a termination region. A depletion trench finger extends from the active region and ends in the termination region. An arched depletion trench surrounds the depletion trench finger in the termination region, the arched depletion trench enables one or both of an increased breakdown voltage and a reduced on-resistance in the power semiconductor device. | 11-13-2014 |
20140332880 | RECESSED GATE SILICON-ON-INSULATOR FLOATING BODY DEVICE WITH SELF-ALIGNED LATERAL ISOLATION - Embodiments of a manufacturing process for recessed gate devices on silicon-on-insulator (SOI) substrate with self-aligned lateral isolation are described. This allows the creation of true in-pitch recessed gate devices without requiring an extra isolation dimension. A lateral isolation trench is formed between pairs of recessed gate devices by etching the silicon-on-insulator area down to a buried oxide layer on which the silicon-on-insulator layer is formed. The position of the trench is self-aligned and defined by the gate width and the dimension of spacers disposed on either side of the gate. The isolation trench is filled with a dielectric material and then etched back to the middle of the SOI body and the remaining volume is filled with a doped conductive material. The doped conductor is subject to a thermal cycle to create source and drain regions of the device through out-diffusion of the doped material. | 11-13-2014 |
20140339629 | CONTACT FORMATION FOR ULTRA-SCALED DEVICES - Embodiments of the invention provide approaches for forming gate and source/drain (S/D) contacts. Specifically, the semiconductor device includes a gate transistor formed over a substrate, a S/D contact formed over a trench-silicide (TS) layer and positioned adjacent the gate transistor, and a gate contact formed over the gate transistor, wherein at least a portion of the gate contact is aligned over the TS layer. This structure enables contact with the TS layer, thereby decreasing the distance between the gate contact and the source/drain, which is desirable for ultra-area-scaling. | 11-20-2014 |
20140346590 | Semiconductor Device, Method of Manufacturing a Semiconductor Device and Integrated Circuit - A semiconductor device formed in a semiconductor substrate includes a source region, a drain region, a gate electrode, and a body region disposed between the source region and the drain region. The gate electrode is disposed adjacent at least two sides of the body region, and the source region and the gate electrode are coupled to a source terminal. A width of the body region between the two sides of the body region is selected so that the body region is configured to be fully depleted. | 11-27-2014 |
20140346591 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a semiconductor device includes forming a device isolation film defining an active region, forming a recess configured to expose a seam contained in the device isolation film by etching the active region and the device isolation film, forming a sacrificial film to fill the exposed seam, and forming a gate at a lower part of the recess. | 11-27-2014 |
20140353743 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a substrate having an element isolation region, a trench formed on the element isolation region, a gate electrode buried in the trench, and a plurality of active regions formed on both ends of the gate electrode, wherein a pin is formed under the gate electrode between the active regions. | 12-04-2014 |
20140353744 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate including a first active region and second active regions, a bit line structure in contact the first active region, and storage node contacts in contact the second active regions. A top surface of the first active region is lower than the top surfaces of the second active regions. | 12-04-2014 |
20140361362 | POWER TRANSISTOR HAVING A TOP-SIDE DRAIN AND FORMING METHOD THEREOF - A power transistor having a top-side drain and a forming method thereof are provided. Firstly, a body layer is formed. An epitaxial layer is subsequently formed on the body layer. Then a gate trench is formed in the body layer and the epitaxial layer. Afterward, a gate structure is formed in the gate trench. Then, a doped drain layer is formed within the epitaxial layer. Next, a source is formed in contact with the body layer. Lastly, a drain is formed in contact with the dope drain layer. The structure and forming method disclosed can through arranging the drain at the top of the power transistor integrate with the newly high performance packaging design structure. Accordingly, the efficiency of the power transistor can be greatly enhanced. | 12-11-2014 |
20140361363 | FIELD EFFECT TRANSISTOR WITH NARROW BANDGAP SOURCE AND DRAIN REGIONS AND METHOD OF FABRICATION - A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode. | 12-11-2014 |
20140367772 | Semiconductor Device Including a Drift Zone and a Drift Control Zone - A semiconductor device includes a semiconductor body having a drift zone of a first conductivity type and a drift control zone. A junction termination structure is at a first side of the semiconductor body. A first dielectric is between the drift zone and the drift control zone. A second dielectric is at a second side of the semiconductor body. The drift control zone includes a first drift control subregion of the first conductivity type and a second drift control subregion of a second conductivity type between the first drift control subregion and the second dielectric. | 12-18-2014 |
20140367773 | Method of Manufacturing a Semiconductor Device with Self-Aligned Contact Plugs and Semiconductor Device - Semiconductor oxide pillars are selectively grown on semiconductor mesas between precursor structures that extend from a main surface into a semiconductor substrate. Spaces between the semiconductor oxide pillars are filled with one or more auxiliary materials to form alignment plugs in a vertical projection of the precursor structures. The semiconductor oxide pillars are removed selectively against the alignment plugs. Contact spacers are provided along sidewalls of the alignment plugs. Between opposing ones of the contact spacers contact plugs are provided directly adjoining the semiconductor mesas. The contact plugs are self-aligned to the semiconductor mesas and allow a further reduction of the lateral dimensions of the semiconductor mesas without recessing the semiconductor mesas. | 12-18-2014 |
20140367774 | Semiconductor Devices Having Partially Oxidized Gate Electrodes - Semiconductor devices are provided including a first trench in a semiconductor substrate; a first insulating film in the first trench; a first conductive film on the first insulating film, the first conductive film having upper and lower portions and filling at least a portion of the first trench; and a first work function adjustment film having first and second portions, a first lower work function adjustment film portion and a first upper work function adjustment portion. The first lower work function adjustment film portion overlaps the lower portion of the first conductive film and the first upper work function adjustment film portion overlaps the upper portion of the first conductive film between the first insulating film and the first conductive film. | 12-18-2014 |
20140374820 | DUAL TRENCH MOS TRANSISTOR AND METHOD FOR FORMING THE SAME - A dual trench MOS transistor comprises of the following elements. A plurality of trenches are formed in an n− epitaxial layer on a heavy doped n+ semiconductor substrate and spaced to each other by one mesa. Each the trench has a trench oxide layer formed on a bottom and sidewalls thereof. A first polysilicon layer is formed in the trenches. A plurality of recesses are formed in the mesas and spaced to each other with one sub-mesa. Each the recess has a recess oxide layer formed on a bottom and sidewalls thereof. A second polysilicon layer for serving as a gate is formed in the recesses. The mesas are implanted to have implanted areas at two side of the gate. The implanted areas and the first polysilicon layer are applied to serve as the source. The rear surface of the substrate is served as the drain. | 12-25-2014 |
20140374821 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is a semiconductor device having a vertical MOS transistor and a method of manufacturing the same. The vertical MOS transistor has a trench gate, a distance between a gate electrode and an N-type high concentration buried layer below the gate electrode is formed longer than that in the conventional structure, and a P-type trench bottom surface lower region ( | 12-25-2014 |
20150008512 | Method of Manufacturing a Semiconductor Device with Device Separation Structures and Semiconductor Device - A method of manufacturing a semiconductor device includes introducing at least a first and a second trench pattern including array trenches from a first surface into a semiconductor substrate, wherein an array isolation portion of the semiconductor substrate separates the first and second trench patterns. A buried gate electrode structure is provided in the first and second trench patterns at a distance to the first surface. In a single etch process, both a device separation trench having a first width is introduced into the array isolation portion and cell separation trenches having at most a second width that is smaller than the first width are introduced into semiconductor fins between the array trenches. Switching devices integrated in the same semiconductor die may be formed in a cost effective way. | 01-08-2015 |
20150008513 | TRENCH TYPE POWER SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A trench type semiconductor power device is disclosed. An epitaxial layer is formed on a semiconductor substrate. A gate trench is formed in the epitaxial layer. A gate oxide layer and a trench gate are formed in the gate trench. A spacer is provided on the gate. A metal top structure on the gate is separated from a contact structure by the spacer. The contact structure extends into the epitaxial layer. A source doping region is provided in the epitaxial layer at least between the contact structure and the gate trench. | 01-08-2015 |
20150008514 | TRENCH GATE MOSFET - A trench gate MOSFET is provided. An epitaxial layer is disposed on a substrate. A body layer is disposed in the epitaxial layer. The epitaxial layer has a first trench therein, the body layer has a second trench therein, and the first trench is disposed below the second trench. A first insulating layer is disposed on a surface of the first trench. A second insulating layer is disposed in the first trench. A first conductive layer is disposed between the first and second insulating layers. A second conductive layer is disposed in the second trench. A third insulating layer is disposed between the second conductive layer and the body layer and between the second conductive layer and the first conductive layer. A dielectric layer is disposed on the epitaxial layer and covers the second conductive layer. Two doped regions are disposed in the body layer respectively beside the second trench. | 01-08-2015 |
20150008515 | TRENCH GATE MOSFET - A trench gate MOSFET is provided. An epitaxial layer is disposed on a substrate. A body layer is disposed in the epitaxial layer. The epitaxial layer has a first trench therein, the body layer has a second trench therein, the first trench is disposed below the second trench, and first trench is narrower than the second trench. | 01-08-2015 |
20150021681 | SEMICONDUCTOR DEVICE HAVING METAL GATE AND MANUFACTURING METHOD THEREOF - A manufacturing method of a semiconductor device having metal gate includes providing a substrate having a first semiconductor device formed thereon, and the first semiconductor device includes a first dummy gate. Next, the dummy gate is removed to form a first gate trench in the first semiconductor device, and the substrate is exposed in a bottom of the first gate trench. Subsequently, an epitaxial channel layer is formed in the first gate trench. | 01-22-2015 |
20150021682 | NORMALLY ON HIGH VOLTAGE SWITCH - In some embodiments, a normally on high voltage switch device (“normally on switch device”) incorporates a trench gate terminal and buried doped gate region. In other embodiments, a surface gate controlled normally on high voltage switch device is formed with trench structures and incorporates a surface channel controlled by a surface gate electrode. The surface gate controlled normally on switch device may further incorporate a trench gate electrode and a buried doped gate region to deplete the conducting channel to aid in the turning off of the normally on switch device. The normally on switch devices thus constructed can be readily integrated with MOSFET devices and formed using existing high voltage MOSFET fabrication technologies. | 01-22-2015 |
20150021683 | METHODS OF FORMING SEMICONDUCTOR DEVICE WITH SELF-ALIGNED CONTACT ELEMENTS AND THE RESULTING DEVICES - One method disclosed herein includes forming a sacrificial etch stop material in a recess above a replacement gate structure, with the sacrificial etch stop material in position, forming a self-aligned contact that is conductively coupled to the source/drain region, after forming the self-aligned contact, performing at least one process operation to expose and remove the sacrificial etch stop material in the recess so as to thereby re-expose the recess, and forming a third layer of insulating material in at least the re-exposed recess. | 01-22-2015 |
20150021684 | SEMICONDUCTOR DEVICE HAVING BURIED CHANNEL ARRAY AND METHOD OF MANUFACTURING THE SAME - A semiconductor device and a method of fabricating a semiconductor device, the device including an active region on a substrate, the active region being defined by a field region; gate trenches in the active region of the substrate; gate structures respectively formed in the gate trenches; and at least one carrier barrier layer in the substrate and under the gate trenches. | 01-22-2015 |
20150021685 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - According to one embodiment, a semiconductor device includes a semiconductor layer; a plurality of semiconductor regions; second semiconductor region; a first electrode being positioned between the plurality of first semiconductor regions, the first electrode contacting with the semiconductor layer, each of the plurality of first semiconductor regions, and the second semiconductor region via a first insulating film; a second electrode provided below the first electrode, and contacting with the semiconductor layer via a second insulating film; an insulating layer interposed between the first electrode and the second electrode; a third electrode electrically connected to the semiconductor layer; and a fourth electrode connected to the second semiconductor region. The first electrode has a first portion and a pair of second portions. And each of the pair of second portions is provided along the first insulating film. | 01-22-2015 |
20150028411 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A semiconductor device includes a first gate structure formed in a semiconductor substrate; a second gate structure formed over the semiconductor substrate and over the first gate structure; and a bit line formed in the semiconductor substrate, and formed below the first gate structure. | 01-29-2015 |
20150028412 | SEMICONDUCTOR DEVICE - A semiconductor device is provided that comprises a semiconductor substrate comprising an active area and a peripheral region adjacent the active area and structure positioned in the peripheral region for hindering the diffusion of mobile ions from the peripheral region into the active area. | 01-29-2015 |
20150028413 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a method for manufacturing a semiconductor device includes: forming a plurality of trenches; forming a gate insulating film; burying a gate electrode; burying an insulating member; projecting the insulating member; forming a base layer; forming a mask film; forming a first semiconductor layer; forming a carrier ejection layer; forming a first electrode; and forming a second electrode. The projecting includes projecting the insulating member from the upper surface of the semiconductor substrate by removing an upper layer portion of the semiconductor substrate. The mask film is formed so as to cover the projected insulating member. The forming the first semiconductor layer includes forming a first semiconductor layer of the first conductivity type in an upper layer portion of the base layer by doping the base layer with impurity, the upper layer portion having a lower surface below an upper end of the gate electrode. | 01-29-2015 |
20150028414 | INSULATED GATE SEMICONDUCTOR DEVICE STRUCTURE - In one embodiment, a vertical insulated-gate field effect transistor includes a shield electrode formed in trench structure within a semiconductor material. A gate electrode is isolated from the semiconductor material using gate insulating layers. Before the shield electrode is formed, spacer layers can be used form shield insulating layers along portions of the trench structure. The shield insulating layers are thicker than the gate insulating layers. In another embodiment, the shield insulating layers have variable thickness. | 01-29-2015 |
20150035050 | SEMICONDUCTOR DEVICE WITH AIR GAP AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a plurality of first conductive structures formed over a substrate, second conductive structures each formed between neighboring first conductive structures of the first conductive structures, air gaps each formed between the second conductive structures and the neighboring first conductive structures thereof, third conductive structures each capping a portion of the air gaps, and capping structures each capping the other portion of the air gaps. | 02-05-2015 |
20150041886 | VERTICAL POWER TRANSISTOR DEVICE - A power metal-oxide-semiconductor field-effect transistor (MOSFET) includes a substrate, a drift layer over the substrate, and a spreading layer over the drift layer. The spreading layer includes a pair of junction implants separated by a junction gate field effect (JFET) region. A gate oxide layer is on top of the spreading layer. The gate contact is on top of the gate oxide layer. Each one of the source contacts are on a portion of the spreading layer separate from the gate oxide layer and the gate contact. The drain contact is on the surface of the substrate opposite the drift layer. | 02-12-2015 |
20150041887 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor layer surrounding a bottom of the trench gate, a second semiconductor layer disposed along one of end portions of the trench gate in a longitudinal direction of the trench gate, one of end portions of the second semiconductor layer contacting the body layer and the other of the end portions of the second semiconductor layer contacting the first semiconductor layer, and a connecting layer, one of end portions of the connecting layer being connected to the body layer and the other of the end portions of the connecting layer being connected to the first semiconductor layer, the connecting layer contacting the second semiconductor layer, and the connecting layer being separated from the one of the end portions of the trench gate in the longitudinal direction of the trench gate by the second semiconductor layer. | 02-12-2015 |
20150041888 | SEMICONDUCTOR DEVICE INCLUDING BURIED BIT LINE, AND ELECTRONIC DEVICE USING THE SAME - A semiconductor device includes: an active region defined by a device isolation film, an upper portion of which is divided into a first active pillar and a second active pillar; a first gate formed to proceed between the first active pillar and the second active pillar so as to obliquely cross the active region, and formed to contact the first active pillar; a second gate formed to proceed between the first active pillar and the second active pillar so as to obliquely cross the active region, and formed to cross the second active pillar; a conductive line formed below the first gate and the second gate, and commonly coupled to the first pillar and the second pillar; and an insulation film formed to enclose the conductive line within the active region. | 02-12-2015 |
20150054067 | Integrated Circuitry Comprising Nonvolatile Memory Cells And Methods Of Forming A Nonvolatile Memory Cell - A method of forming a gate construction of a recessed access device includes forming a pair of sidewall spacers laterally over opposing sidewalls of a gate dielectric and elevationally over first conductive gate material. The gate dielectric, the first conductive gate material, and the sidewall spacers are received within a trench formed in semiconductive material. Second conductive gate material is deposited within the semiconductive material trench between the pair of sidewall spacers in electrical connection with the first conductive gate material. Other implementations are disclosed, including recessed access device gate constructions independent of method of manufacture. | 02-26-2015 |
20150060997 | SUSPENDED BODY FIELD EFFECT TRANSISTOR - A semiconductor fin including a vertical stack, from bottom to top, of a second semiconductor material and a first semiconductor material is formed on a substrate. A disposable gate structure straddling the semiconductor fin is formed. A source region and a drain region are formed employing the disposable gate structure as an implantation mask, At least one semiconductor shell layer or a semiconductor cap layer can be formed as an etch stop structure. A planarization dielectric layer is subsequently formed. A gate cavity is formed by removing the disposable gate structure. A portion of the second semiconductor material is removed selective to the first semiconductor material within the gate cavity so that a middle portion of the semiconductor fin becomes suspended over the substrate. A gate dielectric layer and a gate electrode are sequentially formed. The gate electrode laterally surrounds a body region of a fin field effect transistor. | 03-05-2015 |
20150060998 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - In one embodiment, a method of manufacturing a semiconductor device includes forming, on a semiconductor substrate, a sacrificial semiconductor pillar having a pillar-like shape extending in a first direction perpendicular to a main surface of the semiconductor substrate, and being formed of a first semiconductor material. The method further includes forming, around the sacrificial semiconductor pillar, a channel semiconductor layer having a tube-like shape extending in the first direction, and being formed of a second semiconductor material different from the first semiconductor material. The method further includes removing the sacrificial semiconductor pillar after the channel semiconductor layer is formed. The channel semiconductor layer is formed on electrode layers via an insulator, the electrode layers being formed on the semiconductor substrate. | 03-05-2015 |
20150060999 | POWER SEMICONDUCTOR DEVICE - A power semiconductor device may include: a drift layer having a first conductivity; a hole accumulating layer formed on the drift layer and having the first conductivity; a well layer formed on the hole accumulating layer and having a second conductivity; an emitter region formed in an internal portion of an upper portion of the well layer and having the first conductivity; and trench gates penetrating through the emitter region, the well layer, and the hole accumulating layer, and having a gate insulating layer formed on a surface thereof. The trench gate may be sequentially divided into a first gate part, a second gate part, and a third gate part from an upper portion thereof depending on a height of a material filled in the trench gate, the first to third gate parts having different resistances from each other. | 03-05-2015 |
20150061000 | PROCESS FOR FORMING A SHORT CHANNEL TRENCH MOSFET AND DEVICE FORMED THEREBY - A process for forming a short channel trench MOSFET. The process includes forming a first implant at the bottom of a trench that is formed in the body of the trench MOSFET and forming a second or angled implant that is tilted in its orientation and directed perpendicular to the trench that is formed in the body of the trench MOSFET. The second implant is adjusted so that it does not reach the bottom of the trench. In one embodiment the angled implant is n-type material. | 03-05-2015 |
20150069503 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A semiconductor device including a substrate having an active region is disclosed. A field-plate region and a bulk region are in the active region, wherein the bulk region is at a first side of the field-plate region. At least one trench-gate structure is disposed in the substrate corresponding to the bulk region. At least one source-doped region is in the substrate corresponding to the bulk region, wherein the source-doped region surrounds the trench-gate structure. A drain-doped region is in the substrate at a second side opposite to the first side of the field-plate region, wherein an extending direction of length of the trench-gate structure is perpendicular to that of the drain-doped region as viewed from a top view perspective. | 03-12-2015 |
20150076590 | Semiconductor Device, Integrated Circuit and Method of Manufacturing a Semiconductor Device - A semiconductor device includes a transistor in a semiconductor substrate having a first main surface. The transistor includes a source region, a drain region, a channel region, a drift zone, and a gate electrode adjacent to at least two sides of the channel region. The channel region and the drift zone are disposed along a first direction parallel to the first main surface, between the source region and the drain region. The semiconductor device further includes a conductive layer beneath the gate electrode and insulated from the gate electrode. | 03-19-2015 |
20150076591 | Semiconductor Device and Method of Manufacturing the Same - A semiconductor device includes a semiconductor body having a first surface and a second surface opposite to the first surface. The semiconductor device further includes first and second trenches extending from the first surface into the semiconductor body. The semiconductor device further includes at least one lateral IGFET including a first load terminal at the first surface, a second load terminal at the first surface and a gate electrode within the first trenches. The semiconductor device further includes at least one vertical IGFET including a first load terminal at the first surface, a second load terminal at the second surface and a gate electrode within the second trenches. | 03-19-2015 |
20150076592 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes: forming a trench on a semiconductor layer of a first conductive type; forming a first insulation film which covers an inner surface of the trench; forming a first conductive material on the first insulation film; etching the first conductive material and then the first insulation film such that the semiconductor layer is exposed on an inner surface of an upper portion of the trench and an upper end portion of the first conductive material is positioned above an upper end portion of the first insulation film; re-etching the first conductive material; forming a second insulation film which covers the semiconductor layer exposed on the inner surface of the upper portion of the trench and the first conductive material; and forming a second conductive material on the first insulation film and the second insulation film. | 03-19-2015 |
20150084121 | Transistor Device with a Field Electrode - A transistor device includes a source region, a drift region, and a body region arranged between the source region and the drift region. A gate electrode is adjacent to the body region, and dielectrically insulated from the body region by a gate dielectric. A field electrode arrangement is adjacent to the drift region and the body region, spaced apart from the gate electrode in a first direction that is perpendicular to a vertical direction in which the source region and the drift region are spaced apart, and includes a field electrode and a field electrode dielectric. The field electrode dielectric dielectrically insulates the field electrode at least from the drift region. The field electrode arrangement has a first width adjacent the drift region, and a second width adjacent the body region and the first width is larger than the second width. | 03-26-2015 |
20150084122 | Semiconductor Device - A semiconductor device has an active region defined by a device isolation region arranged on a surface of a semiconductor substrate, a plurality of transistor pillars arranged along a first direction within the active region, and a first dummy pillar disposed in the device isolation region. The first dummy pillar is arranged on a line extending along the first direction from the transistor pillars. The semiconductor device also has a second dummy pillar disposed between the transistor pillars and the first dummy pillar, a gate electrode continuously extending so as to surround each of side surfaces of the transistor pillars, a first power supply gate electrode surrounding a side surface of the first dummy pillar, and a second power supply gate electrode surrounding a side surface of the second dummy pillar. The second power supply gate electrode is connected to the gate electrode and the first power supply gate electrode. | 03-26-2015 |
20150084123 | Semiconductor Device - A semiconductor device includes: a first semiconductor region; a second semiconductor region; a third semiconductor region; a fourth semiconductor region; an insulation film, which is arranged on an inner wall of a recess extending from an upper surface to the second semiconductor region; a control electrode, which is arranged on a region of the insulation film on a side surface of the recess; a first main electrode connected to the first semiconductor region; a second main electrode connected to the fourth semiconductor region; and a bottom electrode, which is arranged on the insulation film and is electrically connected to the second main electrode, and a length of the recess in an extension direction thereof is equal to or larger than a width of the recess, and the width of the recess is wider than an interval between the adjacent recesses. | 03-26-2015 |
20150084124 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate having an element region and a termination region. The element region includes a first body region having a first conductivity type, a first drift region having a second conductivity type, and first floating regions having the first conductivity type. The termination region includes FLR regions, a second drift region and second floating regions. The FLR regions have the first conductivity type and surrounds the element region. The second drift region has the second conductivity type, makes contact with and surrounds the FLR regions. The second floating regions have the first conductivity type and is surrounded by the second drift region. The second floating regions surround the element region. At least one of the second floating regions is placed at an element region side relative to the closest one of the FLR regions to the element region. | 03-26-2015 |
20150091083 | Semiconductor Device and Method of Manufacturing a Semiconductor Device with Lateral FET Cells and Field Plates - A method of manufacturing a semiconductor device includes providing dielectric stripe structures extending from a first surface into a semiconductor substrate between semiconductor fins. A first mask is provided that covers a first area including first stripe sections of the dielectric stripe structures and first fin sections of the semiconductor fins. The first mask exposes a second area including second stripe and second fin sections. A channel/body zone is formed in the second fin sections by introducing impurities, wherein the first mask is used as an implant mask. Using an etch mask that is based on the first mask, recess grooves are formed at least in the second stripe sections. | 04-02-2015 |
20150097230 | TRENCH GATE TRENCH FIELD PLATE VERTICAL MOSFET - A semiconductor device having a vertical drain extended MOS transistor may be formed by forming deep trench structures to define vertical drift regions of the transistor, so that each vertical drift region is bounded on at least two opposite sides by the deep trench structures. The deep trench structures are spaced so as to form RESURF regions for the drift region. Trench gates are formed in trenches in the substrate over the vertical drift regions. The body regions are located in the substrate over the vertical drift regions. | 04-09-2015 |
20150097231 | VERTICAL TRENCH MOSFET DEVICE IN INTEGRATED POWER TECHNOLOGIES - A semiconductor device having a vertical drain extended MOS transistor may be formed by forming deep trench structures to define at least one vertical drift region bounded on at least two opposite sides by the deep trench structures. The deep trench structures include dielectric liners. The deep trench structures are spaced so as to form RESURF regions for the drift region. Vertical gates are formed in vertically oriented gate trenches in the dielectric liners of the deep trench structures, abutting the vertical drift regions. A body implant mask for implanting dopants for the transistor body is also used as an etch mask for forming the vertically oriented gate trenches in the dielectric liners. | 04-09-2015 |
20150102402 | SEMICONDUCTOR COMPONENT AND MANUFACTURING METHOD THEREOF - A semiconductor component includes: a semiconductor substrate; and a semiconductor device provided thereon, the device being a field-effect transistor that includes: a gate insulating film provided on the substrate; a gate electrode provided via the film; and a pair of source-drain regions provided to sandwich the electrode, the substrate including a patterned surface in a portion where the electrode is provided, the patterned surface of the substrate including a raised portion where the film is formed to cover a surface that lies on the same plane as a surface of the pair of source-drain regions, and the electrode is formed on a top surface of the film, and the patterned surface of the substrate including a recessed portion where the film is formed to cover surfaces of a groove formed toward the interior than the surface of the pair of source-drain regions, and the electrode is formed so as to fill the groove provided with the film. | 04-16-2015 |
20150108565 | Power Semiconductor Devices, Structures, and Related Methods - Power semiconductor devices, and related methods, where majority carrier flow is divided into paralleled flows through two drift regions of opposite conductivity types. | 04-23-2015 |
20150108566 | Semiconductor Device Comprising a Transistor Gate Having Multiple Vertically Oriented Sidewalls - A method used in fabrication of a recessed access device transistor gate has increased tolerance for mask misalignment. One embodiment of the invention comprises forming a vertical spacing layer over a semiconductor wafer, then etching the vertical spacing layer and the semiconductor wafer to form a recess in the wafer. A conductive transistor gate layer is then formed within the trench and over the vertical spacing layer. The transistor gate layer is etched, which exposes the vertical spacing layer. A spacer layer is formed over the etched conductive gate layer and over the vertical spacing layer, then the spacer layer and the vertical spacing layer are anisotropically etched. Subsequent to anisotropically etching the vertical spacing layer, a portion of the vertical spacing layer is interposed between the semiconductor wafer and the etched conductive transistor gate layer in a direction perpendicular to the plane of a major surface of the semiconductor wafer. | 04-23-2015 |
20150108567 | METHOD OF FORMING STACKED TRENCH CONTACTS AND STRUCTURES FORMED THEREBY - Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a structure comprising a first contact metal disposed on a source/drain contact of a substrate, and a second contact metal disposed on a top surface of the first contact metal, wherein the second contact metal is disposed within an IID disposed on a top surface of a metal gate disposed on the substrate. | 04-23-2015 |
20150115352 | SEMICONDUCTOR DEVICE - The present disclosure relates to a semiconductor device. Such a semiconductor device includes a trench metal-oxide-semiconductor (MOS) transistor having two or more electrodes in a trench formed on a substrate of the semiconductor, where a part of a shield electrode positioned at a bottom of the trench is formed to have a large thickness, and a groove is formed in a gate electrode that is stacked on the shield electrode, such that a part of the shield electrode protrudes to a surface of the semiconductor device so as to be connected with a source power. | 04-30-2015 |
20150115353 | FIELD EFFECT SEMICONDUCTOR COMPONENT AND METHOD FOR PRODUCING IT - What is provided is a field effect component including a semiconductor body, which extends in an edge zone from a rear side as far as a top side and which includes a semiconductor mesa, which extends in a vertical direction, which is perpendicular to the rear side and/or the top side. The semiconductor body in a vertical cross section further includes a drift region, which extends at least in the edge region as far as the top side and which is arranged partly in the semiconductor mesa, and a body region, which is arranged at least partly in the semiconductor mesa and which forms a pn junction with the drift region. The pn junction extends between two sidewalls of the semiconductor mesa. | 04-30-2015 |
20150115354 | Semiconductor Device - The present disclosure provides a semiconductor device, which includes a compensation area which includes p-regions and n-regions, and a plurality of transistor cells on the compensation area. Each of the plurality of transistor cells includes a source region, a body region, a gate and an interlayer dielectric, and a source metallization layer arranged on the interlayer dielectric. The semiconductor device further includes an additional n-doping region that is provided on top of the n-regions between two neighboring body regions, and a source plug which fills a contact hole formed through the interlayer dielectric between the source and body region and the source metallization layer, so as to electrically connect the source and body region and the source metallization layer. | 04-30-2015 |
20150123195 | RECESSED CHANNEL ACCESS TRANSISTOR DEVICE AND FABRICATION METHOD THEREOF - A recessed channel access transistor device is provided. A semiconductor substrate having thereon a trench is provided. The trench extends from a main surface of the semiconductor substrate to a predetermined depth. A buried gate electrode is disposed at a lower portion of the trench. A gate oxide layer is formed between the buried gate electrode and the semiconductor substrate. A drain doping region on a first side (cell side) of the trench in the semiconductor substrate and a source doping region on a second side (digit side) of the trench are formed. The source doping region has a junction depth that is deeper than that of the drain doping region. An L-shaped channel is defined along a sidewall surface on the first side and along a bottom surface of the trench between the drain doping region and the source doping region. | 05-07-2015 |
20150129956 | METHOD TO MANUFACTURE SHORT CHANNEL TRENCH MOSFET - Aspects of the present disclosure describe a trench MOSFET with a channel length that may be controlled by counterdoping the body-drain junction to form a straggle region adjacent to the trenches. The channel length is defined between the straggle region at the bottom and a source region at the top. Both of the straggle region and the source region are of the same conductivity type though they may be different ion species. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. | 05-14-2015 |
20150129957 | SEMICONDUCTOR DEVICE - A trench structure which is capable of promoting extension of a depletion layer and hardly causes thermal stress is provided. A semiconductor device includes a semiconductor substrate. A plurality of loop trenches is formed on the surface of the semiconductor substrate. Each loop trench is configured to extend so as to surround a region smaller than the region where a plurality of gate trenches is formed. Each loop trench is separated from other loop trenches. A second insulating layer is located in each loop trench. P-type fourth regions are formed in the semiconductor substrate. Each fourth region is in contact with a bottom surface of corresponding one of the loop trenches and is configured to extend along the corresponding one of the loop trenches. | 05-14-2015 |
20150137220 | FIELD EFFECT TRANSISTOR, TERMINATION STRUCTURE AND ASSOCIATED METHOD FOR MANUFATURING - The present disclosure discloses a field effect transistor (“FET”), a termination structure and associated method for manufacturing. The termination structure for the FET includes a plurality of termination cells arranged substantially in parallel from an inner side toward an outer side of a termination area of the FET. Each of the termination cells comprises a termination trench and a guard ring region located underneath the bottom of the termination trench in the semiconductor layer. Each termination trench is lined with a termination insulation layer, and is filled with a first conductive spacer and a second conductive spacer respectively against an inner sidewall and an outer sidewall of the termination trench and spaced apart from each other with a space, and a dielectric layer filling the space between the first and the second spacers. | 05-21-2015 |
20150137221 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device includes: a substrate with an off-angle; an SiC layer provided on a principal surface of the substrate, including an n type drift region, and having a trench whose bottom is located in the drift region; and a gate electrode provided in the trench in the SiC layer. In the trench in the SiC layer, a first angle formed by at least part of a first sidewall on an off-direction side and the principal surface of the substrate is an obtuse angle, and a second angle formed by at least part of a second sidewall opposite to the first sidewall and the principal surface of the substrate is an acute angle, in a cross section parallel to a direction of a normal line to the principal surface of the substrate and a direction of a c-axis of the substrate. | 05-21-2015 |
20150137222 | Stress-Reduced Field-Effect Semiconductor Device and Method for Forming Therefor - A field-effect semiconductor device is provided. The field-effect semiconductor device includes a semiconductor body with a first surface defining a vertical direction. In a vertical cross-section the field-effect semiconductor device further includes a vertical trench extending from the first surface into the semiconductor body and comprising a field electrode, a cavity at least partly surrounded by the field electrode, and an insulation structure substantially surrounding at least the field electrode. An interface between the insulation structure and the surrounding semiconductor body is under tensile stress and the cavity is filled or unfilled so as to counteract the tensile stress. | 05-21-2015 |
20150145026 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A semiconductor device including a substrate having an active region and a field-plate region therein is disclosed. At least one trench-gate structure is in the substrate. The field-plate region is at a first side of the trench-gate structure. At least one source doped region is in the substrate at a second side opposite to the first side of the trench-gate structure. The source doped region adjoins the sidewall of the trench-gate structure. A drain doped region is in the substrate corresponding to the active region. The field-plate region is between the drain doped region and the trench-gate structure. An extending direction of length of the trench-gate structure is perpendicular to that of the drain doped region as viewed from a top-view perspective. | 05-28-2015 |
20150145027 | METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device is provided according to one embodiment of the present invention and includes forming an interlayer dielectric on a substrate; forming a trench surrounded by the interlayer dielectric; depositing a dielectric layer and a work function layer on a surface of the trench sequentially and conformally; filling up the trench with a conductive layer; removing an upper portion of the conductive layer inside the trench; forming a protection film on a top surface of the interlayer dielectric and a top surface of the conductive layer through a directional deposition process; removing the dielectric layer exposed from the protection film; and forming a hard mask to cover the protection film. | 05-28-2015 |
20150145028 | Semiconductor Device with Cell Trench Structures and Contacts and Method of Manufacturing a Semiconductor Device - A semiconductor mesa is formed in a semiconductor layer between a first cell trench structure and a second cell trench structure extending from a first surface into the semiconductor layer. An opening is formed in a capping layer formed on the first surface, wherein the opening exposes at least a portion of the semiconductor mesa. Through the opening impurities of a first conductivity type are introduced into the exposed portion of the semiconductor mesa. A recess defined by the opening is formed. | 05-28-2015 |
20150295028 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - A semiconductor device has a deep layer with a higher impurity concentration than that of a super junction structure. The deep layer is formed from a position deeper from a surface of a semiconductor layer by a predetermined depth, and comes in contact with a high impurity layer and also comes in contact with the super junction structure. The deep layer overlaps with a portion between a first end which is an outermost peripheral side of a portion that comes in contact with the high impurity layer in a front surface electrode and an end on an outer peripheral side in the high impurity layer when viewed from a substrate normal direction. | 10-15-2015 |
20150295032 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device is disclosed. The semiconductor device includes a substrate having an isolation region and an active region defined by the isolation region. At least one trench is formed in the active region and extends along a first direction. A gate layer is disposed on the active region and extends along a second direction, wherein the gate layer conformably fills the at least one trench and covers a bottom surface and sidewalls of the at least one trench. The disclosure also provides a method for manufacturing the semiconductor device. | 10-15-2015 |
20150295066 | PROCESS FOR PRODUCING FET TRANSISTORS - A method of production of a field-effect transistor from a stack of layers forming a semiconductor-on-insulator type substrate, the stack including a superficial layer of an initial thickness, made of a crystalline semiconductor material and covered with a protective layer, the method including: defining, by photolithography, a gate pattern in the protective layer; etching the gate pattern into the superficial layer to leave a thickness of the layer of semiconductor material in place, the thickness defining a height of a conduction channel of the field-effect transistor; forming a gate in the gate pattern; forming, in the superficial layer and on either side of the gate, source and drain zones, while preserving, in the zones, the initial thickness of the superficial layer. | 10-15-2015 |
20150295079 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - [Problem] To provide a semiconductor device wherein withstand voltage of a gate insulating film at the upper edge of a trench is improved, and a method for manufacturing the semiconductor device. | 10-15-2015 |
20150295080 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A split gate trench field effect transistor includes a gate electrode formed in a trench. A shield gate is formed in a trench below the gate electrode and surrounded by an insulating structure to float the shield electrode. | 10-15-2015 |
20150295083 | LATERAL DEVICES CONTAINING PERMANENT CHARGE - A lateral device includes a gate region connected to a drain region by a drift layer. An insulation region adjoins the drift layer between the gate region and the drain region. Permanent charges are embedded in the insulation region, sufficient to cause inversion in the insulation region. | 10-15-2015 |
20150303294 | VERTICAL SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING THE VERTICAL SEMICONDUCTOR DEVICE - Aspects of the invention are directed to a vertical semiconductor device including an element active portion and a voltage withstanding structure portion has a first main electrode and a gate pad electrode on a first main surface of the element active portion, includes first parallel pn layers in a drift layer below the first main electrode, and includes second parallel pn layers below the gate pad electrode. The vertical semiconductor device includes a first conductivity type isolation region between the second parallel pn layers below the gate pad electrode and a p-type well region disposed in a surface layer of the drift layer, and by the repetition pitch of the second parallel pn layers being shorter than the repetition pitch of the first parallel pn layers, it is possible to obtain low on-state resistance, high avalanche withstand, high turn-off withstand, and high reverse recovery withstand. | 10-22-2015 |
20150311282 | Super Junction Semiconductor Device Including Edge Termination - A super junction semiconductor device includes a super junction structure and a channel stopper structure. The super junction structure includes first and second areas alternately arranged along a first lateral direction and extending in parallel along a second lateral direction. Each one of the first areas includes a first semiconductor region of a first conductivity type. Each one of the second areas includes, along the first lateral direction, an inner area between opposite second semiconductor regions of a second conductivity type opposite to the first conductivity type. The channel stopper structure includes a doped semiconductor region electrically coupled to a field plate. The second semiconductor regions extend along the second lateral direction from the transistor cell area through the edge termination area overlap with the field plate. | 10-29-2015 |
20150318365 | TRANSISTOR DEVICE AND RELATED MANUFACTURING METHOD - A transistor device may include a substrate that has a recess and a substrate surface, wherein the recess is recessed with respect to the substrate surface. The transistor device may further include a source and a drain that overlap the substrate. The transistor device may further include a gate structure that has a first gate structure portion and a second gate structure portion, wherein the first gate structure portion is positioned inside the recess, and wherein the second gate structure portion is connected to the first gate structure and is positioned outside the first recess. | 11-05-2015 |
20150325641 | Super Junction Semiconductor Device having Strip Structures in a Cell Area - A super junction semiconductor device includes a semiconductor portion having strip structures in a cell area. Each strip structure has a compensation structure with first and second sections inversely provided on opposite sides of a fill structure. Each section has first and second compensation layers of complementary conductivity types. The strip structures are linear stripes extending through the cell area in a first lateral direction and into an edge area surrounding the cell area in lateral directions. Each strip structure has an end section with a termination portion in the edge area in which the first compensation layer of the first section is connected with the first compensation layer of the second section via a first conductivity layer, and the second compensation layer of the first section is connected with the second compensation layer of the second section via a second conductivity layer. | 11-12-2015 |
20150325685 | Power Semiconductor Device with Low RDSON and High Breakdown Voltage - A semiconductor structure is disclosed. The semiconductor structure includes a trench having substantially parallel trench sidewalls, and a tapered dielectric liner in the trench. The tapered dielectric liner includes slanted dielectric sidewalls. A conductive filler is enclosed by the slanted dielectric sidewalls in the trench. | 11-12-2015 |
20150325696 | SEMICONDUCTOR DEVICE - A semiconductor device including a first conductor layer, a second conductor layer formed over the first conductor layer, a third conductor layer formed over the second conductor layer, a gate trench which passes through the third conductor layer and is formed in the second conductor layer, a first insulating film formed on an inner wall of the gate trench, a second insulating film formed on the inner wall of the gate trench, a first buried conductor layer formed in the gate trench, a gate electrode formed in the gate trench, a fourth conductor layer of the second conductivity type formed on a lower end of the first buried conductor layer and a lower end of the gate trench, and a fifth conduction layer of the first conductivity type formed over the third conductor layer. The first insulating film is thicker than the second insulating film. | 11-12-2015 |
20150333137 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device according to the present invention includes a semiconductor layer provided with a gate trench, a first conductivity type source region formed to be exposed on a surface side of the semiconductor layer, a second conductivity type channel region formed on a side of the source region closer to a back surface of the semiconductor layer to be in contact with the source region, a first conductivity type drain region formed on a side of the channel region closer to the back surface of the semiconductor layer to be in contact with the channel region, a gate insulating film formed on an inner surface of the gate trench, and a gate electrode embedded inside the gate insulating film in the gate trench, while the channel region includes a channel portion formed along the side surface of the gate trench so that a channel is formed in operation and a projection projecting from an end portion of the channel portion closer to the back surface of the semiconductor layer toward the back surface. | 11-19-2015 |
20150333140 | SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME - A semiconductor structure is provided. An N-type epitaxial layer is disposed on an N-type substrate. The N-type epitaxial layer has at least one trench therein, wherein the trench has a straight sidewall. A first insulating layer is disposed on at least a portion of a surface of the trench. A silicon-containing layer is disposed in a lower portion of the trench and has at least one air gap therein. A first conductive layer is disposed in an upper portion of the trench. Two P-type well regions are disposed in the N-type epitaxial layer beside the trench. Two N-type source regions are respectively disposed in the P-type well regions beside the trench. | 11-19-2015 |
20150333176 | TRENCH DMOS DEVICE AND MANUFACTURING METHOD THEREOF - A trench-type DMOS device and a manufacturing method thereof are provided. The DMOS device includes: a substrate ( | 11-19-2015 |
20150340453 | SEMICONDUCTOR DEVICE HAVING BURIED GATE STRUCTURE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes a device isolation region defining an active region in a substrate, and gate structures buried in the active region of the substrate. At least one of the gate structures includes a gate trench, a gate insulating layer conformally formed on an inner wall of the gate trench, a gate barrier pattern conformally formed on the gate insulating layer disposed on a lower portion of the gate trench, a gate electrode pattern formed on the gate barrier pattern and filling the lower portion of the gate trench, an electrode protection layer conformally formed on the gate insulating layer disposed on an upper portion of the gate trench to be in contact with the gate barrier pattern and the gate electrode pattern, a buffer oxide layer conformally formed on the electrode protection layer, and a gate capping insulating layer formed on the buffer oxide layer to fill the upper portion of the gate trench. | 11-26-2015 |
20150340454 | DEVICE ARCHITECTURE AND METHOD FOR IMPROVED PACKING OF VERTICAL FIELD EFFECT DEVICES - A semiconductor field-effect device is disclosed that utilizes an octagonal or inverse-octagonal deep trench super-junction in combination with an octagonal or inverse-octagonal gate trench. The field-effect device achieves improved packing density, improved current density, and improved on resistance, while at the same time maintaining compatibility with the multiple-of-45°-angles of native photomask processing and having well characterized (010), (100) and (110) (and their equivalent) silicon sidewall surfaces for selective epitaxial refill and gate oxidation, resulting in improved scalability. By varying the relative length of each sidewall surface, devices with differing threshold voltages can be achieved without additional processing steps. Mixing trenches with varying sidewall lengths also allows for stress balancing during selective epitaxial refill. | 11-26-2015 |
20150340464 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device manufacturing method includes forming a gate opening in a semiconductor layer; forming a sacrificial gate in the gate opening; forming a source region and a drain region in the semiconductor layer in proximity to the gate opening; removing the sacrificial gate; and forming a gate stack comprising a replacement gate dielectric layer and a replacement gate conductor layer in the gate opening, wherein the gate opening is configured to define a thickness of a portion of the semiconductor layer for a channel region. Channel control in semiconductor devices formed according to the above method can be effectively improved. | 11-26-2015 |
20150340494 | TRENCH POWER METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR AND EDGE TERMINAL STRUCTURE - An edge terminal structure of a trench power semiconductor device includes a first conductive-type substrate, a first conductive-type epitaxial layer thereon, a first electrode on a surface of the first conductive-type epitaxial layer, a second electrode on a back of the first conductive-type substrate, a first and a second field plates. The trench power semiconductor device includes an active area and an edge terminal area. A trench is in the surface of the first conductive-type epitaxial layer. The first field plate includes an L-shaped electric-plate, a gate insulation layer below the L-shaped electric-plate, and the first electrode on the L-shaped electric-plate. The second field plate includes a portion of the first electrode and an insulation layer between the portion of the first electrode and the first conductive-type epitaxial layer. The insulation layer covers the tail of the trench and completely covers the L-shaped electric-plate. | 11-26-2015 |
20150349072 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREFOR - A semiconductor electronic device structure includes a substrate having a trench disposed therein, a gate electrode disposed in the trench, and a gate dielectric layer disposed on the surface in the trench. The substrate and the gate electrode are electrically insulated from each other by the gate dielectric layer. The substrate further has a pair of doped areas. The doped areas each are vertically disposed along the two respective lateral sides of the trench. The doped areas each have a first portion and a second portion arranged atop the first portion. The first portion extends vertically to the portion of the substrate that is aligned to the gate electrode. The lateral dimension of the first portion is smaller than the lateral dimension of the second portion, and the doping concentration of the first portion is lighter than the doping concentration of the second portion. | 12-03-2015 |
20150349073 | DUAL WORK FUNCTION BURIED GATE-TYPE TRANSISTOR, METHOD FOR FORMING THE SAME, AND ELECTRONIC DEVICE INCLUDING THE SAME - A transistor includes: a source region and a drain region that are formed in a substrate to be spaced apart from each other; a trench formed in the substrate between the source region and the drain region; and a buried gate electrode inside the trench, wherein the buried gate electrode includes: a lower buried portion which includes a high work-function barrier layer including an aluminum-containing titanium nitride, and a first low-resistivity layer disposed over the high work-function barrier layer; and an upper buried portion which includes a low work-function barrier layer disposed over the lower buried portion and overlapping with the source region and the drain region, and a second low-resistivity layer disposed over the low work-function barrier layer. | 12-03-2015 |
20150349111 | SEMICONDUCTOR DEVICE - A semiconductor device includes a drift region of a first conductivity type, a channel forming region of a second conductivity type that is selectively provided in a first main surface of the drift region, a first main electrode region of the first conductivity type that is selectively provided in an upper part of the channel forming region, a second main electrode region of the second conductivity type that is provided in a second main surface of the drift region, and a high-concentration region of the first conductivity type that is provided in a portion of the drift region below the channel forming region so as to be separated from the channel forming region. The high-concentration region has a higher impurity concentration than the drift region and the total amount of first-conductivity-type impurities in the high-concentration region is equal to or less than 2.0×10 | 12-03-2015 |
20150349112 | TRENCH MOSFET HAVING REDUCED GATE CHARGE - A trench MOSFET device includes a semiconductor layer of a first doping type. MOS transistor cells are in a body region of a second doping type in the semiconductor layer. The transistor cells include a first cell type including a first trench providing a first gate electrode or the first gate electrode is on the semiconductor surface between the first trench and a second trench, and a first source region is formed in the body region. The first gate electrode is electrically isolated from the first source region. A second cell type has a third trench providing a second gate electrode or the second gate electrode is on the semiconductor surface between the third trench and a fourth trench, and a second source region is in the body region. An electrically conductive member directly connects the second gate electrode, first source region and second source region together. | 12-03-2015 |
20150349114 | SEMICONDUCTOR DEVICE - In a semiconductor device provided with a MOSFET part and a gate pad part, the gate pad part includes: a low resistance semiconductor layer; a drift layer; a poly-silicon layer constituting a conductor layer and a gate pad electrode formed above the drift layer over the whole area of the gate pad part with a field insulation layer interposed therebetween; and a gate oscillation suppressing structure, wherein the gate oscillation suppressing structure includes a p | 12-03-2015 |
20150349116 | Semiconductor Device Having an Active Trench and a Body Trench - A semiconductor substrate having a first main surface and a transistor cell includes a drift region, a body region between the drift region and the first main surface, an active trench at the first main surface extending into the drift region, a gate insulating layer at sidewalls and a bottom side of the active trench, a gate conductive layer in the active trench, a source region in the body region, and adjacent to the active trench, a body trench at the first main surface extending into the drift region, the body trench being adjacent to the body region and to the drift region, an insulating layer at sidewalls and at a bottom side of the body trench, the insulating layer being asymmetric with respect to an axis extending perpendicular to the first main surface at a center of the body trench, and a conductive layer in the body trench. | 12-03-2015 |
20150371991 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - One semiconductor device includes an active region on a semiconductor substrate, a trench having a lower section and an upper section within the active region, a gate insulating film that covers the inner wall surface of the trench, a first barrier metal that covers the lower section of the trench interposed by the gate insulating film, a second barrier metal that covers the first barrier metal, and a metal electrode that covers the second barrier metal and fills up the lower section of the trench. The second barrier metal is thinner than the first barrier metal. | 12-24-2015 |
20150372131 | CHARGED BALANCED DEVICES WITH SHIELDED GATE TRENCH - This invention discloses a semiconductor power device disposed on a semiconductor substrate includes a plurality of deep trenches with an epitaxial layer filling said deep trenches and a simultaneously grown top epitaxial layer covering areas above a top surface of said deep trenches over the semiconductor substrate. A plurality of trench MOSFET cells disposed in said top epitaxial layer with the top epitaxial layer functioning as the body region and the semiconductor substrate acting as the drain region whereby a super junction effect is achieved through charge balance between the epitaxial layer in the deep trenches and regions in the semiconductor substrate laterally adjacent to the deep trenches. Each of the trench MOSFET cells further includes a trench gate and a gate-shielding dopant region disposed below and substantially aligned with each of the trench gates for each of the trench MOSFET cells for shielding the trench gate during a voltage breakdown. | 12-24-2015 |
20150372133 | METHOD TO MANUFACTURE SHORT CHANNEL TRENCH MOSFET - Aspects of the present disclosure describe a trench MOSFET with a channel length that may be controlled by counterdoping the body-drain junction to form a straggle region adjacent to the trenches. The channel length is defined between the straggle region at the bottom and a source region at the top. Both of the straggle region and the source region are of the same conductivity type though they may be different ion species. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. | 12-24-2015 |
20160005837 | Field Effect Transistor Devices with Buried Well Protection Regions - A method of forming a transistor device includes providing a drift layer having a first conductivity type, forming a first region in the drift layer, the first region having a second conductivity type that is opposite the first conductivity type, forming a body layer on the drift layer including the first region, forming a source layer on the body layer, forming a trench in the source layer and the body layer above the first region and extending into the first region, forming a gate insulator on the inner sidewall of the trench, and forming a gate contact on the gate insulator. | 01-07-2016 |
20160005857 | SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device (A | 01-07-2016 |
20160013280 | Semiconductor Device Comprising a Field Electrode | 01-14-2016 |
20160020288 | INSULATED GATE SEMICONDUCTOR DEVICE HAVING A SHIELD ELECTRODE STRUCTURE - A semiconductor device includes a semiconductor region with a charge balance region on a junction blocking region, which has a lower doping concentration. A trench structure having an insulated shield electrode and an insulated gate electrode is provided in the semiconductor region. The semiconductor device further includes one or more features configured to improve operating performance. The features include terminating the trench structure in the junction blocking region, providing a localized doped region adjoining a lower surface of a body region and spaced apart from the trench structure, disposing a notch proximate to the lower surface of the body region, and/or configuring the insulated shield electrode to have a wide portion adjoining a narrow portion. | 01-21-2016 |
20160020290 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a first semiconductor region of a first conductivity type, a first control electrode, a first electrode, a second control electrode, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, and a first insulating film. The first control electrode is provided on or above the first semiconductor region. The first electrode is provided on the first control electrode. The second control electrode is provided on or above the first semiconductor region and includes a first portion which is beside the first control electrode and a second portion which is provided on the first portion and beside the first electrode. The second semiconductor region is provided on the first semiconductor region. A boundary between the first semiconductor region and the second semiconductor region is above the lower end of the first electrode. | 01-21-2016 |
20160020291 | FABRICATION OF SHIELDED GATE TRENCH MOSFET WITH INCREASED SOURCE-METAL CONTACT - A semiconductor device formed on a semiconductor substrate having a substrate top surface, comprising: a gate trench extending from the substrate top surface into the semiconductor substrate; a gate electrode in the gate trench; a gate top dielectric material disposed over the gate electrode; a body region adjacent to the gate trench; a source region embedded in the body region; a metal layer disposed over at least a portion of a gate trench opening and at least a portion of the source region, wherein: the source region has a curved sidewall portion that is adjacent to the gate trench, and that extends above the gate top dielectric material. | 01-21-2016 |
20160020315 | Semiconductor Device Comprising a Plurality of Transistor Cells and Manufacturing Method - A semiconductor device comprises a plurality of transistor cells. Each one of the plurality of transistor cells comprises a trench extending into a drift zone of a semiconductor body from a first surface, the drift zone being of a first conductivity type. The semiconductor device further comprises a gate electrode structure. A field electrode structure and a first dielectric structure are in the trench. A doped region is embedded in the drift zone lining a bottom side of the trench. The doped region is one of a first conductivity type having a doping concentration lower than the drift zone, and a second conductivity type complementary to the first conductivity type. | 01-21-2016 |
20160027785 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - One semiconductor device includes a semiconductor substrate having a plurality of first trenches formed to extend in the first direction, an embedded gate electrode embedded in a lower part of each of the first trenches with a gate insulating film there between, an embedded insulating film embedded in each of the first trenches, said embedded insulating film being on the embedded gate electrode, an isolating insulating film, which is provided on the embedded insulating film, and which has a width smaller than that of the first trenches, a diffusion region that is provided on the semiconductor substrate by being adjacent to the first trenches, a conductive layer in contact with the diffusion region, and a contact plug in contact with the conductive layer. The conductive layer is disposed also on the embedded insulating film on the embedded gate electrode, and is partitioned by means of the isolating insulating film. | 01-28-2016 |
20160027881 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - Disclosed herein is a semiconductor device which includes a semiconductor substrate and a trench gate. The semiconductor substrate includes a drift layer, a body layer, and a first semiconductor layer provided on a part of a front surface of the body layer. The trench gate extends from a front surface of the semiconductor substrate to reach the drift layer. The trench gate includes a gate insulating film and a gate electrode. The inner wall of the trench, which is located at a depth where the inner wall makes contact with the body layer, is a crystal plane. A width of the trench in a transverse direction includes a width located at the front surface of the semiconductor substrate that is narrower than a width located at a depth from a lower end of the first semiconductor layer to a lower end of the body layer. | 01-28-2016 |
20160027912 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type. The second semiconductor region is adjacent to the first semiconductor region in a first direction. A third semiconductor region of the first conductivity type is adjacent to the second semiconductor region in the first direction. A first electrode is in contact with the first semiconductor region, the second semiconductor region, and the third semiconductor region via a first insulating film. A second electrode is directly adjacent to the third semiconductor region in the first direction. And a third electrode has a plurality of first connection regions that each extend along the first direction from a top surface of the first semiconductor region into the first semiconductor region. The third electrode is in contact with the first semiconductor region and spaced apart from the second electrode. | 01-28-2016 |
20160027916 | SEMICONDUCTOR DEVICE WITH GATE ELECTRODES BURIED IN TRENCHES - Trenches are formed in a base layer and extend parallel to each other. A gate insulating film is formed on the inner wall of each of multiple trenches. A gate electrode GE is buried in each of the trenches. The source layer is formed in the base layer to a depth less than the base layer. The source layer is disposed between each of the trenches. A second conduction type high concentration layer is formed between the source layer and the trench in a plan view. The trench, the source layer, and the second conduction type high concentration are arranged in this order repetitively in a plan view. One lateral side of the trench faces the source layer and the other lateral side of the trench faces the second conduction type high concentration layer. | 01-28-2016 |
20160035840 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a first semiconductor layer, a second semiconductor layer provided in a portion on the first semiconductor layer, a first insulating layer provided on the first semiconductor layer on a terminal region side of the second semiconductor layer, a third semiconductor layer provided on the first semiconductor layer on the terminal region side of the first insulating layer, a second insulating layer provided on the first semiconductor layer on the terminal region side of the third semiconductor layer, a fourth semiconductor layer provided between the first semiconductor layer and the second insulating layer, and a plurality of field plate electrodes provided inside an inter-layer insulating film, the plurality of field plate electrodes having mutually-different distances from the first semiconductor layer. | 02-04-2016 |
20160035844 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device with enhanced reliability in which a gate electrode for a trench-gate field effect transistor is formed through a gate insulating film in a trench made in a semiconductor substrate. The upper surface of the gate electrode is in a lower position than the upper surface of the semiconductor substrate in an area adjacent to the trench. A sidewall insulating film is formed over the gate electrode and over the sidewall of the trench. The gate electrode and the sidewall insulating film are covered by an insulating film as an interlayer insulating film. | 02-04-2016 |
20160035845 | Vertical Semiconductor Device having Semiconductor Mesas with Side Walls and a PN-Junction Extending between the Side Walls - A vertical semiconductor device includes a semiconductor body having a backside and extending, in a peripheral area and in a vertical direction substantially perpendicular to the backside, from the backside to a first surface of the semiconductor body, the body including in an active area spaced apart semiconductor mesas extending, in the vertical direction, from the first surface to a main surface arranged above the first surface, in a vertical cross-section the peripheral area extending between the active area and an edge that extends between the back-side and the first surface, in the vertical cross-section each of the mesas including first and second side walls, a first pn-junction extending between the first and second side walls, and a conductive region in Ohmic contact with the mesa and extending from the main surface into the mesa. Gate electrodes are arranged between adjacent mesas and extend across the first pn-junctions. | 02-04-2016 |
20160035882 | MULTIPLE SEMICONDUCTOR DEVICE TRENCHES PER CELL PITCH - A semiconductor device includes a plurality of field plate trenches formed in a semiconductor substrate, a plurality of gate trenches formed in the semiconductor substrate and spaced apart from the field plate trenches, and a plurality of device cells having a cell pitch defined by a distance from one side of a field plate trench to the same side of an adjacent field plate trench. Each device cell includes a first doped region of a first conductivity type and a second doped region of a second conductivity type adjacent the first doped region in a part of the semiconductor substrate disposed between the adjacent field plate trenches that define the cell pitch. At least some of the device cells have more than one gate trench per cell pitch. | 02-04-2016 |
20160043166 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a vertical trench gate element portion and a lateral n-channel element portion for control which includes a well diffusion region, and a junction edge termination region which surrounds the vertical trench gate element portion and the lateral n-channel element portion for control. The junction edge termination region includes an oxide layer, a sustain region in contact with a trench provided at the end, and a diffusion region in contact with the sustain region. The diffusion region is deeper than the base region and has low concentration. The sustain region is shallower than the diffusion region and has high concentration. The well diffusion region is deeper than the base region and the sustain region and has low concentration. The breakdown voltage of the junction edge termination region and the well diffusion region is higher than that of the vertical trench gate element portion. | 02-11-2016 |
20160043171 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device. The semiconductor device includes an isolation region disposed in a semiconductor substrate and configured to define an active region. A gate electrode buried in the active region is disposed. A gate dielectric layer is disposed between the active region and the gate electrode. A first source/drain region and a second source/drain region are disposed in the active region on both sides of the gate electrodes. An interconnection structure intersecting with the gate electrode, overlapping the first and second source/drain regions, electrically connected with the first source/drain region, and spaced apart from the second source/drain region is disposed. A contact structure is disposed on the second source/drain region. | 02-11-2016 |
20160043192 | METHOD OF FORMING SGT MOSFETS WITH IMPROVED TERMINATION BREAKDOWN VOLTAGE - A method of manufacturing a trench power MOSFET device with improved UIS performance and a high avalanche breakdown voltage is disclosed. The method includes performing a first etching of the epitaxial layer to form an active trench with an initial depth in an active area of the semiconductor substrate and a termination trench with a desired depth in a termination area of the semiconductor substrate, wherein the initial depth of the active trench is smaller than the desired depth of the termination trench and performing a second etching to increase the depth of the active trench to a desired depth wherein a depth difference between the desired depth of the active trench and the desired depth of the termination trench is smaller than a depth difference between the initial depth of the active trench and the desired depth of the termination trench. | 02-11-2016 |
20160043214 | SEMICONDUCTOR DEVICE - A first lower insulating film (LIL | 02-11-2016 |
20160049486 | Semiconductor Device Having a Tapered Gate Structure and Method - A semiconductor device includes a semiconductor body having a first surface vertically spaced apart from a second surface. A first trench vertically extends into the semiconductor body from the first surface and includes first and second sidewalls extending across the semiconductor body in a lateral direction that is parallel to the first surface. A field electrode is arranged in first trench and electrically insulated from the semiconductor body by a field dielectric. A first gate electrode is arranged in the first trench. The first gate electrode is electrically insulated from the field electrode by the field dielectric and is electrically insulated from the semiconductor body by a first gate oxide. The first gate electrode includes widened and tapered portions that are continuously connected and adjacent to one another in the lateral direction. The first gate oxide forms a non-perpendicular angle with the first sidewall in the lateral direction. | 02-18-2016 |
20160056137 | SEMICONDUCTOR CHIP AND ELECTRONIC COMPONENT - According to one embodiment, a semiconductor chip includes: a semiconductor layer; an upper electrode provided on the semiconductor layer; and a lower electrode provided under the semiconductor layer, the lower electrode being under an active region of the semiconductor layer, the lower electrode not being under a termination region of the semiconductor layer, an element being disposed in the active region, and the termination region being beside the active region. | 02-25-2016 |
20160056281 | EDGE TERMINATION FOR SUPER-JUNCTION MOSFETS - Edge termination for super-junction MOSFETs. In accordance with an embodiment of the present invention, a super-junction metal oxide semiconductor field effect transistor (MOSFET) includes a core super-junction region including a plurality of parallel core plates coupled to a source terminal of the super-junction MOSFET. The super-junction MOSFET also includes a termination region surrounding the core super-junction region comprising a plurality of separated floating termination segments configured to force breakdown into the core super-junction region and not in the termination region. Each termination segment has a length dimension less than a length dimension of the core plates. | 02-25-2016 |
20160056284 | RECTIFIER DIODE - A pseudo-Schottky diode has an n-channel trench MOSFET which includes: a cathode, an anode, and located between the cathode and the anode, the following elements: a highly n | 02-25-2016 |
20160064550 | INSULATED GATE TYPE SWITCHING DEVICE - An insulated gate type switching device includes: a first region being of a first conductivity type; a body region being of a second conductivity type and in contact with the first region; a second region being of the first conductivity type and separated from the first region by the body region; an insulating film being in contact with the first region, the body region and the second region; and a gate electrode facing the body region via the insulating film. The body region includes a first body region and a second body region. The first body region has a theoretical threshold level Vth larger than that of the second body region. | 03-03-2016 |
20160079350 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a first semiconductor region of a first conductivity type, an element region, a terminal region, and a second electrode. The element region includes a second semiconductor region of a second conductivity type, a third semiconductor region of the second conductivity type, a fourth semiconductor region of the first conductivity type, a gate electrode, and a first electrode. The terminal region includes a fifth semiconductor region of the second conductivity type, and a sixth semiconductor region of the second conductivity type. The terminal region surrounds the element region. The fifth semiconductor region is provided within the first semiconductor region. A plurality of the fifth semiconductor regions are provided along a second direction. The sixth semiconductor region is provided between the first semiconductor region and the fifth semiconductor region. A dopant of the sixth semiconductor region is higher than a dopant concentration of the fifth semiconductor region. | 03-17-2016 |
20160079351 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type provided in the first semiconductor region, an element region, and a termination region. The element region includes a third semiconductor region of the second conductivity type, a fourth semiconductor region of the first conductivity type, and a gate electrode disposed on a gate insulating layer that extends adjacent the third semiconductor region and the fourth semiconductor region. The termination region surrounds the element region and includes a first electrode, which includes first portions extending in a first direction and second portions extending in a second direction. A plurality of first electrodes are provided on the first semiconductor region and the second semiconductor region. An interval between adjacent first portions in the second direction is less than an interval between adjacent second portions in the first direction. | 03-17-2016 |
20160079374 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A manufacturing method of a semiconductor device includes forming a first electrode on a lower portion of a trench that is formed on a semiconductor layer and having a first insulating film between the first electrode and the semiconductor layer; forming a second insulating film that covers an inner surface of an upper portion of the trench, forming a resist film that extends into the upper portion of the trench on the second insulating film, removing the second insulating film between the resist film and a side wall of the trench to leave a portion of the second insulating film on the first electrode, forming a third insulating film on a side wall of an upper portion of the trench, and forming a second electrode on the first electrode in an inner portion of the second insulating film. | 03-17-2016 |
20160079375 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, the electrodes are provided in the first semiconductor layer and extend in a first direction. The gate electrodes are provided on the electrodes and extend in the first direction. The interconnection is provided outside ends in the first direction of the gate electrodes, extends in a second direction crossing the first direction, and is commonly connected to the electrodes. The gate contacts are provided on the gate electrodes and connected to the gate electrodes. | 03-17-2016 |
20160079386 | SEMICONDUCTOR WAFER, METHOD OF PRODUCING SEMICONDUCTOR WAFER AND ELECTRONIC DEVICE - To provide a semiconductor wafer having a wafer, a compound semiconductor layer, a first insulating layer and a second insulating layer, wherein in the depth direction, oxygen atoms and nitrogen atoms are continuously distributed, the number of the nitrogen atoms along the depth direction shows its maximum in the first insulating layer, the total number of third atoms and fourth atoms along the depth direction becomes the largest in the compound semiconductor layer, the number of the oxygen atoms at the interface between the compound semiconductor layer and the first insulating layer is smaller than the number of the oxygen atoms at the interface between the first insulating layer and the second insulating layer. | 03-17-2016 |
20160079412 | SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a first-conductive-type first semiconductor layer having a first surface and an opposing second surface. A first-conductive-type second semiconductor layer is on the first surface, and a second-conductive-type third semiconductor layer is on the second semiconductor layer. A first-conductive-type fourth semiconductor layer is on the third semiconductor layer. A first electrode is provided on the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer via an insulating film. A second electrode is on the fourth semiconductor layer. A third electrode is separated from the second electrode in a second direction. The third electrode has a width in the second direction, and the width of the third electrode narrows from a first depth to a second depth. An angle of the side surface of the second semiconductor layer is greater than or equal to 90 degrees. | 03-17-2016 |
20160079413 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a first electrode, a second electrode, a first semiconductor region of a first conductivity type between the first electrode and the second electrode, a plurality of second semiconductor regions of a second conductivity type selectively provided between the first semiconductor region and the second electrode, a third semiconductor region of the first conductivity type provided between each of the second semiconductor regions and the second electrode, an insulating film provided on the first semiconductor region in a location between adjacent second semiconductor regions, the second semiconductor regions, and the third semiconductor region; and a third electrode located over the insulating film, wherein a portion of the insulating film and the third electrode extend inwardly of the second semiconductor regions. | 03-17-2016 |
20160079414 | SOURCE AND BODY CONTACT STRUCTURE FOR TRENCH-DMOS DEVICES USING POLYSILICON - A semiconductor device includes a gate electrode, a top source region disposed next to the gate electrode, a drain region disposed below the bottom of the gate electrode, a dielectric disposed on top of the gate electrode, and a doped polysilicon spacer disposed on the source region and along a sidewall of the dielectric. Methods for manufacturing such device are also disclosed. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. | 03-17-2016 |
20160093706 | Method of Forming a Transistor, Method of Patterning a Substrate, and Transistor - A method of forming a transistor having a gate electrode includes forming a sacrificial layer over a semiconductor substrate, forming a patterning layer over the sacrificial layer, patterning the patterning layer to form patterned structures, forming spacers adjacent to sidewalls of the patterned structures, removing the patterned structures, etching through the sacrificial layer using the spacers as an etching mask and etching into the semiconductor substrate, thereby forming trenches in the semiconductor substrate, and filling a conductive material in the trenches in the semiconductor substrate to form the gate electrode. | 03-31-2016 |
20160093719 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor device includes: a first semiconductor region; a second semiconductor region selectively provided on the first semiconductor region; a third semiconductor region selectively provided on the second semiconductor region; a first electrode provided on the third semiconductor region and connected to the third semiconductor region; a second electrode electrically connected to the first semiconductor region; a third electrode provide via an insulating film on the first semiconductor region, the second semiconductor region, and the third semiconductor region; and a fourth electrode provided on the second electrode side of the third electrode, the fourth electrode being provided via the insulating film on the first semiconductor region. The insulating film has three or more regions between the fourth electrode and the first semiconductor region. Width of each of the regions in a direction crossing a direction from the third electrode toward the second electrode is different. | 03-31-2016 |
20160093728 | Semiconductor Device and Method of Manufacturing the Same - A semiconductor device comprises a semiconductor body. The semiconductor body comprises insulated gate field effect transistor cells. At least one of the insulated gate field effect transistor cells comprises a source zone of a first conductivity type, a body zone of a second, complementary conductivity type, a drift zone of the first conductivity type, and a trench gate structure extending into the semiconductor body through the body zone along a vertical direction. The trench gate structure comprises a gate electrode separated from the semiconductor body by a trench dielectric. The trench dielectric comprises a source dielectric part interposed between the gate electrode and the source zone and a gate dielectric part interposed between the gate electrode and the body zone. The ratio of a maximum thickness of the source dielectric part along a lateral direction and the minimum thickness of the gate dielectric part along the lateral direction is at least 1.5. | 03-31-2016 |
20160099314 | METHOD OF FORMING A SEMICONDUCTOR DEVICE AND STRUCTURE THEREFOR - In one embodiment, a method of forming an MOS transistor includes forming a threshold voltage (Vth) of the MOS transistor to have a first value at interior portions of the MOS transistor and a second value at other locations within the MOS transistor that are distal from the interior portion wherein the second value is less than the first value. | 04-07-2016 |
20160104783 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method for manufacturing the same are disclosed, which include a gate electrode material in a recess or a buried gate cell structure, a polysilicon material doped with impurities over a sidewall of a recess located over the gate electrode material, and a junction formed by an annealing or a rapid thermal annealing (RTA) process, thereby establishing a degree overlap between a gate electrode material of a buried gate and a junction. | 04-14-2016 |
20160104795 | SEMICONDUCTOR DEVICE - A semiconductor device includes a second conductivity type back gate electrode formed within a body area, and electrically connected with the body area, and performs bidirectional current control in a direction from a drain area to a source area and in a direction from the source area to the drain area. A sheet resistance of the back gate electrode is lower than a sheet resistance of the body area. The source area and the back gate electrode are disposed apart from each other with a clearance sufficient for preventing a breakdown phenomenon caused between the source area and the back gate electrode when a maximum operation voltage is applied between the source area and the drain area. | 04-14-2016 |
20160111488 | INTEGRATED CIRCUITS WITH LATERALLY DIFFUSED METAL OXIDE SEMICONDUCTOR STRUCTURES AND METHODS FOR FABRICATING THE SAME - Integrated circuits with improved laterally diffused metal oxide semiconductor (LDMOS) structures, and methods of fabricating the same, are provided. An exemplary LDMOS integrated circuit includes an n-type reduced surface field, a p-type body well disposed on a lateral side of the n-type reduced surface field region, a shallow trench isolation structure disposed within the n-type reduced surface field region, and a gate structure disposed partially over the p-type body well, partially over the n-type reduced surface field region, partially over the shallow trench isolation structure, and partially within the shallow trench isolation structure. | 04-21-2016 |
20160111490 | INSULATED GATE TYPE SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer. | 04-21-2016 |
20160111504 | Semiconductor Device and Method of Manufacturing a Semiconductor Device Using an Alignment Layer - First trenches extend from a process surface into a semiconductor layer. An alignment layer with mask pits in a with respect to the process surface vertical projection of the first trenches is formed on the process surface. Sidewalls of the mask pits have a smaller tilt angle with respect to the process surface than sidewalls of the first trenches. The mask pits are filled with an auxiliary material. A gate trench for a gate structure is formed in a mesa section of the semiconductor layer between the first trenches, wherein the auxiliary material is used as an etch mask. | 04-21-2016 |
20160111511 | TRANSISTOR WITH PERFORMANCE BOOST BY EPITAXIAL LAYER - The present disclosure relates to a transistor device. In some embodiments, the transistor device has an epitaxial layer disposed over a substrate. The epitaxial layer is arranged between a source region and a drain region separated along a first direction. Isolation structures are arranged on opposite sides of the epitaxial layer along a second direction, perpendicular to the first direction. A gate dielectric layer is disposed over the epitaxial layer, and a conductive gate electrode is disposed over the gate dielectric layer. The epitaxial layer overlying the substrate improves the surface roughness of the substrate, thereby improving transistor device performance. | 04-21-2016 |
20160118493 | SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device structure can include: (i) a first semiconductor layer having dopants of a first type; (ii) a second semiconductor layer having the dopants of the first type on the first semiconductor layer, where the second semiconductor layer is lightly-doped relative to the first semiconductor layer; (iii) first and second column regions spaced from each other in the second semiconductor layer, where the second column region is arranged between two of the first column regions; and (iv) first and second first sub-column regions laterally arranged in the second column region, where a doping concentration of the first sub-column region decreases in a direction from the first column region to the second sub-column region, and where a doping concentration of the second sub-column region decreases in a direction from the first column region to the first sub-column region. | 04-28-2016 |
20160118494 | MOS FIELD-EFFECT TRANSISTOR AND METHOD FOR THE PRODUCTION THEREOF - A substrate for a metal oxide semiconductor field effect transistor, and a metal oxide semiconductor field effect transistor, are made available. The substrate encompasses: an n-doped epitaxial drift zone, a p | 04-28-2016 |
20160126307 | SEMICONDUCTOR DEVICE HAVING SUPER JUNCTION STRUCTURE, METHOD FOR MANUFACTURING THE SAME AND METHOD FOR MANUFACTURING SUPER JUNCTION STRUCTURE - A semiconductor device having a super junction structure includes a substrate, an epitaxial layer of a first conductivity type, a plurality of pillars of a second conductivity type, a plurality of gate trenches, an insulating layer and a plurality of doped wells of the second conductivity type. The epitaxial layer of the first conductivity type is on the substrate. The pillars of the second conductivity type are in the epitaxial layer, in which the second conductivity type is opposite to the first conductivity type. The gate trenches are individually corresponding to and over the pillars. The insulating layer is in the gate trenches. The doped wells of the second conductivity type are in the epitaxial layer, in which each of the doped wells is between two adjacent gate trenches. A method for manufacturing the semiconductor device and a method for manufacturing a super junction structure are also provided. | 05-05-2016 |
20160133742 | SEMICONDUCTOR DEVICE HAVING TRENCH GATE STRUCTURE AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE - A semiconductor device of the present invention includes a semiconductor layer in which a gate trench is formed, a gate insulating film formed along an inner surface of the gate trench, a gate electrode that is buried in the gate trench through the gate insulating film and that has a lower electrode and an upper electrode that are separated upwardly and downwardly from each other with an intermediate insulating film between the lower electrode and the upper electrode, and a gate contact that is formed in the gate trench so as to pass through the upper electrode and through the intermediate insulating film and so as to reach the lower electrode and that electrically connects the lower electrode and the upper electrode together. | 05-12-2016 |
20160133743 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor layer made of first conductivity type semiconductor layer; a second conductivity type well region formed on the semiconductor layer and having a channel region; a first conductivity type source region formed on the well region and including a first region adjacent to the well region and a second region adjacent to the first region; a gate insulating film formed on the semiconductor layer and having a first portion that contacts the first region; a second portion that contacts the well region and that has a thickness that is the same as that of the first portion; and a third portion that contacts the second region and that has a thickness that is greater than that of the first portion; and a gate electrode formed on the gate insulating film and opposed to the channel region where a channel is formed through the gate insulating film. | 05-12-2016 |
20160141204 | TRENCH HAVING THICK DIELECTRIC SELECTIVELY ON BOTTOM PORTION - A method of fabricating a semiconductor device includes etching a semiconductor substrate having a top surface to form a trench having sidewalls and a bottom surface that extends from the top surface into the semiconductor substrate. A dielectric liner of a first dielectric material is formed on the bottom surface and sidewalls of the trench to line the trench. A second dielectric layer of a second dielectric material is deposited to at least partially fill the trench. The second dielectric layer is partially etched to selectively remove the second dielectric layer from an upper portion of the trench while preserving the second dielectric layer on a lower portion of the trench. The trench is filled with a fill material which provides an electrical conductivity that is at least that of a semiconductor. | 05-19-2016 |
20160141380 | Method for Manufacturing a Semiconductor Device, and Semiconductor Device - A method of manufacturing a semiconductor device includes providing a semiconductor substrate having a main surface and a gate electrode which is within a trench between neighboring semiconductor mesas. The gate electrode is electrically insulated from the neighboring semiconductor mesas by respective dielectric layers. A respective pillar on each of the neighboring semiconductor mesas is formed, leaving an opening between the pillars above the trench. Dielectric contact spacers are formed in the opening along respective pillar side walls to narrow the opening above the gate electrode. A conductor is formed, having an interface with the gate electrode. The interface extends along an extension of the gate electrode, and the conductor has a conductivity greater than the conductivity of the gate electrode. | 05-19-2016 |
20160141409 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device provided herein includes a trench in which a gate insulating layer (GIL) and a gate electrode are located. A step is provided in a lateral surface of the trench. The step surface descends toward a center of the trench. First and second regions are of a first conductivity type. A body region, a lateral region and a bottom region are of a second conductivity type. The first region, a body region, and the second region are in contact with the GIL at the upper lateral surface of the trench. The second region is in contact with the GIL at the lower lateral surface of the trench. A lateral region is in contact with the GIL at the lower lateral surface. A bottom region is in contact with the GIL at the bottom surface of the trench. | 05-19-2016 |
20160141410 | SEMICONDUCTOR COMPONENT WITH DYNAMIC BEHAVIOR - One embodiment provides a semiconductor component including a semiconductor body having a first side and a second side and a drift zone; a first semiconductor zone doped complementarily to the drift zone and adjacent to the drift zone in a direction of the first side; a second semiconductor zone of the same conduction type as the drift zone adjacent to the drift zone in a direction of the second side; at least two trenches arranged in the semiconductor body and extending into the semiconductor body and arranged at a distance from one another; and a field electrode arranged in the at least two trenches adjacent to the drift zone. The at least two trenches are arranged at a distance from the second semiconductor zone in the vertical direction, a distance between the trenches and the second semiconductor zone is greater than 1.5 times the mutual distance between the trenches, and a doping concentration of the drift zone in a section between the trenches and the second semiconductor zone differs by at most 35% from a minimum doping concentration in a section between the trenches. | 05-19-2016 |
20160149029 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate including a trench, a gate insulating layer, and a gate electrode. A step is arranged in a side surface of the trench. The semiconductor substrate includes first and second regions, a body region, and a side region. The body region extends from a position being in contact with the first region to a position located on the lower side with respect to the step. The body region is in contact with the gate insulating layer at a portion of the upper side surface located on a lower side with respect to the first region. The second region is located on a lower side of the body region and in contact with the gate insulating layer at the lower side surface. The side region is in contact with the gate insulating layer at the step surface and connected to the second region. | 05-26-2016 |
20160149034 | POWER SEMICONDUCTOR DEVICE HAVING LOW ON-STATE RESISTANCE - A power semiconductor device having low on-state resistance includes a substrate having an epitaxial layer formed thereon, a gate structure, a termination structure, and a patterned conductive layer. The epitaxial layer has at least a first trench and a second trench. The gate structure is embedded in the first trench, including a gate electrode and a shielding electrode disposed under the gate electrode. The termination structure is embedded in the second trench, including a termination electrode. The patterned conductive layer is disposed above the epitaxial layer. Specially, the shield electrode of the gate structure and the termination electrode of the termination structure are configured to receive the gate voltage. The patterned conductive layer is configured to electrically contact said gate electrode and termination electrodes by a first contact plug and a second contact plug respectively. | 05-26-2016 |
20160163789 | SUPER-JUNCTION TRENCH MOSFETS WITH CLOSED CELL LAYOUT HAVING SHIELDED GATE - A super-junction trench MOSFET with closed cell layout having shielded gate is disclosed, wherein closed gate trenches surrounding a deep trench in each unit cell and the shielded gate disposed in the deep trench. Trenched source-body contacts are at least formed between the closed gate trenches and the deep trench. The deep trench has square, rectangular, circle or hexagon shape. | 06-09-2016 |
20160163805 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a semiconductor device is provided. The method includes operations below. First, an epitaxial layer is formed on a substrate. Then, a trench is formed in the epitaxial layer. Then, a first dielectric layer and a shield layer are formed in the trench, in which the shield layer is embedded within the first dielectric layer. Then, a spacer layer is formed in the trench and on the first dielectric layer. Finally, a second dielectric layer and a gate are formed in the trench and on the spacer layer, and a source is formed in the epitaxial layer surrounding the trench, in which the gate is embedded within the second dielectric layer, and the source surrounds the gate. | 06-09-2016 |
20160163854 | SEMICONDUCTOR DEVICE - A front surface electrode common to a plurality of unit cells is provided substantially all over an active region of a semiconductor element. A plurality of electrode pads on the front surface electrode are closer to the outer peripheral portion side than the central portion of the active region. Different wires are joined to substantially the center of each electrode pad. The active region is divided into two or more segments so that the segments are aligned along the path of current flowing through the front surface electrode, and unit cells different in conduction ability are disposed respectively in each segment. Unit cells lowest in conduction ability are in the first segment farthest from junctions of the wires and electrode pads, and the unit cells are disposed so that the farther apart from the junctions of the wires and electrode pads, the lower in conduction ability the unit cells are. | 06-09-2016 |
20160172482 | INTEGRATING ENHANCEMENT MODE DEPLETED ACCUMULATION/INVERSION CHANNEL DEVICES WITH MOSFETS | 06-16-2016 |
20160172488 | SEMICONDUCTOR DEVICE HAVING DUAL WORK FUNCTION GATE STRUCTURE, METHOD FOR FABRICATING THE SAME, TRANSISTOR CIRCUIT HAVING THE SAME, MEMORY CELL HAVING THE SAME, AND ELECTRONIC DEVICE HAVING THE SAME | 06-16-2016 |
20160181416 | Charge-Compensation Device | 06-23-2016 |
20160190266 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes a first capacitive insulating film, a semiconductor region, a gate insulating film, and a gate electrode. The semiconductor region has a groove. The gate insulating film covers a surface of the groove. The gate electrode is in the groove. The gate electrode includes first and second conductive films. The first conductive film is in contact with the gate insulating film. The first conductive film has an upper surface which is higher than a close portion of the second conductive film. The close portion is closer to the upper surface of the first conductive film. | 06-30-2016 |
20160204201 | SEMICONDUCTOR DEVICES HAVING CHANNELS WITH RETROGRADE DOPING PROFILE | 07-14-2016 |
20160204248 | SEMICONDUCTOR DEVICE WITH VERTICAL GATE AND METHOD OF MANUFACTURING THE SAME | 07-14-2016 |
20170236934 | FLOATING-SHIELD TRIPLE-GATE MOSFET | 08-17-2017 |
20180026134 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME | 01-25-2018 |
20190148384 | SEMICONDUCTOR DEVICES | 05-16-2019 |
20190148532 | SEMICONDUCTOR DEVICE | 05-16-2019 |
20190148541 | Termination Design For Trench Superjunction Power MOSFET | 05-16-2019 |
20220140135 | Power Semiconductor Device - A power semiconductor device includes: a semiconductor body; a control electrode at least partially on or inside the semiconductor body; elevated source regions in the semiconductor body adjacent to the control electrode; recessed body regions adjacent to the elevated source regions; and a dielectric layer arranged on a portion of a surface of the semiconductor body and defining a contact hole. The contact hole is at least partially filled with a conductive material establishing an electrical contact with at least a portion of the elevated source regions and at least a portion of the recessed body regions. At least one first contact surface between at least one elevated source region and the dielectric layer extends in a first horizontal plane. At least one second contact surface between at least one recessed body region and the dielectric layer extends in a second horizontal plane located vertically below the first horizontal plane. | 05-05-2022 |