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Gate controls vertical charge flow portion of channel (e.g., VMOS device)

Subclass of:

257 - Active solid-state devices (e.g., transistors, solid-state diodes)

257213000 - FIELD EFFECT DEVICE

257288000 - Having insulated electrode (e.g., MOSFET, MOS diode)

257327000 - Short channel insulated gate field effect transistor

Patent class list (only not empty are listed)

Deeper subclasses:

Class / Patent application numberDescriptionNumber of patent applications / Date published
257330000 Gate electrode in groove 942
Entries
DocumentTitleDate
20130043525SEMICONDUCTOR DEVICES INCLUDING A VERTICAL CHANNEL TRANSISTOR AND METHODS OF FABRICATING THE SAME - According to example embodiments, a semiconductor device includes a plurality of active pillars protruding from a substrate. Each active pillar includes a channel region between upper and lower doped regions. A contact gate electrode faces the channel region and is connected to a word line. The word line extends in a first direction. A bit line is connected to the lower doped region and extends in a second direction. The semiconductor device further includes a string body connection portion that connects the channel region of at least two adjacent active pillars of the plurality of active pillars.02-21-2013
20130026560SEMICONDUCTOR DEVICE - A parallel p-n layer (01-31-2013
20130026559SILICON-CARBIDE MOSFET CELL STRUCTURE AND METHOD FOR FORMING SAME - In one embodiment, the invention comprises a MOSFET comprising individual MOSFET cells. Each cell comprises a U-shaped well (01-31-2013
20090057755SPACER UNDERCUT FILLER, METHOD OF MANUFACTURE THEREOF AND ARTICLES COMPRISING THE SAME - Disclosed herein is a semiconducting device comprising a gate stack formed on a surface of a semiconductor substrate; a vertical nitride spacer element formed on each vertical sidewall of the gate stack; a portion of the vertical nitride spacer overlying the semiconductor substrate; a silicide contact formed on the semiconductor substrate adjacent the gate stack, the silicide contact being in operative communication with drain and source regions formed in the semiconductor substrate; and an oxide spacer disposed between the vertical nitride spacer element and the silicide contact; the oxide spacer operating to minimize an undercut adjacent the vertical nitride spacer during an etching process.03-05-2009
20130134502WAFER LEVEL CHIP SCALE PACKAGE - A semiconductor device, a method of manufacturing semiconductor devices and a circuit package assembly are described. A semiconductor device can have a semiconductor substrate with first and second surfaces and a sidewall between them. First and second conductive pads on the first and second surfaces are in electrical contact with corresponding first and second semiconductor device structures in the substrate. An insulator layer on the first surface and sidewall covers a portion of the first conductive pad on the first surface. An electrically conductive layer on part of the insulator layer on the first conductive pad and sidewall is in electrical contact with the second conductive pad. The insulator layer prevents the conductive layer from making electrical contact between the first and second conductive pads.05-30-2013
20130134503CROSS-POINT DIODE ARRAYS AND METHODS OF MANUFACTURING CROSS-POINT DIODE ARRAYS - Methods of forming an array of memory cells and memory cells that have pillars. Individual pillars can have a semiconductor post formed of a bulk semiconductor material and a sacrificial cap on the semiconductor post. Source regions can be between columns of the pillars, and gate lines extend along a column of pillars and are spaced apart from corresponding source regions. Each gate line surrounds a portion of the semiconductor posts along a column of pillars. The sacrificial cap structure can be selectively removed to thereby form self-aligned openings that expose a top portion of corresponding semiconductor posts. Individual drain contacts formed in the self-aligned openings are electrically connected to corresponding semiconductor posts.05-30-2013
20080258209SEMICONDUCTOR DEVICE AND MANUFATURING METHOD THEREOF - A semiconductor device comprises a plurality of semiconductor pillars laid out in matrix in a first and a second directions parallel with a main surface of a semiconductor substrate, and extending to a direction substantially perpendicular to the main surface; gate insulating films covering each surface of the plurality of semiconductor pillars, respectively; upper diffusion layers formed in each upper part of the plurality of semiconductor pillars, respectively; lower diffusion layers formed in each lower part of the plurality of semiconductor pillars, respectively; gate electrodes encircling at least each channel region between each upper diffusion layer and each lower diffusion layer, respectively; and a plurality of lower electrodes short-circuiting the lower diffusion layers adjacent in the first direction.10-23-2008
20110193157CROSS-HAIR CELL BASED FLOATING BODY DEVICE - A non-planar transistor having floating body structures and methods for fabricating the same are disclosed. In certain embodiments, the transistor includes a fin having upper and lower doped regions. The upper doped regions may form a source and drain separated by a shallow trench formed in the fin. During formation of the fin, a hollow region may be formed underneath the shallow trench, isolating the source and drain. An oxide may be formed in the hollow region to form a floating body structure, wherein the source and drain are isolated from each other and the substrate formed below the fin. In some embodiments, independently bias gates may be formed adjacent to walls of the fin. In other embodiments, electrically coupled gates may be formed adjacent to the walls of the fin.08-11-2011
20130037878VDMOS DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating VDMOS devices includes providing a semiconductor substrate; forming a first N-type epitaxial layer on the semiconductor substrate; forming a hard mask layer with an opening on the first N-type epitaxial layer; etching the first N-type epitaxial layer along the opening until the semiconductor substrate is exposed, to form P-type barrier figures; forming a P-type barrier layer in the P-type barrier figures, the P-type barrier layer having a same thickness as that of the first N-type epitaxial layer; removing the hard mask layer; forming a second N-type epitaxial layer on the first N-type epitaxial layer and the P-type barrier layer; forming a gate on the second N-type epitaxial layer; forming a source in the second N-type epitaxial layer on both side of the gate; and forming a drain on the back of the semiconductor substrate relative to the gate and the source.02-14-2013
20130032878SEMICONDUCTOR DEVICE - According to example embodiments, a semiconductor device includes horizontal patterns stacked on a substrate. The horizontal patterns define an opening through the horizontal patterns. A first core pattern is in the opening. A second core pattern is in the opening on the first core pattern. A first active pattern is between the first core pattern and the horizontal patterns. A second active pattern containing a first element is between the second core pattern and the horizontal patterns. The second active pattern contains the first element at a higher concentration than a concentration of the first element in the second core pattern.02-07-2013
20130032879SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes vertical pillars formed by etching a semiconductor substrate and junction regions which are located among the neighboring vertical pillars and spaced apart from one another in a zigzag pattern. As a result, the semiconductor device easily guarantees an electrical passage between the semiconductor substrate and the vertical pillars, such that it substantially prevents the floating phenomenon from being generated, resulting in the prevention of deterioration of the semiconductor device.02-07-2013
20130032877N-CHANNEL TRANSISTOR COMPRISING A HIGH-K METAL GATE ELECTRODE STRUCTURE AND A REDUCED SERIES RESISTANCE BY EPITAXIALLY FORMED SEMICONDUCTOR MATERIAL IN THE DRAIN AND SOURCE AREAS - When forming sophisticated semiconductor devices including high-k metal gate electrode structures and N-channel transistors, superior performance may be achieved by incorporating epitaxially grown semiconductor materials, for instance a strain-inducing silicon/carbon alloy in combination with an N-doped silicon material, which may provide an acceptable sheet resistivity.02-07-2013
20130075811DOUBLE GATE TRANSISTOR AND METHOD OF FABRICATING THE SAME - The present invention discloses a double gate transistor and a method of fabricating said transistor, said transistor comprising: a semiconductor layer on a substrate; a fin structure formed in said semiconductor layer, said fin structure having two end portions for forming source and drain regions and a middle portion between said two end portions for forming a channel region, said middle portion including two opposed side surfaces perpendicular to a substrate surface; a first gate dielectric layer and a first gate disposed on one side surface of said middle portion; and a second gate dielectric layer and a second gate disposed on the other side surface of said middle portion.03-28-2013
20090121284Semiconductor device and method for manufacturing the same - A sacrifice oxide film is formed in a Fin semiconductor substrate portion, and impurities are then implanted in the semiconductor substrate through a mask pattern as a mask. Thereafter, the sacrifice oxide film is removed to expose the semiconductor substrate. A gate insulating film is then formed on the exposed semiconductor substrate.05-14-2009
20100044784Vertical Channel Fin Field-Effect Transistors Having Increased Source/Drain Contact Area and Methods for Fabricating the Same - A fin field-effect transistor (FinFET) device includes a fin-shaped active region having first and second source/drain regions therein and a channel region therebetween vertically protruding from a semiconductor substrate. A gate electrode is formed on an upper surface and sidewalls of the channel region. First and second source/drain contacts are formed on respective upper surfaces and sidewalls of the first and second source/drain regions of the fin-shaped active region at opposite sides of the gate electrode. The channel region may be narrower than the first and second source/drain regions of the fin-shaped active region.02-25-2010
20090085102SEMICONDUCTOR DEVICE HAVING VERTICAL SURROUNDING GATE TRANSISTOR STRUCTURE, METHOD FOR MANUFACTURING THE SAME, AND DATA PROCESSING SYSTEM - A semiconductor device is provided which includes: semiconductor pillars which include impurity diffused layers, each semiconductor pillar having a width which allows full depletion of a semiconductor forming each semiconductor pillar, the impurity diffused layers being electrically connected to each other; and a common gate section which covers side faces of the pillars.04-02-2009
20120205736Memory Arrays and Methods of Forming Electrical Contacts - Some embodiments include methods of forming electrical contacts. A row of semiconductor material projections may be formed, with the semiconductor material projections containing repeating components of an array, and with a terminal semiconductor projection of the row comprising a contact location. An electrically conductive line may be along said row, with the line wrapping around an end of said terminal semiconductor projection and bifurcating into two branches that are along opposing sides of the semiconductor material projections. Some of the semiconductor material of the terminal semiconductor projection may be replaced with dielectric material, and then an opening may be extended into the dielectric material. An electrical contact may be formed within the opening and directly against at least one of the branches. Some embodiments include memory arrays.08-16-2012
20100102381POWER SEMICONDUCTOR DEVICE - A power semiconductor device according to an embodiment of the present invention includes a first semiconductor layer of a first conductivity type, second semiconductor layers of the first conductivity type and third semiconductor layers of a second conductivity type, which are formed on the first semiconductor layer, have stripe shapes extending in a first horizontal direction, and are alternately arranged along a second horizontal direction orthogonal to the first horizontal direction, a fourth semiconductor layer of the second conductivity type, selectively formed on a surface of one of the third semiconductor layers, a fifth semiconductor layer of the first conductivity type, selectively formed on a surface of the fourth semiconductor layer, and formed into a stripe shape extending in the first horizontal direction without being formed into a stripe shape extending in the second horizontal direction, and a control electrode formed on the second, third, fourth, and fifth semiconductor layers via an insulating layer, and having a plane pattern periodical in the first horizontal direction and the second horizontal direction.04-29-2010
20090159964VERTICAL CHANNEL TRANSISTOR AND METHOD OF FABRICATING THE SAME - A vertical channel transistor includes a plurality of active pillar patterns extending perpendicularly from the top surface of the substrate toward an upper part. A gate insulating layer is deposited on the side wall of the active pillar pattern and serves as an ion diffusion barrier between the pillar patterns and surrounding lower gate electrodes. The resultant pillar pattern structure is encapsulated with a metal. The resultant pillar pattern is surrounded on all sides by a specified height by a sacrificial layer of Spin-On Dielectric (SOD). The metal layer is etched-back to the height of the sacrificial layer, thus forming the lower gate electrodes. A spacer layer of an insulating mater is deposited surrounding the upper part of the pillar patterns and the sacrificial layer is removed exposing a part of the lower gate electrodes. The exposed gate electrode is etched to facilitate semiconductor integration.06-25-2009
20100109079Vertical type semiconductor device - A vertical pillar semiconductor device may include a substrate, a group of channel patterns, a gate insulation layer pattern and a gate electrode. The substrate may be divided into an active region and an isolation layer. A first impurity region may be formed in the substrate corresponding to the active region. The group of channel patterns may protrude from a surface of the active region and may be arranged parallel to each other. A second impurity region may be formed on an upper portion of the group of channel patterns. The gate insulation layer pattern may be formed on the substrate and a sidewall of the group of channel patterns. The gate insulation layer pattern may be spaced apart from an upper face of the group of channel patterns. The gate electrode may contact the gate insulation layer and may enclose a sidewall of the group of channel patterns.05-06-2010
20100109078SEMICONDUCTOR DEVICE AND METHOD OF FORMING A SEMICONDUCTOR DEVICE - A method of forming a semiconductor device comprises providing a semiconductor substrate, providing a semiconductor layer of a first conductivity type over the semiconductor substrate, forming a first region of the first conductivity type in the semiconductor layer, and forming a control region over the semiconductor layer and over part of the first region. A mask layer is formed over the semiconductor layer and outlines a first portion of a surface of the semiconductor layer over part of the first region. Semiconductor material of a second conductivity type is provided to the outlined first portion to provide a second region in the semiconductor layer. The first region and second region are driven into the semiconductor layer so as to form a pre-control region of the first conductivity type extending into the semiconductor layer from the surface and under a portion of the control region and a graded body region of the second conductivity type extending into the semiconductor layer under the pre-control region. A body region is formed by providing semiconductor material of the second conductivity type to the outlined first portion. The body region extends into the pre-control region. A current electrode region is formed in the body region.05-06-2010
20130082322SEMICONDUCTOR DEVICE WITH SELF-CHARGING FIELD ELECTRODES - Disclosed is a semiconductor device including a drift region of a first doping type, a junction between the drift region and a device region, and at least one field electrode structure in the drift region. The field electrode structure includes a field electrode, a field electrode dielectric adjoining the field electrode and arranged between the field electrode and the drift region, and having an opening, at least one of a field stop region and a generation region.04-04-2013
20130082321DUAL-GATE VDMOS DEVICE - Semiconductor devices are described that include a dual-gate configuration. In one or more implementations, the semiconductor devices include a substrate having a first surface and a second surface. The substrate includes a first and a second body region formed proximal to the first surface. Moreover, each body region includes a source region formed therein. The substrate further includes a drain region formed proximal to the second surface and an epitaxial region that is configured to function as a drift region between the drain region and the source regions. A dual-gate is formed over the first surface of the substrate. The dual-gate includes a first gate region and a second gate region that define a gap there between to reduce the gate to drain capacitance.04-04-2013
20130082323SUPERJUNCTION STRUCTURE, SUPERJUNCTION MOS TRANSISTOR AND MANUFACTURING METHOD THEREOF - A superjunction structure with unevenly doped P-type pillars (04-04-2013
20130082320STRAPPED DUAL-GATE VDMOS DEVICE - Semiconductor devices are described that include a dual-gate configuration. In one or more implementations, the semiconductor devices include a substrate having a first surface and a second surface. The substrate includes a first and a second body region formed proximal to the first surface. Moreover, each body region includes a source region formed therein. The substrate further includes a drain region formed proximal to the second surface and an epitaxial region that is configured to function as a drift region between the drain region and the source regions. A dual-gate is formed over the first surface of the substrate. The dual-gate includes a first gate region and a second gate region that define a gap there between to reduce the gate to drain capacitance. A conductive layer may be formed over the first gate region and the second gate region to lower the effective resistance of the dual-gate.04-04-2013
20100133606Three-dimensional semiconductor memory device - A three-dimensional semiconductor memory device includes word lines and gate interlayer insulation layers that are alternatively stacked on a semiconductor substrate while extending in a horizontal direction, a vertical channel layer that faces the word lines and extends upwardly from the semiconductor substrate, and a channel pad that extends from the vertical channel layer and is disposed on an uppermost gate interlayer insulation layer of the gate interlayer insulation layers.06-03-2010
20090039420FINFET MEMORY CELL HAVING A FLOATING GATE AND METHOD THEREFOR - A fin field effect transistor (FinFET) memory cell and method of formation has a substrate for providing mechanical support. A first dielectric layer overlies the substrate. A fin structure overlies the dielectric layer and has a first current electrode and a second current electrode separated by a channel. A floating gate has a vertical portion that is adjacent to and electrically insulated from a side of the channel and has a horizontal portion overlying the first dielectric layer and extending laterally away from the channel. The floating gate stores electrical charge. A second dielectric layer is adjacent the floating gate. A control gate adjacent the second dielectric layer and physically separated from the floating gate by the second dielectric layer. The “L-shape” of the floating gate enhances capacitive coupling ratio between the control gate and the floating gate.02-12-2009
20130087850SEMICONDUCTOR DEVICE HAVING DMOS INTEGRATION - Semiconductor devices that include a trench with conductive material for connecting a VDMOS device to a LDMOS device are described. The semiconductor devices include a substrate having a first region and a second region, wherein the second region is disposed on the first region. A trench extends from a top surface of the second region to the first region. The semiconductor substrate includes a VDMOS device formed proximate to the top surface of the second region and a LDMOS device that is also formed proximate to the top surface of the second region. The drain region of the VDMOS device is electrically connected to the source region of the LDMOS device by way of a conductive material disposed in the trench.04-11-2013
20130087851SEMICONDUCTOR DEVICE WITH VERTICAL SEMICONDUCTOR ELEMENT - A semiconductor device includes a vertical semiconductor element having a super junction structure constructed of a first conductivity-type drift layer disposed on a surface of a semiconductor substrate and second conductivity-type regions having a stripe shape defining a longitudinal direction in one direction and being arranged at a predetermined column pitch in the drift layer. When a surplus concentration obtained by dividing a difference between an electrical charge of the second conductivity-type region and an electrical charge of a first conductivity-type region by the column pitch is i, a depth of the super junction structure is z, a surplus concentration gradient as a change of the surplus concentration i per unit depth dz is di/dz, and a central withstand voltage in which a margin is added to a desired withstand voltage is Vmax, the super junction structure is configured such that the surplus concentration gradient di/dz satisfies a relation of04-11-2013
20120181603VERTICAL CHANNEL TYPE NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a vertical channel type non-volatile memory device including forming a source region, alternately forming a plurality of interlayer dielectric layers and a plurality of conductive layers for a gate electrode over a substrate with the source region formed therein, forming a trench exposing the source region by etching the plurality of interlayer dielectric layers and the plurality of conductive layers for a gate electrode, and siliciding the conductive layers for a gate electrode and the source region that are exposed through the trench.07-19-2012
20130049101SEMICONDUCTOR DEVICES UTILIZING PARTIALLY DOPED STRESSOR FILM PORTIONS AND METHODS FOR FORMING THE SAME - A semiconductor structure and method for forming the same provide a high mobility stressor material suitable for use as source/drain regions or other active devices. The structure is formed in a substrate opening and is doped with an impurity such as boron in upper portions but is void of the impurity in regions that contact the surfaces of the opening. The structure is therefore resistant to out-diffusion of the dopant impurity during high temperature operations and may be formed through selective deposition using reduced pressure chemical vapor deposition or reduced pressure epitaxial deposition.02-28-2013
20130049100METHOD OF MAKING A LOW-RDSON VERTICAL POWER MOSFET DEVICE - The invention relates to a power semiconductor device and its preparation methods thereof. Particularly, the invention aims at providing a method for reducing substrate contribution to the Rdson (drain-source on resistance) of power MOSFETs, and a power MOSFET device made by the method. By forming one or more bottom grooves at the bottom of Si substrate, the on resistance of the power MOSFET device attributed to the substrate is effectively reduced. A matching lead frame base complementary to the substrate with bottom grooves further improves the package of the power MOSFET device.02-28-2013
20090302378METHOD AND SYSTEM FOR VERTICAL DMOS WITH SLOTS - A method for providing a high power, low resistance, high efficient vertical DMOS device is disclosed. The method comprises providing a semiconductor substrate with a source body structure thereon. The method further comprises providing a plurality of slots in the source/body structure and providing a metal within the plurality of slots to form a plurality of structures. A slotted PowerFET array is disclosed. This slotted approach results in a dense PowerFET, a low Ron due to the slotted design, an oxide isolated process without any due extra steps other than the slots, lower capacitance, lower leakage, smaller die, improved heat transfer, improved electro-migration, lower ground resistance, less cross talk, drops the isolation diffusion and the sinker diffusion, mostly low temperature processing and provides double metal with single metal processing. Also disclosed is a method for integrating this vertical DMOS with CMOS, bipolar and BCD to provide an optimized small, efficient die using the buried power buss approach and these technologies.12-10-2009
20090302377VERTICAL-TYPE SEMICONDUCTOR DEVICE - In a vertical-type semiconductor device, a method of manufacturing the same and a method of operating the same, the vertical-type semiconductor device includes a single-crystalline semiconductor pattern having a pillar shape provided on a substrate, a gate surrounding sidewalls of the single-crystalline semiconductor pattern and having an upper surface lower than an upper surface of the single-crystalline semiconductor pattern, a mask pattern formed on the upper surface of the gate, the mask pattern having an upper surface coplanar with the upper surface of the single-crystalline semiconductor pattern, a first impurity region in the substrate under the single-crystalline semiconductor pattern, and a second impurity region under the upper surface of the single-crystalline semiconductor pattern. The vertical-type pillar transistor formed in the single-crystalline semiconductor pattern may provide excellent electrical properties. The mask pattern is not provided on the upper surface of the single-crystalline semiconductor pattern in the second impurity region, to thereby reduce failures of processes.12-10-2009
20090302376SEMICONDUCTOR DEVICE - A semiconductor device includes: a first semiconductor layer of a first conductivity type having a first surface and a second surface opposite to the first surface, a cell region, and a terminal region surrounding the cell region, the cell region being configured to allow a current to flow between the first surface and the second surface; a first guard ring layer of a second conductivity type selectively formed in a surface portion of the first semiconductor layer in the terminal region, the first guard ring layer having a bottom surface thereof and internal and external side surfaces thereof; and a second guard ring layer of the second conductivity type selectively formed in the surface portion of the first semiconductor layer in the terminal region so as to cover a portion of the first guard ring layer at which the bottom surface and the external side surface intersect.12-10-2009
20090302375METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND DEVICE MANUFACTURED BY THE METHOD - A method of manufacturing a semiconductor device includes forming trenches (12-10-2009
20120112267SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - Disclosed herein is a semiconductor device including: a first conductivity type semiconductor base body; a first conductivity type pillar region; second conductivity type pillar regions; element and termination regions provided in the first and second conductivity type pillar regions, transistors being formed in the element region, and no transistors being formed in the termination region; body regions; a gate insulating film; gate electrodes; source regions; and body potential extraction regions, wherein voids are formed in the second conductivity type pillar regions of the termination region.05-10-2012
20120112266SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device of the present invention includes: a semiconductor substrate of a first conductive type; an epitaxial layer of the first conductive type formed on the semiconductor substrate and having a protrusion formed on a surface thereof; a well region of a second conductive type formed on the surface of the epitaxial layer at each side of the protrusion; a source region of the first conductive type selectively formed in a surface of the well region; a gate insulating film formed so as to cover at least the protrusion and the surface of the well region; and a gate electrode formed on a part of the gate insulating film corresponding to the protrusion. The gate insulating film is thicker in a region thereof corresponding to an upper surface of the protrusion than the other regions thereof.05-10-2012
20120306004SEMICONDUCTOR MEMORY DEVICE - Provided is a semiconductor memory device. The semiconductor memory device may include a local bitline extending in a direction substantially vertical to an upper surface of a semiconductor substrate and a local wordline intersecting the local bitline. The local bitline is electrically connected to a bitline channel pillar penetrating a gate of a bitline transistor, and the local wordline is electrically connected to a wordline channel pillar penetrating a gate of a wordline transistor.12-06-2012
20120306003TRANSISTOR WITH CONTROLLABLE COMPENSATION REGIONS - Disclosed is a MOSFET including at least one transistor cell. The at least one transistor cell includes a source region, a drain region, a body region and a drift region. The body region is arranged between the source region and the drift region and the drift region is arranged between the body region and the drain region. The at least one transistor cell further includes a compensation region arranged in the drift region and distant to the body region, a source electrode electrically contacting the source region and the body region, a gate electrode arranged adjacent the body region and dielectrically insulated from the body region by a gate dielectric, and a coupling arrangement including a control terminal. The coupling arrangement is configured to electrically couple the compensation region to at least one of the body region, the source region, the source electrode and the gate electrode dependent on a control signal received at the control terminal.12-06-2012
20090267141METHOD FOR FABRICATING SILICON CARBIDE VERTICAL MOSFET DEVICES - A method of forming a vertical MOSFET device includes forming a trench within a drift layer substrate, the drift layer comprising a first polarity type, the trench generally defining a well region of a second polarity type opposite the first polarity type. An ohmic contact layer is formed within a bottom surface of the trench, the ohmic contact layer comprising a material of the second polarity type. A layer of the second polarity type is epitaxially grown over the drift layer, sidewall surfaces of the trench, and the ohmic contact layer. A layer of the first polarity type is epitaxially grown over the epitaxially grown layer of the second polarity type so as to refill the trench, and the epitaxially grown layers of the first and second polarity type are planarized so as to expose an upper surface of the drift layer substrate.10-29-2009
20110012193SEMICONDUCTOR DEVICE HAVING VERTICAL TRANSISTOR, MANUFACTURING METHOD THEREOF, AND DATA PROCESSING SYSTEM - A semiconductor device includes: a semiconductor substrate; a silicon pillar provided perpendicularly to a main surface of the semiconductor substrate; a gate dielectric film that covers a portion of a side surface of the silicon pillar; an insulator pillar that covers remaining portions of the side surface of the silicon pillar; a gate electrode that covers the silicon pillar via the gate dielectric film and the insulator pillar; an interlayer dielectric film provided above the silicon pillar, the gate dielectric film, the insulator pillar, and the gate electrode; and a gate contact plug embedded in a contact hole provided in the interlayer dielectric film, and in contact with the gate electrode and the insulator pillar. A film thickness of the insulator pillar in a lateral direction is thicker than a film thickness of the gate dielectric film in a lateral direction.01-20-2011
20130161729Methods of Forming Isolation Structures on FinFET Semiconductor Devices - One illustrative method disclosed herein includes performing at least one etching process on a semiconducting substrate to form a plurality of trenches and a plurality of fins for the FinFET device in the substrate, forming a first layer of insulating material in the trenches, wherein an upper surface of the first layer of insulating material is below an upper surface of the substrate, forming an isolation layer within the trenches above the first layer of insulating material, wherein the isolation layer has an upper surface that is below the upper surface of the substrate, forming a second layer of insulating material above the isolation layer, wherein the second layer of insulating material has an upper surface that is below the upper surface of the substrate, and forming a gate electrode structure above the second layer of insulating material.06-27-2013
20130161731SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A three-dimensional (3D) semiconductor device includes first interlayer dielectric layers and word lines that are alternately stacked on a substrate; select lines formed on the first interlayer dielectric layers and the word lines; etch stop patterns formed on the select lines to contact the select lines; channel holes formed to pass through the select lines, the first interlayer dielectric layers, and the word lines; channel layers formed on surfaces of the channel holes; insulating layers formed in the channel holes, the insulating layers having an upper surface that is lower than upper surfaces of the etch stop patterns; impurity-doped layers formed in channel holes on upper surface of the insulating layers; and a second interlayer dielectric layer formed over the etch stop patterns and the impurity-doped layers.06-27-2013
20090236656SEMICONDUCTOR DEVICE HAVING VERTICAL CHANNEL TRANSISTOR AND METHOD FOR FABRICATING THE SAME - A semiconductor device having a substrate; a plurality of pillar structures, wherein each pillar structure includes an active pillar disposed over the substrate; a gate electrode surrounding an outer wall of the active pillar; an interlayer dielectric (ILD) layer insulating adjacent pillar structures; a gate contact penetrating the ILD layer and configured to connect to a sidewall of the gate electrode; and a word line connected to the gate contact.09-24-2009
20130161732VERTICAL CHANNEL THIN FILM TRANSISTOR - Disclosed is a vertical channel thin film transistor including a substrate; a drain electrode formed on the substrate; a spacer formed on the substrate while coming into contact with the drain electrode; a source electrode formed on the spacer; an active layer formed on an entire surface of the substrate including the drain electrode and the source electrode and configured to form a vertical channel; a gate insulating layer formed on the active layer; and a gate electrode formed on the gate insulating layer.06-27-2013
20130161733SEMICONDUCTOR DEVICE - Disclosed herein a semiconductor device, which comprises: a vertical MOS transistor that has an upper diffusion layer, and a first lower diffusion layer disposed at a lower position than the upper diffusion layer; and a first diode that has a first well isolated from the first lower diffusion layer, and a second lower diffusion layer disposed at a lower position than the upper diffusion layer and formed in the first well. A surge voltage is discharged across the second lower diffusion layer and the first well when the surge voltage is applied.06-27-2013
20080296669SYSTEM AND METHOD FOR MAKING A LDMOS DEVICE WITH ELECTROSTATIC DISCHARGE PROTECTION - A semiconductor device includes one or more LDMOS transistors and one of more SCR-LDMOS transistors. Each LDMOS transistor includes a LDMOS well of a first conductivity type, a LDMOS source region of a second conductivity type formed in the LDMOS well, and a LDMOS drain region of a second conductivity type separated from the LDMOS well by a LDMOS drift region of the second conductivity type. Each SCR-LDMOS transistor comprising a SCR-LDMOS well of the first conductivity type, a SCR-LDMOS source region of the second conductivity type formed in the SCR-LDMOS well, a SCR-LDMOS drain region of a second conductivity type, and a anode region of the first conductivity type between the SCR-LDMOS drain region and the SCR-LDMOS drift region. The anode region is separated from the SCR-LDMOS well by a SCR-LDMOS drift region of the second conductivity type.12-04-2008
20120235227Power Semiconductor Device - A semiconductor device includes a vertical power semiconductor chip including a semiconductor layer. A first terminal is at a first side of the semiconductor layer and a second terminal is at a second side of the semiconductor layer opposite the first side along a first direction. A drift zone is within the semiconductor layer between the first terminal and the second terminal. The drift zone has, in a central part, a compressive stress of at least 100 MPa along a second direction perpendicular to the first direction. The central part extends from 40% to 60% of an overall extension of the drift zone along the first direction and into a depth of the semiconductor layer of at least 10 μm with respect to at least one of the first side and the second side of the semiconductor layer.09-20-2012
20110018056SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A first local wiring includes a convex portion protruding from a base and a protrusion protruding from a side surface of the convex portion. The convex portion of the first local wiring is connected to a lower conductive region of a first transistor while the protrusion is connected to a gate electrode of a second transistor. Moreover, the lower surface of the protrusion of the first local wiring is arranged at a height equal to or lower than the upper surface of the gate electrode of the second transistor.01-27-2011
20130207181SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device including a vertical gate and a method for manufacturing the same are disclosed, which prevent a floating body phenomenon, thereby increasing a cell threshold voltage and reducing leakage current, resulting in improved refresh properties of the semiconductor device. The semiconductor device includes a plurality of pillar patterns, including first pillar patterns arranged along a first direction and second pillar patterns arranged along a second direction, formed over a semiconductor substrate; a gate extending in the first direction, arranged along sidewalls of the first pillar patterns, and configured to couple the first pillar patterns; a junction region formed in an upper portion of the pillar patterns; and a conductive line arranged along the sidewalls of the first pillar patterns and provided in a region disposed below the junction region and over the gate.08-15-2013
20100219466SEMICONDUCTOR DEVICE WITH VERTICAL CHANNEL TRANSISTOR - In a high speed vertical channel transistor, a pillar structure is formed over a substrate, a gate electrode surrounds an outer wall of a lower portion of the pillar structure; and a word line extends in a direction to partially contact an outer wall of the gate electrode. The word line shifts toward a side of the pillar structure resulting in increased transistor speed.09-02-2010
20110241103METHOD OF MANUFACTURING A TUNNEL TRANSISTOR AND IC COMPRISING THE SAME - A method of manufacturing a tunnel field effect transistor is disclosed. The method comprises forming a two-step profile in a silicon substrate (10-06-2011
20110101446STAGGERED COLUMN SUPERJUNCTION - A staggered column superjunction semiconductor device may include a cell region having one or more device cells. One or more device cells in the cell region include a semiconductor substrate configured to act as a drain and a semiconductor layer formed on the substrate. A first doped column may be formed in the semiconductor layer to a first depth and a second doped column may be formed in the semiconductor layer to a second depth. The first depth is greater than the second depth. The first and second columns are doped with dopants of a same second conductivity type and extend along a portion of a thickness of the semiconductor layer and are separated from each by a portion of the semiconductor layer.05-05-2011
20100181613SEMICONDUCTOR MEMORY DEVICES - A semiconductor memory device includes first and second active pillar structures protruding at an upper part of a substrate, buried bit lines each extending in a first direction, and first gate patterns and second gate patterns each extending in a second direction. The first and second active pillar structures occupy odd-numbered and even-numbered rows, respectively. The first and the second active pillar structures also occupy even-numbered and odd-numbered columns, respectively. The columns of the second active pillar structures are offset in the second direction from the columns of the first active pillar structures. Each buried bit line is connected to lower portions of the first active pillar structures which occupy one of the even-numbered columns and to lower portions of the second active pillar structures which occupy an adjacent one of the odd-numbered columns.07-22-2010
20110140196EMBEDDED BIT LINE STRUCTURE, FIELD EFFECT TRANSISTOR STRUCTURE WITH THE SAME AND METHOD OF FABRICATING THE SAME - An embedded bit line structure, in which, a substrate includes an insulator layer having an original top surface and a semiconductor layer on the original top surface of the insulator layer, and a bit line is disposed within the lower portion of the trench along one side of an active area. The bit line includes a first portion and a second portion. The first portion is located within the insulator layer and below the original top surface of the insulator layer. The second portion is disposed on the first portion to electrically connect the semiconductor layer of the active area. An insulator liner is disposed on the first portion of the bit line and between the second portion of the bit line and the semiconductor layer of the substrate opposite the active area for isolation. An STI is disposed within the trench to surround the active area for isolation.06-16-2011
20110298040SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device and a method of manufacturing the same are disclosed. By forming a boron nitride film as a sealing film of a buried gate of a cell region from being oxidized, it is possible to improve refresh characteristics, to reduce the number of processes, and to reduce parasitic capacitance so as to improve the characteristics of the device. The semiconductor device includes a recess included in a semiconductor substrate, a gate buried over a bottom of the recess, and a boron nitride film included over the semiconductor substrate including the gate and the recess.12-08-2011
20120139034Process For Manufacturing A MOS Device With Intercell Ion Implant - A process for manufacturing a MOS device includes forming a semiconductor layer having a first type of conductivity; forming an insulated gate structure having an electrode region, above the semiconductor layer; forming body regions having a second type of conductivity, within the semiconductor layer, laterally and partially underneath the insulated gate structure; forming source regions having the first type of conductivity, within the body regions; and forming a first enrichment region, in a surface portion of the semiconductor layer underneath the insulated gate structure. The first enrichment region has the first type of conductivity and is set at a distance from the body regions. In order to form the first enrichment region, a first enrichment window is defined within the insulated gate structure, and first dopant species of the first type of conductivity are introduced through the first enrichment window and in a way self-aligned thereto.06-07-2012
20130161730MEMORY ARRAY STRUCTURE AND METHOD FOR FORMING THE SAME - A memory array structure and a method for forming the same are provided. The memory array structure comprises: a substrate; a plurality of memory cells, each memory cell including a vertical transistor, of which a gate structure is formed in a first trench extending in a first direction; a plurality of word lines in the first direction, each word line formed in the first trench; a plurality of bit lines in a second direction, each bit line formed in lower sides of a semiconductor pillars; a plurality of body lines in the first direction, each body line having a first portion formed on the gate electrodes and a second portion covering a part of a top surface of semiconductor pillar for providing a substrate contact to vertical channel regions; and a plurality of data storage device contacts.06-27-2013
20110284949VERTICAL TRANSISTOR AND A METHOD OF FABRICATING THE SAME - A vertical transistor and a method of fabricating the vertical transistor are provided. The vertical transistor has a substrate, a first electrode formed on the substrate, a first insulation layer formed on the first electrode, with a portion of the first electrode exposed from the first insulation layer and having a thickness greater than 50 nm and no more than 300 nm, a grid electrode formed on the first insulation layer, a semiconductor layer formed on the first electrode, and a second electrode formed on the semiconductor layer.11-24-2011
20110284948SEMICONDUCTOR DEVICE AND FABRICATION METHOD FOR THE SAME - A semiconductor device and a fabrication method for the semiconductor device are provided in which an increase of a forward loss is suppressed and a reverse recovery loss is reduced.11-24-2011
20110291182SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes vertical pillars formed by etching a semiconductor substrate and junction regions which are located among the neighboring vertical pillars and spaced apart from one another in a zigzag pattern. As a result, the semiconductor device easily guarantees an electrical passage between the semiconductor substrate and the vertical pillars, such that it substantially prevents the floating phenomenon from being generated, resulting in the prevention of deterioration of the semiconductor device.12-01-2011
20100213539SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREFOR - It is intended to provide a semiconductor device including a MOS transistor, comprising: a semiconductor pillar; one of a drain region and a source region formed in contact with a lower part of the semiconductor pillar; a first gate formed around a sidewall of the semiconductor pillar through a first dielectric film therebetween; and an epitaxial semiconductor layer formed on a top surface of the semiconductor pillar, wherein the other of the source region and the drain region is formed so as to be at least partially in the epitaxial semiconductor layer, and wherein: the other of the source region and the drain region has a top surface having an area greater than that of the top surface of the semiconductor pillar.08-26-2010
20120098054Reacted Conductive Gate Electrodes and Methods of Making the Same - A semiconductor device and a method for fabricating a semiconductor device involve a semiconductor layer that includes a first material and a second material. The first and second materials can be silicon and germanium. A contact of the device has a portion proximal to the semiconductor layer and a portion distal to the semiconductor layer. The distal portion includes the first material and the second material. A metal layer formed adjacent to the relaxed semiconductor layer and adjacent to the distal portion of the contact is simultaneously reacted with the relaxed semiconductor layer and with the distal portion of the contact to provide metallic contact material.04-26-2012
20120098053SEMICONDUCTOR DEVICE WITH VERTICAL TRANSISTOR AND METHOD FOR FABRICATING THE SAME - A semiconductor device with a vertical transistor includes a plurality of active pillars; a plurality of vertical gates surrounding sidewalls of the active pillars; a plurality of word lines having exposed sidewalls whose surfaces are higher than the active pillars and connecting the adjacent vertical gates together; and a plurality of spacers surrounding the exposed sidewalls of the word lines over the vertical gates.04-26-2012
20100032750Power Semiconductor Device And Method Therefor - A power transistor includes a plurality of transistor cells. Each transistor cell has a first electrode coupled to a first electrode interconnection region overlying a first major surface, a control electrode coupled to a control electrode interconnection region overlying the first major surface, and a second electrode coupled to a second electrode interconnection region overlying a second major surface. Each transistor cell has an approximately constant doping concentration in the channel region. A dielectric platform is used as an edge termination of an epitaxial layer to maintain substantially planar equipotential lines therein. The power transistor finds particular utility in radio frequency applications operating at a frequency greater than 500 megahertz and dissipating more than 5 watts of power. The semiconductor die and package are designed so that the power transistor can efficiently operate under such severe conditions.02-11-2010
20100264484SEMICONDUCTOR DEVICE - In a vertical transistor comprising a pillar-shaped semiconductor layer and a gate electrode formed to around the pillar-shaped semiconductor layer, it is difficult to form a transistor having a gate length greater than that of the vertical transistor. The present invention provides a semiconductor device which comprises two vertical transistors comprising first and second pillar-shaped semiconductor layers each formed on a first diffusion layer on a substrate. The vertical transistors have a common gate electrode. A first upper diffusion layer formed on a top of the first pillar-shaped semiconductor layer is connected to a source electrode, and a second upper diffusion layer formed on a top of the second pillar-shaped semiconductor layer is connected to a drain electrode. The vertical transistors are connected in series to operate as a composite transistor having a gate length two times greater than that of each of the vertical transistors.10-21-2010
20100102380METHOD OF PRODUCING PRECISION VERTICAL AND HORIZONTAL LAYERS IN A VERTICAL SEMICONDUCTOR STRUCTURE - The present invention relates to providing layers of different thickness on vertical and horizontal surfaces (04-29-2010
20090014783ULTRA-THIN BODY VERTICAL TUNNELING TRANSISTOR - A vertical tunneling, ultra-thin body transistor is formed on a substrate out of a vertical oxide pillar having active regions of opposing conductivity on opposite ends of the pillar. In one embodiment, the source region is a p+ region in the substrate under the pillar and the drain region is an n+ region at the top of the pillar. A gate structure is formed along the pillar sidewalls and over the body layers. The transistor operates by electron tunneling from the source valence band to the gate bias-induced n-type channels, along the ultra-thin silicon bodies, thus resulting in a drain current.01-15-2009
20090189217Semiconductor Memory Devices Including a Vertical Channel Transistor - Semiconductor memory devices include a semiconductor substrate and a plurality of semiconductor material pillars in a spaced relationship on the semiconductor substrate. Respective surrounding gate electrodes surround ones of the pillars. A first source/drain region is in the semiconductor substrate between adjacent ones of the pillars and a second source/drain region is in an upper portion of at least one of the adjacent pillars. A buried bit line is in the first source/drain region and electrically coupled to the first source/drain region and a storage node electrode is on the upper portion of the at least one of the adjacent pillars and electrically contacting with the second source/drain region.07-30-2009
20090152623FIN TRANSISTOR - A fin transistor includes: a substrate; a plurality of semiconductor fins formed on the substrate; a gate electrode covering a channel region of the semiconductor fins; and a member as a stress source for the semiconductor fins included in a region of the gate electrode and the region provided between the semiconductor fins, and the member being made of a different material from the gate electrode.06-18-2009
20090121283Semiconductor device and fabrication method of the same - A semiconductor device includes a substrate; a first insulating layer provided on the substrate; a conductive layer buried in the first insulating layer; a semiconductor pillar including a lower diffusion layer provided immediately above the conductive layer, the lower diffusion layer being electrically connected to the conductive layer, a semiconductor layer on the lower diffusion layer, and an upper diffusion layer on the semiconductor layer; a gate insulating film provided on a peripheral side surface of the semiconductor layer; a gate electrode provided on the gate insulating film; and a second insulating layer provided such that the gate electrode and a circumference of the semiconductor pillar are buried in the second insulating layer.05-14-2009
20120228697NONVOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A nonvolatile memory device having a vertical structure and a method of manufacturing the same, the nonvolatile memory device including a channel region that vertically extends from a substrate; gate electrodes on the substrate, the gate electrodes being disposed along an outer side wall of the channel region and spaced apart from one another; and a channel pad that extends from one side of the channel region to an outside of the channel region, the channel pad covering a top surface of the channel region.09-13-2012
20120228696STACKED DIE POWER CONVERTER - A stacked die power converter package includes a lead frame including a die pad and a plurality of package pins, a first die including a first power transistor switch (first power transistor) attached to the die pad, and a first metal clip attached to one side of the first die. The first metal clip is coupled to at least one package pin. A second die including a second power transistor switch (second power transistor) is attached to another side on the first metal clip. A controller is provided by a controller die attached to a second metal clip on one side of the second die, a controller die attached to the second die, or the controller is integrated on the second die. The controller is coupled to both a first control node of the first power transistor and a second control node of the second power transistor.09-13-2012
201101690723D NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A 3D nonvolatile memory device includes a plurality of channel structures each comprising a plurality of channel layers and interlayer dielectric layers which are alternately stacked, a plurality of channel contacts coupled to the plurality of channel layers, respectively, and a plurality of selection lines vertically-coupled to the plurality of channel contacts and crossing over the plurality of channel structures.07-14-2011
20120032255INTEGRATED CIRCUIT HAVING COMPENSATION COMPONENT - An integrated circuit and component is disclosed. In one embodiment, the component is a compensation component, configuring the compensation regions in the drift zone in V-shaped fashion in order to achieve a convergence of the space charge zones from the upper to the lower end of the compensation regions is disclosed.02-09-2012
20100181614SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a semiconductor pillar, an insulator, and an electrode. The semiconductor pillar has a semiconductor portion outwardly extending. The insulator extends along the semiconductor pillar. The insulator has an insulating portion outwardly extending along the semiconductor portion. The electrode extends along the insulator. The insulator is between the semiconductor pillar and the electrode. The electrode has an electrode portion overlapping the insulating portion in plain view. The electrode portion is under the insulating portion.07-22-2010
20120187473Edge Termination With Improved Breakdown Voltage - A MOSFET switch which has a low surface electric field at an edge termination area, and also has increased breakdown voltage. The MOSFET switch has a new edge termination structure employing an N-P-N sandwich structure. The MOSFET switch also has a polysilicon field plate configuration operative to enhance any spreading of any depletion layer located at an edge of a main PN junction of the N-P-N sandwich structure.07-26-2012
20110147829SEMICONDUCTOR DEVICE AND FABRICATION METHOD FOR THE SAME - Provided are a semiconductor device which can shorten reverse recovery time without increasing leakage current between the drain and the source, and a fabrication method for such semiconductor device.06-23-2011
20100078712SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a first semiconductor pillar, a first gate insulating film, a gate electrode, and a first contact. The first semiconductor pillar extends upwardly from a semiconductor substrate. The first gate insulating film covers side surfaces of the first semiconductor pillar. The gate electrode covers the first gate insulating film. The first gate insulating film insulates the gate electrode from the first semiconductor pillar. The first contact partially overlaps, in plane view, the first semiconductor pillar and the gate electrode. The first contact includes a silicon layer having a top level which is higher than a top level of the gate electrode.04-01-2010
20100078710Semiconductor component with a drift zone and a drift control zone - A semiconductor component has a drift zone and a drift control zone, a drift control zone dielectric, which is arranged in sections between the drift zone and the drift control zone, and has a first and a second connection zone, which are doped complementarily with respect to one another and which form a pn junction between the drift control zone and a section of the drift zone.04-01-2010
20100090272TRANSISTOR STRUCTURE HAVING A CONDUCTIVE LAYER FORMED CONTIGUOUS IN A SINGLE DEPOSITION - A semiconductor device is formed having a pedestal. The pedestal includes at least two dielectric layers. The pedestal has a sidewall and a major surface. A conductive layer is formed overlying the pedestal. A vertical portion of the conductive layer adjacent to the sidewall of the pedestal is a gate of the transistor. The portion of the conductive layer overlying the major surface can be used as interconnect. The gate and gate interconnect are contiguous and formed in a single process. A conductive shield layer may be integrated into the pedestal. The conductive shield layer functions as a faraday shield that reduces gate to drain capacitance of the device.04-15-2010
20110198688METHOD FOR FABRICATING SEMICONDUCTOR DEVICE HAVING VERTICAL-TYPE CHANNEL - A semiconductor device includes an active region including a surface region and a first recess formed below the surface region, the active region extending along a first direction; a device isolation structure provided on an edge of the active region; a gate line traversing over the surface region of the active region along a second direction orthogonal to the first direction; a second recess formed in the device isolation structure to receive a given portion of the gate line into the second recess; a first junction region formed in the active region beneath the first recess and on a first side of the gate line; and a second junction region formed on a second side of the gate line and above the first junction region. The first and second junction regions define a vertical-type channel that extends along lateral and vertical directions.08-18-2011
20100090273TRANSISTOR STRUCTURE HAVING DUAL SHIELD LAYERS - A semiconductor device is formed having lower gate to drain capacitance. A trench (04-15-2010
20090273023Segmented pillar layout for a high-voltage vertical transistor - In one embodiment, a transistor fabricated on a semiconductor die includes a first section of transistor segments disposed in a first area of the semiconductor die, and a second section of transistor segments disposed in a second area of the semiconductor die adjacent the first area. Each of the transistor segments in the first and second sections includes a pillar of a semiconductor material that extends in a vertical direction. First and second dielectric regions are disposed on opposite sides of the pillar. First and second field plates are respectively disposed in the first and second dielectric regions. Outer field plates of transistor segments adjoining first and second sections are either separated or partially merged.11-05-2009
20130099305SEMICONDUCTOR DEVICES INCLUDING A VERTICAL CHANNEL TRANSISTOR AND METHODS OF FABRICATING THE SAME - Semiconductor devices having vertical channel transistors are provided. The semiconductor device includes an insulation layer on a substrate and a buried bit line on the insulation layer. The buried bit line extends in a first direction. An active pillar is disposed on the buried bit line. The active pillar includes a lower dopant region, a channel region having a first sidewall and an upper dopant region vertically stacked on the buried bit line. A contact gate electrode is disposed to be adjacent to the first sidewall of the channel region. A word line is electrically connected to the contact gate electrode. The word line extends in a second direction intersecting the first direction. A string body connector is electrically connected to the channel region. Related methods are also provided.04-25-2013
201300993063-D NONVOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A three-dimensional (3-D) nonvolatile memory device includes a support protruded from a surface of a substrate and configured to have an inclined sidewall; channel structures each configured to comprise interlayer insulating layers and channel layers which are alternately stacked over the substrate including the support, bent along the inclined sidewall of the support, wherein each of the channel structures comprises a cell region and a contact region, and the channel layers are exposed in the contact region; select lines formed over the channel structures; and a pillar type channels coupled to respective channel layers at the contact region and penetrating the select lines.04-25-2013
20110169074VERTICAL CHANNEL TRANSISTOR AND METHOD OF FABRICATING THE SAME - A vertical channel transistor includes a plurality of active pillar patterns extending perpendicularly from the top surface of the substrate toward an upper part. A gate insulating layer is deposited on the side wall of the active pillar pattern and serves as an ion diffusion barrier between the pillar patterns and surrounding lower gate electrodes. The resultant pillar pattern structure is encapsulated with a metal. The resultant pillar pattern is surrounded on all sides by a specified height by a sacrificial layer of Spin-On Dielectric (SOD). The metal layer is etched-back to the height of the sacrificial layer, thus forming the lower gate electrodes. A spacer layer of an insulating mater is deposited surrounding the upper part of the pillar patterns and the sacrificial layer is removed exposing a part of the lower gate electrodes. The exposed gate electrode is etched to facilitate semiconductor integration.07-14-2011
20090294842METHODS OF FORMING DATA CELLS AND CONNECTIONS TO DATA CELLS - Disclosed are methods and devices, among which is a method that includes forming a lower conductive material on a substrate, forming a stop material on the substrate, forming a sacrificial material on the substrate, etching the sacrificial material with an etch that is selective to the sacrificial material and selective against the stop material, and etching the lower conductive material.12-03-2009
20110204435VERTICAL CAPACITIVE DEPLETION FIELD EFFECT TRANSISTOR - Vertical capacitive depletion field effect transistors (VCDFETs) and methods for fabricating VCDFETs are disclosed. An example VCDFET includes one or more interleaved drift and gate regions. The gate region(s) may be configured to capacitively deplete the drift region(s) though one or more insulators that separate the gate region(s) from the drift region(s). The drift region(s) may have graded/non-uniform doping profiles. In addition, one or more ohmic and/or Schottky contacts may be configured to couple one or more source electrodes to the drift region(s).08-25-2011
20100219465SEMICONDUCTOR DEVICE - A semiconductor device has a substrate, a source region formed on the surface portion of the substrate, a first insulating layer formed on the substrate, a gate electrode formed on the first insulating layer, a second insulating layer formed on the gate electrode, a body section connected with the source region, penetrating through the first insulating layer, the gate electrode and the second insulating layer, and containing a void, a gate insulating film surrounding the body section, and formed between the body section and the gate electrode, and a drain region connected with the body section.09-02-2010
20100219463QUASI-VERTICAL STRUCTURE FOR HIGH VOLTAGE MOS DEVICE - A semiconductor device provides a high breakdown voltage and a low turn-on resistance. The device includes: a substrate; a buried n+ layer disposed in the substrate; an n-epi layer disposed over the buried n+ layer; a p-well disposed in the n-epi layer; a source n+ region disposed in the p-well and connected to a source contact on one side; a first insulation layer disposed on top of the p-well and the n-epi layer; a gate disposed on top of the first insulation layer; and a metal electrode extending from the buried n+ layer to a drain contact, wherein the metal electrode is insulated from the n-epi layer and the p-well using by a second insulation layer.09-02-2010
20110024828SEMICONDUCTOR STORAGE DEVICE - An SRAM cell using a vertical MISFET is provided, wherein underside source/drain areas of a first access transistor, a first driving transistor and a first load transistor are connected together, and further connected to gates of a second driving transistor and a second load transistor. Underside source/drain areas of a second access transistor, the second driving transistor and the second load transistor are connected together, and further connected to gates of the first driving transistor and the first load transistor. A first arrangement of the first access transistor, the first driving transistor and the first load transistor, and a second arrangement of the second access transistor, the second driving transistor and the second load transistor are symmetric to each other.02-03-2011
20090008707SRAM DEVICE - An integrated circuit device has a base area defining a longitudinal axis. Four in-line transistors, which are NMOS transistors in exemplary embodiments, are each centered on the longitudinal axis. Two off-set transistors, which are PMOS transistors in exemplary embodiments, are off-set to first and second sides of the longitudinal axis, respectively.01-08-2009
20110006360SEMICONDUCTOR DEVICE HAVING 3D-PILLAR VERTICAL TRANSISTOR AND MANUFACTURING METHOD THEREOF - A semiconductor device includes: a semiconductor substrate; a silicon pillar having a side surface perpendicular to a main surface of the semiconductor substrate; a gate dielectric film that covers a side surface of the silicon pillar; a gate electrode that has an inner-circumference side surface and an outer-circumference side surface which are perpendicular to the main surface of the semiconductor substrate, and covers a side surface of the silicon pillar such that the inner-circumference side surface and the side surface of the silicon pillar face each other via the gate dielectric film; a gate-electrode protection film that covers at least a part of the outer-circumference side surface of the gate electrode; an interlayer dielectric film provided above the gate electrode and the gate-electrode protection film; and a gate contact plug that is embedded in a contact hole provided on the interlayer dielectric film and is in contact with the gate electrode and the gate-electrode protection film.01-13-2011
20090065856Semiconductor device having vertical MOS transistor and method for manufacturing the semiconductor device - In a vertical MOS transistor in which a semiconductor pillar is formed by etching a semiconductor substrate in a portion surrounded by an isolation film, the semiconductor pillar is covered with a gate insulating film and a gate electrode to be made a channel part, and diffusion layers to be a source and a drain are included on a top and a bottom of the channel part, electrode 03-12-2009
20090166726METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - There are provided a method of manufacturing a semiconductor device which is capable of narrowing only the width of a Fin channel while maintaining the widths of source and drain regions, and a semiconductor device. The method of manufacturing a semiconductor device is a method of manufacturing a Fin type transistor, including: forming STI region 07-02-2009
20090166725VERTICAL TRANSISTOR AND METHOD FOR FORMING THE SAME - A vertical transistor includes a semiconductor substrate provided with a pillar type active pattern over the surface thereof. A first tensile layer is formed over the semiconductor substrate and around the lower end portion of the pillar type active pattern, and a second tensile layer is formed over the upper end portion of the pillar type active pattern so that a tensile stress is applied in a vertical direction to the pillar type active pattern. A first junction region is formed within the surface of the semiconductor substrate below the first tensile layer and the pillar type active pattern. A gate is formed so as to surround at least a portion of the pillar type active pattern. A second junction region is formed within the upper end portion of the pillar type active pattern.07-02-2009
20080277721THIN FILM TRANSISTOR, PIXEL STRUCTURE AND FABRICATING METHOD THEREOF - A fabricating method of a TFT includes first forming a source on a substrate. Then, a first insulation pattern layer is formed to cover parts of the source and the substrate. The first insulation pattern layer has an opening exposing a part of the source. Thereafter, a gate pattern layer is formed on the first insulation pattern layer. Then, the gate pattern layer and a second insulation pattern layer formed thereon surround the opening. Moreover, a second lateral protection wall is formed on an edge of the gate pattern layer in the opening. Afterwards, a channel layer is formed in the opening and covers the second lateral protection wall and the source. Then, a passivation layer with a contact window is formed on the channel layer and the second insulation pattern layer to expose a portion of the channel layer. Thereafter, a drain is formed on the exposed channel layer.11-13-2008
20080303083SEMICONDUCTOR APPARATUS AND PRODUCTION METHOD OF THE SAME - In order to provide a highly integrated semiconductor apparatus and a production method thereof which can avoid the floating of a channel portion that causes a problem when constituting a memory cell from three-dimensional transistors, a semiconductor apparatus includes: multiple three-dimensional transistors each of which includes: a first pillar; a channel portion provided at the first pillar; diffused layers formed at both an upper portion and a lower portion of the channel portion; and a gate electrode provided around the channel portion via a gate insulation film; and a second pillar which is electrically conductive, wherein the multiple three-dimensional transistors are arranged on a well area while surrounding the second pillar, the multiple three dimensional transistors share the second pillar, and the channel portions of the multiple three dimensional transistors are each connected to the second pillar by a channel connection portion. In addition, six three-dimensional transistors preferably share the second pillar which is a single pillar.12-11-2008
20120292687SUPER JUNCTION TRANSISTOR AND FABRICATION METHOD THEREOF - A super junction transistor includes a drain substrate, an epitaxial layer, wherein the epitaxial layer is disposed on the drain substrate, a plurality of gate structure units embedded on the surface of the epitaxial layer, a plurality of trenches disposed in the epitaxial layer between the drain substrate and the gate structure units, a buffer layer in direct contact with the inner surface of the trenches, a plurality of body diffusion regions with a first conductivity type adjacent to the outer surface of the trenches, wherein there is at least a PN junction on the interface between the body diffusion region and the epitaxial layer, and a doped source region, wherein the doped source region is disposed in the epitaxial layer and is adjacent to the gate structure unit.11-22-2012
20120193702SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - In a SiC-based MISFET and a manufacturing process thereof, after the introduction of an impurity, extremely-high-temperature activation annealing is required. Accordingly, it is difficult to frequently use a self-alignment process as performed in a silicon-based MISFET manufacturing process. This results in the problem that, to control the characteristics of a device, a high-accuracy alignment technique is indispensable. In accordance with the present invention, in a semiconductor device such as a SiC-based vertical power MISFET using a silicon-carbide-based semiconductor substrate and a manufacturing method thereof, a channel region, a source region, and a gate structure are formed in mutually self-aligned relation.08-02-2012
20080290403SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes a first semiconductor layer, a second semiconductor layer provided on a major surface of the first semiconductor layer, a third semiconductor layer provided on the major surface and being adjacent to the second semiconductor layer, a termination semiconductor layer provided on the major surface of the first semiconductor layer in a termination region outside the device region, a channel stop layer, and a channel stop electrode. The channel stop layer is provided in contact with the termination semiconductor layer on the major surface of the first semiconductor layer in an outermost peripheral portion outside the termination semiconductor layer and has a higher impurity concentration than the termination semiconductor layer. The channel stop electrode is provided on at least part of a surface of the channel stop layer and projects toward the termination semiconductor layer beyond at least a superficial portion of the channel stop layer.11-27-2008
20120292688HIGHLY INTEGRATED MOS DEVICE AND THE MANUFACTURING METHOD THEREOF - A MOS semiconductor device and the manufacturing method thereof relates to a highly integrated MOS device having a three-dimensional structure. The method of manufacturing the highly integrated MOS device compromises the steps of forming a layer of gate insulator on the semiconductor substrate, planarizing surface after filling a trench with an insulating material, forming a plurality of MOS transistors on the horizontal planes of a semiconductor substrate, forming vertical planes from the semiconductor substrate, and forming a plurality of MOS transistors on the vertical planes.11-22-2012
20080265313SEMICONDUCTOR DEVICE HAVING ENHANCED PERFORMANCE AND METHOD - In one embodiment, a semiconductor device is formed in a body of semiconductor material. The semiconductor device includes a localized region of doping near a portion of a channel region where current exits during operation.10-30-2008
20100270611SEMICONDUCTOR DEVICE INCLUDING A MOS TRANSISTOR AND PRODUCTION METHOD THEREFOR - It is intended to provide a semiconductor device including a MOS transistor, comprising: a semiconductor pillar; a bottom doped region formed in contact with a lower part of the semiconductor pillar; a first gate formed around a sidewall of the semiconductor pillar through a first dielectric film therebetween; and a top doped region formed so as to at least partially overlap a top surface of the semiconductor pillar, wherein the top doped region has a top surface having an area greater than that of the top surface of the semiconductor pillar.10-28-2010
20100140688SEMICONDUCTOR DEVICE AND METHOD OF FORMING SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor pillar, a first insulating film covering a side face of the first semiconductor pillar, a first electrode covering the first insulating film, a second semiconductor pillar, a second insulating film covering a side face of the second semiconductor pillar, and a second electrode covering the second insulating film. The top level of the second electrode is higher than the top level of the first electrode.06-10-2010
20110266615SEMICONDUCTOR DEVICE - A semiconductor structure may include, but is not limited to: a semiconductor substrate; a first semiconductor structure extending upwardly over the semiconductor substrate; and a second semiconductor structure extending upwardly over the semiconductor substrate, the first and second semiconductor structures being aligned in a first <11-03-2011
20100200913SEMICONDUCTOR STORAGE DEVICE - It is intended to achieve a sufficiently-small SRAM cell area and a stable operation margin in an E/R type 4T-SRAM comprising a vertical transistor SGT. In a static type memory cell made up using four MOS transistors and two load resistor elements, each of the MOS transistor constituting the memory cell is formed on a planar silicon layer formed on a buried oxide film, to have a structure where a drain, a gate and a source are arranged in a vertical direction, wherein the gate is formed to surround a pillar-shaped semiconductor layer, and each of the load resistor elements is made of polysilicon and formed on the planar silicon layer.08-12-2010
20090184367SEMICONDUCTOR DEVICE MANUFACTURING METHOD, AND SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device in which the formation of buried wiring is facilitated includes: forming columnar patterns, which are arranged in a two-dimensional array, and bridge patterns, which connect the columnar patterns in a column direction, on a main surface of a silicon substrate; injecting an impurity in a surface portion of each of the columnar patterns and bridge patterns and in surface portions of the silicon substrate, thereby forming impurity injection layers; forming a side wall on sides of the columnar patterns and bridge patterns; removing the impurity injection layer, which has been formed in the silicon substrate, with the exception of the impurity injection layer covered by the bottom portions of the side walls; removing the side walls by etch-back; and thermally oxidizing the surface portion of the bridge patterns and then etching away the same. Buried wiring extending in the column direction of the columnar patterns is formed within the silicon substrate.07-23-2009
20120139036MANUFACTURING METHOD OF SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR APPARATUS - A screen oxide film is formed on an n− drift layer (06-07-2012
20120068258SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor device includes a first main electrode, a control electrode, an extraction electrode, a second insulating film, a plurality of contact electrodes, and a control terminal. The first main electrode is electrically connected to a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type selectively provided on a surface of the first semiconductor region. The control electrode is provided on the first semiconductor region via a first insulating film. The extraction electrode is electrically connected to the control electrode. The second insulating film is provided on the first main electrode and the extraction electrode. The plurality of contact electrodes are provided in an inside of a plurality of first contact holes formed in the second insulating film and are electrically connected to the extraction electrode. The control terminal covers portions of the first main electrode provided on the first semiconductor region, on the second semiconductor region, and on the control electrode, respectively, and the extraction electrode, is electrically connected to the plurality of contact electrodes, and is electrically insulated from the first main electrode by the second insulating film.03-22-2012
20090206396VERTICAL TRANSISTOR OF SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A vertical transistor of a semiconductor device and a method for forming the same are disclosed. The vertical transistor comprises a silicon fin disposed on a semiconductor substrate, a source region disposed in the semiconductor substrate below a lower portion of the silicon fin, a drain region disposed in an upper portion of the silicon fin, a channel region disposed in a sidewall of the silicon fin between the source region and the drain region, a gate oxide film disposed in a surface of the semiconductor substrate and the sidewall of the silicon fin, and a pair of gate electrodes disposed on the gate oxide films.08-20-2009
20110140195CROSS-POINT DIODE ARRAYS AND METHODS OF MANUFACTURING CROSS-POINT DIODE ARRAYS - Methods of forming an array of memory cells and memory cells that have pillars. Individual pillars can have a semiconductor post formed of a bulk semiconductor material and a sacrificial cap on the semiconductor post. Source regions can be between columns of the pillars, and gate lines extend along a column of pillars and are spaced apart from corresponding source regions. Each gate line surrounds a portion of the semiconductor posts along a column of pillars. The sacrificial cap structure can be selectively removed to thereby form self-aligned openings that expose a top portion of corresponding semiconductor posts. Individual drain contacts formed in the self-aligned openings are electrically connected to corresponding semiconductor posts.06-16-2011
20090101969SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device comprising: a semiconductor substrate; a first conductive layer provided on a surface of the substrate and serving as one of a source and a drain; a first insulating film provided on the first conductive layer; a gate electrode film provided on the first insulating film; a second insulating film provided on the gate electrode film; a gate opening provided so as to penetrate the second insulating film, the gate electrode film and the first insulating film to expose a part of the first conductive layer; a recess provided in the surface of the first conductive layer just below the gate opening; a gate insulator provided on the side surface of the gate opening and having a projecting shape at a portion between the first insulating film and the recess; a second conductive layer buried in the recess and in a bottom of the gate opening so as to be in contact with the gate insulator, and serving as the one of the source and the drain while being in contact with the first conductive layer; a channel which is buried in the gate opening above the second conductive layer so as to face the gate electrode film with the gate insulator therebetween, and which has a channel layer generated therein, the channel layer allowing majority carriers to flow between the source and the drain in response to a voltage applied to the gate; and a third conductive layer buried in the gate opening above the channel so as to be in contact with the gate insulator to serve as the other one of the source and the drain.04-23-2009
20120104489SEMICONDUCTOR DEVICE WITH VERTICAL GATE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a substrate; a plurality of active pillars formed over the substrate; bulb-type trenches, each of the bulb-type trenches formed inside the substrate between the active pillars; buried bit lines, each of the buried bit lines being formed on a sidewall of a respective one of the bulb-type trenches; and vertical gates, each of the vertical gates being formed to surround a sidewall of a respective one of the active pillars.05-03-2012
20120104488DATA CELLS AND CONNECTIONS TO DATA CELLS - Disclosed are devices, among which is a device that includes a transistor and a contact. The transistor includes two terminals that may be formed in respective legs. The contact includes a first portion extending vertically, and a second portion extending perpendicularly with respect to the first portion. The second portion is wider than the first portion.05-03-2012
20120104487SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device may include, but is not limited to, a transistor and a contact plug pillar of an impurity-diffused semiconductor. The transistor includes a semiconductor channel pillar having a vertical channel; and a first diffusion region adjacent to a lower portion of the semiconductor channel pillar. The contact plug pillar of an impurity-diffused semiconductor is coupled to the first diffusion region.05-03-2012
20090200604VERTICAL FIN-FET MOS DEVICES - A new class of high-density, vertical Fin-FET devices that exhibit low contact resistance is described. These vertical Fin-FET devices have vertical silicon “fins” (08-13-2009
20110227148POWER MOS TRANSISTOR DEVICE AND SWITCH APPARATUS COMPRISING THE SAME - A transistor power switch device comprising an array of vertical transistor elements for carrying current between the first and second faces of a semiconductor body and a vertical avalanche diode electrically in parallel with the array of vertical transistors. The array of transistor elements includes at the first face an array of source regions of a first semiconductor type, at least one p region of a second semiconductor type opposite to the first type interposed between the source regions and the second face, at least one control electrode for switchably controlling flow of the current through the p region, and a conductive layer contacting the source regions and insulated from the control electrode. The vertical avalanche diode is configured to conduct breakdown current between the first and second faces in the off state of the device and having a first current carrying diode region of the second semiconductor type in contact with the first face and with the conductive layer and a second semiconductor region of the first semiconductor type electrically connected with the second face.09-22-2011
20090212357SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is a semiconductor device. A well region (08-27-2009
20090242972VERTICAL CHANNEL TRANSISTOR IN SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A method of fabricating a vertical channel transistor for a semiconductor device includes forming, on a substrate, a plurality of active pillars each having a gate electrode formed on and surrounding a lower portion thereof; forming a first insulation layer over the active pillars to fill a gap region between the active pillars; partially removing the first insulation layer to exposes a circumferential surface of the gate electrode in all directions, without exposing the substrate in the gap region between the active pillars; forming a conductive layer on the remaining first insulation layer to fill the gap region between the active pillars; and patterning the conductive layer to form a word line that surrounds and contacts the circumferential surface of the gate electrode in all directions.10-01-2009
20090315102Process and system for manufacturing a MOS device with intercell ion implant - A process for manufacturing a MOS device includes forming a semiconductor layer having a first type of conductivity; forming an insulated gate structure having an electrode region (12-24-2009
20090250748Semiconductor device and method of fabricating the same - A semiconductor device and method of fabricating the same includes preparing a substrate, forming a plurality of conductive layer patterns on the substrate, forming a gate insulation layer on sidewalls of the conductive layer patterns, forming a pillar neck pattern between the conductive layer patterns, forming a pillar head over the pillar neck pattern and the conductive layer patterns, and forming a gate electrode surrounding the pillar neck pattern and forming a pillar head pattern by selectively etching the conductive layer patterns and the pillar head formed over the pillar neck pattern.10-08-2009
20120193703CROSS-POINT DIODE ARRAYS AND METHODS OF MANUFACTURING CROSS-POINT DIODE ARRAYS - Methods of forming an array of memory cells and memory cells that have pillars. Individual pillars can have a semiconductor post formed of a bulk semiconductor material and a sacrificial cap on the semiconductor post. Source regions can be between columns of the pillars, and gate lines extend along a column of pillars and are spaced apart from corresponding source regions. Each gate line surrounds a portion of the semiconductor posts along a column of pillars. The sacrificial cap structure can be selectively removed to thereby form self-aligned openings that expose a top portion of corresponding semiconductor posts. Individual drain contacts formed in the self-aligned openings are electrically connected to corresponding semiconductor posts.08-02-2012
20110101448VERTICAL TRANSISTOR AND MANUFACTURING METHOD THEREOF - A vertical transistor includes: a substrate, a bottom-oxide layer, an epitaxial silicon layer, an insulating oxide layer, two gate-oxide films and a gate-stacked layer. The bottom-oxide layer is disposed on the substrate, and the bottom-oxide layer has a gate recess concavely formed thereof. The substrate has a first doped area in an upper part corresponding to the gate recess. The epitaxial silicon layer is formed on the gate recess, and the epitaxial silicon layer has a second doped area in an upper part. The insulating oxide layer is disposed on the epitaxial silicon layer. The gate-oxide films are respectively formed on two opposite sides of the epitaxial silicon layer. The gate-stacked layer is formed on the two gate-oxide layers and the bottom-oxide layer. Whereby, the lateral area of transistor is reduced, and the integration and the performance of the device are improved.05-05-2011
20100013008SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The invention prevents a semiconductor device from warping due to heat when it is used. The invention also prevents a formation defect such as peeling of a resist layer used as a plating mask and a formation defect of a front surface electrode. A source pad electrode connected to a source region is formed on a front surface of a semiconductor substrate forming a vertical MOS transistor. A front surface electrode is formed on the source pad -electrode by a plating method using a resist layer having openings as a mask. The semiconductor substrate formed with the front surface electrode is thinned by back-grinding. A back surface electrode connected to a drain region is formed on the back surface of the semiconductor substrate. The front surface electrode and the back surface electrode are made of metals having the same coefficients of linear expansion, preferably copper. The front surface electrode and the back surface electrode preferably have the same thicknesses or almost the same thicknesses.01-21-2010
20120193704SEMICONDUCTOR DEVICE HAVING VERTICAL TRANSISTOR, MANUFACTURING METHOD THEREOF, AND DATA PROCESSING SYSTEM - A semiconductor device includes: a semiconductor substrate; a silicon pillar provided perpendicularly to a main surface of the semiconductor substrate; a gate dielectric film that covers a portion of a side surface of the silicon pillar; an insulator pillar that covers remaining portions of the side surface of the silicon pillar; a gate electrode that covers the silicon pillar via the gate dielectric film and the insulator pillar; an interlayer dielectric film provided above the silicon pillar, the gate dielectric film, the insulator pillar, and the gate electrode; and a gate contact plug embedded in a contact hole provided in the interlayer dielectric film, and in contact with the gate electrode and the insulator pillar. A film thickness of the insulator pillar in a lateral direction is thicker than a film thickness of the gate dielectric film in a lateral direction.08-02-2012
20100155831Deep trench insulated gate bipolar transistor - In one embodiment, a power transistor device comprises a substrate of a first conductivity type that forms a PN junction with an overlying buffer layer of a second conductivity type. The power transistor device further includes a first region of the second conductivity type, a drift region of the second conductivity type that adjoins a top surface of the buffer layer, and a body region of the first conductivity type. The body region separates the first region from the drift region. First and second dielectric regions respectively adjoin opposing lateral sidewall portions of the drift region. The dielectric regions extend in a vertical direction from at least just beneath the body region down at least into the buffer layer. A trench gate that controls forward conduction is disposed above the dielectric region adjacent to and insulated from the body region.06-24-2010
20100187598SEMICONDUCTOR DEVICE HAVING SWITCHING ELEMENT AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE HAVING SWITCHING ELEMENT - There is provided a semiconductor device having a switching element, including a first semiconductor layer including a first, second and third surfaces, a first electrode connected to the first semiconductor layer, a plurality of second semiconductor layers selectively configured on the first surface, a third semiconductor layer configured on the second semiconductor layer, a second electrode configured to be contacted with the second semiconductor layer and the third semiconductor layer, a gate electrode formed over the first semiconductor layer, a first region including a first tale region, a density distribution of crystalline defects being gradually increased therein, a peak region crossing a current path applying to a forward direction in a p-n junction, a second tale region continued from the peak region, and a second region including a third tale region, the density distribution of the crystalline defects being gradually increased therein.07-29-2010
20100258857Method of Forming a Layer Comprising Epitaxial Silicon, and a Field Effect Transistor - This invention includes methods of forming layers comprising epitaxial silicon, and field effect transistors. In one implementation, a method of forming a layer comprising epitaxial silicon comprises epitaxially growing a silicon-comprising layer from an exposed monocrystalline material. The epitaxially grown silicon comprises at least one of carbon, germanium, and oxygen present at a total concentration of no greater than 1 atomic percent. In one implementation, the layer comprises a silicon germanium alloy comprising at least 1 atomic percent germanium, and further comprises at least one of carbon and oxygen at a total concentration of no greater than 1 atomic percent. Other aspects and implementations are contemplated.10-14-2010
20100187601SEMICONDUCTOR DEVICE - A hermetic compressor includes a closed vessel for storing lubricating oil, an electric-driving element, and a compressing element driven by the electric-driving element. The compressing element includes a cylinder block forming a compression chamber, a piton that reciprocates inside the compression chamber, and an oiling device for supplying the lubricating oil to an outer circumference of the piston. A first oil groove is concavely formed on the outer circumference of the piston, and a second oil groove is concavely formed on a side opposite to the compression chamber relative to the first oil groove. The second oil groove has a spatial volume same or greater than that of the first oil groove. An expanded clearance portion is provided such that a clearance between the piston and the cylindrical hole portion broadens from a top dead point to a bottom dead point.07-29-2010
20130214347CIRCUIT INCLUDING VERTICAL TRANSISTORS - An electrical circuit includes a first transistor and a second transistor. Each transistor includes a substrate and a first electrically conductive material layer stack positioned on the substrate. The first electrically conductive material layer stack includes a reentrant profile. A second electrically conductive material layer includes first and second discrete portions in contact with first and second portions of a semiconductor material layer that conforms to the reentrant profile and is in contact with the electrically insulating material layer that conforms to the reentrant profile. A third electrically conductive material layer is in contact with a third portion of the semiconductor material layer and is positioned over the first electrically conductive material layer stack but is not in electrical contact with the first electrically conductive material layer stack. The third electrically conductive material layer of the first transistor and the second transistor are physically separate from each other.08-22-2013
20100187599SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - Disclosed herein is a semiconductor device including: a first conductivity type semiconductor base body; a first conductivity type pillar region; second conductivity type pillar regions; element and termination regions provided in the first and second conductivity type pillar regions, transistors being formed in the element region, and no transistors being formed in the termination region; body regions; a gate insulating film; gate electrodes; source regions; and body potential extraction regions, wherein voids are formed in the second conductivity type pillar regions of the termination region.07-29-2010
20100187600SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING THE SAME - It is an object to provide an SGT production method capable of obtaining a structure for reducing a resistance of a gate, a desired gate length, desired source and drain configurations and a desired diameter of a pillar-shaped semiconductor. The object is achieved by a semiconductor device production method which comprises the steps of: forming a pillar-shaped first-conductive-type semiconductor layer; forming a second-conductive-type semiconductor layer underneath the pillar-shaped first-conductive-type semiconductor layer; forming a gate dielectric film and a gate electrode around the pillar-shaped first-conductive-type semiconductor layer; forming a sidewall-shaped dielectric film on an upper region of a sidewall of the pillar-shaped first-conductive-type semiconductor layer and in contact with a top of the gate; forming a sidewall-shaped dielectric film on a sidewall of the gate; and forming a second-conductive-type semiconductor layer in an upper portion of the pillar-shaped first-conductive-type semiconductor layer and on the second-conductive-type semiconductor layer formed underneath the pillar-shaped first-conductive-type semiconductor layer.07-29-2010
20100013007SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device (01-21-2010
20100207202SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate, a first insulating film, a second insulating film, and a conductive layer. The semiconductor substrate includes a pillar portion extending from a main surface of the semiconductor substrate. The first insulating film covers a side surface of the pillar portion. The second insulating film covers the main surface of the semiconductor substrate. The second insulating film is thicker than the first insulating film. The conductive layer extends along the first insulating film.08-19-2010
20100207201SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREFOR - It is intended to provide a semiconductor device comprising a circuit which has a connection between one of a drain region and a source region of a first MOS transistor and one of a drain region and a source region of a second MOS transistor. The semiconductor device comprises: a substrate; a dielectric film on the substrate; and a planar semiconductor layer formed on the on-substrate dielectric film, wherein: the first MOS transistor includes a first drain or source region formed in the planar semiconductor layer, a first pillar-shaped semiconductor layer formed on the planar semiconductor layer, a second source or drain region formed in an upper portion of the first pillar-shaped semiconductor layer, and a first gate electrode formed in such a manner that the first gate electrode surrounds a sidewall of the first pillar-shaped semiconductor layer through a first dielectric film; and the second MOS transistor includes a third drain or source region formed in the planar semiconductor layer, a second pillar-shaped semiconductor layer formed on the planar semiconductor layer, a fourth source or drain region formed in an upper portion of the second pillar-shaped semiconductor layer, and a second gate electrode formed in such a manner that the second gate electrode surrounds a sidewall of the second pillar-shaped semiconductor layer through a second dielectric film, and wherein a first silicide layer is formed to connect at least a part of a surface of the first drain or source region and at least a part of a surface of the third drain or source region, wherein the first silicide layer is formed in an area other than an area in which a contact for at least the first drain or source region and the third drain or source region is formed.08-19-2010
20100237407SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - To provide a semiconductor memory device comprising a plurality of silicon pillars arranged in a matrix, whose sidewalls are provided with gate electrodes with gate insulating films interposed between the silicon pillars and the gate electrodes and whose top ends are electrically connected to memory elements, and a bit line and a word line provided between the silicon pillars so as to be orthogonal to each other. The bit line is electrically connected to a bottom end of the silicon pillars on both sides of the bit line in alternate rows, and the word line is electrically connected to a gate electrode formed on a sidewall of the silicon pillars on both sides of the word line in alternate columns.09-23-2010
20100252879Semiconductor device and method of forming the same - A semiconductor device includes a semiconductor substrate; a well of a first conductivity type in the semiconductor substrate; a first element; and a first vertical transistor. The first element supplies potential to the well, the first element being in the well. The first element may include, but is not limited to, a first pillar body of the first conductivity type. The first pillar body has an upper portion that includes a first diffusion layer of the first conductivity type. The first diffusion layer is greater in impurity concentration than the well. The first vertical transistor is in the well. The first vertical transistor may include a second pillar body of the first conductivity type. The second pillar body has an upper portion that includes a second diffusion layer of a second conductivity type.10-07-2010
20100237405SEMICONDUCTOR DEVICE WITH VERTICAL TRANSISTOR AND METHOD FOR FABRICATING THE SAME - A semiconductor device with a vertical transistor includes a plurality of active pillars, a plurality of vertical gates surrounding sidewalls of the active pillars; a plurality of word lines having exposed sidewalls whose surfaces are higher than the active pillars and connecting the adjacent vertical gates together, and a plurality of spacers surrounding the exposed sidewalls of the word lines over the vertical gates.09-23-2010
20100148246Power mosfet device structure for high frequency applications - This invention discloses a new switching device supported on a semiconductor that includes a drain disposed on a first surface and a source region disposed near a second surface of said semiconductor opposite the first surface. The switching device further includes an insulated gate electrode disposed on top of the second surface for controlling a source to drain current. The switching device further includes a source electrode interposed into the insulated gate electrode for substantially preventing a coupling of an electrical field between the gate electrode and an epitaxial region underneath the insulated gate electrode. The source electrode further covers and extends over the insulated gate for covering an area on the second surface of the semiconductor to contact the source region. The semiconductor substrate further includes an epitaxial layer disposed above and having a different dopant concentration than the drain region. The insulated gate electrode further includes an insulation layer for insulating the gate electrode from the source electrode wherein the insulation layer having a thickness depending on a Vgsmax rating of the vertical power device.06-17-2010
20100237406SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor memory device includes a silicon pillar that is provided with a first channel formed in a first area on one side among two sides that are perpendicular to an extension direction of a bit line, a second channel formed in a second area on the other side among the two sides that is not overlapped with the first area in the extension direction of the bit line, and of which the other area on the two sides is an insulating oxide film formed by being oxidized, and two word lines that cover the one side and the other side of the silicon pillar via a gate insulating film, respectively. The first channel and the second channel are separated from each other in an insulating manner by the insulating oxide film.09-23-2010
20110006361Integrated Power Supplies and Combined High-Side Plus Low-Side Switches - The present application discloses new approaches to integrated power. Two new classes of structures each provide an integrated phase leg, in a process which can easily be integrated with low-voltage and/or peripheral circuits: in one class of disclosed structures, a lateral PMOS device is combined with an NMOS device which has predominantly vertical current flow. In another class of embodiments, a predominantly vertical n-channel device is used for the low-side switch, in combination with a lateral n-channel device. In either case, the common output node is preferably brought out at a backside contact. This device structure is advantageously used to construct complete power supply and/or voltage conversions circuits on a single chip (perhaps connected to external passive reactances).01-13-2011
20110057256SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a first conductive type semiconductor substrate; a first conductive type semiconductor region provided thereon in which first conductive type first pillar regions and second conductive type second pillar regions alternately arranged; second conductive type second semiconductor regions provided on second pillar regions in an element region to be in contact with first pillar regions therein; gate electrodes each provided on adjacent second semiconductor regions and on one of the first pillar region interposed therebetween; third semiconductor regions functioning as a first conductive type source region provided in parts of the second semiconductor regions located under side portions of the gate electrodes; and a second conductive type resurf region which is a part of a terminal region surrounding the element region and which is provided on first pillar regions and second pillar regions in the part of the terminal regions.03-10-2011
20110057255SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a first conductive type semiconductor substrate; a first conductive type semiconductor region provided thereon in which first conductive type first pillar regions and second conductive type second pillar regions alternately arranged; second conductive type second semiconductor regions provided on second pillar regions in an element region to be in contact with first pillar regions therein; gate electrodes each provided on adjacent second semiconductor regions and on one of the first pillar region interposed therebetween; third semiconductor regions functioning as a first conductive type source region provided in parts of the second semiconductor regions located under side portions of the gate electrodes; and a second conductive type resurf region which is a part of a terminal region surrounding the element region and which is provided on first pillar regions and second pillar regions in the part of the terminal regions.03-10-2011
20130126962SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device and a method of manufacturing the same are provided. After spacers are formed on sidewalls of a pillar pattern and a photoresist pattern exposing an OSC formation region is formed on a semiconductor substrate including the pillar pattern and the spacer, processes for removing a spacer corresponding to the OSC formation region to form an OSC, removing the photoresist pattern, forming a bit line between the pillar patterns, an epitaxial layer on the pillar pattern, and forming a vertical gate and a storage node contact, are performed so that the OSC formation process can be simplified. In addition, the OSC formation process is performed in a state that the pillar pattern has a low height so that a failure such as a not-open failure caused in the OSC formation process can be prevented.05-23-2013
20100052046SEMICONDUCTOR STRUCTURES FORMED ON SUBSTRATES AND METHODS OF MANUFACTURING THE SAME - A semiconductor apparatus includes a metal substrate, a doped silicon layer on the metal substrate, a semiconductor layer overlying the doped silicon layer, and semiconductor structures having one or more p-n junctions at least partially within the semiconductor layer formed by using layering, patterning, and doping steps. In an embodiment, the doped silicon layer comprises a heavily doped silicon layer. In another embodiment, the doped silicon region has a thickness that is less than a thickness of a cleavable region formed by ion implantation. In a specific embodiment, the thickness of the cleavable region is about 1-2 um. In another embodiment, the semiconductor layer has a thickness of approximately 10 um. In another embodiment, the semiconductor structures includes a vertical power MOSFET with the metal substrate configured to be a drain terminal contact region.03-04-2010
20100200912Mosfets with terrace irench gate and improved source-body contact - A trench MOSFET with terrace gates and improved source-body contact structure is disclosed. When refilling the gate trenches, the deposited polysilicon layer is higher than the sidewalls of the trenches to be used as terrace gates of the MOSFET, and the improved source-body contact structure can enlarge the P+ area below to wrap the sidewalls and bottom of source-body contact within P body region to further enhance the avalanche capability.08-12-2010
20090179258NITRIDE SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING NITRIDE SEMICONDUCTOR DEVICE - A nitride semiconductor device includes: a nitride semiconductor structure portion including a first layer made of an n-type group III nitride semiconductor, a second layer made of a group III nitride semiconductor containing a p-type impurity provided on the first layer and an n-type region formed on a part of the second layer, and having a wall surface extending over the first layer, a body region of the second layer other than the n-type region and the n-type region; a gate insulating film formed such that the gate insulating film is opposed to the body region on the wall surface; a gate electrode formed such that the gate electrode is opposed to the body region through the gate insulating film; a source electrode formed such that the source electrode is electrically connected to the n-type region; a drain electrode formed such that the drain electrode is electrically connected to the first layer; and a body electrode formed such that the body electrode is electrically connected to the body region.07-16-2009
20090114981SEMICONDUCTOR DEVICE WITH VERTICAL CHANNEL TRANSISTOR AND METHOD FOR FABRICATING THE SAME - In a high speed vertical channel transistor, a pillar structure is formed over a substrate, a gate electrode surrounds an outer wall of a lower portion of the pillar structure; and a word line extends in a direction to partially contact an outer wall of the gate electrode. The word line shifts toward a side of the pillar structure resulting in increased transistor speed.05-07-2009
20090039421Nitride semiconductor device and method for producing nitride semiconductor device - A nitride semiconductor device of the present invention includes a nitride semiconductor laminated structure comprising an n type first layer, a second layer containing a p type dopant laminated on the first layer, and an n type third layer laminated on the second layer, each layer of the nitride semiconductor laminated structure made of a group III nitride semiconductor, and the nitride semiconductor laminated structure having a wall surface extending the first, through the second, to the third layers; a gate insulating film formed on the wall surface such that the gate insulating film extends for the first, second, and third layers; a gate electrode formed such that the gate electrode is opposed to the wall surface of the second layer with the gate insulating film sandwiched between the gate electrode and the wall surface;02-12-2009
20080303084Vertical Tunneling Transistor - The disclosed embodiments relate to a vertical tunneling transistor that may include a channel disposed on a substrate. A quantum dot may be disposed so that an axis through the channel and the quantum dot is substantially perpendicular to the substrate. A gate may be disposed so that an axis through the channel, the quantum dot and the gate is substantially perpendicular to the substrate.12-11-2008
20100219462MOS-Gated Power Devices, Methods, and Integrated Circuits - MOS-gated devices, related methods, and systems for vertical power and RF devices including an insulated trench and a gate electrode. A body region is positioned so that a voltage bias on the gate electrode will cause an inversion layer in the body region. Permanent electrostatic charges are included in said insulation material. A conductive shield layer is positioned above the insulated trench, to reduce parasitic capacitances.09-02-2010
20090108339HIGH VOLTAGE TMOS SEMICONDUCTOR DEVICE WITH LOW GATE CHARGE STRUCTURE AND METHOD OF MAKING - A TMOS device (04-30-2009
20090072302Gate metal routing for transistor with checkerboarded layout - In one embodiment, a transistor fabricated on a semiconductor die is arranged into sections of elongated transistor segments. The sections are arranged in rows and columns substantially across the semiconductor die. Adjacent sections in a row or a column are oriented such that the length of the transistor segments in a first one of the adjacent sections extends in a first direction, and the length of the transistor segments in a second one of the adjacent sections extends in a second direction, the first direction being substantially orthogonal to the second direction. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.03-19-2009
20100219464PRODUCTION METHOD FOR SEMICONDUCTOR DEVICE - Disclosed is a semiconductor device production method, which comprises the steps of: forming a pillar-shaped first-conductive-type semiconductor layer on a planar semiconductor layer; forming a second-conductive-type semiconductor layer in a portion of the planar semiconductor layer underneath the pillar-shaped first-conductive-type semiconductor layer; forming a gate dielectric film and a gate electrode having a laminated structure of a metal film and an amorphous silicon or polysilicon film, around the pillar-shaped first-conductive-type semiconductor layer; forming a sidewall-shaped dielectric film on an upper region of a sidewall of the pillar-shaped first-conductive-type semiconductor layer and in contact with a top of the gate electrode; forming first and second sidewall-shaped dielectric films on a sidewall of the gate electrode; forming a second-conductive-type semiconductor layer in an upper portion of the pillar-shaped first-conductive-type semiconductor layer; forming a metal-semiconductor compound on the second-conductive-type semiconductor layer formed in the portion of the planar semiconductor layer underneath the pillar-shaped first-conductive-type semiconductor layer; forming a metal-semiconductor compound on the second-conductive-type semiconductor layer formed in the upper portion of the pillar-shaped first-conductive-type semiconductor layer; forming a metal-semiconductor compound on the gate electrode; forming a contact on the second-conductive-type semiconductor layer formed in the portion of the planar semiconductor layer underneath the pillar-shaped first-conductive-type semiconductor layer; and forming a contact on the second-conductive-type semiconductor layer formed in the upper portion of the pillar-shaped first-conductive-type semiconductor layer.09-02-2010
20090108341SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A method of fabricating a semiconductor device includes forming a first vertical pillar over a semiconductor substrate. A spacer is formed over a sidewall of the first vertical pillar. A portion of the semiconductor substrate exposed between the first vertical pillars is etched to form a recess that exposes a second vertical pillar extending below from the first vertical pillar. A sacrificial film is formed over the semiconductor substrate including the recess and a sidewall of the first vertical pillar to fill the recess, the second vertical pillar and the first vertical pillar. A supporting layer is deposited over the sacrificial film and the first vertical pillar. The supporting layer is patterned to form a supporting pattern connecting the first vertical pillar with each other. The sacrificial film is removed to expose the second vertical pillar. A surrounding gate is formed over a sidewall of the second vertical pillar.04-30-2009
20090108340SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A method of fabricating a semiconductor device includes forming a mask pattern over a semiconductor substrate to define a channel region. A portion of the semiconductor substrate is etched using the mask pattern as an etching mask to form a first pillar. A spacer is formed over a sidewall of the mask pattern and the first pillar. A portion of the semiconductor substrate exposed between the first pillars is etched using the spacer and the mask pattern as an etching mask to form a second pillar elongated from the first pillar. A portion of the second pillar is selectively etched to form a third pillar. The spacer and the mask pattern are removed. An impurity is implanted into an upper part of the first pillar and the semiconductor substrate between the third pillars to form a source/drain region. A surrounding gate is formed over an outside of the third pillar.04-30-2009
20100295119VERTICALLY-ORIENTED SEMICONDUCTOR SELECTION DEVICE FOR CROSS-POINT ARRAY MEMORY - A vertical semiconductor material mesa upstanding from a semiconductor base that forms a conductive channel between first and second doped regions. The first doped region is electrically coupled to one or more first silicide layers on the surface of the base. The second doped region is electrically coupled to a second silicide layer on the upper surface of the mesa. A gate conductor is provided on one or more sidewalls of the mesa.11-25-2010
20100295121SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - To provide a semiconductor device including a first silicon pillar, an interlayer dielectric film provided on an upper surface of the first silicon pillar and having a through-hole filled with a conductive material, and a first-diffusion-layer contact plug provided on an upper-side opening of the through-hole. An area of a lower-side opening of the through-hole is equal to an area of the upper surface of the first silicon pillar, and an area of the upper-side opening of the through-hole is larger than the area of the lower-side opening of the through-hole. With this configuration, an area of a contact surface between the conductive material within the through-hole and the first-diffusion-layer contact plug is larger than the area of the upper surface of the first silicon pillar.11-25-2010
20100301407SEMICONDUCTOR DEVICE HAVING VERTICAL CHANNEL TRANSISTOR AND MANUFACTURING METHOD OF THE SAME - A semiconductor device having a vertical channel transistor and a method for manufacturing the same are provided. In the semiconductor device, a metal bit line is formed between vertical channel transistors, and the metal bit line is connected to only one of the vertical channel transistors through an asymmetric bit line contact. Through such a structure, the resistance of the bit line can be improved and the process margin for formation of the bit line can be secured.12-02-2010
20110108909VERTICAL THIN FILM TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME AND DISPLAY DEVICE INCLUDING THE VERTICAL THIN FILM TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME - A vertical thin film transistor and a method for manufacturing the same and a display device including the vertical thin film transistor and a method for manufacturing the same are disclosed. The vertical thin film transistor is applied to a substrate. In the present invention, a gate layer of the vertical thin film transistor is formed to have a plurality of concentric annular structures and the adjacent concentric annular structures are linked. By the concentric annular structures of the gate electrode layer, resistance to stress and an on-state current of the vertical thin film transistor can be increased.05-12-2011
20110018055POWER SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a power semiconductor device includes a first semiconductor layer, and first, second and third semiconductor regions. The first semiconductor layer has a first conductivity type. The first semiconductor regions have a second conductivity type, and are formed with periodicity in a lateral direction in a second semiconductor layer of the first conductivity type. The second semiconductor layer is provided on a major surface of the first semiconductor layer in a device portion with a main current path formed in a vertical direction generally perpendicular to the major surface and in a terminal portion provided around the device portion. The second semiconductor region has the first conductivity type and is a portion of the second semiconductor layer sandwiched between adjacent ones of the first semiconductor regions. The third semiconductor regions have the second conductivity type and are provided below the first semiconductor regions in the terminal portion.01-27-2011
20110108910SEMICONDUCTOR DEVICE - A semiconductor device may include, but is not limited to: a semiconductor structure extending upwardly; a first insulating film covering at least a side surface of the semiconductor structure; a gate electrode extending upwardly, the gate electrode being adjacent to the first insulating film; and an insulating structure extending upwardly, the insulating structure being adjacent to the gate electrode.05-12-2011
20090065857RAISED VERTICAL CHANNEL TRANSISTOR DEVICE - A method for fabricating a vertical channel transistor device is provided. An opening is formed in a dielectric stack comprised of a pad nitride layer and a pad oxide layer. A plurality of epitaxial silicon growth and dry etching processes are carried out to form drain, vertical channel and source in the opening. Subsequently, sidewall gate dielectric and sidewall gate electrode are formed on the vertical channel. The present invention is suited for dynamic random access memory (DRAM) devices, particularly suited for very high-density trench-capacitor DRAM devices.03-12-2009
20110042740SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREOF - A method for producing a semiconductor device includes preparing a structure having a substrate, a planar semiconductor layer and a columnar semiconductor layer, forming a second drain/source region in the upper part of the columnar semiconductor layer, forming a contact stopper film and a contact interlayer film, and forming a contact layer on the second drain/source region. The step for forming the contact layer includes forming a pattern and etching the contact interlayer film to the contact stopper film using the pattern to form a contact hole for the contact layer and removing the contact stopper film remaining at the bottom of the contact hole by etching. The projection of the bottom surface of the contact hole onto the substrate is within the circumference of the projected profile of the contact stopper film formed on the top and side surface of the columnar semiconductor layer onto the substrate.02-24-2011
20110042739MOS DEVICE RESISTANT TO IONIZING RADIATION - An embodiment of a MOS device resistant to ionizing-radiation, has: a surface semiconductor layer with a first type of conductivity; a gate structure formed above the surface semiconductor layer, and constituted by a dielectric gate region and a gate-electrode region overlying the dielectric gate region; and body regions having a second type of conductivity, formed within the surface semiconductor layer, laterally and partially underneath the gate structure. In particular, the dielectric gate region is formed by a central region having a first thickness, and by side regions having a second thickness, smaller than the first thickness; the central region overlying an intercell region of the surface semiconductor layer, set between the body regions.02-24-2011
20100163974SEMICONDUCTOR DEVICE WITH VERTICAL CHANNEL TRANSISTOR AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device including a vertical channel transistor includes providing a substrate including a semiconductor pillar, forming a gate electrode surrounding the semiconductor pillar, forming an impurity region for a bit line by doping impurities into the substrate and forming a device isolation trench by etching a portion of the substrate including the impurity region to a certain depth, thereby defining the bit line, wherein the impurity doping is performed with given concentration so as to form the impurity region under the semiconductor pillar.07-01-2010
20110241104INTEGRATED CIRCUIT DEVICE AND METHOD FOR ITS PRODUCTION - An integrated circuit device includes a semiconductor body fitted with a first electrode and a second electrode on opposite surfaces. A control electrode on an insulating layer controls channel regions of body zones for a current flow between the two electrodes. A drift section adjoining the channel regions comprises drift zones and charge compensation zones. A part of the charge compensation zones includes conductively connected charge compensation zones electrically connected to the first electrode. Another part includes nearly-floating charge compensation zones, so that an increased control electrode surface has a monolithically integrated additional capacitance C10-06-2011
20110241102SEMICONDUCTOR DEVICES INCLUDING BIT LINE CONTACT PLUG AND BURIED CHANNEL ARRAY TRANSISTOR, METHODS OF FABRICATING THE SAME, AND SEMICONDUCTOR MODULES, ELECTRONIC CIRCUIT BOARDS AND ELECTRONIC SYSTEMS INCLUDING THE SAME - A semiconductor device having a cell area and a peripheral area includes a semiconductor substrate, a cell insulating isolation region delimiting a cell active region of the semiconductor substrate in the cell area, a word line disposed within the semiconductor substrate in the cell area, a bit line contact plug disposed on the cell active region, a bit line disposed on the bit line contact plug, a peripheral insulating isolation region delimiting a peripheral active region of the semiconductor substrate in the peripheral area, and a peripheral transistor including a peripheral transistor lower electrode and a peripheral transistor upper electrode. The bit line contact plug is formed at the same level in the semiconductor device as the peripheral transistor lower electrode, and the bit line electrode is formed at the same level in the semiconductor device as the peripheral transistor upper electrode.10-06-2011
20100013005INTEGRATED CIRCUIT INCLUDING A VERTICAL TRANSISTOR AND METHOD - An integrated circuit including a vertical transistor and method of manufacturing. In one embodiment a vertical transistor is formed in a pillar of a semiconductor substrate. A buried conductive line is separated from the semiconductor substrate by a first insulating layer in a first portion and is electrically coupled to a buried source/drain region of the vertical transistor through a contact structure. A second insulating layer is arranged above and adjacent to the contact structure. At least one of the first and second insulating layers includes a dopant. A doped region is formed in the semiconductor substrate at an interface to the at least one insulating layer. The doped region has a dopant concentration higher than a substrate dopant concentration.01-21-2010
20100013006SEMICONDUCTOR DEVICE - A semiconductor device has a semiconductor substrate having a surface layer and a p-type semiconductor region, wherein the surface layer includes a contact region, a channel region and a drift region, the channel region is adjacent to and in contact with the contact region, the drift region is adjacent to and in contact with the channel region and includes n-type impurities at least in part, and the p-type semiconductor region is in contact with the drift region and at least a portion of a rear surface of the channel region, a main electrode disposed on the surface layer and electrically connected to the contact region, a gate electrode disposed on the surface layer and extending from above a portion of the contact region to above at least a portion of the drift region via above the channel region, and an insulating layer covering at least the portion of the contact region and not covering at least the portion of the drift region. The gate electrode and the contact region are insulated by the insulating layer, and the gate electrode and the drift region are in direct contact to form a Schottky junction.01-21-2010
20100038709VERTICAL TRANSISTOR AND ARRAY WITH VERTICAL TRANSISTORS - A vertical transistor includes a substrate, a semiconductor structure, a gate, a gate dielectric layer, and a conductive layer. The semiconductor structure is disposed on the substrate and includes two vertical plates and a bottom plate. The bottom plate has an upper surface connected to bottoms of the two vertical plates and a bottom surface connected to the substrate. The gate surrounds the semiconductor structure to fill between the two vertical plates, and the gate is disposed around the two vertical plates. The gate dielectric layer is sandwiched in between the gate and the semiconductor structure, and the conductive layer is disposed on the semiconductor structure and electrically connected with tops of the two vertical plates.02-18-2010
20100065903High-voltage vertical transistor with a varied width silicon pillar - In one embodiment, a vertical HVFET includes a pillar of semiconductor material a pillar of semiconductor material arranged in a loop layout having at least two substantially parallel and substantially linear fillet sections each having a first width, and at least two rounded sections, the rounded sections having a second width narrower than the first width, a source region of a first conductivity type being disposed at or near a top surface of the pillar, and a body region of a second conductivity type being disposed in the pillar beneath the source region. First and second dielectric regions are respectively disposed on opposite sides of the pillar, the first dielectric region being laterally surrounded by the pillar, and the second dielectric region laterally surrounding the pillar. First and second field plates are respectively disposed in the first and second dielectric regions.03-18-2010
20110175161Advanced Forming Method and Structure of Local Mechanical Strained Transistor - Embodiments of the invention provide a semiconductor fabrication method and a structure for strained transistors. A method comprises forming a stressor layer over a MOS transistor. The stressor layer is selectively etched over the gate electrode, thereby affecting strain conditions within the MOSFET channel region. An NMOS transistor may have a tensile stressor layer, and a PMOS transistor may have compressive stressor layer.07-21-2011
20110175160SHORT-CHANNEL SCHOTTKY-BARRIER MOSFET DEVICE AND METHOD OF MANUFACTURE - A MOSFET device and method of fabricating are disclosed. The present invention utilizes Schottky barrier contacts for source and/or drain contact fabrication within the context of a MOSFET device structure to eliminate the requirement for halo/pocket implants and shallow source/drain extensions to control short channel effects. Additionally, the present invention unconditionally eliminates the parasitic bipolar gain associated with MOSFET fabrication, reduces manufacturing costs, tightens control of device performance parameters, and provides for superior device characteristics as compared to the prior art.07-21-2011
20110101447SEMICONDUCTOR DEVICE WITH BURIED BIT LINES AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a substrate having trenches, buried bit lines formed in the substrate, and including a metal silicide layer and a metallic layer, wherein the metal silicide layer contacts sidewalls of the trenches and the metallic layer is formed over the sidewalls of the trenches and contacts the metal silicide layer.05-05-2011
20110101449ASYMMETRIC FIELD EFFECT TRANSISTOR STRUCTURE AND METHOD - Disclosed are embodiments of an asymmetric field effect transistor structure and a method of forming the structure in which both series resistance in the source region (R05-05-2011
20110068388SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - An object is to provide a high reliability thin film transistor using an oxide semiconductor layer which has stable electric characteristics. In the thin film transistor in which an oxide semiconductor layer is used, the amount of change in threshold voltage of the thin film transistor before and after a BT test is made to be 2 V or less, preferably 1.5 V or less, more preferably 1 V or less, whereby the semiconductor device which has high reliability and stable electric characteristics can be manufactured. In particular, in a display device which is one embodiment of the semiconductor device, a malfunction such as display unevenness due to change in threshold voltage can be reduced.03-24-2011
20110248335SEMICONDUCTOR DEVICE - A semiconductor device includes: a first conductivity type semiconductor substrate; and a plurality of second conductivity type semiconductor regions, the respective second conductivity type semiconductor regions being embedded in a plurality of stripe shaped trenches formed in the semiconductor substrate so that the respective second conductivity type semiconductor regions are extended in the row direction or the column direction in parallel with a first principal surface of the semiconductor substrate and are spaced in a fixed gap mutually. The semiconductor substrate and the plurality of the semiconductor regions are depleted by a depletion layer extended in the direction in parallel to the first principal surface from a plurality of pn junction interfaces, and the respective pn junction interfaces are formed between the semiconductor substrate and the plurality of the semiconductor regions.10-13-2011
20100264485SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - This invention provides a method of manufacturing a semiconductor device, which comprises the steps of: forming a first columnar semiconductor layer on a first flat semiconductor layer; forming a first semiconductor layer of a second conductive type in a lower portion of the first columnar semiconductor layer; forming a first insulating film around a lower sidewall of the first columnar silicon layer; forming a gate insulating film and a gate electrode around the first columnar silicon layer; forming a sidewall-shaped second insulating film to surround an upper sidewall of the first columnar silicon layer; forming a semiconductor layer of a first conductive type between the first semiconductor layer of the second conductive type and a second semiconductor layer of the second conductive type; and forming a metal-semiconductor compound on an upper surface of the first semiconductor layer of the second conductive type.10-21-2010
20100078711METHOD OF MANUFACTURING INTEGRATED CIRCUITS INCLUDING A FET WITH A GATE SPACER - A method of manufacturing integrated circuits including a FET with a gate spacer. One embodiment provides forming a lamella of a semiconductor material and two insulator structures on opposing sides of the lamella. The lamella is recessed. A fin is formed from a central portion of the lamella. The fin is thinner than a first and a second portion of the lamella which face each other on opposing sides of the fin. A first spacer structure is formed which encompasses a first portion of the fin, the first portion adjoining to the first lamella portion. A gate electrode is disposed adjacent to the first spacer structure and encompasses a further portion of the fin on a top side and on two opposing lateral sides.04-01-2010
20080315300Semiconductor device and method for manufacturing semiconductor device - A semiconductor device includes: a semiconductor substrate having a substrate surface; a spiral body constituted by a linear semiconductor layer on which a body region including a channel region, a first source/drain region disposed on the body region, and a second source/drain region disposed under the body region or in the semiconductor substrate around the linear semiconductor layer are formed, the linear semiconductor layer being formed on the substrate surface substantially in a spiral form viewed from the substrate surface in a plan view, formed substantially in a protrudent form in a cross-sectional view, and having a pair of sidewall portions; a gate insulating film formed on at least the pair of sidewall portions constituting the linear semiconductor layer; and a gate electrode that is adjacent to the pair of sidewall portions via the gate insulating film.12-25-2008
20080315299SEMICONDUCTOR DEVICE - A semiconductor device includes a first first-conductivity-type semiconductor layer, a second first-conductivity-type semiconductor layer provided on a major surface of the first first-conductivity-type semiconductor layer; a third second-conductivity-type semiconductor layer being adjacent to the second first-conductivity-type semiconductor layer, provided on the major surface of the first first-conductivity-type semiconductor layer, and forming a periodic array structure in combination with the second first-conductivity-type semiconductor layer in a horizontal direction generally parallel to the major surface of the first first-conductivity-type semiconductor layer, and a sixth semiconductor layer located outside and adjacent to the periodic array structure of the second first-conductivity-type semiconductor layer and the third second-conductivity-type semiconductor layer, provided on the major surface of the first first-conductivity-type semiconductor layer, and having a lower impurity concentration than the periodic array structure. The amount of impurity in the outermost semiconductor layer of the first conductivity type or the second conductivity type adjacent to the sixth semiconductor layer in the periodic array structure is generally half the amount of impurity in the second first-conductivity-type semiconductor layer or the third second-conductivity-type semiconductor layer inside the outermost semiconductor layer.12-25-2008
20090166727POWER SEMICONDUCTOR HAVING A LIGHTLY DOPED DRIFT AND BUFFER LAYER - A power semiconductor element having a lightly doped drift and buffer layer is disclosed. One embodiment has, underneath and between deep well regions of a first conductivity type, a lightly doped drift and buffer layer of a second conductivity type. The drift and buffer layer has a minimum vertical extension between a drain contact layer on the adjacent surface of a semiconductor substrate and the bottom of the deepest well region which is at least equal to a minimum lateral distance between the deep well regions. The vertical extension can also be determined such that a total amount of dopant per unit area in the drift and buffer layer is larger then a breakdown charge amount at breakdown voltage.07-02-2009
20110254081SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - In a method of fabricating a semiconductor device on a substrate which includes a plurality of pillar patterns, an impurity region between adjacent pillar patterns, a gate electrode on each pillar pattern, a first capping layer covering the gate electrode, and a separation layer covering the first capping layer between the gate electrodes of adjacent pillar patterns, the first capping layer is removed except for a portion contacting the separation layer, a sacrificial layer is formed to cover the gate electrode, a second capping layer is formed on sidewalls of each pillar pattern, the sacrificial layer is removed and a word line connecting the gate electrodes of the adjacent pillar patterns is formed. In the manufactured device, the first capping layer isolates the impurity region from the word line and the second capping region prevents the sidewalls of the respective pillar pattern from being exposed.10-20-2011
20080203471NITRIDE SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING NITRIDE SEMICONDUCTOR DEVICE - The nitride semiconductor device includes: a nitride semiconductor structure comprising an n-type first layer, a p-type second layer, and an n-type third layer, the nitride semiconductor structure comprising a mesa structure having a lateral surface which forms a wall surface extending from the first, second, to third layers; a gate insulating film formed on the wall surface of the mesa structure; a gate electrode formed as facing the wall surface in the second layer; a drain electrode electrically connected to the first layer; and a source electrode electrically connected to the third layer, the nitride semiconductor structure having a high dislocation region and a low dislocation region arranged along a direction parallel to a principal surface of lamination of the nitride semiconductor structure, a dislocation density of the low dislocation region being lower than that of the high dislocation region, the mesa structure being formed in the low dislocation region.08-28-2008
20130168759FIELD EFFECT TRANSISTOR WITH A VERTICAL CHANNEL AND FABRICATION METHOD THEREOF - Disclosed herein is a field effect transistor with a vertical channel and a fabrication method thereof. A channel region of the field effect transistor is a circular ring-shaped Si platform, which is formed over a substrate and perpendicular to the substrate; a source, which is made of polysilicon, is located at an upper end of the Si platform; a drain is disposed at an outside of a lower end of the circular ring-shaped Si platform; a gate is placed on an outer side surface of the circular ring-shaped Si platform; and an inside of the circular ring-shaped Si platform is filled with a dielectric material. In comparison with the conventional vertical structure MOSFET with a Si platform, the circular ring-shaped structure field effect transistor according to the invention can effectively suppress the short channel effect and improve the device performance.07-04-2013
20130168758SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method for manufacturing the same are disclosed, in which a buried gate region is formed, a nitride film spacer is formed at sidewalls of the buried gate region, and the spacer is etched in an active region in such a manner that the spacer remains in a device isolation region. Thus, if a void occurs in the device isolation region, the spacer can prevent a short-circuit from occurring between the device isolation region and its neighboring gates.07-04-2013
20100320531STANDING CHIP SCALE PACKAGE - A standing chip scale package is disclosed. The standing chip scale package provides electrical connection to bumped device contacts on both sides of the chip. The package is coupleable to a printed circuit board in a standing configuration such that front and back sides of the bumped chip are substantially perpendicular to a mounting surface. A process of fabricating the standing chip scale package is also disclosed.12-23-2010
20100320530METHODS OF MAKING VERTICAL JUNCTION FIELD EFFECT TRANSISTORS AND BIPOLAR JUNCTION TRANSISTORS WITHOUT ION IMPLANTATION AND DEVICES MADE THEREWITH - Methods of making semiconductor devices such as vertical junction field effect transistors (VJFETs) or bipolar junction transistors (BJTs) are described. The methods do not require ion implantation. The VJFET device has an epitaxially regrown n-type channel layer and an epitaxially regrown p-type gate layer as well as an epitaxially grown buried gate layer. Devices made by the methods are also described.12-23-2010
20100283102VERTICAL CHANNEL TRANSISTOR IN SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A method of fabricating a vertical channel transistor for a semiconductor device includes forming, on a substrate, a plurality of active pillars each having a gate electrode formed on and surrounding a lower portion thereof; forming a first insulation layer over the active pillars to fill a gap region between the active pillars; partially removing the first insulation layer to exposes a circumferential surface of the gate electrode in all directions, without exposing the substrate in the gap region between the active pillars; forming a conductive layer on the remaining first insulation layer to fill the gap region between the active pillars; and patterning the conductive layer to form a word line that surrounds and contacts the circumferential surface of the gate electrode in all directions.11-11-2010
20100295120VERTICALLY-ORIENTED SEMICONDUCTOR SELECTION DEVICE PROVIDING HIGH DRIVE CURRENT IN CROSS-POINT ARRAY MEMORY - A vertical semiconductor material mesa upstanding from a semiconductor base that forms a conductive channel between first and second doped regions. The first doped region is electrically coupled to one or more first silicide layers on the surface of the base. The second doped region is electrically coupled to one of a plurality of second silicide layers on the upper surface of the mesa. A gate conductor is provided on one or more sidewalls of the mesa.11-25-2010
20100181615SEMICONDUCTOR DEVICE - There is provided a semiconductor device in which an upper main electrode region of a 3D pillar SGT includes a selective epitaxial growth semiconductor film, at least two adjacent 3D pillar SGTs are interconnected in parallel with each other by joining the selective epitaxial growth semiconductor films together, thereby the need for providing an interconnect layer for interconnecting 3D pillar SGTs in parallel with each other is eliminated.07-22-2010
20110169073TRANSISTOR DEVICE HAVING ASYMMETRIC EMBEDDED STRAIN ELEMENTS AND RELATED MANUFACTURING METHOD - Semiconductor transistor devices and related fabrication methods are provided. An exemplary transistor device includes a layer of semiconductor material having a channel region defined therein and a gate structure overlying the channel region. Recesses are formed in the layer of semiconductor material adjacent to the channel region, such that the recesses extend asymmetrically toward the channel region. The transistor device also includes stress-inducing semiconductor material formed in the recesses. The asymmetric profile of the stress-inducing semiconductor material enhances carrier mobility in a manner that does not exacerbate the short channel effect.07-14-2011
20100117143Vertical type semiconductor device - A vertical type semiconductor device including a first vertical semiconductor device on a semiconductor substrate, a second vertical semiconductor device on the first vertical semiconductor device, and an interconnection between the first and second vertical semiconductor devices.05-13-2010
20110079841SEMICONDUCTOR DEVICE - There is provided a semiconductor device which has a CMOS inverter circuit and which can accomplish high-integration by configuring an inverter circuit with a columnar structural body. A semiconductor device includes a columnar structural body which is arranged on a substrate and which comprises a p-type silicon, an n-type silicon, and an oxide arranged between the p-type silicon and the n-type silicon and running in the vertical direction to the substrate, n-type high-concentration silicon layers arranged on and below the p-type silicon, p-type high-concentration silicon layers arrange on and below the n-type silicon, an insulator which surrounds the p-type silicon, the n-type silicon, and the oxide, and which serves as a gate insulator, and a conductive body which surrounds the insulator and which serves as a gate electrode.04-07-2011
20110180867METAL TRANSISTOR DEVICE - The present invention is related to a depletion or enhancement mode metal transistor in which the channel regions of a transistor device comprises a thin film metal or metal composite layer formed over an insulating substrate.07-28-2011
20100025758METHOD OF MANUFACTURING HIGH-INTEGRATED SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURED USING THE SAME - A semiconductor device comprises a plurality of vertical transistors each comprising barrier metal layers corresponding to source/drain regions in which a conduction region is formed under a channel region having a pillar form, and a bit line comprising a metal layer to connect the plurality of vertical transistors.02-04-2010
20100025757Conductive structure and vertical-type pillar transistor - In a conductive structure, method of forming the conductive structure, a vertical-type pillar transistor and a method of manufacturing the vertical-type pillar transistor, the conductive structure includes a pillar provided on a substrate. A first conductive layer pattern is provided on a sidewall of the pillar, at least a portion of the first conductive layer pattern facing the sidewall of the pillar. A second conductive layer pattern is provided on a surface of the first conductive layer pattern, the second conductive layer pattern facing the sidewall of the pillar. A hard mask pattern covers upper surfaces of the first conductive layer pattern and the pillar. The conductive structure includes an electric conductor with a relatively low resistance. The conductive structure may be used as an electrode of a memory device.02-04-2010
20110012194Multi-die DC-DC Buck Power Converter with Efficient Packaging - A DC-DC buck converter in multi-die package is proposed having an output inductor, a low-side Schottky diode and a high-side vertical MOSFET controlled by a power regulating controller (PRC). The multi-die package includes a first die pad with the Schottky diode placed there on side by side with the vertical MOSFET. The PRC die is attached atop the first die pad via an insulating die bond. Alternatively, the first die pad is grounded. The vertical MOSFET is a top drain N-channel FET, the substrate of Schottky diode die is its anode. The Schottky diode and the vertical MOSFET are stacked atop the first die pad. The PRC is attached atop the first die pad via a conductive die bond. The Schottky diode die can be supplied in a flip-chip configuration with cathode being its substrate. Alternatively, the Schottky diode is supplied with anode being its substrate without the flip-chip configuration.01-20-2011
20100123186POWER SEMICONDUCTOR DEVICE - In a vertical power semiconductor device having the super junction structure both in a device section and a terminal section, an n-type impurity layer is formed on the outer peripheral surface in the super junction structure. This allows an electric field on the outer peripheral surface of the super junction structure region to be reduced. Accordingly, a reliable vertical power semiconductor device of a high withstand voltage can be provided.05-20-2010
20120146132MEMORY ARRAY WITH SURROUNDING GATE ACCESS TRANSISTORS AND CAPACITORS WITH GLOBAL AND STAGGERED LOCAL BIT LINES - A memory array with staggered local data/bit lines extending generally in a first direction formed in an upper surface of a substrate and memory cell access transistors extending generally upward and aligned generally atop a corresponding local data/bit line. Selected columns of the memory cell access transistors are sacrificed to define local data/bit access transistors which are interconnected with overlying low resistance global data/bit lines. The global data/bit lines provide selectable low resistance paths between memory cells and sense amplifiers. The sacrificed memory cell access transistors and staggered local data/bit lines provide increased footprints for sense amplifiers to facilitate increased circuit integration.06-14-2012
20120146131VERTICAL SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A vertical semiconductor device includes a first active pillar vertically protruded from a semiconductor substrate; a first vertical gate connected to at least one side of the first active pillar and formed along a direction that crosses a buried bit line; and a first body line connected to at least one side of the first active pillar which is not connected to the first vertical gate.06-14-2012
20120146130SEMICONDUCTOR COMPONENT WITH A SEMICONDUCTOR VIA - A method for producing a semiconductor component includes providing a semiconductor body with a first surface and a second surface opposite the first surface, forming an insulation trench which extends into the semiconductor body from the first surface and which in a horizontal plane of the semiconductor body has a geometry such that the insulation trench defines a via region of the semiconductor body, forming a first insulation layer on one or more sidewalls of the insulation trench, removing semiconductor material of the semiconductor body from the second surface to expose at least parts of the first insulation layer, to remove at least parts of the first insulation layer, or to leave at least partially a semiconductor layer with a thickness of less than 1 μm between the first insulation layer and the second surface, and forming first and second contact electrodes on the via region.06-14-2012
20110068387Semiconductor device including vertical transistor and horizontal transistor and method of manufacturing the same - A semiconductor device includes a semiconductor substrate, a vertical transistor, a horizontal transistor, a lead, wire-bonding pads, and penetrating electrodes. The semiconductor substrate has first and second surfaces and includes a first surface portion adjacent to the first surface. The vertical transistor includes first and second electrodes on the first surface and a third electrode on the second surface. The horizontal transistor includes first, second, and third electrodes on the first surface. The vertical transistor and the horizontal transistor further include PN junction parts in the first surface portion. The lead is disposed to the first surface and is electrically coupled with the first electrode of the vertical transistor. The wire-bonding pads are disposed on the second surface. The second electrode of the vertical transistor and the first to third electrodes of the horizontal transistor are electrically coupled with the wire-boding pads through the penetrating electrodes.03-24-2011
20110316073SOI CMOS DEVICE HAVING VERTICAL GATE STRUCTURE - The present invention discloses an SOI CMOS device having a vertical gate structure, comprising: an SOI substrate, and an NMOS region and a PMOS region grown on the SOI substrate, wherein the NMOS region and the PMOS region share one vertical gate region, said vertical gate region lying in the same plane as the NMOS region and the PMOS region and between the NMOS region and the PMOS region; a gate oxide layer is arranged between the vertical gate region and the NMOS region for isolation; and a gate oxide layer is arranged between the vertical gate region and the PMOS region for isolation. The present invention occupies small area, contains less pattern layers, requires a simple process, has an open body region that can completely avoid the floating effect of the traditional SOI CMOS device, and is convenient to parasitic resistance and capacitance tests.12-29-2011
20110316072SEMICONDUCTOR MEMORY DEVICES INCLUDING ASYMMETRIC WORD LINE PADS - Semiconductor memory devices may include a semiconductor substrate, a first stack disposed on the semiconductor substrate and a second stack disposed on the first stack. The first stack may include a plurality of first word lines with a plurality of first line pads stacked in a stair form, and the second stack may include a plurality of second word lines with a plurality of second line pads stacked in a stair form. The second stack may be shifted on the first stack such that sides of the plurality of first word line pads are exposed.12-29-2011
20090140328Bridged Gate FinFet - In a fin-type field effect transistor (FinFET) structure, a gate strap is positioned on the top of a gate conductor and runs along the gate conductor. The top of the gate strap is positioned a greater height above the top surface of the substrate than the top of the fin cap. The gate strap is conformal and, therefore, the top of the portion of the gate strap that crosses the fin cap has a greater height above the top surface of the substrate than top portions of other regions of the gate strap. Further, the material of the gate strap can have a different work function than a material of the gate conductor.06-04-2009
20120001256SEMICONDUCTOR DEVICE - A semiconductor device includes: a first insulator pillar surrounding an active region; a second insulator pillar with a second side surface opposed in a y direction to a first side surface of the first insulator pillar on the active region side; an insulating film covering top surfaces of first and second insulator pillars; a second gate electrode electrically connected to the first gate electrode, covering at least the first and second side surfaces; and a gate contact plug in a contact hole and electrically connected to a top surface of the second gate electrode, the insulating film and the second gate electrode being exposed in a bottom of the contact hole. A distance between first and second side surfaces01-05-2012
20120001255SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - The present invention relates to a semiconductor device and a method of manufacture thereof, particularly, to a semiconductor device including a vertical type gate and a method of forming the same. According to the present invention, a semiconductor device includes a vertical pillar which is protruded from a semiconductor substrate, has a vertical channel, and has a first width; an insulating layer which has a second width smaller than the first width, provided in both sides of the vertical pillar which is adjacent in a first direction; and a nitride film provided in a side wall of the insulating layer.01-05-2012
20110156134METHOD OF FABRICATING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE FABRICATED THEREBY - The present invention is for weakening an electric field between a gate and a drain and preventing an electronic short between them. An embodiment of the present invention provides a method for manufacturing a semiconductor device, comprising forming a highly doped region in a semiconductor substrate through a first ion implantation process, forming a lightly doped region over the highly doped region through a second ion implantation process, forming a vertical transistor including the lightly doped region and a channel region having a pillar shape over the lightly doped region.06-30-2011
20120056261BI-DIRECTIONAL, REVERSE BLOCKING BATTERY SWITCH - Embodiments of the present invention relate to an improved package for a bi-directional and reverse blocking battery switch. According to one embodiment, two switches are oriented side-by-side, rather than end-to-end, in a die package. This configuration reduces the total switch resistance for a given die area, often reducing the resistance enough to avoid the use of backmetal in order to meet resistance specifications. Elimination of backmetal reduces the overall cost of the die package and removes the potential failure modes associated with the manufacture of backmetal. Embodiments of the present invention may also allow for more pin connections and an increased pin pitch. This results in redundant connections for higher current connections, thereby reducing electrical and thermal resistance and minimizing the costs of manufacture or implementation of the die package.03-08-2012
20120012923SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - The present invention relates to a semiconductor device and a method for forming the same. The semiconductor device includes: a vertical pillar protruded from a semiconductor substrate; a first junction region provided at an upper part of the vertical pillar; a second junction region provided in a lower part of the vertical pillar to be separated apart from the first junction region; and a gate oxidation layer in which a thickness thereof in a surface of the vertical pillar in which the first junction region is provided being thicker than that in a surface of the vertical pillar in which the first junction region is not provided. The present invention forms a gate oxidation layer using the oxidation rate difference without a mask process to minimize GIDL that leads to improvement in the characteristic of a semiconductor device.01-19-2012
20120012922SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method of manufacturing the same are provided. Upon forming source or drain at a lower part of the pillar pattern, a silicon oxide layer (barrier layer) is formed inside the pillar pattern to prevent the pillar pattern from being electrically floated. Furthermore, impurities are diffused to a vertical direction (longitudinal direction) of the pillar pattern to overlay junction between the semiconductor substrate and source or drain formed at a lower part of the pillar pattern that leads to improvement of a current characteristic.01-19-2012
20110049617SEMICONDUCTOR DEVICE - A semiconductor device is provided. The semiconductor device includes a substrate and a plurality of material layers. The substrate includes a concave portion having a bottom surface and a side surface, and a protruded portion extended from the side surface. The plurality of material layers have flat portions on the bottom surface and side portions extended over the side surface from the flat portions, and spaced from each other. Here, at least one of the sidewall portions of the material layers has a thickness greater than a thickness of the flat portions of the material layers.03-03-2011
20110049616SEMICONDUCTOR STRUCTURE FOR A POWER DEVICE AND CORRESPONDING MANUFACTURING PROCESS - An embodiment of a semiconductor structure for a power device integrated on a semiconductor substrate, of a first type of conductivity, and comprising:—an epitaxial layer, of said first type of conductivity, made on said semiconductor substrate, and having a plurality of column structures, of a second type of conductivity, to define a charge balancing region;—an active surface layer made on said epitaxial layer for housing a plurality of active regions; said epitaxial layer comprising a semiconductor separating layer arranged between the charge balancing region and the active surface layer, said semiconductor separating layer decoupling said column structures from said active regions.03-03-2011
20110049615POWER SEMICONDUCTOR DEVICE - According to one embodiment, a power semiconductor device includes a second semiconductor layer of a first conductivity type and a third semiconductor layer of a second conductivity type periodically disposed repeatedly along a surface of the first semiconductor layer on a first semiconductor layer of the first conductivity type. A first main electrode is provided to electrically connect to the first semiconductor layer. A fourth semiconductor layer of the second conductivity type is provided to connect to the third semiconductor layer. Fifth semiconductor layers of the first conductivity type are selectively provided in the fourth semiconductor layer surface. A second main electrode is provided on a surface of the fourth and fifth semiconductor layers. A control electrode is provided on a surface of the fourth, fifth, and second semiconductor layers via a gate insulating film. First insulating films are provided by filling a trench made in the second semiconductor layer.03-03-2011
20120061747SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a drift region of a first conductivity type, a base region of a second conductivity type, a source region of the first conductivity type, a gate electrode in a trench shape, a contact region of the second conductivity type, a drain electrode, and a source electrode. The drift region is selectively provided in a drain layer of the first conductivity type from a surface of the drain layer to an inside of the drain layer. The base region is selectively provided in the drift region from a surface of the drift region to an inside of the drift region. The source region is selectively provided in the base region from a surface of the base region to an inside of the base region. The gate electrode penetrates from a part of the source region through the base region adjacent to the part of the source region to reach a part of the drift region in a direction substantially parallel to a major surface of the drain layer. The contact region is selectively provided on the surface of the drift region. The contact region contains an impurity having a concentration higher than an impurity concentration of the base region. The drain electrode is connected to the drain layer. The source electrode is connected to the source region and the contact region. The contact region extends from a side of the drain layer toward the drift region and does not contact the drain layer.03-15-2012
20120119288SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Disclosed herein is a semiconductor device, including: a first semiconductor region of a first conductivity type; a second semiconductor region having pairs of first pillar regions of the first conductivity type, and second pillar regions of a second conductivity type alternately provided; a third semiconductor region of the second conductivity type; a fourth semiconductor region of the first conductivity type; and control electrodes each provided within a trench through an insulating film, a sidewall of the trench being formed so as to contact each of the third semiconductor region and the fourth semiconductor region.05-17-2012
20120153379SEMICONDUCTOR DEVICES WITH VERTICAL CHANNEL TRANSISTORS - Semiconductor devices with vertical channel transistors, the devices including semiconductor patterns disposed on a substrate, first gate patterns disposed between the semiconductor patterns on the substrate, a second gate pattern spaced apart from the first gate patterns by the semiconductor patterns, and conductive lines crossing the first gate patterns. The second gate pattern includes a first portion extending parallel to the first gate patterns and a second portion extending parallel to the conductive lines.06-21-2012
20120153378SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A semiconductor device and a method for forming the same are disclosed. The semiconductor device prevents separation between the channel region and the semiconductor substrate to prevent the floating body effect and to guarantee a sufficient overlap between a gate and a junction region. The semiconductor device includes a vertical pillar including a vertical channel, a diffusion control layer contained in the vertical pillar, and a junction region formed close to the diffusion control layer in the vertical pillar.06-21-2012
20100096691SEMICONDUCTOR DEVICE HAVING VERTICALLY ALIGNED PILLAR STRUCTURES THAT HAVE FLAT SIDE SURFACES AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device having vertically aligned transistors made from pillar structures that have flat side surfaces is presented. The semiconductor device includes a semiconductor substrate, spacers, and gates. The semiconductor substrate has lo pillar structures that have flat side surfaces. The spacers are on sidewalls only on the upper portions of the pillar structures. The gates surround lower portions of the pillar structures.04-22-2010
20090134456Semiconductor devices and method of manufacturing them - The present invention aims to suppress the diffusion of p-type impurities (typically magnesium), included in a semiconductor region of a III-V compound semiconductor, into an adjoining different semiconductor region. A semiconductor device 05-28-2009
20110089483METHOD OF FORMING A POWER SEMICONDUCTOR DEVICE AND POWER SEMICONDUCTOR DEVICE - A method of forming a power semiconductor device comprises forming a first semiconductor layer of a first conductivity type extending across the power semiconductor device; forming an epitaxial layer of the first conductivity type over the first semiconductor layer, the epitaxial layer having a doping concentration that increases from a first surface of the epitaxial layer towards the first semiconductor layer; forming a body region of a second conductivity type in the epitaxial layer extending from the first surface of the epitaxial layer into the epitaxial layer, wherein a junction between the body region and the epitaxial layer is at or substantially adjacent to a region of the epitaxial layer having a maximum doping concentration; and forming a gate region such that the gate region is adjacent at least a portion of the body region. In operation of the semiconductor device, the portion of the body region adjacent the gate region functions as a channel region of the semiconductor device.04-21-2011
20110089482METHOD AND APPARATUS FOR CONTROLLING A CIRCUIT WITH A HIGH VOLTAGE SENSE DEVICE - A control circuit with a high voltage sense device. In one embodiment, a circuit includes a first transistor disposed in a first substrate having first, second and third terminals. A first terminal of the first transistor is coupled to an external voltage. A voltage provided at a third terminal of the first transistor is substantially proportional to a voltage between the first and second terminals of the first transistor when the voltage between the first and second terminals of the first transistor is less than a pinch-off voltage of the first transistor. The voltage provided at the third terminal of the first transistor is substantially constant and less than the voltage between the first and second terminals of the first transistor when the voltage between the first and second terminals of the first transistor is greater than the pinch-off voltage of the first transistor. The circuit also includes a control circuit disposed in the first substrate and coupled to the third terminal of the first transistor. The circuit further includes a second transistor disposed in a second substrate. A first terminal of the second transistor coupled to the external voltage.04-21-2011
20120119286SEMICONDUCTOR DEVICES HAVING VERTICAL CHANNEL TRANSISTORS AND METHODS FOR FABRICATING THE SAME - A semiconductor device has a plurality of vertical channels extending upright on a substrate, a plurality of bit lines extending among the vertical channels, a plurality of word lines which include a plurality of gates disposed adjacent first sides of the vertical channels, respectively, and a plurality of conductive elements disposed adjacent second sides of the vertical channels opposite the first sides. The conductive elements can provide a path to the substrate for charge carriers which have accumulated in the associated vertical channel to thereby mitigate a so-called floating effect.05-17-2012
201201192873D SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING SAME - A three dimensional (3D) semiconductor device includes; a vertical channel extending from a lower end proximate a substrate to an upper end and connecting a plurality of memory cells, and a cell array comprising the plurality of cells, wherein the cell array is arranged in a gate stack of layers having a stair-stepped structure disposed on the substrate. The gate stack includes a lower layer including a lower select line coupled to a lower non-memory transistor proximate the lower end, upper layers including conductive lines respectively coupled to an upper non-memory transistor proximate the upper end and connected as a single conductive piece to form an upper select line, and intermediate layers respectively including a word line and coupled to a cell transistor, wherein the intermediate layers are disposed between the lower select line and the upper select line.05-17-2012
20120119285SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method for manufacturing the same are disclosed, which can form a gate electrode material only in a recess of a buried gate cell structure, improve a Gate Induced Drain Leakage (GIDL) of a gate electrode material and a junction (i.e., drain region), prevent the gate electrode material from overlapping with the junction (i.e., drain region), and adjust the depth of junction, thereby improving channel resistance. The method for manufacturing a semiconductor device includes forming a device isolation region defining an active region over a semiconductor substrate, burying a gate electrode material in the semiconductor substrate, forming a gate electrode pattern by etching the gate electrode material, wherein the gate electrode pattern is formed at sidewalls of the active region including a source region, and forming a capping layer in the exposed active region.05-17-2012
20120126314VERTICAL DMOS-FIELD EFFECT TRANSISTOR - A vertical diffused metal oxide semiconductor (DMOS) field-effect transistors (FET) comprises a substrate of a first conductivity type forming a drain region; an epitaxial layer of the first conductivity type on said substrate; first and second base regions of the second conductivity type within said epitaxial layer, spaced apart by a predefined distance; first and second source regions of a first conductivity type arranged in said first and second base regions, respectively, wherein said first and second base region is operable to form first and second lateral channels between said source region and said epitaxial layer; a gate structure insulated from said epitaxial layer by an insulation layer and arranged above the region between the first and second base regions and wherein the gate structure comprises first and second gate regions, each gate region only covering the first and second channel, respectively within said first and second base region.05-24-2012
20120126310METHOD FOR FORMING CHANNEL MATERIAL - The present invention provides a method for forming a channel material, comprising: forming a substrate; forming an MOS device with a dummy gate stack on the substrate; removing the dummy gate stack; forming a channel trench at the channel located under the dummy gate stack; filling the channel trench with the channel material; and forming a gate stack. According to the embodiments of the present invention, the channel material is formed by a replacement gate process after the high temperature process, such as a high temperature annealing, thereby any negative influence on the formed channel material due to the high temperature process may be effectively avoided.05-24-2012
20120126311POWER TRANSISTOR WITH METAL SOURCE AND METHOD OF MANUFACTURE - A metal source power transistor device and method of manufacture is provided, wherein the metal source power transistor having a source which is comprised of metal and which forms a Schottky barrier with the body region and channel region of the transistor. The metal source power transistor is unconditionally immune from parasitic bipolar action and, therefore, the effects of snap-back and latch-up, without the need for a body contact. The ability to allow the body to float in the metal source power transistor reduces the process complexity and allows for more compact device layout.05-24-2012
20120126315SEMICONDUCTOR APPARATUS - A semiconductor apparatus that has a first parallel pn-layer formed between an active region and an n05-24-2012
20120126313ULTRA THIN DIE TO IMPROVE SERIES RESISTANCE OF A FET - A method for producing a power field effect transistor (FET) device having a low series resistance between the drain and source when switched on has the steps of: forming a vertical power FET in a semiconductor die; and back-grinding the semiconductor die to a thickness of less than or equal to about 100 μm (4 mils) or less.05-24-2012
20120126312VERTICAL DMOS-FIELD EFFECT TRANSISTOR - A vertical diffused metal oxide semiconductor (DMOS) field-effect transistors (FET), has a cell structure with a substrate; an epitaxial layer or well of the first conductivity type on the substrate; first and second base regions of the second conductivity type arranged within the epitaxial layer or well and spaced apart by a predefined distance; first and second source regions of a first conductivity type arranged within the first and second base region, respectively; a gate structure insulated from the epitaxial layer or well by an insulation layer and arranged above the region between the first and second base regions and covering at least partly the first and second base region, wherein the gate structure comprises first and second gates being spaced apart wherein each gate covers a respective portion of the base region.05-24-2012
20100207199SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREFOR - The method includes the steps of: forming a planar semiconductor layer on an oxide film formed on a substrate and then forming a pillar-shaped first-conductive-type semiconductor layer on the planar semiconductor layer; forming a second-conductive-type semiconductor layer in a portion of the planar semiconductor layer underneath the pillar-shaped first-conductive-type semiconductor layer; forming a gate dielectric film and a gate electrode made of a metal, around the pillar-shaped first-conductive-type semiconductor layer; forming a sidewall-shaped dielectric film on an upper region of a sidewall of the pillar-shaped first-conductive-type semiconductor layer and in contact with a top of the gate electrode; forming a sidewall-shaped dielectric film on a sidewall of the gate electrode; forming a second-conductive-type semiconductor layer in an upper portion of the pillar-shaped first-conductive-type semiconductor layer.08-19-2010
20100207200SEMICONDUCTOR DEVICE - It is intended to solve a problem of increase in power consumption and reduction in operating speed due to an increase in parasitic capacitance of a surrounding gate transistor (SGT) as a three-dimensional semiconductor device, to provide an SGT achieving an increase in speed and power consumption reduction in a semiconductor circuit. The semiconductor device comprises a second-conductive type impurity region (08-19-2010
20120211824 VERTICAL TRANSISTOR HAVING A GATE STRUCTURE FORMED ON A BURIED DRAIN REGION AND A SOURCE REGION OVERLYING THE UPPER MOST LAYER OF THE GATE STRUCTURE - Raised structures comprising overlying silicon layers formed by controlled selective epitaxial growth, and methods for forming such raised-structure on a semiconductor substrate are provided. The structures are formed by selectively growing an initial epitaxial layer of mono crystalline silicon on the surface of a semi conductive substrate, and forming a thin film of insulative material over the epitaxial layer. A second epitaxial layer is selectively, grown on the exposed surface of the initial epitaxially grown crystal layer, and a thin insulative film is deposited over the second epitaxial layer. Additional epitaxial layers are added as desired to provide a vertical structure of a desired height comprising multiple layers of single silicon crystals, each epitaxial layer have insulated sidewalls, with the uppermost epitaxial layer also with an insulated top surface.08-23-2012
20120132987Reducing Device Performance Drift Caused by Large Spacings Between Active Regions - A method of forming an integrated circuit structure includes providing a semiconductor substrate; and forming a first and a second MOS device. The first MOS device includes a first active region in the semiconductor substrate; and a first gate over the first active region. The second MOS device includes a second active region in the semiconductor substrate; and a second gate over the second active region. The method further include forming a dielectric region between the first and the second active regions, wherein the dielectric region has an inherent stress; and implanting the dielectric region to form a stress-released region in the dielectric region, wherein source and drain regions of the first and the second MOS devices are not implanted during the step of implanting.05-31-2012
20120132986SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - A semiconductor device includes a substrate having a plurality of horizontal channel transistors formed thereon, an insulation layer structure on the substrate and covering the horizontal transistors, and a plurality of vertical channel transistors on the insulation layer structure.05-31-2012
20120168855NANOWIRE TRANSISTOR WITH SURROUNDING GATE - One aspect of the present subject matter relates to a method for forming a transistor. According to an embodiment of the method, a pillar of amorphous semiconductor material is formed on a crystalline substrate, and a solid phase epitaxy process is performed to crystallize the amorphous semiconductor material using the crystalline substrate to seed the crystalline growth. The pillar has a sublithographic thickness. A transistor body is formed in the crystallized semiconductor pillar between a first source/drain region and a second source/drain region. A surrounding gate insulator is formed around the semiconductor pillar, and a surrounding gate is formed around and separated from the semiconductor pillar by the surrounding gate insulator. Other aspects are provided herein.07-05-2012
20120168854SEMICONDUCTOR DEVICE AND METOD FOR FORMING THE SAME - A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes a first junction region formed at the bottom of a vertical pillar, a bit line formed below the first junction region, and an insulation film formed below the bit line. As a result, the 4F2-sized semiconductor device is provided and the bit line is configured in the form of a laminated structure of a conductive layer and a polysilicon layer, so that bit line resistance is reduced. In addition, the semiconductor device reduces ohmic contact resistance by forming silicide between the conductive layer and the polysilicon layer, and includes an insulation film at a position between the semiconductor substrate and the bit line, resulting in reduction of bit line capacitance. Therefore, the sensing margin of the semiconductor device is increased and the data retention time is also increased.07-05-2012
20100244124SEMICONDUCTOR DEVICES HAVING A VERTICAL CHANNEL TRANSISTOR - Embodiments according to the inventive concept can provide semiconductor devices including a substrate and a plurality of active pillars arranged in a matrix on the substrate. Each of the pillars includes a channel part that includes a channel dopant region disposed in a surface of the channel part. A gate electrode surrounds an outer surface of the channel part. The plurality of active pillars may be arranged in rows in a first direction and columns in a second direction crossing the first direction.09-30-2010
20120223382NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a non-volatile memory device includes forming a channel link layer and an isolation layer surrounding the channel link layer over a substrate, forming a stack structure having interlayer dielectric layers that are alternately stacked with gate electrode layers over the channel link layer and the isolation layer, and forming a pair of channels connected to the channel link layer through the stack structure, and a memory layer interposed between the channel and the stack structure.09-06-2012
20100193861Three-Dimensional Memory Device - A three-dimensional semiconductor device includes a semiconductor substrate, vertical channel structures arranged on the semiconductor substrate in a matrix, a P-type semiconductor layer disposed at the semiconductor substrate to be in direct with the vertical channel structures, and a common source line disposed at the semiconductor substrate between the vertical channel structures. The common source line may be in contact with the P-type semiconductor layer.08-05-2010
20120256252COMPATIBLE VERTICAL DOUBLE DIFFUSED METAL OXIDE SEMICONDUCTOR TRANSISTOR AND LATERAL DOUBLE DIFFUSED METAL OXIDE SEMICONDUCTOR TRANSISTOR AND MANUFACTURE METHOD THEREOF - A method for manufacturing compatible vertical double diffused metal oxide semiconductor (VDMOS) transistor and lateral double diffused metal oxide semiconductor (LDMOS) transistor includes: providing a substrate having an LDMOS transistor region and a VDMOS transistor region; forming an N-buried region in the substrate; forming an epitaxial layer on the N-buried layer region; forming isolation regions in the LDMOS transistor region and the VDMOS transistor region; forming a drift region in the LDMOS transistor region; forming gates in the LDMOS transistor region and the VDMOS transistor region; forming PBODY regions in the LDMOS transistor region and the VDMOS transistor region; forming an N-type GRADE region in the LDMOS transistor region; forming an NSINK region in the VDMOS transistor region, where the NSINK region is in contact with the N-buried layer region; forming sources and drains in the LDMOS transistor region and the VDMOS transistor region; and forming a P+ region in the LDMOS transistor region, where the P+ region is in contact with the source.10-11-2012
20120228698VERTICAL COMPLEMENTARY FET - A vertical complementary field effect transistor (FET) relates to the production technology of semiconductor chips and more particularly to the production technology of power integration circuit. A part of the substrate bottom of the invention extends into the middle layer and form the plug between the two MOS units. There is an output terminal under the substrate layer. When on-state voltage is applied on the gate electrode of the two MOS units, two conduction paths are formed from MOS unit-plug-substrate to the output terminal. This technology can integrate more than two MOS devices. Therefore, the die size is reduced.09-13-2012
20110121383MEMORY ARRAY WITH SURROUNDING GATE ACCESS TRANSISTORS AND CAPACITORS WITH GLOBAL AND STAGGERED LOCAL BIT LINES - A memory array with staggered local data/bit lines extending generally in a first direction formed in an upper surface of a substrate and memory cell access transistors extending generally upward and aligned generally atop a corresponding local data/bit line. Selected columns of the memory cell access transistors are sacrificed to define local data/bit access transistors which are interconnected with overlying low resistance global data/bit lines. The global data/bit lines provide selectable low resistance paths between memory cells and sense amplifiers. The sacrificed memory cell access transistors and staggered local data/bit lines provide increased footprints for sense amplifiers to facilitate increased circuit integration.05-26-2011
20120319190SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - Semiconductor devices and methods for manufacturing the same are disclosed. In one embodiment, the semiconductor device comprises a semiconductor substrate; an insulating layer located on the semiconductor substrate; a semiconductor body located on the insulating layer; a cavity formed in the semiconductor body and into the insulating layer; source/drain regions abutting opposite first side faces of the semiconductor body; gates located on opposite second side faces of the semiconductor body; a channel layer interposed between the respective second side faces and the cavity; and a super-steep-retrograded-well and a halo super-steep-retrograded-well formed in the channel layer. The super-steep-retrograded-well and the halo super-steep-retrograded-well have opposite dopant polarities.12-20-2012
20120319192Gate Structures - An apparatus includes a first device. The first device includes a first projection and a first gate structure, the first projection extending upwardly from a substrate and having a first channel region therein, and the first gate structure engaging the first projection adjacent the first channel region. The first structure includes an opening over the first channel region, and a conformal, pure metal with a low resistivity disposed in the opening. The apparatus also includes a second device that includes a second projection and a second gate structure, the second projection extending upwardly from the substrate and having a second channel region therein, and the second gate structure engaging the second projection adjacent the second channel region. The second structure includes a silicide disposed over the second channel region, wherein the silicide includes a metal that is the same metal disposed in the opening.12-20-2012
20120261745SEMICONDUCTOR SWITCHING DEVICE EMPLOYING A QUANTUM DOT STRUCTURE - A semiconductor device includes a semiconductor island having at least one electrical dopant atom and encapsulated by dielectric materials including at least one dielectric material layer. At least two portions of the at least one dielectric material layer have a thickness less than 2 nm to enable quantum tunneling effects. A source-side conductive material portion and a drain-side conductive material portion abuts the two portions of the at least one dielectric material layer. A gate conductor is located on the at least one dielectric material layer between the source-side conductive material portion and the drain-side conductive material portion. The potential of the semiconductor island responds to the voltage at the gate conductor to enable or disable tunneling current through the two portions of the at least one dielectric material layer. Design structures for the semiconductor device are also provided.10-18-2012
20120261744MICROELECTRONIC DEVICE STRUCTURE AND MANUFACTURING METHOD THEREOF - The present invention refers to a semiconductor device especially a tunneling filed effect transistor (TFET) using narrow bandgap material as the source electrode material. A Semiconductor device which is a tunneling field effect transistor type semiconductor device, in which the source material is characterized as narrow band-gap material; meanwhile, there is a u-groove channel. The narrow band-gap material results in a raise of driving current and the u-groove channel reduced drain leakage current. The TFET disclosed in to present invention has the advantages of low leakage current, high drive current, and high integration density. The static power consumption is also reduced by using the present invention. The integration density is improved as well.10-18-2012
20120299088Memory Arrays, Semiconductor Constructions, and Methods of Forming Semiconductor Constructions - Some embodiments include memory arrays. The memory arrays may have digit lines under vertically-oriented transistors, with the digit lines interconnecting transistors along columns of the array. Each individual transistor may be directly over only a single digit line, with the single digit line being entirely composed of one or more metal-containing materials. The digit lines can be over a deck, and electrically insulative regions can be directly between the digit lines and the deck. Some embodiments include methods of forming memory arrays. A plurality of linear segments of silicon-containing material may be formed to extend upwardly from a base of the silicon-containing material. The base may be etched to form silicon-containing footings under the linear segments, and the footings may be converted into metal silicide. The linear segments may be patterned into a plurality of vertically-oriented transistor pedestals that extend upwardly from the metal silicide footings.11-29-2012
20120267706Semiconductor device and manufacturing method thereof - The invention discloses a novel MOSFET device and its implementation method, the device comprising: a substrate; a gate stack structure, on either side of which is eliminated a conventional isolation spacer; source/drain regions located in the substrate on opposite sides of the gate stack structure; epitaxially grown metal silicide located on the source/drain regions; characterized in that, the epitaxially grown metal silicide is in direct contact with a channel region controlled by the gate stack structure, thereby eliminating the high resistance region below the conventional isolation spacer. At the same time, the epitaxially grown metal silicide can withstand a second high-temperature annealing used for improving the performance of a high-k gate dielectric material, which further improves the performance of the device. The MOSFET according to the invention reduces the parasitic resistance and capacitance greatly and thereby decreases the RC delay, thus improving the switching performance of the MOSFET device significantly.10-25-2012
20120267707SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - Disclosed herein is a semiconductor device including: a first conductivity type semiconductor base body; a first conductivity type pillar region; second conductivity type pillar regions; element and termination regions provided in the first and second conductivity type pillar regions, transistors being formed in the element region, and no transistors being formed in the termination region; body regions; a gate insulating film; gate electrodes; source regions; and body potential extraction regions, wherein voids are formed in the second conductivity type pillar regions of the termination region.10-25-2012
20120319191PROCESS FOR MANUFACTURING A SEMICONDUCTOR POWER DEVICE COMPRISING CHARGE-BALANCE COLUMN STRUCTURES AND RESPECTIVE DEVICE - Process for manufacturing a semiconductor power device, wherein a trench is formed in a semiconductor body having a first conductivity type; the trench is annealed for shaping purpose; and the trench is filled with semiconductor material via epitaxial growth so as to obtain a first column having a second conductivity type. The epitaxial growth is performed by supplying a gas containing silicon and a gas containing dopant ions of the second conductivity type in presence of a halogenide gas and occurs with uniform distribution of the dopant ions. The flow of the gas containing dopant ions is varied according to a linear ramp during the epitaxial growth; in particular, in the case of selective growth of the semiconductor material in the presence of a hard mask, the flow decreases; in the case of non-selective growth, in the absence of hard mask, the flow increases.12-20-2012
20110227147SUPER JUNCTION DEVICE WITH DEEP TRENCH AND IMPLANT - RESURF effect devices with both relatively deep trenches and relatively deep implants are described herein. Also, methods of fabricating such devices are described herein. A RESURF effect device may include alternating regions of first and second conductivity types where each of the second regions includes an implant region formed into a trench region of the second region.09-22-2011
20120080746SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - Disclosed herein is a fabrication method of a semiconductor device to order to increase an operation liability of the semiconductor device. A method for fabricating a semiconductor device comprises forming a recess in a semiconductor substrate, forming a word line in a lower part of the recess, oxidizing a top portion of the word line, and depositing an insulating material in a remained part of the recess.04-05-2012
20120080745VERTICAL TRANSISTOR AND METHOD FOR FORMING THE SAME - A vertical transistor includes a semiconductor substrate provided with a pillar type active pattern over the surface thereof. A first tensile layer is formed over the semiconductor substrate and around the lower end portion of the pillar type active pattern, and a second tensile layer is formed over the upper end portion of the pillar type active pattern so that a tensile stress is applied in a vertical direction to the pillar type active pattern. A first junction region is formed within the surface of the semiconductor substrate below the first tensile layer and the pillar type active pattern. A gate is formed so as to surround at least a portion of the pillar type active pattern. A second junction region is formed within the upper end portion of the pillar type active pattern.04-05-2012
20120080744SEMICONDUCTOR DEVICE - A semiconductor device has a semiconductor substrate having an upper main surface and a lower main surface. The semiconductor substrate includes a drain layer, a main base region, an underpad base region and a source region. The semiconductor device includes a first main electrode connected to the main base regions and the source region and not connected to the underpad base region, a gate electrode opposed to a channel region in the main base region interposed between the drain layer and the source region with a gate insulating film provided therebetween, a conductive gate pad opposed to an exposed surface of the underpad base region in the upper main surface with an insulating layer interposed therebetween and the conductive gate pad is connected to the gate electrode, and a second main electrode connected to the lower main surface.04-05-2012
20120080743SEMICONDUCTOR DEVICE WITH INCREASED CHANNEL LENGTH AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a trench formed in a predetermined portion of a substrate and a first recess region beneath the trench. A field oxide layer is buried into both the trench and the first recess region. An active region is defined by the field oxide layer, having first active region and a second active region. The latter has a second recess region formed in lower portion of the active region than the former. A step gate pattern is formed on border region between the first active region and the second active region. The gate pattern has step structure whose one side extends to a surface of the first active region and the other side extends to a surface of the second active region. Other embodiments are also described.04-05-2012
20100230745POWER SEMICONDUCTOR DEVICE - A power semiconductor device according to an embodiment of the present invention includes a first semiconductor layer of a first or second conductivity type, a second semiconductor layer of the first conductivity type formed on the first semiconductor layer, a third semiconductor layer of the second conductivity type selectively formed on a surface of the second semiconductor layer, at least one trench formed in a periphery of the third semiconductor layer on the surface of the second semiconductor layer, a depth of a bottom surface of the at least one trench being deeper than a bottom surface of the third semiconductor layer, and shallower than a top surface of the first semiconductor layer, and some or all of the at least one trench being in contact with a side surface of the third semiconductor layer, at least one insulator buried in the at least one trench, a first main electrode electrically connected to the first semiconductor layer, and a second main electrode electrically connected to the third semiconductor layer.09-16-2010
20120280309MOS TRANSISTOR SUPPRESSING SHORT CHANNEL EFFECT AND METHOD OF FABRICATING THE SAME - A MOS transistor suppressing a short channel effect includes a substrate, a first diffusion region and a second diffusion region separated from each other by a channel region in an upper portion of the substrate, a gate insulating layer including a first gate insulating layer disposed on a surface of the substrate in the channel region and a second gate insulating layer having a specified depth from the surface of the substrate to be disposed between the first diffusion region and the channel region, and a gate electrode disposed on the first gate insulating layer.11-08-2012
20120326226SUPERJUNCTION DEVICE AND METHOD FOR MANUFACTURING THE SAME - A superjunction device is disclosed, wherein P-type regions in an active region are not in contact with the N+ substrate, and the distance between the surface of the N+ substrate and the bottom of the P-type regions in the active region is greater than the thickness of a transition region in the N-type epitaxial layer. Methods for manufacturing the superjunction device are also disclosed. The present invention is capable of improving the uniformity of reverse breakdown voltage and overshoot current handling capability in a superjunction device.12-27-2012
20090302374Differential Nitride Pullback to Create Differential NFET to PFET Divots for Improved Performance Versus Leakage - Disclosed are embodiments of an integrated circuit structure with field effect transistors having differing divot features at the isolation region-semiconductor body interfaces so as to provide optimal performance versus stability (i.e., optimal drive current versus leakage current) for logic circuits, analog devices and/or memory devices. Also disclosed are embodiments of a method of forming the integrated circuit structure embodiments. These method embodiments incorporate the use of a cap layer pullback technique on select semiconductor bodies and subsequent wet etch process so as to avoid (or at least minimize) divot formation adjacent to some but not all semiconductor bodies.12-10-2009
20120139035SEMICONDUCTOR DEVICE - A semiconductor memory device includes a static memory cell having six MOS transistors arranged on a substrate. The six MOS transistors include first and second NMOS access transistors, third and fourth NMOS driver transistors, and first and second PMOS load transistors. Each of the first and second NMOS access transistors has a first diffusion layer, a pillar-shaped semiconductor layer, and a second diffusion layer arranged vertically on the substrate in a hierarchical manner. Each of the third and fourth NMOS driver transistors has a third diffusion layer, a pillar-shaped semiconductor layer, and a fourth diffusion layer arranged vertically on the substrate in a hierarchical manner. The lengths between the upper ends of the third diffusion layers and the lower ends of the fourth diffusion layers are shorter than the lengths between the upper ends of the first diffusion layer and the lower ends of the second diffusion layers.06-07-2012
20130009236THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES USING DIRECT STRAPPING LINE CONNECTIONS - Memory devices include a plurality of elongate gate stacks extending in parallel on a substrate and at least one insulation region disposed in a trench between adjacent ones of the gate stacks. The at least one insulation region has linear first portions having a first width and widened second portions having a second width greater than the first width. A common source region is disposed in the substrate underlying the at least one insulation region. The devices further include respective conductive plugs passing through respective ones of the widened second portions of the at least one insulation region and electrically connected to the common source region and at least one strapping line disposed on the conductive plugs between the adjacent ones of the gate stacks and in direct contact with the conductive plugs.01-10-2013
20130009235NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A non-volatile memory device includes first and second vertical channel layers generally protruding upwardly from a semiconductor substrate substantially in parallel; a first gate group configured to include a plurality of memory cell gates which are stacked substantially along the first vertical channel layer and are isolated from each other with an interlayer insulating layer interposed substantially between the memory cell gates; a second gate group configured to include a plurality of memory cell gates which are stacked substantially along the second vertical channel layer and are isolated from each other with the interlayer insulating layer interposed substantially between the memory cell gates; a pipe channel layer configured to couple the first and the second vertical channel layers; and a channel layer extension part generally extended from the pipe channel layer to the semiconductor substrate and configured to couple the pipe channel layer and the semiconductor substrate.01-10-2013
20130140627METHOD FOR PRODUCING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A SGT production method includes a step of forming first and second fin-shaped silicon layers, forming a first insulating film, and forming first and second pillar-shaped silicon layers; a step of forming diffusion layers by implanting an impurity into upper portions of the first and second pillar-shaped silicon layers, upper portions of the first and second fin-shaped silicon layers, and lower portions of the first and second pillar-shaped silicon layers; a step of forming a gate insulating film and first and second polysilicon gate electrodes; a step of forming a silicide in upper portions of the diffusion layers formed in the upper portions of the first and second fin-shaped silicon layers; and a step of depositing an interlayer insulating film, exposing and etching the first and second polysilicon gate electrodes, then depositing a metal, and forming first and second metal gate electrodes.06-06-2013
20130140628SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a cylindrical main pillar that is formed on a substrate and of which a central axis is perpendicular to the surface of the substrate, source and drain diffused layers that are formed in a concentric shape centered on the central axis at upper and lower portions of the main pillar and made from a first-conduction-type material, a body layer that is formed at an intermediate portion of the main pillar sandwiched between the source and drain diffused layers and made from the first-conduction-type material, and a front gate electrode that is formed on a lateral face of the main pillar while placing a gate insulating film therebetween. Moreover, a back gate electrode made from a second-conduction-type material is formed in a pillar shape penetrating from an upper portion to a lower portion on an inner side of the main pillar.06-06-2013
20130140629INSULATED GATE FIELD EFFECT TRANSISTOR HAVING PASSIVATED SCHOTTKY BARRIERS TO THE CHANNEL - A transistor having at least one passivated Schottky barrier to a channel includes an insulated gate structure on a p-type substrate in which the channel is located beneath the insulated gate structure. The channel and the insulated gate structure define a first and second undercut void regions that extend underneath the insulated gate structure toward the channel from a first and a second side of the insulated gate structure, respectively. A passivation layer is included on at least one exposed sidewall surface of the channel, and metal source and drain terminals are located on respective first and second sides of the channel, including on the passivation layer and within the undercut void regions beneath the insulated gate structure. At least one of the metal source and drain terminals comprises a metal that has a work function near a valence band of the p-type substrate.06-06-2013
20080224205Vertical Thin-Film Transistor with Enhanced Gate Oxide - A method is provided for forming a low-temperature vertical gate insulator in a vertical thin-film transistor (V-TFT) fabrication process. The method comprises: forming a gate, having vertical sidewalls and a top surface, overlying a substrate insulation layer; depositing a silicon oxide thin-film gate insulator overlying the gate; plasma oxidizing the gate insulator at a temperature of less than 400° C., using a high-density plasma source; forming a first source/drain region overlying the gate top surface; forming a second source/drain region overlying the substrate insulation layer, adjacent a first gate sidewall; and, forming a channel region overlying the first gate sidewall, in the gate insulator interposed between the first and second source/drain regions. When the silicon oxide thin-film gate insulator is deposited overlying the gate a Si oxide layer, a low temperature deposition process can be used, so that a step-coverage of greater than 65% can be obtained.09-18-2008
20130181280PSEUDO SELF ALIGNED RADHARD MOSFET AND PROCESS OF MANUFACTURE - A Vertical Power MOSFET (VDMOS) device with special features that enable the Power MOSFET or IGBT device to withstand harsh radiation environments and the process of making such a device is described. All implanted and diffused layers are “self aligned” to a “Sacrificial Poly” layer, which later on is removed, preparing the wafers for a “late gate” oxide to be grown. A starting material with graded doping profile in the epitaxial layer on the substrate is shown to increase the SEB capability of the Power MOSFET.07-18-2013
20130175606INTEGRATED CIRCUIT HAVING RAISED SOURCE DRAINS DEVICES WITH REDUCED SILICIDE CONTACT RESISTANCE AND METHODS TO FABRICATE SAME - A structure has at least one field effect transistor having a gate stack disposed between raised source drain structures that are adjacent to the gate stack. The gate stack and raised source drain structures are disposed on a surface of a semiconductor material. The structure further includes a layer of field dielectric overlying the gate stack and raised source drain structures and first contact metal and second contact metal extending through the layer of field dielectric. The first contact metal terminates in a first trench formed through a top surface of a first raised source drain structure, and the second contact metal terminates in a second trench formed through a top surface of a second raised source drain structure. Each trench has silicide formed on sidewalls and a bottom surface of at least a portion of the trench. Methods to fabricate the structure are also disclosed.07-11-2013
20130134501METHOD OF MANUFACTURING A VERTICAL-TYPE SEMICONDUCTOR DEVICE AND METHOD OF OPERATING A VERTICAL-TYPE SEMICONDUCTOR DEVICE - In a vertical-type semiconductor device, a method of manufacturing the same and a method of operating the same, the vertical-type semiconductor device includes a single-crystalline semiconductor pattern having a pillar shape provided on a substrate, a gate surrounding sidewalls of the single-crystalline semiconductor pattern and having an upper surface lower than an upper surface of the single-crystalline semiconductor pattern, a mask pattern formed on the upper surface of the gate, the mask pattern having an upper surface coplanar with the upper surface of the single-crystalline semiconductor pattern, a first impurity region in the substrate under the single-crystalline semiconductor pattern, and a second impurity region under the upper surface of the single-crystalline semiconductor pattern. The vertical-type pillar transistor formed in the single-crystalline semiconductor pattern may provide excellent electrical properties. The mask pattern is not provided on the upper surface of the single-crystalline semiconductor pattern in the second impurity region, to thereby reduce failures of processes.05-30-2013
20130093002MOSFET AND METHOD FOR MANUFACTURING THE SAME - The present disclosure discloses a MOSFET and a method for manufacturing the same, wherein the MOSFET comprises: an SOI wafer comprising a semiconductor substrate, a buried insulating layer on the semiconductor substrate, and a semiconductor layer on the buried insulating layer; a gate stack on the semiconductor layer; a source region and a drain region in the semiconductor layer on both sides of the gate stack; and a channel region in the semiconductor layer and located between the source region and the drain region, wherein the MOSFET further comprises a back gate which is located in the semiconductor substrate and has a first doped region as a lower portion of the back gate and a second doped region as an upper portion of the back gate, and the second doped region of the back gate is self-aligned with the gate stack. The MOSFET can adjust a threshold voltage by changing doping type and doping concentration of the back gate.04-18-2013
20130093005THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE - Three-dimensional (3D) semiconductor memory devices are provided. According to the 3D semiconductor memory device, a gate structure includes gate patterns and insulating patterns alternately stacked on a semiconductor substrate. A vertical active pattern penetrates the gate structure. A gate dielectric layer is disposed between a sidewall of the vertical active pattern and each of the gate patterns. A semiconductor pattern is disposed on the gate structure and is connected to the vertical active pattern. A string drain region is formed in a portion of the semiconductor pattern and is spaced apart from the vertical active pattern.04-18-2013
20130093004SEMICONDUCTOR DEVICE INCLUDING DUMMY PILLAR NEAR INTERMEDIATE PORTION OF SEMICONDUCTOR PILLAR GROUP - A semiconductor device includes a semiconductor pillar group having semiconductor pillars which are formed in a first direction with a space left therebetween. A dummy pillar is disposed near a particular semiconductor pillar in the semiconductor pillar group in a second direction perpendicular to the first direction that is any one of the semiconductor pillars which are positioned in an intermediate portion exclusive of both end portions. Gate insulating films are formed on outer circumferential surfaces of the semiconductor pillars. One gate insulating film is formed on a part of an outer circumferential surface of the dummy pillar. Formed over side faces of the semiconductor pillars and over a side face of the dummy pillar via the gate insulating films, gate electrodes fill gaps between the semiconductor pillars and a gap between the particular semiconductor pillar and the dummy pillar.04-18-2013
20130093003SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor device includes first, second, and third semiconductor layers each having multiple diffusion layers. The first direction widths of the first diffusion layers are the same. The amount of impurity within the first diffusion layers gradually increases from the bottom end towards the top end of the first semiconductor layer. The first direction widths of the second diffusion layers are the same. The amounts of impurity within the second diffusion layers are the same. The first direction widths of the third diffusion layers are narrower than the first direction widths of the first diffusion layers and the first direction widths of the second diffusion layers at the same level, and gradually become narrower from the bottom end towards the top end of the third semiconductor layer. The amount of impurity within the third. diffusion layers are the same.04-18-2013
20130093000VERTICAL TRANSISTOR HAVING AN ASYMMETRIC GATE - A transistor structure is formed to include a substrate and, overlying the substrate, a source; a drain; and a channel disposed vertically between the source and the drain. The channel is coupled to a gate conductor that surrounds the channel via a layer of gate dielectric material that surrounds the channel. The gate conductor is composed of a first electrically conductive material having a first work function that surrounds a first portion of a length of the channel and a second electrically conductive material having a second work function that surrounds a second portion of the length of the channel. A method to fabricate the transistor structure is also disclosed. The transistor structure can be characterized as being a vertical field effect transistor having an asymmetric gate.04-18-2013
20130093001POWER MOSFET DEVICE STRUCTURE FOR HIGH FREQUENCY APPLICATIONS - This invention discloses a new switching device that includes a drain disposed on a first surface and a source region disposed near a second surface of a semiconductor opposite the first surface. An insulated gate electrode is disposed on top of the second surface for controlling a source to drain current and a source electrode is interposed into the insulated gate electrode for substantially preventing a coupling of an electrical field between the gate electrode and an epitaxial region underneath the insulated gate electrode. The source electrode further covers and extends over the insulated gate for covering an area on the second surface of the semiconductor to contact the source region, An epitaxial layer is disposed above and having a different dopant concentration than the drain region. The gate electrode is insulated from the source electrode by an insulation layer having a thickness depending on a Vgsmax rating of the vertical power device.04-18-2013
20130113037METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A manufacturing method includes forming a fin-shaped silicon layer on a silicon substrate, forming a first insulating film around the fin-shaped silicon layer, and forming a pillar-shaped silicon layer on the fin-shaped silicon layer; forming diffusion layers in an upper portion of the pillar-shaped silicon layer, an upper portion of the fin-shaped silicon layer, and a lower portion of the pillar-shaped silicon layer; forming a gate insulating film, a polysilicon gate electrode, and a polysilicon gate wiring; forming a silicide in an upper portion of the diffusion layer in the upper portion of the fin-shaped silicon layer; depositing an interlayer insulating film, exposing the polysilicon gate electrode and the polysilicon gate wiring, etching the polysilicon gate electrode and the polysilicon gate wiring, and then depositing a metal to form a metal gate electrode and a metal gate wiring; and forming a contact.05-09-2013
20130119459SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method for manufacturing the same are disclosed, which form a bit line only at one side of a line pattern by partially etching a semiconductor substrate in a vertical gate structure, such that a body tied structure for reducing the floating body effect can be implemented. A semiconductor device includes a line pattern formed over a semiconductor substrate, a bit line buried in a bottom part of one side of the line pattern, and a gate formed over the bit line, and located perpendicular to the bit line.05-16-2013
20130126963SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device includes a semiconductor substrate having first and second regions, a first pillar transistor, and a second pillar transistor, wherein the first pillar transistor comprises a first semiconductor pillar disposed in the first region, and a first gate electrode covering a side surface of the first semiconductor pillar, wherein the second pillar transistor comprises a second semiconductor pillar disposed in the second region, and a second gate electrode covering a side surface of the second semiconductor pillar, wherein the first gate electrode is different in height from the second gate electrode, and the first and second pillar transistors form a CMOS device.05-23-2013
20130126964SEMICONDUCTOR DEVICE INCLUDING VERTICAL TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device including a vertical transistor and a method for forming the same are disclosed, which can greatly reduce a cell area as compared to a conventional layout of 8F2 and 6F2, and need not form a bit line contact, a storage node contact, or a land plug, such that the number of fabrication steps is reduced and a contact region between the bit line and the active region is increased in size. The semiconductor device including a vertical transistor includes an active region formed over a semiconductor substrate, a first recess formed to have a predetermined depth at both sides of the active region, and a bit line buried in the first recess.05-23-2013
20130134500POWER SEMICONDUCTOR DEVICE - A problem associated with n-channel power MOSFETs and the like that the following is caused even by relatively slight fluctuation in various process parameters is solved: source-drain breakdown voltage is reduced by breakdown at an end of a p-type body region in proximity to a portion in the vicinity of an annular intermediate region between an active cell region and a chip peripheral portion, arising from electric field concentration in that area. To solve this problem, the following measure is taken in a power semiconductor device having a superjunction structure in the respective drift regions of a first conductivity type of an active cell region, a chip peripheral region, and an intermediate region located therebetween: the width of at least one of column regions of a second conductivity type comprising the superjunction structure in the intermediate region is made larger than the width of the other regions.05-30-2013
20130175607SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF - A semiconductor device is provided. The semiconductor device includes a substrate having a first doping region and an overlying second doping region, wherein the first and second doping regions have a first conductivity type and wherein the second doping region has at least one first trench and at least one second trench adjacent thereto. A first epitaxial layer is disposed in the first trench and has a second conductivity type. A second epitaxial layer is disposed in the second trench and has the first conductivity type, wherein the second epitaxial layer has a doping concentration greater than that of the second doping region and less than that of the first doping region. A gate structure is disposed on the second trench. A method of fabricating a semiconductor device is also disclosed.07-11-2013
20130175609Semiconductor Device with a Low Ohmic Current Path - A semiconductor device includes a semiconductor substrate having a main horizontal surface, a back surface arranged opposite the main horizontal surface, a vertical transistor structure including a doped region and a control electrode arranged next to the main horizontal surface, an insulating region arranged at or close to the back surface, a deep vertical trench extending from the main horizontal surface through the semiconductor substrate and to the insulating region, an insulating layer arranged on a side wall of the deep vertical trench, and a low ohmic current path extending at least partially along the insulating layer and between the main horizontal surface and the back surface. A first metallization is in ohmic contact with the doped region and arranged on the main horizontal surface. A control metallization is arranged on the back surface and in ohmic contact with the control electrode via the low ohmic current path.07-11-2013
20130175608SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF - A semiconductor device is provided. The semiconductor device includes a plurality of first epitaxial layers, a second epitaxial layer and a gate structure. The plurality of first epitaxial layers is stacked on a substrate and has a first conductivity type. Each first epitaxial layer includes at least one first doping region and at least one second doping region adjacent thereto. The first doping region has a second conductivity and the second doping region has the first conductivity type. The second epitaxial layer is disposed on the plurality of first epitaxial layers, having the first conductivity type. The second epitaxial layer has a trench therein and a third doping region having the second conductivity type is adjacent to a sidewall of the trench. The gate structure is disposed on the second epitaxial layer above the second doping region. A method of fabricating a semiconductor device is also disclosed.07-11-2013
20100276749VERTICAL TRANSISTORS - The invention includes a semiconductor structure having U-shaped transistors formed by etching a semiconductor substrate. In an embodiment, the source/drain regions of the transistors are provided at the tops of pairs of pillars defined by crossing trenches in the substrate. One pillar is connected to the other pillar in the pair by a ridge that extends above the surrounding trenches. The ridge and lower portions of the pillars define U-shaped channels on opposite sides of the U-shaped structure, facing a gate structure in the trenches on those opposite sides, forming a two sided surround transistor. Optionally, the space between the pillars of a pair is also filled with gate electrode material to define a three-sided surround gate transistor. One of the source/drain regions of each pair extending to a digit line and the other extending to a memory storage device, such as a capacitor. The invention also includes methods of forming semiconductor structures.11-04-2010
20110215396SEMICONDUCTOR CELLS, ARRAYS, DEVICES AND SYSTEMS HAVING A BURIED CONDUCTIVE LINE AND METHODS FOR FORMING THE SAME - Semiconductor arrays including a plurality of access devices disposed on a buried conductive line and methods for forming the same are provided. The access devices each include a transistor having a source region and drain region spaced apart by a channel region of opposite dopant type and an access line associated with the transistor. The access line may be electrically coupled with one or more of the transistors and may be operably coupled to a voltage source. The access devices may be formed in an array on one or more conductive lines. A system may be formed by integrating the semiconductor devices with one or more memory semiconductor arrays or conventional logic devices, such as a complementary metal-oxide-semiconductor (CMOS) device.09-08-2011
20130146964METHOD OF PRODUCING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method for producing a semiconductor device includes the steps of forming a planar silicon layer, first and second pillar-shaped silicon layers on a silicon substrate; forming a gate insulating film, depositing a metal film and a polysilicon around the gate insulating film, conducting planarization, conducting etching to expose upper portions of the first and second pillar-shaped silicon layers, forming first and second insulating film sidewalls, and forming first and second gate electrodes and a gate line; forming n-type diffusion layers in upper and lower portions of the first pillar-shaped silicon layer, and forming p-type diffusion layers in upper and lower portions of the second pillar-shaped silicon layer; forming a third insulating film sidewall on side walls of the first and second insulating film sidewalls, the first and second gate electrodes, and the gate line; and forming a silicide.06-13-2013
20130146965METHODOLOGY FOR FABRICATING ISOTROPICALLY RECESSED DRAIN REGIONS OF CMOS TRANSISTORS - A method for fabricating recessed drain regions of aggressively scaled CMOS devices. In this method a processing sequence of plasma etch, deposition, followed by plasma etch is used to controllably form recessed regions of the drain in the channel of a thin body, much less than 40 nm, device to enable subsequent epitaxial growth of SiGe, SiC, or other materials, and a consequent increase in the device and ring oscillator performance. A Field Effect Transistor device is also provided, which includes: a buried oxide layer; a silicon layer above the buried oxide layer; an isotropically recessed drain region; and a gate stack which includes a gate dielectric, a conductive material, and a spacer.06-13-2013
20080197406Sensing FET integrated with a high-voltage vertical transistor - In one embodiment, a semiconductor device includes a main vertical field-effect transistor (FET) and a sensing FET. The main vertical FET and the sense FET are both formed on a pillar of semiconductor material. Both share an extended drain region formed in the pillar above the substrate, and first and second gate members formed in a dielectric on opposite sides of the pillar. The source regions of the main vertical FET and the sensing FET are separated and electrically isolated in a first lateral direction. In operation, the sensing FET samples a small portion of a current that flows in the main vertical FET. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.08-21-2008
20080197405TRENCH DIFFUSION ISOLATION IN POWER TRANSISTORS - A semiconductor structure comprises a plurality of columns doped with alternating dopants. The columns are separated by trenches, and the dopant is diffused in the doped columns. The trenches are filled with semiconductor material. Other embodiments may be described and claimed.08-21-2008
20120256254STRUCTURE AND FABRICATION PROCESS OF SUPER JUNCTION MOSFET - This invention discloses a specific superjunction MOSFET structure and its fabrication process. Such structure includes: a drain, a substrate, an EPI, a source, a side-wall isolation structure, a gate, a gate isolation layer and source. There is an isolation layer inside the active area underneath the source. Along the side-wall of this isolation layer, a buffer layer with same doping type as body can be introduced & source can be extended down too to form field plate. Such buffer layer & field plate can make the EPI doping much higher than convention device which results in lower Rdson, better performance, shorter gate so that to reduce both gate charge Qg and gate-to-drain charge Qgd. The process to make such structure is simpler and more cost effective.10-11-2012
20120256253Vertical Memory Devices - Vertical memory devices include a channel, a ground selection line (GSL), a word line, a string selection line (SSL), a pad and an etch-stop layer. The channel extends in a first direction on a substrate. The channel includes an impurity region and the first direction is perpendicular to a top surface of the substrate. At least one GSL, a plurality of the word lines and at least one SSL are spaced apart from each other in the first direction on a sidewall of the channel. The pad is disposed on a top surface of the channel. The etch-stop layer contacts the pad.10-11-2012
20100308399POWER SEMICONDUCTOR DEVICE - A power semiconductor device includes: a first semiconductor layer of the first conduction type; second semiconductor layers of the first conduction type and third semiconductor layers of the second conduction type alternately provided transversely on the first semiconductor layer; fourth semiconductor layers of the second conduction type provided on the surfaces of the third semiconductor layers; fifth semiconductor layers of the first conduction type provided selectively on the surfaces of the fourth semiconductor layer; sixth semiconductor layers of the second conduction type and seventh semiconductor layers of the first conduction type alternately provided transversely on the second and the third semiconductor layers; a first main electrode electrically connected to the first semiconductor layer; an insulation film provided on the fourth semiconductor layers, the sixth semiconductor layers and the seventh semiconductor layers; a control electrode provided on the fourth semiconductor layers, the sixth semiconductor layers and the seventh semiconductor layers via the insulation film; and a second main electrode joined to the surfaces of the fourth semiconductor layers and the fifth semiconductor layers, the sixth semiconductor layers being connected to the fourth semiconductor layers and to at least one of the third semiconductor layers, which is provided between two of the fourth semiconductor layers, and an impurity concentration of the third semiconductor layers provided below the sixth semiconductor layers being higher than an impurity concentration of the third semiconductor layers provided under the fourth semiconductor layers.12-09-2010
20120273873PACKAGE WITH MULTIPLE DIES - A semiconductor die package is disclosed. It includes a leadframe structure comprising a first die attach pad and a second die attach pad. A plurality of leads extend from the first and second die attach pads. The plurality of leads includes at least a first control lead and a second control lead. A first semiconductor die including a first device is mounted on the first die attach pad, and a second semiconductor die has a second device is mounted on the second die attach pad. A housing is provided in the semiconductor die package and protects the first and second dies. The housing may have an exterior surface and at least partially covers the first semiconductor die and the second semiconductor die. The first control lead and the second control lead are at opposite sides of the semiconductor die package.11-01-2012
20120273872Three Dimensional Semiconductor Memory Devices and Methods of Fabricating the Same - A three dimensional semiconductor memory device includes an electrode structure having a plurality of conductive electrode patterns and insulating patterns alternatingly stacked on a substrate. Opposite sidewalls of the electrode structure include respective grooves therein extending in a direction substantially perpendicular to the substrate. First and second active patterns protrude from the substrate and extend within the grooves in the opposite sidewalls of the electrode structure, respectively. Respective data storing layers extend in the grooves between the conductive electrode patterns of the electrode structure and sidewalls of the first and second active patterns adjacent thereto. Related fabrication methods are also discussed.11-01-2012
20120273871Superjunction Structures for Power Devices and Methods of Manufacture - A power device includes a semiconductor region which in turn includes a plurality of alternately arranged pillars of first and second conductivity type. Each of the plurality of pillars of second conductivity type further includes a plurality of implant regions of the second conductivity type arranged on top of one another along the depth of pillars of second conductivity type, and a trench portion filled with semiconductor material of the second conductivity type directly above the plurality of implant regions of second conductivity type.11-01-2012
20130187220VERTICAL MEMORY DEVICES, APPARATUSES INCLUDING VERTICAL MEMORY DEVICES, AND METHODS FOR FORMING SUCH VERTICAL MEMORY DEVICES AND APPARATUSES - Methods of forming vertical memory devices include forming first trenches, at least partially filling the first trenches with a polysilicon material, and forming second trenches generally perpendicular to the first trenches. The second trenches may be formed by removing one of silicon and oxide with a first material removal act and by removing the other of silicon and oxide in a different second material removal act. Methods of forming an apparatus include forming isolation trenches, at least partially filling the isolation trenches with a polysilicon material, and forming word line trenches generally perpendicular to the isolation trenches, the word line trenches having a depth in a word line end region about equal to or greater than a depth thereof in an array region. Word lines may be formed in the word line trenches. Semiconductor devices, vertical memory devices, and apparatuses are formed by such methods.07-25-2013
20130187221SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A method of forming a semiconductor device includes performing a first pre-amorphous implantation process on a substrate, where the substrate has a gate stack. The method further includes forming a first stress film over the substrate. The method also includes performing a first annealing process on the substrate and the first stress film. The method further includes performing a second pre-amorphous implantation process on the annealed substrate, forming a second stress film over the substrate, and performing a second annealing process on the substrate and the second stress film.07-25-2013
20130187222SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device includes forming a target etch layer, forming a first mask pattern on the target etch layer, wherein the first mask pattern includes line patterns extended in parallel in a first direction, forming a second mask pattern configured to include openings at positions where the openings overlap with spaces between the line patterns, before or after forming the first mask pattern, wherein each of the openings has a hole form and a first interval between the adjacent openings in the first direction is shorter than a second interval between the adjacent openings in a second direction that crosses the first direction, and forming holes by etching the target etch layer using the first mask pattern and the second mask pattern as a barrier.07-25-2013
20110233657High-voltage vertical transistor with a varied width silicon pillar - In one embodiment, a vertical HVFET includes a pillar of semiconductor material a pillar of semiconductor material arranged in a loop layout having at least two substantially parallel and substantially linear fillet sections each having a first width, and at least two rounded sections, the rounded sections having a second width narrower than the first width, a source region of a first conductivity type being disposed at or near a top surface of the pillar, and a body region of a second conductivity type being disposed in the pillar beneath the source region. First and second dielectric regions are respectively disposed on opposite sides of the pillar, the first dielectric region being laterally surrounded by the pillar, and the second dielectric region laterally surrounding the pillar. First and second field plates are respectively disposed in the first and second dielectric regions.09-29-2011
20110233656SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a semiconductor layer of a first conductivity type, first semiconductor pillar regions of the first conductivity type and second semiconductor pillar regions of a second conductivity type, a semiconductor region of the first conductivity type, a base region of the second conductivity type, a source region, a first main electrode, a second main electrode and a control electrode. The second semiconductor pillar region includes a plurality of semiconductor regions of the second conductivity type. A difference is provided between peak values of impurity concentration profiles of an uppermost and a lowermost semiconductor regions of the plurality of semiconductor regions, and in the alternately arranging direction of the first and second semiconductor pillar regions, maximum width of the uppermost semiconductor region is generally equal to or narrower than maximum width of the lowermost semiconductor region.09-29-2011
20110233658ELECTRONIC DEVICE INCLUDING AN INSULATING LAYER HAVING DIFFERENT THICKNESSES AND A CONDUCTIVE ELECTRODE AND A PROCESS OF FORMING THE SAME - An electronic device includes a transistor, wherein the electronic device can include a semiconductor layer having a primary surface, a channel region, a gate electrode, a source region, a conductive electrode, and an insulating layer lying between the primary surface of the semiconductor layer and the conductive electrode. The insulating layer has a first region and a second region, wherein the first region is thinner than the second region. The channel region, gate electrode, source region, or any combination thereof can lie closer to the first region than the second region. The thinner portion can allow for faster switch of the transistor, and the thicker portion can allow a relatively large voltage difference to be placed across the insulating layer. Alternative shapes for the transitions between the different regions of the insulating layer and exemplary methods to achieve such shapes are also described.09-29-2011
20130153987ELECTRONIC DEVICE COMPRISING A CONDUCTIVE STRUCTURE AND AN INSULATING LAYER WITHIN A TRENCH AND A PROCESS OF FORMING THE SAME - An electronic device can include a semiconductor layer overlying a substrate and having a primary surface and a thickness, wherein a trench extends through at least approximately 50% of the thickness of semiconductor layer to a depth. The electronic device can further include a conductive structure within the trench, wherein the conductive structure extends at least approximately 50% of the depth of the trench. The electronic device can still further include a vertically-oriented doped region within the semiconductor layer adjacent to and electrically insulated from the conductive structure; and an insulating layer disposed between the vertically-oriented doped region and the conductive structure. A process of forming an electronic device can include patterning a semiconductor layer to define a trench extending through at least approximately 50% of the thickness of the semiconductor layer and forming a vertically-oriented doped region after patterning the semiconductor layer to define the trench.06-20-2013
20130153988ELECTRONIC DEVICE INCLUDING A TRENCH WITH A FACET AND A CONDUCTIVE STRUCTURE THEREIN AND A PROCESS OF FORMING THE SAME - An electronic device can include a transistor structure including a semiconductor layer overlying a substrate and a trench extending into the semiconductor layer having a tapered shape. In an embodiment, the tapered shape includes a facet. The transistor structure can include a source region and a drain region wherein different portions of the drain regions are disposed adjacent to the primary surface and within the trench. In another embodiment, different facets may be spaced apart from each other. Processes of forming the tapered etch can be tailored based on the needs or desires of a fabricator.06-20-2013
20130153989METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A CMOS SGT manufacturing method includes a step of forming first and second fin-shaped silicon layers on a substrate, forming a first insulating film around the first and second fin-shaped silicon layers, and forming first and second pillar-shaped silicon layers; a step of forming n-type diffusion layers; a step of forming p-type diffusion layers; a step of forming a gate insulating film and first and second polysilicon gate electrodes; a step of forming a silicide in upper portions of the diffusion layers in upper portions of the first and second fin-shaped silicon layers; and a step of depositing an interlayer insulating film, exposing the first and second polysilicon gate electrodes, etching the first and second polysilicon gate electrodes, and then depositing a metal to form first and second metal gate electrodes.06-20-2013
20130153990SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - In a semiconductor device and a method for manufacturing the same, a pillar pattern is formed in an alternating pattern and a one side contact (OSC) is formed without using a tilted ion implantation process or a mask, resulting in formation of a vertical gate. The semiconductor device includes an alternating or zigzag-type pillar pattern formed over a semiconductor substrate, a first hole formed between pillars of the pillar pattern, a passivation layer formed over a sidewall of the first hole, a second hole formed by partially etching a lower part of the first hole, a bit line formed in the second hole, and a contact formed at a lower part of the pillar pattern.06-20-2013
20120280308VERTICAL POWER TRANSISTOR DIE PACKAGES AND ASSOCIATED METHODS OF MANUFACTURING - The present technology is directed generally to a semiconductor device. In one embodiment, the semiconductor device includes a first vertical transistor and a second vertical transistor, and the first vertical transistor is stacked on top of the second vertical transistor. The first vertical transistor is mounted on a lead frame with the source electrode of the first vertical transistor coupled to the lead frame. The second vertical transistor is stacked on the first vertical transistor with the source electrode of the second vertical transistor coupled to the drain electrode of the first vertical transistor.11-08-2012
20110303974INTEGRATED CIRCUIT DEVICES INCLUDING VERTICAL CHANNEL TRANSISTORS WITH SHIELD LINES INTERPOSED BETWEEN BIT LINES AND METHODS OF FABRICATING THE SAME - An integrated circuit device includes a plurality of pillars protruding from a substrate in a first direction. Each of the pillars includes source/drain regions in opposite ends thereof and a channel region extending between the source/drain regions. A plurality of conductive bit lines extends on the substrate adjacent the pillars in a second direction substantially perpendicular to the first direction. A plurality of conductive shield lines extends on the substrate in the second direction such that each of the shield lines extends between adjacent ones of the bit lines. Related fabrication methods are also discussed.12-15-2011
20110303973SEMICONDUCTOR DEVICE AND PRODUCTION METHOD - The semiconductor device according to the present invention is an nMOS SGT and is composed of a first n+ type silicon layer, a first gate electrode containing metal and a second n+ type silicon layer arranged on the surface of a first columnar silicon layer positioned vertically on a first planar silicon layer. Furthermore, a first insulating film is positioned between the first gate electrode and the first planar silicon layer, and a second insulating film is positioned on the top surface of the first gate electrode. In addition, the first gate electrode containing metal is surrounded by the first n+ type silicon layer, the second n+ type silicon layer, the first insulating film and the second insulating film.12-15-2011
20110303972SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device manufacturing method of an embodiment includes the steps of: forming a first insulating layer on a semiconductor substrate; forming on the first insulating layer an amorphous or polycrystalline semiconductor layer having a narrow portion; forming on the semiconductor layer a second insulating layer having a thermal expansion coefficient larger than that of the semiconductor layer; performing thermal treatment; removing the second insulating layer; forming a gate insulating film on the side faces of the narrow portion; forming a gate electrode on the gate insulating film; and forming a source-drain region in the semiconductor layer.12-15-2011
20120286351CELL ARRAY - A semiconductor device includes a plurality of pillars disposed to protrude from a semiconductor substrate, bit lines surrounding perimeters of portions of the plurality of pillars and extending in a first direction, gates spaced apart from the bit lines, surrounding perimeters of portions of the plurality of pillars over the bit lines, and extending to a second direction perpendicular to the first direction, and separation layers separating the gates parallel to the second direction. Therefore, the semiconductor device suitable to the high integration of semiconductor devices can be implemented.11-15-2012
20120018799SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method for manufacturing the same are provided. The method includes forming a cell structure where a storage node contact is coupled to a silicon layer formed over a gate, thereby simplifying the manufacturing process of the device. The semiconductor device includes a bit line buried in a semiconductor substrate; a plurality of gates disposed over the semiconductor substrate buried with the bit line; a first plug disposed in a lower portion between the gates and coupled to the bit line; a silicon layer disposed on the upper portion and sidewalls of the gate; and a second plug coupled to the silicon layer disposed over the gate.01-26-2012
20130193507SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes: a sense amplifier; a plurality of memory cell arrays; a shared MOS transistor that connects/disconnects the sense amplifier and a bit line included in the memory cell arrays; and a control circuit that controls operation of the shared MOS transistor. A part or whole of an in-sense-amplifier bit line that is a bit line connecting the sense amplifier and the shared MOS transistor is embedded in a semiconductor substrate.08-01-2013
20130193508SEMICONDUCTOR DEVICE WITH SUPER JUNCTION STRUCTURE AND METHOD FOR FABRICATING THE SAME - A semiconductor device with a super-junction structure is provided, including: a semiconductor substrate having a first conductivity type; an epitaxial layer having the first conductivity type formed over the semiconductor substrate; a first doping region having the first conductive type formed in a portion of the epitaxial layer; a second doping region having a second conductivity type formed in a portion of the of the epitaxial layer; a third doping region having the second conductivity type formed in a portion of the of the epitaxial layer, wherein the doping region partially comprises doped polysilicon materials having the second conductivity type; a gate dielectric layer formed over the epitaxial layer, partially overlying the well region; and a gate electrode formed over a portion of the gate dielectric layer.08-01-2013
20120025298WAFER LEVEL CHIP SCALE PACKAGE - A semiconductor device, a method of manufacturing semiconductor devices and a circuit package assembly are described. A semiconductor device can have a semiconductor substrate with first and second surfaces and a sidewall between them. First and second conductive pads on the first and second surfaces are in electrical contact with corresponding first and second semiconductor device structures in the substrate. An insulator layer on the first surface and sidewall covers a portion of the first conductive pad on the first surface. An electrically conductive layer on part of the insulator layer on the first conductive pad and sidewall is in electrical contact with the second conductive pad. The insulator layer prevents the conductive layer from making electrical contact between the first and second conductive pads.02-02-2012
20120068259THREE DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A three-dimensional semiconductor device includes a stacked structure including a plurality of conductive layers stacked on a substrate, a distance along a first direction between sidewalls of an upper conductive layer and a lower conductive layer being smaller than a distance along a second direction between sidewalls of the upper conductive layer and the lower conductive layer, the first and second directions crossing each other and defining a plane parallel to a surface supporting the substrate, and vertical channel structures penetrating the stacked structure.03-22-2012
20120080742Semiconductor device having vertical type transistor - A semiconductor device includes: a first vertical type transistor having a first lower diffusion layer, a first upper diffusion layer, and a gate electrode; a second vertical type transistor having a second lower diffusion layer, a second upper diffusion layer, and a second gate electrode; a gate wiring connected to the first and second gate electrodes; a first wiring connected to the first lower diffusion layer and second upper diffusion layer; and a second wiring connected to the first upper diffusion layer and second lower diffusion layer.04-05-2012
20120086072THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND RELATED METHOD OF MANUFACTURE - A method of manufacturing a three-dimensional semiconductor memory device comprises forming a thin layer structure by alternately stacking first and second material layers on a substrate, forming a penetration dent penetrating the thin layer structure and exposing a top surface of the substrate recessed by the penetration dent, forming a vertical insulation layer penetrating the thin layer structure to cover an inner wall of the penetration dent, forming a semiconductor pattern penetrating the vertical insulation layer at the penetration dent to be inserted into the substrate, and forming an oxide layer between the thin layer structure and the substrate by oxidizing a sidewall of the penetration dent.04-12-2012
20130207182SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes vertical channel layers, a pipe channel layer coupling bottoms of the vertical channel layers, a pipe gate contacting a bottom surface and side surfaces of the pipe channel layer, and a dummy pipe gate formed of a non-conductive material and contacting a top surface of the pipe channel layer.08-15-2013

Patent applications in class Gate controls vertical charge flow portion of channel (e.g., VMOS device)

Patent applications in all subclasses Gate controls vertical charge flow portion of channel (e.g., VMOS device)