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With additional, non-memory control electrode or channel portion (e.g., accessing field effect transistor structure)

Subclass of:

257 - Active solid-state devices (e.g., transistors, solid-state diodes)

257213000 - FIELD EFFECT DEVICE

257288000 - Having insulated electrode (e.g., MOSFET, MOS diode)

257314000 - Variable threshold (e.g., floating gate memory device)

257324000 - Multiple insulator layers (e.g., MNOS structure)

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Entries
DocumentTitleDate
20090194810SEMICONDUCTOR DEVICE USING ELEMENT ISOLATION REGION OF TRENCH ISOLATION STRUCTURE AND MANUFACTURING METHOD THEREOF - A stacked film including a gate dielectric film and electrode film of each memory cell of a flash memory is formed on a semiconductor substrate. The stacked film is patterned by reactive ion etching to form an isolation trench for formation of an element isolation region and the surface of the semiconductor substrate is exposed to the internal portion of the isolation trench. An O08-06-2009
20100078706Nonvolatile semiconductor memory device and method of manufacturing nonvolatile semiconductor memory device - A nonvolatile semiconductor memory device (and method of forming same) includes a word gate provided above a channel region of a semiconductor substrate via an insulating layer, a control gate provided at a side of the word gate, and a charge storage layer provided by an ONO film between the channel region and the control gate, and between the word gate and the control gate. The control gate includes a silicide layer including silicide containing nickel, and a non-silicide layer provided between the silicide layer and the charge storage layer.04-01-2010
20100072538NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A nonvolatile semiconductor memory device includes a plurality of memory strings, each of which has a plurality of electrically rewritable memory cells connected in series; and select transistors, one of which is connected to each of ends of each of the memory strings. Each of the memory strings is provided with a first semiconductor layer having a pair of columnar portions extending in a perpendicular direction with respect to a substrate, and a joining portion formed so as to join lower ends of the pair of columnar portions; a charge storage layer formed so as to surround a side surface of the columnar portions; and a first conductive layer formed so as to surround the side surface of the columnar portions and the charge storage layer, and configured to function as a control electrode of the memory cells. Each of the select transistors is provided with a second semiconductor layer extending upwardly from an upper surface of the columnar portions; and a second conductive layer formed so as to surround a side surface of the second semiconductor layer with a gap interposed, and configured to function as a control electrode of the select transistors.03-25-2010
20100072539MEMORY CELL OF NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A memory cell of a nonvolatile semiconductor memory device according to an embodiment of the invention has a MONOS structure. The charge storage layer of the memory cell includes insulating material layers. The relationship between the conduction band edge energy and valance band edge energy of the insulating material layers either increases gradually or decreases gradually from the tunnel insulating film toward the block insulating film. Furthermore, when the relative permittivity of the block insulating film is expresses as ∈03-25-2010
20100044778Non-volatile memory device and method of manufacturing same - A non-volatile memory device and a method of manufacturing the non-volatile memory device are provided. At least one first semiconductor layer and at least one second semiconductor layer are disposed. At least one control gate electrode is disposed between the at least one first semiconductor layer and the at least one second semiconductor layer. At least one first layer selection line is capacitively coupled to the at least one first semiconductor layer. At least one second layer selection line is capacitively coupled to the at least one second semiconductor layer.02-25-2010
20100044777RECONFIGURABLE SEMICONDUCTOR DEVICE - A reconfigurable semiconductor device is disclosed. The semiconductor device includes a substrate, a first insulating material formed on the substrate, two channels having different polarities, a plurality of terminal electrodes formed on the insulating material and coupled in common with the channels at their opposite ends, a second insulating material formed on the terminal electrodes, and a control gate formed on the second insulating material. The channels have different polarity and a charge storage layer is formed inside the second insulating material. The control gate is applied with a forward bias or a reverse bias and then the bias is cut off. The voltage-current characteristics of the semiconductor device are changed according to an electrical charge created in the charge storage layer.02-25-2010
20090159962Non-Volatile Memory Devices - Non-volatile memory devices are provided including a control gate electrode on a substrate; a charge storage insulation layer between the control gate electrode and the substrate; a tunnel insulation layer between the charge storage insulation layer and the substrate; a blocking insulation layer between the charge storage insulation layer and the control gate electrode; and a material layer between the tunnel insulation layer and the blocking insulation layer, the material layer having an energy level constituting a bottom of a potential well.06-25-2009
20100109075SEMICONDUCTOR DEVICE HAVING AN EXPANDED STORAGE NODE CONTACT AND METHOD FOR FABRICATING THE SAME - A semiconductor device is disclosed that stably ensures an area of a storage node contact connected to a junction region in an active region of the semiconductor device and is thus able to improve the electrical properties of the semiconductor device and enhance a yield, and a method for fabricating the same. The semiconductor device includes a semiconductor substrate having an active region including a gate, a storage node contact region, and an isolation region that defines the active region. A passing gate and an isolation structure surrounding the passing gate are formed in the isolation region. A silicon epitaxial layer is selectively formed over an upper portion of the passing gate to expand the storage node contact region.05-06-2010
20120181602SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a semiconductor memory device includes a semiconductor substrate, memory cell array portion, single-crystal semiconductor layer, and circuit portion. The memory cell array portion is formed on the semiconductor substrate, and includes memory cells. The semiconductor layer is formed on the memory cell array portion, and connected to the semiconductor substrate by being formed in a hole extending through the memory cell array portion.07-19-2012
20100327341NONVOLATILE SEMICONDUCTOR MEMORY DEVICE HAVING CHARGE STORAGE LAYERS AND MANUFACTURING METHOD THEREOF - A nonvolatile semiconductor memory device includes first electrodes, a second and a third electrode, a first film, a first inter layer film, a second inter layer film, and a second film. The first electrodes each have a charge storage and a control electrode. The second and the third electrodes are formed above the semiconductor substrate. The first film is formed on each sidewall of the second and third electrodes and formed on the surface of the semiconductor substrate. The first inter layer film filled in a gap between the second and third electrodes. The second inter layer film filled in a gap between the first and second electrode. The second film is formed on the first to third gate electrodes, the first film and the first inter layer film, and a second inter layer insulating film to suppress diffusion of hydrogen atoms included in the first inter layer film.12-30-2010
20130069142SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes an element isolation region having an element isolation insulating film therein; an active region delineated by the element isolation region; agate insulating film formed in the active region; a charge storage layer above the gate insulating film; and an interelectrode insulating film. The interelectrode insulating film is formed in a first region above an upper surface of the element isolation insulating film, a second region along a sidewall of the charge storage layer, and a third region above an upper surface of the charge storage layer. The interelectrode insulating film includes a stack of a first silicon oxide film, a first silicon nitride film, a second silicon oxide film, and a second silicon nitride film. A control electrode layer is formed above the interelectrode insulating film. The second silicon oxide film is thinner in the first region than in the third region.03-21-2013
20100084703SEMICONDUCTOR MEMORY DEVICE INCLUDING A STACKED GATE HAVING A CHARGE STORAGE LAYER AND A CONTROL GATE, AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory device includes a source region, a drain region, a channel region, a charge storage layer, and a control gate electrode. The source region and drain region are formed separately from each other in a surface of a semiconductor substrate. The channel region is formed in the semiconductor substrate and located between the source region and the drain region. The charge storage layer is formed on the channel region with a first insulating film interposed therebetween. The control gate electrode is formed on the charge storage layer with a second insulating film interposed therebetween. The control gate has an upper corner portion rounded with a radius of curvature of 5 nm or more.04-08-2010
20130062686NON-VOLATILE SEMICONDUCTOR MEMORY USING CHARGE-ACCUMULATION INSULATING FILM - There is provided a non-volatile semiconductor memory having a charge accumulation layer of a configuration where a metal oxide with a dielectric constant sufficiently higher than a silicon nitride, e.g., a Ti oxide, a Zr oxide, or a Hf oxide, is used as a base material and an appropriate amount of a high-valence substance whose valence is increased two levels or more (a VI-valence) is added to produce a trap level that enables entrance and exit of electrons with respect to the base material.03-14-2013
20100200908Nonvolatile memory device and method of fabricating the same - Provided are a nonvolatile memory device having a vertical folding structure and a method of manufacturing the nonvolatile memory device. A semiconductor structure includes first and second portions that are substantially vertical. A plurality of memory cells are arranged along the first and second portions of the semiconductor structure and are serially connected.08-12-2010
20120235226NONVOLATILE SEMICONDUCTOR MEMORY - A nonvolatile semiconductor memory of an aspect of the present invention includes a memory cell including, a charge storage layer on a gate insulating film, a multilayer insulator on the charge storage layer, and a control gate electrode on the multilayer insulator, the gate insulating film including a first tunnel film, a first high-dielectric-constant film on the first tunnel film and offering a greater dielectric constant than the first tunnel film, and a second tunnel film on the first high-dielectric-constant film and having the same configuration as that of the first tunnel film, the multilayer insulator including a first insulating film, a second high-dielectric-constant film on the first insulating film and offering a greater dielectric constant than the first insulating film, and a second insulating film on the second high-dielectric-constant film and having the same configuration as that of the first insulating film.09-20-2012
20100213538NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A memory string comprises: a first semiconductor layer having a plurality of columnar portions extending in a perpendicular direction with respect to a substrate, and joining portions joining lower ends of the plurality of columnar portions; a charge storage layer surrounding a side surface of the first semiconductor layer; and a first conductive layer surrounding a side surface of the charge storage layer and functioning as a control electrode of memory cells. A select transistor comprises: a second semiconductor layer extending upwardly from an upper surface of the columnar portions; an insulating layer surrounding a side surface of the second semiconductor layer; a second conductive layer surrounding a side surface of the insulating layer and functioning as a control electrode of the select transistors; and a third semiconductor layer formed on an upper surface of the second semiconductor layer and including silicon germanium.08-26-2010
20100213537NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A memory string comprises: a pair of columnar portions; a first insulating layer surrounding a side surface of the columnar portions; a charge storage layer surrounding a side surface of the first insulating layer; a second insulating layer surrounding a side surface of the charge storage layer; and a first conductive layer surrounding a side surface of the second insulating layer. A select transistor comprises: a second semiconductor layer extending from an upper surface of the columnar portions; a third insulating layer surrounding a side surface of the second semiconductor layer; a fourth insulating layer surrounding a side surface of the third insulating layer; and a second conductive layer surrounding a side surface of the fourth insulating layer. The first semiconductor layer is formed continuously in an integrated manner with the second semiconductor layer. The first insulating layer is formed continuously in an integrated manner with the third insulating layer.08-26-2010
20080308860Method of forming a pattern for a semiconductor device, method of forming a charge storage pattern using the same method, non-volatile memory device and methods of manufacturing the same - A method of forming a semiconductor device pattern, a method of forming a charge storage pattern, a non-volatile memory device including a charge storage pattern and a method of manufacturing the same are provided. The method of forming the charge storage pattern including forming a trench on a substrate, and a device isolation pattern in the trench. The device isolation pattern protrudes from a surface of the substrate such that an opening exposing the substrate is formed. A tunnel oxide layer is formed on the substrate in the opening. A preliminary charge storage pattern is formed on the tunnel oxide layer and the device isolation pattern by selective deposition of conductive materials. The preliminary charge storage pattern may be removed from the device isolation pattern. The preliminary charge storage pattern remains only on the tunnel oxide layer to form the charge storage pattern on the substrate.12-18-2008
20100032747SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor memory device includes a plurality of memory cell transistors each having a gate electrode section including a charge accumulation layer formed on a semiconductor substrate via a gate insulating film, a first insulating film formed using a material with a higher dielectric constant than the gate insulating film, a control gate, an impurity diffusion layer functioning as a source or a drain, and a plurality of barrier films formed on a side surface of the gate electrode section so as to cover a side surface of at least the first insulating film and formed between the first insulating film and the control gate. The device further includes a plurality of second insulating films formed on the semiconductor substrate and each formed between the gate electrode sections of adjacent ones of the plurality of memory cell transistors.02-11-2010
20090146207Nonvolatile Memory Devices Including Common Source - Provided is a nonvolatile memory device including a common source. The device includes a first active region crossing a second active region, a common source disposed in the second active region, and a source conductive line disposed on the common source in parallel to the common source. The source conductive line is electrically connected to the common source.06-11-2009
20080237698METHOD OF MAKING THREE DIMENSIONAL NAND MEMORY - A monolithic, three dimensional NAND string includes a first memory cell located over a second memory cell. A semiconductor active region of the first memory cell is a first pillar having a square or rectangular cross section when viewed from above, the first pillar being a first conductivity type semiconductor region located between second conductivity type semiconductor regions. A semiconductor active region of the second memory cell is a second pillar having a square or rectangular cross section when viewed from above, the second pillar located under the first pillar, the second pillar being a first conductivity type semiconductor region located between second conductivity type semiconductor regions. One second conductivity type semiconductor region in the first pillar contacts one second conductivity type semiconductor region in the second pillar.10-02-2008
20090321816Vertical-type non-volatile memory device - In a vertical-type non-volatile memory device, first and second single-crystalline semiconductor pillars are arranged to face each other on a substrate. Each of the first and second single-crystalline semiconductor pillars has a rectangular parallelepiped shape with first, second, third and fourth sidewalls. A first tunnel oxide layer, a first charge storage layer and a first blocking dielectric layer are sequentially stacked on the entire surface of the first sidewall of the first single-crystalline semiconductor pillar. A second tunnel oxide layer, a second charge storage layer and a second blocking dielectric layer are sequentially stacked on the entire surface of the first sidewall of the second single-crystalline semiconductor pillar. A word line makes contact with surfaces of both the first and second blocking dielectric layers. The word line is used in common for the first and second single-crystalline semiconductor pillars.12-31-2009
20100117141Memory cell transistors having limited charge spreading, non-volatile memory devices including such transistors, and methods of formation thereof - In one aspect, a transistor comprises: a substrate body; a tunnel oxide layer on the body; a charge trapping layer on the tunnel oxide layer; a blocking layer on the charge trapping layer; a control gate on the blocking layer, the control gate having first and second sidewalls, the first and second sidewalls being spaced apart from each other by a first distance; and charge confinement features on the body, the charge confinement features being spaced apart from each other by a second distance that is greater than or substantially equal to the first distance, the charge confinement features suppressing or preventing migration of charge present in the charge trapping layer.05-13-2010
20100123184NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - In a nonvolatile semiconductor memory device provided with memory cell transistors arranged in a direction and a select transistor to select the memory cell transistors, each of the memory cell transistors of a charge trap type are at least composed of a first insulating layer and a first gate electrode respectively, and the select transistor is at least composed of a second insulating layer and a second gate electrode. The first gate electrode is provided with a first silicide layer of a first width formed on the first insulating layer. The second gate electrode is provided with an impurity-doped silicon layer formed on the second insulating layer and with a second silicide layer of a second width formed on the impurity-doped silicon layer. The second silicide has the same composition as the first silicide. The second width is larger than the first width.05-20-2010
20090267139THREE DIMENSIONAL STACKED NONVOLATILE SEMICONDUCTOR MEMORY - A three dimensional stacked nonvolatile semiconductor memory according to examples of the present invention includes a memory cell array comprised of first and second blocks disposed side by side and a driver disposed between the first and second blocks. At least two conductive layers having the same structure as that of the at least two conductive layers in the first and second blocks are disposed on the driver, and select gate lines in the first and second blocks are connected to the driver through the at least two conductive layers on the driver.10-29-2009
20090267138SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A charge trap type non-volatile memory device has memory cells formed on a silicon substrate at a predetermined interval via an element isolation trench along a first direction in which word lines extend. Each of the memory cells has a tunnel insulating film formed on the silicon substrate, a charge film formed on the tunnel insulating film, and a common block film formed on the charge film. The common block film is formed in common with the memory cells along first direction. An element isolation insulating film buried in the element isolation trench has an upper portion of a side wall of the element isolation insulating film which contacts with a side wall of the charge film in each of the memory cells and a top portion of the element isolation insulating film which contacts with the common block film. A control electrode film is formed on the common block film.10-29-2009
20110147827Flash memory with partially removed blocking dielectric in the wordline direction - The present disclosure relates generally to the fabrication of non-volatile memory. In at least one embodiment, the present disclosure relates to forming a layered blocking dielectric which has a portion thereof removed in the wordline direction.06-23-2011
20090184365SEMICONDUCTOR MEMORY DEVICE USING SILICON NITRIDE FILM AS CHARGE STORAGE LAYER OF STORAGE TRANSISTOR AND MANUFACTURING METHOD THEREOF - A semiconductor memory device includes a tunnel insulating film, charge storage layer, block insulating film and control gate electrode stacked and formed on the surface of a semiconductor substrate. The charge storage layer is formed of an insulating film containing nitrogen. A dopant that reduces the trap density of charges moved in and out of an internal portion of the charge storage layer via the tunnel insulating film is doped into a region of the charge storage layer on the interface side with the tunnel insulating film or a dopant is doped into the above region with higher concentration in comparison with that of another region.07-23-2009
20090206393NONVOLATILE MEMORY ELEMENT AND METHOD OF MANUFACTURING THE SAME - A nonvolatile memory element includes a semiconductor region, a source region and a drain region provided in the semiconductor region, a tunnel insulating layer provided on the semiconductor region between the source region and the drain region, a charge storage layer provided on the tunnel insulating layer, a block insulating layer provided on the charge storage layer, and a control gate electrode provided on the block insulating layer. The charge storage layer includes one of an oxide, a nitride and an oxynitride, which contains at least one material selected from the group consisting of Hf, Al, Zr, Ti and a rare-earth metal, and is entirely or partially crystallized. The block insulating layer includes one of an oxide, an oxynitride, a silicate and an aluminate, which contains at least one rare-earth metal.08-20-2009
20090090965NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - A non-volatile semiconductor storage device has a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series. Each of the memory strings includes: a memory columnar semiconductor extending in a direction perpendicular to a substrate; a tunnel insulation layer contacting the memory columnar semiconductor; a charge accumulation layer contacting the tunnel insulation layer and accumulating charges; a block insulation layer contacting the charge accumulation layer; and a plurality of memory conductive layers contacting the block insulation layer. The lower portion of the charge accumulation layer is covered by the tunnel insulation layer and the block insulation layer.04-09-2009
20110193156ELECTRICALLY ERASABLE PROGRAMMABLE MEMORY AND ITS MANUFACTURING METHOD - The electrically erasable programmable memory and its manufacturing method of the present invention forms above the floating gate the polysilicon spacer regions that are extended from the central part of the source region; the insulating part between the polysilicon spacer region and the floating gate has a smaller thickness to increase the capacitance between the floating gate and the polysilicon spacer region and further increasing the voltage coupled to the floating gate. Therefore, the present invention can effectively increase the coupling capacitance at the drain terminal, and has an advantage of low cost and easy production.08-11-2011
20090090964SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a device isolation insulating film which is buried in a semiconductor substrate, a gate insulation film which is provided on the semiconductor substrate, a gate electrode which is provided on the gate insulation film, a source region and a drain region which are provided in the semiconductor substrate and spaced apart from each other in a manner to sandwich the gate electrode, both end portions of each of the source region and the drain region being offset from the device isolation insulating film in a channel width direction by a predetermined distance, and first and second gate electrode extension portions which are provided in a manner to cover both end portions of each of the source region and the drain region in a channel length direction.04-09-2009
20110198687HIGH-DENSITY FLASH MEMORY CELL STACK, CELL STACK STRING, AND FABRICATION METHOD THEREOF - Provided a flash memory cell stack, a flash memory cell stack string, a cell stack array, and a method of fabricating thereof. A flash memory cell stack includes a semiconductor substrate; a control electrode provided in a vertical pillar shape on a surface of the semiconductor substrate; an insulating film provided between the control electrode and the semiconductor substrate; a gate stack provided on a side surface of the control electrode; a plurality of first insulating films provided as layers on a side surface of the gate stack; a plurality of second doping semiconductor areas provided as layers on a side surface of the gate stack; and a first doping semiconductor area provided on side surfaces of the first insulating films and the second doping semiconductor areas, wherein the first insulating films and the second doping semiconductor areas are alternately provided as layers on the side surface of the gate stack.08-18-2011
20110198686NITRIDE READ ONLY MEMORY DEVICE WITH BURIED DIFFUSION SPACERS AND METHOD FOR MAKING THE SAME - A method for making a nitride read only memory device with buried diffusion spacers is disclosed. An oxide-nitride-oxide (ONO) layer is formed on top of a silicon substrate, and a polysilicon gate is formed over the ONO layer. The polysilicon gate is formed less than a length of the ONO layer. Two buried diffusion spacers are formed beside two sidewalls of the polysilicon gate and over the ONO layer. Two buried diffusion regions are implanted on the silicon substrate next to the two buried diffusion spacers. The two buried diffusion regions are then annealed such that the approximate interfaces of the buried diffusion regions are under the sidewalls of the polysilicon gate. The structure of a nitride read only memory device with buried diffusion spacers is also described.08-18-2011
20090294838NON-VOLATILE SEMICONDUCTOR MEMORY DEVICES - A non-volatile memory device includes a tunneling insulating layer on a semiconductor substrate, a charge storage layer, a blocking insulating layer, and a gate electrode. The charge storage layer is on the tunnel insulating layer and has a smaller band gap than the tunnel insulating layer and has a greater band gap than the semiconductor substrate. The blocking insulating layer is on the charge storage layer and has a greater band gap than the charge storage layer and has a smaller band gap than the tunnel insulating layer. The gate electrode is on the blocking insulating layer.12-03-2009
20110266612NAND-TYPE NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - The present invention provides a high-performance MONOS-type NAND-type nonvolatile semiconductor memory device using an aluminum oxide film as a part of gate insulating film in a select transistor and as a block insulating film in a memory transistor. The NAND-type nonvolatile semiconductor memory device has, on a semiconductor substrate, a plurality of memory cell transistors connected to each other in series and a select transistor. The memory cell transistor includes a first insulating film on the semiconductor substrate, a charge trapping layer, a second insulating film made of aluminum oxide, 11-03-2011
20110204433NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - A nonvolatile semiconductor storage device is disclosed. The nonvolatile semiconductor storage device includes a semiconductor substrate including a surface layer; an element isolation insulating film isolating the surface layer of the semiconductor device into a plurality of active regions; a first gate insulating film formed above the active regions; a charge storing layer formed above the first gate insulating film and including a silicon layer containing an upper layer selectively doped with carbon; a second gate insulating film formed above the charge storing layer; and a control gate electrode formed above the second gate insulating film.08-25-2011
20100127320NONVOLATILE SEMICONDUCTOR MEMORY - Two diffusion layers are provided in an element area. A tunnel insulating film is provided on the surface of the element area between the two diffusion layers. A charge storage layer is provided on the tunnel insulating film. A first insulator provided on the upper surface of the charge storage layer. An inter-electrode insulating film provided on the first insulator, on the side surface of the charge storage layer in a first direction and on the isolation insulating film. And a control gate electrode extends in the first direction and covers the charge storage layer via the first insulator and the inter-electrode insulating film. The first insulator is thicker than the inter-electrode insulating film, and the inter-electrode insulating film has a first slit on the first insulator.05-27-2010
20080283904TWO-BIT FLASH MEMORY CELL AND METHOD FOR MANUFACTURING THE SAME - A two-bit flash memory cell includes a substrate, a gate oxide layer disposed on the substrate, a gate stacked on the gate oxide layer. A charge storage spacer stack is disposed at either side of the gate. The charge storage spacer stack includes a bottom charge storage layer and an upper spacer layer. An insulating layer is disposed between the charge storage spacer stack and the gate. A liner is disposed underneath the bottom charge storage layer. A source/drain region is disposed at one side of the bottom charge storage layer within the substrate.11-20-2008
20080283905Nonvolatile memory devices and methods of fabricating the same - Provided are nonvolatile memory devices and methods of fabricating the same which may prevent or reduce deterioration of device characteristics and deterioration of a breakdown voltage. The nonvolatile memory device may include a semiconductor substrate, a charge-trap insulation layer on the semiconductor substrate and having a first region and second regions having a lower density of charge-trap sites than the first region, and a gate electrode on the charge-trap insulation layer, wherein the first region is overlapped by the gate electrode and the second regions are outside of the first region.11-20-2008
20090179256MEMORY HAVING SEPARATED CHARGE TRAP SPACERS AND METHOD OF FORMING THE SAME - A silicon-oxide-nitride-oxide-silicon (SONOS) memory and the corresponding forming method are disclosed. The memory includes a plurality of select gate structures arranged in an array, a plurality of charge trap spacers that do not contact each other, and a plurality of word lines. The word lines can directly contact the select gates' surfaces of the select gate structures. All of the select gate structures disposed in one line can share two charge trap spacers, and the two charge trap spacers are disposed on the opposed sidewalls of these select gate structures.07-16-2009
20090184364NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - A non-volatile semiconductor storage device includes device regions and device isolation regions that are formed on a semiconductor substrate, with a first direction defined as their longitudinal direction. The non-volatile semiconductor storage device also includes memory cells having a cell transistor formed on the device regions and a selection transistor to select the cell transistor. Each of gate electrode wires provides a common connection between a plurality of memory cells arranged in a line in a second direction, and is arranged to extend in the second direction. Each of the gate electrode wires has a first width on the device regions and a second width larger than the first width on the device isolation regions.07-23-2009
20090134453Non-Volatile Memory Device with Improved Immunity to Erase Saturation and Method for Manufacturing Same - A non-volatile memory device having a control gate on top of the second dielectric (interpoly or blocking dielectric), at least a bottom layer of the control gate in contact with the second dielectric being constructed in a material having a predefined high work-function and showing a tendency to reduce its work-function when in contact with a group of certain high-k materials after full device fabrication. At least a top layer of the second dielectric, separating the bottom layer of the control gate from the rest of the second dielectric, is constructed in a predetermined high-k material, chosen outside the group for avoiding a reduction in the work-function of the material of the bottom layer of the control gate. In the manufacturing method, the top layer is created in the second dielectric before applying the control gate.05-28-2009
20100200909SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - To provide a technique capable of improving reliability of a semiconductor device having a nonvolatile memory cell by suppressing the reduction of the drive force.08-12-2010
20090184366SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor memory device has a substrate having a semiconductor layer, an n-type semiconductor region formed beneath a main surface of the semiconductor layer, a plurality of cell gates being aligned at a space from each other and including a gate insulating film formed on the main surface of the semiconductor layer, a charge storage layer formed on the gate insulating film, a charge block layer formed on the charge storage layer and a control gate electrode formed on the charge block layer, an insulating film between cells formed on the main surface of the semiconductor layer between the cell gates, and a carbon accumulation region formed in the insulating film between the cells and has a maximum concentration of a carbon element in a region within 2 nm from an interface between the semiconductor layer and the insulating film between the cells.07-23-2009
20090001452Semiconductor device and manufacturing method thereof - The invention provides a semiconductor device and its manufacturing method in which a memory transistor and a plurality of thin film transistors that have gate insulating films with different thicknesses are fabricated over a substrate. The invention is characterized by the structural difference between the memory transistor and the plurality of thin film transistors. Specifically, the memory transistor and some of the plurality of thin film transistors are provided to have a bottom gate structure while the other thin film transistors are provided to have a top gate structure, which enables the reduction of characteristic defects of the transistor and simplification of its manufacturing process.01-01-2009
20090146208Independently controlled, double gate nanowire memory cell with self-aligned contacts - A double gate, dynamic storage device and method of fabrication are disclosed. A back (bias gate) surrounds three sides of a semiconductor body with a front gate disposed on the remaining surface. Two different gate insulators and gate materials may be used.06-11-2009
20090273021SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate, a tunnel insulating film on the semiconductor substrate, a charge storage layer on the tunnel insulating film, a block insulating film on the charge storage layer, and a control gate electrode on the block insulating film, the charge storage layer including a plurality of layers including first and second charge storage layers, the second charge storage layer being provided on a nearest side of the block insulating film, the first charge storage layer being provided between the tunnel insulating film and the second charge storage layer, the second charge storage layer having a higher trap density than the first charge storage layer, the second charge storage layer having a smaller band gap than the first charge storage layer, and the second charge storage layer having a higher permittivity than the first charge storage layer and a silicon nitride film.11-05-2009
20090101967SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes an insulating layer, a channel structure, an insulating structure and a gate. The channel structure includes a channel bridge for connecting two platforms. The bottom of the channel bridge is separated from the insulating layer by a distance, and the channel bridge has a plurality of separated doping regions. The insulating structure wraps around the channel bridge, and the gate wraps around the insulating structure.04-23-2009
20090200603High density vertical structure nitride flash memory - A charge trap type of memory having a memory channel with vertical and possibly horizontal components is described. The invention includes a new operation method of simultaneous hole and electron injection operation for high speed and high reliability non-volatile memories, as well as high-density non-volatile memories. Array implementations for high-density memory arrays and high-speed memory arrays and their fabrication methods are also described.08-13-2009
20120126309INTEGRATED NON-VOLATILE MEMORY (NVM) AND METHOD THEREFOR - A feature is formed in the NVM isolation region during the patterning and etching of an NVM device and a logic device such that the feature is of substantially equal height to the logic device and is well-defined so that it does not cause defect signals. A first conductive layer is formed over a substrate. The first conductive layer is patterned to expose at least a portion of the substrate in an NVM region and at least a portion of an isolation region. An NVM dielectric stack is formed over the first conductive layer, the exposed substrate, and the exposed isolation region, and a second conductive layer is formed over the NVM dielectric stack. The first and second conductive layers and the NVM dielectric stack are patterned to form a first gate and a second gate of an NVM cell in the NVM region and a feature over the isolation region. The feature comprises a portion of the first conductive layer, a portion of the NVM dielectric stack adjacent a first sidewall of the portion of the first conductive layer, and a portion of the second conductive layer adjacent the portion of the NVM dielectric stack.05-24-2012
20090230462NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - Each of the memory strings includes: a first columnar semiconductor layer extending in a vertical direction to a substrate; a plurality of first conductive layers formed to sandwich an insulation layer with a charge trap layer and expand in a two-dimensional manner; a second columnar semiconductor layer formed in contact with the top surface of the first columnar semiconductor layer and extending in a vertical direction to the substrate; and a plurality of second conductive layers formed to sandwich an insulation layer with the second columnar semiconductor layer and formed in a stripe pattern extending in a first direction orthogonal to the vertical direction. Respective ends of the plurality of first conductive layers in the first direction are formed in a stepwise manner in relation to each other, entirety of the plurality of the second conductive layers are formed in an area immediately above the top layer of the first conductive layers, and the plurality of first conductive layers and the plurality of second conductive layers are covered with a protection insulation layer that is formed continuously with the plurality of first conductive layers and the second conductive layers.09-17-2009
20090242970SEMICONDUCTOR DEVICE, CAPACITOR, AND FIELD EFFECT TRANSISTOR - It is made possible to provide a semiconductor device that has the effective work function of the connected metal optimized at the interface between a semiconductor and the metal. A semiconductor device includes: a semiconductor film; an oxide film formed on the semiconductor film, the oxide film including at least one of Hf and Zr, and at least one element selected from the group consisting of V, Cr, Mn, Nb, Mo, Tc, W, and Re being added to the oxide film; and a metal film formed on the oxide film.10-01-2009
20090250747NON-VOLATILE MEMORY DEVICES HAVING A MULTI-LAYERED CHARGE STORAGE LAYER - A non-volatile memory device includes a substrate having a first region and a second region. A first gate electrode is disposed on the first region. A multi-layered charge storage layer is interposed between the first gate electrode and the substrate, the multi-layered charge storage including a tunnel insulation, a trap insulation, and a blocking insulation layer which are sequentially stacked. A second gate electrode is placed on the substrate of the second region, the second gate electrode including a lower gate and an upper gate connected to a region of an upper surface of the lower gate. A gate insulation layer is interposed between the second gate electrode and the substrate. The first gate electrode and the upper gate of the second gate electrode comprise a same material.10-08-2009
20100013003NON-VOLATILE MEMORY CELL WITH A HYBRID ACCESS TRANSISTOR - An integrated circuit (IC) is disclosed. The IC comprises a substrate with a cell region defined thereon. The cell region comprises a thin gate doped well tailored for transistors with thin gate dielectric layers. The IC also includes a non-volatile memory cell in the cell region. The non-volatile memory cell has an access transistor and a storage transistor. The access transistor includes an access gate with an access gate dielectric comprising a thick gate dielectric layer on the thin gate doped well. Wells for transistors with thick gate dielectric layers have a lower dopant concentration than the thin gate doped well.01-21-2010
20100148242SEMICONDUCTOR DEVICE - A semiconductor device suppresses short-circuit failure between a selection gate electrode and a control gate electrode while shortening the distance between the upper portions of the selection gate electrode and the control gate electrode. The device includes an impurity region formed on both sides of a channel region of a semiconductor substrate; a selection gate electrode on the channel region via a gate insulating film; a control gate electrode in the shape of sidewall via a gate isolation insulating film on both side surfaces of the selection gate electrode and on the surface of the channel region; a protective insulating film covering the sidewall of the control gate electrode; and a silicide layer on the selection gate electrode. The protective insulating film is a two-layer structure of a silicon nitride film covering the sidewall of the control gate electrode and a silicon oxide film covering the silicon nitride film.06-17-2010
20100155826Non-volatile memory device and method of fabricating the same - Provided are a non-volatile memory device and a method of fabricating the same. The non-volatile memory device may include a substrate and a plurality of semiconductor pillars on the substrate. A plurality of control gate electrodes may be stacked on the substrate and intersecting the plurality of semiconductor pillars. A plurality of dummy electrodes may be stacked adjacent to the plurality of control gate electrodes on the substrate, the plurality of dummy electrodes being spaced apart from the plurality of control gate electrodes. A plurality of via plugs may be connected to the plurality of control gate electrodes. A plurality of wordlines may be on the plurality of via plugs. Each of the plurality of via plugs may penetrate a corresponding one of the plurality of control gate electrodes and at least one of the plurality of dummy electrodes.06-24-2010
20090078990NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device includes a charge storage layer on a first insulating film, a second insulating film which is provided on the charge storage layer, formed of layers, and a control gate electrode on the second insulating film. The second insulating film includes a bottom layer (A) provided just above the charge storage layer, a top layer (C) provided just below the control gate electrode, and a middle layer (B) provided between the bottom layer (A) and the top layer (C). The middle layer (B) has higher barrier height and lower dielectric constant than both the bottom layer (A) and the top layer (C). The average coordination number of the middle layer (B) is smaller than both the average coordination number of the top layer (C) and the average coordination number of the bottom layer (A).03-26-2009
20100013002NONVOLATILE STORAGE DEVICE AND METHOD FOR MANUFACTURING THE SAME - Provided is an excellent nonvolatile storage device having advantageous in miniaturization and less variation in initial threshold value, and exhibiting a high writing efficiency, without an erasing failure and a retention failure. The nonvolatile storage device is characterized by including a film stack extending from between a semiconductor substrate and a gate electrode onto at least a surface of the gate electrode lying on a first impurity diffusion region side, the film stack including a charge accumulating layer and a tunnel insulating film sequentially from a gate electrode side.01-21-2010
20120139031NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - In a nonvolatile semiconductor memory device provided with memory cell transistors arranged in a direction and a select transistor to select the memory cell transistors, each of the memory cell transistors of a charge trap type are at least composed of a first insulating layer and a first gate electrode respectively, and the select transistor is at least composed of a second insulating layer and a second gate electrode. The first gate electrode is provided with a first silicide layer of a first width formed on the first insulating layer. The second gate electrode is provided with an impurity-doped silicon layer formed on the second insulating layer and with a second silicide layer of a second width formed on the impurity-doped silicon layer. The second silicide has the same composition as the first silicide. The second width is larger than the first width.06-07-2012
20100237404SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - A semiconductor device having a non-volatile memory is disclosed, whose disturb defect can be diminished or prevented. A memory cell of the non-volatile memory has a memory gate electrode formed over a main surface of a semiconductor substrate through an insulating film for charge storage. A first side wall is formed on a side face of the memory gate electrode, and at a side face of the first side wall, a second side wall is formed. On an upper surface of an n09-23-2010
20120139032NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A memory device includes a semiconductor substrate, memory elements formed above the substrate in rows and columns, bit lines and word lines selectively connected with the memory elements in the respective columns and rows, each memory element including, a first gate insulator formed above the substrate, a charge accumulation layer formed on the first gate insulator, a second gate insulator formed on the charge accumulation layer, and a control electrode formed on the second gate insulator, wherein a ratio r/d is not smaller than 0.5, where r: a radius of curvature of an upper corner portion or surface roughness of the charge accumulation layer and d: an equivalent oxide thickness of the second gate insulator in a cross section along a direction vertical to the bit lines.06-07-2012
20100207195NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of columnar portions; a charge storage layer formed to surround the side surfaces of the columnar portions; and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers functions as gate electrodes of the memory cells.08-19-2010
20090278195SEMICONDUCTOR MEMORY DEVICE PROVIDED WITH STACKED LAYER GATE INCLUDING CHARGE ACCUMULATION LAYER AND CONTROL GATE, AND MANUFACTURING METHOD THEREOF - A semiconductor memory device includes a memory cell transistor and a first MOS transistor. The memory cell transistor includes a first insulating film, a second insulating film, a control gate electrode, and a first diffusion layer. The first insulating film formed on the first active region. The second insulating film formed on the first insulating film. The control gate electrode formed so as to include a first metal film formed on the second insulating film and a first conductive film formed on the first metal film. The first MOS transistor includes a second conductive film, a second metal film, a third conductive film, and a second diffusion layer. The second conductive film formed on a second active region. The second metal film formed on the second conductive film. The third conductive film formed on a second metal film.11-12-2009
20090114977NONVOLATILE MEMORY DEVICE HAVING CHARGE TRAPPING LAYER AND METHOD FOR FABRICATING THE SAME - Disclosed herein is a nonvolatile memory device having a charge trapping layer and a method of making the same. The nonvolatile memory device includes a substrate, a tunneling layer disposed on the substrate, a charge trapping layer disposed on the tunneling layer, a first blocking layer disposed on the charge trapping layer, a second blocking layer disposed on the first blocking layer, and a control gate electrode disposed on the second blocking layer. A first band gap between the first blocking layer and the charge trapping layer is larger than a second band gap between the second blocking layer and the charge trapping layer.05-07-2009
20090072298Semiconductor device and method of manufacturing the same - An embodiment of a semiconductor device includes a substrate including a cell region and a peripheral region; a cell gate pattern on the cell region; and a peripheral gate pattern on the peripheral region, wherein a first cell insulation layer, a second cell insulation layer, and a third cell insulation layer may be between the substrate and the cell gate pattern, a first peripheral insulation layer, a second peripheral insulation layer, and a third peripheral insulation layer may be between the substrate and the peripheral gate pattern, and the second cell insulation layer and the third cell insulation layer include the same material as the respective second peripheral insulation layer and third peripheral insulation layer.03-19-2009
20090108334Charge Trap Device and Method for Fabricating the Same - A charge trapping device includes a plurality of isolation layers, a plurality of charge trapping layers, a blocking layer, and a control gate electrode. The isolation layers define active regions, and the isolation layers and active regions extend as respective stripes along a first direction on a semiconductor substrate. The charge trapping layers are disposed on the active regions in island forms where the charge trapping layers are separated from each other in the first direction and disposed on the respective active regions between the isolation layers in a second direction perpendicular to the first direction. The blocking layer is disposed on the isolation layers and the charge trapping layers. The control gate electrode is disposed on the charge trapping layer.04-30-2009
20110127600SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device and a method of fabricating thereof, including preparing a substrate including a first and second region; forming first and second conductive lines on the first and second region, respectively, the first conductive lines being spaced apart at a first interval and the second conductive lines being spaced apart at a second interval wider than the first interval; forming a dielectric layer in spaces between the first and second conductive lines; etching the dielectric layer until a top surface thereof is lower than top surfaces of the first conductive lines and the second conductive lines; forming a spacer on the etched dielectric layer such that the spacer covers an entire top surface of the etched dielectric layer between the first conductive lines and exposes portions of the etched dielectric layer between the second conductive lines; and removing portions of the etched dielectric layer between the second conductive lines.06-02-2011
20110024827NONVOLATILE SEMICONDUCTOR MEMORY - A nonvolatile semiconductor memory according to an aspect of the invention comprises a semiconductor substrate which has an SOI region and an epitaxial region at its surface, a buried oxide film arranged on the semiconductor substrate in the SOI region, an SOI layer arranged on the buried oxide film, a plurality of memory cells arranged on the SOI layer, an epitaxial layer arranged in the epitaxial region, and a select gate transistor arranged on the epitaxial layer, wherein the SOI layer is made of a microcrystalline layer.02-03-2011
20110024826NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREFOR - A nonvolatile semiconductor memory device includes a first columnar protrusion and a second columnar protrusion formed to be spaced out on a surface of a semiconductor substrate, and the first and the second columnar protrusions each include a split gate nonvolatile memory cell in which a first source/drain region and a second source/drain region are formed at a surrounding part and an extremity, and in which a first layered structure, in which a charge accumulating film and a memory gate line are layered, and a second layered structure, in which a gate oxide film and a control gate line are layered, are formed on a surface of a sidewall between the surrounding part and the extremity. The first layered structure is also formed between the first and second columnar protrusions, whereby the memory gate line of the first columnar protrusion and the second columnar protrusion is connected each other.02-03-2011
20100163969FLASH MEMORY DEVICE AND MANUFACTURING METHOD THE SAME - A flash memory device and a method of manufacturing a flash memory device. A flash memory device may include an isolation layer and/or an active area over a semiconductor substrate, a memory gate formed over an active area, a control gate formed over a semiconductor substrate including a memory gate, and/or a common source line contact formed over a semiconductor substrate including a control gate. A flash memory device may include a source plate having substantially the same interval as an interval of an active area of a bit line. A source plate may include an active area in which a common source line contact may be formed. A common source line contact may include a long butting contact extending in a direction traversing an active area.07-01-2010
20100038704NONVOLATILE SEMICONDUCTOR MEMORY DEVICE SUPPRESSING FLUCTUATION IN THRESHOLD VOLTAGE - First and second memory cell transistors are isolated by an element isolation insulating film. A barrier insulating film covers the element isolation insulating film. The first memory cell transistor includes a first tunnel insulating film, a first charge storage layer made of an insulating film, a first block insulating film, and a first gate electrode. The second memory cell transistor includes a second tunnel insulating film, a second charge storage layer made of an insulating film, a second block insulating film, and a second gate electrode. The barrier insulating film is in contact with the first and second charge storage layers, and has a film thickness smaller than that of the first and second charge storage layers.02-18-2010
20090218615SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device according to an embodiment of the present invention has a bit line and a word line. The device includes a substrate, a first gate insulation film formed on the substrate, a charge storage layer formed on the first gate insulation film, a second gate insulation film formed on the charge storage layer, and a gate electrode formed on the second gate insulation film, the width between side surfaces of the second gate insulation film in the bit line direction being smaller than the width between side surfaces of the gate electrode in the bit line direction.09-03-2009
20100038703NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE - A memory string has a semiconductor layer with a joining portion that is formed to join a plurality of columnar portions extending in a vertical direction with respect to a substrate and lower ends of the plurality of columnar portions. First conductive layers are formed in a laminated fashion to surround side surfaces of the columnar portions and an electric charge storage layer, and function as control electrodes of memory cells. A second conductive layer is formed around the plurality of columnar portions via a gate insulation film, and functions as control electrodes of selection transistors. Bit lines are formed to be connected to the plurality of columnar portions, respectively, with a second direction orthogonal to a first direction taken as a longitudinal direction.02-18-2010
20100044779Memory devices capable of reducing lateral movement of charges - Memory devices is provided, the memory devices include a tunneling insulating layer disposed on a substrate, a charge storage layer disposed on the tunneling insulating layer, a blocking insulating layer disposed on the charge storage layer and a control gate electrode disposed on the blocking insulating layer. The control gate electrode may have an edge portion spaced farther apart from the blocking insulating layer than a central portion of the control gate electrode to concentrate charge density distribution on a central portion of a memory cell.02-25-2010
20100059813NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREFOR - A gate electrode of a select gate transistor includes a gate insulating film that is formed on a semiconductor substrate, a lower gate electrode that is formed on the gate insulating film and that has a tapered portion in which a side surface on a side of a gate electrode of a memory cell transistor is in a tapered shape, a first oxide film, a silicon nitride film, a second oxide film, and a conductive film that are sequentially formed on the tapered portion, and an upper gate electrode that is connected to the conductive film and the lower gate electrode.03-11-2010
20110248334MULTI-LEVEL CHARGE STORAGE TRANSISTORS AND ASSOCIATED METHODS - Methods of fabricating charge storage transistors are described, along with apparatus and systems that include them. In one such method, a pillar of epitaxial silicon is formed. At least first and second charge storage nodes (e.g., floating gates) are formed around the pillar of epitaxial silicon at different levels. A control gate is formed around each of the charge storage nodes. Additional embodiments are also described.10-13-2011
20110073937Method for Fabricating a Charge Trapping Memory Device - A method for fabricating a charge trapping memory device includes providing a substrate; forming a first oxide layer on the substrate; forming a number of BD regions in the substrate; nitridizing the interface of the first oxide layer and the substrate via a process; forming a charge trapping layer on the first oxide layer; and forming a second oxide layer on the charge trapping layer.03-31-2011
20100264483SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING SAME - A semiconductor storage device and method of manufacturing same at a lower cost by without forming a photolithographic resist. Second impurity regions are arranged in such a manner that second impurity regions adjacent along the column direction are joined together. A select gate electrode is arranged into a ring shape so as to surround the second impurity regions, and is electrically connected to a word line. A first control gate electrode is arranged into a ring shape on the outer peripheral side of the select gate electrode, and a second control gate electrode is arranged into a ring shape on the inner peripheral side of the select gate electrode. A pair of first and second bit lines corresponding to every row are placed on the memory cells of the device, a first bit line is electrically connected to one of first impurity regions that are adjacent along the row direction, and a second bit line is electrically connected to the other of the first impurity regions that are adjacent along the row direction.10-21-2010
20080315296NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - A non-volatile semiconductor storage device 12-25-2008
20090001451NON-VOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A method of fabricating a semiconductor device includes forming a fin-shaped active region including opposing sidewalls and a surface therebetween protruding from a substrate, forming a gate structure on the surface of the active region, and performing an ion implantation process to form source/drain regions in the active region at opposite sides of the gate structure. The source/drain regions respectively include a first impurity region in the surface of the active region and second impurity regions in the opposing sidewalls of the active region. The first impurity region has a doping concentration that is greater than that of the second impurity regions. Related devices are also discussed.01-01-2009
20120241846NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a nonvolatile semiconductor memory device comprises a first conductive layer, a second conductive layer, a first inter-electrode insulating film, and a third conductive layer stacked above the first conductive layer, a memory film, a semiconductor layer, an insulating member, and a silicide layer. The memory film and the semiconductor layer is formed on the inner surface of through hole provided in the second conductive layer, the first inter-electrode insulating film, and the third conductive layer. The insulating member is buried in a slit dividing the second conductive layer, the first inter-electrode insulating film, and the third conductive layer. The silicide layer is formed on surfaces of the second conductive layer and the third conductive layer in the slit. The distance between the second conductive layer and the third conductive layer along the inner surface of the slit is longer than that of along the stacking direction.09-27-2012
20120199898ULTRAHIGH DENSITY VERTICAL NAND MEMORY DEVICE AND METHOD OF MAKING THEREOF - Monolithic, three dimensional NAND strings include a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate, the blocking dielectric comprising a plurality of blocking dielectric segments, a plurality of discrete charge storage segments, and a tunnel dielectric located between each one of the plurality of the discrete charge storage segments and the semiconductor channel.08-09-2012
20130119458NOR FLASH MEMORY CELL AND STRUCTURE THEREOF - The present invention provides a NOR flash memory cell. The NOR flash memory cell includes a a substrate, an active area, a first gate structure, a second gate structure and at least one third gate structure. The first gate structure covers a first partial region of the active area and is formed by a silicon-rich nitride material. The second gate structure covers a second partial region of the active area. The third gate structure covers a third partial region between a first opening and the first gate structure. The active area has the first opening, the first opening disposed on a first side of the first gate structure and the first side is not neighbor to the second gate structure. The NOR flash memory cell further comprises a first conducting structure for covering the first opening to form a bit line signal receiving terminal.05-16-2013
20110169071NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING SAME - A memory string is formed to surround the side surface of a columnar portion and a charge storing layer, and includes plural first conductive layers functioning as gates of memory transistors, and a first protecting layer stacked to protect an upper portion of the plural first conductive layers. The plural first conductive layers constitute a first stairway portion formed stepwise such that their ends are located at different positions. Each first conductive layer constitutes a step of the first stairway portion. A top surface of a first portion of the first stairway portion is covered with the first protecting layer including a first number of layers, and A tope surface of a second portion of the first stairway portion located at a lower level than the first portion is covered with the first protecting layer including a second number of layers fewer than the first number of layers.07-14-2011
20100065902SCALABLE HIGH DENSITY NON-VOLATILE MEMORY CELLS IN A CONTACTLESS MEMORY ARRAY - A plurality of mesas are formed in the substrate. Each pair of mesas forms a trench. A plurality of diffusion areas are formed in the substrate. A mesa diffusion area is formed in each mesa top and a trench diffusion area is formed under each trench. A vertical, non-volatile memory cell is formed on each sidewall of the trench. Each memory cell is comprised of a fixed threshold element located vertically between a pair of non-volatile gate insulator stacks. In one embodiment, each gate insulator stack is comprised of a tunnel insulator formed over the sidewall, a deep trapping layer, and a charge blocking layer. In another embodiment, an injector silicon rich nitride layer is formed between the deep trapping layer and the charge blocking layer.03-18-2010
20110175159NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE - Each of the memory blocks includes: a first conductive layer expanding in parallel to the substrate over the first area, n layers of the first conductive layers being formed in a lamination direction and shared by the plurality of memory strings; a first semiconductor layer; and an electric charge accumulation layer. The memory strings are arranged with m columns in a second direction for each of the memory blocks. The wiring layers are arranged in the second direction, formed to extend to the vicinity of one end of the first conductive layer in the first direction from one side of the memory block, and connected via contact plugs to the first conductive layers. A relation represented by (Formula 1) is satisfied: (Formula 1) m>=n07-21-2011
20100025754SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - To improve characteristics of a semiconductor device having a nonvolatile memory.02-04-2010
20100025755SEMICONDUCTOR DEVICE - In the trap type memory chip the withstanding voltage is raised up, and then the electric current for reading out is increased. There are formed on the p-type semiconductor substrate 02-04-2010
20110215395MULTI-TRANSISTOR MEMORY CELL - The invention relates to a multi-transistor, e.g. two-transistor memory cell arranged on a semiconductor substrate 09-08-2011
20100019312SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a semiconductor region, a tunnel insulating film formed on a surface of the semiconductor region, a charge-storage insulating film formed on a surface of the tunnel insulating film and containing silicon and nitrogen, a block insulating film formed on a surface of the charge-storage insulating film, and a control gate electrode formed on a surface of the block insulating film, wherein the tunnel insulating film has a first insulating film formed on the surface of the semiconductor region and containing silicon and oxygen, a second insulating film formed on a surface of the first insulating film, and a third insulating film formed on a surface of the second insulating film and containing silicon and oxygen, and a charge trap state in the second insulating film has a lower density than that in the charge-storage insulating film.01-28-2010
20100019311SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - This semiconductor memory device comprises a semiconductor substrate, a plurality of tunnel insulator films formed on the semiconductor substrate along a first direction and a second direction orthogonal to the first direction with certain spaces in each directions, a plurality of charge accumulation layers formed on the plurality of tunnel insulator films, respectively, a plurality of element isolation regions formed on the semiconductor substrate, the plurality of element isolation regions including a plurality of trenches formed along the first direction between the plurality of tunnel insulator films, a plurality of element isolation films filled in the plurality of trenches, a plurality of inter poly insulator films formed over the plurality of element isolation regions and on the upper surface and side surfaces of the plurality of charge accumulation layer along the second direction in a stripe shape, a plurality of air gaps formed between the plurality of element isolation films filled in the plurality of trenches and the plurality of inter poly insulator films and a plurality of control gate electrodes formed on the plurality of inter poly insulator films.01-28-2010
20120146128NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - In a nonvolatile semiconductor memory device provided with memory cell transistors arranged in a direction and a select transistor to select the memory cell transistors, each of the memory cell transistors of a charge trap type are at least composed of a first insulating layer and a first gate electrode respectively, and the select transistor is at least composed of a second insulating layer and a second gate electrode. The first gate electrode is provided with a first silicide layer of a first width formed on the first insulating layer. The second gate electrode is provided with an impurity-doped silicon layer formed on the second insulating layer and with a second silicide layer of a second width formed on the impurity-doped silicon layer. The second silicide has the same composition as the first silicide. The second width is larger than the first width.06-14-2012
20110156132NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device according to an embodiment includes memory strings which have a plurality of transistors including gate electrode films formed over sides of columnar semiconductor films on gate dielectric films in a height direction of the semiconductor films, and which are arranged in a matrix shape substantially perpendicularly above a substrate. The gate electrode films of the transistors at same height of the memory strings arranged in a first direction are connected to one another. A distance between the semiconductor films at least in a forming position of the transistor at an uppermost layer of the memory strings adjacent to each other in the first direction is smaller than double of thickness of the gate dielectric films.06-30-2011
20100006924ONE-TIME PROGRAMMABLE READ-ONLY MEMORY - A one-time programmable read-only memory (OTP-ROM) including a substrate, a first doped region, a second doped region, a third doped region, a first dielectric layer, a select gate, a second dielectric layer, a first channel, a second channel and a silicide layer is provided. The first doped region, the second doped region and the third doped region are disposed apart in a substrate. The first dielectric layer is disposed on the substrate between the first doped region and the second doped region. The select gate is disposed on the first dielectric layer. The second dielectric layer is disposed on the substrate between the second doped region and the third doped region. The silicide layer is disposed on the first doped region, the second doped region and the third doped region. The OTP-ROM stores data by a punch-through effect occurring between the second doped region and the third doped region.01-14-2010
20120012921MEMORY ARRAYS HAVING SUBSTANTIALLY VERTICAL, ADJACENT SEMICONDUCTOR STRUCTURES AND THE FORMATION THEREOF - Memory arrays and methods of their formation are disclosed. One such memory array has memory-cell strings are formed adjacent to separated substantially vertical, adjacent semiconductor structures, where the separated semiconductor structures couple the memory cells of the respective strings in series. For some embodiments, two dielectric pillars may be formed from a dielectric formed in a single opening, where each of the dielectric pillars has a pair of memory-cell strings adjacent thereto and where at least one memory cell of one of the strings on one of the pillars and at least one memory cell of one of the strings on the other pillar are commonly coupled to an access line.01-19-2012
20090039417Nonvolatile Flash Memory Device and Method for Producing Dielectric Oxide Nanodots on Silicon Dioxide - A method of producing dielectric oxide nanodots (02-12-2009
20110049612NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - According to one embodiment, a nonvolatile semiconductor memory device including a semiconductor layer with a main surface, a first insulating layer formed on the main surface of the semiconductor layer, a charge storage layer formed on the first insulating layer, a second insulating layer formed on the charge storage layer, and a control gate electrode formed on the second insulating layer. At least one inelastic scattering film that reduces energy of electrons by scattering is contained in at least one of the charge storage layer and second insulating layer.03-03-2011
20110049611NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD OF NONVOLATILE SEMICONDUCTOR STORAGE DEVICE - In a memory cell portion, a stacked structure, in which dielectric layers and semiconductor layers are alternately stacked, is arranged in a fin shape on a semiconductor substrate, and in a peripheral circuit portion, a gate electrode is arranged on the semiconductor substrate via a gate dielectric film so that a height of an upper surface of the gate electrode is set to be substantially equal to a height of an upper surface of the stacked structure in which the dielectric layers and the semiconductor layers are alternately stacked.03-03-2011
20120132985NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a plurality of memory cells are provided on a semiconductor substrate. In each memory cell, a control gate electrode is provided on a charge accumulation layer with an inter-electrode insulation film interposed between the control gate electrode and the charge accumulation layer, an air gap is provided between the charge accumulation layers adjacent to each other in a word line direction, and an insulation film disposed below the inter-electrode insulation film is divided into an upper part and a lower part by the air gap.05-31-2012
20120211823SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory device includes a lower select transistor formed within a semiconductor substrate, memory cells stacked over the lower select transistors, and an upper select transistor formed over the memory cells.08-23-2012
20100270610NROM FLASH MEMORY DEVICES ON ULTRATHIN SILICON - An NROM flash memory cell is implemented in an ultra-thin silicon-on-insulator structure. In a planar device, the channel between the source/drain areas is normally fully depleted. An oxide layer provides an insulation layer between the source/drain areas and the gate insulator layer on top. A control gate is formed on top of the gate insulator layer. In a vertical device, an oxide pillar extends from the substrate with a source/drain area on either side of the pillar side. Epitaxial regrowth is used to form ultra-thin silicon body regions along the sidewalls of the oxide pillar. Second source/drain areas are formed on top of this structure. The gate insulator and control gate are formed on top.10-28-2010
20090090963SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A plurality of memory cells each constituted of a memory cell transistor having a gate electrode in a laminated structure composed of a charge storage layer and a control gate layer and a select transistor having source/drain diffusion layers while one of the source/drain diffusion layers is shared by the memory cell transistor are arranged in and on a semiconductor substrate. The impurity concentration of the source/drain diffusion layer shared by the memory cell transistor and the select transistor in each of the plurality of memory cells is set lower than the impurity concentration of the other source/drain diffusion layers in each of the memory cells.04-09-2009
20120217573NON-VOLATILE MEMORY (NVM) CELL FOR ENDURANCE AND METHOD OF MAKING - A first dielectric is formed over a semiconductor layer, a first gate layer over the first dielectric, a second dielectric over the first gate layer, and a third dielectric over the second dielectric. An etch is performed to form a first sidewall of the first gate layer. A second etch is performed to remove portions of the first dielectric between the semiconductor layer and the first gate layer to expose a bottom corner of the first gate layer and to remove portions of the second dielectric between the first gate layer and the third dielectric layer to expose a top corner of the first gate layer. An oxide is grown on the first sidewall and around the top and bottom corners to round the corners. The oxide is then removed. A charge storage layer and second gate layer is formed over the third dielectric layer and overlapping the first sidewall.08-30-2012
20100006925NON-VOLATILE TWO TRANSISTOR MEMORY CELL AND METHOD FOR PRODUCING THE SAME - The invention relates to a nonvolatile two-transistor semiconductor memory cell and an associated fabrication method, source and drain regions (01-14-2010
20100244122MEMORY UTILIZING OXIDE NANOLAMINATES - Structures, systems and methods for transistors utilizing oxide nanolaminates are provided. One transistor embodiment includes a first source/drain region, a second source/drain region, and a channel region therebetween. A gate is separated from the channel region by a gate insulator. The gate insulator includes oxide insulator nanolaminate layers with charge trapping in potential wells formed by different electron affinities of the insulator nanolaminate layers.09-30-2010
20090065852NONVOLATILE MEMORY DEVICE WITH NANOWIRE CHANNEL AND METHOD FOR FABRICATING THE SAME - A nonvolatile memory device with nanowire channel and a method for fabricating the same are proposed, in which side etching is used to shrink side walls of a side-gate to form a nanowire pattern, thereby fabricating a nanowire channel on the dielectric of the side walls of the side-gate. A nonvolatile memory device with nanowire channel and dual-gate control can thus be achieved. This nonvolatile memory device can enhance data writing and erasing efficiency, and also has the capability of low voltage operation. Moreover, through a process of low cost and easy steps, highly reproducible and mass producible fabrication of nanowire devices can be accomplished.03-12-2009
20110121382SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD THEREOF - Over the top of a semiconductor substrate, a lamination pattern having a control gate electrode, a first insulation film thereover, and a second insulation film thereover is formed. Over the top of the semiconductor substrate, a memory gate electrode adjacent to the lamination pattern is formed. Between the control gate electrode and the semiconductor substrate, a third insulation film for gate insulation film is formed. Between the memory gate electrode and the semiconductor substrate, and between the lamination pattern and the memory gate electrode, a fourth insulation film including a lamination film of a silicon oxide film, a silicon nitride film, and another silicon oxide film is formed. At the sidewall on the side of the lamination pattern adjacent to the memory gate electrode, the first insulation film is retreated from the control gate electrode and the second insulation film, and the upper end corner portion of the control gate electrode is rounded.05-26-2011
20080296664INTEGRATION OF NON-VOLATILE CHARGE TRAP MEMORY DEVICES AND LOGIC CMOS DEVICES - A semiconductor structure and method to form the same. The semiconductor structure includes a substrate having a non-volatile charge trap memory device disposed on a first region and a logic device disposed on a second region. A charge trap dielectric stack may be formed subsequent to forming wells and channels of the logic device. HF pre-cleans and SC1 cleans may be avoided to improve the quality of a blocking layer of the non-volatile charge trap memory device. The blocking layer may be thermally reoxidized or nitridized during a thermal oxidation or nitridation of a logic MOS gate insulator layer to densify the blocking layer. A multi-layered liner may be utilized to first offset a source and drain implant in a high voltage logic device and also block silicidation of the nonvolatile charge trap memory device.12-04-2008
20080296663SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device according to an embodiment of the present invention includes a first gate insulator, a first gate electrode, a second gate insulator, and a second gate electrode. Regarding the thickness of the second gate insulator, the thickness of the insulator, on a first edge of the first gate electrode in the word-line direction, and the thickness of the insulator, on a second edge of the first gate electrode in the word-line direction, are larger than, the thickness of the insulator, on the upper surface of the first gate electrode, the thickness of the insulator, on the first side of the first gate electrode in the word-line direction, and the thickness of the insulator, on the second side of the first gate electrode in the word-line direction.12-04-2008
20120261743SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND A METHOD OF MANUFACTURING THE SAME - A semiconductor device having plural memory cell regions featuring nonvolatile memory cells, each nonvolatile memory cell including a first insulating film formed over a semiconductor substrate, a control electrode formed over the first insulating film, the first insulating film acting as a gate insulator for the control gate electrode, a second insulating film formed over the semiconductor substrate, and a memory gate electrode formed over the second insulating film and arranged adjacent with the control gate electrode through the second gate insulating film, the second insulating film acting as a gate insulator for the memory gate electrode and featuring a non-conductive charge trap film, wherein each of the nonvolatile memory cells of a first memory cell region and each of the nonvolatile memory cells of a second memory cell region are formed adjacent to one another such that a drain region is shared between them.10-18-2012
20120299087NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A non-volatile memory device includes gate structures including first insulation layers that are alternately stacked with control gate layers over a substrate, wherein the gate structures extend in a first direction, channel lines that each extend over the gate structures in a second direction different from the first direction, a memory layer formed between the gate structures and the channel lines and arranged to trap charges by electrically insulating the gate structures from the channel lines, bit line contacts forming rows that each extend in the first direction and contacting top surfaces of the channel lines, source lines that each extend in the first direction and contact the top surfaces of the channel lines, wherein the source lines alternate with the rows of bit line contacts, and bit lines that are each formed over the bit line contacts and extend in the second direction.11-29-2012
20110210387NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device includes a charge storage layer on a first insulating film, a second insulating film which is provided on the charge storage layer, formed of layers, and a control gate electrode on the second insulating film. The second insulating film includes a bottom layer (A) provided just above the charge storage layer, a top layer (C) provided just below the control gate electrode, and a middle layer (B) provided between the bottom layer (A) and the top layer (C). The middle layer (B) has higher barrier height and lower dielectric constant than both the bottom layer (A) and the top layer (C). The average coordination number of the middle layer (B) is smaller than both the average coordination number of the top layer (C) and the average coordination number of the bottom layer (A).09-01-2011
20120080741SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a device isolation insulating film which is buried in a semiconductor substrate, a gate insulation film which is provided on the semiconductor substrate, a gate electrode which is provided on the gate insulation film, a source region and a drain region which are provided in the semiconductor substrate and spaced apart from each other in a manner to sandwich the gate electrode, both end portions of each of the source region and the drain region being offset from the device isolation insulating film in a channel width direction by a predetermined distance, and first and second gate electrode extension portions which are provided in a manner to cover both end portions of each of the source region and the drain region in a channel length direction.04-05-2012
20120326225NON-VOLATILE MEMORY DEVICE - A non-volatile memory device includes a substrate having an active region defined by a device isolation region that has a trench and an air gap, a device isolation pattern positioned at a lower portion of the trench, a memory cell layer including a tunnel insulation layer, a trap insulation layer and a blocking insulation layer that are sequentially stacked on the active region and one of which extends from the active region toward the device isolation region encloses top of the air gap whose bottom is defined by a layer other than that of the top, and a control gate electrode positioned on the cell structure. The one of the insulation layer extending includes a recess at a region corresponding to the center of the air gap.12-27-2012
20120139030NONVOLATILE SEMICONDUCTOR MEMORY - According to one embodiment, a nonvolatile semiconductor memory includes first to n-th (n is a natural number not less than 2) semiconductor layers in a first direction and extend in a second direction, and the semiconductor layers having a stair case pattern in a first end of the second direction, a common semiconductor layer connected to the first to n-th semiconductor layers commonly in the first end of the second direction, first to n-th layer select transistors which are provided in order from the first electrode side between the first electrode and the first to n-th memory strings, and first to n-th impurity regions which make the i-th layer select transistor (i is one of 1 to n) a normally-on state in the first end of the second direction of the i-th semiconductor layer.06-07-2012
20080237700Nonvolatile memory device having cell and peripheral regions and method of making the same - A nonvolatile memory device and method of making the same are provided. Memory cells may be provided in a cell area wherein each memory cell has an insulative structure including a tunnel insulating layer, a floating trap layer and a blocking layer, and a conductive structure including an energy barrier layer, a barrier metal layer and a low resistance gate electrode. A material having a lower resistivity may be used as the gate electrode so as to avoid problems associated with increased resistance and to allow the gate electrode to be made relatively thin. The memory device may further include transistors in the peripheral area, which may have a gate dielectric layer, a lower gate electrode of poly-silicon and an upper gate electrode made of metal silicide, allowing an improved interface with the lower gate electrode without diffusion or reaction while providing a lower resistance.10-02-2008
20080237699NONVOLATILE SEMICONDUCTOR MEMORY AND MANUFACTURING METHOD THEREOF - A nonvolatile semiconductor memory includes a source area and a drain area provided on a semiconductor substrate with a gap which serves as a channel area, a first insulating layer, a charge accumulating layer, a second insulating layer (block layer) and a control electrode, formed successively on the channel area, and the second insulating layer is formed by adding an appropriate amount of high valence substance into base material composed of substance having a sufficiently higher dielectric constant than the first insulating layer so as to accumulate a large amount of negative charges in the block layer by localized state capable of trapping electrons, so that the high dielectric constant of the block layer and the high electronic barrier are achieved at the same time.10-02-2008
20090179257NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A non-volatile semiconductor memory device includes a first columnar semiconductor layer and a plurality of first conductive layers formed such that a charge storage layer for storing charges is sandwiched between the first conductive layers and the first columnar semiconductor layer. Also, the non-volatile semiconductor memory device includes a second columnar semiconductor layer and a second conductive layer formed such that an insulating layer is sandwiched between the second conductive layer and the second columnar semiconductor layer, the second conductive layer being repeatedly provided in a line form by providing a certain interval in a first direction perpendicular to a laminating direction. A first sidewall conductive layer being in contact with the second conductive layer and extending in the first direction is formed on a sidewall along a longitudinal direction of the second conductive layer.07-16-2009
20130092999NONVOLATILE STORAGE DEVICE - A nonvolatile storage device includes a tunnel insulating film disposed on a surface of a semiconductor substrate and a charge trap layer disposed in contact with an upper surface of the tunnel insulating film. The charge trap layer includes a second charge trap film disposed in contact with the upper surface of the tunnel insulating film and a first charge trap film disposed in contact with an upper surface of the second charge trap film.04-18-2013
20110272757SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - To improve characteristics of a semiconductor device having a nonvolatile memory.11-10-2011
20110291180ANGLED ION IMPLANTATION IN A SEMICONDUCTOR DEVICE - Angled ion implants are utilized to form doped regions in a semiconductor pillar formed in an opening of a mask. The pillar is formed to a height less than the height of the mask. Angled ion implantation can be used to form regions of a semiconductor device such as a body tie region, a halo region, or current terminal extension region of a semiconductor device implemented with the semiconductor pillar.12-01-2011
20110309434NONVOLATILE MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A nonvolatile memory device and a manufacturing method thereof are provided. The manufacturing method includes the following steps. First, a substrate is provided. Then, a tunneling dielectric layer is formed on the substrate, and a dummy gate is form on the tunneling dielectric layer. Subsequently, an interlayer dielectric layer is formed around the dummy gate, and the dummy gate is removed to form an opening. Following that, a charge storage layer is formed on the inner side wall of the opening, and the charge storage layer covers the tunneling dielectric layer. Moreover, an inter-gate dielectric layer is formed on the charge storage layer, and a metal gate is formed on the inter-gate dielectric layer. Accordingly, a stacked gate structure of the nonvolatile memory device includes the tunneling dielectric layer, the charge storage layer, the inter-gate dielectric layer, and the metal gate.12-22-2011

Patent applications in class With additional, non-memory control electrode or channel portion (e.g., accessing field effect transistor structure)