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Multiple insulator layers (e.g., MNOS structure)

Subclass of:

257 - Active solid-state devices (e.g., transistors, solid-state diodes)

257213000 - FIELD EFFECT DEVICE

257288000 - Having insulated electrode (e.g., MOSFET, MOS diode)

257314000 - Variable threshold (e.g., floating gate memory device)

Patent class list (only not empty are listed)

Deeper subclasses:

Class / Patent application numberDescriptionNumber of patent applications / Date published
257326000 With additional, non-memory control electrode or channel portion (e.g., accessing field effect transistor structure) 123
257325000 Non-homogeneous composition insulator layer (e.g., graded composition layer or layer with inclusions) 62
Entries
DocumentTitleDate
20110175157NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a nonvolatile semiconductor memory device includes a semiconductor layer; first and second insulating layers; a functional layer; first and second gate electrodes. The first insulating layer opposes the semiconductor layer. The second insulating layer is provided between the semiconductor layer and the first insulating layer. The functional layer is provided between the first and second insulating layers. The second gate electrode is separated from the first gate electrode. The first insulating layer is disposed between the first gate electrode and the semiconductor layer and between the second gate electrode and the semiconductor layer. The charge storabilities in first and second regions of the functional layer are different from that of a third region of the functional layer. The first and second regions oppose the first and second gate electrodes, respectively. The third region is between the first and the second regions.07-21-2011
20130043523NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a nonvolatile semiconductor memory device includes a plurality of gate electrode structures formed on a semiconductor substrate and an insulating film which covers the gate electrode structures and has an air gap in it. Each of the gate electrode structures includes a gate insulting film, a charge storage layer, an intermediary insulating film, and a control gate electrode. The control gate electrode includes a first control gate and a second control gate whose width is greater than that of the first control gate. The air gap is formed so as to be higher than a space between the control gate electrodes and than the control gate electrodes.02-21-2013
20130026558SEMICONDUCTOR DEVICES INCLUDING VARIABLE RESISTANCE MATERIAL AND METHODS OF FABRICATING THE SAME - The semiconductor device includes an insulating substrate, a channel layer over the insulating substrate, a gate at least partially extending from an upper surface of the channel layer into the channel layer, a source and a drain respectively at opposing sides of the gate on the channel layer, a gate insulating layer surrounding, the gate and electrically insulating the gate from the channel layer, the source, and the drain, and a variable resistance material layer between the insulating substrate and the gate.01-31-2013
20130026557SONOS NON-VOLATILE MEMORY CELL AND FABRICATING METHOD THEREOF - A method for fabricating a silicon-oxide-nitride-oxide-silicon (SONOS) non-volatile memory cell, wherein the method comprises steps as following: a pad oxide layer and a first hard mask layer are sequentially formed on a substrate. The pad oxide layer and the first hard mask layer are then etched through to form an opening exposing a portion of the substrate. Subsequently, an oxide-nitride-oxide (ONO) structure with a size substantially less than or equal to the opening is formed to coincide with the portion of the substrate exposed from the opening.01-31-2013
20090206389NONVOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A nonvolatile memory device which contributes to improvement of electrical erase characteristics and a method of manufacturing the same are provided. The nonvolatile memory device includes a semiconductor substrate, a gate electrode formed on the semiconductor substrate, a diffusing layer electrode formed adjacent to the gate electrode on the semiconductor substrate; a charge accumulating layer formed on a lateral side of the gate electrode and retaining injected electrons, and an LDD region formed below the diffusing layer electrode. The charge accumulating layer is formed on only the lateral side of the gate electrode and does not extend along the LDD region.08-20-2009
20110180865CHARGE STORAGE NODES WITH CONDUCTIVE NANODOTS - Memory cells formed to include a charge storage node having conductive nanodots over a charge storage material are useful in non-volatile memory devices and electronic systems.07-28-2011
20090309154SELECTION TRANSISTOR - Provided are a selection transistor and a method of fabricating the same. A selection transistor can be formed on an active region in a semiconductor substrate to include a gate electrode that includes recessed portions of a sidewall of the gate electrode which are recessed inward adjacent lower portions of the gate electrode to define a T-shaped cross section of the gate electrode. A tunnel insulating layer can be located between the gate electrode and the active region.12-17-2009
20110204430NONVOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A nonvolatile memory device and a method of fabricating the same is provided to prevent charges stored in a charge trap layer from moving to neighboring memory cells. The method of fabricating a nonvolatile memory device, includes forming a first dielectric layer on a semiconductor substrate in which active regions are defined by isolation layers, forming a charge trap layer on the first dielectric layer, removing the first dielectric layer and the charge trap layer over the isolation layers, forming a second dielectric layer on the isolation layers including the charge trap layer, and forming a conductive layer on the second dielectric layer.08-25-2011
20100059810SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - The present invention can realize a highly-integrated semiconductor device having a MONOS type nonvolatile memory cell equipped with a split gate structure without deteriorating the reliability of the device. A memory gate electrode of a memory nMIS has a height greater by from 20 to 100 nm than that of a select gate electrode of a select nMIS so that the width of a sidewall formed over one (side surface on the side of a source region) of the side surfaces of the memory gate electrode is adjusted to a width necessary for achieving desired disturb characteristics. In addition, a gate electrode of a peripheral second nMIS has a height not greater than the height of a select gate electrode of a select nMIS to reduce the width of a sidewall formed over the side surface of the gate electrode of the peripheral second nMIS so that a shared contact hole is prevented from being filled with the sidewall.03-11-2010
20090194808SEMICONDUCTOR DEVICE - A semiconductor device includes an element region having a channel region, and a unit gate structure inducing a channel in the channel region, the unit gate structure including a tunnel insulating film formed on the element region, a charge storage insulating film formed on the tunnel insulating film, a block insulating film formed on the charge storage insulating film, and a control gate electrode formed on the block insulating film, wherein a distance between the element region and the control gate electrode is shorter at a center portion of the unit gate structure than at both ends thereof, as viewed in a section parallel to a channel width direction.08-06-2009
20090194807SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor memory device includes: a semiconductor substrate; an element isolation trench formed on the semiconductor substrate so as to surround an element region in which a memory element is to be formed; a first gate insulating film formed on the element region of the semiconductor substrate; a charge storing layer formed on the first gate insulating film; a second gate insulating film formed on the charge storing layer; a control electrode formed on the second gate insulating film; an impurity diffusion layer formed in a surface layer of the semiconductor substrate along a channel direction of the charge storing layer; a sidewall oxide film formed on a side surface of the element isolation trench; and an element isolation insulating film formed so as to fill the element isolation trench together with the element isolation insulation film; wherein the top surface of the sidewall oxide film is flush with or above the top surface of the first gate insulating film.08-06-2009
20100052040METHOD FOR FORMING SILICON NITRIDE FILM, METHOD FOR MANUFACTURING NONVOLATILE SEMICONDUCTOR MEMORY DEVICE, NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND PLASMA APPARATUS - A Plasma processing apparatus (03-04-2010
20120168852NONVOLATILE MEMORY DEVICES - A nonvolatile memory device includes a string selection transistor, a plurality of memory cell transistors, and a ground selection transistor electrically connected in series to the string selection transistor and to the pluralities of memory cell transistors. First impurity layers are formed at boundaries of the channels and the source/drain regions of the memory cell transistors. The first impurity layers are doped with opposite conductivity type impurities relative to the source/drain regions of the memory cell transistors. Second impurity layers are formed at boundaries between a channel and a drain region of the string selection transistor and between a channel and a source region of the ground selection transistor. The second impurity layers are doped with the same conductivity type impurities as the first impurity layers and have a higher impurity concentration than the first impurity layers.07-05-2012
20110284947NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.11-24-2011
20080258205NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - An erase current of a non-volatile semiconductor memory device is decreased. A memory cell of the non-volatile semiconductor memory device comprises a source region and a drain region formed in a semiconductor substrate. Over a portion of the semiconductor substrate between the source region and the drain region, a select gate electrode is formed via a gate dielectric film. On a side wall of the select gate electrode, a memory gate electrode is formed via a bottom silicon oxide film and a charge-trapping silicon oxynitride film. In the memory cell configured as above, erase operation is performed as follows. By applying a positive voltage to the memory gate electrode, holes are injected from the memory gate electrode into the silicon oxynitride film to decrease a threshold voltage in a program state to a certain level. Thereafter, hot holes generated by a band-to-band tunneling phenomenon are injected into the silicon oxynitride film and the erase operation is completed.10-23-2008
20080258204MEMORY STRUCTURE AND OPERATING METHOD THEREOF - A memory structure including a substrate, a charge trapping layer, a block layer, a conducting layer and two doped regions is provided in the present invention. The charge trapping layer is disposed on the substrate. The block layer is disposed on the charge trapping layer. The conducting layer is disposed on the block layer. The doped regions are disposed respectively in the substrate on the two sides of the conducting layer.10-23-2008
20080258203STACKED SONOS MEMORY - An integrated circuit includes a first SONOS memory cell and a second SONOS memory cell. The second memory cell is stacked on the first memory cell.10-23-2008
20110193155SEMICONDUCTOR MEMORY DEVICE INCLUDING A STACKED GATE HAVING A CHARGE STORAGE LAYER AND A CONTROL GATE, AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory device includes a source region, a drain region, a channel region, a charge storage layer, and a control gate electrode. The source region and drain region are formed separately from each other in a surface of a semiconductor substrate. The channel region is formed in the semiconductor substrate and located between the source region and the drain region. The charge storage layer is formed on the channel region with a first insulating film interposed therebetween. The control gate electrode is formed on the charge storage layer with a second insulating film interposed therebetween. The control gate has an upper corner portion rounded with a radius of curvature of 5 nm or more.08-11-2011
20110193154Non-volatile Memory Device - A non-volatile memory device includes a substrate, a tunneling layer over the substrate, a charge trapping layer including a nitride layer and a silicon boron nitride layer over the tunneling layer, and a blocking layer over the charge trapping layer, and a control gate electrode arranged on the blocking layer.08-11-2011
20110193153NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a nonvolatile semiconductor memory device includes a stacked body, a semiconductor pillar and a charge storage layer. The stacked body includes a plurality of insulating films alternately stacked with a plurality of electrode films. The semiconductor pillar is buried in the stacked body, and extends in a stacking direction of the insulating films and the electrode films. The charge storage layer is provided between the electrode films and the semiconductor pillar. The electrode films are divided into a plurality of control gate electrodes. Each of the plurality of control gate electrodes faces the semiconductor pillar and sandwiches the charge storage layer with the semiconductor pillar.08-11-2011
20100001335Flash Memory Cells Having Leakage-Inhibition Layers - A semiconductor device includes a semiconductor substrate; a tunneling layer over the semiconductor substrate, wherein the tunneling layer has a first conduction band; a storage layer over the tunneling layer, wherein the storage layer has a second conduction band; a blocking layer over the storage layer, wherein the blocking layer has a third conduction band; a gate electrode over the blocking layer; and at least one of a first leakage-inhibition layer and a second leakage-inhibition layer. The first leakage-inhibition layer is between the tunneling layer and the storage layer, and has a fourth conduction band lower than the first conduction band. The second leakage-inhibition layer is between the blocking layer and the gate electrode, and has a fifth conduction band lower than the third conduction band.01-07-2010
20100117138NONVOLATILE MEMORY CELL COMPRISING A NONWIRE AND MANUFACTURING METHOD THEREOF - A memory cell (05-13-2010
20100117137NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - Each of memory strings is provided with a first semiconductor layer having a pair of columnar portions extending in a perpendicular direction with respect to a substrate; a charge storage layer formed to surround a side surface of the columnar portions; and a first conductive layer formed to surround the charge storage layer. Each of the select transistors is provided with a second semiconductor layer extending upwardly from an upper surface of the columnar portions; a gate insulating layer formed to surround a side surface of the second semiconductor layer; and a second conductive layer formed to surround the gate insulating layer. An effective impurity concentration of the second semiconductor layer is less than or equal to an effective impurity concentration of the first semiconductor layer.05-13-2010
20100072536Non-volatile memory device and method of manufacturing the same - In a non-volatile memory device and a method of manufacturing the non-volatile memory device, a tunnel insulating layer, a charge trapping layer, a dielectric layer and a conductive layer may be sequentially formed on a channel region of a substrate. The conductive layer may be patterned to form a gate electrode and spacers may be formed on sidewalls of the gate electrode. A dielectric layer pattern, a charge trapping layer pattern, and a tunnel insulating layer pattern may be formed on the channel region by an anisotropic etching process using the spacers as an etch mask. Sidewalls of the charge trapping layer pattern may be removed by an isotropic etching process to reduce the width thereof. Thus, the likelihood of lateral diffusion of electrons may be reduced or prevented in the charge trapping layer pattern and high temperature stress characteristics of the non-volatile memory device may be improved.03-25-2010
20100072535NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device includes a source region and a drain region provided apart from each other in a semiconductor substrate, a first insulating film provided on a channel region between the source region and the drain region, a charge storage layer provided on the first insulating film, a second insulating film provided on the charge storage layer and including a stacked structure of a lanthanum aluminum silicate film and a dielectric film made of silicon oxide or silicon oxynitride, and a control gate electrode provided on the second insulating film.03-25-2010
20130075806MULTI-GATE BANDGAP ENGINEERED MEMORY - Memory cells comprising: a semiconductor substrate having a source region and a drain region disposed below a surface of the substrate and separated by a channel region; a tunnel dielectric structure disposed above the channel region, the tunnel dielectric structure comprising at least one layer having a hole-tunneling barrier height; a charge storage layer disposed above the tunnel dielectric structure; an insulating layer disposed above the charge storage layer; and a gate electrode disposed above the insulating layer are described along with arrays and methods of operation.03-28-2013
20130032874METHOD FOR MANUFACTURING NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a method is disclosed for manufacturing a nonvolatile semiconductor memory device. The device includes a plurality of electrode films stacked along a first axis perpendicular to a major surface of a substrate, a plurality of semiconductor layers penetrating through the electrode films, and a memory film provided between the electrode films and the semiconductor layer. The method can include forming a first stacked body by alternately stacking a plurality of first films and second films. The method can include forming a support unit supporting the first films. The method can include forming a first hole and removing the second films via the first hole to form a second stacked body. The method can include forming a plurality of through holes penetrating through the first films. In addition, the method can include burying the memory film and the semiconductor layers in the through holes.02-07-2013
20130032875SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - One example embodiment of a semiconductor device includes a memory cell array formed on a substrate. The memory cell array includes a gate stack including alternating conductive and insulating layers. A first lower conductive layer in the gate stack has a portion disposed below a first upper conductive layer in the gate stack, and a first contact area of the first lower conductive layer is disposed higher than a second contact area of the first upper conductive layer. The semiconductor device further includes first and second contact plugs extending into the gate stack to contact the first and second contact areas, respectively.02-07-2013
20130032873SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor memory device includes a stacked body, a semiconductor pillar, and a plurality of memory cells. The stacked body includes a plurality of stacked gate electrodes and inter-electrode insulating layers provided between the gate electrodes. The semiconductor pillar punches through the stacked body. The plurality of memory cells is provided in stacking direction. The memory cell includes a charge trap layer provided between the semiconductor pillar and the gate electrode via an air gap. The block insulating layer is provided between the charge trap layer and the gate electrode. Each of the plurality of memory cells is provided with a support portion configured to keep air gap distance between the charge trap layer and the semiconductor pillar.02-07-2013
20130075807SEMICONDUCTOR MEMORY DEVICES HAVING SELECTION TRANSISTORS WITH NONUNIFORM THRESHOLD VOLTAGE CHARACTERISTICS - Provided is a semiconductor memory device. In the semiconductor memory device, a lower selection gate controls a first channel region that is defined at a semiconductor substrate and a second channel region that is defined at the lower portion of an active pattern disposed on the semiconductor substrate. The first threshold voltage of the first channel region is different from the second threshold voltage of the second channel region.03-28-2013
20130075805METHOD FOR MANUFACTURING NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND NONVOLATILE SEMICONDUCTOR STORAGE DEVICE - According to one embodiment, a method for manufacturing a nonvolatile semiconductor storage device includes; forming a first and a second stacked bodies; forming a through hole penetrating through the first stacked body, a second portion communicating with the first portion and penetrating through a select gate, and a third portion communicating with the second portion and penetrating through a second insulating layer; forming a memory film, a gate insulating film, and a channel body; forming a third insulating layer inside the channel body; forming a first embedded portion above a boundary portion inside the third portion; exposing the channel body by removing part of the first embedded portion and part of the third insulating layer in the third portion; and embedding a second embedded portion including silicon having higher impurity concentration than the first embedded portion above the first embedded portion inside the third portion.03-28-2013
20090121281SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device has an element isolation region between rewrite units of memory cells. A plurality of memory cells are memory cell groups arranged in a row direction, and each memory cell group consists of (8×N) memory cells arranged in a row direction as a unit to be used as a storage region. The number of a plurality of selection word lines is at least eight, and the number of selection transistors corresponding to at least N is connected to each of the plurality of selection word lines. At least one selection transistor in addition to (8×N) selection transistors are connected in total to the plurality of selection word lines. A plurality of main bit lines includes at least one main bit line in addition to (4×N) main bit lines connected to the common drain of a pair of selection transistors.05-14-2009
20090121280SEMICONDUCTOR DEVICES, METHODS OF FORMING THE SEMICONDUCTOR DEVICES AND METHODS OF OPERATING THE SEMICONDUCTOR DEVICES - Described are a semiconductor device, methods of forming the semiconductor device and methods of operating the semiconductor device. The semiconductor device includes a gate electrode and laminated charge trap layers interposed between substrates. The methods of forming the semiconductor device include forming a gate stacked structure including insulating layers having a different etching selectivity, forming spaces on sidewalls of the gate stacked structure using an etching selectivity and forming charge trap layers in the spaces. The methods of operating the semiconductor device include programming trap layers by controlling a voltage applied to a gate electrode.05-14-2009
20100044775SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR DEVICE - Provided is a semiconductor memory device that can retain information by trapping electric charges into a trap level in a gate insulating film. The information retention capacity is improved by restricting lateral diffusion of electric charges. The semiconductor memory device is provided with a semiconductor substrate (02-25-2010
20100044776NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - A multilayer body is formed by alternately stacking electrode films serving as control gates and dielectric films in a direction orthogonal to an upper surface of a silicon substrate. Trenches extending in the word line direction are formed in the multilayer body and a memory film is formed on an inner surface of the trench. Subsequently, a silicon body is buried inside the trench, and a charge storage film and the silicon body are divided in the word line direction to form silicon pillars. This simplifies the configuration of memory cells in the bit line direction, and hence can shorten the arrangement pitch of the silicon pillars, decreasing the area per memory cell.02-25-2010
20100096687NON-VOLATILE MEMORY HAVING SILICON NITRIDE CHARGE TRAP LAYER - A flash memory device and methods of forming a flash memory device are provided. The flash memory device includes a doped silicon nitride layer having a dopant comprising carbon, boron or oxygen. The doped silicon nitride layer generates a higher number and higher concentration of nitrogen and silicon dangling bonds in the layer and provides an increase in charge holding capacity and charge retention time of the unit cell of a non-volatile memory device.04-22-2010
20090159961SEMICONDUCTOR MEMORY DEVICE WITH STACKED GATE INCLUDING CHARGE STORAGE LAYER AND CONTROL GATE AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory device includes a first active region, a second active region, a first element isolating region and a second element isolating region. The first active region is formed in a semiconductor substrate. The second active region is formed in the semiconductor substrate. The first element isolating region electrically separates the first active regions adjacent to each other. The second element isolating region electrically separates the second active regions adjacent to each other. An impurity concentration in a part of the second active region in contact with a side face of the second element isolating region is higher than that in the central part of the second active region, and a impurity concentration in a part of the first active region in contact with a side face of the first element isolating region is equal to that in the first active region.06-25-2009
20090159960Non-volatile memory device - A non-volatile memory device includes a memory cell region which is formed on a semiconductor substrate to store predetermined information, and a peripheral circuit region which is formed on the semiconductor substrate. The memory cell region includes a gate electrode; and a charge storage layer, the charge storage layer being formed to be a notch or wedge shape having an edge extending into both sides of a bottom end of the gate electrode. The peripheral circuit region includes no charge storage layer therein.06-25-2009
20090159959Nonvolatile semiconductor memory device and method of fabricating the same - A charge trap flash (CTF) memory cell and manufacturing method include a semiconductor substrate and an isolation region and an active region being formed in the substrate. A tunneling layer, a charge trapping layer and a blocking layer are formed on the isolation region and the active region. A resistance layer is formed on the blocking layer over the isolation region. The resistance layer prevents or substantially reduces trapping of electrons at the edges of the active region, i.e., the edge effect. As a result, after programming of the devices, the threshold voltages of the programmed cells are substantially uniform throughout the cells. This results in improved reliability of the devices.06-25-2009
20090159958ELECTRONIC DEVICE INCLUDING A SILICON NITRIDE LAYER AND A PROCESS OF FORMING THE SAME - An electronic device can include a silicon nitride layer. In an embodiment, the silicon nitride layer can include boron, grains, or both. The silicon nitride layer may be used as part of a charge storage layer within a nonvolatile memory cell within the electronic device. In a particular embodiment, the boron within the silicon nitride layer may be no greater than approximately 9 atomic % of the layer. The boron can be incorporated into the silicon nitride layer as it is being formed. The layer can be formed using chemical vapor deposition, physical vapor deposition, another suitable formation process, or any combination thereof.06-25-2009
20090159957NONVOLATILE MEMORIES WITH LATERALLY RECESSED CHARGE-TRAPPING DIELECTRIC - Charge-trapping dielectric (06-25-2009
20100109073FLASH MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A flash memory device includes a semiconductor substrate having a trench formed therein, the trench including a device isolation film, an oxide film formed over the semiconductor substrate including the trench, a nitride film pattern inserted into the oxide film and formed at a sidewall of the trench, and a polysilicon pattern formed over the oxide film including the nitride film pattern. A method for manufacturing a flash memory device includes forming a first oxide film over the semiconductor substrate including the trench, forming the nitride film pattern at the sidewall of the trench provided with the first oxide film and forming a second oxide film over the semiconductor substrate including the nitride film pattern, forming an oxide film pattern at a contact surface between the nitride film pattern and the semiconductor substrate and a side of the nitride film pattern by partially removing the first oxide film and the second oxide film formed over the bottom of the trench and the semiconductor substrate, and forming a third oxide film over the semiconductor substrate including the oxide film pattern to form the oxide cover film into which the nitride film pattern is inserted.05-06-2010
20100109070FABRICATING METHOD OF MIRROR BIT MEMORY DEVICE HAVING SPLIT ONO FILM WITH TOP OXIDE FILM FORMED BY OXIDATION PROCESS - A device and method employing a polyoxide-based charge trapping component. A charge trapping component is patterned by etching a layered stack that includes a tunneling layer positioned on a substrate, a charge trapping layer positioned on the tunneling layer, and an amorphous silicon layer positioned on the charge trapping layer. An oxidation process grows a gate oxide layer from the substrate and converts the amorphous silicon layer into a polyoxide layer.05-06-2010
20100109072NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - A nonvolatile semiconductor memory device includes a first stacked body on a silicon substrate, and a second stacked body is provided thereon. The first stacked body includes a plurality of insulating films alternately stacked with a plurality of electrode films, and a first portion of a through-hole extending in a stacking direction is formed. The second stacked body includes a plurality of insulating films alternately stacked with a plurality of electrode films, and a second portion of the through-hole is formed. A memory film is formed on an inner face of the through-hole, and a silicon pillar is buried in an interior of the through-hole. A central axis of the second portion of the through-hole is shifted from a central axis of the first portion, and a lower end of the second portion is positioned lower than an upper portion of the first portion.05-06-2010
20100006923SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a tunnel insulating film formed on a surface of a semiconductor region, a charge storage insulating film formed on a surface of the tunnel insulating film, a block insulating film formed on a surface of the charge storage insulating film, and a control gate electrode formed on a surface of the block insulating film, wherein the block insulating film includes a first insulating film containing a metal element and oxygen as main components, a second insulating film containing silicon and oxygen as main components, and an interface layer formed between the first insulating film and the second insulating film and containing the metal element, silicon, and oxygen as main components.01-14-2010
20130082318INTEGRATION OF eNVM, RMG, AND HKMG MODULES - A memory device is fabricated through the integration of embedded non-volatile memory (eNVM) with replacement metal gate (RMG) and high-k/metal gate (HKMG) modules. Embodiments include forming two substrate portions having upper surfaces at different heights, forming non-volatile gate stacks over the substrate portion with the lower upper surface, and forming high-voltage gate stacks and logic gate stacks over the other substrate portion. Embodiments include the upper surfaces of the non-voltage gate stacks, the high-voltage gate stacks, and the logic gate stacks being substantially coplanar.04-04-2013
20130082319MEMORY DEVICE - According to one embodiment, a memory device includes the following structure. A first double tunnel junction structure includes a first nanocrystal layer that includes first conductive minute particles, and first and second tunnel insulating films arranged to sandwich the first nanocrystal layer. A second double tunnel junction structure includes a second nanocrystal layer that includes second conductive minute particles, and third and fourth tunnel insulating films arranged to sandwich the second nanocrystal layer. A charge storage layer is arranged between the first and second double tunnel junction structures. First and second conductive layers are arranged to sandwich the first double tunnel junction structure, the charge storage layer, and the second double tunnel junction structure. The first conductive minute particles has an average grain size which is different from that of the second conductive minute particles.04-04-2013
20120211821SEMICONDUCTOR MEMORY DEVICE, METHOD FOR MANUFACTURING SAME, AND METHOD FOR MANUFACTURING INTEGRATED CIRCUIT DEVICE - According to one embodiment, a method for manufacturing a semiconductor memory device includes forming a first stacked body on a substrate by alternately stacking a first film and a second film, forming a second stacked body on the first stacked body by alternately stacking a third film and a fourth film, making a through-hole to pierce the second stacked body and the first stacked body by performing etching, an etching rate of the third film being lower than an etching rate of the first film in the etching, forming a charge storage film on an inner surface of the through-hole, and forming a semiconductor member in the through-hole. The first film and the second film are formed of mutually different materials. The third film and the fourth film are formed of mutually different materials. And, the first film and the third film are formed of mutually different materials.08-23-2012
20130087849METHOD OF FABRICATING A CHARGE TRAP NAND FLASH MEMORY DEVICE - Subject matter disclosed herein relates to a method of manufacturing a semiconductor integrated circuit device, and more particularly to a method of fabricating a charge trap NAND flash memory device.04-11-2013
20130087847Nonvolatile Memory Device - Patterns of a nonvolatile memory device include a semiconductor substrate that defines active regions extending in a longitudinal direction, an isolation structure formed between the active regions, a tunnel insulating layer formed on the active regions, a charge trap layer formed on the tunnel insulating layer, a first dielectric layer formed on the charge trap layer and the isolation structure, wherein the first dielectric layers is extended along a lateral direction, a control gate layer formed on the first dielectric layer, wherein the control gate layer is extended along the lateral direction, and a second dielectric layer formed on a sidewall of the control gate layer along the lateral direction and coupled to the first dielectric layer.04-11-2013
20130087846SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes word lines and interlayer insulating layers alternately stacked, a channel layer penetrating the word lines and the interlayer insulating layers, a tunnel insulating layer surrounding the channel layer, and first charge trap layers surrounding the tunnel insulating layer, interposed between the word lines and the tunnel insulating layer, respectively, and doped with first impurities.04-11-2013
20130087848Method of Forming a Nanocluster-Comprising Dielectric Layer and Device Comprising Such a Layer - A method of forming a dielectric layer on a further layer of a semiconductor device is disclosed. The method comprises depositing a dielectric precursor compound and a further precursor compound over the further layer, the dielectric precursor compound comprising a metal ion from the group consisting of Yttrium and the Lanthanide series elements, and the further precursor compound comprising a metal ion from the group consisting of group IV and group V metals; and chemically converting the dielectric precursor compound and the further precursor compound into a dielectric compound and a further compound respectively, the further compound self-assembling during said conversion into a plurality of nanocluster nuclei within the dielectric layer formed from the first dielectric precursor compound. The nanoclusters may be dielectric or metallic in nature. Consequently, a dielectric layer is formed that has excellent charge trapping capabilities.04-11-2013
20130087845NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a method of manufacturing a nonvolatile semiconductor memory device is provided. In the method, a conductive film serving as a control gate is formed above a substrate. A hole extending through the conductive film from its upper surface to its lower surface is formed. A block insulating film, a charge storage layer, a tunnel insulating film, and a semiconductor layer are formed on the inner surface of the hole. A film containing a material having an oxygen dissociation catalytic action is formed on the semiconductor layer not to fill the hole. The interface between the tunnel insulating film and the semiconductor layer is oxidized through the film from the inside of the hole.04-11-2013
20120181601METHODS FOR FORMING A MEMORY CELL HAVING A TOP OXIDE SPACER - Methods for fabricating a semiconductor memory cell that has a spacer layer are disclosed. A method includes forming a plurality of source/drain regions in a substrate where the plurality of source/drain regions are formed between trenches, forming a first oxide layer above the plurality of source/drain regions and in the trenches, forming a charge storage layer above the oxide layer and separating the charge storage layer in the trenches where a space is formed between separated portions of the charge storage layer. The method further includes forming a spacer layer to fill the space between the separated portions of the charge storage layer and to rise a predetermined distance above the space. A second oxide layer is formed above the charge storage layer and the spacer layer and a polysilicon layer is formed above the second oxide layer.07-19-2012
20120181600SONOS FLASH MEMORY DEVICE - A semiconductor device fabricated by forming a dummy layer on a semiconductor substrate, forming a groove in the semiconductor substrate while using the dummy layer as a mask, forming a tunnel insulating film and a trap layer to cover an inner surface of the groove and the dummy layer, eliminating the trap layer formed above the upper surface and at the sides of the dummy layer, and forming a top insulating film to cover a remaining trap layer and the exposed tunnel insulating film.07-19-2012
20120181599LOW COST SCALABLE 3D MEMORY - An integrated circuit device is described that includes a 3D memory comprising a plurality of self-aligned stacks of word lines orthogonal to and interleaved with a plurality of self-aligned stacks of bit lines. Data storage structures such as dielectric charge storage structures, are provided at cross points between word lines and bit lines in the plurality of self-aligned stacks of word lines interleaved with the plurality of self-aligned stacks of bit lines.07-19-2012
20090045455Nonvolatile memory device and method of fabricating the same - Example embodiments relate to nonvolatile semiconductor memory devices using an electric charge storing layer as a storage node and fabrication methods thereof. An electric charge trap type nonvolatile memory device may include a tunneling film, an electric charge storing layer, a blocking insulation film, and a gate electrode. The blocking insulation film may be an aluminum oxide having an energy band gap larger than that of a γ-phase aluminum oxide film. An α-phase crystalline aluminum oxide film as a blocking insulation film may have an energy band gap of about 7.0 eV or more along with fewer defects. The crystalline aluminum oxide film may be formed by providing a source film (e.g., AlF02-19-2009
20090045454Semiconductor non-volatile memory cell, method of producing the same, semiconductor non-volatile memory having the semiconductor non-volatile memory cell, and method of producing the same - A semiconductor non-volatile memory cell includes an Si (silicon) layer containing substrate including an activation region having a ridge portion; an element separation region embedded in both sides of the activation region; a gate electrode with a gate insulation film inbetween formed over the ridge portion for covering a part of both side surfaces of the ridge portion and an upper surface of the element separation region; a channel forming region formed in a surface layer region of the ridge portion; an extension region formed on both sides of the channel forming region in the longitudinal direction; and an electric charge accumulation layer capable of accumulating electric charges and a sidewall formed on the extension region and one or both of side surfaces of the gate electrode facing with each other in the longitudinal direction.02-19-2009
20130049099Semiconductor Device - A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.02-28-2013
20130049096METHODS AND APPARATUSES INCLUDING STRINGS OF MEMORY CELLS FORMED ALONG LEVELS OF SEMICONDUCTOR MATERIAL - Various embodiments include methods and apparatuses including strings of memory cells formed along levels of semiconductor material. One such apparatus includes a stack comprised of a number of levels of single crystal silicon and a number of levels of dielectric material. Each of the levels of silicon is separated from an adjacent level of silicon by a level of the dielectric material. Strings of memory cells are formed along the levels of silicon. Additional apparatuses and methods are disclosed.02-28-2013
20100001337Semiconductor memory device - A semiconductor memory device includes: sequentially stacked first and second semiconductor layers; at least one first memory transistor disposed on the first semiconductor layer; and at least one second memory transistor disposed on the second semiconductor layer, wherein a gate electrode of the first memory transistor has a broader width than that of the second memory transistor.01-07-2010
20100001336SONOS-NAND DEVICE HAVING A STORAGE REGION SEPARATED BETWEEN CELLS - The present invention is a semiconductor device including a semiconductor substrate having a trench, a first insulating film provided on side surfaces of the trench, a second insulating film of a material different from the first insulating film provided to be embedded in the trench, a word line provided extending to intersect with the trench above the semiconductor substrate, a gate insulating film of a material different from the first insulating film separated in an extending direction of the word line by the trench and provided under a central area in a width direction of the word line, and a charge storage layer separated in the extending direction of the word line by the trench and provided under both ends in the width direction of the word line to enclose the gate insulating film, and a method for manufacturing the same.01-07-2010
20100133604Semiconductor Devices Having Gate Structures with Conductive Patterns of Different Widths and Methods of Fabricating Such Devices - A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a first dielectric pattern, a data storage pattern and a second dielectric pattern, which are sequentially stacked on a semiconductor substrate. A first conductive pattern is provided on the second dielectric pattern. A second conductive pattern having a greater width than the first conductive pattern is provided on the first conductive pattern.06-03-2010
20100133605SELF ALIGNED NARROW STORAGE ELEMENTS FOR ADVANCED MEMORY DEVICE - A method of forming a sub-lithographic charge storage element on a semiconductor substrate is provided. The method can involve providing first and second layers on a semiconductor substrate, a thickness of the first layer being larger than a thickness of the second layer; forming a spacer adjacent a side surface of the first layer and on a portion of an upper surface of the second layer; and removing an exposed portion of the second layer that is not covered by the spacer. By removing the exposed portion of the second layer while leaving a portion of the second layer that is protected by the spacer, the method can make a sub-lithographic charge storage element from the remaining portion of the second layer on the semiconductor substrate.06-03-2010
20090302370METHOD AND APPARATUS FOR FLATBAND VOLTAGE TUNING OF HIGH-K FIELD EFFECT TRANSISTORS - In one embodiment, the invention is a method and apparatus for flatband voltage tuning of high-k field effect transistors. One embodiment of a field effect transistor includes a substrate, a high-k dielectric layer deposited on the substrate, a gate electrode deposited on the high-k dielectric layer, and a dipole layer positioned between the substrate and the gate electrode, for shifting the threshold voltage of the field effect transistor.12-10-2009
20090302369METHOD AND APPARATUS FOR FLATBAND VOLTAGE TUNING OF HIGH-K FIELD EFFECT TRANSISTORS - In one embodiment, the invention is a method and apparatus for flatband voltage tuning of high-k field effect transistors. One embodiment of a field effect transistor includes a substrate, a high-k dielectric layer deposited on the substrate, a gate electrode deposited on the high-k dielectric layer, and a dipole layer positioned between the substrate and the gate electrode, for shifting the threshold voltage of the field effect transistor.12-10-2009
20120217572Flash Memory Device With an Array of Gate Columns Penetrating Through a Cell Stack - A flash memory device includes a substrate; a cell stack having a semiconductor layer for providing junction areas and channel areas and an interlayer isolation layer for insulating the semiconductor layer, wherein the semiconductor layer and the interlayer isolation layer are repeatedly stacked; an array of gate columns, the gate columns penetrating through the cell stack, perpendicular to the substrate; and a trap layered stack introduced into an interface between the gate columns and the cell stack to store charge.08-30-2012
20120217570SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor memory device includes: a lower pillar protruding from a substrate in a vertical direction and extending in a first direction by a trench formed in the first direction; an upper pillar protruding on the lower pillar in a second direction perpendicular to the first direction; a buried bit line junction region disposed on one sidewall of the lower pillar; a buried bit line contacting the buried bit line junction region and filling a portion of the trench; an etch stop film disposed on an exposed surface of the buried bit line; a first interlayer dielectric film recessed to expose a portion of an outer side of at least the upper pillar disposed on the etch stop film; a second interlayer dielectric film disposed on the first interlayer dielectric film; and a gate surrounding the exposed outer side of the upper pillar and crossing the buried bit line.08-30-2012
20110006357NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING SAME - Provided are an architecture for a non-volatile memory device that can increase the write efficiency for split-gate trap memory, as well as increase resistance to disturbances; and a method of manufacturing said memory device. The device includes, at least: a layered film having traps, formed on top of the semiconductor substrate; a memory gate electrode formed on top of the layered film; a word gate electrode laid out so as to contact the memory gate electrode and the substrate through an insulating film; and source and drain regions in the substrate, sandwiching the two gate electrodes. The equivalent oxide thickness of the insulating film sandwiched between the word gate electrode and the substrate is made greater where the layered film is in contact than where there is no contact.01-13-2011
20130069141VERTICALLY FOLDABLE MEMORY ARRAY STRUCTURE - A vertically foldable memory array structure is provided, comprising: a memory module distributed in columns and rows, comprising: a drain selection transistor; a bottom connecting line and a source selection transistor; and a plurality of memory cell transistors connected between the drain selection transistor and the bottom connecting line and between the source selection transistor and the bottom connecting line, a drain of each drain selection transistor is connected to a bit line, a drain of a drain selection transistor in a M03-21-2013
20130069140METHOD FOR MANUFACTURING NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a method is disclosed for manufacturing a nonvolatile semiconductor memory device. The method can includes forming a semiconductor layer containing an impurity and forming a pattern on the semiconductor layer. The method can include forming first insulating layers in a stripe shape from a surface of the semiconductor layer toward an inside and forming a first insulating film on the semiconductor layer and on the first insulating layers to form a stacked body including electrode layers on the first insulating film. The method can include forming a pair of holes in the stacked body and forming a space portion connected to a lower end of the holes. The method can include forming a memory film on a side wall of the holes. In addition, the method can include forming a channel body layer on a surface of the memory film.03-21-2013
20130069139NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a nonvolatile semiconductor memory device includes a substrate, an electrode layer provided above the substrate, a first insulating layer provided on the electrode layer, a stacked body provided on the insulating layer, a memory film, a channel body layer, a channel body connecting portion and a second insulating layer. The stacked body has a plurality of conductive layers and a plurality of insulating film alternately stacked on each other. The memory film is provided on a sidewall of each of a pair of holes penetrating the stacked body in a direction of stacking the stacked body. The channel body layer is provided on an inner side of the memory film in each of the pair of the holes.03-21-2013
20130056819NONVOLATILE SEMICONDUCTOR MEMORY - According to one embodiment, a nonvolatile semiconductor memory includes a semiconductor layer, a first insulating layer on the semiconductor layer, a charge storage layer on the first insulating layer, a second insulating layer on the charge storage layer, and a control gate electrode on the second insulating layer. The second insulating layer comprises a stacked structure provided in order of a first lanthanum aluminate layer, a lanthanum aluminum silicate layer and a second lanthanum aluminate layer from the charge storage layer side to the control gate electrode side.03-07-2013
20130056818NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR MANUFACTURING SAME - A nonvolatile semiconductor storage device includes: a structural body; semiconductor layers; a memory film; a connecting member; and a conductive member. The structural body is provided above a memory region of a substrate including the memory region and a non-memory region, and includes electrode films stacked along a first axis perpendicular to a major surface of the substrate. The semiconductor layers penetrate through the structural body along the first axis. The memory film is provided between the electrode films and the semiconductor layer. The connecting member is provided between the substrate and the structural body and connected to respective end portions of two adjacent ones of the semiconductor layers. The conductive member is provided between the substrate and the connecting member, extends from the memory region to the non-memory region, includes a recess provided above the non-memory region, and includes a first silicide portion provided in the recess.03-07-2013
20120112265NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - A non-volatile semiconductor device includes an n type well formed in a semiconductor substrate having a surface, the surface having a plurality of stripe shaped grooves and a plurality of stripe shaped ribs, a plurality of stripe shaped p type diffusion regions formed in upper parts of each of the plurality of ribs, the plurality of stripe shaped p type diffusion regions being parallel to a longitudinal direction of the ribs, a tunneling insulation film formed on the grooves and the ribs, a charge storage layer formed on the tunneling insulating film, a gate insulation film formed on the charge storage layer, and a plurality of stripe shaped conductors formed on the gate insulating film, the plurality of stripe shaped conductors arranged in a direction intersecting the longitudinal direction of the ribs with a predetermined interval wherein an impurity diffusion structure in the ribs are asymmetric.05-10-2012
20120112264THREE-DIMENSIONAL SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - A three-dimensional semiconductor device includes an upper structure on a lower structure, the upper structure including conductive patterns, a semiconductor pattern connected to the lower structure through the upper structure, and an insulating spacer between the semiconductor pattern and the upper structure, a bottom surface of the insulating spacer being positioned at a vertical level equivalent to or higher than an uppermost surface of the lower structure.05-10-2012
20130056820THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A three-dimensional semiconductor device and a method of fabricating the same, the device including a lower insulating layer on a top surface of a substrate; an electrode structure sequentially stacked on the lower insulating layer, the electrode structure including conductive patterns; a semiconductor pattern penetrating the electrode structure and the lower insulating layer and being connected to the substrate; and a vertical insulating layer interposed between the semiconductor pattern and the electrode structure, the vertical insulating layer crossing the conductive patterns in a vertical direction and being in contact with a top surface of the lower insulating layer.03-07-2013
20090294831Semiconductor Constructions, Methods Of Forming Transistor Gates, And Methods Of Forming NAND Cell Units - Some embodiments include methods of forming charge storage transistor gates and standard FET gates in which common processing is utilized for fabrication of at least some portions of the different types of gates. FET and charge storage transistor gate stacks may be formed. The gate stacks may each include a gate material, an insulative material, and a sacrificial material. The sacrificial material is removed from the FET and charge storage transistor gate stacks. The insulative material of the FET gate stacks is etched through. A conductive material is formed over the FET gate stacks and over the charge storage transistor gate stacks. The conductive material physically contacts the gate material of the FET gate stacks, and is separated from the gate material of the charge storage transistor gate stacks by the insulative material remaining in the charge storage transistor gate stacks. Some embodiments include gate structures.12-03-2009
20090065849Semiconductor device and method for manufacturing the same - To improve a charge retention characteristic of a nonvolatile memory transistor. A first insulating film, a charge trapping film, and a second insulating film are formed between a semiconductor substrate and a conductive film. The charge trapping film is formed of a silicon nitride film including an upper region having a low concentration of hydrogen and a lower region having a high concentration of hydrogen. Such a silicon nitride film is formed in such a manner that a silicon nitride film including 15 atomic % or more hydrogen is formed by a chemical vapor deposition method and an upper portion of the silicon nitride film is nitrided. The nitridation treatment is performed by nitriding the silicon nitride film by nitrogen radicals produced in plasma of a nitrogen gas.03-12-2009
20090267136SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory device having a memory cell region and a peripheral circuit region, and a method of manufacturing such a semiconductor memory device, are proposed, in which trench grooves are formed to be shallow in the memory cell region in order to improve the yield, and trench grooves are formed to be deep in the high voltage transistor region of the peripheral circuit region, in particular in a high voltage transistor region thereof, in order to improve the element isolation withstand voltage. A plurality of memory cell transistors having an ONO layer 10-29-2009
20090267135NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - A non-volatile semiconductor storage device includes a first layer and a second layer. The first layer includes: a plurality of first conductive layers extending in parallel to a substrate and laminated in a direction perpendicular to the substrate; a first insulation layer formed on an upper layer of the plurality of first conductive layers; a first semiconductor layer formed to penetrate the plurality of first conductive layers; and a charge accumulation layer formed between the first conductive layers and the first semiconductor layer. Respective ends of the first conductive layers are formed in a stepwise manner in relation to each other in a first direction. The second layer includes: a plurality of second conductive layers extending in parallel to the substrate and laminated in a direction perpendicular to the substrate, the second conductive layers being formed in the same layer as the plurality of first conductive layers; and a second insulation layer formed on an upper layer of the plurality of second conductive layers. Respective ends of the second conductive layers are formed to align along a straight line extending in a direction substantially perpendicular to the substrate at a predetermined area.10-29-2009
20090267134NONVOLATILE SEMICONDUCTOR MEMORY APPARATUS - A nonvolatile semiconductor memory apparatus includes: a memory element including: a semiconductor substrate; a source region and a drain region formed at a distance from each other in the semiconductor substrate; a first insulating film formed on a portion of the semiconductor substrate located between the source region and the drain region, having sites that perform electron trapping and releasing and are formed by adding an element different from a base material, and including insulating layers having different dielectric constants, the sites having a higher level than a Fermi level of a material forming the semiconductor substrate; a charge storage film formed on the first insulating film; a second insulating film formed on the charge storage film; and a control gate electrode formed on the second insulating film.10-29-2009
20130062684GATE STACK STRUCTURE AND FABRICATING METHOD USED FOR SEMICONDUCTOR FLASH MEMORY DEVICE - The invention relates to a gate stack structure suitable for use in a semiconductor flash memory device and its fabricating method. The gate stack structure is fabricated on a p-type 100 silicon substrate, which also includes the following components in sequence from bottom to top: a charge tunnel layer of Al03-14-2013
20130062682SEMICONDUCTOR MEMORY AND MANUFACTURING METHOD THEREOF - According to one embodiment, a semiconductor memory includes a memory cell provided in a first active area surrounded with a first isolation insulating film, a first transistor provided in a second active area surrounded with a second isolation insulating film, a shield gate electrode on the second isolation insulating film. The bottom surface of the shield gate electrode is positioned more closely to a semiconductor substrate side as compared with the highest upper surface of the second isolation insulating film.03-14-2013
20130062681SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor memory device includes a stacked body, a semiconductor pillar, an insulating film, and a charge storage film. The stacked body includes a plurality of electrode films stacked with an inter-layer insulating film provided between the electrode films. The semiconductor pillar pierces the stacked body. The insulating film is provided between the semiconductor pillar and the electrode films on an outer side of the semiconductor pillar with a gap interposed. The charge storage film is provided between the insulating film and the electrode films. The semiconductor pillar includes germanium. An upper end portion of the semiconductor pillar is supported by an interconnect provided above the stacked body.03-14-2013
20130062683SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a method of manufacturing a semiconductor memory device is provided. In the method, a laminated body in which a first silicon layer, a first sacrificial layer, a second silicon layer, and a second sacrificial layer are laminated in turn is formed. A first insulating film is formed on the laminated body. A trench is formed in the laminated body and the first insulating film. A third sacrificial layer is formed into the trench. The third sacrificial layer is etched by wet etching to be retreated from a top surface of the third sacrificial layer, thereby etching end faces of the first sacrificial layer and the second sacrificial layer.03-14-2013
20110012191SELF-ALIGNED PATTERNING METHOD BY USING NON-CONFORMAL FILM AND ETCH BACK FOR FLASH MEMORY AND OTHER SEMICONDUCTUR APPLICATIONS - A method for fabricating a memory device with a self-aligned trap layer which is optimized for scaling is disclosed. In the present invention, a non-conformal oxide is deposited over the charge trapping layer to form a thick oxide on top of the core source/drain region and a pinch off and a void at the top of the STI trench. An etch is performed on the pinch-off oxide and the thin oxide on the trapping layer on the STI oxide. The trapping layer is then partially etched between the core cells. A dip-off of the oxide on the trapping layer is performed. And a top oxide is formed. The top oxide converts the remaining trap layer to oxide and thus isolate the trap layer.01-20-2011
20110012190SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate, a first insulating film formed on the semiconductor substrate, a charge storage layer formed on the first insulating film, a second insulating film formed on the charge storage layer, and a control electrode formed on the second insulating film, the second insulating film including a lower silicon nitride film, a lower silicon oxide film formed on the lower silicon nitride film, an intermediate insulating film formed on the lower silicon oxide film and containing a metal element, the intermediate insulating film having a relative dielectric constant of greater than 7, an upper silicon oxide film formed on the intermediate insulating film, and an upper silicon nitride film formed on the upper silicon oxide film.01-20-2011
20110012189SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device includes stacked-gate structures including a plurality of cell gate patterns and insulating patterns alternately stacked on a semiconductor substrate and extending in a first direction. Active patterns and gate dielectric patterns are disposed in the stacked-gate structures. The active patterns penetrate the stacked-gate structures and are spaced apart from each other in a second direction intersecting the first direction, and the gate dielectric patterns are interposed between the cell gate patterns and the active patterns and extend onto upper and lower surfaces of the cell gate patterns. The active patterns share the cell gate patterns in the stacked-gate structures.01-20-2011
20110012188SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes: a stacked body formed of a plurality of inter-layer insulating films and a plurality of electrode films alternately stacked and having a through-hole formed in the stacking direction; an electrode-side insulating film of a film thickness of 4 nm or more provided on an inner surface of the through-hole; a charge storage film provided on the electrode-side insulating film; a semiconductor-side insulating film of a film thickness of 4 nm or more provided on the charge storage film; and a semiconductor pillar buried in the through-hole.01-20-2011
20100123180NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A nonvolatile semiconductor memory device includes a semiconductor layer as a channel, a conductive layer which is formed on a surface of the semiconductor layer with a first insulating layer and a second insulating layer interposed therebetween and functions as a control gate electrode; and a plurality of first charge storage layers formed between the first insulating layer and the second insulating layer. The plurality of first charge storage layers are formed in isolation from one another along a surface of the first insulating layer. The first insulating layer is formed so as to protrude towards the semiconductor layer at a position where each of the first charge storage layers is formed.05-20-2010
20090242966Vertical-type semiconductor devices - In a vertical-type memory device and a method of manufacturing the vertical-type memory device, the vertical memory device includes an insulation layer pattern of a linear shape provided on a substrate, pillar-shaped single-crystalline semiconductor patterns provided on both sidewalls of the insulation layer pattern and transistors provided on a sidewall of each of the single-crystalline semiconductor patterns. The transistors are arranged in a vertical direction of the single-crystalline semiconductor pattern, and thus the memory device may be highly integrated.10-01-2009
20130161728FABRICATING METHOD OF MIRROR BIT MEMORY DEVICE HAVING SPLIT ONO FILM WITH TOP OXIDE FILM FORMED BY OXIDATION PROCESS - A device and method employing a polyoxide-based charge trapping component. A charge trapping component is patterned by etching a layered stack that includes a tunneling layer positioned on a substrate, a charge trapping layer positioned on the tunneling layer, and an amorphous silicon layer positioned on the charge trapping layer. An oxidation process grows a gate oxide layer from the substrate and converts the amorphous silicon layer into a polyoxide layer.06-27-2013
20130161727NON-VOLATILE MEMORY DEVICE HAVING STACKED STRUCTURE, AND MEMORY CARD AND ELECTRONIC SYSTEM INCLUDING THE SAME - Provided are a non-volatile memory devices having a stacked structure, and a memory card and a system including the same. A non-volatile memory device may include a substrate. A stacked NAND cell array may have at least one NAND set and each NAND set may include a plurality of NAND strings vertically stacked on the substrate. At least one signal line may be arranged on the substrate so as to be commonly coupled with the at least one NAND set.06-27-2013
201301617243-DIMENSIONAL NON-VOLATILE MEMORY DEVICE, MEMORY SYSTEM INCLUDING THE SAME, AND METHOD OF MANUFACTURING THE DEVICE - A 3-dimensional non-volatile memory device, a memory system including the same, and a method of manufacturing the same comprise vertical channel layers protruding from a substrate, a plurality of interlayer insulating layers and a plurality of conductive layers alternately formed along the vertical channel layers, a charge trap layer surrounding the vertical channel layers, the charge trap layer having a smaller thickness in a plurality of first regions, interposed between the plurality of conductive layers and the vertical channel layers, than in a plurality of second regions, interposed between the plurality of interlayer insulating layers and the vertical channel layers and a blocking insulating layer formed in each of the plurality of first regions, between the plurality of conductive layers and the charge trap layer.06-27-2013
20090236654NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to an aspect of the present invention, there is provided a nonvolatile semiconductor storage device including: a semiconductor substrate; a source region and a drain region that are formed in the semiconductor substrate so as to be separated from each other and so as to define a channel region therebetween; a tunnel insulating film that is formed on the channel region; an insulative charge storage film that is formed on the tunnel insulating film; a conductive charge storage film that is formed on the insulative charge storage film so as to be shorter than the insulative charge storage film in a channel direction; an interlayer insulating film that is formed on the conductive charge storage film; and a gate electrode that is formed on the interlayer insulating film.09-24-2009
20100140686FLASH MEMORY AND METHOD OF MANUFACTURING A FLASH MEMORY - A semiconductor memory which includes a semiconductor substrate, a plurality of memory cells, and a plurality of active regions disposed in the substrate between adjacent ones of the memory cells. At least two contact electrodes are disposed between adjacent ones of the memory cells and each being connected to one of the active regions, and a contact member is connected to one of the contact electrodes and extending over a gate electrode of a memory cell disposed adjacent to the one contact electrode. Faults can be detected in the memory cells due to particles located between the various insulator and electrode layers in the gate electrode structure, or between the substrate and the gate insulator of the memory cell.06-10-2010
20090008704SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a semiconductor substrate having a projection, an upper end portion of the projection being curved, a first element isolation insulating film formed on the substrate surface at the root of the projection, having an upper surface lower than an upper surface of the projection, a second element isolation insulating film formed in the projection, a gate insulating film formed on the projection, and including a charge storage layer, and a gate electrode formed on the gate insulating film. A height of a first portion where the gate electrode is in contact with the gate insulating film above the upper surface of the first element isolation insulating film is smaller than that of a second portion where the gate electrode is in contact with the gate insulating film above an upper end of the second element isolation insulating film.01-08-2009
20090008703NON-VOLATILE MEMORY CELL AND FABRICATING METHOD THEREOF - A super-silicon-rich oxide (SSRO) non-volatile memory cell includes a gate conductive layer on a substrate, a source/drain in the substrate at respective sides of the gate conductive layer, a tunneling dielectric layer between the gate conductive layer and the substrate, a SSRO layer serving as a charge trapping layer between the gate conductive layer and the tunneling dielectric layer, and an upper-dielectric layer between the gate conductive layer and the SSRO layer.01-08-2009
20090008702DIELECTRIC CHARGE-TRAPPING MATERIALS HAVING DOPED METAL SITES - Dielectric materials having implanted metal sites and methods of their fabrication have been described. Such materials are suitable for use as charge-trapping nodes of non-volatile memory cells for memory devices. By incorporating metal sites into dielectric charge-trapping materials using an ammonia plasma and a metal source in contact with the plasma, improved programming and erase voltages may be facilitated.01-08-2009
20090008701NONVOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A nonvolatile memory device includes a semiconductor substrate, a charge trap layer formed on the semiconductor substrate, a blocking layer formed on the charge trap layer, and a gate electrode formed on the blocking layer. Sides of blocking layer extend laterally beyond sides of the charge trap layer and lateral sides of the gate electrode.01-08-2009
20120235224Circuit and Method for a Three Dimensional Non-Volatile Memory - An architecture, circuit and method for providing a very dense, producible, non volatile FLASH memory with SONOS cells. SONOS memory cells are formed using a uniformly doped channel region. A FinFET embodiment cell is disclosed. Because the novel SONOS cells do not rely on diffused regions, the cells may be formed into a three dimensional array of cells without diffusion problems. FLASH memory arrays are formed by forming layers of NAND Flash cells in the local interconnect layers of an integrated circuit, with the metal layers forming the global bit line conductors. The three dimensional non-volatile arrays formed of the SONOS cells rely on conventional semiconductor processing. P-channel and n-channel devices may be used to form the SONOS non-volatile cells.09-20-2012
20120235223NONVOLATILE SEMICONDUCTOR MEMORY - According to one embodiment, a nonvolatile semiconductor memory including a first gate insulating film formed on a channel region of a semiconductor substrate, a first particle layer formed in the first gate insulating film, a charge storage part formed on the first gate insulating film, a second gate insulating film which is formed on the charge storage part, a second particle layer formed in the second gate insulating film, and a gate electrode formed on the second gate insulating film. The first particle layer includes first conductive particles that satisfy Coulomb blockade conditions. The second particle layer includes second conductive particles that satisfy Coulomb blockade conditions and differs from the first conductive particles in average particle diameter.09-20-2012
20120235222NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A device isolation film has a first height in a first area and a second height higher than the first height in a second area. The first area includes a first end of a dummy memory transistor facing a memory string and a part of a device isolation film adjacent thereof. The second area includes a second end of the dummy memory transistor facing a select transistor and a part of the device isolation film adjacent thereof.09-20-2012
20120235221SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor device includes a substrate, a first stacked body, a memory film, a first channel body, a second stacked body, a gate insulating film and a second channel body. A step part is formed between a side face of the select gate and the second insulating layer. A film thickness of a portion covering the step part of the second channel body is thicker than a film thickness of a portion provided between the second insulating layers of the second channel body.09-20-2012
20120235220SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a substrate, a stacked body, a first insulating film, a charge storage film, a second insulating film and a channel body. The stacked body includes a plurality of electrode layers and insulating layers which are alternately stacked above the substrate. The first insulating film is provided on a side wall of a hole which is formed through the stacked body. The charge storage film is provided on an inner side of the first insulating film. The charge storage film includes a protrusion part which protrudes toward the electrode layer with facing the electrode layer and has a film thickness thicker than a film thickness of a part other than the protrusion part. The second insulating film is provided on an inner side of the charge storage film. The channel body is provided on an inner side of the second insulating film.09-20-2012
20120267703Information Storage Medium Using Nanocrystal Particles, Method of Manufacturing the Information Storage Apparatus Including the Information Storage Medium - Provided is an information storage medium using nanocrystal particles, a method of manufacturing the information storage medium, and an information storage apparatus including the information storage medium. The information storage medium includes a conductive layer, a first insulating layer formed on the conductive layer, a nanocrystal layer that is formed on the first insulating layer and includes conductive nanocrystal particles that can trap charges, and a second insulating layer formed on the nanocrystal layer.10-25-2012
20100176442STRUCTURES CONTAINING TITANIUM SILICON OXIDE - A dielectric containing a titanium silicon oxide film disposed in an integrated circuit and a method of fabricating such a dielectric provide a dielectric for use in a variety of electronic devices. Embodiments include a dielectric containing a titanium silicon oxide film arranged as one or more monolayers. Embodiments include structures for capacitors, transistors, memory devices, and electronic systems with dielectrics containing a titanium silicon oxide film, and methods for forming such structures.07-15-2010
20110024825SEMICONDUCTOR MEMORY - A semiconductor memory according to an example of the invention includes active areas, and element isolation areas which isolate the active areas. The active areas and the element isolation areas are arranged alternately in a first direction. An n-th (n is odd number) active area from an endmost portion in the first direction and an (n+1)-th active area are coupled to each other at an endmost portion in a second direction perpendicular to the first direction.02-03-2011
20120168848NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A non-volatile memory device includes a channel structure extended in a first direction that includes a plurality of inter-layer dielectric layers and a plurality of channel layers alternately stacked over a substrate such that each inter-layer dielectric layer is adjacent to a corresponding one of the plurality of channel layers. A word line extends in a second direction crossing the first direction over the channel structure, and a gate electrode protrudes from the word line in a downward direction to contact a sidewall of the channel structure. A memory gate insulation layer is interposed between the gate electrode and the channel structure, where sidewalls of the channel layers contacting the gate electrode are protruded toward the gate electrode, compared with sidewalls of the inter-layer dielectric layers.07-05-2012
20120299084SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - To improve the electric performance and reliability of a semiconductor device. A memory gate electrode of a split gate type nonvolatile memory is a metal gate electrode formed from a stacked film of a metal film 11-29-2012
20110278660ORO AND ORPRO WITH BIT LINE TRENCH TO SUPPRESS TRANSPORT PROGRAM DISTURB - Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line openings containing a bit line dielectric between the memory cells. The memory cell contains a charge storage layer and a first poly gate. The bit line opening extends into the semiconductor substrate. By containing the bit line dielectric in the bit line openings that extend into the semiconductor substrate, the memory device can improve the electrical isolation between memory cells, thereby preventing and/or mitigating TPD.11-17-2011
20080251837SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device which includes both an E-FET and a D-FET and can facilitate control of the Vth in an E-FET and suppress a decrease in the Vf, and a manufacturing method of the same are provided. A semiconductor device which includes both an E-FET and a D-FET on the same semiconductor substrate includes: a first threshold adjustment layer for adjusting threshold of the E-FET; a first etching stopper layer formed on the first threshold adjustment layer; the second threshold adjustment layer formed on the first etching stopper layer for adjusting threshold of the D-FET; a second etching stopper layer formed on the second threshold adjustment layer; a first gate electrode penetrating through the first etching stopper layer, the second threshold adjustment layer, and the second etching stopper layer, which is in contact with the first threshold adjustment layer; and the second gate electrode penetrating through the second etching stopper layer, which is in contact with the second threshold adjustment layer.10-16-2008
20100096689NON-VOLATILE MEMORY DEVICE INCLUDING NITROGEN POCKET IMPLANTS AND METHODS FOR MAKING THE SAME - In a non-volatile memory structure, the source/drain regions are surrounded by a nitrogen-doped region. As a result, an interface between the substrate and the charge trapping layer above the nitrogen-doped region is passivated by a plurality of nitrogen atoms. The nitrogen atoms can improve data retention, and performance of cycled non-volatile memory devices.04-22-2010
20110298038THREE DIMENSIONAL SEMICONDUCTOR DEVICE - Provided are a three-dimensional semiconductor memory device and manufacturing method of the three-dimensional semiconductor memory device. The three-dimensional semiconductor memory device may include a gate structure on a substrate with the gate structure including a plurality of gate electrodes. Conductive lines are disposed between the gate structure and the substrate. A horizontal semiconductor pattern is disposed between the gate structure and the conductive line. And a vertical semiconductor pattern penetrating the gate structure is connected to the horizontal semiconductor pattern.12-08-2011
20110298037VERTICAL STRUCTURE NONVOLATILE MEMORY DEVICES - A vertical structure nonvolatile memory device can include a channel layer that extends in a vertical direction on a substrate. A memory cell string includes a plurality of transistors that are disposed on the substrate in the vertical direction along a vertical sidewall of the channel layer. At least one of the plurality of transistors includes at least one recess in a gate of the transistor into which at least one protrusion, which includes the channel layer, extends.12-08-2011
20120139028SEMICONDUCTOR MEMORY DEVICE AND EMTHOD OF FORMING THE SAME - A semiconductor memory device includes a device isolation pattern defining an active region of a substrate, a buried gate electrode extending longitudinally in a given direction across the active region, a first impurity region and a second impurity region disposed along respective sides of the buried gate electrode, a conductive pad disposed on the substrate and electrically connected to the first impurity region, a first contact plug disposed on the substrate and electrically connected to the second impurity doping region, and a second contact plug disposed on the pad.06-07-2012
20130161725SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory device includes conductive films and insulating layers alternately stacked on a substrate, substantially vertical channel layers penetrating the conductive films and the insulating layers, multilayer films including a charge storage film interposed between the conductive films and the substantially vertical channel layers, and a first anti-diffusion film formed on etched surfaces of the conductive films.06-27-2013
20130161726NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A non-volatile memory device includes a channel layer vertically extending from a substrate, a plurality of inter-layer dielectric layers and a plurality of gate electrodes that are alternately stacked along the channel layer, and an air gap interposed between the channel layer and each of the plurality of gate electrodes. The non-volatile memory device may improve erase operation characteristics by suppressing back tunneling of electrons by substituting a charge blocking layer interposed between a gate electrode and a charge storage layer with an air gap, and a method for fabricating the non-volatile memory device.06-27-2013
20120286349Non-Volatile Memory Device With Additional Conductive Storage Layer - In one example, the memory device includes a gate insulation layer, a first conductive storage layer positioned above the gate insulation layer and a first non-conductive charge storage layer positioned above the first conductive storage layer. The device further includes a blocking insulation layer positioned above the first non-conductive charge storage layer and a gate electrode positioned above said blocking insulation layer.11-15-2012
20090090960NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - A non-volatile semiconductor storage device includes: a substrate; a control circuit layer provided on the substrate; a support layer provided on the control circuit layer; and a memory cell array layer provided on the support layer. The memory cell array layer includes: a first lamination part having first insulation layers and first conductive layers alternately laminated therein; and a second lamination part provided on either the top or bottom surface of the respective first lamination part and laminated so as to form a second conductive layer between second insulation layers. The control circuit layer includes at least any one of: a row decoder driving word lines provided in the memory cell array layer, and a sense amplifier sensing and amplifying a signal from bit lines provided in the memory cell array layer.04-09-2009
20110284946SEMICONDUCTOR MEMORY AND METHOD FOR MANUFACTURING SAME - A semiconductor memory capable of increasing bit density by three-dimensional arrangement of cells and a method for manufacturing the same are provided.11-24-2011
20090090962Nonvolatile semiconductor memory and method of manufacturing the same - A nonvolatile semiconductor memory device includes: a semiconductor substrate; a first gate electrode formed on the semiconductor substrate through a gate insulating film; a second gate electrode formed in a side direction of the first gate electrode and electrically insulated from the first gate electrode; and an insulating film formed at least between the semiconductor substrate and the second gate electrode to trap electric charge, as an electric charge trapping film. The first gate electrode comprises a lower portion contacting the gate insulating film and an upper portion above the lower portion of the first gate electrode, and a distance between the upper portion of the first gate electrode and the second gate electrode is longer than a distance between the lower portion of the first gate electrode and the second gate electrode.04-09-2009
20100090268SEMICONDUCTOR DEVICE AND MEMORY - A memory applicable to an embedded memory is provided. The memory includes a substrate, a gate, a charge-trapping gate dielectric layer, a source, and a drain. The gate is disposed above the substrate. The charge-trapping gate dielectric layer is disposed between the gate and the substrate. The source and the drain are disposed in the substrate beside the gate respectively.04-15-2010
20110291179Scalable Interpoly Dielectric Stacks With Improved Immunity to Program Saturation - A method for manufacturing a non-volatile memory device is described. The method comprises growing a layer in a siliconoxide consuming material, e.g. DyScO, on top of the upper layer of the layer where charge is stored. A non-volatile memory device is also described. In the non-volatile memory device, the interpoly/blocking dielectric comprises a layer in a siliconoxide consuming material, e.g. DyScO, on top of the upper layer of the layer where charge is stored, the siliconoxide consuming material having consumed at least part of the upper layer.12-01-2011
20110291178SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor device includes a substrate, a lower gate layer, a stacked body, a dummy electrode layer, an insulating film, and a channel body. The lower gate layer is provided above the substrate. The stacked body includes a plurality of insulating layers and a plurality of electrode layers alternately stacked above the lower gate layer. The dummy electrode layer is provided between the lower gate layer and the stacked body, made of the same material as the electrode layer, and thicker than each of the electrode layers. The insulating film includes a charge storage film provided on a side wall of a hole formed to penetrate through the stacked body and the dummy electrode layer. The channel body is provided on an inside of the insulating film in the hole.12-01-2011
20110291177NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A nonvolatile memory device includes a pipe insulation layer having a pipe channel hole, a pipe gate disposed over the pipe insulation layer, a pair of cell strings each having a columnar cell channel, and a pipe channel coupling the columnar cell channels and surrounding inner sidewalls and a bottom of the pipe channel hole.12-01-2011
20110291176NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A non-volatile memory device includes a pair of columnar cell channels vertically extending from a substrate, a doped pipe channel arranged to couple lower ends of the pair of columnar cell channels, insulation layers over the substrate in which the doped pipe channel is buried, memory layers arranged to surround side surfaces of the columnar cell channels, and control gate electrodes arranged to surround the memory layers.12-01-2011
20080290400SONOS ONO stack scaling - Scaling a nonvolatile trapped-charge memory device and the article made thereby. In an embodiment, scaling includes multiple oxidation and nitridation operations to provide a tunneling layer with a dielectric constant higher than that of a pure silicon dioxide tunneling layer but with a fewer hydrogen and nitrogen traps than a tunneling layer having nitrogen at the substrate interface. In an embodiment, scaling includes forming a charge trapping layer with a non-homogenous oxynitride stoichiometry. In one embodiment the charge trapping layer includes a silicon-rich, oxygen-rich layer and a silicon-rich, oxygen-lean oxynitride layer on the silicon-rich, oxygen-rich layer. In an embodiment, the method for scaling includes a dilute wet oxidation to density a deposited blocking oxide and to oxidize a portion of the silicon-rich, oxygen-lean oxynitride layer.11-27-2008
20120098052Minimizing disturbs in dense non volatile memory arrays - A nitride read only memory (NROM) array includes a silicon substrate having trenches therein, a plurality of polysilicon bit lines deposited in the trenches and connecting columns of memory cells, a layer of (oxide nitride oxide) ONO at least within the memory cells and a plurality of polysilicon word lines to connect rows of the memory cells. An NROM array with a virtual ground architecture includes a plurality of bit lines to connect columns of NROM memory cells, a layer of ONO at least within the memory cells and a plurality of word lines to connect rows of the NROM memory cells, wherein a distance between word lines is at least twice the width of the word lines.04-26-2012
20120098051NONVOLATILE MEMORY DEVICE AND METHOD OF FORMING THE SAME - A nonvolatile memory device and a method of forming the same, the device including a semiconductor substrate; a plurality of gate patterns stacked on the semiconductor substrate; inter-gate dielectric patterns between the gate patterns; active pillars sequentially penetrating the gate patterns and the inter-gate dielectric patterns to contact the semiconductor substrate; and a gate insulating layer between the active pillars and the gate patterns, wherein corners of the gate patterns adjacent to the active pillars are rounded.04-26-2012
20120098050Three-Dimensional Semiconductor Devices - Three-dimensional semiconductor devices may be provided. The devices may include a stack-structure including gate patterns and an insulation pattern. The stack-structure may further include a first portion and a second portion, and the second portion of the stack-structure may have a narrower width than the first portion. The devices may also include an active pattern that penetrates the stack-structure. The devices may further include a common source region adjacent the stack-structure. The devices may additionally include a strapping contact plug on the common source region.04-26-2012
20120098049THREE DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FABRICATING THE SAME - A three dimensional semiconductor memory device has a stacked structure including cell gates stacked therein that are insulated from each other and first string selection gates laterally separated from each other, vertical active patterns extending through the first string selection gates, multi-layered dielectric layers between sidewalls of the vertical active patterns and the cell gates and between the sidewalls of the vertical active patterns and the first string selection gates, and at least one first supplement conductive pattern. The first string selection gates are disposed over an uppermost cell gate of the cell gates. Each vertical active pattern extends through each of the cell gates stacked under the first string selection gates. The first supplement conductive pattern is in contact with a sidewall of one of the first string selection gates.04-26-2012
20120098048VERTICAL MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - A vertical memory device includes a channel, a ground selection line (GSL), word lines and a string selection line (SSL). The channel extends in a first direction substantially perpendicular to a top surface of a substrate, and a thickness of the channel is different according to height. The GSL, the word lines and the SSL are sequentially formed on a sidewall of the channel in the first direction and spaced apart from each other.04-26-2012
20090101965ELECTRON BLOCKING LAYERS FOR ELECTRONIC DEVICES - Methods and apparatuses for electronic devices such as non-volatile memory devices are described. The memory devices include a multi-layer control dielectric, such as a double or triple layer. The multi-layer control dielectric includes a combination of high-k dielectric materials such as aluminum oxide, hafnium oxide, and/or hybrid films of hafnium aluminum oxide. The multi-layer control dielectric provides enhanced characteristics, including increased charge retention, enhanced memory program/erase window, improved reliability and stability, with feasibility for single or multi state (e.g., two, three or four bit) operation.04-23-2009
20120025297NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a nonvolatile semiconductor memory device includes a source region and a drain region provided on a surface area of a semiconductor region, a tunnel insulating film provided on a channel between the source region and the drain region, a charge storage layer provided on the tunnel insulating film, a first dielectric film provided on the charge storage layer and containing lanthanum aluminum silicon oxide or oxynitride, a second dielectric film provided on the first dielectric film and containing oxide or oxynitride containing at least one of hafnium (Hf), zirconium (Zr), titanium (Ti), and a rare earth metal, and a control gate electrode provided on the second dielectric film.02-02-2012
20100102378Non-Volatile Memory Device - A non-volatile memory device and a method of fabricating the same are disclosed. The method includes the steps of: providing a semiconductor substrate having isolation layers in an isolation region, a tunnel insulating layer formed between the isolation layers, and first electron charge layers formed between the isolation layers, wherein the isolation layers comprise projections extending higher than the semiconductor substrate; etching the first electron charge layers, thereby reducing the thickness of the first electron charge layers and exposing sidewalls of the isolation layers; performing a first etch process to reduce the width of the projections; forming second electron charge layers between the projections on the first electron charge layers; and performing a second etch process to remove the projections between the second electron charge layers.04-29-2010
20100102377NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A nonvolatile semiconductor memory device includes a semiconductor substrate, a first insulating layer formed on the semiconductor substrate, a plurality of charge storage layers formed on the first insulating layer, a plurality of element isolation insulating films formed between the charge storage layers respectively, a second insulating layer formed on the charge storage layers and the element isolation insulating films, the second insulating layer including a stacked structure of a first silicon nitride film, a first silicon oxide film, an intermediate insulating film having a relative dielectric constant of not less than 7 and a second silicon oxide film, and a control electrode formed on the second insulating layer. The first silicon nitride film has a nitrogen concentration of not less than 21×1004-29-2010
20090212349SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate, and a nonvolatile memory cell provided on the semiconductor substrate, the nonvolatile memory cell including a tunnel insulating film provided on a surface of the semiconductor substrate, the tunnel insulating film including semiconductor grains, the semiconductor grains included in both end portions of the tunnel insulating film having smaller grain size than the semiconductor grains included in other portions of the tunnel insulating film, a charge storage layer provided on the tunnel insulating film, an insulating film provided on the charge storage layer, and a control gate electrode provided on the insulating film.08-27-2009
20090184362Flash memory cell string - The present invention relates to a flash memory cell string. The flash memory cell string includes a plurality of cell devices and switching devices connected to ends of the cell devices. Each of the cell devices includes a semiconductor substrate, and a transmissive insulating layer, a charge storage node, a control insulating layer and a control electrode sequentially formed on the semiconductor substrate. In the flash memory cell string, a buried insulating layer is provided on the semiconductor substrate between the cell device and an adjacent cell device, thus enabling an inversion layer, which performs the functions of source/drain, to be easily formed.07-23-2009
20090189214SEMICONDUCTOR DEVICE AND FABRICATION METHOD FOR THE SAME - The semiconductor device includes: a plurality of bit lines formed in stripes in a semiconductor substrate of a first conductivity type, each of the bit lines being a diffusion layer of an impurity of a second conductivity type; a plurality of gate insulation films s formed on regions of the semiconductor substrate between the bit lines; a plurality of word lines formed on the semiconductor substrate via the gate insulating films, the word lines extending in a direction intersecting with the bit lines; and a plurality of bit line isolation diffusion layers formed in regions of the semiconductor substrate between the word lines, each of the bit line isolation diffusion layers being a diffusion layer of an impurity of the first conductivity type. The bit line isolation diffusion layer includes a diffusion suppressor for suppressing diffusion of an impurity.07-30-2009
20090189212ELECTRONIC DEVICE HAVING A DOPED REGION WITH A GROUP 13 ATOM - An electronic device includes a memory cell. The memory cell includes a semiconductor region, a first current-carrying electrode adjacent to the semiconductor region, and a first dopant-containing region adjacent to a first current-carrying electrode. The semiconductor region includes a Group 14 atom and the first dopant-containing region includes a Group 13 atom. The Group 13 atom has an atomic number greater than the atomic number of the Group 14 atom.07-30-2009
20090078988SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a protection target element formed on a semiconductor substrate and includes a protection target element electrode, a substrate connecting part including a substrate connecting electrode electrically connected to the semiconductor substrate and a fuse structure provided between the protection target element electrode and the substrate connecting electrode and includes a fuse film configured to be torn by applying a predetermined current thereto. The protection target element electrode, the substrate connecting electrode and the fuse film are formed of an integral conductive film as long as the fuse film is not torn.03-26-2009
20100109071SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes: a semiconductor substrate; a stacked body with a plurality of conductive layers and a plurality of dielectric layers alternately stacked, the stacked body being provided on the semiconductor substrate; a semiconductor layer provided inside a hole formed through the stacked body, the semiconductor layer extending in stacking direction of the conductive layers and the dielectric layers; and a charge storage layer provided between the conductive layers and the semiconductor layer. The stacked body in a memory cell array region including a plurality of memory strings is divided into a plurality of blocks by slits with an interlayer dielectric film buried therein, the memory string including as many memory cells series-connected in the stacking direction as the conductive layers, the memory cell including the conductive layer, the semiconductor layer, and the charge storage layer provided between the conductive layer and the semiconductor layer, and each of the block is surrounded by the slits formed in a closed pattern.05-06-2010
20090315100METHOD OF MANUFACTURING SEMICONDUCTUR DEVICE - Disclosed is a method of manufacturing a semiconductor device. The method includes forming an oxide-nitride-oxide (ONO) layer over a semiconductor substrate, and forming a recess over the semiconductor substrate by etching the ONO layer, forming a vertical structure pattern being higher than the ONO layer over the recess, sequentially forming a spacer oxide film and a first gate poly over the side wall of the vertical structure pattern, and forming a nitride film spacer at a partial region of the side wall of the first gate poly, removing the nitride film spacer, and forming a second gate poly in a spacer shape over the side wall of the first gate poly, and forming a first split gate and a second split gate, symmetrically divided from each other, by removing the vertical structure pattern.12-24-2009
20090152619SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - Provided is a nonvolatile semiconductor memory device having a split gate structure, wherein a memory gate is formed over a convex shaped substrate and side surfaces of it is used as a channel. The nonvolatile semiconductor memory device according to the present invention is excellent in read current driving power even if a memory cell is scaled down.06-18-2009
20090152620ATOMIC LAYER DEPOSITION OF GdScO3 FILMS AS GATE DIELECTRICS - The use of atomic layer deposition (ALD) to form a nanolaminate dielectric of gadolinium oxide (Gd06-18-2009
20090121282Non-Volatile Memory Device and Method for Manufacturing the Same - An increase of charge storing capacity, prevention of an over-erase, and a reduction of ΔVth may be achieved when a 2-bit/cell non-volatile memory device includes a gate of a predetermined width above a semiconductor substrate, an insulating layer between the gate and the semiconductor substrate and at lateral sides of the gate, having a greater width than the gate, a pair of storage layers at the lateral sides of the gate, a pair of blocking layers at the lateral sides of the gate and covering the pair of storage layers, a source and a drain formed in the semiconductor substrate at first opposed locations external to the gate, and a trap impurity implanted into the insulating layer at second locations external to the gate.05-14-2009
20090121279SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a single crystal silicon substrate an insulating layer partially formed on the single crystal silicon substrate, a single crystal silicon layer formed on the single crystal silicon substrate and the insulating layer, and containing a defect layer resulting from an excessive group IV element, and a plurality of first gate structures for memory cells, each including a first gate insulating film formed on the single crystal silicon layer, a charge storage layer formed on the first gate insulating film, a second gate insulating film formed on the charge storage layer, and a control gate electrode formed on the second gate insulating film.05-14-2009
20090121278STRUCTURE AND FABRICATION METHOD OF FLASH MEMORY - A method for forming a flash memory cell and the structure thereof is disclosed. The flash memory cell includes a substrate, a first raised source/drain region and a second raised source/drain region separated by a trench in-between, a first charge-trapping spacer and a second charge-trapping spacer respectively on the sidewall of the first and second raised source/drain region, a gate structure covering the first and second spacers, the trench and the first and second raised source/drain regions and a gate oxide layer located between the gate structure and the first and second raised source/drain regions and the substrate. By forming the charge-trapping spacers with less e-distribution, the flash memory affords better erasure efficiency.05-14-2009
20120228694SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device according to an embodiment, includes a dielectric film and an Si semiconductor part. The dielectric film is formed by using one of oxide, nitride and oxynitride. The Si semiconductor part is arranged below the dielectric film, having at least one element of sulfur (S), selenium (Se), and tellurium (Te) present in an interface with the dielectric film, and formed by using silicon (Si).09-13-2012
20110169069HTO OFFSET AND BL TRENCH PROCESS FOR MEMORY DEVICE TO IMPROVE DEVICE PERFORMANCE - Memory devices having an increased effective channel length and/or improved TPD characteristics, and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The bit line dielectrics can extend into the semiconductor. The memory cell contains a charge trapping dielectric stack, a poly gate, a pair of pocket implant regions, and a pair of bit lines. The bit line can be formed by an implant process at a higher energy level and/or a higher concentration of dopants without suffering device short channel roll off issues because spacers at bit line sidewalls constrain the implant in narrower implant regions.07-14-2011
20080237696ALIGNMENT PROTECTION IN NON-VOLATILE MEMORY AND ARRAY - A memory device, a memory array and a method of arranging memory devices and arrays. The memory device includes a memory region including a plurality of memory cells, each memory cell with a source, a drain and a channel between the source and the drain, a channel dielectric, a charge storage region and an electrically alterable conductor-material system in proximity to the charge storage region. The memory device includes a plurality of conductor lines. The memory includes a non-memory region having embedded logic including a plurality of transistors, each transistor for electrically coupling one of the conductor lines and each transistor including a transistor source, a transistor drain and a transistor gate.10-02-2008
201102410983D STACKED ARRAY HAVING CUT-OFF GATE LINE AND FABRICATION METHOD THEREOF - A three-dimensional stacked flash memory array having cut-off gate line and a fabricating method of the same are provided. The flash memory array enables to operate two memory cells by each word line, to produce a high integrity without limitation by vertical stacks of word lines, to increase operating speed and uniformity of electrical property between cells by using a single crystal substrate as a channel region, and to reduce a fabricating cost to a great amount by a fabricating method which is including steps of forming a plurality of trenches in a semiconductor substrate and stacking repeatedly a conductive material interlaid with an insulating layer from bottom of each trench to form a cut-off gate line and a plurality of word lines.10-06-2011
20080246077Method of fabricating semiconductor memory device and semiconductor memory device fabricated by the method - In a method for fabricating a semiconductor memory device and a semiconductor memory device fabricated by the method, the method includes forming a multi-layered dielectric structure including a first dielectric layer with an ion implantation layer and a second dielectric layer without an ion implantation layer, over a semiconductor substrate; forming nanocrystals in the first and second dielectric layers by diffusing ions of the ion implantation layer by thermally treating the multi-layered dielectric structure; and forming a gate electrode on the multi-layered dielectric structure.10-09-2008
20090309152Integrated Circuits Having a Contact Region and Methods for Manufacturing the Same - In an embodiment, an integrated circuit having a memory cell arrangement is provided. The memory cell arrangement may include a substrate, a fin structure disposed above the substrate, and a memory cell contacting region. The fin structure may include a memory cell region having a plurality of memory cell structures being disposed above one another, each memory cell structure having an active region of a respective memory cell. Furthermore, the memory cell contacting region may be configured to electrically contact each of the memory cell structures, wherein the memory cell contacting region may include a plurality of contact regions, which are at least partially displaced with respect to each other in a direction parallel to the main processing surface of the substrate.12-17-2009
20100117140NON-VOLATILE MEMORY DEVICE FOR 2-BIT OPERATION AND METHOD OF FABRICATING THE SAME - A non-volatile memory device for 2-bit operation and a method of fabricating the same are provided. The non-volatile memory device includes an active region and a gate extending in a word line direction on a semiconductor substrate, and crossing each other repeatedly; a charge storage layer disposed below the gate, and confined at a portion where the gate and the active region cross; a charge blocking layer formed on the charge storage layer; a tunnel dielectric layer formed below the charge storage layer; first and second source/drain regions formed in the active region exposed by the gate; and first and second bit lines crossing the word line direction. The active region may be formed in a first zigzag pattern and/or the gate may be formed in a second zigzag pattern in symmetry with the first zigzag pattern.05-13-2010
20090283820NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - A non-volatile semiconductor memory device includes a memory cell array having a cell transistor and a selective transistor provided on a semiconductor substrate. The cell transistor includes a tunnel insulation film, a charge accumulation layer, a block insulation film, and a gate electrode on the substrate. The charge accumulation layer is disconnected between adjacent cell transistors. The selective transistor includes a gate insulation film and a gate electrode formed of the same material as the material of the block insulation film on the substrate. A step is provided on a surface of the substrate between the cell transistor and the selective transistor, such that the step is positioned higher on a side of the cell transistor and lower on a side of the selective transistor.11-19-2009
20090014779NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A nonvolatile semiconductor memory device includes bit line diffusion layers extending along the X direction in an upper portion of a semiconductor substrate; and gate structures extending along the Y direction on the semiconductor substrate and each including a charge trapping film and a gate electrode. The nonvolatile semiconductor memory device further includes a first interlayer insulating film in which first contacts respectively connected to the bit line diffusion layers are formed; and second contacts that penetrate through a UV blocking film and a second interlayer insulating film formed on the first interlayer insulating film and have bottom faces respectively in contact with the first contacts and top faces respectively in contact with metal interconnections.01-15-2009
20100084702NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A nonvolatile semiconductor memory device comprises a memory cell configured to store data and a resistor element provided around the memory cell. The memory cell includes a charge storage layer provided above a substrate, a first semiconductor layer formed on a top surface of the charge storage layer via an insulating layer, and a first low resistive layer formed on a top surface of the first semiconductor layer and having resistance lower than that of the first semiconductor layer. The resistor element includes a second semiconductor layer formed on the same layer as the first semiconductor layer, and a second low resistive layer formed on the same layer as the first low resistive layer and on a top surface of the second semiconductor layer, having resistance lower than that of the second semiconductor layer. The second semiconductor layer is formed to extend in a first direction parallel to the substrate. The second low resistive layer is formed at both ends of the second semiconductor layer in the first direction.04-08-2010
20120032249NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a nonvolatile semiconductor memory device includes a multilayer body, a semiconductor pillar, a memory layer, a first insulating film and a second insulating film. The multilayer body includes a plurality of interelectrode insulating films and a plurality of electrode films alternately stacked in a first direction. The semiconductor pillar penetrates through the multilayer body in the first direction. The memory layer is provided between each of the electrode films and the semiconductor pillar and extends in the first direction. The first insulating film is provided between the memory layer and the semiconductor pillar and extends in the first direction. The second insulating film is provided between each of the electrode films and the memory layer and extends in the first direction. The second insulating film is projected between the electrode films.02-09-2012
20100117139Methods of Operating Non-Volatile Memory Devices - Methods of operating non-volatile memory devices are described. The memory devices comprise memory cells having an n-type semiconductor substrate and p-type source and drain regions disposed below a surface of the substrate and separated by a channel region. A tunneling dielectric layer is disposed above the channel region. A charge storage layer is disposed above the tunneling dielectric layer. An upper insulating layer is disposed above the charge storage layer, and a gate is disposed above the upper insulating multi-layer structure. A positive bias is applied to a word line of the memory device in a selected memory cell and a negative bias is applied to a bit line in the selected cell. In another memory device, opposite polarity voltages are applied to the bit line and the word line.05-13-2010
20090267137METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING NOTCHED GATE MOSFET - Provided is a method of manufacturing a semiconductor device, by which a cell transistor formed on a cell array area of a semiconductor substrate employs a structure in which an electrode in the shape of spacers is used to form a gate and a multi-bit operation is possible using localized bits, and transistors having structures optimized to satisfy different requirements depending upon functions of the transistors can be formed on a peripheral circuit area which is the residual area of the semiconductor substrate. In this method, a cell transistor is formed on the cell array area. The cell transistor includes a notch gate structure, a first channel region formed on a semiconductor substrate under the notch gate structure, a source region and a drain region formed on both sides of the first channel region, a first gate insulation film formed between the first channel region and the notch gate structure, and a memory layer locally formed on areas adjacent to the source and drain regions between the first channel region and the notch gate structure. At the same time that the cell transistor is formed, a plurality of peripheral circuit transistors including at least one transistor having a different structure from the cell transistor are formed on the peripheral circuit area.10-29-2009
20110147826Methods Of Forming Memory Cells - Some embodiments include methods of utilizing polysilazane in forming non-volatile memory cells. The memory cells may be multi-level cells (MLCs). The polysilazane may be converted to silicon nitride, silicon dioxide, or silicon oxynitride with thermal processing and exposure to an ambient that contains one or both of oxygen and nitrogen. The methods may include using the polysilazane in forming a charge trapping layer of a non-volatile memory cell. The methods may alternatively, or additionally include using the polysilazane in forming intergate dielectric material of a non-volatile memory cell. Some embodiments include methods of forming memory cells of a NAND memory array.06-23-2011
20110198685Non-Volatile Memory Devices - Non-volatile memory devices are provided including a control gate electrode on a substrate; a charge storage insulation layer between the control gate electrode and the substrate; a tunnel insulation layer between the charge storage insulation layer and the substrate; a blocking insulation layer between the charge storage insulation layer and the control gate electrode; and a material layer between the tunnel insulation layer and the blocking insulation layer, the material layer having an energy level constituting a bottom of a potential well.08-18-2011
20110147823VERTICAL CHANNEL TYPE NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a vertical channel type nonvolatile memory device includes forming alternately a plurality of interlayer dielectric layers and a plurality of conductive layers over a substrate, forming a trench having a plurality of recesses on a surface of the trench by etching the plurality of interlayer dielectric layers and a plurality of conductive layers, wherein the plurality of recesses are formed at a certain interval on the surface of the trench, forming a charge blocking layer over a plurality of surfaces of the plurality of recesses, forming a charge storage layer over the charge blocking layer for filling a plurality of the remaining recesses with a charge storage material, forming a tunnel dielectric layer to cover the charge storage layer, and forming a vertical channel layer by filling the remaining trench.06-23-2011
20110147824SEMICONDUCTOR DEVICES AND METHODS FOR FABRICATING THE SAME - In semiconductor devices and methods of manufacture, a semiconductor device comprises a substrate of semiconductor material extending in a horizontal direction. A plurality of interlayer dielectric layers are on the substrate. A plurality of gate patterns are provided, each gate pattern between a neighboring lower interlayer dielectric layer and a neighboring upper interlayer dielectric layer. A vertical channel of semiconductor material is on the substrate and extending in a vertical direction through the plurality of interlayer dielectric layers and the plurality of gate patterns. The vertical channel has an outer sidewall, the outer sidewall having a plurality of channel recesses, each channel recess corresponding to a gate pattern of the plurality of gate patterns. The vertical channel has an inner sidewall. An information storage layer is present in the recess between each gate pattern and the vertical channel that insulates the gate pattern from the vertical channel.06-23-2011
20100078704SEMICONDUCTOR STORAGE ELEMENT AND MANUFACTURING METHOD THEREOF - A semiconductor storage element includes: a source region and a drain region provided in a semiconductor substrate; a tunnel insulating film provided on the semiconductor substrate between the source region and the drain region; a charge storage film provided on the tunnel insulating film; a block insulating film provided on the charge storage film; a gate electrode provided on the block insulating film; and a region containing a gas molecule, the region provided in a neighborhood of an interface between the charge storage film and the block insulating film.04-01-2010
20100078705NON-VOLATILE MEMORY SEMICONDUCTOR DEVICE - A technique capable of improving the reliability of a non-volatile memory semiconductor device is provided and, in particular, a technique capable of supplying electricity without fail to a memory gate electrode of split gate transistor is provided.04-01-2010
20100078703SPLIT-GATE NON-VOLATILE MEMORY CELL AND METHOD - A method is disclosed for making a non-volatile memory cell on a semiconductor substrate. A select gate structure is formed over the substrate. The control gate structure has a sidewall. An epitaxial layer is formed on the substrate in a region adjacent to the sidewall. A charge storage layer is formed over the epitaxial layer. A control gate is formed over the charge storage layer. This allows for in-situ doping of the epitaxial layer under the select gate without requiring counterdoping. It is beneficial to avoid counterdoping because counterdoping reduces charge mobility and increases the difficulty in controlling threshold voltage. Additionally there may be formed a recess in the substrate and the epitaxial layer is formed in the recess, and a halo implant can be performed, prior to forming the epitaxial layer, through the recess into the substrate in the area under the select gate.04-01-2010
201100625103D NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A non-volatile memory device having a string of a plurality of memory cells that are serially coupled, wherein the string of memory cells includes a plurality of second channels of a pillar type, a first channel coupling lower end portions of the plurality of the second channels with each other, and a plurality of control gate electrodes surrounding the plurality of the second channels.03-17-2011
20110062509SEMICONDUCTOR DEVICE HAVING UPPER LAYER PORTION OF SEMICONDUCTOR SUBSTRATE DIVIDED INTO A PLURALITY OF ACTIVE AREAS - A semiconductor memory device includes: a semiconductor substrate; a plurality of element isolation insulators disposed in parts of an upper layer portion of the semiconductor substrate and dividing the upper layer portion into a plurality of active areas extended in one direction; tunnel insulating films provided on the active areas: charge storage members provided on the tunnel insulating films; and control gate electrodes provided on the charge storage members. A width of a middle portion of one of the active areas in the up-to-down direction being smaller than a width of a portion of the active areas upper of the middle portion and a width of a portion of the active areas below the middle portion.03-17-2011
20120193699NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND PRODUCTION METHOD FOR THE SAME - According to one embodiment, a nonvolatile semiconductor memory device includes a semiconductor substrate; an element isolation insulating film buried in the semiconductor substrate so as to isolate adjacent element; a memory cell having a first insulating film and a charge accumulation film; a second insulating film formed on the charge accumulation films of the memory cells and the element isolation insulating film; and a control electrode film formed on the second insulating film. An upper surface of the element isolation insulating film is lower than an upper surface of the charge accumulation film, the second insulating film is provided with a cell upper portion on the charge accumulation film and an inter-cell portion on the element isolation insulating film, and a dielectric constant of the cell upper portion is lower than a dielectric constant of the inter-cell portion.08-02-2012
20120193700Semiconductor Memory Device And Method Of Forming The Same - Semiconductor memory devices and methods of forming semiconductor memory devices are provided. The methods may include forming insulation layers and cell gate layers that are alternately stacked on a substrate, forming an opening by successively patterning through the cell gate layers and the insulation layers, and forming selectively conductive barriers on sidewalls of the cell gate layers in the opening.08-02-2012
20090206392Memory device and fabrication method thereof - A method of forming a memory device, where a first insulator layer and a charge trapping layer may be formed on a substrate, and at least one of the first insulator layer and charge trapping layer may be patterned to form patterned areas. A second insulation layer and a conductive layer may be formed on the patterned areas, and one or more of the conductive layer, second insulator layer, charge trapping layer and first insulator layer may be patterned to form a string selection line, ground selection line, a plurality of word lines between the string selection and ground selection lines on the substrate, a low voltage gate electrode, and a plurality of insulators of varying thickness. The formed memory device may be a NAND-type non-volatile memory device having a SONOS gate structure, for example.08-20-2009
20090206391SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor memory device has a semiconductor substrate, a plurality of word lines formed on the semiconductor substrate at predetermined intervals, a selecting transistor arranged on each of two sides of each of the plurality of word lines in which a spacing between the selecting transistor and an adjacent one of the word lines is not less than three times a width of each of the word lines, an interlayer insulating film formed to cover upper surfaces of the word lines and selecting transistors, a first cavity portion which is located between each pair of adjacent ones of the word lines and whose upper portion is covered with the interlayer insulating film, a second cavity portion which is formed at a side wall portion of the word line adjacent to each selecting transistor which faces the selecting transistor and whose upper portion is covered with the interlayer insulating film, and a third cavity portion which is formed at a side wall portion of each of the selecting transistors and whose upper portion is covered with the interlayer insulating film.08-20-2009
20090206390SEMICONDUCTOR NONVOLATILE MEMORY DEVICE WITH INTER-GATE INSULATING FILM FORMED ON THE SIDE SURFACE OF A MEMORY CELL AND METHOD FOR MANUFACTURING THE SAME - A nonvolatile semiconductor device and method having a plurality of series-connected memory cells with floating and control gate electrodes, and a first insulating layer formed between the gate electrodes. One of the memory cells has the floating gate formed to contact the control gate electrode through an aperture in the insulating layer. The insulating layer is removed to form spaces between the gate electrodes. A second insulating film is formed in the spaces between the gate electrodes. The dummy electrode supports the series of gate electrodes to maintain the spaces between the electrodes. The second insulating layer is formed to be continuous in the spaces and on side surfaces of the gate electrodes. The second insulating layer may have a stacked structure with n layers in the spaces and (n−1)/2 layers on the side surfaces.08-20-2009
20090206387Non-volatile memory device, method of fabricating the same, and non-volatile semiconductor integrated circuit device, including the same - A non-volatile memory device has improved operating characteristics. The non-volatile memory device includes an active region; a wordline formed on the active region to cross the active region; and a charge trapping layer interposed between the active region and the wordline, wherein a cross region of the active region and the wordline includes an overlap region in which the charge trapping layer is disposed and a non-overlap region in which the charge trapping layer is not disposed.08-20-2009
20090101964Method of forming nano dots, method of fabricating the memory device including the same, charge trap layer including the nano dots and memory device including the same - Provided are a method of forming nano dots, method of fabricating a memory device including the same, charge trap layer including the nano dots and memory device including the same. The method of forming the nano dots may include forming cores, coating surfaces of the cores with a polymer, and forming graphene layers covering the surfaces of the cores by thermally treating the cores coated with the polymer. Also, the cores may be removed after forming the graphene layers. In addition, the surfaces of the cores may be coated with a graphitization catalyst material before coating the cores with the polymer. Also, the cores may include metal particles that trap charges and may also function as a graphitization catalyst.04-23-2009
20090014778NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A nonvolatile semiconductor memory device includes bit line diffusion layers extending along the X direction in an upper portion of a semiconductor substrate; and gate structures extending along the Y direction on the semiconductor substrate and each including a charge trapping film and a gate electrode. The nonvolatile semiconductor memory device further includes a first interlayer insulating film in which first contacts respectively connected to the bit line diffusion layers are formed; and second contacts that penetrate through a UV blocking film and a second interlayer insulating film formed on the first interlayer insulating film and have bottom faces respectively in contact with the first contacts and top faces respectively in contact with metal interconnections.01-15-2009
20090152617HETERO-STRUCTURE VARIABLE SILICON RICHNESS NITRIDE FOR MLC FLASH MEMORY DEVICE - Charge storage stacks containing hetero-structure variable silicon richness nitride for memory cells and methods for making the charge storage stacks are provided. The charge storage stack can contain a first insulating layer on a semiconductor substrate; n charge storage layers comprising silicon-rich silicon nitride on the first insulating layer, wherein numbers of the charge storage layers increase from the bottom to the top and a k-value of an n-1th charge storage layer is higher than a k-value of an nth charge storage layer; n-1 dielectric layers comprising substantially stoichiometric silicon nitride between each of the n charge storage layers; and a second insulating layer on the nth charge storage layers.06-18-2009
20090242964NON-VOLATILE MEMORY DEVICE - A finFET-based non-volatile memory device on a semiconductor substrate includes source and drain regions, a fin body, a charge trapping stack and a gate. The fin body extends between the source and the drain region as a connection. The charge trapping stack covers a portion of the fin body and the gate covers the charge trapping stack at the location of the fin body. The fin body has a corner-free shape for at least ¾ of the circumference of the fin body which lacks distinct crystal faces and transition zones in between the crystal faces.10-01-2009
20090090959NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - A first lamination part includes: a charge accumulation layer provided on the respective sidewalls of laminated first conductive layers and accumulating charges; and a first semiconductor layer provided in contact with the fourth insulation layer and formed to extend to the lamination direction. A second lamination part includes a second semiconductor layer provided in contact with the first semiconductor layer. A third lamination part includes: a plurality of first contact layers formed in contact with the respective second lamination part, extending to a first direction perpendicular to the lamination direction, and in line with each other along a second direction perpendicular to the first direction; and a plurality of contact plug layers formed in contact with any one of the first contact layers and extending to the lamination direction. The contact plug layers are arranged at different positions relative to each other in the first direction.04-09-2009
20100123183NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A technique capable of improving the memory retention characteristics of a non-volatile memory is provided. In particular, a technique of fabricating a non-volatile semiconductor memory device is provided capable of enhancing the film quality of a silicon oxide film even when a silicon oxide film as a first potential barrier film is formed with a plasma oxidation method to improve the memory retention characteristics of the non-volatile memory. After a silicon oxide film, which is a main component of a first potential barrier film, is formed with a plasma oxidation method, plasma nitridation at a high temperature and a heat treatment in an atmosphere containing nitric oxide are performed in combination, thereby forming a silicon oxynitride film on the surface of the silicon oxide film, and segregating nitrogen to an interface between the silicon oxide film and a semiconductor substrate.05-20-2010
20090273018NONVOLATILE MEMORY DEVICE WITH MULTIPLE BLOCKING LAYERS AND METHOD OF FABRICATING THE SAME - A nonvolatile memory device with a blocking layer controlling the transfer of electric charges in a charge storage layer includes the blocking layer having a first blocking layer in contact with the charge storage layer and a second blocking layer over the first blocking layer, wherein the first blocking layer has a greater energy band gap than the second blocking layer and the second blocking layer has a greater permittivity than the first blocking layer.11-05-2009
20090278194Capacitorless one-transistor semiconductor memory device having improved data retention abilities and operation characteristics - A capacitorless one transistor (1T) semiconductor device whose data storage abilities are increased and leakage current is reduced is provided. The capacitor-less 1T semiconductor device includes a buried insulating layer formed on a substrate, an active region formed on the buried insulating layer and including a source region, a drain region and a floating body formed between the source region and the drain region, and a gate pattern formed on the floating body, wherein the floating body includes a main floating body having the same top surface height as one of the source region and the drain region, and a first upper floating body formed between the main floating body and the gate pattern.11-12-2009
20090090961Non-Volatile Semiconductor Memory Device - A non-volatile semiconductor device includes an n type well formed in a semiconductor substrate having a surface, the surface having a plurality of stripe shaped grooves and a plurality of stripe shaped ribs, a plurality of stripe shaped p type diffusion regions formed in upper parts of each of the plurality of ribs, the plurality of stripe shaped p type diffusion regions being parallel to a longitudinal direction of the ribs, a tunneling insulation film formed on the grooves and the ribs, a charge storage layer formed on the tunneling insulating film, a gate insulation film formed on the charge storage layer, and a plurality of stripe shaped conductors formed on the gate insulating film, the plurality of stripe shaped conductors arranged in a direction intersecting the longitudinal direction of the ribs with a predetermined interval wherein an impurity diffusion structure in the ribs are asymmetric.04-09-2009
20080277720NON-VOLATILE MEMORY DEVICE, METHOD OF FABRICATING THE SAME, AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME - A non-volatile memory device which can be highly-integrated without a decrease in reliability, and a method of fabricating the same, are provided. In the non-volatile memory device, a first doped layer of a first conductivity type is disposed on a substrate. A semiconductor pillar of a second conductivity type opposite to the first conductivity type extends upward from the first doped layer. A first control gate electrode substantially surrounds a first sidewall of the semiconductor pillar. A second control gate electrode substantially surrounds a second sidewall of the semiconductor pillar and is separated from the first control gate electrode. A second doped layer of the first conductivity type is disposed on the semiconductor pillar.11-13-2008
20110198683Patterns of Nonvolatile Memory Device and Method of Forming the Same - Patterns of a nonvolatile memory device include a semiconductor substrate that defines active regions extending in a longitudinal direction, an isolation structure formed between the active regions, a tunnel insulating layer formed on the active regions, a charge trap layer formed on the tunnel insulating layer, a first dielectric layer formed on the charge trap layer and the isolation structure, wherein the first dielectric layers is extended along a lateral direction, a control gate layer formed on the first dielectric layer, wherein the control gate layer is extended along the lateral direction, and a second dielectric layer formed on a sidewall of the control gate layer along the lateral direction and coupled to the first dielectric layer.08-18-2011
20110198682NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - In one embodiment, a nonvolatile semiconductor memory device includes a substrate, and a well of a first conductivity type formed in the substrate. The device further includes a plurality of first isolation layers disposed in parallel to each other in the well, and a second isolation layer disposed in parallel to the first isolation layers in the well, a width of a substrate surface between the second isolation layer and the first isolation layers being set greater than a width of a substrate surface between the first isolation layers. The device further includes a memory cell including a gate insulator, a floating gate, an inter-gate insulator, and a control gate sequentially disposed on the well between the first isolation layers, and a dummy cell including a gate insulator, a floating gate, an inter-gate insulator, and a control gate sequentially disposed on the well between the second isolation layer and one of the first isolation layers. The device further includes a diffusion layer of a second conductivity type formed under the dummy cell in the well between the second isolation layer and the one of the first isolation layers, an upper surface of the diffusion layer being formed at a position higher than bottom surfaces of the first and second isolation layers with the surface of the substrate.08-18-2011
20090289297CHARGE TRAP-TYPE NON-VOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A charge trap-type non-volatile memory device, and related method, includes forming over a substrate a tunnel insulating layer, a charge trapping layer, a dielectric layer, and a conductive layer for a gate electrode; forming a gate electrode by selectively etching the conductive layer for the gate electrode; forming a spacer including a first spacer and a second spacer on a sidewall of the gate electrode, the second spacer being formed of material different from that of the first spacer; and etching the dielectric layer and the charge trapping layer by using the spacer as an etching barrier, thereby preventing an attack to the gate electrode when etching the charge trapping layer and thus enhancing reliability and stability of transistors. In addition, in one or more embodiments, a sidewall of the charge trapping layer pattern is formed vertically, thereby preventing formation of a tail and an attack to the substrate.11-26-2009
20090273020SONOS Flash Memory - A method for fabricating a silicon-oxide-nitride-oxide-silicon (SONOS) flash memory, comprising: preparing a silicon substrate including a silicon oxide-silicon nitride-silicon oxide (ONO) layer, a first polysilicon layer and a first etch stop layer in sequence; etching the first etch stop layer along a direction of bit line; selectively etching the first polysilicon layer with the first etch stop layer as a mask, till the silicon oxide-silicon nitride-silicon oxide (ONO) layer is exposed, the etched first polysilicon layer having an inverse trapezia section along a direction of word line; filling a dielectic layer between portions of the first polysilicon layer, the dielectric layer having a trapezia section along the direction of word line. After the above steps, it becomes easy to remove the portion of the first polysilicon layer on a sidewall of the dielectric layer by vertical etching. Thus, no polysilicon residue will be formed on the sidewall of the dielectric layer. Thereby, the short circuit between different memory cells may be avoided.11-05-2009
20110198684SELF-ALIGNED CHARGE STORAGE REGION FORMATION FOR SEMICONDUCTOR DEVICE - Devices and methods for forming self-aligned charge storage regions are disclosed. In one embodiment, a method for manufacturing a semiconductor device comprises forming a layer of a nitride film stacked between two oxide films on a semiconductor substrate, and forming a gate electrode on the layer of the nitride film stacked between the two oxide films. In addition, the method comprises removing side portions of the nitride film such that a central portion of the nitride film below a center portion of the gate electrode remains, oxidizing the central portion of the nitride film, and forming charge storage layers in the side portions of the nitride film, where the charge storage layers are separated by the central portion of the nitride film.08-18-2011
20090294835SEMICONDUCTOR MEMORY DEVICE INCLUDING LAMINATED GATE HAVING ELECTRIC CHARGE ACCUMULATING LAYER AND CONTROL GATE AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory device includes a first active region, a second active region, an element isolation region, memory cell transistors. Each of memory cell transistors includes a laminated gate and a first impurity diffusion layer functioning as a source and a drain. The laminated gate includes a first insulating film, a second insulating film, and a control gate electrode. The second insulating film is commonly connected between the plurality of memory cell transistors to step over the element isolation region and is in contact with an upper surface of the element isolation region. An upper surface of the element isolation region is higher than a bottom surface of the first insulating film and is located under the upper surface of the first insulating film.12-03-2009
20090278192SEMICONDUCTOR DEVICE - A semiconductor device includes a tunnel insulation layer pattern, a charge trapping layer pattern, a blocking layer pattern and a gate structure. The tunnel insulation layer pattern is formed on a substrate. The charge trapping layer pattern is formed on the tunnel insulation layer pattern. The blocking layer pattern is formed on the substrate and extends up onto and covers the charge trapping layer pattern. The gate surrounds an upper portion of the charge trapping layer pattern so as to face towards and upper surface and opposite side surfaces of the charge trapping layer pattern.11-12-2009
20090283821NONVOLATILE MEMORY AND MANUFACTURING METHOD THEREOF - Isolation trenches are formed in the main surface of a semiconductor substrate, and isolation regions. are embedded in these trenches. First insulating films, charge storage layers, a second insulating film, and a control gate are formed on the main surface of the semiconductor substrate sectioned by the isolation regions. Shielding layers are arranged in the isolation regions in such a manner that their bottom portions are lower than the channel regions and their upper portions are higher than at least the main surface of the semiconductor substrate to provide an electric and magnetic shield between their storage layers and channel regions of adjacent memory cells.11-19-2009
20090283819NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - A nonvolatile semiconductor memory device includes: a substrate; a plurality of dielectric films and electrode films which are alternately stacked on the substrate and have a through hole penetrating in the stacking direction; a semiconductor pillar formed inside the through hole; and a charge storage layer provided at least between the semiconductor pillar and the electrode film. At least part of a side surface of a portion of the through hole located in the electrode film is sloped relative to the stacking direction.11-19-2009
20130099303MEMORY AND MANUFACTURING METHOD THEREOF - A memory and a manufacturing method thereof are provided. A plurality of stacked structures extending along a first direction is formed on a substrate. Each of the stacked structures includes a plurality of first insulating layers and a plurality of second insulating layers. The first insulating layers are stacked on the substrate and the second insulating layers are respectively disposed between the adjacent first insulating layers. A plurality of trenches extending along the first direction is formed in each of the stacked structures. The trenches are respectively located at two opposite sides of each of the second insulating layers. A first conductive layer is filled in the trenches. A plurality of charge storage structures extending along a second direction is formed on the stacked structures and a second conductive layer is formed on each of the charge storage structures.04-25-2013
201300993043-DIMENSIONAL NONVOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - The device includes plural control gates stacked on a substrate, plural first channels, configured to penetrate the control gates, and plural memory layer patterns, each located between the control gate and the first channel, configured to respectively surround the first channel, wherein the memory layer patterns are isolated from one another.04-25-2013
20090294837Nonvolatile Memory Devices Having a Fin Shaped Active Region - A nonvolatile memory device includes a semiconductor substrate and a device isolation layer on the semiconductor substrate. A fin-shaped active region is formed between portions of the device isolation layer. A sidewall protection layer is formed on the sidewall of the fin-shaped active region where source and drain regions are formed. Thus, it may be possible to reduce the likelihood of an undesirable connection between an interconnection layer connected to the source and drain regions and a lower sidewall of the active region so that charge leakage from the interconnection layer to a substrate can be prevented or reduced. The sidewall protection layer may be formed using the device isolation layer. Alternatively, an insulating layer having an etch selectivity with respect to an interlayer insulating layer may be formed on the device isolation layer so as to cover the sidewall of the active region.12-03-2009
20090294833Semiconductor memory device and method of fabricating the same - A semiconductor memory device includes a memory substrate including memory transistors and vertical active pillars, the vertical active pillars defining active regions of the memory transistors, a peripheral circuit substrate including peripheral circuit transistors, a bonding layer interposed between the memory substrate and the peripheral circuit substrate, and a connection structure electrically connecting the memory transistors to the peripheral circuit transistors.12-03-2009
20090294832Semiconductor Device - One or more embodiments relate to a memory device, comprising: a substrate; a charge storage layer disposed over the substrate; and a control gate disposed over the charge storage layer, wherein the charge storage layer or the control gate layer comprises a carbon allotrope.12-03-2009
20090261405Non-Volatile Memory Devices - Non-volatile memory devices include a tunnel insulating layer on a channel region of a substrate, a charge-trapping layer pattern on the tunnel insulating layer and a first blocking layer pattern on the charge-trapping layer pattern. Second blocking layer patterns are on the tunnel insulating layer proximate sidewalls of the charge-trapping layer pattern. The second blocking layer patterns are configured to limit lateral diffusion of electrons trapped in the charge-trapping layer pattern. A gate electrode is on the first blocking layer pattern. The second blocking layer patterns may prevent lateral diffusion of the electrons trapped in the charge-trapping layer pattern.10-22-2009
20090261403SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a memory cell transistor including a first lower insulating film provided on a semiconductor substrate, a first intermediate insulating film provided on the first lower insulating film, a first upper insulating film provided on the first intermediate insulating film, and a first gate electrode provided on the first upper insulating film, and a select transistor including a second lower insulating film provided on the semiconductor substrate, a second intermediate insulating film provided on the second lower insulating film, a second upper insulating film provided on the second intermediate insulating film, and a second gate electrode provided on the second upper insulating film, wherein trap density of the second intermediate insulating film is lower than that of the first intermediate insulating film.10-22-2009
20090261402METHOD AND STRUCTURE FOR A SEMICONDUCTOR CHARGE STORAGE DEVICE - A semiconductor charge storage device includes a semiconductor substrate having a surface region. The semiconductor substrate is characterized by a first conductivity type. A charge trapping material overlies and is in contact with at least a portion of the surface region of the semiconductor substrate. The charge trapping material is characterized by a first dielectric constant and by a first charge trapping capability. The first dielectric constant is higher than a dielectric constant associated with silicon oxide. A dielectric material overlies and is in contact with at least a portion of the charge trapping material. The dielectric material is formed using a conversion of a portion of the charge trapping material for providing a second charge trapping capability. The device also includes a conductive material overlying the second dielectric. The conductive material is capable of receiving an electrical signal to cause electrical charges being trapped in the semiconductor charge storage device.10-22-2009
20090261401NON-VOLATILE MEMORY CELL AND METHOD OF FABRICATING THE SAME - A non-volatile memory cell is described, including a semiconductor substrate, two separate charge trapping structures on the substrate, first spacers at least on the opposite sidewalls of the two charge trapping structures, a gate dielectric layer on the substrate between the two charge trapping structures, a gate on the two charge trapping structures and the gate dielectirc layer, and two doped regions in the substrate beside the gate.10-22-2009
20090039414CHARGE TRAPPING MEMORY CELL WITH HIGH SPEED ERASE - A band gap engineered, charge trapping memory cell includes a charge trapping element that is separated from a metal or metal compound gate, such as a platinum gate, by a blocking layer of material having a high dielectric constant, such as aluminum oxide, and separated from the semiconductor body including the channel by an engineered tunneling dielectric. Fast program and erase speeds with memory window as great as 7 V are achieved.02-12-2009
20090166715Scalable Interpoly Dielectric Stacks With Improved Immunity To Program Saturation - A method for manufacturing a non-volatile memory device is described. The method comprises growing a layer in a siliconoxide consuming material, e.g. DyScO, on top of the upper layer of the layer where charge is stored. A non-volatile memory device is also described. In the non-volatile memory device, the interpoly/blocking dielectric comprises a layer in a siliconoxide consuming material, e.g. DyScO, on top of the upper layer of the layer where charge is stored, the siliconoxide consuming material having consumed at least part of the upper layer.07-02-2009
20100283099Non-Volatile Semiconductor Memory Device and Manufacturing Method Thereof - A non-volatile semiconductor device includes an n type well formed in a semiconductor substrate having a surface, the surface having a plurality of stripe shaped grooves and a plurality of stripe shaped ribs, a plurality of stripe shaped p type diffusion regions formed in upper parts of each of the plurality of ribs, the plurality of stripe shaped p type diffusion regions being parallel to a longitudinal direction of the ribs, a tunneling insulation film formed on the grooves and the ribs, a charge storage layer formed on the tunneling insulating film, a gate insulation film formed on the charge storage layer, and a plurality of stripe shaped conductors formed on the gate insulating film, the plurality of stripe shaped conductors arranged in a direction intersecting the longitudinal direction of the ribs with a predetermined interval wherein an impurity diffusion structure in the ribs are asymmetric.11-11-2010
20110266611NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A nonvolatile memory device includes a plurality of interlayer dielectric layers and conductive layers for gate electrodes alternately stacked over a substrate, a channel trench passing through the interlayer dielectric layers and the conductive layers and exposing the substrate, a charge blocking layer and a charge trap or charge storage layer formed on sidewalls of the trench, a coupling prevention layer formed at the surface of the charge trap or charge storage layer, and a tunnel insulation layer formed over the coupling prevention layer.11-03-2011
20110204431FULLY DEPLETED SILICON-ON-INSULATOR CMOS LOGIC - A extractor implanted region is used in a silicon-on-insulator CMOS memory device. The extractor region is reversed biased to remove minority carriers from the body region of partially depleted memory cells. This causes the body region to be fully depleted without the adverse floating body effects.08-25-2011
20090166717NONVOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - Embodiments relate to a nonvolatile memory device and a method for manufacturing the same. According to embodiments, a nonvolatile memory device may include a tunnel ONO film having an oxide film, a nitride film, and an oxide film stacked on and/or over a semiconductor substrate. It may also include a trap nitride film formed on and/or over the tunnel ONO film, a blocking oxide film formed on and/or over the trap nitride film and having a high-dielectric film with a higher dielectric constant than a dielectric constant of a SiO07-02-2009
20090166716SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a first oxide-nitride-oxide (ONO) layer in which a block oxide, a tunnel oxide and a trap nitride are stacked sequentially on one side of a semiconductor substrate; a second oxide-nitride-oxide (ONO) layer in which the block oxide, the tunnel oxide and the trap nitride are stacked sequentially on the other side of the semiconductor substrate; a third oxide formed between the first ONO layer and the second ONO layer; a silicon gate formed on the first ONO layer, the second ONO layer and the third oxide; and a source region and a drain region formed on the surface of the semiconductor substrate of both sides of the silicon gate.07-02-2009
20090166714Non-volatile memory device - A non-volatile memory device includes field insulating layer patterns on a substrate to define an active region of the substrate, upper portions of the field insulating layer patterns protruding above an upper surface of the substrate, a tunnel insulating layer on the active region, a charge trapping layer on the tunnel insulating layer, a blocking layer on the charge trapping layer, first insulating layers on upper surfaces of the field insulating layer patterns, and a word line structure on the blocking layer and first insulating layers.07-02-2009
20090166713Semiconductor Device and Method of Fabricating the Same - Provided are a semiconductor device and a method of fabricating the same. The semiconductor device comprises a plurality of device isolation layers disposed in a semiconductor substrate, the device isolation layers extending in a word line direction and spaced apart from each other; a plurality of floating gate devices extending in a bit line direction perpendicular to the device isolation layer and spaced apart from each other; a source region and a drain region disposed at sides of the floating gate device; an insulation layer disposed on the floating gate device and the source region, and a polysilicon line extending in the word line direction and connected to the drain region.07-02-2009
20080277719NON-VOLATILE MEMORY CELL AND METHOD OF MANUFACTURING THE SAME - The present invention relates to a non-volatile memory cell and a method of fabricating the same. The non-volatile memory cell according to the present invention comprises a substrate, a first oxide film formed over an active region of the substrate, a source and drain formed within the active region, a charge storage unit formed on the first oxide film, a second oxide film configured to surround the charge storage unit and formed on the first oxide film, and a gate formed to surround the second oxide film. According to the non-volatile memory cell and a cell array including the same in accordance with the present invention, the charge storage unit is fully surrounded by the gate or the gate line, thus a disturbance phenomenon that may occur due to the memory operation of cells formed in other neighboring gate or gate line can be minimized.11-13-2008
20080277717MINORITY CARRIER SINK FOR A MEMORY CELL ARRAY COMPRISING NONVOLATILE SEMICONDUCTOR MEMORY CELLS - A memory cell array of nonvolatile semiconductor memory cells is specified in which a minority carrier sink is formed within a semiconductor body in the region of the memory cell array, the minority carrier sink being arranged outside a space charge zone structure that forms in the semiconductor body during operation of the semiconductor memory cells, and the minority carrier sink having a shorter minority carrier lifetime in comparison with a semiconductor zone reaching as far as a surface of the semiconductor body.11-13-2008
20080283901NONVOLATILE MEMORY WITH MULTIPLE BITS PER CELL - A dual-gate memory cell includes a first memory device and a second memory device each having a gate electrode and a charge storage gate dielectric layer. The first and second memory devices share a channel region and source and drain regions. Such a memory cell is read by sensing the charge in one of the dielectric layers by applying a first voltage in the gate electrode associated with the dielectric layer sensed, and applying a second voltage substantially different than the first voltage in the other dielectric layer.11-20-2008
20080290401NONVOLATILE SEMICONDUCTOR MEMORY DEVICES WITH CHARGE INJECTION CORNER - An erase method where a corner portion on which an electric field concentrates locally is provided on the memory gate electrode, and charges in the memory gate electrode are injected into a charge trap film in a gate dielectric with Fowler-Nordheim tunneling operation is used. Since current consumption at the time of erase can be reduced by the Fowler-Nordheim tunneling, a power supply circuit area of a memory module can be reduced. Since write disturb resistance can be improved, a memory array area can be reduced by adopting a simpler memory array configuration. Owing to both the effects, an area of the memory module can be largely reduced, so that manufacturing cost can be reduced. Further, since charge injection centers of write and erase coincide with each other, so that (program and erase) endurance is improved.11-27-2008
20080290398Nonvolatile charge trap memory device having <100> crystal plane channel orientation - A nonvolatile charge trap memory device and a method to form the same are described. The device includes a channel region having a channel length with <100> crystal plane orientation. The channel region is between a pair of source and drain regions and a gate stack is disposed above the channel region.11-27-2008
20080290397MEMORY CELL AND METHOD FOR MANUFACTURING AND OPERATING THE SAME - A memory cell is disposed on a substrate having plurality of isolation structures that define at least a fin structure in the substrate, wherein the surface of the fin structure is higher than that of the isolation structures. The memory cell includes a gate, a charge trapping structure, a protection layer and two source/drain regions. The gate is disposed on the substrate,and straddled the fin structure. The charge trapping structure is disposed between the gate and the fin structure. The protection layer is disposed between the upper portion of the fin structure and the gate separating the charge trapping structure. The source/drain regions are disposed in the fin structure at both sides of the gate.11-27-2008
20080303080BACK-SIDED TRAPPED NON-VOLATILE MEMORY DEVICE - Non-volatile memory devices and arrays are described that utilize back-side trapped floating node memory cells with band-gap engineered gate stacks with asymmetric tunnel barriers. Embodiments of the present invention allow for direct tunneling programming and efficient erase with electrons and holes, while maintaining high charge blocking barriers and deep carrier trapping sites for good charge retention and reduces the possibility of damage to the channel/insulator interface. The direct tunneling program and efficient erase capability reduces damage to the gate stack and the crystal lattice from high energy carriers, reducing write fatigue and leakage issues and enhancing device lifespan. Memory device embodiments of the present invention are presented that are arranged in NOR or NAND memory architecture arrays. Memory cell embodiments of the present invention also allow multiple levels of bit storage in a single memory cell, and allow for programming and erase with reduced voltages.12-11-2008
20100270609Modification of charge trap silicon nitride with oxygen plasma - A flash memory device comprises a substrate comprising silicon with a silicon dioxide layer thereon. A silicon-oxygen-nitrogen layer is on the silicon dioxide layer, and the silicon-oxygen-nitrogen layer comprises a shaped concentration level profile of oxygen through the thickness of the layer. A blocking dielectric layer is on the silicon-oxygen-nitrogen layer, and a gate electrode is on the blocking dielectric layer. Oxygen ions can be implanted into a silicon nitride layer to form the silicon-oxygen-nitrogen layer.10-28-2010
200802777181T MEMS scalable memory cell - This invention relates to the use of a gate dielectric placed under the mobile gate electrode of MOS transistor, without the need of a conductive floating gate. The invention exploits the electromechanical hysteretic behavior of the mobile gate when down contacting (pull-in) and up separating (pull-out) from the gate dielectric, based on the (non)equilibrium between electrical and elastic forces.11-13-2008
20080237695SEMICONDUCTOR MEMORY DEVICE - This disclosure concerns a memory comprising a charge trapping film; a gate insulating film; a back gate on the charge trapping film; a front gate on the gate insulating film; and a body region provided between a drain and a source, wherein the memory includes a first storage state for storing data depending on the number of majority carriers in the body region and a second storage state for storing data depending on the amount of charges in the charge trapping film, and the memory is shifted from the first storage state to the second storage state by converting the number of majority carriers in the body region into the amount of charges in the charge trapping film or from the second storage state to the first storage state by converting the amount of charges in the charge trapping film into the number of majority carriers in the body region.10-02-2008
20090315099METHOD OF MAKING FLASH MEMORY CELLS AND PERIPHERAL CIRCUITS HAVING STI, AND FLASH MEMORY DEVICES AND COMPUTER SYSTEMS HAVING THE SAME - An integrated circuit includes flash memory cells, and peripheral circuitry including low voltage transistors (LVT) and high voltage transistors (HVT). The integrated circuit includes a tunnel barrier layer comprising SiON, SiN or other high-k material. The tunnel barrier layer may comprise a part of the gate dielectric of the HVTs. The tunnel barrier layer may constitute the entire gate dielectric of the HVTs. The corresponding tunnel barrier layer may be formed between or upon shallow trench isolation (STIs). Therefore, the manufacturing efficiency of a driver chip IC may be increased.12-24-2009
20090315098SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING - A method for manufacturing a semiconductor device is disclosed. The method includes forming a shallow trench isolation (STI) region extending in a first direction on a semiconductor substrate, forming a mask layer extending in a second direction that intersects with the first direction on the semiconductor substrate and forming a trench on the semiconductor substrate by using the STI region and the mask layer as masks. In addition, the method includes forming a charge storage layer so as to cover the trench and forming a conductive layer on side surfaces of the trench and the mask layer. Word lines are formed from the conductive layer on side surfaces of the trench that oppose in the first direction by etching. The word lines are separated from each other and extend in the second direction.12-24-2009
20080272427Sonos Memory Device With Reduced Short-Channel Effects - A non-volatile memory device on a semiconductor substrate having a semiconductor surface layer (11-06-2008
20130119457MEMORY DEVICE, MANUFACTURING METHOD AND OPERATING METHOD OF THE SAME - A memory device, a manufacturing method and an operating method of the same are provided. The memory device includes a substrate, stacked structures, a channel element, a dielectric element, a source element, and a bit line. The stacked structures are disposed on the substrate. Each of the stacked structures includes a string selection line, a word line, a ground selection line and an insulating line. The string selection line, the word line and the ground selection line are separated from each other by the insulating line. The channel element is disposed between the stacked structures. The dielectric element is disposed between the channel element and the stacked structure. The source element is disposed between the upper surface of the substrate and the lower surface of the channel element. The bit line is disposed on the upper surface of the channel element.05-16-2013
20080265309Semiconductor memory device and manufacturing method thereof - After an ONO film in which a silicon nitride film (10-30-2008
20080265308METHODS OF FORMING FINFETS AND NONVOLATILE MEMORY DEVICES INCLUDING FINFETS - A FinFET includes a fin that is on a substrate and extends away from the substrate. A device isolation layer is disposed on the substrate on both sides of the fin. An insulating layer is between the fin and the substrate. The insulating layer is directly connected to the device isolation layer and has a different thickness than the device isolation layer. A gate electrode crosses over the fin. A gate insulating layer is between the gate electrode and the fin. Source and drain regions are on the fins and on opposite sides of the gate electrode. Related nonvolatile memory devices that include FinFETs and methods of making FinFETs and nonvolatile memory devices are also disclosed.10-30-2008
20080265307NON-VOLATILE SEMICONDUCTOR MEMORY DEVICES - A non-volatile memory device includes a tunneling insulating layer on a semiconductor substrate, a charge storage layer, a blocking insulating layer, and a gate electrode. The charge storage layer is on the tunnel insulating layer and has a smaller band gap than the tunnel insulating layer and has a greater band gap than the semiconductor substrate. The blocking insulating layer is on the charge storage layer and has a greater band gap than the charge storage layer and has a smaller band gap than the tunnel insulating layer. The gate electrode is on the blocking insulating layer.10-30-2008
20100140684NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - On a silicon substrate is formed a stacked body by alternately stacking a plurality of silicon oxide films and silicon films, a trench is formed in the stacked body, an alumina film, a silicon nitride film and a silicon oxide film are formed in this order on an inner surface of the trench, and a channel silicon crystalline film is formed on the silicon oxide film. Next, a silicon oxide layer is formed at an interface between the silicon oxide film and the channel silicon crystalline film by performing thermal treatment in an oxygen gas atmosphere.06-10-2010
20090179254Memory Device With Improved Performance And Method Of Manufacturing Such A Memory Device - Non-volatile memory device on a semiconductor substrate, comprising a semiconductor base layer, a charge storage layer stack, and a control gate; the base layer comprising source and drain regions and a current-carrying channel region being positioned in between the source and drain regions; the charge storage layer stack comprising a first insulating layer, a charge trapping layer and a second insulating layer, the first insulating layer being positioned above the current-carrying channel region, the charge trapping layer being above the first insulating layer and the second insulating layer being above the charge trapping layer; the control gate being positioned above the charge storage layer stack; the charge storage layer stack being arranged for trapping charge in the charge trapping layer by direct tunneling of charge carriers from the current-carrying channel region through the first insulating layer, wherein the current-carrying channel region is a p-type channel for p-type charge carriers, and the material of at least one of the current-carrying channel region and/or the source and drain regions is in an elastically strained state.07-16-2009
20090179253Oxide-nitride-oxide stack having multiple oxynitride layers - A semiconductor device including an oxide-nitride-oxide (ONO) structure having a multi-layer charge storing layer and methods of forming the same are provided. Generally, the method involves: (i) forming a first oxide layer of the ONO structure; (ii) forming a multi-layer charge storing layer comprising nitride on a surface of the first oxide layer; and (iii) forming a second oxide layer of the ONO structure on a surface of the multi-layer charge storing layer. Preferably, the charge storing layer comprises at least two silicon oxynitride layers having differing stoichiometric compositions of Oxygen, Nitrogen and/or Silicon. More preferably, the ONO structure is part of a silicon-oxide-nitride-oxide-silicon (SONOS) structure and the semiconductor device is a SONOS memory transistor. Other embodiments are also disclosed.07-16-2009
20100270608Integrated Circuits And Fabrication Using Sidewall Nitridation Processes - Semiconductor devices are provided with encapsulating films for protection of sidewall features during fabrication processes, such as etching to form isolation regions. In a non-volatile flash memory, for example, a trench isolation process is divided into segments to incorporate an encapsulating film along the sidewalls of charge storage material. A pattern is formed over the layer stack followed by etching the charge storage material to form strips elongated in the column direction across the substrate, with a layer of tunnel dielectric material therebetween. Before etching the substrate, an encapsulating film is formed along the sidewalls of the strips of charge storage material. The encapsulating film can protect the sidewalls of the charge storage material during subsequent cleaning, oxidation and etch processes. In another example, the encapsulating film is simultaneously formed while etching to form strips of charge storage material and the isolation trenches.10-28-2010
20090140323Integrated Circuit having Memory Cell Array including Barriers, and Method of Manufacturing Same - An integrated circuit device (e.g., a logic device or a memory device) having (i) a memory cell array which includes a plurality of memory cells (for example, memory cells having electrically floating body transistors) arranged in a matrix of rows and columns, wherein each memory cell includes at least one transistor having a gate, gate dielectric and first, second and body regions, wherein: (i) the body region of each transistor is electrically floating and (ii) the transistors of adjacent memory cells include a layout that provides a common first region and/or a common second region. Each common first region and/or second regions of transistors of adjacent memory cells includes a barrier disposed therein and/or therebetween, wherein each barrier provides a discontinuity in the common regions and/or includes one or more electrical characteristics that are different from one or more corresponding electrical characteristics of the common regions. A plurality of electrical contacts, wherein an electrical contact is disposed on a (i) common first region and/or second region and (ii) barrier(s) associated therewith which is disposed therein and/or therebetween. Also disclosed are inventive methods of manufacturing such integrated circuit devices.06-04-2009
20090140325FORMING METAL-SEMICONDUCTOR FILMS HAVING DIFFERENT THICKNESSES WITHIN DIFFERENT REGIONS OF AN ELECTRONIC DEVICE - A method of forming an electronic device is provided that includes selectively implanting ions into a workpiece, wherein ions are implanted into a first region of the workpiece that includes a semiconductor material, while substantially none of the ions are implanted into a second region of the workpiece that also includes a semiconductor material. The method further includes depositing a metal-containing film over the first region and the second region after selectively implanting, and then reacting the metal-containing film with the semiconductor material to form a first metal-semiconductor film within the first region and a second metal-semiconductor film within the second region. The first metal-semiconductor film has a first thickness and the second metal-semiconductor film has a second thickness that is different from the first thickness.06-04-2009
20090278193NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A nonvolatile semiconductor memory device includes a first stack unit with a first selection transistor and a second selection transistor formed on a semiconductor substrate and a second stack unit with first insulating layers and first conductive layers stacked alternately on the upper surface of the first stack unit. The second stack unit includes a second insulating layer formed in contact with side walls of the first insulating layer and the first conductive layer, a charge storage layer formed in contact with the second insulating layer for storing electrical charges, a third insulating layer formed in contact with the charge storage layer, and a first semiconductor layer formed in contact with the third insulating layer so as to extend in a stacking direction, with one end connected to one diffusion layer of the first selection transistor and the other end connected to a diffusion layer of the second selection transistor.11-12-2009
20100200907Semiconductor Integrated Circuit Device and Method of Fabricating the Same - A semiconductor integrated circuit device is provided. The semiconductor integrated circuit device includes a plurality of isolation regions which are formed within a semiconductor substrate and define active regions. A tunnel layer and a trap seed layer are formed in each of the active regions and are sequentially stacked between the isolation regions. A trap layer is formed on the trap seed layer and protrudes further than a top surface of each of the isolation regions. A blocking layer is formed on the trap layer. A gate electrode is formed on the blocking layer.08-12-2010
20100200906NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - A nonvolatile semiconductor memory device includes: a semiconductor substrate; a multilayer structure; a semiconductor pillar; a third insulating film; and a fourth insulating film layer. The a multilayer structure is provided on the semiconductor substrate and including a plurality of constituent multilayer bodies stacked in a first direction perpendicular to a major surface of the semiconductor substrate. Each of the plurality of constituent multilayer bodies includes an electrode film provided parallel to the major surface, a first insulating film, a charge storage layer provided between the electrode film and the first insulating film, and a second insulating film provided between the charge storage layer and the electrode film. The semiconductor pillar penetrates through the multilayer structure in the first direction. The third insulating film is provided between the semiconductor pillar and the electrode film. The fourth insulating film is provided between the semiconductor pillar and the charge storage layer.08-12-2010
20100200905NAND MEMORY CELLS AND MANUFACTURING METHOD THEREOF - A method for manufacturing NAND memory cells includes providing a substrate having a first doped region formed therein; sequentially forming a first dielectric layer, a storage layer and a patterned hard mask on the substrate; forming a STI defining a plurality of recesses in the substrate through the patterned hard mask; sequentially forming a second dielectric layer and a first conductive layer filling the recesses on the substrate; and performing a planarization process to remove a portion of the first conductive layer and the second dielectric layer to form a plurality of self-aligned islanding gate structures.08-12-2010
20100200904GATE FRINGING EFFECT BASED CHANNEL FORMATION FOR SEMICONDUCTOR DEVICE - Methods and structures for forming semiconductor channels based on gate fringing effect are disclosed. In one embodiment, a NAND flash memory device comprises multiple NAND strings of memory transistors. Each memory transistor includes a charge trapping layer and a gate electrode formed on the charge trapping layer. The memory transistors are formed close to each other to form a channel between an adjacent pair of the memory transistors based on a gate fringing effect associated with the adjacent pair of the memory transistors.08-12-2010
20090184363SILICON ON INSULATOR DEVICE AND METHOD FOR FABRICATING THE SAME - An SOI device includes an SOI substrate having a structure in which a first buried oxide layer and a silicon layer are stacked in turn over a semiconductor substrate. A gate is formed over the silicon layer of the SOI substrate. A second buried oxide layer is formed at both sides of the gate in a lower portion of the silicon layer so that a lower end portion of the second buried oxide layer is in contact with the first buried oxide layer. A junction region is then formed in the portion of the silicon layer above the second buried oxide layer so that the lower end portion of the junction region is in contact with the second buried oxide layer.07-23-2009
20090184361LATERAL CHARGE STORAGE REGION FORMATION FOR SEMICONDUCTOR WORDLINE - Devices and methods for forming charge storage regions are disclosed. In one embodiment, a semiconductor device comprises a semiconductor layer having a trench, charge storage layers formed at both side surfaces of the trench, a wordline buried in the trench in contact with the charge storage layers, and source-drain regions formed in the semiconductor layer at both sides of the trench.07-23-2009
20090140322Semiconductor Memory Device and Method of Manufacturing the Same - A first insulation film (silicon dioxide film) and a second insulation film (aluminum oxide film) are laminated on a surface of a silicon substrate in this order to form a gate insulation film. At least one element (aluminum) of elements, which constitutes the second insulation film but is different from elements commonly contained in the whole area of the first insulation film, is caused to be contained in a part of the first insulation film, whereby a charge trapping site region is formed in the first insulation film.06-04-2009
20090140321SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device and a method of fabricating the same are provided. First, a first oxide layer and a nitride layer are formed on a base having a first region and a second region. Next, the nitride layer is oxidized. A part of nitride in the nitride layer moves to the first oxide layer and the base. An upper portion of the nitride layer is converted to an upper oxide layer. Then, the upper oxide layer, the nitride layer and the first oxide layer in the second region are removed. Thereon, a second oxide layer is grown on the base in the second region. Nitride in the second region moves to the second oxide layer.06-04-2009
20090140324METHOD OF MANUFACTURING FLASH MEMORY DEVICE - A method of manufacturing a flash memory device and a flash memory device in which a tunnel oxide layer and a first polysilicon pattern are formed on and/or over a semiconductor substrate. A second polysilicon pattern and a third polysilicon pattern are formed on and/or over a sidewall of the first polysilicon pattern and a dielectric layer and a polysilicon layer formed on and/or over the first, second and third polysilicon patterns. An etching process is performed to form a tunnel oxide layer pattern, a dielectric pattern, and a fourth polysilicon pattern.06-04-2009
20120139027VERTICAL STRUCTURE NON-VOLATILE MEMORY DEVICES INCLUDING IMPURITY PROVIDING LAYER - A vertical structure non-volatile memory device includes a channel region that vertically extends on a substrate. A memory cell string vertically extends on the substrate along a first wall of the channel regions, and includes at least one selection transistor and at least one memory cell. An impurity providing layer is disposed on a second wall of the channel region and includes impurities.06-07-2012
20120068256NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - An dielectric film is formed above the semiconductor substrate. A first conductive layer is formed in the dielectric film and extending in a first direction. The first conductive layer is connected to a first select transistor. A second conductive layer formed in the dielectric film and extending in the first direction. The second conductive layer is connected to a second select transistor. A semiconductor layer is connected to both the first and second conductive layers and functioning as a channel layer of a memory transistor. A gate-insulating film is formed on the semiconductor layer. The gate-insulating film includes a charge accumulation film as a portion thereof. A third conductive layer is surrounded by the gate-insulating film.03-22-2012
20120068255THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES - Three-dimensional (3D) nonvolatile memory devices include a substrate having a well region of second conductivity type (e.g., P-type) therein and a common source region of first conductivity type (e.g., N-type) on the well region. A recess is provided, which extends partially (or completely) through the common source region. A vertical stack of nonvolatile memory cells are provided on the substrate. This vertical stack of nonvolatile memory cells includes a vertical stack of spaced-apart gate electrodes and a vertical active region, which extends on sidewalls of the vertical stack of spaced-apart gate electrodes and on a sidewall of the recess. Gate dielectric layers are provided, which extend between respective ones of the vertical stack of spaced-apart gate electrodes and the vertical active region. The gate dielectric layers may include a composite of a tunnel insulating layer, a charge storage layer, a relatively high bandgap barrier dielectric layer and a blocking insulating layer having a relatively high dielectric strength.03-22-2012
20120068253NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a nonvolatile semiconductor memory device includes a memory region and a non-memory region. The memory region includes a stacked structural body, a semiconductor pillar, a memory layer, an inner insulating film and an outer insulating film. The stacked structural body includes a plurality of electrode films stacked alternately along a first direction with a plurality of inter-electrode insulating films. The semiconductor pillar pierces the stacked structural body in the first direction. The memory layer is provided between the semiconductor pillar and each of the plurality of electrode films. The inner insulating film is provided between the memory layer and the semiconductor pillar. The outer insulating film is provided between the memory layer and each of the plurality of electrode films. The non-memory region is provided with the memory region along a second direction orthogonal to the first direction. The non-memory region includes an insulating part.03-22-2012
20090206386DECODING SYSTEM CAPABLE OF CHARGING PROTECTION FOR FLASH MEMORY DEVICES - One embodiment of the present invention relates to a flash memory array. The flash memory array comprises at least two word lines of gate electrode material. At least one of the word lines is connected through a first metal level to a discharge circuit, while other word line(s) may connect to a discharge circuit through a first and second metal level. The memory array further comprises a shorting path between the word lines of the memory array. The shorting path is a high resistance layer of undoped gate electrode material. The resistance value of the gate electrode material is such that the word lines can be used to read, write, or erase without effecting each other, but that during the formation of a first metal level, as charges will build up on a first word line which requires a second metal level to connect to its discharge junction circuit, it will short the first word line to an adjacent second word line that has a connection to its junction circuit on the first metal level. Other methods and circuits are also disclosed.08-20-2009
20090146206NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - A non-volatile semiconductor storage device has a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series. Each of the memory strings includes: a first columnar semiconductor layer extending in a direction perpendicular to a substrate and having a first hollow extending downward from its upper end; a first insulation layer formed in contact with the outer wall of the first columnar semiconductor layer; a second insulation layer formed on the inner wall of the first columnar semiconductor layer so as to leave the first hollow; and a plurality of first conductive layers formed to sandwich the first insulation layer with the first columnar semiconductor layer and functioning as control electrodes of the memory cells.06-11-2009
20090321814SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor memory device includes, in a memory region, a plurality of bit line diffusion layers, a plurality of word lines, and a plurality of memory elements composed of a bit line diffusion layer pair, a gate insulating film, and a gate electrode. The plurality of bit line diffusion layers are divided into plural in respective columns, and are connected electrically to each other through bit line contact diffusion layers. The width of sidewall insulating films on the sides of the bit line contact diffusion layers formed at the word lines arranged adjacent to the bit line contact diffusion layers is smaller than that of the sidewall insulating films formed on the opposite sides of the bit line contact diffusion layers.12-31-2009
20110220988METHOD FOR MANUFACTURING NAND MEMORY CELLS - A method for manufacturing NAND memory cells includes providing a substrate having a first doped region formed therein; forming a first dielectric layer, a storage layer and a patterned hard mask on the substrate; forming a STI in the substrate through the patterned hard mask and removing the patterned hard mask to define a plurality of recesses; forming a second dielectric layer and a first conductive layer filling the recesses on the substrate; and performing a planarization process to remove a portion of the first conductive layer and the second dielectric layer to form a plurality of self-aligned islanding gate structures.09-15-2011
20090050953NON-VOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A non-volatile memory device including a substrate, an insulating layer, a charge storage layer, a multi-layer tunneling dielectric structure and a gate is provided. The substrate has a channel region. The insulating layer is disposed on the channel region. The charge storage layer is disposed on the insulating layer. The multi-layer tunneling dielectric structure is disposed on the charge storage layer. The gate is disposed on the multi-layer tunneling dielectric structure and the charge carriers are injected from the gate.02-26-2009
20090050956SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - In a memory cell including an nMIS for memory formed on the sides of an nMIS for select and an nMIS for select via dielectric films and a charge storage layer, the thickness of a gate dielectric under the gate longitudinal direction end of a select gate electrode is formed thicker than that of the gate dielectric under the gate longitudinal direction center and the thickness of the lower layer dielectric film that is positioned between the select gate electrode and the charge storage layer and is nearest to a semiconductor substrate is formed 1.5 times or below of the thickness of the lower layer dielectric film positioned between the semiconductor substrate and the charge storage layer.02-26-2009
20090200600Nonvolatile semiconductor memory device and method of manufacturing the same - A nonvolatile semiconductor memory device has: a semiconductor substrate; a control gate and a floating gate that are formed side by side on a gate insulating film on a channel region in the semiconductor substrate; and an erase gate facing an upper surface of the floating gate and totally located above the upper surface of the floating gate. The upper surface of the floating gate includes a first side and a second side that face each other. A bottom surface of the erase gate is closer to the first side and the second side than the upper surface between the first side and the second side.08-13-2009
20090085096Nonvolatile Memory Devices and Methods of Forming the Same - Provided are nonvolatile memory devices and methods of forming nonvolatile memory devices. Nonvolatile memory devices include a device isolation layer that defines an active region in a substrate. Nonvolatile memory devices further include a first insulating layer, a nonconductive charge storage pattern, a second insulating layer and a control gate line that are sequentially disposed on the active region. The charge storage pattern includes a horizontal portion and a protrusion disposed on an upper portion of an edge of the horizontal portion.04-02-2009
20110140192METHOD FOR MANUFACTURING TWIN BIT STRUCTURE CELL WITH FLOATING POLYSILICON LAYER - A method for forming a twin-bit cell structure is provided. The method includes providing a semiconductor substrate including a surface region. A gate dielectric layer is formed overlying the surface region. The method forms a polysilicon gate structure overlying the gate dielectric layer. In a specific embodiment, the method subjects the gate polysilicon structure to an oxidizing environment to cause formation of a first silicon oxide layer overlying the gate polysilicon structure. Preferably, an undercut region is allowed to be formed underneath the gate polysilicon structure. The method includes forming an undoped polysilicon material overlying the polysilicon gate structure including the undercut region and the gate dielectric layer. The undoped polysilicon material is subjected to a selective etching process to form an insert region in a portion of the undercut region while the insert region remains filled with the undoped polysilicon material.06-16-2011
20110140191METHOD FOR MANUFACTURING TWIN BIT STRUCTURE CELL WITH SILICON NITRIDE LAYER - A method for manufacturing a twin bit cell structure with a silicon nitride material includes forming a gate dielectric layer overlying a semiconductor substrate and a polysilicon gate structure overlying the gate dielectric layer. An undercut region is formed in each side of the gate dielectric layer underneath the polysilicon gate structure. Thereafter, an oxidation process is performed to form a first silicon oxide layer on a peripheral surface of the polysilicon gate structure and a second silicon oxide layer on an exposed surface of the semiconductor substrate. Then, a silicon nitride material is deposited over the first and second silicon oxide layers including the undercut region and the gate dielectric layer. The silicon nitride material is selectively etched to form an insert region in a portion of the undercut region. A sidewall spacer is formed to isolate and protect the exposed silicon nitride material and the polysilicon gate structure.06-16-2011
20110140190METHOD FOR MANUFACTURING TWIN BIT STRUCTURE CELL WITH ALUMINUM OXIDE LAYER - A method for manufacturing a twin bit cell structure with an aluminum oxide material includes forming a gate dielectric layer overlying a semiconductor substrate and a polysilicon gate structure overlying the gate dielectric layer. An undercut region is formed in each side of the gate dielectric layer underneath the polysilicon gate structure. Thereafter, an oxidation process is performed to form a first silicon oxide layer on a peripheral surface of the polysilicon gate structure and a second silicon oxide layer on an exposed surface of the semiconductor substrate. Then, an aluminum oxide material is deposited over the first and second silicon oxide layers including the undercut region and the gate dielectric layer. The aluminum oxide material is selectively etched to form an insert region in a portion of the undercut region. A sidewall spacer is formed to isolate and protect the exposed aluminum oxide material and the polysilicon gate structure.06-16-2011
20090101963SPLIT CHARGE STORAGE NODE INNER SPACER PROCESS - Methods of forming a memory cell containing two split sub-lithographic charge storage nodes on a semiconductor substrate are provided. The methods can involve forming two split sub-lithographic charge storage nodes by using spacer formation techniques. By removing exposed portions of a first poly layer while leaving portions of the first poly layer protected by the spacers, the method can provide two split sub-lithographic first poly gates. Further, by removing exposed portions of a charge storage layer while leaving portions of the charge storage layer protected by the two split sub-lithographic first poly gates, the method can provide two split, narrow portions of the charge storage layer, which subsequently form two split sub-lithographic charge storage nodes.04-23-2009
20090014781Nonvolatile memory devices and methods for fabricating nonvolatile memory devices - A nonvolatile memory device may include: a tunnel insulating layer on a semiconductor substrate; a charge storage layer on the tunnel insulating layer; a blocking insulating layer on the charge storage layer; and a control gate electrode on the blocking insulating layer. The tunnel insulating layer may include a first tunnel insulating layer and a second tunnel insulating layer. The first tunnel insulating layer and the second tunnel insulating layer may be sequentially stacked on the semiconductor substrate. The second tunnel insulating layer may have a larger band gap than the first tunnel insulating layer. A method for fabricating a nonvolatile memory device may include: forming a tunnel insulating layer on a semiconductor substrate; forming a charge storage layer on the tunnel insulating layer; forming a blocking insulating layer on the charge storage layer; and forming a control gate electrode on the blocking insulating layer.01-15-2009
20120104485Nonvolatile Memory Devices And Methods Of Manufacturing The Same - A method of manufacturing a nonvolatile memory device includes forming a tunnel dielectric layer, a charge storage layer, and a hard mask layer on a substrate in sequential order. Active portions are defined by forming trenches in the substrate. A tunnel dielectric pattern, a preliminary charge storage pattern, and a hard mask pattern are formed on each of the active portions in sequential order by sequentially patterning the hard mask layer, the charge storage layer, the tunnel dielectric layer, and the substrate. A capping pattern is formed covering an upper surface of the trenches such that a first void remains in a lower portion of the trenches, the capping pattern including etch particles formed by etching the hard mask pattern through a sputtering etch process.05-03-2012
20080296659Nand Flash Memory Array Having Pillar Structure and Fabricating Method of the Same - The present invention relates to a NAND flash memory array having vertical channels and sidewall gate structure and a fabricating method of the same. A NAND flash memory array of the present invention has insulator strip structure and one or more semiconductor strips are next to the both sides of the insulator strip. A NAND flash memory array of the present invention allows for an improvement of the integrity by decreasing the memory cell area by half and less, and solves the problems of the conventional three-dimensional structure regarding isolation between not only channels but also source/drain regions at the bottom of trenches. A method for fabricating the NAND flash memory array having a pillar structure, which uses the conventional CMOS process and an etching process with minimum masks, enables to cut down costs.12-04-2008
20090200599U-SHAPED SONOS MEMORY HAVING AN ELEVATED SOURCE AND DRAIN - A semiconductor device and a method for manufacturing thereof are provided. The semiconductor device includes two epitaxial semiconductor layers formed on a semiconductor substrate, bit lines formed on upper portions of the two epitaxial semiconductor layers, and a charge storage layer formed on the semiconductor substrate between the two epitaxial semiconductor layers.08-13-2009
20120126308NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A non-volatile memory device includes a plurality of memory cells stacked along a channel protruded from a substrate, a first select transistor connected to one end of the plurality of memory cells, a first interlayer dielectric layer for being coupled between a source line and the first select transistor, and a second interlayer dielectric layer disposed between the first select transistor and the one end of the plurality of memory cells, and configured to include a first recess region.05-24-2012
20090230457Semiconductor device and method of forming the same - A semiconductor device includes a plurality of transistors disposed on a semiconductor substrate, a device isolation layer disposed around the transistors, a guard ring disposed to surround the device isolation layer and the transistors, and a guard region disposed between adjacent transistors.09-17-2009
20090230460NONVOLATILE SEMICONDUCTOR MEMORY - A nonvolatile semiconductor memory of an aspect of the present invention including a memory cell which has a first gate insulating film, a charge storage layer, a block insulating film, and a first gate electrode on the block insulating film, a first transistor which has a second gate insulating film and a second gate electrode, a second transistor which has a third gate insulating film and a third gate electrode, and a third transistor which has a fourth gate insulating film and a fourth gate electrode and which is different in drive voltage from the second transistor, wherein the second gate insulating film includes an insulating film of the same configuration as the block insulating film, the second gate electrode has the same structure as the first gate electrode, and the third and fourth gate electrodes partly include conductive layers of the same configuration as the first gate electrode.09-17-2009
20090230459NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A non-volatile semiconductor memory device includes a memory string which is electrically rewritable and includes a plurality of memory cells connected in series. The memory string includes a plurality of first conductive layers which are extended parallel to a substrate and laminated; a first semiconductor layer which is formed so as to pass through the plurality of the first conductive layers; and an electric charge accumulation layer which is formed between the first conductive layer and the first semiconductor layer and is configured so as to be able to accumulate electric charge. The first conductive layer is configured by material smaller in work function than P09-17-2009
20090230458NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - A non-volatile semiconductor storage device has a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series. Each of the memory strings includes: a columnar semiconductor layer extending in a direction perpendicular to a substrate; a plurality of conductive layers formed at a sidewall of the columnar semiconductor layer via memory layers; and interlayer insulation layers formed above of below the conductive layers. A sidewall of the conductive layers facing the columnar semiconductor layer is formed to be inclined such that the distance thereof from a central axis of the columnar semiconductor layer becomes larger at lower position thereof than at upper position thereof. While, a sidewall of the interlayer insulation layers facing the columnar semiconductor layer is formed to be inclined such that the distance thereof from a central axis of the columnar semiconductor layer becomes smaller at lower position thereof than at upper position thereof.09-17-2009
20090108331Memory and manufacturing method thereof - A memory having isolated dual memory cells is provided. A first isolation wall and a second isolation wall are separately disposed between a source and a drain on a substrate. An isolation bottom layer and a polysilicon layer are orderly disposed on the substrate between the first and the second isolation walls. A first charge storage structure and a first gate are orderly disposed on the substrate between the first isolation wall and the source. A second charge storage structure and a second gate are orderly disposed on the substrate between the second isolation wall and the drain. A word line disposed on the polysilicon layer, the first gate, the second gate, the first isolation wall and the second isolation wall is electrically connected to the first gate, the second gate and the polysilicon layer.04-30-2009
20090108330SPLIT CHARGE STORAGE NODE OUTER SPACER PROCESS - Memory cells containing two split sub-lithographic charge storage nodes on a semiconductor substrate and methods for making the memory cells are provided. The methods can involve forming two split sub-lithographic charge storage nodes by using spacer formation techniques. By removing an exposed portion of a fist poly layer between sloping side surfaces or outer surfaces of spacers while leaving portions of the first poly layer protected by the spacers, the method can provide two split sub-lithographic first poly gates. Further, by removing an exposed portion of a charge storage layer between sloping side surfaces or outer surfaces of spacers, the method can provide two split, narrow portions of the charge storage layer, which subsequently form two split sub-lithographic charge storage nodes.04-30-2009
20090194809SEMICONDUCTOR MEMORY AND METHOD FOR MANUFACTURING THE SAME - A semiconductor memory in which a gate insulating film (tunnel insulating film) in a memory cell provides higher operational reliability. The semiconductor memory includes an insulating film 08-06-2009
20090212352SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor memory device has a semiconductor substrate, a plurality of word lines formed at predetermined intervals on the semiconductor substrate, each word line having a gate insulating film, a charge storage layer, a first insulating film, and a controlling gate electrode which are stacked in order, and including a metal oxide layer above the level of the gate insulating film, a second insulating film covering a side of the word line and a surface of the semiconductor substrate between the word lines, and having a film thickness of 15 nm or less, and a third insulating film formed between the word lines adjacent to each other such that a region below the level of the metal oxide layer has a cavity.08-27-2009
20090212347SONOS MEMORY DEVICE WITH OPTIMIZED SHALLOW TRENCH ISOLATION - Method of manufacturing a non-volatile memory device on a semiconductor substrate in a memory area, said non-volatile memory device comprising a cell stack of a first semiconductor layer, a charge trapping layer and an electrically conductive layer, the charge trapping layer being the intermediate layer between the first semiconductor layer and the electrically conductive layer, the charge trapping layer comprising at least a first insulating layer; the method comprising:—providing the substrate having the first semiconductor layer;—depositing the charge trapping layer;—depositing the electrically conductive layer; —patterning the cell stack to form at least two non-volatile memory cells, and—creating a shallow trench isolation in between said at least two non-volatile memory cells.08-27-2009
20090242967NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - A non-volatile semiconductor storage device has a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series. Each of the memory strings comprises: a first columnar semiconductor layer extending in a vertical direction to a substrate; a charge accumulation layer formed around the first columnar semiconductor layer via a first insulation layer; and a first conductive layer formed around the charge accumulation layer via a second insulation layer. Each of the first conductive layers is formed to expand in a two-dimensional manner, and air gaps are formed between the first conductive layers located there above and there below.10-01-2009
20090212351ELECTRON BLOCKING LAYERS FOR ELECTRONIC DEVICES - Methods and apparatuses for electronic devices such as non-volatile memory devices are described. The memory devices include a multi-layer control dielectric, such as a double or triple layer. The multi-layer control dielectric includes a combination of high-k dielectric materials such as aluminum oxide, hafnium oxide, and/or hybrid films of hafnium aluminum oxide. The multi-layer control dielectric provides enhanced characteristics, including increased charge retention, enhanced memory program/erase window, improved reliability and stability, with feasibility for single or multi state (e.g., two, three or four bit) operation.08-27-2009
20090256192NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - In a nonvolatile semiconductor memory device where a tunnel insulating film, a charge storage layer, a blocking insulating film, and a control gate are stacked one on top of another on a semiconductor substrate, with an element isolation insulating film buried between adjacent cells, a barrier layer composed of at least one of a silicon nitride film, a silicon oxynitride film, and a silicon oxide film which has a higher density than that of the element isolation insulating film is provided at the interface between the element isolation insulating film and the blocking insulating film or between the element isolation film and the control gate.10-15-2009
20090096017STACKED THIN FILM TRANSISTOR, NON-VOLATILE MEMORY DEVICES AND METHODS FOR FABRICATING THE SAME - A manufacturing method for stacked, non-volatile memory devices provides a plurality of bitline layers and wordline layers with charge trapping structures. The bitline layers have a plurality of bitlines formed on an insulating layer, such as silicon on insulator technologies. The wordline layers are patterned with respective pluralities of wordlines and charge trapping structures orthogonal to the bitlines.04-16-2009
20100264480USE OF A POLYMER SPACER AND SI TRENCH IN A BITLINE JUNCTION OF A FLASH MEMORY CELL TO IMPROVE TPD CHARACTERISTICS - Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The bit line dielectrics can extend into the semiconductor. The memory cell contains one or more charge storage nodes, a first poly gate, a pair of first bit lines, and a pair of second bit lines. The second bit line can be formed at a higher energy level, a higher concentration of dopants, or a combination thereof compared to an energy level and a concentration of dopants of the first bit line.10-21-2010
20090242969SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor storage device including a semiconductor substrate including an upper surface having a plurality of trenches formed into the upper surface; a plurality of element isolation insulating films filled in each of the trenches so as to protrude upward from the upper surface of the semiconductor substrate, the element isolation insulating films containing an oxide material; a tunnel insulating film formed on the semiconductor substrate situated between the element isolation insulating films; a charge storing layer comprising a first nitride film and being formed on the tunnel insulating film; a block film formed across an upper surface of the charge storing layer and an upper surface of the element isolation insulating film to prevent charge transfer; a gate electrode formed on the block film; and a barrier layer containing a second nitride film formed between the element isolation insulating film and the block film.10-01-2009
20090242965MEMORY CELL DEVICE HAVING VERTICAL CHANNEL AND DOUBLE GATE STRUCTURE - A memory cell device having a vertical channel and a double gate structure is provided. More specifically, a memory cell device having a vertical channel and a double gate structure is characterized by having a pillar active region with a predetermined height, which is including a first semiconductor layer forming a first source/drain region, a second semiconductor layer being placed under the first semiconductor layer with a predetermined distance and forming a second source/drain region, and a third semiconductor layer forming a body region and a channel region between the first semiconductor layer and the second semiconductor layer, and therefore, there is no need for unnecessary contacts when it is used as a unit cell for any type of memory array, not to speak of NOR type flash memory array. And the present invention makes to program/erase more effectively and increase the read speed and the amount of sensing current.10-01-2009
20090242963SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - In a semiconductor device, the side walls are made of SiO10-01-2009
20090242961RECESSED CHANNEL SELECT GATE FOR A MEMORY DEVICE - A memory device comprising one or more recessed channel select gates and at least one charge trapping layer.10-01-2009
20090242968NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - In a nonvolatile semiconductor memory device, a stacked body is formed by alternately stacking dielectric films and conductive films on a silicon substrate and a plurality of through holes extending in the stacking direction are formed in a matrix configuration. A shunt interconnect and a bit interconnect are provided above the stacked body. Conductor pillars are buried inside the through holes arranged in a line immediately below the shunt interconnect out of the plurality of through holes, and semiconductor pillars are buried inside the remaining through holes. The conductive pillars are formed from a metal, or low resistance silicon. Its upper end portion is connected to the shunt interconnect and its lower end portion is connected to a cell source formed in an upper layer portion of the silicon substrate.10-01-2009
20090250746NOR-Type Flash Memory Cell Array and Method for Manufacturing the Same - Disclosed is a non-volatile (e.g., NOR type flash) memory cell array and a method for manufacturing the same. The memory cell array includes a plurality of isolation layers on a semiconductor substrate, parallel to a bit line and defining an active device area, a plurality of common source areas in the semiconductor substrate, separated from each other by the isolation layers such that the common source areas connect memory cells adjacent to each other in a bit line direction, a common source line on the semiconductor substrate, connected to each source area and extending in a word-line direction, an insulating spacer along a first sidewall of the common source line, a gate at a second sidewall of the insulating spacer including a tunnel oxide layer, a first electrode, an inter-electrode dielectric layer, and a second electrode, and a drain area in the semiconductor substrate on an opposite side of the gate from the common source area.10-08-2009
20090250745Memory devices and methods of forming and operating the same - A memory device, including a first ground selection transistor, a first string selection transistor, and first memory cell transistors disposed in series between the first ground selection transistor and the first string selection transistor, wherein the first ground selection transistor and the first memory cell transistors have a same structure. A method of programming the memory device may include programming the ground selection transistor before programming the memory cell.10-08-2009
20090250744Semiconductor memory device and manufacturing method therefor - A semiconductor memory device has a cover film (10-08-2009
20090256193SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - In a semiconductor device which includes a split-gate type memory cell having a control gate and a memory gate, a low withstand voltage MISFET and a high withstand voltage MISFET, variations of the threshold voltage of the memory cell are suppressed. A gate insulating film of a control gate is thinner than a gate insulating film of a high withstand voltage MISFET, the control gate is thicker than a gate electrode 10-15-2009
20100148239GATE STRUCTURE OF SEMICONDUCTOR DEVICE AND METHODS OF FORMING WORD LINE STRUCTURE AND MEMORY - A gate structure for a semiconductor device is provided. The gate structure includes a conductive structure. The conductive structure insulatively disposed over a substrate includes a middle portion and two spacer portions. The middle portion has a first surface and two second surfaces. The first surface is between the two second surfaces. The two spacer portions are respectively connected to the two second surfaces of the middle portion. A width of each of the two spacer portions gradually increases from top to bottom.06-17-2010
20090261404Non-volatile Memory Device - A non-volatile memory device having a SONOS structure and a manufacturing method thereof, where a conductive layer is formed between a charge trap layer and a blocking insulation layer of the SONOS structure. Therefore, when a voltage is applied to a gate, the conductive layer undergoes voltage distributions. Accordingly, a desired voltage can be applied to the blocking insulation layer, the charge trap layer and the tunnel insulating layer by controlling the effective oxide thickness (EOT) of the blocking insulation layer and the EOT of the charge trap layer and the tunnel insulating layer. It is therefore possible to improve the erase speed of a cell.10-22-2009
20100264481Nonvolatile Memory Devices and Related Methods - Nonvolatile memory devices and methods of fabricating the same are provided. A semiconductor substrate is provided having a cell field region and a high-voltage field region. Device isolation films are provided on the substrate. The device isolation films define active regions of the substrate. A cell gate-insulation film and a cell gate-conductive film are provided on the cell field region of the substrate including the device isolation films. A high-voltage gate-insulation film and a high-voltage gate-conductive film are provided on the high-voltage field region of the substrate including the device isolation films. The device isolation film on the high-voltage field region of the substrate is at least partially recessed to provide a groove therein.10-21-2010
20100264479SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - Provided is a semiconductor device having, over a semiconductor substrate, a control gate electrode and a memory gate electrode which are adjacent to each other and constitute a nonvolatile memory. The height of the memory gate electrode is lower than the height of the control gate electrode. A metal silicide film is formed over the upper surface of the control gate electrode, but not formed over the upper surface of the memory gate electrode. The memory gate electrode has, over the upper surface thereof, a sidewall insulating film made of silicon oxide. This sidewall insulating film is formed in the same step as that for the formation of respective sidewall insulating films over the sidewalls of the memory gate electrode and the control gate electrode. The present invention makes it possible to improve the production yield and performance of the semiconductor device having a nonvolatile memory.10-21-2010
20100155822SEMICONDUCTOR MEMORY DEVICE WITH BIT LINE OF SMALL RESISTANCE AND MANUFACTURING METHOD THEREOF - A reduction of a resistance of a bit line of a memory cell array and a reduction of a forming area of the memory cell array are planed.06-24-2010
20100155816HTO OFFSET AND BL TRENCH PROCESS FOR MEMORY DEVICE TO IMPROVE DEVICE PERFORMANCE - Memory devices having an increased effective channel length and/or improved TPD characteristics, and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The bit line dielectrics can extend into the semiconductor. The memory cell contains a charge trapping dielectric stack, a poly gate, a pair of pocket implant regions, and a pair of bit lines. The bit line can be formed by an implant process at a higher energy level and/or a higher concentration of dopants without suffering device short channel roll off issues because spacers at bit line sidewalls constrain the implant in narrower implant regions.06-24-2010
20100148241SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The semiconductor device has a stacked structure in which a tunnel oxide layer, a charge trapping layer, a blocking oxide layer, and a gate electrode are sequentially formed on a silicon substrate, wherein the blocking oxide layer includes a crystalline layer disposed adjacent to the charge trapping layer and an amorphous layer disposed adjacent to the gate electrode.06-17-2010
20100148240SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Disclosed are a semiconductor device and a manufacturing method thereof. The semiconductor device includes a first insulating layer pattern on a semiconductor substrate, a second insulating layer including fluorine on the first insulating layer pattern, a third insulating layer pattern on the second insulating layer pattern, and a polysilicon pattern on the third insulating layer pattern. The fluorine is included in the second insulating layer that may be a nitride layer that stores data in a flash memory device, so that data retention and reliability are improved without exerting an influence upon capacitor characteristics.06-17-2010
20100155821STACKED NON-VOLATILE MEMORY DEVICE AND METHODS FOR FABRICATING THE SAME - A stacked non-volatile memory device comprises a plurality of bit line and word line layers stacked on top of each other. The bit line layers comprise a plurality of bit lines that can be formed using advanced processing techniques making fabrication of the device efficient and cost effective. The device can be configured for NAND operation.06-24-2010
20100155819METHOD OF FABRICATING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device, includes forming an element isolation trench by processing a silicon substrate and a film to be processed, and filling the element isolation trench with an insulating film by a thermal CVD method. The thermal CVD method in filling the trench is executed under a film forming condition that the insulating film filling a part of the trench that is level with or is located lower than an upper surface of the silicon substrate has a porosity set so as to be not less than 5% and that the insulating film filling a part of the trench located higher than the upper surface of the silicon substrate has a lower deposition rate than the insulating film filling said part of the trench that is level with or is located lower than the upper surface of the silicon substrate.06-24-2010
20100176439NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - The charge retention characteristics of a non-volatile memory, particularly, a MONOS-type non-volatile memory is improved. In a non-volatile memory cell including a tunnel silicon oxide film (07-15-2010
20120032252THICKENED SIDEWALL DIELECTRIC FOR MEMORY CELL - Methods and devices are disclosed, such as those involving memory cell devices with improved charge retention characteristics. In one or more embodiments, a memory cell is provided having an active area defined by sidewalls of neighboring trenches. A layer of dielectric material is blanket deposited over the memory cell, and etched to form spacers on sidewalls of the active area. Dielectric material is formed over the active area, a charge trapping structure is formed over the dielectric material over the active area, and a control gate is formed over the charge trapping structure. In some embodiments, the charge trapping structure includes nanodots. In some embodiments, the width of the spacers is between about 130% and about 170% of the thickness of the dielectric material separating the charge trapping material and an upper surface of the active area.02-09-2012
20090078987PROGRAMMABLE ELEMENT AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - In one aspect of the present invention, a programmable element, may include a semiconductor substrate, source/drain layers formed apart from each other in the upper surface of the semiconductor substrate, a gate insulating film including a charge-trapping film containing Hf and formed on a portion between the source/drain layers of the semiconductor substrate, and a gate electrode formed on the gate insulating film with a program voltage applied to the gate electrode.03-26-2009
20100193858NAND MEMORY DEVICE WITH INVERSION BIT LINES AND METHODS FOR MAKING THE SAME - A NAND based memory device uses inversion bit lines in order to eliminate the need for implanted bit lines. As a result, the cell size can be reduced, which can provide greater densities in smaller packaging. In another aspect, a method for fabricating a NAND based memory device that uses inversion bit lines is disclosed.08-05-2010
20100193857NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A split gate type nonvolatile semiconductor memory device having a FinFET structure includes a semiconductor substrate, parallel trenches on a surface of the semiconductor substrate, and select and memory gate electrodes perpendicular to the trenches. While either the select or the memory gate electrodes are formed prior to the other gate electrodes, each remaining gate electrode is formed adjacent to a side wall of each of the gate electrodes. The semiconductor memory device includes source/drain regions each formed between each pair of the select gate electrodes and between each pair of the memory gate electrodes in protruding portions between each pair of the trenches. A difference between heights of the select gate electrodes and the memory gate electrodes is equal to or greater than a difference between heights of insulation layers formed on the bottom of each of the trenches and the source/drain regions.08-05-2010
20130214344NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to example embodiments of inventive concepts, a non-volatile memory device includes a substrate including a second impurity region crossing a first impurity region, and channel regions extending in a vertical direction on the substrate. Gate electrodes may be separated from each other in a vertical direction and a horizontal direction along outer walls of the channel regions. A first insulating interlayer may be on the gate electrodes and the channel regions, where the first insulating interlayer defines a contact hole between at least one adjacent pair gate electrodes and a contact plug is formed in the contact hole to be electrically connected to the second impurity region. An etch stop layer pattern may be on the contact plug and the first insulating interlayer.08-22-2013
20130214345NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device includes a charge storage layer on a first insulating film, a second insulating film which is provided on the charge storage layer, formed of layers, and a control gate electrode on the second insulating film. The second insulating film includes a bottom layer (A) provided just above the charge storage layer, a top layer (C) provided just below the control gate electrode, and a middle layer (B) provided between the bottom layer (A) and the top layer (C). The middle layer (B) has higher barrier height and lower dielectric constant than both the bottom layer (A) and the top layer (C). The average coordination number of the middle layer (B) is smaller than both the average coordination number of the top layer (C) and the average coordination number of the bottom layer (A).08-22-2013
20100187597METHOD OF FORMING SPACED-APART CHARGE TRAPPING STACKS - Methods are provided for fabricating memory devices. A method comprises fabricating charge-trapping stacks overlying a silicon substrate and forming bit line regions in the substrate between the charge trapping stacks. Insulating elements are formed overlying the bit line regions between the stacks. The charge-trapping stacks are etched to form two complementary charge storage nodes and to expose portions of the silicon substrate. Silicon is grown on the exposed silicon substrate by selective epitaxial growth and is oxidized. A control gate layer is formed overlying the complementary charge storage nodes and the oxidized epitaxially-grown silicon.07-29-2010
20100155818VERTICAL CHANNEL TYPE NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating, a vertical channel type nonvolatile memory device includes: alternately forming a plurality of sacrificial layers and a plurality of interlayer dielectric layers over a semiconductor substrate; etching the sacrificial layers and the interlayer dielectric layers to form a plurality of first openings for channel each of which exposes the substrate; filling the first openings to form a plurality of channels protruding from the semiconductor substrate; etching the sacrificial layers and the interlayer dielectric layers to form second openings for removal of the sacrificial layers between the channels; exposing sidewalls of the channels by removing the sacrificial layers exposed by the second openings; and forming a tunnel insulation layer, a charge trap layer, a charge blocking layer, and a conductive layer for gate electrode on the exposed sidewalls of the channels.06-24-2010
20100012999SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided are a semiconductor memory device and a method of manufacturing the same. The semiconductor memory device comprises two gate electrodes on a semiconductor substrate between device isolation regions, a common source region on the semiconductor substrate between the two gate electrodes, a drain region on the semiconductor substrate at outer sides of the two gate electrodes, a spacer on the drain region and on outer sidewalls of the two gate electrodes, a third oxide layer on inner sidewalls of the two gate electrodes, and a silicide layer on the common source region.01-21-2010
20100176438DEPLETION-MODE CHARGE-TRAPPING FLASH DEVICE - A memory device includes a plurality of semiconductor lines, such as body-tied fins, on a substrate. The lines including buried-channel regions doped for depletion mode operation. A storage structure lies on the plurality of lines, including tunnel insulating layer on the channel regions of the fins, a charge storage layer on the tunnel insulating layer, and a blocking insulating layer on the charge storage layer. A plurality of word lines overlie the storage structure and cross over the channel regions of the semiconductor lines, whereby memory cells lie at cross-points of the word lines and the semiconductor lines.07-15-2010
20100176437MEMORY ARRAY AND METHOD FOR MANUFACTURING AND OPERATING THE SAME - The invention provides a memory array. The memory array comprises a substrate, a plurality of word lines, a charge trapping structure, a plurality of trench channels and a plurality of bit lines. The word lines are located over the substrate and the word lines are parallel to each other. The charge trapping structure covers a surface of each of the word lines. The trench channels are located over the substrate and the word lines and the trench channels are alternatively arranged and each trench channel is separated from the adjacent word lines by the charge trapping structure. The bit lines are located over the word lines and each bit line is across over each of the word lines and each trench channel is electrically coupled to the bit lines.07-15-2010
20100176440SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device includes: a first layer; a second layer; a columnar structural unit; and a side portion. The second layer is provided on a major surface of the first layer. The columnar structural unit is conductive and aligned in the first layer and the second layer to pass through the major surface. The side portion is added to a side wall of the columnar structural unit on the second layer side of the major surface.07-15-2010
20100193856SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A step is provided between a substrate surface of a select gate and a substrate surface of a memory gate. When the substrate surface of the select gate is lower than the substrate surface of the memory gate, electrons in a channel upon writing obliquely flow in the step portion. Even if the electrons obtain the energy required for passing a barrier during the oblique flow, the electron injection does not occur because electrons are away from the substrate surface. The injection can occur only on a drain region side from a position where the electrons reach the substrate surface. As a result, the injection of the electrons into a gap region is suppressed, so that the electron distribution comes close to the hole distribution. Therefore, variation in a threshold value upon information retention is suppressed, and information-retaining characteristics of a memory cell are improved.08-05-2010
20100224928METHOD FOR MANUFACTURING NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A method for manufacturing a nonvolatile semiconductor memory device, the device including a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction and a semiconductor pillar piercing the stacked structural unit in the first direction, the method includes: forming a stacked unit including a core material film alternately stacked with a sacrificial film on a major surface of a substrate perpendicular to the first direction; making a trench in the stacked unit, the trench extending in the first direction and a second direction in a plane perpendicular to the first direction; filling a filling material into the trench; removing the sacrificial film to form a hollow structural unit, the hollow structural unit including a post unit supporting the core material film on the substrate, the post unit being made of the filling material; and forming the stacked structural unit by stacking one of the insulating films and one of the electrode films on a surface of the core material film exposed by removing the sacrificial film.09-09-2010
20100001338Non-volatile semiconductor memory device, and manufacture method for non-volatile semiconductor memory device - A non-volatile semiconductor memory device includes a semiconductor substrate, a charge-storage layer that is formed above the semiconductor substrate, a first gate that is formed above the charge-storage layer, and that includes a first surface and a second surface, a second gate that is formed beside the first surface of the first gate, an insulating layer that is formed above the second surface of the first gate, a diffusion region that is formed on the semiconductor substrate at a position corresponding to the second surface of the first gate, and a silicide layer that is formed above the insulating layer and the diffusion region.01-07-2010
20100155823DEPLETION MODE BANDGAP ENGINEERED MEMORY - Memory cells comprising: a semiconductor substrate having a source region and a drain region disposed below a surface of the substrate and separated by a channel region; a tunnel dielectric structure disposed above the channel region, the tunnel dielectric structure comprising at least one layer having a hole-tunneling barrier height; a charge storage layer disposed above the tunnel dielectric structure; an insulating layer disposed above the charge storage layer; and a gate electrode disposed above the insulating layer are described along with arrays and methods of operation.06-24-2010
20090294836NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR MANUFACTURING SAME - A nonvolatile semiconductor storage device includes: a plurality of stacked units juxtaposed on a major surface of a substrate, each stacked unit aligning in a first direction parallel to the major surface of the substrate; and a gate electrode aligning parallel to the major surface in a second direction non-parallel to the first direction. Each of the plurality of stacked units includes a plurality of stacked semiconductor layers via an insulating layer. The plurality of stacked units are juxtaposed so that the spacings between adjacent stacked units are alternately a first spacing and a second spacing larger than the first spacing. The second spacing is provided at a periodic interval four times a size of a half pitch F of the bit line. The gate electrode includes a protruding portion that enters into a gap of the second spacing between the stacked units. A first insulating film, a charge storage layer, and a second insulating film are provided between a side face of the semiconductor layer and the protruding portion.12-03-2009
20090212350NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - A nonvolatile semiconductor storage device has a plurality of memory strings in which a plurality of electrically rewritable memory cells are connected in series. The memory string has a columnar semiconductor layer extending in a direction perpendicular to a substrate; a conductive layer formed so as to sandwich a charge storing layer in cooperation with the columnar semiconductor layer; and a metal layer formed so as to be in contact with the top face of the conductive layer.08-27-2009
20100213536Nonvolatile Memory Device and Method of Forming the Same - A nonvolatile memory device includes a device isolation pattern, a charge trap layer, and a plurality of word lines. The device isolation pattern defines an active region in a semiconductor substrate and extends in a first direction. The charge trap layer covers the active region and the device isolation pattern. The word lines on the charge trap layer cross the active region and extend in a second direction. The charge trap layer disposed in a first region where the word line and the active region cross each other has a different nitrogen content ratio from the charge trap layer disposed in a second region surrounding the first region.08-26-2010
20100276746SONOS MEMORY CELLS HAVING NON-UNIFORM TUNNEL OXIDE AND METHODS FOR FABRICATING SAME - Methods for forming a memory cell are disclosed. A method includes forming a source-drain structure in a semiconductor substrate where the source-drain structure includes a rounded top surface and sidewall surfaces. An oxide layer is formed on the top and sidewall surfaces of the source-drain structure. The thickness of the portion of the oxide layer that is formed on the top surface of the source-drain structure is greater than the thickness of the portion of the oxide layer that is formed on the sidewall surfaces of the source-drain structure.11-04-2010
20100230743SELF-ALIGNED PATTERNING METHOD BY USING NON-CONFORMAL FILM AND ETCH FOR FLASH MEMORY AND OTHER SEMICONDUCTOR APPLICATIONS - A method for fabricating a memory device with a self-aligned trap layer which is optimized for scaling is disclosed. In the present invention, a non-conformal film is deposited over the charge trapping layer to form a thick film on top of the core source/drain region and a pinch off and a void or a narrow channel at the top of the STI trench. An etch is performed on the non-conformal film to open pinch-off or widen the narrow channel in the non-conformal. The trapping layer is then completely or partially etched between the core cells. The non-conformal film is removed. And a top oxide is formed. The top oxide converts the remaining trap layer to oxide if the trapping layer is partially etched and thus isolate the trap layer.09-16-2010
20100237402SEMICONDUCTOR MEMORY DEVICE HAVING THREE-DIMENSIONALLY ARRANGED MEMORY CELLS, AND MANUFACTURING METHOD THEREOF - A first select transistor is formed on a semiconductor substrate. Memory cell transistors are stacked on the first select transistor and connected in series. A second select transistor is formed on the memory cell transistors. The memory cell transistors include a tapered semiconductor pillar which increases in diameter from the first select transistor toward the second select transistor, a tunnel dielectric film formed on the side surface of the semiconductor pillar, a charge storage layer which is formed on the side surface of the tunnel dielectric film and which increases in charge trap density from the first select transistor side toward the second select transistor side, a block dielectric film formed on the side surface of the charge storage layer, and conductor films which are formed on the side surface of the block dielectric film and which serve as gate electrodes.09-23-2010
20100237399NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor memory device includes: a semiconductor substrate; a plurality of device isolation regions being disposed in an upper-layer portion of the semiconductor substrate, and dividing the upper-layer portion into a plurality of semiconductor portions extending in a first direction; a plurality of charge storage films which are disposed on one of the plurality of the semiconductor portions and spaced apart from one another in the first direction; a block insulating film disposed covering the plurality of charge storage films; and a word electrode disposed on the block insulating film for each of rows of the plurality of charge storage films arranged in a second direction intersecting the first direction, wherein the block insulating film is disposed continuously in the first direction and in the second direction.09-23-2010
20100213535ADJACENT WORDLINE DISTURB REDUCTION USING BORON/INDIUM IMPLANT - Semiconductor devices having reduced parasitic current and methods of malting the semiconductor devices are provided. Further provided are memory devices having reduced adjacent wordline disturb. The memory devices contain wordlines formed over a semiconductor substrate, wherein at least one wordline space is formed between the wordlines. Adjacent wordline disturb is reduced by implanting one or more of indium, boron, and a combination of boron and indium in the surface of the at least one wordline space.08-26-2010
20100001339Semiconductor device and methods of forming and operating the same - Provided are a semiconductor device and a methods of forming and operating the semiconductor device. The semiconductor device may include active pillars extending from a semiconductor substrate and disposed two dimensionally disposed on the semiconductor substrate, upper interconnections connecting the active pillars along one direction, lower interconnections crossing the upper interconnections and disposed between the active pillars, word lines crossing the upper interconnections and disposed between the active pillars, and data storage patterns disposed between the word lines and the active pillars.01-07-2010
20100237400NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device includes: a multilayer body with a plurality of insulating films and electrode films alternately stacked therein; a plurality of select gate electrodes provided on the multilayer body, extending in one direction orthogonal to a stacking direction of the multilayer body, and spaced from each other; semiconductor pillars penetrating through the multilayer body and the select gate electrodes; and a charge storage film provided between one of the electrode films and one of the semiconductor pillars, two neighboring ones of the semiconductor pillars penetrating through a common one of the select gate electrodes and penetrating through mutually different positions in a width direction of the select gate electrodes.09-23-2010
20100230742NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - A non-volatile semiconductor memory device includes a plurality of memory cell regions including a plurality of bit lines, a plurality of word lines intersecting the plurality of bit lines, and a first insulating film formed in a region between any two adjacent bit lines, a bit line contact region including bit line contacts connected to the plurality of bit lines, a first UV light shielding film covering at least a portion of the semiconductor substrate in the bit line contact region, an interlayer insulating film, and a second UV light shielding film covering the plurality of memory cell regions. The first UV light shielding film effectively reduces or blocks UV light generated during a fabrication step.09-16-2010
20100230741SEMICONDUCTOR DEVICES WITH AN AIR GAP IN TRENCH ISOLATION DIELECTRIC - A tunnel insulating layer and a charge storage layer are sequentially stacked on a substrate. A recess region penetrates the charge storage layer, the tunnel insulating layer and a portion of the substrate. The recess region is defined by a bottom surface and a side surface extending from the bottom surface. A first dielectric pattern includes a bottom portion covering the bottom surface and inner walls extending from the bottom portion and covering a portion of the side surface of the recess region. A second dielectric pattern is in the recess region between the inner walls of the first dielectric pattern, and the second dielectric pattern enclosing an air gap. The air gap that is enclosed by the second dielectric pattern may extend through a major portion of the second dielectric pattern in a direction away from the bottom surface of the recess region.09-16-2010
20100237403ZrAlON FILMS - Atomic layer deposition (ALD) can be used to form a dielectric layer of zirconium aluminum oxynitride (ZrAlON) for use in a variety of electronic devices. Forming the dielectric layer may include depositing zirconium oxide using atomic layer deposition and precursor chemicals, followed by depositing aluminum nitride using precursor chemicals, and repeating. The dielectric layer may be used as the gate insulator of a MOSFET, a capacitor dielectric, and a tunnel gate insulator in flash memories.09-23-2010
20100237401GATE STRUCTURES OF SEMICONDUCTOR DEVICES - Gate structures of semiconductor devices and methods of forming gate structures of semiconductor devices are provided. A first insulating pattern may be disposed on an active region of a semiconductor substrate. A data storage pattern may be disposed on the first insulating pattern. A second insulating pattern may be disposed on the data storage pattern and may contact the data storage pattern. A first conductive pattern may conform to the second insulating pattern and to sidewalls of a mold comprising the second insulating pattern. A second conductive pattern may be disposed within a cavity defined by the first conductive pattern. Spacers may be formed on sidewalls of at least one of the first insulating pattern, the data storage pattern, the second insulating pattern, and the conductive pattern.09-23-2010
20100252877Non-Volatile Semiconductor Memory Devices Having Charge Trap Layers Between Word Lines and Active Regions Thereof - A non-volatile memory device includes: word line disposed on a substrate; an active region crossing over the word line; and a charge trap layer that is between the word line and the active region.10-07-2010
20100252876Structure and method for forming an oscillating MOS transistor and nonvolatile memory - With simply applying the gate voltage, the transistor will start sending out oscillating signals, working like a semiconductor “engine”. A special MOS field effect transistor (FET) includes an extended lightly doped drain and an intrinsic undoped or very lightly doped “gap” between the gate and the heavily doped source. The gap needs to be specially engineered so that the transistor is not always turned on by the MOSFET gate voltage, but will be turned on by the carriers from the forward-biased channel-drain junction diode. Oscillation occurs to the drain current (or voltage) when a suitable gate voltage is applied, due to the repeated back and forth actions of deep depletion in the transistor well and forward bias of the drain-well p-n junction diode. By forming a second spacer gate on one side of the main gate, the device can be used as a non-volatile memory, with the charges stored at the dielectrics / silicon interface, which can significantly impact the oscillating for the READ operation of a memory. This device can also be a frequency amplifier.10-07-2010
20100252878NON-VOLATILE MEMORY CELL - A super-silicon-rich oxide (SSRO) non-volatile memory cell includes a gate conductive layer on a substrate, a source/drain in the substrate at respective sides of the gate conductive layer, a tunneling dielectric layer between the gate conductive layer and the substrate, a SSRO layer serving as a charge trapping layer between the gate conductive layer and the tunneling dielectric layer, and an upper-dielectric layer between the gate conductive layer and the SSRO layer.10-07-2010
20090206388SEPERATION METHODS FOR SEMICONDUCTOR CHARGE ACCUMULATION LAYERS AND STRUCTURES THEREOF - Devices and methods for isolating adjacent charge accumulation layers in a semiconductor device are disclosed. In one embodiment, a semiconductor device comprises a bit line formed in a semiconductor substrate, a charge accumulation layer formed on the semiconductor substrate, a word line formed on the charge accumulation layer across the bit line, and a channel region formed in the semiconductor substrate below the word line and between the bit line and its adjacent bit line. For the semiconductor device, the charge accumulation layer is formed above the channel region in a widthwise direction of the word line, and a width of the word line is set to be narrower than a distance between an end of the channel region and a central part of the channel region in a lengthwise direction of the word line.08-20-2009
20090020804SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device and a method for fabricating the same. The semiconductor device includes a gate pattern formed on a semiconductor substrate, a first impurity-doped region formed in the substrate on one side of the gate pattern and a second impurity-doped region formed in the substrate on the other side of the gate pattern, a salicide shielding film pattern partially covering either the first impurity-doped region or the second impurity-doped region, an insulating film formed on the semiconductor substrate, the insulating film including a first hole which exposes the salicide shielding film pattern, and a second hole which partially exposes the first impurity-doped region or the second impurity-doped region that is not covered by the salicide shielding film pattern, and a first line coming in contact with the salicide shielding film pattern through the first hole.01-22-2009
20080230830NONVOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A nonvolatile memory device and a method of fabricating the same is provided to prevent charges stored in a charge trap layer from moving to neighboring memory cells. The method of fabricating a nonvolatile memory device, includes forming a first dielectric layer on a semiconductor substrate in which active regions are defined by isolation layers, forming a charge trap layer on the first dielectric layer, removing the first dielectric layer and the charge trap layer over the isolation layers, forming a second dielectric layer on the isolation layers including the charge trap layer, and forming a conductive layer on the second dielectric layer.09-25-2008
20110057251NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A nonvolatile semiconductor memory device includes a first region having a plurality of electrically rewritable memory cells disposed therein, and a second region adjacent to the first region. The nonvolatile semiconductor memory device includes a plurality of first conductive layers, a semiconductor layer, a charge storage layer, and an insulating columnar layer. The plurality of first conductive layers are stacked in the first region and the second region, and include a stepped portion in the second region, positions of ends of the plurality of first conductive layers being different in the stepped portion. The semiconductor layer is surrounded by the first conductive layers in the first region, includes a first columnar portion extending in a stacking direction. The charge storage layer is formed between the first conductive layers and a side surface of the first columnar portion. The insulating columnar layer is surrounded by the first conductive layers in the stepped portion, and includes a second columnar portion extending in the stacking direction and comprising an insulator.03-10-2011
20110057250NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A plurality of conductive layers are stacked in a first region and a second region. A semiconductor layer is surrounded by the conductive layers in the first region, includes a columnar portion extending in a perpendicular direction with respect to a substrate. A charge storage layer is formed between the conductive layers and a side surface of the columnar portion. The conductive layers includes first trenches, second trenches, and third trenches. The first trenches are arranged in the first region so as to have a first pitch in a first direction. The second trenches are arranged in the second region so as to have a second pitch in the first direction. The third trenches are arranged in the second region so as to have a third pitch in the first direction and so as to be sandwiched by the second trenches.03-10-2011
20110057249NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a nonvolatile semiconductor memory device includes a substrate, a stacked structural body, a semiconductor pillar, and a memory unit. The stacked structural body is provided on a major surface of the substrate. The stacked structural body includes electrode films alternately stacked with inter-electrode insulating films in a direction perpendicular to the major surface. The pillar pierces the body in the direction. The memory unit is provided at an intersection between the pillar and the electrode films. The electrode films include at least one of amorphous silicon and polysilicon. The stacked structural body includes first and second regions. A distance from the second region to the substrate is greater than a distance from the first region to the substrate. A concentration of an additive included in the electrode film in the first region is different from that included in the electrode film in the second region.03-10-2011
20110057248VARIED SILICON RICHNESS SILICON NITRIDE FORMATION - A method, in one embodiment, can include forming a tunnel oxide layer on a substrate. In addition, the method can include depositing via atomic layer deposition a first layer of silicon nitride over the tunnel oxide layer. Note that the first layer of silicon nitride includes a first silicon richness. The method can also include depositing via atomic layer deposition a second layer of silicon nitride over the first layer of silicon nitride. The second layer of silicon nitride includes a second silicon richness that is different than the first silicon richness.03-10-2011
20130126961NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of columnar portions; a charge storage layer formed to surround the side surfaces of the columnar portions; and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers function as gate electrodes of the memory cells.05-23-2013
20100127319Semiconductor devices including a dielectric layer - A semiconductor device includes a substrate and a doped hafnium oxide layer disposed on the substrate, the doped hafnium oxide layer including a hafnium oxide layer doped with doping atoms and having tetragonal unit lattices, an ion size of the doping atom being greater than an ion size of a hafnium atom.05-27-2010
20100013000MEMORY APPARATUS - The memory apparatus includes a memory device including a gate insulating layer formed on a silicon substrate by sequentially stacking a tunnel oxide layer, a charge trap layer, and a block oxide layer in this order, on the silicon substrate. In addition, a gate electrode is formed on the gate insulating layer. The block oxide layer is formed by stacking a first block oxide layer and a second block oxide layer, wherein the first block oxide layer is adjacent to the charge trap layer and the second block oxide layer is adjacent to the gate electrode. The second block oxide layer is formed of a dielectric material having higher permittivity than that of the first block oxide layer and having higher electron affinity than that of the first block oxide layer.01-21-2010
20090014780DISCRETE TRAP NON-VOLATILE MULTI-FUNCTIONAL MEMORY DEVICE - A multiple layer tunnel insulator is fabricated between a substrate and a discrete trap layer. The properties of the multiple layers determines the volatility of the memory device. The composition of each layer and/or the quantity of layers is adjusted to fabricate either a DRAM device, a non-volatile memory device, or both simultaneously.01-15-2009
20090242962Plasma oxidation of a memory layer to form a blocking layer in non-volatile charge trap memory devices - A blocking layer of a non-volatile charge trap memory device is formed by oxidizing a portion of a charge trapping layer of the memory device. In one embodiment, the blocking layer is grown by a radical oxidation process at temperature below 500° C. In accordance with one implementation, the radical oxidation process involves flowing hydrogen (H10-01-2009
20090212348MIRROR BIT MEMORY DEVICE APPLYING A GATE VOLTAGE ALTERNATELY TO GATE - A semiconductor device and a method for manufacturing thereof are provided. The semiconductor device includes: an ONO film including a charge storage layer on a semiconductor substrate; a plurality of bit lines each extending inside the semiconductor substrate; a plurality of interspaces each interposed between the adjacent bit lines; a plurality of gates each provided along the bit line on the ONO film above the interspaces; and a plurality of word lines electrically coupled with the corresponding gates formed on one of the interspaces, each extending to intersect with the bit lines. The two gates adjacent with each other in a width direction of the bit line are connected to different word lines.08-27-2009
20090189213NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A nonvolatile semiconductor memory device includes a semiconductor substrate having a plurality of active regions separately formed by a plurality of trenches formed in a surface of the substrate at predetermined intervals, a first gate insulating film formed on an upper surface of the substrate corresponding to each active region, a gate electrode of a memory cell transistor formed by depositing an electrical charge storage layer formed on an upper surface of the gate insulating film, a second gate insulating film and a control gate insulating film sequentially, an element isolation insulating film buried in each trench and formed from a coating type oxide film, and an insulating film formed inside each trench on a boundary between the semiconductor substrate and the element isolation insulating film, the insulating film containing nontransition metal atoms and having a film thickness not more than 5 Å.07-30-2009
20090152618NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A nonvolatile semiconductor memory device includes a semiconductor substrate, a first insulation layer formed on the semiconductor substrate, a charge storage layer formed on the first insulation layer, a second insulation layer formed on the charge storage layer, a control electrode formed on the second insulation layer. The second insulation layer includes a first silicon oxide film, an intermediate insulating film formed on the first silicon oxide film and having a relative permittivity of not less than 7, and a second silicon oxide film formed on the intermediate insulating film. A charge trap layer is formed at least in either first or second silicon oxide film or a boundary between the first silicon oxide film and the intermediate insulating film or a boundary between the second silicon oxide film and the intermediate insulating film.06-18-2009
20090039415Method of forming dielectric including dysprosium and scandium by atomic layer deposition and integrated circuit device including the dielectric layer - In one embodiment, the method of forming a dielectric layer includes supplying a first precursor at a temperature less than 400 degrees Celsius to a chamber including a substrate. The first precursor includes dysprosium. A first reaction gas is supplied to the chamber to react with the first precursor. A second precursor is supplied at a temperature less than 400 degrees Celsius to the chamber, and the second precursor includes scandium. A second reaction gas is supplied to the chamber to react with the second precursor.02-12-2009
20090114976Programming and Erasing Method for Charge-Trapping Memory Devices - A method for programming and erasing charge-trapping memory device is provided. The method includes applying a first negative voltage to a gate causing a dynamic balance state (RESET\ERASE state). Next, a positive voltage is applied to the gate to program the device. Then, a second negative voltage is applied to the gate to restore the device to the RESET\ERASE state.05-07-2009
20080283902Non-volatile memory device and method of manufacturing the same - A method of manufacturing a non-volatile memory device includes sequentially depositing a first insulation layer, a charge storage layer, and a second insulation layer on a substrate, forming a first opening through the resultant structure to expose the substrate, forming second and third openings through the second insulation layer to form a second insulation layer pattern, forming a conductive layer on the second insulation layer pattern, forming a photoresist pattern structure on the conductive layer, and forming simultaneously a common source line, at least one ground selection line, at least one string selection line, and a plurality of gate structures on the substrate by etching through the photoresist pattern structure, wherein the common source line and the gate structures are formed simultaneously on a substantially same level and of substantially same components.11-20-2008
20090072297Multibit electro-mechanical memory device and method of manufacturing the same - A memory device comprises a cantilever electrode comprising a first portion that is supported by a pad electrode, and that extends from the pad electrode, and further comprising a second portion that arches over an upper part of the lower word line, wherein a lower void is between the second portion of the cantilever electrode and the lower word line, and wherein the second portion of the cantilever electrode, in a first position, is curved, wherein a trap site extends above the cantilever electrode, the trap site separated from the cantilever electrode by an upper void, and wherein an upper word line on the trap site receives a charge that enables the second portion of the cantilever electrode, in a second position, to be curved toward the trap site.03-19-2009
20090072296Multibit electro-mechanical device and method of manufacturing the same - A multibit electro-mechanical memory device capable of increasing an integrated level of memory devices, and a method of manufacturing the same, are provided. The memory device includes a substrate, a bit line in a first direction on the substrate, a lower word line insulated from the bit line and in a second direction intersecting the first direction, a pad electrode isolated from a sidewall of the lower word line and connected to the bit line, a cantilever electrode expending in the first direction over the lower word line with a lower void therebetween, and connected to the pad electrode and curved in a third direction vertical to the first and second direction by an electrical field induced by a charge applied to the lower word line, a trap site expending in the second direction over the cantilever electrode with an upper void therebetween, and an upper word line to which a charge to curve the cantilever electrode in a direction of the trap site is applied, the upper word line on the trap site.03-19-2009
20080265306Non-Volatile Memory Device Having a Gap in the Tunnuel Insulating Layer and Method of Manufacturing the Same - A non-volatile memory device (10-30-2008
20090108333NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - A non-volatile semiconductor storage device has a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series. Each of the memory strings includes: a first columnar semiconductor layer extending in a direction perpendicular to a substrate; a charge accumulation layer formed on the first columnar semiconductor layer via a first air gap and accumulating charges; a block insulation layer contacting the charge accumulation layer; and a plurality of first conductive layers contacting the block insulation layer.04-30-2009
20090032862Non-volatile memory cell and non-volatile memory device using said cell - A non-volatile electrically erasable programmable read only memory (EEPROM) capable of storing two bit of information having a non-conducting charge trapping dielectric, such as silicon nitride, sandwiched between two silicon dioxide layers acting as electrical insulators is disclosed. The invention includes a method of programming, reading and erasing the two bit EEPROM device. The non-conducting dielectric layer functions as an electrical charge trapping medium. A conducting gate layer is placed over the upper silicon dioxide layer. A left and a right bit are stored in physically different areas of the charge trapping layer, near left and right regions of the memory cell, respectively. Each bit of the memory device is programmed in the conventional manner, using hot electron programming, by applying programming voltages to the gate and to either the left or the right region while the other region is grounded. Hot electrons are accelerated sufficiently to be injected into the region of the trapping dielectric layer near where the programming voltages were applied to. The device, however, is read in the opposite direction from which it was written, meaning voltages are applied to the gate and to either the right or the left region while the other region is grounded. Two bits are able to be programmed and read due to a combination of relatively low gate voltages with reading in the reverse direction. This greatly reduces the potential across the trapped charge region. This permits much shorter programming times by amplifying the effect of the charge trapped in the localized trapping region associated with each of the bits. In addition, both bits of the memory cell can be individually erased by applying suitable erase voltages to the gate and either left or right regions so as to cause electrons to be removed from the corresponding charge trapping region of the nitride layer.02-05-2009
20100295116Semiconductor Device and Manufacturing Method Thereof - A semiconductor device having a first semiconductor region and second semiconductor region including impurities formed on an insulating layer formed on a semiconductor substrate, an insulator formed between the first semiconductor region and the second semiconductor region, a first impurity diffusion control film formed on the first semiconductor region and a second impurity diffusion control film formed on the second semiconductor region, a channel layer formed on the first impurity diffusion control film and second impurity diffusion film to cross at right angles with a direction where the first semiconductor region and the second semiconductor region are extended, a gate insulating film formed on the channel layer and a gate electrode formed on the gate insulating layer.11-25-2010
20100295115NONVOLATILE SEMICONDUCTOR MEMORY DEVICE INCLUDING NONVOLATILE MEMORY CELL - A nonvolatile semiconductor memory device includes the following structure. Element isolation films are formed at predetermined intervals in a first direction in a surface region of a semiconductor substrate. The element isolation films extend in a second direction and isolate the surface region of the semiconductor substrate to provide element regions. Upper surface of the element isolation films are lower than upper surface of the element regions of the semiconductor substrate. A tunnel insulating film is formed on the element region. A charge accumulation layer is formed only on the tunnel insulating film. A block layer continuously is formed in the first direction on the charge accumulation layer and the element isolation film. A bottom surface of the block layer on the element isolation film is lower than the upper surface of the element region of the semiconductor substrate. A gate electrode is formed on the block layer.11-25-2010
20100301406ZIRCONIUM-DOPED TANTALUM OXIDE FILMS - Dielectric layers containing a zirconium-doped tantalum oxide layer, where the zirconium-doped tantalum oxide layer is formed of one or more monolayers of tantalum oxide doped with zirconium, provide an insulating layer in a variety of structures for use in a wide range of electronic devices.12-02-2010
20110248332Oxide-Nitride-Oxide Stack Having Multiple Oxynitride Layers - A semiconductor device including a silicon-oxide-oxynitride-oxide-silicon structure and methods of forming the same are provided. Generally, the structure comprises: a tunnel oxide layer on a surface of a substrate including silicon; a multi-layer charge storing layer including an oxygen-rich, first oxynitride layer on the tunnel oxide layer in which the stoichiometric composition of the first oxynitride layer results in it being substantially trap free, and an oxygen-lean, second oxynitride layer on the first oxynitride layer in which the stoichiometric composition of the second oxynitride layer results in it being trap dense; a blocking oxide layer on the second oxynitride layer; and a silicon containing gate layer on the blocking oxide layer. Other embodiments are also disclosed.10-13-2011
20110006356NON-VOLATILE MEMORY AND METHOD FOR FABRICATING THE SAME - A non-volatile memory is described, which includes gate structures, doped regions, second spacers and contact plugs. The gate structures are disposed on the substrate, each of which includes a control gate and a gate dielectric layer. The control gates are disposed on the substrate, and two first spacers are deployed at both sides of each control gate. The gate dielectric layers are disposed between the control gates and the substrate, respectively. Each of the doped regions is formed in the substrate between two adjacent gate structures. The second spacers are disposed on the sidewalls of the gate structures. The contact plugs are formed between two adjacent second spacers, respectively.01-13-2011
20110108907SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor device includes a substrate, a foundation layer, a lower layer side stacked body, an upper layer side stacked body, an inter-layer insulating layer, and a plurality of contact electrodes. The foundation layer is provided in the second contact region to form a difference in levels between the second contact region and the first contact region. The lower layer side stacked body includes a plurality of conductive layers stacked alternately with a plurality of insulating layers. An upper level portion of the lower layer side stacked body stacked on the foundation layer is patterned into a stairstep configuration. The upper layer side stacked body is provided on a lower level portion of the lower layer side stacked body stacked in the first contact region. The upper layer side stacked body includes a plurality of conductive layers stacked alternately with a plurality of insulating layers.05-12-2011
20110001182SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device includes: a stacked body including a conductive layer and an insulating layer alternately stacked on a base body; a pair of wall portions formed on the base body with a height equivalent to or larger than a thickness of the stacked body and opposed with a spacing wider than a thickness for one layer of the conductive layer; a contact layer interposed between the wall portions and connected to the conductive layer in the stacked body through an open end between the wall portions; and a contact electrode provided on the contact layer and connected to the contact layer.01-06-2011
20110018050NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - A nonvolatile semiconductor memory device, includes: a stacked structural unit including electrode films alternately stacked with inter-electrode insulating films; first and second semiconductor pillars piercing the stacked structural unit; a connection portion semiconductor layer electrically connect the first and second semiconductor pillars; a connection portion conductive layer provided to oppose the connection portion semiconductor layer; a memory layer and an inner insulating film provided between the first and semiconductor pillars and each of the electrode films, and between the connection portion conductive layer and the connection portion semiconductor layer; an outer insulating film provided between the memory layer and each of the electrode films; and a connection portion outer insulating film provided between the memory layer and the connection portion conductive layer. The connection portion outer insulating film has a film thickness thicker than a film thickness of the outer insulating film.01-27-2011
20110018049Charge trapping device and method for manufacturing the same - The present invention relates to a charge trapping device and a method for manufacturing the same. The charge trapping device includes: a substrate having a first surface and an opposite second surface; a tunneling insulating layer, disposed on the first surface of the substrate; a charge trapping layer, disposed on the tunneling insulating layer and including a first dielectric layer and a second dielectric layer, in which the first dielectric layer is connected to the tunneling insulating layer, the second dielectric layer is disposed over the first dielectric layer, and a conduction band offset between the first dielectric layer and the substrate is larger than that between the second dielectric layer and the substrate; and a blocking insulating layer, disposed on the charge trapping layer and connected to the second dielectric layer. Accordingly, the charge trapping device of the present invention has excellent programming, and erasing and charge retention properties.01-27-2011
20110001184METHOD OF ADJUSTING THE THRESHOLD VOLTAGE OF A TRANSISTOR BY A BURIED TRAPPING LAYER - An electronic subassembly and associated method for the production of an electronic subassembly include a semiconductor layer bearing at least a first transistor having an adjustable threshold voltage is joined to an insulator layer and a in which a first trapping zone is formed at a predetermined first depth. The first trapping zone extends at least beneath a channel of the first transistor and includes traps of greater density than the density of traps outside the first trapping zone, in such a way that the semiconductor layer and the first trapping zone are capacitively coupled. The useful information from the first transistor includes the charge transport within this transistor. A second trapping zone can be formed that extends at least beneath a channel of a second transistor that is formed by a second implantation with an energy and/or a dose and/or atoms that differ from those used to form the first trapping zone.01-06-2011
20110024824NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a nonvolatile semiconductor memory device includes a semiconductor layer and a transistor. The transistor includes: a source region, a drain region, and a channel region provided in the semiconductor layer, the channel region being between the source and drain regions; a gate insulating film provided on the channel region; a charge layer provided on the gate insulating film, the charge layer having a side portion and a apical portion;02-03-2011
20110024823NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE WITH INTRINSIC CHARGE TRAPPING LAYER - A non-volatile semiconductor memory device includes a substrate, a first gate formed on a first region of a surface of the substrate, a second gate formed on a second region of the surface of the substrate, a charge storage layer filled between the first gate and the second gate, a first diffusion region formed on a first side of the charge storage layer, and a second diffusion region formed opposite the charge storage layer from the first diffusion region. The first region and the second region are separated by a distance sufficient for forming a self-aligning charge storage layer therebetween.02-03-2011
20090065851OPERATING METHOD OF NON-VOLATILE MEMORY DEVICE - A non-volatile memory device includes memory cells having a semiconductor substrate, a stack layer, and source and drain regions disposed below a surface of the substrate and separated by a channel region. The stack layer includes an insulating layer disposed on the channel region, a charge storage layer disposed on the insulating layer, a multi-layer tunneling dielectric structure on the charge storage layer, and a gate disposed on the multi-layer tunneling dielectric structure. A negative bias is supplied to the gate to inject electrons into the charge storage layer through the multi-layer tunneling dielectric structure by −FN to tunneling so that the threshold voltage of the device is increased. A positive bias is supplied to the gate to inject holes into the charge storage layer through the multi-layer tunneling dielectric structure by +FN tunneling so that the threshold voltage of the device is decreased.03-12-2009
20090065848NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD THEREOF - A charge holding insulating film in a memory cell is constituted by a laminated film composed of a bottom insulating film, a charge storage film, and a top insulating film on a semiconductor substrate. Further, by performing a plasma nitriding treatment to the bottom insulating film, a nitride region whose nitrogen concentration has a peak value and is 1 atoms or more is formed on the upper surface side in the bottom insulating film. The thickness of the nitride region is set to 0.5 nm or more and 1.5 nm or less, and the peak value of nitrogen concentration is set to 5 atom % or more and 40 atom % or less, and a position of the peak value of nitrogen concentration is set within 2 nm from the upper surface of the bottom insulating film, thereby suppressing an interaction between the bottom insulating film and the charge storage film.03-12-2009
20110031550NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - A nonvolatile semiconductor memory device includes: a stacked structural unit including a plurality of electrode films and a plurality of inter-electrode insulating films alternately stacked in a first direction; a first selection gate electrode stacked on the stacked structural unit in the first direction; a first semiconductor pillar piercing the stacked structural unit and the first selection gate electrode in the first direction; a first memory unit provided at an intersection of each of the electrode films and the first semiconductor pillar; and a first selection gate insulating film provided between the first semiconductor pillar and the first selection gate electrode, the first selection gate electrode including a first silicide layer provided on a face of the first selection gate electrode perpendicular to the first direction.02-10-2011
20110042738NITRIDGE READ-ONLY MEMORY CELL AND METHOD OF MANUFACTURING THE SAME - A nitride read-only memory cell and a method of manufacturing the same are provided. First, a substrate is provided, and a first oxide layer is formed on the substrate. Next, a nitride layer is deposited on the first oxide layer via a first gas and a second gas. The flow ratio of the first gas to the second gas is 2:1. After that, a second oxide layer is formed on the nitride layer. Then, a bit-line region is formed at the substrate. Afterward, a gate is formed on the second oxide layer. The first oxide layer, nitride layer, the second oxide layer and the gate compose a stack structure of the cell. Further, a spacer is formed on the side-wall of the stack structure.02-24-2011
20110115014NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a nonvolatile semiconductor memory device includes a substrate, a stacked body, a plurality of semiconductor pillars and a charge storage film. The stacked body is provided on the substrate, with a plurality of insulating films alternately stacked with a plurality of electrode films, and includes a hydrophobic layer provided between one of the insulating films and one of the electrode films. The hydrophobic layer has higher hydrophobicity than the electrode films. The plurality of semiconductor pillars extend in a stacking direction of the stacked body and pierce the stacked body, and the charge storage film is provided between the electrode films and one of the semiconductor pillars.05-19-2011
20110084331SEMICONDUCTOR DEVICE - A semiconductor device has a substrate, a source region formed on the surface portion of the substrate, a first insulating layer formed on the substrate, a gate electrode formed on the first insulating layer, a second insulating layer formed on the gate electrode, a body section connected with the source region, penetrating through the first insulating layer, the gate electrode and the second insulating layer, and containing a void, a gate insulating film surrounding the body section, and formed between the body section and the gate electrode, and a drain region connected with the body section.04-14-2011
20100140685Nonvolatile Memory Devices - Nonvolatile memory devices and methods of manufacturing nonvolatile memory devices are provided. The method includes patterning a bulk substrate to form an active pillar; forming a charge storage layer on a side surface of active pillar; and forming a plurality of gates connected to the active pillar, the charge storage layer being disposed between the active pillar and the gates. Before depositing a gate, a bulk substrate is etched using a dry etching to form a vertical active pillar which is in a single body with a semiconductor substrate.06-10-2010
20090032861NONVOLATILE MEMORIES WITH CHARGE TRAPPING LAYERS CONTAINING SILICON NITRIDE WITH GERMANIUM OR PHOSPHORUS - A nonvolatile memory has a charge trapping layer which includes a layer (02-05-2009
20090032864SELF-ALIGNED CHARGE STORAGE REGION FORMATION FOR SEMICONDUCTOR DEVICE - Devices and methods for forming self-aligned charge storage regions are disclosed. In one embodiment, a method for manufacturing a semiconductor device comprises forming a layer of a nitride film stacked between two oxide films on a semiconductor substrate, and forming a gate electrode on the layer of the nitride film stacked between the two oxide films. In addition, the method comprises removing side portions of the nitride film such that a central portion of the nitride film below a center portion of the gate electrode remains, oxidizing the central portion of the nitride film, and forming charge storage layers in the side portions of the nitride film, where the charge storage layers are separated by the central portion of the nitride film.02-05-2009
20090032863Nitridation oxidation of tunneling layer for improved SONOS speed and retention - A method for forming a tunneling layer of a nonvolatile trapped-charge memory device and the article made thereby. The method includes multiple oxidation and nitridation operations to provide a dielectric constant higher than that of a pure silicon dioxide tunneling layer but with a fewer hydrogen and nitrogen traps than a tunneling layer having nitrogen at the substrate interface. The method provides for an improved memory window in a SONOS-type device. In one embodiment, the method includes an oxidation, a nitridation, a reoxidation and a renitridation. In one implementation, the first oxidation is performed with O02-05-2009
20100163968SEMICONDUCTOR MEMORY DEVICE HAVING INSULATION PATTERNS AND CELL GATE PATTERNS - Semiconductor memory devices and methods of forming semiconductor memory devices are provided. The methods may include forming insulation layers and cell gate layers that are alternately stacked on a substrate, forming an opening by successively patterning through the cell gate layers and the insulation layers, and forming selectively conductive barriers on sidewalls of the cell gate layers in the opening.07-01-2010
20100163966FLASH MEMORY DEVICE AND MANUFACTURING METHOD OF THE SAME - Disclosed are a flash memory device and a method for manufacturing the same. The flash memory device includes first and second memory gates on a substrate; a floating poly between the first and second memory gates; first and second select gates at respective outer sides of the first and second memory gates; an oxide layer between the first memory gate and the first select gate and between the second memory gate and the second select gate; a drain region in the substrate at outer sides of the first and second select gates; a source region in the substrate between the first and second memory gates; and a metal contact on each of the drain region and the source region.07-01-2010
20100163967Flash Memory Device and Method of Fabricating the Same - A flash memory device and a method for fabricating the same are disclosed. The flash memory device includes an ONO layer on a substrate, polysilicon gates on the ONO layer, a gate oxide layer on the substrate, the ONO layer and the polysilicon gates, and a low temperature oxide layer and polysilicon sidewall spacers on outer side surfaces of the polysilicon gates, except in a region between nearest adjacent polysilicon gates.07-01-2010
20100163964METHOD FOR MANUFACTURING FLASH MEMORY DEVICE - A method of manufacturing a flash memory device and devices thereof, which may be capable of preventing damage to a gate. A method of manufacturing a flash memory device may include preparing a semiconductor substrate having an active region defined by a device separator. A method of manufacturing a flash memory device may include forming a floating gate, a oxide-nitride-oxide (ONO) layer and/or a control gate layer on and/or over a substrate. A method of manufacturing a flash memory device may include forming a low temperature oxide (LTO) film on and/or over a control gate, etching a LTO film to expose a desired part of a control gate, using a LTO film as a mask to etch a desired part of each of a floating gate layer, a ONO layer and/or a control gate to form a gate pattern, and/or substantially removing a LTO film by wet etching.07-01-2010
20100163965FLASH MEMORY DEVICE AND MANUFACTURING METHOD OF THE SAME - Disclosed are a flash memory device and a method for manufacturing the same. The flash memory device includes a floating gate including adjacent first and second floating gates on a substrate; first and second select gates respectively on the first and second floating gates; an insulating layer between the first floating gate and the first select gate and between the second floating gate and the second select gate; a drain region at outer sides of the first and second select gates; a source region between the first and second select gates; and a metal contact on each of the drain region and the source region. The select gate can be defined as a self-align structure, and the length of the select gate can be controlled depending on the thickness of the material used to form the select gate.07-01-2010
20100163963NONVOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - There is provided a nonvolatile memory device having a tunnel dielectric layer formed over a substrate, the charge capturing layer formed over the tunnel dielectric layer and including a combination of at least one charge storage layer and at least one charge trap layer, a charge blocking layer formed over the charge capturing layer, and a gate electrode formed over the charge blocking layer.07-01-2010
20100219460Semiconductor device and method for manufacturing the same - A semiconductor device including a semiconductor substrate, a tunnel insulation film provided on the surface of the semiconductor substrate, charge trap states at which an electron potential energy is higher than a Fermi level of the semiconductor substrate being provided at part of the tunnel insulation film at least in the vicinity of an interface with the semiconductor substrate, and at least one charge storage layer being provided on the tunnel insulation film, charges supplied from the semiconductor substrate via the tunnel insulation film being accumulated in the charge storage layer.09-02-2010
20110241100STACKED NON-VOLATILE MEMORY DEVICE AND METHODS FOR FABRICATING THE SAME - A stacked non-volatile memory device comprises a plurality of bit line and word line layers stacked on top of each other. The bit line layers comprise a plurality of bit lines that can be formed using advanced processing techniques making fabrication of the device efficient and cost effective. The device can be configured for NAND operation.10-06-2011
20110241099SEMICONDUCTOR DEVICE INCLUDING TRANSISTOR AND FUSE CIRCUIT AND SEMICONDUCTOR MODULE INCLUDING THE SAME - A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate, a first node impurity region, a second node impurity region, a third node impurity region, and an insulating layer. The first through third node impurity regions are disposed in the semiconductor substrate. Each of the first through third node impurity regions has a longitudinal length, a transverse length and a thickness respectively corresponding to first through third directions, which are perpendicular with respect to each other. The first node impurity region is parallel to the second and third node impurity regions, which are disposed in the substantially same line. The insulating layer is located between the first through third node impurity regions in the semiconductor substrate.10-06-2011
20110241097Semiconductor device and manufacturing method thereof - Device isolation regions for isolating a device forming region are formed over a substrate. Subsequently, a gate insulation film is formed over the device forming region. Then, a lower gate electrode film comprised of a metal nitride film is formed over the gate insulation film. Further, a heat treatment is performed to the lower gate electrode film and then an upper gate electrode film is formed over the lower gate electrode film.10-06-2011
20110084330LOCAL INTERCONNECT HAVING INCREASED MISALIGNMENT TOLERANCE - A method is provided for forming an interconnect in a semiconductor memory device. The method includes forming a pair of source select transistors on a substrate. A source region is formed in the substrate between the pair of source select transistors. A first inter-layer dielectric is formed between the pair of source select transistors. A mask layer is deposited over the pair of source select transistors and the inter-layer dielectric, where the mask layer defines a local interconnect area between the pair of source select transistors having a width less than a distance between the pair of source select transistors. The semiconductor memory device is etched to remove a portion of the first inter-layer dielectric in the local interconnect area, thereby exposing the source region. A metal contact is formed in the local interconnect area.04-14-2011
20110084329NON-VOLATILE MEMORY DEVICE - A non-volatile memory device includes a semiconductor layer including a cell region and a peripheral region, a cell region gate structure disposed in the cell region of the semiconductor layer, and wherein the cell region gate structure includes a tunneling insulating layer and a first blocking insulating layer, a second blocking insulating layer, and a third blocking insulating layer. The non-volatile memory device further includes a peripheral region gate structure formed in the peripheral region of the semiconductor layer. The peripheral region gate structure includes a first peripheral region insulating layer including a same material as a material included in the tunneling insulating layer and a second peripheral region insulating layer including a same material as a material included in the third blocking insulating layer.04-14-2011
20090321813NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - A nonvolatile semiconductor memory device includes: a stacked body with a plurality of insulating films and electrode films alternately stacked therein, through which a through hole extending in the stacking direction is formed; a semiconductor pillar buried inside the through hole; and a charge storage layer located on both sides of each of the electrode films in the stacking direction and insulated from the electrode film and the semiconductor pillar.12-31-2009
20090321815Non-volatile memory device and method of fabricating the same - A non-volatile memory device, including a substrate of a first conductivity type, the substrate including a plurality of wells of a second conductivity type, a plurality of memory cells in one of the plurality of wells of the second conductivity type, and a peripheral circuit including at least one first transistor of the second conductivity type on the substrate, and at least one second transistor of the first conductivity type in another one of the plurality of wells of the second conductivity type.12-31-2009
20090218614SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor storage device has a plurality of word lines formed with a predetermined interval on a semiconductor substrate, a selection transistor provided at an end portion of the plurality of word lines, a first insulating film formed so as to cover side surfaces of the word lines, a side surface of the selection transistor, and a surface of the semiconductor substrate between the word lines, a high-permittivity film formed on the first insulation film, a second insulating film formed so as to cover the upper surface of the word lines and the selection transistor, a first air-gap portion located between the word lines and surrounded by the high-permittivity film and the second insulating film, and a second air-gap portion formed via the first insulating film and the high-permittivity film at a sidewall portion, which opposes the selection transistor, of the word line adjacent to the selection transistor, an upper portion of the second air-gap portion being covered by the second insulating film.09-03-2009
20090321812SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THEREOF - The present invention provides a semiconductor device including a semiconductor substrate provided with a trench section; a tunnel insulating film covering an inner surface of the trench section; a trap layer provided in contact with the tunnel insulating film on an inner surface of an upper portion of the trench section; a top insulating film provided in contact with the trap layer; a gate electrode embedded in the trench section, and provided in contact with the tunnel insulating film at a lower portion of the trench section and in contact with the top insulating film at the upper portion of the trench section, in which the trap layer and the top insulating film, in between the lower portion of the trench section and the upper portion of the trench section, extend and protrude from both sides of the trench section so as to be embedded in the gate electrode, and a method for manufacturing thereof.12-31-2009
20100038701INTEGRATED TWO DEVICE NON-VOLATILE MEMORY - The non-volatile memory cell is comprised of the series integration of a fixed threshold element and a bistable element. The fixed threshold element is formed over a substrate with a gate insulator layer and an access gate having a nitride layer. The bistable element is formed adjacent to the fixed threshold element by a tunnel insulator over the substrate, a charge trapping layer over the tunnel insulator, a charge blocking layer over the trapping layer, and a control gate, having a nitride layer, over the charge blocking layer. In one embodiment, the gate insulator, tunnel insulator and charge trapping layers are all SiON with thicknesses that depend on the designed programming voltage. The control gate can be formed overlapping the access gate or the access gate can be formed overlapping the control gate.02-18-2010
20100038698HIGH DENSITY FLASH MEMORY DEVICE , CELL STRING FABRICATING METHOD THEREOF - A flash memory cell string and a method of fabricating the same are provided. The flash memory cell string includes a plurality of cell devices and switching devices connected to ends of the cell devices. Each of the cell devices includes a semiconductor substrate, a tunneling insulating layer, a charge storage node, a control insulating layer, and a control electrode which are sequentially laminated on the semiconductor substrate. In each cell device, a source/drain region is not formed. The switching device does not include a source or drain region in a side connected to the cell devices. The switching device includes a source or drain region in the other side that is not connected to the cell devices. The source or drain region does or does not overlap the control electrode. Accordingly, it is possible to improve a miniaturization property and performance of NAND flash memory cell devices. If necessary, it is possible to electrically connect cells or cell strings by inducing an inversion layer through a fringing electric field from a control electrode.02-18-2010
20100038699NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - A stacked body is formed on a silicon substrate by stacking a plurality of insulating films and a plurality of electrode films alternately and through-holes are formed to extend in the stacking direction. Next, gaps are formed between the electrode films using etching the insulating films via the through-holes. Charge storage layers are formed along side faces of the through-holes and inner faces of the gaps, and silicon pillars are filled into the through-holes. Thereby, a nonvolatile semiconductor memory device is manufactured.02-18-2010
20100038702Nonvolatile memory device and methods of forming the same - Example embodiments relate to a semiconductor memory device and methods of forming the same. Other example embodiments relate to a nonvolatile memory device and methods of forming the same. The memory device may include memory cells separately formed on a channel region between impurity regions formed on a substrate. The memory cells may each include a memory layer having a tunnel insulating layer, a nano-sized charge storage layer, and a blocking insulating layer and a side gate formed on the memory layer. According to example embodiments, larger scale integration of the nonvolatile memory devices may be achieved and the reliability of the memory devices may increase.02-18-2010
20110175156SEMICONDUCTOR MEMORY DEVICE - In a semiconductor memory device having split-gate MONOS memory cells, disturb resistance during writing by a SSI method is improved. In addition, with an improvement in the disturb resistance of a non-selected memory cell, a reduction in the area occupied by a memory module can be achieved. Over a side surface of a memory gate electrode, a first insulating film is formed between a charge storage film and a second insulating film so that the total thickness of the first and second insulating films over the side surface of the memory gate electrode is larger than the thickness of the second insulating film under the memory gate electrode.07-21-2011
20120241843NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array part, a first contact part, and a peripheral circuit part. The first contact part is juxtaposed with the memory cell array part in a first plane. The peripheral circuit part is juxtaposed with the memory cell array part in the first plane. The memory cell array part includes a first stacked body, a first semiconductor layer, and a memory film. The first contact part includes a first contact part insulating layer, and a plurality of first contact electrodes. The peripheral circuit part includes a peripheral circuit, a structure body, a peripheral circuit part insulating layer, and a peripheral circuit part contact electrode. A width along an axis perpendicular to the first axis of the peripheral circuit part insulating layer is smaller than a diameter of the first particle.09-27-2012
20120241841NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - According to one embodiment, a semiconductor device, including a substrate, a stacked layer body provided above the substrate, the stacked layer body alternately stacking an insulator and an electrode film one on another, silicon pillars contained with fluorine, the silicon pillar penetrating through and provided in the stacked layer body, a tunnel insulator provided on a surface of the silicon pillar facing to the stacked layer body, a charge storage layer provided on a surface of the tunnel insulator facing to the stacked layer body, a block insulator provided on a surface of the charge storage layer facing to the stacked layer body, the block insulator being in contact with the electrode film, and an embedded portion provided in the silicon pillars.09-27-2012
20100059812FLASH MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - Disclosed are a flash memory device and a method for manufacturing the same. The flash memory device includes a semiconductor substrate having a unit cell defined by an isolation layer, a gate formed over the semiconductor substrate, LDD areas formed at shallow areas of the semiconductor substrate at both sides of the gate, a source and a drain formed at deep areas of the semiconductor substrate while making contact with the LDD areas, and spacers formed at sidewalls of the gate. The spacer includes a first oxide layer pattern, a nitride layer pattern, and a second oxide layer pattern, and the semiconductor substrate includes silicon, so that a silicon-oxide-nitride-oxide-silicon structure for the flash memory device is formed by the silicon of the semiconductor substrate and the spacer at the drain side of the gate.03-11-2010
20100059811NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - In a nonvolatile semiconductor memory device, a stacked body is provided on a silicon substrate by alternately stacking pluralities of isolation dielectric films and electrode films, a through-hole is formed in the stacked body to extend in the stacking direction, a memory film is formed by stacking a block layer, a charge layer and a tunnel layer in this order at an inner face of the through-hole, and thereby a silicon pillar is buried in the through-hole. At this time, the electrode film is protruded further than the isolation dielectric film toward the silicon pillar at the inner face of the through-hole, and an end face of the isolation dielectric film has a curved shape displacing toward the silicon pillar side as the electrode film is approached.03-11-2010
20100059809NON-VOLATILE MEMORY AND METHOD OF FABRICATING THE SAME - A method of fabricating a non-volatile memory is provided. First, a bottom oxide layer is formed on a substrate. Thereafter, a silicon-rich nitride layer is formed on the bottom oxide layer by using NH03-11-2010
20090101966Method of identifying logical information in a programming and erasing cell by on-side reading scheme - A method of identifying logical information in a cell, particularly in a programming by hot hole injection nitride electron storage (PHINES) cell by one-side reading scheme is disclosed. The method comprise steps of: erasing the first region and the second region of PHINES cell by increasing a local threshold voltage (Vt) to a certain value; programming at least one of the first region and the second region of the PHINES cell by hot hole injection; and reading a logical state of the PHINES cell by measuring an output current of one of the first region and the second region; wherein different quantity of the output current is caused by interaction between different quantity of the hot hole stored in the first region and the second region, so as to determine the logical state of the PHINES cell by one-side reading scheme.04-23-2009
20110101442Multi-Layer Charge Trap Silicon Nitride/Oxynitride Layer Engineering with Interface Region Control - A non-volatile memory semiconductor device comprising a semiconductor substrate having a channel and a gate stack above the channel. The gate stack comprises a tunnel layer adjacent to the channel, a charge trapping layer above the tunnel layer, a charge blocking layer above the charge trapping layer, a control gate above the charge blocking layer, and an intentionally incorporated interface region between the charge trapping layer and the charge blocking layer. The charge trapping layer comprises a compound including silicon and nitrogen, the charge blocking layer contains an oxide of a charge blocking component, and the interface region comprises a compound including silicon, nitrogen and the charge blocking component. The tunnel layer may comprise up to three tunnel sub-layers, the charge trapping layer may comprise two trapping sub-layers, and the charge blocking layer may comprise up to five blocking sub-layers. Various gate stack formation techniques can be employed.05-05-2011
20110248331SEMICONDUCTOR DEVICE WITH MINI SONOS CELL AND METHOD FOR FABRICATING THE SAME - A semiconductor device with mini silicon-oxide-nitride-oxide-silicon (mini-SONOS) cell is disclosed. The semiconductor device includes: a semiconductor substrate; a shallow trench isolation (STI) embedded in the semiconductor substrate; a logic device partially overlapping the STI; and a SONOS cell formed in the overlapped region of the logic device and the STI.10-13-2011
20100123181NONVOLATILE MEMORY DEVICES INCLUDING MULTIPLE CHARGE TRAPPING LAYERS - A charge trap nonvolatile memory device includes a gate electrode on a substrate; a charge trapping layer between the substrate and the gate electrode; a charge tunneling layer between the charge trapping layer and the substrate; and a charge blocking layer between the gate electrode and the charge trapping layer. The charge trapping layer includes a first charge trapping layer having a first energy band gap and a second charge trapping layer having a second energy band gap that is different than the first energy band gap. The first and second charge trapping layers are repeatedly stacked and the first and second energy band gaps are smaller than energy band gaps of the charge tunneling layer and the charge blocking layer.05-20-2010
20110101443NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - Provided are a nonvolatile memory device and a method for fabricating the same. The nonvolatile memory device may include a stacked structure, a semiconductor pattern, an information storage layer, and a fixed charge layer. The stacked structure may be disposed over a semiconductor substrate. The stacked structure may include conductive patterns and interlayer dielectric patterns alternately stacked therein. The semiconductor pattern may be connected to the semiconductor substrate by passing through the stacked structure. The information storage layer may be disposed between the semiconductor pattern and the conductive patterns. The fixed charge layer may be disposed between the semiconductor pattern and the interlayer dielectric pattern. The fixed charge layer may include fixed charges. Electrical polarity of the fixed charges may be equal to electrical polarity of majority carriers of the semiconductor pattern.05-05-2011
20110073934SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The invention provides a semiconductor device and its manufacturing method in which a memory transistor and a plurality of thin film transistors that have gate insulating films with different thicknesses are fabricated over a substrate. The invention is characterized by the structural difference between the memory transistor and the plurality of thin film transistors. Specifically, the memory transistor and some of the plurality of thin film transistors are provided to have a bottom gate structure while the other thin film transistors are provided to have a top gate structure, which enables the reduction of characteristic defects of the transistor and simplification of its manufacturing process.03-31-2011
20110073933SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory device includes: a semiconductor substrate; a first device-isolation insulation film that divides the semiconductor substrate at a first transistor region into first device regions; a second device-isolation insulation film that divides the semiconductor substrate at a second transistor region into second device regions; a plurality of first transistors formed in the first transistor region; a plurality of second transistors formed in the second transistor region; and an anti-inversion diffusion layer formed under the first device-isolation insulation film. Each of the first and second transistors includes, respectively: a first and second gate insulation film provided respectively on the first and second device regions; a first and second gate electrode provided respectively on the first and second gate insulation films; and a first and second diffusion layer formed respectively on a surface of the semiconductor substrate so as to sandwich the first and second gate electrodes.03-31-2011
20110254079NON-VOLATILE MEMORY DEVICES - A non-volatile memory device can include a plurality of parallel active regions that are defined by a plurality of device isolation layers formed on a semiconductor substrate, where each of the plurality of parallel active regions extends in a first direction and has a top surface and sidewalls. A plurality of parallel word lines can extend in a second direction and cross over the plurality of parallel active regions at intersecting locations. A plurality of charge storage layers can be disposed at the intersecting locations between the plurality of parallel active regions and the plurality of parallel word lines. Each of the plurality of charge storage layers at the intersecting locations can have a first side and a second side that is parallel to the second direction and can have a first length, a third side and a fourth side that are parallel to the first direction and can have a second length, where the first length is less than the second length.10-20-2011
20110248333INTEGRATION OF RESISTORS AND CAPACITORS IN CHARGE TRAP MEMORY DEVICE FABRICATION - A semiconductor device structure and method to form the same. The semiconductor device structure includes a non-volatile charge trap memory device and a resistor or capacitor. A dielectric layer of a charge trap dielectric stack of the memory device is patterned to expose a portion of a first conductive layer peripheral to the memory device. A second conductive layer formed over the dielectric layer and on the exposed portion of the first conductive layer is patterned to form resistor or capacitor contacts and capacitor plates.10-13-2011
20120267702VERTICAL MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - A device includes a first GSL, a plurality of first word lines, a first SSL, a plurality of first insulation layer patterns, and a first channel. The first GSL, the first word lines, and the first SSL are spaced apart from each other on a substrate in a first direction perpendicular to a top surface of a substrate. The first insulation layer patterns are between the first GSL, the first word lines and the first SSL. The first channel on the top surface of the substrate extends in the first direction through the first GSL, the first word lines, the first SSL, and the first insulation layer patterns, and has a thickness thinner at a portion thereof adjacent to the first SSL than at portions thereof adjacent to the first insulation layer patterns.10-25-2012
20110163371METHODS OF FABRICATING NONVOLATILE SEMICONDUCTOR MEMORY DEVICES - A nonvolatile semiconductor memory device includes a plurality of pillars protruding upward from a semiconductor substrate and having respective top surfaces and opposing sidewalls, a bit line on the top surfaces of the pillars and connecting a row of the pillars along a first direction, a pair of word lines on the opposing sidewalls of one of the plurality of pillars and crossing beneath the bit line, and a pair of memory layers interposed between respective ones of the pair of word lines and the one of the plurality of pillars. Methods of fabricating a nonvolatile semiconductor memory device include selectively etching a semiconductor substrate to form pluralities of stripes having opposing sidewalls and being arranged along a direction, forming memory layers and word lines along the sidewalls of the stripes selectively etching the stripes to form a plurality of pillars, and forming a bit line connecting the pillars and crossing above the word lines.07-07-2011
20090001450Non-volatile memory device and method of fabricating the same - Provided are a non-volatile memory device and a method of fabricating the same. The non-volatile memory device may include a lower semiconductor substrate, an upper semiconductor pattern on the lower semiconductor substrate, a device isolation pattern defining an active region in the lower semiconductor substrate and the upper semiconductor pattern, a lower charge storage layer between the upper semiconductor pattern and the lower semiconductor substrate, a gate conductive structure crossing over the upper semiconductor pattern, a first upper charge storage layer and a second upper charge storage layer spaced apart from each other between the gate conductive structure and the upper semiconductor pattern, and a source/drain region in the upper semiconductor pattern on both sides of the gate conductive structure.01-01-2009
20090001449SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - The present invention provides a technology capable of reducing an area occupied by a nonvolatile memory while improving the reliability of the nonvolatile memory. In a semiconductor device, the structure of a code flash memory cell is differentiated from that of a data flash memory cell. More specifically, in the code flash memory cell, a memory gate electrode is formed only over the side surface on one side of a control gate electrode to improve a reading speed. In the data flash memory cell, on the other hand, a memory gate electrode is formed over the side surfaces on both sides of a control gate electrode. By using a multivalued memory cell instead of a binary memory cell, the resulting data flash memory cell can have improved reliability while preventing deterioration of retention properties and reduce its area.01-01-2009
20100264482MEMORY CELLS CONFIGURED TO ALLOW FOR ERASURE BY ENHANCED F-N TUNNELING OF HOLES FROM A CONTROL GATE TO A CHARGE TRAPPING MATERIAL - Memory cells including a control gate, a charge trapping material, and a charge blocking material between the control gate and the charge trapping material. The charge blocking material is configured to allow for erasure of the memory cell by enhanced F-N tunneling of holes from the control gate to the charge trapping material.10-21-2010
20080315292Atomic Layer Deposition Method and Semiconductor Device Formed by the Same - There is provided a method of manufacturing a semiconductor device, including the following steps: flowing a first precursor gas to the semiconductor substrate within a ALD chamber to form a first discrete monolayer on the semiconductor substrate; flowing an inert purge gas to the semiconductor substrate within the ALD chamber; flowing a second precursor gas to the ALD chamber to react with the first precursor gas which has formed the first monolayer, thereby forming a first discrete compound monolayer; and flowing an inert purge gas; forming a first dielectric layer to cover the discrete compound monolayer; forming a second third monolayer above first dielectric layer; and forming a second discrete compound monolayer; and forming a second dielectric layer to cover the second discrete compound monolayer above the first dielectric layer. There is also provided a semiconductor device formed by the ALD method.12-25-2008
20080315294DUAL-GATE DEVICE AND METHOD - A memory circuit having dual-gate memory cells and a method for fabricating such a memory circuit are disclosed. The dual-gate memory cells each include a memory device and an access device sharing a semiconductor layer, with their respective channel regions provided on different surfaces of the semiconductor layer. The semiconductor layer has a thickness such that a sensitivity parameter relating an electrical interaction between the gate electrodes of the access device and the memory device is less than a predetermined value. The dual-gate memory cells can be used as building blocks for a non-volatile memory array, such as a memory array formed by NAND-strings. In such an array, during programming of a nearby memory device in a NAND string, in NAND-strings not to be programmed, if inversion regions are allowed to be formed in the semiconductor layer, or if the semiconductor layer is allowed to electrically float, electrical interaction exists between the access devices and the memory devices to inhibit programming of the memory devices.12-25-2008
20080315293Atomic Layer Deposition Method and Semiconductor Device Formed by the Same - There is provided a method of manufacturing a semiconductor device, including the following steps: flowing a first precursor gas to the semiconductor substrate within the ALD chamber to form a first discrete monolayer on the semiconductor substrate; flowing an inert purge gas to the semiconductor substrate within the ALD chamber; flowing a second precursor gas to the ALD chamber to react with the first precursor gas which has formed the first monolayer, thereby forming a first discrete compound monolayer; and flowing an inert purge gas; and forming a second discrete compound monolayer above the semiconductor substrate by the same process as that for forming the first discrete compound monolayer. There is also provided a semiconductor device in which the charge trapping layer is a dielectric layer containing the first and second discrete compound monolayers formed by the ALD method.12-25-2008
20080315291NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A nonvolatile semiconductor memory device has a plurality of memory strings each including a plurality of electrically rewritable memory cells serially connected. The memory string includes a columnar semiconductor portion extending in the vertical direction from a substrate, a first charge storage layer formed adjacent to the columnar semiconductor portion and configured to accumulate charge, a first block insulator formed adjacent to the first charge storage layer, and a first conductor formed adjacent to the first block insulator.12-25-2008
20090108332Non-volatile memory device with charge trapping layer and method for fabricating the same - Disclosed herein are a non-volatile memory device and a method of manufacturing the same. The non-volatile memory device includes a substrate, a tunneling layer disposed on the substrate, a charge trapping layer disposed on the tunneling layer, a blocking layer disposed on the charge trapping layer, and a control gate electrode disposed on the blocking layer. The blocking layer in contact with the charge trapping layer includes an aluminum nitride layer.04-30-2009
20110175158DUAL CHARGE STORAGE NODE MEMORY DEVICE AND METHODS FOR FABRICATING SUCH DEVICE - A dual node memory device and methods for fabricating the device are provided. In one embodiment the method comprises forming a layered structure with an insulator layer, a charge storage layer, a buffer layer, and a sacrificial layer on a semiconductor substrate. The layers are patterned to form two spaced apart stacks and an exposed substrate portion between the stacks. A gate insulator and a gate electrode are formed on the exposed substrate, and the sacrificial layer and buffer layer are removed. An additional insulator layer is deposited overlying the charge storage layer to form insulator-storage layer-insulator memory storage areas on each side of the gate electrode. Sidewall spacers are formed at the sidewalls of the gate electrode overlying the storage areas. Bit lines are formed in the substrate spaced apart from the gate electrode, and a word line is formed that contacts the gate electrode and the sidewall spacers.07-21-2011
20090050954Non-volatile memory device including charge trap layer and method of manufacturing the same - Provided are a non-volatile memory device and a method of manufacturing the non-volatile memory device. The non-volatile memory device includes a charge trap layer having a crystalline material. In the method, a tunneling insulating layer is formed on a substrate, and a crystalline charge trap layer is formed on the tunneling insulating layer.02-26-2009
20090050955NONVOLATILE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A charge storage layer interposed between a memory gate electrode and a semiconductor substrate is formed shorter than a gate length of the memory gate electrode or a length of insulating films so as to make the overlapping amount of the charge storage layer and a source region to be less than 40 nm. Therefore, in the write state, since the movement in the transverse direction of the electrons and the holes locally existing in the charge storage layer decreases, the variation of the threshold voltage when holding a high temperature can be reduced. In addition, the effective channel length is made to be 30 nm or less so as to reduce an apparent amount of holes so that coupling of the electrons with the holes in the charge storage layer decreases; therefore, the variation of the threshold voltage when holding at room temperature can be reduced.02-26-2009
20110254078METHOD FOR DEPOSITING SILICON NITRIDE FILM, COMPUTER-READABLE STORAGE MEDIUM, AND PLASMA CVD DEVICE - Provided is a method for depositing a silicon nitride film in a plasma CVD device which introduces microwaves into a process chamber by a planar antenna having a plurality of apertures, and the method including setting the pressure in the process chamber within a range from 10 Pa to 133.3 Pa and performing plasma CVD by using film formation gas including a silicon containing compound gas and a nitrogen gas while applying an RF bias to the wafer by supplying high-frequency power with an output density within a range from 0.009 W/cm10-20-2011
20110254077SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes a plurality of gate structures disposed on a substrate. Respective gate structures may include a lower control gate layer and an upper control gate layer. The upper control gate layer may be disposed on the lower control gate layer and may include a different material from the lower control gate layer. The semiconductor device may further include insulation patterned layers disposed in gap regions defined between the gate structures adjacent to each other. Upper surfaces of the insulation patterned layers may be lower than an upper surface of the lower control gate layer.10-20-2011
20080251836NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a non-volatile memory device includes forming a charge tunneling layer composed of a hafnium silicate (HfSi10-16-2008
20120032253NONVOLATILE SEMICONDUCTOR MEMORY AND METHOD OF MANUFACTURING THE SAME - A nonvolatile semiconductor memory has a semiconductor substrate, a first insulating film formed on a channel region on a surface portion of the semiconductor substrate, a charge accumulating layer formed on the first insulating film, a second insulating film formed on the charge accumulating layer, a control gate electrode formed on the second insulating film, and a third insulating film including an Si—N bond that is formed on a bottom surface and side surfaces of the charge accumulating layer.02-09-2012
20120032251NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - First and second memory cells have first and second channels, first and second tunnel insulating films, first and second charge storage layers formed of an insulating film, first and second block insulating films, and first and second gate electrodes. A first select transistor has a third channel, a first gate insulating film, and a first gate electrode. The first channel includes a first-conductivity-type region and a second-conductivity-type region which is formed on at least a part of the first-conductivity-type region and whose conductivity type is opposite to the first conductivity type. The third channel includes the first-conductivity-type region and the second-conductivity-type region formed on the first-conductivity-type region. The number of data stored in the first memory cell is smaller than that of data stored in the second memory cell.02-09-2012
20080203467NROM FLASH MEMORY DEVICES ON ULTRATHIN SILICON - An NROM flash memory cell is implemented in an ultra-thin silicon-on-insulator structure. In a planar device, the channel between the source/drain areas is normally fully depleted. An oxide layer provides an insulation layer between the source/drain areas and the gate insulator layer on top. A control gate is formed on top of the gate insulator layer. In a vertical device, an oxide pillar extends from the substrate with a source/drain area on either side of the pillar side. Epitaxial regrowth is used to form ultra-thin silicon body regions along the sidewalls of the oxide pillar. Second source/drain areas are formed on top of this structure. The gate insulator and control gate are formed on top.08-28-2008
20080203466METHOD OF MANUFACTURING A NONVOLATILE SEMICONDUCTOR MEMORY DEVICE, AND A NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - For enhancing the high performance of a non-volatile semiconductor memory device having an MONOS type transistor, a non-volatile semiconductor memory device is provided with MONOS type transistors having improved performance in which the memory cell of an MONOS non-volatile memory comprises a control transistor and a memory transistor. A control gate of the control transistor comprises an n-type polycrystal silicon film and is formed over a gate insulative film comprising a silicon oxide film. A memory gate of the memory transistor comprises an n-type polycrystal silicon film and is disposed on one of the side walls of the control gate. The memory gate comprises a doped polycrystal silicon film with a sheet resistance lower than that of the control gate comprising a polycrystal silicon film formed by ion implantation of impurities to the undoped silicon film.08-28-2008
20130168756SOURCE/DRAIN ZONES WITH A DELECTRIC PLUG OVER AN ISOLATION REGION BETWEEN ACTIVE REGIONS AND METHODS - Devices, memory arrays, and methods are disclosed. In an embodiment, one such device has a source/drain zone that has first and second active regions, and an isolation region and a dielectric plug between the first and second active regions. The dielectric plug may extend below upper surfaces of the first and second active regions and may be formed of a dielectric material having a lower removal rate than a dielectric material of the isolation region for a particular isotropic removal chemistry.07-04-2013
20130168757NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A nonvolatile memory device includes a channel layer extending in a vertical direction from a substrate, a plurality of interlayer dielectric layers and word lines alternately stacked along the channel layer over the substrate; a bit line formed under plurality of interlayer dielectric layers and word lines, coupled to the channel layer, and extending in a direction crossing the word lines, and a common source layer coupled to the channel layer and formed over the plurality of interlayer dielectric layers and word lines.07-04-2013
20100320528THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE - In a three-dimensional semiconductor memory device, the device includes a semiconductor substrate having a recessed region, an active pattern extending in a direction transverse to the recessed region, an insulating pillar being adjacent to the active pattern and extending in the direction transverse to the recessed region, and a lower select gate facing the active pattern and extending horizontally on the semiconductor substrate. The active pattern is disposed between the insulating pillar and the lower select gate.12-23-2010
20100320527NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - A nonvolatile semiconductor memory device according to embodiment includes: a semiconductor substrate having an upper portion being partitioned into a plurality of semiconductor portions extending in a first direction; a charge storage film provided on the semiconductor portion; a word-line electrode provided on the semiconductor substrate and extending in a second direction intersecting with the first direction; and a pair of selection gate electrodes provided on both sides of the word-line electrode in the first direction on the semiconductor substrate and extending in the second direction, a shortest distance between a corner portion of each of the semiconductor portions and each of the selection gate electrodes being longer than a shortest distance between the corner portion of the semiconductor portion and the word-line electrode in a cross section parallel to the second direction.12-23-2010
20100320526NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - A nonvolatile semiconductor memory device includes: a semiconductor substrate; a memory unit; and a circuit unit provided between the semiconductor substrate and the memory unit. The memory unit includes: a stacked structural unit having electrode films alternately stacked with inter-electrode-film insulating films; a semiconductor pillar piercing the stacked structural unit; and a storage unit provided corresponding to an intersection between the electrode films and the semiconductor pillar. The circuit unit includes first and second transistors having different conductivity type, a first interconnect, and first and second contact plugs. The first interconnect includes silicide provided on a side of the first and second transistors opposite to the semiconductor substrate. The first contact plug made of polysilicon of the first conductivity type connects the first interconnect to the first transistor. The second contact plug made of polysilicon of the second conductivity type connects the first interconnect to the second transistor.12-23-2010
20100320525NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device includes: fin-shaped control gate electrodes formed on an insulating layer; and a body layer having a channel region arranged to cross the control gate electrodes and embedded in the control gate electrodes sequentially via a first insulating layer, a charge storage layer, and a second insulating layer.12-23-2010
20110254076HIGH DENSITY FLASH MEMORY CELL DEVICE, CELL STRING AND FABRICATION METHOD THEREFOR - Provided is an ultra highly-integrated flash memory cell device. The cell device includes a semiconductor substrate, a first doping semiconductor area formed on the semiconductor substrate, a second doping semiconductor area formed on the first doping semiconductor area, and a tunneling insulating layer, a charge storage node, a control insulating layer, and a control electrode which are sequentially formed on the second doping semiconductor area. The first and second doping semiconductor areas are doped with impurities of the different semiconductor types According to the present invention, it is possible to greatly improve miniaturization characteristics and performance of the cell devices in conventional NOR or NAND flash memories. Unlike conventional transistor type cell devices, the cell device according to the present invention does not have a channel and a source/drain. Therefore, in comparison with the conventional memories, the fabricating process can be simplified, and the problem such as cross-talk or read disturb can be greatly reduced.10-20-2011
20110073932NON VOLATILE SEMICONDUCTOR MEMORY DEVICE - A non volatile semiconductor memory device includes: a semiconductor substrate comprising element regions; gate structures each comprising a first gate insulation film, a charge storage layer, a second gate insulation film, and a control gate; element isolation insulation films defining the element regions and electrically isolating the element regions; impurity diffusion layers in the element regions; a third gate insulation film of a first insulation material located between the gate structures; and a fourth gate insulation film of a second insulation material which is different from the first insulation material configured to be in contact with side walls of the gate structures. A bottom face of the fourth gate insulation film is located so as to be remote from a surface of the semiconductor substrate by a distance equal to at least half of a height of the charge storage layer.03-31-2011
20100283100SEMICONDUCTOR MEMORY COMPRISING DUAL CHARGE STORAGE NODES AND METHODS FOR ITS FABRICATION - A dual charge storage node memory device and methods for its fabrication are provided. In one embodiment a dielectric plug is formed comprising a first portion recessed into a semiconductor substrate and a second portion extending above the substrate. A layer of semiconductor material is formed overlying the second portion. A first layered structure is formed overlying a first side of the second portion of the dielectric plug, and a second layered structure is formed overlying a second side, each of the layered structures overlying the layer of semiconductor material and comprising a charge storage layer between first and second dielectric layers. Ions are implanted into the substrate to form a first bit line and second bit line, and a layer of conductive material is deposited and patterned to form a control gate overlying the dielectric plug and the first and second layered structures.11-11-2010
20100283097MOS SEMICONDUCTOR MEMORY DEVICE - The invention provides a MOS semiconductor memory device that achieves excellent data retention characteristics while also achieving high-speed data write performance, low-power operation performance, and high reliability. A MOS semiconductor memory device 601 includes a first insulating film 11-11-2010
20100283098NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND A METHOD OF MANUFACTURING THE SAME - A nonvolatile semiconductor memory device includes a plurality of bit line diffusion layers formed in a semiconductor region, and extending in a row direction; a plurality of first insulating films, each being formed on the semiconductor region and between adjacent two of the bit line diffusion layers, and including a charge trapping film; a plurality of bit line insulating films formed above the respective bit line diffusion layers; and a plurality of word lines formed above the semiconductor region to cover the first insulating films and the bit line insulating films, intersecting the bit line diffusion layers, and extending in a column direction. The bit line insulating films have smaller thicknesses than the first insulating films, and upper surfaces of the bit line insulating films are parallel to upper surfaces of the first insulating films.11-11-2010
20100283096SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device including a conductive layer, a diffusion barrier layer formed over the conductive layer, including a refractory metal compound, and acquired after a surface treatment, and a metal silicide layer formed over the diffusion barrier layer. The adhesion between a diffusion barrier layer and a metal silicide layer may be improved by increasing the surface energy of the diffusion barrier layer through a surface treatment. Therefore, although the metal silicide layer is fused in a high-temperature process, it is possible to prevent a void from being caused at the interface between the diffusion barrier layer and the metal silicide layer. Moreover, it is possible to increase the adhesion between a conductive layer and the diffusion barrier layer by increasing the surface energy of the conductive layer through the surface treatment.11-11-2010
20110001183Memory device and method of fabricating the same - A memory device and a method of fabricating the same are provided. The memory device includes a tunneling dielectric layer on a substrate, a charge storage layer on the tunneling dielectric layer, a blocking dielectric layer on the charge storage layer, the blocking dielectric layer including a first dielectric layer having silicon oxide, a second dielectric layer on the first dielectric layer and having aluminum silicate, and a third dielectric layer formed on the second dielectric layer and having aluminum oxide, and an upper electrode on the blocking dielectric layer.01-06-2011
20110133268Memory Cells - Some embodiments include memory cells having vertically-stacked charge-trapping zones spaced from one another by dielectric material. The dielectric material may comprise high-k material. One or more of the charge-trapping zones may comprise metallic material. Such metallic material may be present as a plurality of discrete isolated islands, such as nanodots. Some embodiments include methods of forming memory cells in which two charge-trapping zones are formed over tunnel dielectric, with the zones being vertically displaced relative to one another, and with the zone closest to the tunnel dielectric having deeper traps than the other zone. Some embodiments include electronic systems comprising memory cells. Some embodiments include methods of programming memory cells having vertically-stacked charge-trapping zones.06-09-2011
20110169070SEMICONDUCTOR DEVICE - For providing a cheap semiconductor memory device with improving reliability by level of a cell, in the place of escaping from defects on memory cells electrically, through such as ECC, and further for providing a cell structure enabling scaling-down in the vertical direction with maintaining the reliability, in a semiconductor memory device, upon which high-speeded read-out operation is required, a charge storage region is constructed with particles made from a large number of semiconductor charge storage small regions, each being independent, thereby increasing the reliability by the cell level.07-14-2011
20110095357Semiconductor Constructions, Methods Of Forming Transistor Gates, And Methods Of Forming NAND Cell Units - Some embodiments include methods of forming charge storage transistor gates and standard FET gates in which common processing is utilized for fabrication of at least some portions of the different types of gates. FET and charge storage transistor gate stacks may be formed. The gate stacks may each include a gate material, an insulative material, and a sacrificial material. The sacrificial material is removed from the FET and charge storage transistor gate stacks. The insulative material of the FET gate stacks is etched through. A conductive material is formed over the FET gate stacks and over the charge storage transistor gate stacks. The conductive material physically contacts the gate material of the FET gate stacks, and is separated from the gate material of the charge storage transistor gate stacks by the insulative material remaining in the charge storage transistor gate stacks. Some embodiments include gate structures.04-28-2011
20110095355SPLIT CHARGE STORAGE NODE OUTER SPACER PROCESS - Memory cells containing two split sub-lithographic charge storage nodes on a semiconductor substrate and methods for making the memory cells are provided. The methods can involve forming two split sub-lithographic charge storage nodes by using spacer formation techniques. By removing an exposed portion of a fist poly layer between sloping side surfaces or outer surfaces of spacers while leaving portions of the first poly layer protected by the spacers, the method can provide two split sub-lithographic first poly gates. Further, by removing an exposed portion of a charge storage layer between sloping side surfaces or outer surfaces of spacers, the method can provide two split, narrow portions of the charge storage layer, which subsequently form two split sub-lithographic charge storage nodes.04-28-2011
20110095354NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A nonvolatile semiconductor memory device is provided in such a manner that a semiconductor layer is formed over a substrate, a charge accumulating layer is formed over the semiconductor layer with a first insulating layer interposed therebetween, and a gate electrode is provided over the charge accumulating layer with a second insulating layer interposed therebetween. The semiconductor layer includes a channel formation region provided in a region overlapping with the gate electrode, a first impurity region for forming a source region or drain region, which is provided to be adjacent to the channel formation region, and a second impurity region provided to be adjacent to the channel formation region and the first impurity region. A conductivity type of the first impurity region is different from that of the second impurity region.04-28-2011
20110095353ONE-TRANSISTOR CELL SEMICONDUCTOR ON INSULATOR RANDOM ACCESS MEMORY - Silicon-oxide-nitride-oxide-silicon SONOS-type devices (or BE-SONOS) fabricated in Silicon-On-Insulator (SOI) technology for nonvolatile implementations. An ultra-thin tunnel oxide can be implemented providing for very fast program/erase operations, supported by refresh operations as used in classical DRAM technology. The memory arrays are arranged in divided bit line architectures. A gate injection, DRAM cell is described with no tunnel oxide.04-28-2011
20100155820Flash memory device and manufacturing method of the same - A flash memory device may include a device isolation layer and an active area formed over a semiconductor substrate, a memory gate formed over the active area, and a control gate formed over the semiconductor substrate including the memory gate, wherein the active area, where a source contact is to be formed, has the same interval spacing as a bit line, and a common source line area, where the source contact is to be formed, has an impurity area connecting neighboring active areas.06-24-2010
20110260236Transistor Constructions and Processing Methods - A transistor construction includes a first floating gate having a first conductive or semiconductive surface and a second floating gate having a second conductive or semiconductive surface. A dielectric region is circumferentially surrounded by the first surface. The region is configured to reduce capacitive coupling between the first and second surfaces. Another transistor construction includes a floating gate having a cavity extending completely through the floating gate from a first surface of the floating gate to an opposing second surface of the floating gate. The floating gate otherwise encloses the cavity, which is filled with at least one dielectric. A method includes closing an upper portion of an opening in insulator material with a gate material during the deposition before filling a lower portion with the gate material. The depositing and closing provide an enclosed cavity within the lower portion of the opening.10-27-2011
20080217682SELECTIVE INCORPORATION OF CHARGE FOR TRANSISTOR CHANNELS - A device and method for selective placement of charge into a gate stack includes forming gate stacks including a gate dielectric adjacent to a transistor channel and a gate conductor and forming doped regions for transistor operation. A layer rich in a passivating element is deposited over the doped regions and the gate stack, and the layer rich the passivating element is removed from selected transistors. The layer rich in the passivating element is than annealed to drive-in the passivating element to increase a concentration of charge at or near transistor channels on transistors where the layer rich in the passivating element is present. The layer rich in the passivating element is removed.09-11-2008
20080217681Charge trap memory device and method of manufacturing the same - Provided are a charge trap memory device and method of manufacturing the same. A charge trap memory device may include a tunnel insulating layer on a substrate, a charge trap layer on the tunnel insulating layer, and a blocking insulating layer formed of a material including Gd or a smaller lanthanide element on the charge trap layer.09-11-2008
20080217679MEMORY UNIT STRUCTURE AND OPERATION METHOD THEREOF - A memory unit is proposed. The memory unit includes a Si substrate, a trapping layer formed on the Si substrate, a first and a second doping regions formed in the Si substrate on either side of the trapping layer, a gate formed on the trapping layer, a first oxide layer formed between the gate and the trapping layer, a high-Dit material layer formed between the Si substrate and the trapping layer, and a second oxide layer formed between the high-Dit material layer and the trapping layer, wherein an interface trap density (Dit) between the high-Dit material layer and the Si substrate is in a rang from 1009-11-2008
20090273019MEMORY DEVICE TRANSISTORS - Method and device embodiments are described for fabricating MOSFET transistors in a semiconductor also containing non-volatile floating gate transistors. MOSFET transistor gate dielectric smiling, or bird's beaks, are adjustable by re-oxidation processing. An additional re-oxidation process is performed by opening a poly-silicon layer prior to forming an inter-poly oxide dielectric provided for the floating gate transistors.11-05-2009
20100038700Semiconductor Device - A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.02-18-2010
20100025752CHARGE TRAP TYPE NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - There is provided a charge trap type non-volatile memory device and a method for fabricating the same, the charge trap type non-volatile memory device including: a tunnel insulation layer formed over a substrate; a charge trap layer formed over the tunnel insulation layer, the charge trap layer including a charge trap polysilicon thin layer and a charge trap nitride-based layer; a charge barrier layer formed over the charge trap layer; a gate electrode formed over the charge barrier layer; and an oxide-based spacer formed over sidewalls of the charge trap layer and provided to isolate the charge trap layer.02-04-2010
20100025753SEMICONDUCTOR DEVICE - Provided is a semiconductor device including: source-drain regions formed on a silicon substrate with a channel forming region sandwiched therebetween; a word gate electrode formed on the channel forming region via a word gate insulating film not including a charge storage layer; a control gate formed on the silicon substrate on one side of the word gate electrode via a trap insulating film including a charge storage layer; and a control gate formed on the silicon substrate on the other side of the word gate electrode via a trap insulating film including a charge storage layer. A bottom of the word gate electrode is made to be higher than the control gate and a bottom of the control gate, and a level difference between the bottoms of the electrodes is made to be larger than a physical film thickness of the word gate insulating film.02-04-2010
20110215394SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor memory device includes a base, a stacked body, a memory film, a channel body, a contact plug, a global bit line, and a plurality of local bit lines. The base has a substrate and a peripheral circuit formed on the substrate. The stacked body has a plurality of conductive layers and insulating layers stacked alternately above the base. The memory film includes a charge storage film provided on an inner wall of a memory hole formed in a stacking direction of the stacked body. The channel body is provided inside the memory film in the memory hole. The contact plug is provided by piercing the stacked body. The global bit line is provided between the peripheral circuit and the stacked body and connected to a lower end portion of the contact plug. The plurality of local bit lines are provided above the stacked body and divided in an extending direction of the plurality of local bit lines. The plurality of local bit lines are connected to the channel body and commonly connected to the global bit line through the contact plug.09-08-2011
20100019310SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes: a semiconductor substrate; a stacked body provided on the semiconductor substrate and having a plurality of insulator layers and a plurality of conductive layers alternately stacked; a semiconductor layer provided inside a through-hole formed so as to pass through the stacked body and extending in a stacking direction of the insulator layers and the conductive layers; and a charge trap layer provided between the conductive layer and the semiconductor layer. A lower part in the semiconductor layer is narrower than an upper part therein, and at least the lowermost layer in the conductive layers is thinner than the uppermost layer therein.01-28-2010
20100019309MULTI-LEVEL FLASH MEMORY STRUCTURE - A multi-level flash memory structure comprises a semiconductor substrate having a protrusion, a plurality of storage structures separated by the protrusion, a dielectric layer overlying the storage structures and the protrusion of the semiconductor substrate, a gate structure positioned on the dielectric layer, and several diffusion regions positioned at the sides of the protrusion. Each of the storage structures includes a charge-trapping site and an insulation structure isolating the charge-trapping site from the semiconductor substrate.01-28-2010
20110018051Integrated Circuit Memory Devices Having Vertical Transistor Arrays Therein and Methods of Forming Same - An integrated circuit device includes a transistor array having a vertical stack of independently controllable gate electrodes therein. A first semiconductor channel region is provided, which extends on a first sidewall of the vertical stack of independently controllable gate electrodes. A first electrically insulating layer is also provided, which extends between the first semiconductor channel region and the first sidewall of the vertical stack of independently controllable gate electrodes. Source and drain regions are provided, which are electrically coupled to first and second ends of the first semiconductor channel region, respectively.01-27-2011
20100187596Self-aligned double patterning for memory and other microelectronic devices - A method for transferring a pattern to one or more microelectronic layers. A first mask layer, having a patterned feature, and a second mask layer, having another patterned feature, are formed. The first mask layer and the second mask layer are at least partially covered with a film, and openings are formed in the film by removing the other patterned feature of the second mask layer. A pattern of a microelectronic layer is then defined by patterning the patterned feature of the first mask layer through the openings in the film. In one example, the patterned feature of the first mask layer is defined by forming spacers adjacent to the other patterned feature. In another example, the other patterned feature of the second mask layer is defined by removing a portion of the other patterned feature via an anisotropic etching process.07-29-2010
20090173991METHODS FOR FORMING RHODIUM-BASED CHARGE TRAPS AND APPARATUS INCLUDING RHODIUM-BASED CHARGE TRAPS - Isolated conductive nanoparticles on a dielectric layer and methods of fabricating such isolated conductive nanoparticles provide charge traps in electronic structures for use in a wide range of electronic devices and systems. In an embodiment, conductive nanoparticles are deposited on a dielectric layer by a plasma-assisted deposition process such that each conductive nanoparticle is isolated from the other conductive nanoparticles to configure the conductive nanoparticles as charge traps.07-09-2009
20090173990STRUCTURES FOR AND METHOD OF SILICIDE FORMATION ON MEMORY ARRAY AND PERIPHERAL LOGIC DEVICES - A memory device and peripheral circuitry on a substrate are described, made by a process that includes forming a charge trapping structure having a first thickness over a first area. A first gate dielectric layer having a second thickness is formed for low-voltage transistors. A second gate dielectric layer having a third thickness, greater than the second thickness, is formed for high-voltage transistors. Polysilicon is deposited and patterned to define word lines and transistor gates. The thickness of the second gate dielectric layer in regions adjacent the gates, and over a source and drain regions, is reduced to a thickness that is close to that of the second thickness.07-09-2009
20110147825NONVOLATILE MEMORY DEVICES INCLUDING DEEP AND HIGH DENSITY TRAPPING LAYERS - A charge trap nonvolatile memory device includes a gate electrode on a substrate; a charge trapping layer between the gate electrode and the substrate, the charge trapping layer having trap sites configured to trap charges; a charge tunneling layer between the trapping layer and the semiconductor substrate; and a charge blocking layer between the gate electrode and the trapping layer. The charge trapping layer comprises a deep trapping layer having a plurality of energy barriers and a high density trapping layer having a trap site density higher than a trap site density of the deep trapping layer.06-23-2011
20120098047GETTERING AGENTS IN MEMORY CHARGE STORAGE STRUCTURES - Memory cells including a charge storage structure having a gettering agent therein can be useful for non-volatile memory devices. Providing for gettering of oxygen from a charge-storage material of the charge storage structure can facilitate a mitigation of detrimental oxidation of the charge-storage material.04-26-2012
20120205735NONVOLATILE SEMICONDUCTOR STORAGE DEVICE - In one embodiment, there is provided a nonvolatile semiconductor storage device. The device includes: a plurality of nonvolatile memory cells. Each of the nonvolatile memory cells includes: a first semiconductor layer including a first source region, a first drain region, and a first channel region; a block insulating film formed on the first channel region; a charge storage layer formed on the block insulating film; a tunnel insulating film formed on the charge storage layer; a second semiconductor layer formed on the tunnel insulating film and including a second source region, a second drain region, and a second channel region. The second channel region is formed on the tunnel insulating film such that the tunnel insulating film is located between the second source region and the second drain region. A dopant impurity concentration of the first channel region is higher than that of the second channel region.08-16-2012
20120306000Formation of Field Effect Transistor Devices - A method includes defining active regions on a substrate, forming a dummy gate stack material over exposed portions of the active regions of the substrate and non-active regions of the substrate, removing portions of the dummy gate stack material to expose portions of the active regions and non-active regions of the substrate and define dummy gate stacks, forming a gap-fill dielectric material over the exposed portions of the substrate and the source and drain regions, removing portions of the gap-fill dielectric material to expose the dummy gate stacks, removing the dummy gate stacks to form dummy gate trenches, forming dividers within the dummy gate trenches, depositing gate stack material inside the dummy gate trenches, over the dividers, and the gap-fill dielectric material, and removing portions of the gate stack material to define gate stacks.12-06-2012
20120306001SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a semiconductor substrate having a main surface, a MONOS-type memory cell formed over the main surface and having a channel, an n-channel transistor formed over the main surface, and a p-channel transistor formed over the man surface. Nitride films are formed in a manner to contact the top surfaces of the MONOS-type memory cell, the n-channel transistor, and the p-channel transistor. The nitride films apply stress to the channels of the MONOS-type memory cell, the n-channel transistor, and the p-channel transistor.12-06-2012
20120146127NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A nonvolatile memory device includes a pipe gate having a pipe channel hole; a plurality of interlayer insulation layers and a plurality of gate electrodes alternately stacked over the pipe gate; a pair of columnar cell channels passing through the interlayer insulation layers and the gate electrodes and coupling a pipe channel formed in the pile channel hole; a first blocking layer and a charge trapping and charge storage layer formed on sidewalk of the columnar cell channels; and a second blocking layer formed between the first blocking layer and the plurality of gate electrodes.06-14-2012
20120146126HIGH-K CAPPED BLOCKING DIELECTRIC BANDGAP ENGINEERED SONOS AND MONOS - A blocking dielectric engineered, charge trapping memory cell includes a charge trapping element that is separated from a gate by a blocking dielectric including a buffer layer in contact with the charge trapping element, such as silicon dioxide which can be made with high-quality, and a second capping layer in contact with said one of the gate and the channel. The capping layer has a dielectric constant that is higher than that of the first layer, and preferably includes a high-κ material. The second layer also has a conduction band offset that is relatively high. A bandgap engineered tunneling layer between the channel and the charge trapping element is provided which, in combination with the multilayer blocking dielectric described herein, provides for high-speed erase operations by hole tunneling. In an alternative, a single layer tunneling layer is used.06-14-2012
20120037978NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A nonvolatile semiconductor memory device is provided in such a manner that a semiconductor layer is formed over a substrate, a charge accumulating layer is formed over the semiconductor layer with a first insulating layer interposed therebetween, and a gate electrode is provided over the charge accumulating layer with a second insulating layer interposed therebetween. The semiconductor layer includes a channel formation region provided in a region overlapping with the gate electrode, a first impurity region for forming a source region or drain region, which is provided to be adjacent to the channel formation region, and a second impurity region provided to be adjacent to the channel formation region and the first impurity region. A conductivity type of the first impurity region is different from that of the second impurity region.02-16-2012
20120037977SEMICONDUCTOR DEVICES INCLUDING VERTICAL CHANNEL PATTERN - An insulating pattern is disposed on a surface of a semiconductor substrate and includes a silicon oxynitride film. A conductive pattern is disposed on the insulating pattern. A data storage pattern and a vertical channel pattern are disposed within a channel hole formed to vertically penetrate the insulating pattern and the conductive pattern. The data storage pattern and the vertical channel pattern are conformally stacked along sidewalls of the insulating pattern and the conductive pattern. A concave portion is formed in the semiconductor substrate adjacent to the insulating pattern. The concave portion is recessed relative to a bottom surface of the insulating pattern.02-16-2012
20130200450NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a nonvolatile semiconductor memory device includes a fin structure stacked in order of a first oxide layer, a semiconductor layer and a second oxide layer in a first direction perpendicular to a surface of the semiconductor substrate, the fin structure extending in a second direction parallel to the surface of the semiconductor substrate, and a gate structure stacked in order of a gate oxide layer, a charge storage layer, a block insulating layer and a control gate electrode in a third direction perpendicular to the first and second directions from a surface of the semiconductor layer in the third direction.08-08-2013
20100176441SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREFOR - In a nonvolatile semiconductor memory device of the method which enables a single cell to store more than or equal to 2-bit information, it is possible to prevent wire failure and ensure high operation reliability. The nonvolatile semiconductor memory device 07-15-2010
20110316069NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a nonvolatile semiconductor memory device includes a memory unit and a non-memory unit. The memory unit includes a stacked structure including electrode films stacked in a first direction, and a interelectrode insulating film provided between the electrode films, a select gate electrode stacked with the stacked structure along the first direction, a semiconductor pillar piercing the stacked structure and the select gate electrode along the first direction and a pillar portion memory layer provided between the electrode films and the semiconductor pillar. The non-memory unit includes a dummy conductive film including a portion in a layer being identical to at least one of the electrode films, a dummy select gate electrode in a layer being identical to the select gate electrode, a first non-memory unit contact electrode electrically connected to the dummy conductive and a second non-memory unit contact electrode electrically connected to the dummy select gate.12-29-2011
20110316070CHARGE TRAPPING NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MAKING - The present invention provides a charge trapping non-volatile semiconductor memory device and a method of making the device. The charge trapping non-volatile semiconductor memory device comprises a semiconductor substrate, a source region, a drain region, and, consecutively formed over the semiconductor substrate, a channel insulation layer, a charge trapping layer, a blocking insulation layer, and a gate electrode. The drain region includes a P-N junction, and the source region includes a metal-semiconductor junction formed between the semiconductor substrate and a metal including titanium, cobalt, nickel, platinum or one of their various combinations. The charge trapping non-volatile semiconductor memory device according to the present disclosure has low programming voltage, fast programming speed, low energy consumption, and relatively high device reliability.12-29-2011
20120043601NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - In a nonvolatile semiconductor memory device, a stacked body is formed by alternately stacking dielectric films and conductive films on a silicon substrate and a plurality of through holes extending in the stacking direction are formed in a matrix configuration. A shunt interconnect and a bit interconnect are provided above the stacked body. Conductor pillars are buried inside the through holes arranged in a line immediately below the shunt interconnect out of the plurality of through holes, and semiconductor pillars are buried inside the remaining through holes. The conductive pillars are formed from a metal, or low resistance silicon. Its upper end portion is connected to the shunt interconnect and its lower end portion is connected to a cell source formed in an upper layer portion of the silicon substrate.02-23-2012
20110156131NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - On a silicon substrate is formed a stacked body by alternately stacking a plurality of silicon oxide films and silicon films, a trench is formed in the stacked body, an alumina film, a silicon nitride film and a silicon oxide film are formed in this order on an inner surface of the trench, and a channel silicon crystalline film is formed on the silicon oxide film. Next, a silicon oxide layer is formed at an interface between the silicon oxide film and the channel silicon crystalline film by performing thermal treatment in an oxygen gas atmosphere.06-30-2011
20110156130METHOD FOR FORMING NARROW STRUCTURES IN A SEMICONDUCTOR DEVICE - A method of forming multiple conductive structures in a semiconductor device includes forming spacers adjacent side surfaces of a mask, where the mask and the spacers are formed on a conductive layer. The method also includes etching at least one trench in a portion of the conductive layer not covered by the spacers or the mask. The method may further include depositing a material over the semiconductor device, removing the mask and etching the conductive layer to remove portions of the conductive layer not covered by the spacers or the material, where remaining portions of the conductive layer form the conductive structures.06-30-2011
20110156128DIELECTRIC FILM MANUFACTURING METHOD - The present invention provides a manufacturing method of a dielectric film which reduces a leak current value while suppressing the reduction of a relative permittivity, suppresses the reduction of a deposition rate caused by the reduction of a sputtering rate, and also provides excellent planar uniformity. A dielectric film manufacturing method according to an embodiment of the present invention is forms a dielectric film of a metal oxide mainly containing Al, Si, and O on a substrate, and comprises steps of forming the metal oxide having an amorphous structure in which a molar fraction between an Al element and a Si element, Si/(Si+Al), is 006-30-2011
20110156127FLASH MEMORY DEVICE WITH WORD LINES OF UNIFORM WIDTH AND METHOD FOR MANUFACTURING THEREOF - A method for manufacturing a semiconductor device, the method including: forming a bit line in a semiconductor substrate; forming a plurality of word lines which intersect with the bit line at predetermined intervals on the semiconductor substrate; eliminating a portion of the plurality of word lines; forming an interlayer insulating film on the semiconductor substrate; and forming a metal plug which penetrates through the interlayer insulating film and is coupled to the bit line in a region where the portion of the plurality of word lines was eliminated.06-30-2011
20110156129METHOD FOR MANUFACTURING TWIN BIT STRUCTURE CELL WITH HAFNIUM OXIDE AND NANO-CRYSTALLINE SILICON LAYER - A method and system for forming a non-volatile memory structure. The method provides a semiconductor substrate and forms a gate dielectric layer overlying a surface region of the semiconductor substrate. A polysilicon gate structure is formed overlying the gate dielectric layer. The method subjects the polysilicon gate structure to an oxidizing environment to cause formation of a first silicon oxide layer overlying the polysilicon gate structure and formation of a second silicon oxide layer overlying a surface region of the substrate. A hafnium oxide material is formed overlying the first and second silicon oxide layers and filling the undercut region. The hafnium oxide material has a nanocrystalline silicon material sandwiched between a first hafnium oxide layer and a second hafnium oxide layer. The hafnium oxide material is selectively etched while a portion of it is maintained in an insert region in a portion of the undercut region.06-30-2011
20110057252METHOD FOR FORMING GATE OXIDE OF SEMICONDUCTOR DEVICE - Disclosed herein is a method for forming a triple gate oxide of a semiconductor device. The method for forming a triple gate oxide of a semiconductor device includes the steps of defining a first region where a gate oxide having a first thickness will be formed, a second region where a gate oxide having a second thickness will be formed and a third region where a gate oxide having a third thickness will be formed on a semiconductor substrate, forming a first oxide film through wet oxidation on the semiconductor substrate and forming a second oxide film on the first oxide film, blocking the first region and selectively removing portions the second oxide film and the first oxide film, which are formed on the second region and the third region, forming a third oxide film through thermal oxidation on the semiconductor substrate, blocking the first region and the second region and selectively removing a portion of the third oxide film, which is formed on the third region, and forming a fourth oxide film through thermal oxidation on the semiconductor substrate and then forming a nitride film thereon, wherein a gate oxide having a triple structure of the first oxide film/second oxide film/nitride film is formed in the first region, a gate oxide having a double structure of the third oxide film/nitride film is formed in the second region and a gate oxide having a double structure of the fourth oxide film/nitride film is formed in the third region.03-10-2011
20090294834NONVOLATILE MEMORY DEVICE, METHOD OF MANUFACTURING THE NONVOLATILE MEMORY DEVICE, AND METHOD OF MANUFACTURING FLAT PANEL DISPLAY DEVICE PROVIDED WITH THE NONVOLATILE MEMORY DEVICE - Provided are a nonvolatile memory device, a method of manufacturing the nonvolatile memory device, and a method of manufacturing a flat panel display device provided therein with the nonvolatile memory device. According to an embodiment, an amorphous silicon layer is formed on a substrate, and then annealed by using an Excimer laser to form a crystallized silicon layer. A nitrogen plasma treatment is performed for the crystallized silicon layer to planarize an upper surface of the crystallized silicon layer. An ONO layer is formed on the nitrogen plasma-treated crystallized silicon layer. A metal layer is formed on the ONO layer. The metal layer, the ONO layer and the nitrogen plasma-treated crystallized silicon layer are patterned.12-03-2009
20120056259MEMORY CELL, MEMORY DEVICE AND METHOD FOR MANUFACTURING MEMORY CELL - A memory cell including a substrate, a stacked gate structure and a first isolation structure is provided. The substrate has a first doped region, a second doped and a channel region located between the first doped region and the second doped region. The stacked gate structure is disposed on the channel and at least includes a charge trapping layer and a gate from bottom to top. The first isolation structure is disposed in the substrate and is connected to the first doped region and extends downwards from the first doped region for a predetermined length, and a bottom of the first isolation structure is lower than a bottom of the first doped region.03-08-2012
20120056260METHOD AND DEVICE EMPLOYING POLYSILICON SCALING - A memory and method of manufacture employing word line scaling. A layered stack, including a charge trapping component and a core polysilicon layer, is formed on a core section and a peripheral section of a substrate. A portion of the layered stack, including the core polysilicon layer is then removed from the peripheral section. A peripheral polysilicon layer, which is thicker than the core polysilicon layer of the layered stack, is next formed on the layered stack and the peripheral section. The layered stack is then isolated from the peripheral polysilicon layer by removing a portion of the peripheral polysilicon layer from the core section, and polysilicon lines are patterned in the isolated layered stack.03-08-2012
20120061743SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor memory device includes a stacked body, a contact, a semiconductor member, a charge storage layer, and a penetration member. The stacked body includes an electrode film stacked alternately with an insulating film. A configuration of an end portion of the stacked body is a stairstep configuration having a step provided every electrode film. The contact is connected to the electrode film from above the end portion. The semiconductor member is provided in a portion of the stacked body other than the end portion to pierce the stacked body in a stacking direction. The charge storage layer is provided between the electrode film and the semiconductor member. The penetration member pierces the end portion in the stacking direction. The penetration member does not include the same kind of material as the charge storage layer.03-15-2012
201200071673D Memory Array With Improved SSL and BL Contact Layout - A 3D memory device includes a plurality of ridges, in some embodiments ridge-shaped, in the form of multiple strips of conductive material separated by insulating material, arranged as bit lines which can be coupled through decoding circuits to sense amplifiers. The strips of conductive material have side surfaces on the sides of the stacks. A plurality of conductive lines arranged as word lines which can be coupled to row decoders, extends orthogonally over the plurality of stacks. The conductive lines conform to the surface of the stacks. Memory elements lie in a multi-layer array of interface regions at cross-points between side surfaces of the semiconductor material strips on the stacks and the conductive lines. The memory elements are programmable, like the anti-fuses or charge trapping structures. In some embodiments, the 3D memory is made using only two critical masks for multiple layers. Some embodiments include a staircase-shaped structure positioned at ends of the semiconductor material strips. Some embodiments include SSL interconnects on a metal layer parallel to the semiconductor material strips, and further SSL interconnects on a higher metal layer, parallel to the word lines.01-12-2012
20120012920VERTICAL NON-VOLATILE MEMORY DEVICE - A vertical non-volatile memory device includes a semiconductor pattern disposed on a substrate; and a plurality of transistors of first through n-th layers that are stacked on a side of the semiconductor pattern at predetermined distances from each other, wherein the transistors are spaced apart and insulated from one another at the predetermined distances via air gap, where n is a natural number equal to or greater than 2.01-19-2012
20110049610NONVOLATILE MEMORY DEVICE AND METHOD OF FORMING THE SAME - Provided are a nonvolatile memory device and a method of forming the same. The nonvolatile memory device includes: a semiconductor substrate including a device isolation layer defining an active region; a tunnel insulating layer on the active region; a charge trapping layer on the tunnel insulating layer; a blocking insulating layer on the charge trapping layer and the device isolation layer; a gate electrode on the blocking insulating layer; and a barrier capping layer formed between the device isolation layer and the blocking insulating layer.03-03-2011
20110049609NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A nonvolatile semiconductor memory device has: a first source/drain diffusion region; a second source/drain diffusion region; a channel region between the first source/drain diffusion region and the second source/drain diffusion region; a first charge storage layer formed on the channel region; a second charge storage layer formed in a same layer as the first charge storage layer and electrically isolated from the first charge storage layer; a first gate electrode; and a second gate electrode electrically isolated from the first gate electrode. The first charge storage layer includes a first memory section and a second memory section. The second charge storage layer includes a third memory section and a fourth memory section. The first gate electrode is formed on the first memory section and the third memory section. The second gate electrode is formed on the second memory section and the fourth memory section.03-03-2011
20110049608NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A memory string comprises: a first semiconductor layer including a columnar portion extending in a stacking direction on a substrate; a first charge storage layer surrounding the columnar portion; and a plurality of first conductive layers stacked on the substrate so as to surround the first charge storage layer. A select transistor comprises: a second semiconductor layer in contact with an upper surface of the columnar portion and extending in the stacking direction; a second charge storage layer surrounding the second semiconductor layer; and a second conductive layer deposited above the first conductive layer to surround the second charge storage layer. The second charge storage layer is formed from a layer downward of the second conductive layer to an upper end vicinity of the second conductive layer, and is not formed in a layer upward of the upper end vicinity.03-03-2011
20110049607SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE - A semiconductor device manufacturing method includes: alternately stacking a plurality of insulating layers and electrode layers; forming a hole penetrating through a multilayer body of the insulating layers and the electrode layers; forming a conductive film on an inner wall of the hole; anisotropically etching the conductive film to selectively leave the conductive film on a sidewall of the hole; altering the conductive film into an insulator by heat treatment; and removing the insulator covering the electrode layers to expose the electrode layers into the hole.03-03-2011
20110049606CHARGE-TRAP BASED MEMORY - Methods of fabricating 3D charge-trap memory cells are described, along with apparatus and systems that include them. In a planar stack formed by alternate layers of electrically conductive and insulating material, a substantially vertical opening may be formed. Inside the vertical opening a substantially vertical structure may be formed that comprises a first layer, a charge-trap layer, a tunneling oxide layer, and an epitaxial silicon portion. Additional embodiments are also described.03-03-2011
20120061745METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - There is provided a technology capable of improving the processing precision of memory cells forming a nonvolatile memory in a semiconductor device including the nonvolatile memory. A second polysilicon film is formed in such a manner as to cover a first polysilicon film and a dummy gate electrode. Thus, the second polysilicon film is formed reflecting the shapes of a step difference portion and a gap groove. Particularly, in the second polysilicon film covering the gap groove, a concave part is formed. Subsequently, over the second polysilicon film, an antireflection film is formed. Thus, the antireflection film having high flowability flows from the higher region to the lower region of the step difference portion, but is stored in a sufficient amount in the concave part. Accordingly, the antireflection film is supplied from the concave part so as to compensate for the amount of the antireflection film to flow out therefrom.03-15-2012
20110095356NONVOLATILE MEMORY DEVICES - Nonvolatile memory devices and methods of making the same are described. A nonvolatile memory device includes a string selection transistor, a plurality of memory cell transistors, and a ground selection transistor electrically connected in series to the string selection transistor and to the pluralities of memory cell transistors. Each of the transistors includes a channel region and source/drain regions. First impurity layers are formed at boundaries of the channels and the source/drain regions of the memory cell transistors. The first impurity layers are doped with opposite conductivity type impurities relative to the source/drain regions of the memory cell transistors. Second impurity layers are formed at boundaries between a channel and a drain region of the string selection transistor and between a channel and a source region of the ground selection transistor. The second impurity layers are doped with the same conductivity type impurities as the first impurity layers and have a higher impurity concentration than the first impurity layers.04-28-2011
20120104484NONVOLATILE MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A nonvolatile memory device includes a substrate, a stacked structure with conductive materials and first insulating materials and the conductive materials and the first insulating materials are alternately stacked on the substrate, and a plurality of pillars in contact with the substrate and the pillars extend through the stacked structure in a direction perpendicular to the substrate. The device also includes information storage layers between the conductive materials and the first insulating materials, and second insulating materials between the first insulating materials and the pillars.05-03-2012
20120104483NON-VOLATILE MEMORY AND LOGIC CIRCUIT PROCESS INTEGRATION - A method of making a logic transistor in a logic region of a substrate and a non-volatile memory cell in an NVM region of the substrate includes forming a gate dielectric layer on the substrate. A first polysilicon layer is formed on the gate dielectric. The first polysilicon layer is formed over the NVM region and removing the first polysilicon layer over the logic region. A dielectric layer is formed over the NVM region including the first polysilicon layer and over the logic region. A protective layer is formed over the dielectric layer. The dielectric layer and the protective layer are removed from the logic region to leave a remaining portion of the dielectric layer and a remaining portion of the protective layer over the NVM region. A high-k dielectric layer is formed over the logic region and the remaining portion of the protective layer. A first metal layer is formed over the high K dielectric layer. The first metal layer, the high K dielectric, and the remaining portion of the protective layer are removed over the NVM region to leave a remaining portion of the first metal layer and a remaining portion of the high K dielectric layer over the logic region. A conductive layer is deposited over the remaining portion of the dielectric layer and over the first metal layer. The NVM cell and the logic transistor are formed and this includes patterning the conductive layer.05-03-2012
20120068254NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a memory device includes a semiconductor substrate, first, second, third and fourth fin-type stacked layer structures, each having memory strings stacked in a first direction perpendicular to a surface of the semiconductor substrate, and each extending to a second direction parallel to the surface of the semiconductor substrate, a first part connected to first ends in the second direction of the first and second fin-type stacked layer structures each other, a second part connected to first ends in the second direction of the third and fourth fin-type stacked layer structures each other, a third part connected to second ends in the second direction of the first and third fin-type stacked layer structures each other, and a fourth part connected to second ends in the second direction of the second and fourth fin-type stacked layer structures each other.03-22-2012
20120153377EDGE ROUNDED FIELD EFFECT TRANSISTORS AND METHODS OF MANUFACTURING - Embodiments of the present technology are directed toward gate sidewall engineering of field effect transistors. The techniques include formation of a blocking dielectric region and nitridation of a surface thereof. After nitridation of the blocking dielectric region, a gate region is formed thereon and the sidewalls of the gate region are oxidized to round off gate sharp corners and reduce the electrical field at the gate corners.06-21-2012
20100096688NON-VOLATILE MEMORY HAVING CHARGE TRAP LAYER WITH COMPOSITIONAL GRADIENT - A flash memory device and method of forming a flash memory device are provided. The flash memory device includes a silicon nitride layer having a compositional gradient in which the ratio of silicon to nitrogen varies through the thickness of the layer. The silicon nitride layer having a compositional gradient of silicon and nitrogen provides an increase in charge holding capacity and charge retention time of the unit cell of a non-volatile memory device.04-22-2010
20080237694Integrated circuit, cell, cell arrangement, method for manufacturing an integrated circuit, method for manufacturing a cell, memory module - The invention relates to integrated circuits, to a cell, to a cell arrangement, to a method for manufacturing an integrated circuit, to a method for manufacturing a cell, and to a memory module. In an embodiment of the invention, an integrated circuit is provided having a cell, the cell including a low-k dielectric layer, a first high-k dielectric layer disposed above the low-k dielectric layer, a charge trapping layer disposed above the first high-k dielectric layer, and a second high-k dielectric layer disposed above the charge trapping layer.10-02-2008
20090134449NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is a nonvolatile semiconductor memory device highly integrated and highly reliable. A plurality of memory cells are formed in a plurality of active regions sectioned by a plurality of isolations (silicon oxide films) extending in the Y direction and deeper than a well (p type semiconductor region). In each memory cell, a contact is provided in the well (p type semiconductor region) so as to penetrate through a source diffusion layer (n05-28-2009
20090134448Non-volatile memory device and method of forming the same - Example embodiments provide a non-volatile semiconductor memory device and method of forming the same. The non-volatile memory device may include a tunnel insulation layer on a semiconductor substrate, a charge storage layer on the tunnel insulation layer, a first blocking insulation layer on the charge storage layer, and a gate electrode on the first blocking insulation layer, wherein the gate electrode includes aluminum and the first blocking insulation layer does not include aluminum.05-28-2009
20110089480MEMORY AND MANUFACTURING METHOD THEREOF - A memory having isolated dual memory cells is provided. A first isolation wall and a second isolation wall are separately disposed between a source and a drain on a substrate. An isolation bottom layer and a polysilicon layer are orderly disposed on the substrate between the first and the second isolation walls. A first charge storage structure and a first gate are orderly disposed on the substrate between the first isolation wall and the source. A second charge storage structure and a second gate are orderly disposed on the substrate between the second isolation wall and the drain. A word line disposed on the polysilicon layer, the first gate, the second gate, the first isolation wall and the second isolation wall is electrically connected to the first gate, the second gate and the polysilicon layer.04-21-2011
20110089479SCALABLE FLASH EEPROM MEMORY CELL WITH FLOATING GATE SPACER WRAPPED BY CONTROL GATE AND METHOD OF MANUFACTURE - A polysilicon spacer as a floating gate of a Flash memory device. An advantage of such spacer structure is to reduce a cell size, which is desirable for state-of-the-art Flash memory technology. In a preferred embodiment, the floating gate can be self-aligned to a nearby and/or within a vicinity of the select gate of the cell select transistor. In a preferred embodiment, the present invention preserves a tunnel oxide layer after the removal, using dry etching, a polysilicon spacer structure on the drain side of the select transistor gate. More preferably, the present method provides for a certain amount of tunnel oxide to remain so as to prevent the active silicon area in the drain region of the memory cell from being etched by the dry etching gas.04-21-2011
20120161222METHOD FOR FILLING A PHYSICAL ISOLATION TRENCH AND INTEGRATING A VERTICAL CHANNEL ARRAY WITH A PERIPHERY CIRCUIT - A method of processing a semiconductor structure may include preparing a vertical channel memory structure for filling of a physical isolation trench formed therein. The physical isolation trench may be formed between active structures adjacent to each other and extending in a first direction. The active structures may have channels adjacent to sides of the active structures that are opposite to sides of the active structures that are adjacent to the physical isolation trench. The method may further include filling the physical isolation trench in connection with application of a multi-dielectric layer (ex. an oxide-nitride-oxide (ONO) layer), a polysilicon liner and/or an oxide film. A corresponding apparatus and method for integrating such a structure with a planar periphery are also provided.06-28-2012
20120211822NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a non-volatile memory device includes alternately stacking a plurality of interlayer dielectric layers and a plurality of conductive layers over a substrate, etching the interlayer dielectric layers and the conductive layers to form a trench which exposes a surface of the substrate forming a first material layer over a resulting structure in which the trench is formed, forming a second material layer over the first material layer, removing portions of the second material layer and the first material layer formed on a bottom of the trench to expose the surface of the substrate, removing the second material layer, and burying a channel layer within the trench in which the second material layer is removed.08-23-2012
20120211820SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor memory device includes a plurality of gate electrode films arranged parallel to each other along a direction, a semiconductor member extending in the direction, and passing through the plurality of gate electrode films, and a charge storage film provided between the gate electrode films and the semiconductor member. Protrusions are provided projecting along the direction at the ends of the gate electrode films in opposition to the semiconductor member. A gaseous layer is formed in a part of a gap between the gate electrode films.08-23-2012
20100289072Electronic Device Including a Gate Electrode Having Portions with Different Conductivity Types - An electronic device can include a gate electrode having different portions with different conductivity types. In an embodiment, a process of forming the electronic device can include forming a semiconductor layer over a substrate, wherein the semiconductor layer has a particular conductivity type. The process can also include selectively doping a region of the semiconductor layer to form a first doped region having an opposite conductivity type. The process can further include patterning the semiconductor layer to form a gate electrode that includes a first portion and a second portion, wherein the first portion includes a portion of the first doped region, and the second region includes a portion of the semiconductor layer outside of the first doped region. In a particular embodiment, the electronic device can have a gate electrode having edge portions of one conductivity type and a central portion having an opposite conductivity type.11-18-2010
20120161223DISCRETE TRAP NON-VOLATILE MULTI-FUNCTIONAL MEMORY DEVICE - A multiple layer tunnel insulator is fabricated between a substrate and a discrete trap layer. The properties of the multiple layers determines the volatility of the memory device. The composition of each layer and/or the quantity of layers is adjusted to fabricate either a DRAM device, a non-volatile memory device, or both simultaneously.06-28-2012
20100207194NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - A nonvolatile semiconductor memory device includes: a semiconductor substrate; a stacked body provided on the semiconductor substrate, the stacked body having electrode films and insulating films being alternately stacked; a first and second semiconductor pillars; and a first and second charge storage layers. The first and second semiconductor pillars are provided inside a through hole penetrating through the stacked body in a stacking direction of the stacked body. The through hole has a cross section of an oblate circle, when cutting in a direction perpendicular to the stacking direction. The first and second semiconductor pillars face each other in a major axis direction of the first oblate circle. The first and second semiconductor pillars extend in the stacking direction. The first and second charge storage layers are provided between the electrode film and the first and second semiconductor pillars, respectively.08-19-2010
20100207192NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A non-volatile semiconductor memory device capable of more efficiently trapping charges in a charge storage layer without increasing the thickness of the charge storage layer, as well as a manufacturing method thereof. In the non-volatile semiconductor memory device a tunnel insulating film, a charge storage layer, a block insulating film, and a gate electrode are disposed successively between a first source/drain region and a second source/drain region above a semiconductor substrate. The charge storage layer has a first layer and second layers, the first layer has a first nitrogen atom concentration, each of the second layers has a second nitrogen atom concentration, higher than the first nitrogen atom concentration and faces one of the tunnel insulating film and the block insulator.08-19-2010
20100207191METHOD AND DEVICE EMPLOYING POLYSILICON SCALING - A memory and method of manufacture employing word line scaling. A layered stack, including a charge trapping component and a core polysilicon layer, is formed on a core section and a peripheral section of a substrate. A portion of the layered stack, including the core polysilicon layer is then removed from the peripheral section. A peripheral polysilicon layer, which is thicker than the core polysilicon layer of the layered stack, is next formed on the layered stack and the peripheral section. The layered stack is then isolated from the peripheral polysilicon layer by removing a portion of the peripheral polysilicon layer from the core section, and polysilicon lines are patterned in the isolated layered stack.08-19-2010
20120132983SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, a conductive member, a semiconductor pillar, and a charge storage layer. The stacked body is provided above the substrate. The stacked body includes a plurality of insulating films stacked alternately with a plurality of electrode films. A plurality of terraces are formed in a stairstep configuration along only a first direction in an end portion of the stacked body on the first-direction side. The first direction is parallel to an upper face of the substrate. The plurality of terraces are configured with upper faces of the electrode films respectively. The conductive member is electrically connected to the terrace to connect electrically the electrode film to the substrate by leading out the electrode film in a second direction parallel to the upper face of the substrate and orthogonal to the first direction. The semiconductor pillar is provided in a central portion of the stacked body and extends in a stacking direction of the insulating films and the electrode films. The charge storage layer is provided between the electrode film and the semiconductor pillar.05-31-2012
20120132984SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME AS WELL AS SEMICONDUCTOR MEMORY AND METHOD OF MANUFACTURING THE SAME - A contact plug 05-31-2012
20110180866NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a nonvolatile semiconductor memory device includes a substrate, a stacked body, an insulating film, a non-doped semiconductor film, a semiconductor pillar, a charge storage film, a contact, and a spacer insulating film. The stacked body is provided on the substrate. The stacked body includes a plurality of doped semiconductor films stacked. The insulating film is provided between the doped semiconductor films in a first region. The non-doped semiconductor film is provided between the doped semiconductor films in a second region. The semiconductor pillar pierces the stacked body in a stacking direction of the stacked body in the first region. The charge storage film is provided between the doped semiconductor film and the semiconductor pillar. The contact pierces the stacked body in the stacking direction in the second region. The spacer insulating film is provided around the contact.07-28-2011
20110180864MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A memory device is provided, including a substrate, a conductive layer, a charge storage layer, a plurality of isolation structures, a plurality of first doped regions, and a plurality of second doped regions. The substrate has a plurality of trenches. The conductive layer is disposed on the substrate and fills the trenches. The charge storage layer is disposed between the substrate and the conductive layer. The isolation structures are disposed in the substrate between two adjacent trenches, respectively. The first doped regions are disposed in an upper portion of the substrate between each isolation structure and each trench, respectively. The second doped regions are disposed in the substrate under a bottom portion of the trenches, in which each isolation structure is disposed between two adjacent second doped regions.07-28-2011
20110175155NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - In one embodiment, a nonvolatile semiconductor memory device includes a plurality of memory cell transistors disposed on device regions. Each of the memory cell transistors includes a tunnel insulator disposed on a device region, a charge storage layer disposed on the tunnel insulator, and formed of an insulator, a block insulator disposed on the charge storage layer, and a gate electrode disposed on the block insulator. The gate electrode of each memory cell transistor is isolated by an insulator from the gate electrode of an adjacent memory cell transistor adjacent in a gate length direction. Further, the block insulator is disposed on the device region extending in the gate length direction, and continuously disposed in regions under the gate electrodes of the memory cell transistors and in regions between the gate electrodes of the memory cell transistors. Further, the block insulator disposed in the regions between the gate electrodes includes a thin portion which has a smaller thickness than the block insulator formed in the regions under the gate electrodes.07-21-2011
20120248525THREE DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FABRICATING THE SAME - Three dimensional semiconductor memory devices and methods of fabricating the same are provided. According to the method, sacrificial layers and insulating layers are alternately and repeatedly stacked on a substrate, and a cutting region penetrating an uppermost sacrificial layer of the sacrificial layers is formed. The cutting region is filled with a non sacrificial layer. The insulating layers and the sacrificial layers are patterned to form a mold pattern. The mold pattern includes insulating patterns, sacrificial patterns, and the non sacrificial layer in the cutting region. The sacrificial patterns may be replaced with electrodes. The related semiconductor memory device is also provided.10-04-2012
20090057752NON-VOLATILE MEMORY AND METHOD FOR MANUFACTURING THE SAME - A non-volatile memory located on a substrate is provided. The non-volatile memory includes a tunnel layer, a charge trapping composite layer, a gate and a source/drain region. The tunnel layer is located on the substrate, the charge trapping composite layer is located on the tunnel layer and the gate is located over the charge trapping composite layer. The source/drain region is located in the substrate on both sides of the tunnel layer. With the charge trapping composite layer, the non-volatile memory has relatively better programming and erasing performance and higher data retention ability. Furthermore, since there is no need to perform a thermal process in the formation of the charge trapping composite layer, thermal budget of the manufacturing process is low.03-05-2009
20090057753NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device includes a source region and a drain region spaced from each other in a surface of a semiconductor layer, a tunnel insulating film provided on the semiconductor layer between the source region and the drain region, a charge storage film provided on the tunnel insulating film, a block insulating film provided on the charge storage film, and a control gate electrode provided on the block insulating film. The block insulating film is made of (Rm03-05-2009
20120168850NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A nonvolatile memory device includes a channel protruding in a vertical direction from a substrate, a plurality of interlayer dielectric layers and gate electrode layers which are alternately stacked over the substrate along the channel, and a memory layer formed between the channel and a stacked structure of the interlayer dielectric layers and gate electrode layers. Two or more gate electrode layers of the plurality of gate electrode layers are coupled to an interconnection line to form a selection transistor.07-05-2012
20120168853SEMICONDUCTOR NON-VOLATILE MEMORY DEVICE - A semiconductor non-volatile memory (NVM) device, comprising: a semiconductor substrate; a three-layer stack structure of medium layer-charge trapping layer-medium layer disposed on the semiconductor substrate; a gate disposed above the three-layer stack structure; a source and a drain disposed in the semiconductor substrate at either side of the three-layer stack structure; wherein the charge trapping layer is a dielectric layer containing one or more discrete compound clusters formed by atomic layer deposition (ALD) method.07-05-2012
20120168851NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A nonvolatile semiconductor memory device including a memory cell configured to store data and a resistor element provided around the memory cell. The memory cell includes a charge storage layer provided above a substrate, a first semiconductor layer formed on a top surface of the charge storage layer via an insulating layer, and a first low resistive layer formed on a top surface of the first semiconductor layer and having resistance lower than that of the first semiconductor layer. The resistor element includes a second semiconductor layer formed on the same layer as the first semiconductor layer, and a second low resistive layer formed on the same layer as the first low resistive layer and on a top surface of the second semiconductor layer, having resistance lower than that of the second semiconductor layer.07-05-2012
20120168849NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A non-volatile memory device includes a substrate including a resistor layer having a resistance lower than that of a source line, channel structures including a plurality of inter-layer dielectric layers that are alternately staked with a plurality of channel layers over the substrate, and the source line configured to contact sidewalls of the channel layers, where a lower end of the source line contacts the resistor layer.07-05-2012
20120168847MEMORY WITH EXTENDED CHARGE TRAPPING LAYER - A memory array includes a plurality of bit lines and a plurality of word lines, a gate region, and a charge trapping layer. The charge trapping layer is wider than a word line; the charge trapping layer is extended beyond the edge of the gate region to facilitate capturing and removing charges.07-05-2012
20100052042SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - The semiconductor memory device of the present invention includes a plurality of memory strings having a plurality of electrically reprogrammable memory cells connected in series, the memory strings having a column shaped semiconductor, a first insulation film formed around the column shaped semiconductor, a charge accumulation layer formed around the first insulation film, a second insulation film formed around the charge accumulation film and a plurality of electrodes formed around the second insulation film, a bit line connected to one end of the memory strings via a plurality of selection transistors, and a conducting layer extending in two dimensions and in which the plurality of electrodes of the memory strings and the plurality of electrodes of different memory strings are shared respectively, wherein each end part of the conducting layer is formed in step shapes in a direction parallel with the bit line.03-04-2010
20100052039SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device of an embodiment can prevent nitriding of the lower-layer insulating film and oxygen diffusion from the upper-layer insulating film, so as to minimize the decrease in charge capture density. This semiconductor device includes a semiconductor layer, a first insulating film provided on the semiconductor layer, a nitrogen-added amorphous silicon layer formed on the first insulating film, a first silicon nitride layer formed on the amorphous silicon layer, and a second insulating film formed above the first silicon nitride layer.03-04-2010
20100052038SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THEREOF - A semiconductor device which includes two trenches formed in a semiconductor substrate, a charge storage layer as an insulator formed on each side surface of the trenches, and separated on a bottom surface thereof, and a bit line formed below the bottom surface of the trenches in the semiconductor substrate. A channel region is formed in the semiconductor substrate from a side surface of one of the two trenches to that of the other trench via an upper surface of a protruding portion between those two trenches. A method for manufacturing the semiconductor device is also provided.03-04-2010
20100052037Charge-trapping engineered flash non-volatile memory - This invention proposes a charge-trapping-engineered flash (CTEF) non-volatile memory (NVM) of electrode-[blocking oxide]-[trapping03-04-2010
20100052041Nonvolatile Memory Devices Having Charge-Trap Layers Therein with Relatively High Election Affinity - Provided is a nonvolatile memory device. The nonvolatile memory device may include a tunnel insulating layer on a semiconductor substrate; a charge trap layer disposed on the tunnel insulating layer and having an electron affinity greater than a silicon nitride layer; a barrier insulating layer on the charge trap layer; a blocking insulating layer on the barrier insulating layer; and a gate electrode on the blocking insulating layer. An electron affinity of the barrier insulating layer is smaller than an electron affinity of the blocking insulating layer.03-04-2010
20090096015Nonvolatile semiconductor memory device and manufacturing method therefor - In a nonvolatile semiconductor memory device, a floating gate is formed on a semiconductor substrate through a gate insulating film, and has a first portion contacting the gate insulating film and a second portion extending upwardly from a part of a surface of the first portion. A first diffusion layer is formed in the semiconductor substrate to have a plane parallel to a surface of the semiconductor substrate. A second diffusion layer is formed in the semiconductor substrate, to have the plane. A control gate is provided near the floating gate above a channel region in the semiconductor substrate and is formed on a first side of the first portion. A conductive film is connected with the first diffusion layer and is formed on a second side of the first portion and a first side of the second portion through the first insulating film.04-16-2009
20090096014NONVOLATILE MEMORY DEVICES THAT INCLUDE AN INSULATING FILM WITH NANOCRYSTALS EMBEDDED THEREIN AND METHODS OF MANUFACTURING THE SAME - A nonvolatile memory device includes a semiconductor substrate, a charge-trap structure disposed on the semiconductor substrate, which includes an insulating film and a plurality of carbon nanocrystals embedded in the insulating film, and a gate disposed on the charge-trap structure. The nonvolatile memory device may exhibit memory hysteresis characteristics with improved reliability.04-16-2009
20090096013NON-VOLATILE MEMORY DEVICES WITH CHARGE STORAGE REGIONS - A memory device includes a cell stack and a select gate formed adjacent to the cell stack. The cell stack includes a tunneling dielectric layer, a charge storage layer, a blocking dielectric layer, and a control gate. Applying a positive bias to the control gate, the select gate and the source of the device injects negative charges from a channel region of a substrate by hot electron injection through the tunneling dielectric layer at a location near a gap between the select gate and the control gate into the charge storage layer to store negative charges in the charge storage layer. Applying a negative bias is to the control gates directly tunnels positive charges from the channel region of the substrate through the tunneling dielectric layer and into the charge storage layer to store positive charges in the charge storage layer.04-16-2009
20120313159NON-VOLATILE MEMORY DEVICES INCLUDING GATES HAVING REDUCED WIDTHS AND PROTECTION SPACERS AND METHODS OF MANUFACTURING THE SAME - Non-volatile memory devices and methods of manufacturing the same are disclosed. In a non-volatile memory device, widths of a metal gate and an upper portion of a base gate in a gate electrode are less than the width of a hard mask pattern disposed on the metal gate. First and second protection spacers are disposed on opposing sidewalls of the metal gate and on opposing sidewalls of the upper portion of the base gate, respectively.12-13-2012
20120217571NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - Nonvolatile semiconductor memory device includes first memory cell array layer, first insulating layer formed thereabove, and second memory cell array layer formed thereabove. First memory cell array layer includes first NAND cell units each including plural first memory cells. The first memory cell includes first semiconductor layer, first gate insulating film formed thereabove, and first charge accumulation layer formed thereabove. The second memory cell array layer includes second NAND cell units each including plural second memory cells. The second memory cell includes second charge accumulation layer, second gate insulating film formed thereabove, and second semiconductor layer formed thereabove. Control gates are formed, via an inter-gate insulating film, on first-direction both sides of the first and second charge accumulation layers positioned the latter above the former via the first insulating layer. The control gates extend in a second direction perpendicular to the first direction.08-30-2012
20120074487APPARATUS CONTAINING COBALT TITANIUM OXIDE - Electronic apparatus and methods of forming the electronic apparatus include cobalt titanium oxide on a substrate for use in a variety of electronic systems. The cobalt titanium oxide may be structured as one or more monolayers. The cobalt titanium oxide may be formed by a monolayer by monolayer sequencing process such as atomic layer deposition.03-29-2012
20120074486MULTI-GATE BANDGAP ENGINEERED MEMORY - Memory cells comprising: a semiconductor substrate having a source region and a drain region disposed below a surface of the substrate and separated by a channel region; a tunnel dielectric structure disposed above the channel region, the tunnel dielectric structure comprising at least one layer having a hole-tunneling barrier height; a charge storage layer disposed above the tunnel dielectric structure; an insulating layer disposed above the charge storage layer; and a gate electrode disposed above the insulating layer are described along with arrays and methods of operation.03-29-2012
20100006922NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - The invention provides a nonvolatile semiconductor memory device comprising a plurality of memory strings each including a plurality of electrically programmable memory cells connected in series. The memory string includes a semiconductor pillar, an insulator formed around the circumference of the semiconductor pillar, and first through nth electrodes to be turned into gate electrodes (n denotes a natural number equal to 2 or more) formed around the circumference of the insulator. It also includes interlayer electrodes formed in regions between the first through nth electrodes around the circumference of the insulator.01-14-2010
20100244119NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction; a selection gate electrode stacked on the stacked structural unit in the first direction; an insulating layer stacked on the selection gate electrode in the first direction; a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction; a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit.09-30-2010
20090078989Method of forming silicon nitride at low temperature, charge trap memory device including crystalline nano dots formed by using the same, and method of manufacturing the charge trap memory device - Provided are a method of forming silicon nitride at a low temperature, a charge trap memory device including crystalline nano dots formed by using the same, and a method of manufacturing the charge trap memory device. The method of forming silicon nitride includes loading a substrate into a chamber of a silicon nitride deposition device comprising a filament; increasing a temperature of the filament to a temperature whereby a reactant gas to be injected into the chamber may be dissociated; and injecting the reactant gas into the chamber so as to form a crystalline silicon nitride film or crystalline silicon nitride nano dots on the substrate. In the method, the temperature of the filament may be maintained at 1,400° C.˜2,000° C., and a pressure in the chamber may be maintained at several to several ten torr when the reactant gas in injected into the chamber.03-26-2009
20090065850NON-VOLATILE MEMORY DEVICES - According to a nonvolatile memory device having a multi gate structure and a method for forming the same of the present invention, a gate electrode is formed using a damascene process. Therefore, a charge storage layer, a tunneling insulating layer, a blocking insulating layer and a gate electrode layer are not attacked from etching in a process for forming the gate electrode, thereby forming a nonvolatile memory device having good reliability.03-12-2009
20120313160SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - Provided is a semiconductor device having, over a semiconductor substrate, a control gate electrode and a memory gate electrode which are adjacent to each other and constitute a nonvolatile memory. The height of the memory gate electrode is lower than the height of the control gate electrode. A metal silicide film is formed over the upper surface of the control gate electrode, but not formed over the upper surface of the memory gate electrode. The memory gate electrode has, over the upper surface thereof, a sidewall insulating film made of silicon oxide. This sidewall insulating film is formed in the same step as that for the formation of respective sidewall insulating films over the sidewalls of the memory gate electrode and the control gate electrode. The present invention makes it possible to improve the production yield and performance of the semiconductor device having a nonvolatile memory.12-13-2012
20090315097SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING - A semiconductor device and a method for manufacturing the semiconductor device is disclosed. The semiconductor device includes a bit line formed to extend into a semiconductor substrate, a charge storage layer formed on the semiconductor substrate, a word line formed above the charge storage layer to extend across the bit line, a gate electrode formed on the charge storage layer under the word line and between bit lines, a first insulating film formed over the bit line and to extend in the direction of the bit line and a second insulating film that includes a different material than that of the first insulating film and formed to adjoin a side surface of the first insulating film. In addition, the semiconductor device includes an interlayer insulating film that includes a different material from that of the second insulating film that is formed on the first insulating film and the second insulating film and a contact plug coupled to the bit line and formed to penetrate through the first insulating film and the interlayer insulating film and to be sandwiched by the second insulating film.12-24-2009
20120187471METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR MEMORY DEVICE THEREBY - A method of manufacturing a semiconductor device comprises forming memory cells on a memory cell region, alternately forming a sacrificial layer and an insulating interlayer on a connection region for providing wirings configured to electrically connect the memory cells, forming an etching mask pattern including etching mask pattern elements on a top sacrificial layer, forming blocking sidewalls on either sidewalls of each of the etching mask pattern element, forming a first photoresist pattern selectively exposing a first blocking sidewall furthermost from the memory cell region and covering the other blocking sidewalls, etching the exposed top sacrificial layer and an insulating interlayer to expose a second sacrificial layer, forming a second photoresist pattern by laterally removing the first photoresist pattern to the extent that a second blocking sidewall is exposed, and etching the exposed top and second sacrificial layers and the insulating interlayers to form a staircase shaped side edge portion.07-26-2012
20120223381Non-volatile memory structure and method for manufacturing the same - A non-volatile memory structure is disclosed. LDD regions may be optionally formed through an ion implantation using a mask for protection of a gate channel region of an active area. Two gates are apart from each other and disposed on an isolation structure on two sides of a middle region of the active area, respectively. The two gates may be each entirely disposed on the isolation structure or partially to overlap a side portion of the middle region of the active area. A charge-trapping layer and a dielectric layer are formed between the two gates and on the active area to serve for a storage node function. They may be further formed onto all sidewalls of the two gates to serve as spacers. Source/drain regions are formed through ion implantation using a mask for protection of the gates and the charge-trapping layer.09-06-2012
20090026529SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a silicon substrate having a main surface, the main surface including a region in which a groove structure or a concavity and convexity structure is formed, and a nonvolatile memory cell provided on the main surface of the silicon substrate, the nonvolatile memory cell including a first insulating film as a tunnel insulating film provided on the region, a charge storage layer provided on the first insulating film, a second insulating film provided on the charge storage layer, a control gate provided on the second insulating film.01-29-2009
20120256249NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A MONOS type non-volatile semiconductor memory device which is capable of electrically writing, erasing, reading and retaining data, the memory device including source/drain regions, a first gate insulating layer, a first charge trapping layer formed on the first gate insulating layer, a second gate insulating layer formed on the first charge trapping layer, and a controlling electrode formed on the second gate insulating layer. The first charge trapping layer includes an insulating film containing Al and O as major elements and having a defect pair formed of a complex of an interstitial O atom and a tetravalent cationic atom substituting for an Al atom, the insulating film also having electron unoccupied levels within the range of 2 eV-6 eV as measured from the valence band maximum of Al10-11-2012
20120256248STRUCTURE AND FABRICATION METHOD OF TUNNEL FIELD EFFECT TRANSISTOR WITH INCREASED DRIVE CURRENT AND REDUCED GATE INDUCED DRAIN LEAKAGE (GIDL) - Gate induced drain leakage in a tunnel field effect transistor is reduced while drive current is increased by orienting adjacent semiconductor bodies, based on their respective crystal orientations or axes, to optimize band-to-band tunneling at junctions. Maximizing band-to-band tunneling at a source-channel junction increases drive current, while minimizing band-to-band tunneling at a channel-drain junction decreases GIDL. GIDL can be reduced by an order of magnitude in an embodiment. Power consumption for a given frequency can also be reduced by an order of magnitude.10-11-2012
20100140683SILICON NITRIDE FILM AND NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - Provided is a silicon nitride film which has an excellent charge storage capacity and thus is useful as a charge storage layer of a semiconductor memory device. The silicon nitride film having substantially uniform trap density in the film thickness direction has high charge storage performance. The silicon nitride film is formed by plasma CVD by using a plasma processing apparatus (06-10-2010
20100327340NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a nonvolatile semiconductor memory device includes a stacked structural unit, a semiconductor pillar, a memory layer, an inner insulating film, an outer insulating film and a cap insulating film. The unit includes a plurality of electrode films stacked alternately in a first direction with a plurality of inter-electrode insulating films. The pillar pierces the stacked structural unit in the first direction. The memory layer is provided between the electrode films and the semiconductor pillar. The inner insulating film is provided between the memory layer and the semiconductor pillar. The outer insulating film is provided between the memory layer and the electrode films. The cap insulating film is provided between the outer insulating film and the electrode films, and the cap insulating film has a higher relative dielectric constant than the outer insulating film.12-30-2010
20100327339NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor memory device provided with a cell array section and a peripheral circuit section, the device includes: a back gate electrode; a stacked body provided on the back gate electrode; a plurality of semiconductor pillars extending in a stacking direction; connection members, each of the connection members connecting one of the semiconductor pillars to another one of the semiconductor pillars; a back-gate electrode contact applying a potential to the back gate electrode; a gate electrode provided in the peripheral circuit section; and a gate electrode contact applying a potential to the gate electrode, the back gate electrode and the gate electrode respectively including: a lower semiconductor layer; a conductive layer provided on the lower semiconductor layer; and an upper semiconductor layer provided on the conductive layer, the connection members being provided in or on the upper semiconductor layer, the back-gate electrode contact and the gate electrode contact being in contact with the conductive layer.12-30-2010
20080296661INTEGRATION OF NON-VOLATILE CHARGE TRAP MEMORY DEVICES AND LOGIC CMOS DEVICES - A semiconductor structure and method to form the same. The semiconductor structure includes a substrate having a non-volatile charge trap memory device disposed on a first region and a logic device disposed on a second region. A charge trap dielectric stack may be formed subsequent to forming wells and channels of the logic device. HF pre-cleans and SC12-04-2008
20080296660LOW RESISTIVITY CONDUCTIVE STRUCTURES, DEVICES AND SYSTEMS INCLUDING SAME, AND METHODS FORMING SAME - A conductive structure and method for making same is disclosed and includes a first nucleation layer formed by performing a cyclic deposition process on a substrate, a second nucleation layer formed on the first nucleation layer by a CVD process, and a bulk metal layer formed on the second nucleation layer.12-04-2008
20090179255Method for forming gate oxide of semiconductor device - The method for forming a triple gate oxide of a semiconductor device includes the steps of defining a first region, a second region and a third region, forming a first oxide film and forming a second oxide film on the first oxide film, blocking the first region and selectively removing portions the second oxide film and the first oxide film, forming a third oxide film on the semiconductor substrate, blocking the first region and the second region and selectively removing a portion of the third oxide film and forming a fourth oxide film on the semiconductor substrate and then forming a nitride film thereon, wherein a gate oxide having a triple structure is formed in the first region, a gate oxide having a double structure is formed in the second region and a gate oxide having a double structure is formed in the third region.07-16-2009
20120261742NONVOLATILE SEMICONDUCTOR MEMORY APPARATUS - A nonvolatile semiconductor memory apparatus according to an embodiment includes: a semiconductor layer; a first insulating film formed on the semiconductor layer, the first insulating film being a single-layer film containing silicon oxide or silicon oxynitride; a charge trapping film formed on the first insulating film; a second insulating film formed on the charge trapping film; and a control gate electrode formed on the second insulating film. A metal oxide exists in an interface between the first insulating film and the charge trapping film, the metal oxide comprises material which is selected from the group of Al10-18-2012
20080290399Nonvolatile charge trap memory device having a deuterated layer in a multi-layer charge-trapping region - A nonvolatile charge trap memory device is described. The device includes a substrate having a channel region and a pair of source/drain regions. A gate stack is above the substrate over the channel region and between the pair of source/drain regions. The gate stack includes a multi-layer charge-trapping region having a first deuterated layer. The multi-layer charge-trapping region may further include a deuterium-free charge-trapping layer.11-27-2008
20120299086SEMICONDUCTOR MEMORY DEVICES - Methods of fabricating a semiconductor device are provided. The method includes alternately stacking first material layers and second material layers on a substrate to form a stacked structure, forming a through hole penetrating the stacked structure, forming a data storage layer on a sidewall of the through hole, forming a semiconductor pattern electrically connected to the substrate on an inner sidewall of the data storage layer, etching an upper portion of the data storage layer to form a first recessed region exposing an outer sidewall of the semiconductor pattern, and forming a first conductive layer in the first recessed region. Related devices are also disclosed.11-29-2012
20120299085SELECT TRANSISTOR, METHOD FOR MAKING SELECT TRANSISTOR, MEMORY DEVICE, AND METHOD FOR MANUFACTURING MEMORY DEVICE - A select transistor for use in a memory device including a plurality of memory transistors connected in series includes a tunnel insulating layer formed on a semiconductor substrate, a charge storage layer formed on the tunnel insulating layer, a blocking insulating layer formed on the charge storage layer and configured to be irradiated with a gas cluster ion beam containing argon as source gas, a gate electrode formed on the blocking insulating layer, and a source/drain region formed within the semiconductor substrate at both sides of the gate electrode.11-29-2012
20120299083NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - According to one embodiment, a nonvolatile semiconductor memory device includes a semiconductor region, a tunnel insulator provided above the semiconductor region, a charge storage insulator provided above the tunnel insulator, a block insulator provided above the charge storage insulator, a control gate electrode provided above the block insulator, and an interface region including a metal element, the interface region being provided at one interface selected from between the semiconductor region and the tunnel insulator, the tunnel insulator and the charge storage insulator, the charge storage insulator and the block insulator, and the block insulator and the control gate electrode.11-29-2012
20110018052NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a nonvolatile semiconductor memory device includes a stacked structure, a semiconductor pillar, a memory layer and an outer insulating film. The stacked structure includes a plurality of electrode films and a plurality of interelectrode insulating films alternately stacked in a first direction. The semiconductor pillar pierces the stacked structure in the first direction. The memory layer is provided between the electrode films and the semiconductor pillar. The outer insulating film is provided between the electrode films and the memory layer. The device includes a first region and a second region. An outer diameter of the outer insulating film along a second direction perpendicular to the first direction in the first region is larger than that in the second region. A thickness of the outer insulating film along the second direction in the first region is thicker than that in the second region.01-27-2011
20110037119MEMORY - A memory includes: a semiconductor substrate (02-17-2011
20110037118Nonvolatile memory device having cell and peripheral regions and method of making the same - A nonvolatile memory device and method of making the same are provided. Memory cells may be provided in a cell area wherein each memory cell has an insulative structure including a tunnel insulating layer, a floating trap layer and a blocking layer, and a conductive structure including an energy barrier layer, a barrier metal layer and a low resistance gate electrode. A material having a lower resistivity may be used as the gate electrode so as to avoid problems associated with increased resistance and to allow the gate electrode to be made relatively thin. The memory device may further include transistors in the peripheral area, which may have a gate dielectric layer, a lower gate electrode of poly-silicon and an upper gate electrode made of metal silicide, allowing an improved interface with the lower gate electrode without diffusion or reaction while providing a lower resistance.02-17-2011
20110037117LANTHANUM-METAL OXIDE DIELECTRIC APPARATUS, METHODS, AND SYSTEMS - Lanthanum-metal oxide dielectrics and methods of fabricating such dielectrics provide an insulating layer in a variety of structures for use in a wide range of electronic devices and systems. In an embodiment, a lanthanum-metal oxide dielectric is formed using a trisethylcyclopentadionatolanthanum precursor and/or a trisdipyvaloylmethanatolanthanum precursor. Additional apparatus, systems, and methods are disclosed.02-17-2011
20120267701THREE DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - Nonvolatile memory devices include a vertical stack of nonvolatile memory cells. The vertical stack of nonvolatile memory cells includes a first nonvolatile memory cell having a first gate pattern therein, which is separated from a vertical active region by a first multi-layered dielectric pattern having a first thickness, and a second nonvolatile memory cell having a second gate pattern therein, which is separated from the vertical active region by a second multi-layered dielectric pattern having a second thickness. The second gate pattern is also separated from the first gate pattern by a distance less than a sum of the first and second thicknesses.10-25-2012
20110220989Memory Cells, Methods Of Forming Dielectric Materials, And Methods Of Forming Memory Cells - Some embodiments include memory cells. The memory cells may include a tunnel dielectric material, a charge-retaining region over the tunnel dielectric material, crystalline ultra-high k dielectric material over the charge-retaining region, and a control gate material over the crystalline ultra-high k dielectric material. Additionally, the memory cells may include an amorphous region between the charge-retaining region and the crystalline ultra-high k dielectric material, and/or may include an amorphous region between the crystalline ultra-high k dielectric material and the control gate material. Some embodiments include methods of forming memory cells which contain an amorphous region between a charge-retaining region and a crystalline ultra-high k dielectric material, and/or which contain an amorphous region between a crystalline ultra-high k dielectric material and a control gate material.09-15-2011
20120319187SEMICONDUCTOR DEVICE - For providing a cheap semiconductor memory device with improving reliability by level of a cell, in the place of escaping from defects on memory cells electrically, through such as ECC, and further for providing a cell structure enabling scaling-down in the vertical direction with maintaining the reliability, in a semiconductor memory device, upon which high-speeded read-out operation is required, a charge storage region is constructed with particles made from a large number of semiconductor charge storage small regions, each being independent, thereby increasing the reliability by the cell level.12-20-2012
20110227141NON-VOLATILE MEMORY DEVICES HAVING VERTICAL CHANNEL STRUCTURES AND RELATED FABRICATION METHODS - A memory device having a vertical channel structure is disclosed. The memory device includes a plurality of gate lines extending substantially parallel to one another along a surface of a substrate, and a connection unit electrically connecting the plurality of gate lines. The connection unit includes a first portion laterally extending along the surface of the substrate, a second portion extending substantially perpendicular to the surface of the substrate, and a supporting insulating layer extending in a cavity defined by the first and second portions of the connection unit. Related fabrication methods are also discussed.09-22-2011
20110227140SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, a memory film, and a SiGe film. The stacked body includes a plurality of conductive layers and a plurality of insulating layers alternately stacked above the substrate. The memory film includes a charge storage film. The memory film is provided on a sidewall of a memory hole punched through the stacked body. The SiGe film is provided inside the memory film in the memory hole.09-22-2011
20120080740CHARGE TRAPPING DIELECTRIC STRUCTURES - A dielectric structure may be arranged having a thin nitrided surface of an insulator with a charge blocking insulator over the nitrided surface. The insulator may be formed of a number of different insulating materials such as a metal oxide, a metal oxycarbide, a semiconductor oxide, or oxycarbide. In an embodiment, the dielectric structure may be formed by nitridation of a surface of an insulator using ammonia and deposition of a blocking insulator having a larger band gap than the insulator. The dielectric structure may form part of a memory device, as well as other devices and systems.04-05-2012
20120080739NONVOLATILE PROGRAMMABLE LOGIC SWITCH - A nonvolatile programmable logic switch according to an embodiment includes: a memory cell transistor including: a first source region and a first drain region of a second conductivity type formed at a distance from each other in a first semiconductor region of a first conductivity type; a first insulating film, a charge storage film, a second insulating film, and a control gate stacked in this order and formed on the first semiconductor region between the first source region and the first drain region; a pass transistor including: a second source region and a second drain region of a second conductivity type formed at a distance from each other in a second semiconductor region of the first conductivity type; a third insulating film, a gate electrode stacked in this order and formed on the second semiconductor region between the second source region and the second drain region, the gate electrode being electrically connected to the first drain region; and an electrode for applying a substrate bias to the first and second semiconductor regions.04-05-2012
20100224927NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A NAND-type nonvolatile semiconductor memory device which suppresses write error caused by hot carriers and has improved reliability is provided. On a main plane of a semiconductor substrate, a plurality of memory cell transistors connected in series with each other, and a select gate transistor connected to an end of the plurality of memory cell transistors are arranged. A first impurity layer of a conductivity type opposite to that of the substrate is formed as a common source/drain on the semiconductor substrate between the select gate transistor and the memory cell transistor connected thereto. An impurity concentration distribution of the first impurity layer is asymmetrical with respect to a first virtual plane being at equal distances from ends of the select gate electrode and the control gate electrode and being perpendicular to the main plane, and an impurity concentration of the first impurity layer on the memory cell transistor side is higher than that on the gate transistor side with reference to the first virtual plane.09-09-2010
20100230740NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - First and second memory cells have first and second channels, first and second tunnel insulating films, first and second charge storage layers formed of an insulating film, first and second block insulating films, and first and second gate electrodes. A first select transistor has a third channel, a first gate insulating film, and a first gate electrode. The first channel includes a first-conductivity-type region and a second-conductivity-type region which is formed on at least a part of the first-conductivity-type region and whose conductivity type is opposite to the first conductivity type. The third channel includes the first-conductivity-type region and the second-conductivity-type region formed on the first-conductivity-type region. The number of data stored in the first memory cell is smaller than that of data stored in the second memory cell.09-16-2010
20120280306ONE-TRANSISTOR COMPOSITE-GATE MEMORY - One-transistor memory devices facilitate nonvolatile data storage through the manipulation of oxygen vacancies within a trapping layer of a field-effect transistor (FET), thereby providing control and variation of threshold voltages of the transistor. Various threshold voltages may be assigned a data value, providing the ability to store one or more bits of data in a single memory cell. To control the threshold voltage, the oxygen vacancies may be manipulated by trapping electrons within the vacancies, freeing trapped electrons from the vacancies, moving the vacancies within the trapping layer and annihilating the vacancies.11-08-2012
20120280305FLASH MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - The present invention discloses a flash memory device. The flash memory device comprises a semiconductor substrate and a flash memory area located on the semiconductor substrate. The flash memory area comprises a first doped well, which is divided into a first region and a second region by an isolation region, the second region being doped with an impurity having an electrical conductivity opposite to that of the first doped well; a high-k gate dielectric layer located on the first doped well; and a metal layer located on the high-k gate dielectric layer. The present invention enables compatibility between the high-k dielectric metal gate and the erasable flash memory and increases the operation performance of the flash memory. The present invention also provides a manufacturing method of the flash memory device, which greatly increases the production efficiency and yield of flash memory devices.11-08-2012
20120086068METHOD FOR DEPOSITING A DIELECTRIC ONTO A FLOATING GATE FOR STRAINED SEMICONDUCTOR DEVICES - A method for forming a semiconductor device and a corresponding device are provided. The method includes forming a floating gate device in a process with dual strain layers, and an etch stop layer. An oxide is formed between the floating gate device and a nitride layer above the floating gate.04-12-2012
20120326224SEMICONDUCTOR DEVICE - A semiconductor device has a semiconductor substrate, and a semiconductor element having an FET on the semiconductor substrate and comprises a different threshold voltage depending on an OFF state and an ON state. The semiconductor element has an insulating film disposed above a part where a channel of the semiconductor substrate is formed, a gate electrode disposed above the insulating film, and a charge trap film disposed between the insulating film and the gate electrode, and to exchange more electrons with the gate electrode than with the channel.12-27-2012
20130020630GATE DIELECTRIC OF SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device having a different gate structure in each of a plurality of device regions is described. The method may include a replacement gate process. The method includes forming a hard mask layer on oxide layers formed on one or more regions of the substrate. A high-k gate dielectric layer is formed on each of the first, second and third device regions. The high-k gate dielectric layer may be formed directly on the hard mask layer in a first and second device regions and directly on an interfacial layer formed in a third device region. A semiconductor device including a plurality of devices (e.g., transistors) having different gate dielectrics formed on the same substrate is also described.01-24-2013
20130020631Memory Cell and Method of Manufacturing a Memory Cell - A memory cell and a method of manufacturing a memory cell are provided. The memory cell includes a substrate; at least one first electrode disposed above the substrate; at least one second electrode disposed above the at least one first electrode; a moveable electrode disposed between the at least one first electrode and the at least one second electrode; wherein the moveable electrode is configured to move between the at least one first electrode and the at least one second electrode; wherein the moveable electrode comprises metal.01-24-2013
20120326223SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a method for manufacturing a semiconductor memory device includes forming a stacked body by alternately stacking an insulating film and a conductive film. The method includes forming a trench in the stacked body. The trench extends in one direction and divides the conductive film. The method includes burying a diblock copolymer in the trench. The method includes phase-separating the diblock copolymer into a plurality of first blocks and an insulative second block extending in a stacking direction of the insulating film and the conductive film. The method includes forming a plurality of holes by removing the first blocks. The method includes forming charge accumulation layers on inner surfaces of the holes. And, the method includes forming a plurality of semiconductor pillars extending in the stacking direction by burying a semiconductor material in the holes.12-27-2012
20120326222MEMORY STRUCTURE AND FABRICATING METHOD THEREOF - A memory structure including a memory cell is provided, and the memory cell includes following elements. A first gate is disposed on a substrate. A stacked structure includes a first dielectric structure, a channel layer, a second dielectric structure and a second gate disposed on the first gate, a first charge storage structure disposed in the first dielectric structure and a second charge storage structure disposed in the second dielectric structure. At least one of the first charge storage structure and the second charge storage structure includes two charge storage units which are physically separated. A first dielectric layer is disposed on the first gate at two sides of the stacked structure. A first source and drain and a second source and drain are disposed on the first dielectric layer and located at two sides of the channel layer.12-27-2012
20120286348Structures and Methods of Improving Reliability of Non-Volatile Memory Devices - In one example, the memory device disclosed herein includes a gate insulation layer and a charge storage layer positioned above the gate insulation layer, wherein the charge storage layer has a first width. The device further includes a blocking insulation layer positioned above the charge storage layer and a gate electrode positioned above the blocking insulation layer, wherein the gate electrode has a second width that is greater than the first width. An illustrative method disclosed herein includes forming a gate stack for a memory device, wherein the gate stack includes a gate insulation layer, an initial charge storage layer, a blocking insulation layer and a gate electrode, and wherein the initial charge storage layer has a first width. The method further includes performing an etching process to selectively remove at least a portion of the initial charge storage layer so as to produce a charge storage layer having a second width that is less than the first width of the initial charge storage layer.11-15-2012
20100224929NONVOLATILE MEMORY DEVICE - A vertical NAND string nonvolatile memory device can include an upper dopant region disposed at an upper portion of an active pattern and can have a lower surface located a level higher than an upper surface of an upper selection gate pattern. A lower dopant region can be disposed at a lower portion of the active pattern and can have an upper surface located at a level lower than a lower surface of a lower selection gate pattern.09-09-2010
20100258852NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a non-volatile memory device includes alternately stacking a plurality of interlayer dielectric layers and a plurality of conductive layers over a substrate, etching the interlayer dielectric layers and the conductive layers to form a trench which exposes a surface of the substrate forming a first material layer over a resulting structure in which the trench is formed, forming a second material layer over the first material layer, removing portions of the second material layer and the first material layer formed on a bottom of the trench to expose the surface of the substrate, removing the second material layer, and burying a channel layer within the trench in which the second material layer is removed.10-14-2010
20120139029NONVOLATILE SEMICONDUCTOR MEMORY - A nonvolatile semiconductor memory of an aspect of the present invention includes a memory cell including, a charge storage layer on a gate insulating film, a multilayer insulator on the charge storage layer, and a control gate electrode on the multilayer insulator, the gate insulating film including a first tunnel film, a first high-dielectric-constant film on the first tunnel film and offering a greater dielectric constant than the first tunnel film, and a second tunnel film on the first high-dielectric-constant film and having the same configuration as that of the first tunnel film, the multilayer insulator including a first insulating film, a second high-dielectric-constant film on the first insulating film and offering a greater dielectric constant than the first insulating film, and a second insulating film on the second high-dielectric-constant film and having the same configuration as that of the first insulating film.06-07-2012
20130009232NON-VOLATILE MEMORY CELL AND FABRICATING METHOD THEREOF - A non-volatile memory cell includes a substrate, two charge trapping structures, a gate oxide layer, a gate and two doping regions. The charge trapping structures are disposed on the substrate separately. The gate oxide layer is disposed on the substrate between the two charge trapping structures. The gate is disposed on the gate oxide layer and the charge trapping structures, wherein the charge trapping structures protrude from two sides of the gate. The doping regions are disposed in the substrate at two sides of the gate.01-10-2013
20130009234SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a substrate, a first gate insulation film formed over a first device forming region disposed in the substrate, a second gate insulation film formed over a second device forming region disposed in the substrate, a lower gate electrode film formed over the first gate insulation film and over the second gate insulation film and comprising a metal nitride film; a mask film formed over the lower gate electrode film situated over the second gate insulation film, and an upper gate electrode film formed over the lower gate electrode film and over the mask film.01-10-2013
20130009233Transistor Constructions and Processing Methods - A transistor construction includes a first floating gate having a first conductive or semiconductive surface and a second floating gate having a second conductive or semiconductive surface. A dielectric region is circumferentially surrounded by the first surface. The region is configured to reduce capacitive coupling between the first and second surfaces. Another transistor construction includes a floating gate having a cavity extending completely through the floating gate from a first surface of the floating gate to an opposing second surface of the floating gate. The floating gate otherwise encloses the cavity, which is filled with at least one dielectric. A method includes closing an upper portion of an opening in insulator material with a gate material during the deposition before filling a lower portion with the gate material. The depositing and closing provide an enclosed cavity within the lower portion of the opening.01-10-2013
20100155817HTO OFFSET FOR LONG LEFFECTIVE, BETTER DEVICE PERFORMANCE - Memory devices having an increased effective channel length and/or improved TPD characteristics, and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The memory cell contains a charge trapping dielectric stack, a poly gate, a pair of pocket implant regions, and a pair of bit lines. The bit line can be formed by an implant process at a higher energy level and/or a higher concentration of dopants without suffering device short channel roll off issues because spacers at bit line sidewalls constrain the implant in narrower implant regions.06-24-2010
20130015520NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a nonvolatile semiconductor memory device includes a fin-type stacked layer structure in which a first insulating layer, a first semiconductor layer, . . . an n-th insulating layer, an n-th semiconductor layer, and an (n+1)-th insulating layer (n is a natural number equal to or more than 2) are stacked in order thereof in a first direction perpendicular to a surface of a semiconductor substrate and which extends in a second direction parallel to the surface of the semiconductor substrate, first to n-th memory strings which use the first to n-th semiconductor layers as channels respectively, a common semiconductor layer which combines the first to n-th semiconductor layers at first ends of the first to n-th memory strings in the second direction.01-17-2013
20130015519NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAMEAANM Fujii; ShosukeAACI Yokohama-shiAACO JPAAGP Fujii; Shosuke Yokohama-shi JPAANM Sakuma; KiwamuAACI Yokohama-shiAACO JPAAGP Sakuma; Kiwamu Yokohama-shi JPAANM Fujiki; JunAACI Yokohama-shiAACO JPAAGP Fujiki; Jun Yokohama-shi JPAANM Kinoshita; AtsuhiroAACI Kamakura-shiAACO JPAAGP Kinoshita; Atsuhiro Kamakura-shi JP - According to one embodiment, a nonvolatile semiconductor memory device includes first to n-th semiconductor layers which are stacked in a first direction perpendicular to a surface of a semiconductor substrate and which extend in a second direction parallel to the surface of the semiconductor substrate, an electrode which extends in the first direction along side surfaces of the first to n-th semiconductor layers, the side surfaces of the first to n-th semiconductor layers exposing in a third direction perpendicular to the first and second directions, and first to n-th charge storage layers located between the first to n-th semiconductor layers and the electrode respectively. The first to n-th charge storage layers are separated from each other in areas between the first to n-th semiconductor layers.01-17-2013
20100123182VERTICAL TYPE SEMICONDUCTOR DEVICE - A vertical pillar semiconductor device includes a substrate, a single crystalline semiconductor pattern, a gate insulation layer structure and a gate electrode. The substrate may include a first impurity region. The single crystalline semiconductor pattern may be on the first impurity region. The single crystalline semiconductor pattern has a pillar shape substantially perpendicular to the substrate. A second impurity region may be formed in an upper portion of the single crystalline semiconductor pattern. The gate insulation layer structure may include a charge storage pattern, the gate insulation layer structure on a sidewall of the single crystalline semiconductor pattern. The gate electrode may be formed on the gate insulation layer structure and opposite the sidewall of the single crystalline semiconductor pattern. The gate electrode has an upper face substantially lower than that of the single crystalline semiconductor pattern.05-20-2010
20110140193SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device having a non-volatile memory and a method of manufacturing the same are provided. The semiconductor device includes a base material and a stack structure. The stack structure disposed on the base material at least includes a tunneling layer, a trapping layer and a dielectric layer. The trapping layer is disposed on the tunneling layer. The dielectric layer has a dielectric constant and is disposed on the trapping layer. The dielectric layer is transformed from a first solid state to a second solid state when the dielectric layer undergoes a process.06-16-2011
20120241845SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A first insulation film is on a substrate. A first resistance part is on the first insulation film. A boundary film is on the first resistance part. A second resistance part is on the boundary film. A second insulation film is on the second resistance part. A first conductive part and a second conductive part are on the second insulation film, and are isolated from each other. The first conductive part includes a first connection part penetrating the second insulation film and the second resistance part and contacting a surface of the boundary film. The second conductive part includes a second connection part penetrating the second insulation film and the second resistance part and contacting a surface of the boundary film. The first resistance part is connected to the first conductive part via the first connection part, and is connected to the second conductive part via the second connection part.09-27-2012
20120241844NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a nonvolatile semiconductor memory device includes: first and second stacked bodies, first and second semiconductor pillars, a connection portion, a memory film, and a partitioning insulating layer. The stacked bodes include electrode films stacked along a first axis and an inter-electrode insulating film provided between the electrode films. Through-holes are provided in the stacked bodies. The semiconductor pillars are filled into the through-holes. The connection portion electrically connects the semiconductor pillars. The memory film is provided between the semiconductor pillars and the electrode films. The partitioning insulating layer partitions the first and second electrode films. A side surface of the first through-hole on the partitioning insulating layer side and a side surface of the second through-hole on the partitioning insulating layer side have a portion parallel to a plane orthogonal to a second axis from the first stacked body to the second stacked body.09-27-2012
20120241842NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a nonvolatile semiconductor memory device includes first and second stacked body, first and second semiconductor pillars, a connecting portion, a first memory film, and a dividing portion. The stacked bodies include a plurality of electrode films stacked along a first axis and as interelectrode insulating film provided between the electrode films. The first and second semiconductor pillars penetrate through the first and second stacked bodies along the first axis, respectively. The connecting portion electrically connects the first and second semiconductor pillars. The first memory film is provided between the electrode film and the semiconductor pillar. The dividing portion electrically divides the first and second electrode films from each other between the first semiconductor pillar and the second semiconductor pillar, is in contact with the connecting portion, and includes a stacked film including a material used for the first memory film.09-27-2012
20080246078Charge trap flash memory device and memory card and system including the same - A charge trap flash memory device and method of making same are provided. The device includes: a tunnel insulating layer, a charge trap layer; a blocking insulating layer; and a gate electrode sequentially formed on a substrate. The charge trap layer includes: plural trap layers comprising a first material having a first band gap energy level; spaced apart nanodots, each nanodot being at least partially surrounded by at least one of the trap layers, wherein the nanodots comprise a second material having a second band gap energy level that is lower than the first band gap energy level; and an intermediate blocking layer comprising a third material having a third band gap energy level that is higher than the first band gap energy level, formed between at least two of the trap layers. This structure prevents loss of charges from the charge trap layer and improves charge storage capacity.10-09-2008
20100090267Nonvolatile memory devices and methods of forming the same - Nonvolatile memory devices and methods of forming the same are provided, the nonvolatile memory devices may include first regions and second regions which extend in a first direction and are alternately disposed in a semiconductor substrate along a second direction crossing the first direction. Buried doped lines are formed at the first regions respectively and extend in the first direction. The buried doped lines may be doped with a dopant of a first conductivity type. Bulk regions doped with a dopant of a second conductivity type and device isolation patterns are disposed along the second direction. The bulk regions and the device isolation patterns may be formed in the second regions. Word lines crossing the buried doped lines and the bulk regions are formed parallel to one another. Contact structures are connected to the buried doped lines and disposed between the device isolation patterns. Sidewalls of the device isolation patterns disposed in the first direction overlap with the word lines directly adjacent to the contact structures.04-15-2010
20080230829Memory device and method of fabricating the same - A memory device and a method of fabricating the same. The memory device includes a substrate and a first gate electrode overlying the substrate. Overlying a top surface of the first gate electrode, a second gate electrode comprises end portions extending to spaces adjacent to the substrate and sidewalls of the first gate electrode. Further, a dielectric layer comprises a first portion sandwiched between the first gate electrode and the second gate electrode, and second portions extending from the first portion, sandwiched between the substrate and the end portions of the second gate electrode.09-25-2008
20130140624Semiconductor Structure and Method for Forming The Semiconductor Structure - The invention discloses a semiconductor structure comprising: a substrate, a conductor layer, and a dielectric layer surrounding the conductor layer on the substrate; a first insulating layer covering both of the conductor layer and the dielectric layer; a gate conductor layer formed on the first insulating layer, and a dielectric layer surrounding the gate conductor layer; and a second insulating layer covering both of the gate conductor layer and the dielectric layer surrounding the gate conductor layer; wherein a through hole filled with a semiconductor material penetrates through the gate conductor layer perpendicularly, the bottom of the through hole stops on the conductor layer, and a first conductor plug serving as a drain/source electrode is provided on the top of the through hole; and a second conductor plug serving as a source/drain electrode electrically contacts the conductor layer, and a third conductor plug serving as a gate electrode electrically contacts the gate conductor layer.06-06-2013
20130140622NONVOLATILE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A charge storage layer interposed between a memory gate electrode and a semiconductor substrate is formed shorter than a gate length of the memory gate electrode or a length of insulating films so as to make the overlapping amount of the charge storage layer and a source region to be less than 40 nm. Therefore, in the write state, since the movement in the transverse direction of the electrons and the holes locally existing in the charge storage layer decreases, the variation of the threshold voltage when holding a high temperature can be reduced. In addition, the effective channel length is made to be 30 nm or less so as to reduce an apparent amount of holes so that coupling of the electrons with the holes in the charge storage layer decreases; therefore, the variation of the threshold voltage when holding at room temperature can be reduced.06-06-2013
20130140623THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE - A three-dimensional semiconductor memory device may include gap-fill insulating layers extending upward from a substrate, an electrode structure delimited by sidewalls of the gap-fill insulating layers, vertical structures provided between adjacent ones of the gap-fill insulating layers to penetrate the electrode structure, and at least one separation pattern extending along the gap-fill insulating layers and penetrating at least a portion of the electrode structure. The separation pattern may include at least one separation semiconductor layer.06-06-2013
20130140621FLASH MEMORY - A MONOS Charge-Trapping flash (CTF), with record thinnest 3.6 nm ENT trapping layer, has a large 3.1V 10-year extrapolated retention window at 125° C. and excellent 1006-06-2013
20130175598Damascene Word Line - The technology relates to a damascene word line for a three dimensional array of nonvolatile memory cells. Conductive lines such as silicon are formed over stacked nonvolatile memory structures. Word line trenches separate neighboring ones of the silicon lines. The silicon lines separated by the word line trenches are oxidized, making insulating surfaces in the word line trenches. Word lines are made in the word line trenches.07-11-2013
20130181278NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE DEVICE - Provided is a non-volatile memory device that includes a substrate including a plurality of active regions extending in a first direction and a plurality of element isolation trenches disposed between the active regions, a plurality of tunnel insulating layer patterns and a plurality of storage layer patterns sequentially disposed on the substrate, a plurality of blocking insulating layers and a plurality of gate electrodes disposed on the storage layer patterns and extending in a second direction perpendicular to the first direction, and first insulating layers including air gaps disposed between the active regions on the element isolation trenches and extending in the first direction, wherein the active regions include first active regions and second active regions adjacent to the first active regions, wherein a width of first air gaps is different from a width of second air gaps.07-18-2013
20130181279SONOS STRUCTURE AND MANUFACTURING METHOD THEREOF - The invention provides an SONOS structure and a manufacturing method thereof The manufacturing method comprises: forming a tunneling oxide layer on a substrate; depositing a Si-rich silicon nitride layer above the tunneling oxide layer, wherein the Si/N content ratio of the Si-rich silicon nitride layer is constant; depositing a graded silicon nitride layer having graded silicon content above the Si-rich silicon nitride layer; and depositing a blocking oxide layer; wherein the silicon content of the graded silicon nitride layer is reduced in the direction from the Si-rich silicon nitride layer to the blocking oxide layer. According to the present invention, the Si-rich silicon nitride layer provides shallower trapping levels, which is beneficial to trap the charges and improve the programming and erasing speed. Furthermore, the charge retention time increases due to the constrained charges in the deep trapping levels, thus the reliability of the device enhances.07-18-2013
20130175599INLINE METHOD TO MONITOR ONO STACK QUALITY - Embodiments of structures and methods for determining operating characteristics of a non-volatile memory transistor comprising a charge-storage-layer and a tunneling-layer are described. In one embodiment, the method comprises: forming on a substrate a structure including a nitrided tunneling-layer and a charge-storage-layer overlying the tunneling-layer comprising a first charge-storage layer adjacent to the tunneling-layer, and a second charge-storage layer overlying the first charge-storage layer, wherein the first charge-storage layer is separated from the second charge-storage layer by a anti-tunneling layer comprising an oxide; depositing a positive charge on the charge-storage-layer and determining a first voltage to establish a first leakage current through the charge-storage-layer and the tunneling-layer; depositing a negative charge on the charge-storage-layer and determining a second voltage to establish a second leakage current through the charge-storage-layer and the tunneling-layer; and determining a differential voltage by calculating a difference between the first and second voltages.07-11-2013
20130175600SONOS STACK WITH SPLIT NITRIDE MEMORY LAYER - Embodiments of a non-planar memory device including a split charge-trapping region and methods of forming the same are described. Generally, the device comprises: a channel formed from a thin film of semiconducting material overlying a surface on a substrate connecting a source and a drain of the memory device; a tunnel oxide overlying the channel; a split charge-trapping region overlying the tunnel oxide, the split charge-trapping region including a bottom charge-trapping layer comprising a nitride closer to the tunnel oxide, and a top charge-trapping layer, wherein the bottom charge-trapping layer is separated from the top charge-trapping layer by a thin anti-tunneling layer comprising an oxide. Other embodiments are also disclosed.07-11-2013
20130175601FABRICATING METHOD OF MIRROR BIT MEMORY DEVICE HAVING SPLIT ONO FILM WITH TOP OXIDE FILM FORMED BY OXIDATION PROCESS - A device and method employing a polyoxide-based charge trapping component. A charge trapping component is patterned by etching a layered stack that includes a tunneling layer positioned on a substrate, a charge trapping layer positioned on the tunneling layer, and an amorphous silicon layer positioned on the charge trapping layer. An oxidation process grows a gate oxide layer from the substrate and converts the amorphous silicon layer into a polyoxide layer.07-11-2013
20130175602Non-Volatile Memory Device Having Three Dimensional, Vertical Channel, Alternately Stacked Gate Electrode Structure - A method for fabricating a non-volatile memory device, the method includes alternately stacking inter-layer dielectric layers and sacrificial layers over a substrate, etching the inter-layer dielectric layers and the sacrificial layers to form trenches to expose a surface of the substrate, etching the inter-layer dielectric layers exposed by the trenches to a predetermined thickness, forming junction layers over etched portions of the inter-layer dielectric layers, and burying a layer for a channel within the trenches in which the junction layers have been formed to form a channel.07-11-2013
20130175603VERTICAL CHANNEL TYPE NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a vertical channel type nonvolatile memory device includes: alternately forming a plurality of sacrificial layers and a plurality of interlayer dielectric layers over a semiconductor substrate; etching the sacrificial layers and the interlayer dielectric layers to form a plurality of first openings for channel each of which exposes the substrate; filling the first openings to form a plurality of channels protruding from the semiconductor substrate; etching the sacrificial layers and the interlayer dielectric layers to form second openings for removal of the sacrificial layers between the channels; exposing side walls of the channels by removing the sacrificial layers exposed by the second openings; and forming a tunnel insulation layer, a charge trap layer, a charge blocking layer, and a conductive layer for gate electrode on the exposed sidewalls of the channels.07-11-2013
20130181277SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THEREOF - A semiconductor device includes a semiconductor substrate having a first opening and a second opening adjacent thereto. A first dielectric layer is disposed in a lower portion of the first opening. A charge-trapping dielectric layer is disposed in an upper portion of the first opening to cover the first dielectric layer. A doping region of a predetermined conductivity type is formed in the semiconductor substrate adjacent to the first opening and the second opening, wherein the doping region of the predetermined conductivity type has a polarity which is different from that of the charges trapped in the charge-trapping dielectric layer. A gate electrode is disposed in a lower portion of the second opening. A method for fabricating the semiconductor device is also disclosed.07-18-2013
20080217680NON-VOLATILE SEMICONDUCTOR MEMORY USING CHARGE-ACCUMULATION INSULATING FILM - There is provided a non-volatile semiconductor memory having a charge accumulation layer of a configuration where a metal oxide with a dielectric constant sufficiently higher than a silicon nitride, e.g., a Ti oxide, a Zr oxide, or a Hf oxide, is used as a base material and an appropriate amount of a high-valence substance whose valence is increased two levels or more (a VI-valence) is added to produce a trap level that enables entrance and exit of electrons with respect to the base material.09-11-2008
20080217678Memory Gate Stack Structure - A memory gate stack structure (09-11-2008
20130134498MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A memory device is described, including a tunnel dielectric layer over a substrate, a gate over the tunnel dielectric layer, at least one charge storage layer between the gate and the tunnel dielectric layer, two doped regions in the substrate beside the gate, and a word line that is disposed on and electrically connected to the gate and has a thickness greater than that of the gate.05-30-2013
20130134497MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A memory device is described, including a gate over a substrate, a gate dielectric between the gate and the substrate, and two charge storage layers. The width of the gate is greater than that of the gate dielectric, so that two gaps are present at both sides of the gate dielectric and between the gate and the substrate. Each charge storage layer includes a body portion in one of the gaps, a first extension portion connected with the body portion and protruding out of the corresponding sidewall of the gate, and a second extension portion connected to the first extension portion and extending along the sidewall of the gate, wherein the edge of the first extension portion protrudes from the sidewall of the second extension portion.05-30-2013
20130092997NON-VOLATILE MEMORY AND MANUFACTURING METHOD THEREOF - A non-volatile memory and a manufacturing method thereof are provided. A first oxide layer having a protrusion is formed on a substrate. A pair of doped regions is formed in the substrate at two sides of the protrusion. A pair of charge storage spacers is formed on the sidewalls of the protrusion. A second oxide layer is formed on the first oxide layer and the charge storage spacers. A conductive layer is formed on the second oxide layer.04-18-2013
20130092998Memory Devices Capable Of Reducing Lateral Movement Of Charges - Memory devices are provided, the memory devices include a tunneling insulating layer disposed on a substrate, a charge storage layer disposed on the tunneling insulating layer, a blocking insulating layer disposed on the charge storage layer and a control gate electrode disposed on the blocking insulating layer. The control gate electrode may have an edge portion spaced farther apart from the blocking insulating layer than a central portion of the control gate electrode to concentrate charge density distribution on a central portion of a memory cell.04-18-2013
20130113034NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE, PRODUCTION METHOD FOR SAME, AND CHARGE STORAGE FILM - A non-volatile semiconductor memory device comprises a tunnel insulating film on a semiconductor substrate, a charge storage film on the tunnel insulating film, a blocking insulating film on the charge storage film, a control gate electrode arranged on the blocking insulating film, and source/drain regions formed on the semiconductor substrate on the both sides of the control gate electrode, that the charge storage film is a silicon nitride film produced according to the catalytic chemical vapor deposition technique and that the ratio between the constituent elements: N/Si falls within the range of from 1.2 to 1.4.05-09-2013
20130113033NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A non-volatile memory device in accordance with one embodiment of the present invention includes a substrate including a P-type impurity-doped region, a channel structure comprising a plurality of interlayer insulating layers that are alternately stacked with a plurality of channel layers on the substrate, a P-type semiconductor pattern that contacts sidewalls of the plurality of channel layers, wherein a lower end of the P-type semiconductor pattern contacts the P-type impurity-doped region, and source lines that are disposed at both sides of the P-type semiconductor pattern and contact the sidewalls of the plurality of channel layers.05-09-2013
20130113032SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor memory device includes a substrate, a conductive layer provided on a major surface of the substrate, a stacked body, a memory film, and a channel body. The stacked body includes multiple insulating layers alternately stacked with multiple electrode layers on the conductive layer. The memory film includes a charge storage film provided on side walls of holes made to pierce the stacked body. The channel body includes a pair of columnar portions and a linking portion. The pair of columnar portions is provided on an inner side of the memory film inside the holes. The linking portion is provided inside the conductive layer to link lower ends of the pair of columnar portions. The electrode layers are tilted with respect to the major surface of the substrate. The columnar portions of the channel body and the memory film pierce the tilted portion of the electrode layers.05-09-2013
20130126960Semiconductor Device and Method of Manufacturing the Same - Technique of improving a manufacturing yield of a semiconductor device including a non-volatile memory cell in a split-gate structure is provided. A select gate electrode of a CG shunt portion is formed so that a second height d05-23-2013
20110272756METHOD OF FORMING AN INSULATOR LAYER IN A SEMICONDUCTOR STRUCTURE AND STRUCTURES RESULTING THEREFROM - An electronic system, method of manufacture of a semiconductor structure, and one or more semiconductor structures are disclosed. For example, a method of manufacture of a semiconductor structure is disclosed, which includes forming a first semiconductor substructure over a semiconductor substrate, forming a first spacer layer over the first semiconductor substructure and the semiconductor substrate, and forming a second semiconductor substructure over at least a portion of the first spacer layer.11-10-2011
20130134499NONVOLATILE PROGRAMMABLE SWITCHES - A nonvolatile programmable switch according to an embodiment includes: a first nonvolatile memory transistor including a first to third terminals connected to a first to third interconnects respectively; a second nonvolatile memory transistor including a fourth terminal connected to a fourth interconnect, a fifth terminal connected to the second interconnect, and a sixth terminal connected to the third interconnect, the first and second nonvolatile memory transistors having the same conductivity type; and a pass transistor having a gate electrode connected to the second interconnect. When the first and fourth interconnects are connected to a first power supply while the third interconnect is connected to a second power supply having a higher voltage than that of the first power supply, a threshold voltage of the first nonvolatile memory transistor increases, and a threshold voltage of the second nonvolatile memory transistor decreases.05-30-2013
20090218613SEMICONDUCTOR TIME SWITCH SUITABLE FOR EMBEDDING IN NAND FLASH MEMORY DEVICE - A semiconductor time switch includes a cell portion and an electron booster. The cell portion contains parallel linear semiconductor layers provided on a substrate as active areas, first and second linear conductor layers alternately formed on the linear semiconductor layers through a gate insulating film as control gates and extending so as to cross the linear semiconductor layers, and floating gates inserted into respective intersections of the linear semiconductor layers and the first linear conductor layers, and coupled to the first linear conductor layers through an inter-gate insulating film. The electron booster is provided on the substrate and includes a MOS transistor having a booster gate electrode connected to the second linear conductor layers. Both ends of the linear semiconductor layers are connected to first and second I/O terminals of the switch, respectively.09-03-2009
20090096016Method of manufacturing a sonos device - A SONOS device and a method of manufacturing the same is provided. A tunnel dielectric layer, a charge trap layer, and a charge blocking layer are formed on a semiconductor substrate, and the charge blocking layer is formed on the charge trap layer such that the charge blocking layer is relatively thicker at regions adjacent to or overlapping the source and the drain and relatively thinner at a region overlapping the channel region. A gate is then formed on the blocking layer.04-16-2009
20080197404Method of fabricating semiconductor memory device and semiconductor memory device - A semiconductor memory device is fabricated by: forming a device isolation region in a recessed portion of a semiconductor substrate having an irregularly-shaped portion; forming a gate electrode wiring trench in a direction orthogonal to a longitudinal direction of an active region which is a projecting portion of the semiconductor substrate having the irregularly-shaped portion in the device isolation region; forming a gate electrode material layer so as to fill the gate electrode wiring trench; forming a gate electrode by patterning the layer formed of the gate electrode material; forming an active region by etching the device isolation region; forming a charge storage layer on at least one side surface of the gate electrode, the surface being adjacent to the projecting portion of the semiconductor substrate having the irregularly-shaped portion; and forming a side wall on at least a part of the charge storage layer.08-21-2008
20130126959SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, there are provided a first shaped pattern in which a plurality of first holes are arranged and of which a width is periodically changed along an arrangement direction of the first holes, a second shaped pattern in which a plurality of second holes are arranged and of which a width is periodically changed along an arrangement direction of the second holes, and slits which are formed along the arrangement direction of the first holes and separate the first shaped pattern and the second shaped pattern.05-23-2013
20110220987SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor memory device includes a base, a stacked body, a memory film, a channel body, an interconnection, and a contact plug. The base includes a substrate and a peripheral circuit formed on a surface of the substrate. The stacked body includes a plurality of conductive layers and a plurality of insulating layers alternately stacked above the base. The memory film is provided on an inner wall of a memory hole punched through the stacked body to reach a lowermost layer of the conductive layers. The memory film includes a charge storage film. The interconnection is provided below the stacked body. The interconnection electrically connects the lowermost layer of the conductive layers in an interconnection region laid out on an outside of a memory cell array region and the peripheral circuit. The contact plug pierces the stacked body in the interconnection region to reach the lowermost layer of the conductive layers in the interconnection region.09-15-2011
20110220986MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A memory device including a substrate, a conductive layer, a charge storage layer, first and second dopant regions and first and second cell dopant regions is provided. A plurality of trenches is deployed in the substrate. The conductive layer is disposed on the substrate and fills the trenches. The charge storage layer is disposed between the substrate and the conductive layer. The first and second dopant regions having a first conductive type are configured in the substrate under bottoms of the trenches and in an upper portion of the substrate between two adjacent trenches, respectively. The first and second cell dopant regions having a second conductive type are configured in the substrate between lower portions of side surfaces of the trenches and in the substrate adjacent to the bottoms of the second dopant regions, respectively. The first and the second conductive types are different dopant types.09-15-2011
20090309153METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A process of forming a non-volatile memory in a memory region on a silicon substrate, in which a select gate electrode is formed on a main surface of the silicon substrate, and a dummy gate adjacent to one of sidewall surfaces of the electrode is formed. Then, memory source/drain regions are formed by ion implantation using the dummy gate as an ion implantation mask. Then, the dummy gate is removed, and a charge accumulating film and a memory gate electrode are sequentially formed at the part where the dummy gate has been provided, thereby forming a structure in which the memory source/drain regions are arranged at portions below and lateral to the memory gate electrode. In this process, the charge accumulating film and the memory gate electrode are formed after the ion implantation for forming the memory source/drain regions is carried out.12-17-2009
20100308398Flash Memory Device With an Array of Gate Columns Penetrating Through a Cell Stack - A flash memory device includes a substrate; a cell stack having a semiconductor layer for providing junction areas and channel areas and an interlayer isolation layer for insulating the semiconductor layer, wherein the semiconductor layer and the interlayer isolation layer are repeatedly stacked; an array of gate columns, the gate columns penetrating through the cell stack, perpendicular to the substrate; and a trap layered stack introduced into an interface between the gate columns and the cell stack to store charge.12-09-2010
20100308397SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a semiconductor device includes forming an insulating film on a semiconductor region of a semiconductor substrate on which a MOS transistor is to be formed and patterning the insulating film; implanting an impurity into the semiconductor region through the patterned insulating film using a step of implanting an impurity into a source/drain region of the MOS transistor, to form, below the insulating film, a resistive layer of a resistance element to be formed in the semiconductor region; and siliciding a surface of the source/drain region of the MOS transistor using the insulating film as a silicidation-preventing film of the resistive layer.12-09-2010
20120273870MEMORY ARRAYS HAVING SUBSTANTIALLY VERTICAL, ADJACENT SEMICONDUCTOR STRUCTURES AND THE FORMATION THEREOF - Memory arrays and methods of their formation are disclosed. One such memory array has memory-cell strings are formed adjacent to separated substantially vertical, adjacent semiconductor structures, where the separated semiconductor structures couple the memory cells of the respective strings in series. For some embodiments, two dielectric pillars may be formed from a dielectric formed in a single opening, where each of the dielectric pillars has a pair of memory-cell strings adjacent thereto and where at least one memory cell of one of the strings on one of the pillars and at least one memory cell of one of the strings on the other pillar are commonly coupled to an access line.11-01-2012
20120273869NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device includes a charge storage layer on a first insulating film, a second insulating film which is provided on the charge storage layer, formed of layers, and a control gate electrode on the second insulating film. The second insulating film includes a bottom layer (A) provided just above the charge storage layer, a top layer (C) provided just below the control gate electrode, and a middle layer (B) provided between the bottom layer (A) and the top layer (C). The middle layer (B) has higher barrier height and lower dielectric constant than both the bottom layer (A) and the top layer (C). The average coordination number of the middle layer (B) is smaller than both the average coordination number of the top layer (C) and the average coordination number of the bottom layer (A).11-01-2012
20120273868NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURE THEREOF - A nonvolatile semiconductor storage device including a number of memory cells formed on a semiconductor substrate, each of the memory cells has a tunnel insulating film, a charge storage layer, a block insulating film, and a gate electrode which are formed in sequence on the substrate. The gate electrode is structured such that at least first and second gate electrode layers are stacked. The dimension in the direction of gate length of the second gate electrode layer, which is formed on the first gate electrode layer, is smaller than the dimension in the direction of gate length of the first gate electrode layer.11-01-2012
20120273867NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A non-volatile memory device includes a substrate; a first conductive layer over the substrate, a second conductive layer over the first conductive layer, a stacked structure disposed over the second conductive layer, wherein the stacked structure includes a plurality of first inter-layer dielectric layers and a plurality of third conductive layers alternately stacked, a pair of first channels that penetrate the stacked structure and the second conductive layer, a second channel which is buried in the first conductive layer, covered by the second conductive layer, and coupled to lower ends of the pair of the first channels; and a memory layer formed along internal walls of the first and second channels.11-01-2012
20120273866Semiconductor Memory Device with a Buried Drain and Its Memory Array - A semiconductor memory device with a buried drain is provided. The device comprises a semiconductor substrate (11-01-2012
20130207178SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes word lines and interlayer insulating layers alternately stacked over a substrate, vertical channel layers protruding from the substrate and passing through the word lines and the interlayer insulating layers, a tunnel insulating layer surrounding each of the vertical channel layers, a charge trap layer surrounding the tunnel insulating layer, wherein first regions of the charge trap layer between the tunnel insulating layer and the word lines have a thickness smaller than a thickness of second regions thereof between the tunnel insulating layer and the interlayer insulating layers, and first charge blocking layer patterns surrounding the first regions of the charge trap layer.08-15-2013
20130187217NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a nonvolatile semiconductor memory device is provided in which memory strings, which are formed by providing a plurality of transistors having gate electrode films on sides of columnar semiconductor films in a height direction of the columnar semiconductor films via charge storage layers, are substantially perpendicularly arranged in a matrix shape on a substrate. A coupling section made of a semiconductor material that connects lower portions of the columnar semiconductor films forming a pair of the memory strings adjacent to each other in a predetermined direction is provided. Each of the columnar semiconductor films is formed of a generally single-crystal-like germanium film or silicon germanium film.07-25-2013
20110233653NON-VOLATILE SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING NON-VOLATILE SEMICONDUCTOR DEVICES - A non-volatile semiconductor device includes a memory cell in a first area of a substrate, a low voltage transistor in a second area of the substrate, and a high voltage transistor in a third area of the substrate. The memory cell includes a tunnel insulation layer formed on the substrate, a charge trapping layer pattern formed on the tunnel insulation layer in the first area of the substrate, a blocking layer pattern formed on the charge trapping layer pattern and a control gate formed on the blocking layer pattern. The control gate has a width substantially smaller than a width of the blocking layer pattern and the width of the control gate is substantially smaller than a width of the charge trapping layer pattern. In addition, an offset is formed between the control gate and the blocking layer pattern such that a spacer is not formed on a sidewall of the control gate.09-29-2011
20110233652NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE - A non-volatile semiconductor storage device includes: a memory cell area in which a plurality of electrically rewritable memory cells are formed; and a peripheral circuit area in which transistors that configure peripheral circuits to control the memory cells are formed. The memory cell area has formed therein: a semiconductor layer formed to extend in a vertical direction to a semiconductor substrate; a plurality of conductive layers extending in a parallel direction to, and laminated in a vertical direction to the semiconductor substrate; and a property-varying layer formed between the semiconductor layer and the conductive layers and having properties varying depending on a voltage applied to the conductive layers. The peripheral circuit area has formed therein a plurality of dummy wiring layers that are formed on the same plane as each of the plurality of conductive layers and that are electrically separated from the conductive layers.09-29-2011
20110233651METHOD TO SEPERATE STORAGE REGIONS IN THE MIRROR BIT DEVICE - Devices and methods for isolating adjacent charge accumulation layers in a semiconductor device are disclosed. In one embodiment, a semiconductor device comprises a bit line formed in a semiconductor substrate, a charge accumulation layer formed on the semiconductor substrate, a word line formed on the charge accumulation layer across the bit line, and a channel region formed in the semiconductor substrate below the word line and between the bit line and its adjacent bit line. For the semiconductor device, the charge accumulation layer is formed above the channel region in a widthwise direction of the word line, and a width of the word line is set to be narrower than a distance between an end of the channel region and a central part of the channel region in a lengthwise direction of the word line.09-29-2011
20110233650NONVOLATILE MEMORY DEVICES AND METHODS OF FORMING THE SAME - Provided are nonvolatile memory devices and methods of forming nonvolatile memory devices. Nonvolatile memory devices include a device isolation layer that defines an active region in a substrate. Nonvolatile memory devices further include a first insulating layer, a nonconductive charge storage pattern, a second insulating layer and a control gate line that are sequentially disposed on the active region. The charge storage pattern includes a horizontal portion and a protrusion disposed on an upper portion of an edge of the horizontal portion.09-29-2011
20110233649NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - A non-volatile semiconductor memory device includes: a charge accumulation layer (CAL) on a substrate; a memory gate formed onto the substrate through the CAL; a first side gate formed through a first insulating film on a first side of the memory gate; a second side gate formed through a second insulating film on a second side opposite to the first side; a first impurity implantation region (IIR09-29-2011
20110233648Three-Dimensional Semiconductor Memory Devices And Methods Of Fabricating The Same - Three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor devices include an electrode structure with sequentially-stacked electrodes disposed on a substrate, semiconductor patterns penetrating the electrode structure, and memory elements including a first pattern and a second pattern interposed between the semiconductor patterns and the electrode structure, the first pattern vertically extending to cross the electrodes and the second pattern horizontally extending to cross the semiconductor patterns.09-29-2011
20110233647METHODS FOR FORMING A MEMORY CELL HAVING A TOP OXIDE SPACER - Methods for fabricating a semiconductor memory cell that has a spacer layer are disclosed. A method includes forming a plurality of source/drain regions in a substrate where the plurality of source/drain regions are formed between trenches, forming a first oxide layer above the plurality of source/drain regions and in the trenches, forming a charge storage layer above the oxide layer and separating the charge storage layer in the trenches where a space is formed between separated portions of the charge storage layer. The method further includes forming a spacer layer to fill the space between the separated portions of the charge storage layer and to rise a predetermined distance above the space. A second oxide layer is formed above the charge storage layer and the spacer layer and a polysilicon layer is formed above the second oxide layer.09-29-2011
20110233646NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a nonvolatile semiconductor memory device is provided in which memory strings, which are formed by providing a plurality of transistors having gate electrode films on sides of columnar semiconductor films in a height direction of the columnar semiconductor films via charge storage layers, are substantially perpendicularly arranged in a matrix shape on a substrate. A coupling section made of a semiconductor material that connects lower portions of the columnar semiconductor films forming a pair of the memory strings adjacent to each other in a predetermined direction is provided. Each of the columnar semiconductor films is formed of a generally single-crystal-like germanium film or silicon germanium film.09-29-2011
20110233645MANUFACTURING METHOD OF NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND NONVOLATILE SEMICONDUCTOR STORAGE DEVICE - According to one embodiment, a manufacturing method of a nonvolatile semiconductor storage device, includes: forming a plurality of structures above a semiconductor substrate, each of the plurality of structures being such that in a stacked film where a plurality of first semiconductor films and a plurality of second semiconductor films are stacked alternately at least the second semiconductor films are held by a semiconductor or conductor pillar member via a gate dielectric film; selectively removing the first semiconductor films from the stacked film while maintaining a state where the second semiconductor films are held by the pillar member for each of the structures; oxidizing an exposed surface for each of the structures after removing the first semiconductor films; and embedding an inter-layer dielectric film between the plurality of structures in which the exposed surface is oxidized.09-29-2011
20110233644NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a nonvolatile semiconductor memory device includes first and second stacked structural bodies, first and second semiconductor pillars, a memory unit connection portion, a selection unit stacked structural body, first and second selection unit semiconductor pillars, a selection unit connection portion, and first to fifth interconnections. The semiconductor pillars pierce the stacked structural bodies. The first and second interconnections are connected to the first and second semiconductor pillars, respectively. The memory unit connection portion connects the first and second semiconductor pillars. The selection unit semiconductor pillars pierce the selection unit stacked structural body. The third and fourth interconnections are connected to the first and second selection unit semiconductor pillars, respectively. The selection unit connection portion connects the first and second selection unit semiconductor pillars. The fifth interconnection is connected to the third interconnection on a side opposite to the selection unit stacked structural body.09-29-2011
20100314680MEMORY ARRAY - A memory array includes a charge storage structure and a plurality of conductive materials over the charge storage structure is provided. Each conductive material, serving as a word line, has a substantially arc-sidewall and a substantially straight sidewall.12-16-2010
20100314679CHARGE TRAPPING NONVOLATILE MEMORY DEVICES WITH A HIGH-K BLOCKING INSULATION LAYER - Provided is a charge trapping nonvolatile memory device. The charge trapping nonvolatile memory device includes: an active pattern and a gate electrode, spaced apart from each other; a charge storage layer between the active pattern and the gate electrode; a tunnel insulation layer between the active pattern and the charge storage layer; and a blocking insulation layer disposed between the charge storage layer and the gate electrode and including a high-k layer with a higher dielectric constant than the tunnel insulation layer and a barrier insulation layer with a higher band gap than the high-k layer. A physical thickness of the high-k layer is less than or identical to that of the barrier insulation layer12-16-2010
20100314678NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a non-volatile memory device, the method includes alternately stacking inter-layer dielectric layers and sacrificial layers over a substrate, etching the inter-layer dielectric layers and the sacrificial layers to form trenches to expose a surface of the substrate, etching the inter-layer dielectric layers exposed by the trenches to a predetermined thickness, forming junction layers over etched portions of the inter-layer dielectric layers, and burying a layer for a channel within the trenches in which the junction layers have been formed to form a channel.12-16-2010
201301539833-D NONVOLATILE MEMORY DEVICE, MEMORY SYSTEM INCLUDING THE 3-D NONVOLATILE MEMORY DEVICE, AND METHOD OF MANUFACTURING THE 3-D NONVOLATILE MEMORY DEVICE - A three dimensional (3-D) nonvolatile memory device includes a first pipe gate layer, a second pipe gate disposed over the first pipe gate layer, word lines formed over the second pipe gate layer, memory channel layers configured to penetrate the word lines, a pipe channel layer formed in the first pipe gate layer, where the pipe channel layer is to come in contact with the bottom surface of the second pipe gate layer and couple the lower ends of the memory channel layers, a memory layer configured to surround the pipe channel layer and the memory channel layers, and a first gate insulating layer interposed between the first pipe gate layer and the memory layer.06-20-2013
20130153984Semiconductor Constructions, NAND Unit Cells, Methods of Forming Semiconductor Constructions, and Methods of Forming NAND Unit Cells - Some embodiments include methods of forming semiconductor constructions. Alternating layers of n-type doped material and p-type doped material may be formed. The alternating layers may be patterned into a plurality of vertical columns that are spaced from one another by openings. The openings may be lined with tunnel dielectric, charge-storage material and blocking dielectric. Alternating layers of insulative material and conductive control gate material may be formed within the lined openings. Some embodiments include methods of forming NAND unit cells. Columns of alternating n-type material and p-type material may be formed. The columns may be lined with a layer of tunnel dielectric, a layer of charge-storage material, and a layer of blocking dielectric. Alternating layers of insulative material and conductive control gate material may be formed between the lined columns. Some embodiments include semiconductor constructions, and some embodiments include NAND unit cells.06-20-2013
20130153985NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A MONOS type non-volatile semiconductor memory device which is capable of electrically writing, erasing, reading and retaining data, the memory device including source/drain regions, a first gate insulating layer, a first charge trapping layer formed on the first gate insulating layer, a second gate insulating layer formed on the first charge trapping layer, and a controlling electrode formed on the second gate insulating layer. The first charge trapping layer includes an insulating film containing Al and O as major elements and having a defect pair formed of a complex of an interstitial O atom and a tetravalent cationic atom substituting for an Al atom, the insulating film also having electron unoccupied levels within the range of 2 eV-6 eV as measured from the valence band maximum of Al06-20-2013
20130153982SEMICONDUCTOR DEVICE CAPABLE OF REDUCING INFLUENCES OF ADJACENT WORD LINES OR ADJACENT TRANSISTORS AND FABRICATING METHOD THEREOF - A semiconductor device capable of reducing influences of adjacent word lines is provided in the present invention. The semiconductor device includes: a substrate, and a word line disposed in the substrate. The word line includes: a gate electrode, a gate dielectric layer disposed between the gate electrode and the substrate and at least one first charge trapping dielectric layer disposed adjacent to the gate electrode, wherein the first charge trapping dielectric layer comprises HfO06-20-2013
20090212353NON-VOLATILE MEMORY - A non-volatile memory includes a substrate having two openings, a stacked gate structure disposed on the substrate between the two openings, a liner disposed on a bottom of each of the two openings and parts of a sidewall of each of the two openings, a second conductive layer disposed on the liner at the bottom of each of the two openings, and a third conductive layer on the second conductive layer and the liner. The stacked gate structure includes a first dielectric layer, a charge storage layer, a second dielectric layer, and a first conductive layer. The liner has a top surface lower than that of the substrate. The second conductive layer has a top surface co-planar with that of the liner. The third conductive layer has a top surface at least co-planar with that of the substrate and lower than that of the first dielectric layer.08-27-2009
20110298039NONVOLATILE SEMICONDUCTOR MEMORY DEVICE PROVIDED WITH CHARGE STORAGE LAYER IN MEMORY CELL - A nonvolatile semiconductor memory device includes a semiconductor substrate, a first insulation layer formed on the semiconductor substrate, a charge storage layer formed on the first insulation layer, a second insulation layer formed on the charge storage layer, and a control electrode formed on the second insulation layer. The second insulation layer includes a first silicon oxide film formed above the charge storage layer, a silicon nitride film formed on the first silicon oxide film, a metal oxide film formed on the silicon nitride film, and a nitride film formed on the metal oxide film. The metal oxide film has a relative permittivity of not less than 7.12-08-2011
20130119456SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes: a substrate; a stacked body provided above the substrate, including a selector gate and an insulating layer provided on the selector gate; an insulating film provided on a sidewall of a hole formed by penetrating the stacked body in the stacking direction; a channel body and a semiconductor layer. The channel body is provided on a sidewall of the insulating film in the hole, that blocks the hole near an end of the insulating layer side in the selector gate, and that encloses a cavity below a part that blocks the hole. The semiconductor layer is formed of a same material as the channel body and is embedded continuously in the hole above the part where the channel body blocks the hole.05-16-2013
20130119455NAND FLASH WITH NON-TRAPPING SWITCH TRANSISTORS - A manufacturing method for a memory array includes first forming a multilayer stack of dielectric material on a plurality of semiconductor strips, and then exposing the multilayer stack in switch transistor regions. The multilayer stacks exposed in the switch transistor regions are processed to form gate dielectric structures that are different than the dielectric charge trapping structures. Word lines and select lines are then formed. A 3D array of dielectric charge trapping memory cells includes stacks of NAND strings of memory cells. A plurality of switch transistors are coupled to the NAND strings, the switch transistors including gate dielectric structures wherein the gate dielectric structures are different than the dielectric charge trapping structures.05-16-2013
20110303971THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a three-dimensional semiconductor memory includes forming a plurality of stacked structures disposed on a substrate to be spaced apart from each other, each of the stacked structures including a plurality of dielectric patterns and a plurality of polysilicon patterns alternately stacked, forming a metal layer to cover sidewalls of the stacked structures and a top surface of the substrate exposed between the stacked structures, and forming stacked gate electrodes on the substrate and a conductive line in the substrate by performing a silicidation process between the metal layer and each of the polysilicon patterns and the substrate.12-15-2011
20110303970VERTICAL SEMICONDUCTOR DEVICES - A vertical semiconductor device and a method of making a vertical semiconductor device include a first semiconductor pattern formed on a substrate and a first gate structure formed on a sidewall of the first semiconductor pattern. A second semiconductor pattern is formed on the first semiconductor pattern. A plurality of insulating interlayer patterns is formed on sidewalls of the second semiconductor pattern. The insulating interlayer patterns are spaced apart from each other to define grooves between the insulating interlayer patterns. The plurality of second gate structures is disposed in the grooves, respectively.12-15-2011
20110303969SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a semiconductor memory device with memory cells each composed of a vertical transistor, comprises a silicon layer formed into a columnar shape on a silicon substrate, a gate insulating film part in which a tunnel insulating film, a charge storage layer, and a block insulating film are formed to surround the sidewall surface of the silicon layer, and a stacked structure part formed to surround the sidewall surface of the gate insulating film part and in which a plurality of interlayer insulating films and a plurality of control gate electrode layers are stacked alternately. The silicon layer, gate insulating film part, and control gate electrode layer constitute the vertical transistor. The charge storage layer has a region lower in trap level than a region facing the control gate electrode layer between the vertical transistors.12-15-2011
20110303968Nonvolatile Memory Array With Continuous Charge Storage Dielectric Stack - An integrated circuit of an array of nonvolatile memory cells has a dielectric stack layer over the substrate, and implanted regions in the substrate under the dielectric stack layer. The dielectric stack layer is continuous over a planar region, that includes locations of the dielectric stack layer that store nonvolatile data, such that these locations are accessed by word lines/bit lines.12-15-2011
20110309433Semiconductor Device With Resistor Pattern And Method Of Fabricating The Same - Disclosed is a semiconductor device with a resistor pattern and methods of fabricating the same. Embodiments of the present invention provide a method of fabricating a resistor pattern having high sheet resistance by using a polycide layer for a gate electrode in a semiconductor device with the resistor pattern. Embodiments of the invention also provide a semiconductor device with a resistor pattern that is formed narrower than the minimum line width that can be defined in a photolithographic process so that sheet resistance thereof increases, and a method of fabricating the same.12-22-2011
20110309432NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a nonvolatile semiconductor memory device includes a stacked body including electrode films stacked in a first direction; a conductive pillar piercing the stacked body in the first direction; a inner insulating film; a semiconductor pillar; an intermediate insulating film; a memory layer; and an outer insulating film. The inner insulating film, the semiconductor pillar, the intermediate insulating film, the memory layer and the outer insulating film are provided between the conductive pillar and the electrode films. The inner insulating film is provided around a side face of the conductive pillar. The semiconductor pillar is provided around a side face of the inner insulating film. The intermediate insulating film is provided around a side face of the semiconductor pillar. The memory layer is provided around a side face of the intermediate insulating film. The outer insulating film is provided around a side face of the memory layer.12-22-2011
20110309431NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a nonvolatile semiconductor memory device includes a stacked structure, a select gate electrode, a semiconductor pillar, a memory layer, and a select gate insulating film. The stacked structure includes a plurality of electrode films stacked in a first direction and an interelectrode insulating film provided between the electrode films. The select gate electrode is stacked with the stacked structure along the first direction and includes a plurality of select gate conductive films stacked in the first direction and an inter-select gate conductive film insulating film provided between the select gate conductive films. The semiconductor pillar pierces the stacked structure and the select gate electrode in the first direction. The memory layer is provided between the electrode films and the semiconductor pillar. The select gate insulating film is provided between the select gate conductive films and the semiconductor pillar.12-22-2011
20080211011NONVOLATILE SEMICONDUCTOR MEMORY ELEMENT AND NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - It is made possible to provide a nonvolatile semiconductor memory element that can be miniaturized and can store multi-level data. A nonvolatile semiconductor memory element includes a semiconductor substrate; a source region and a drain region formed at a distance from each other in the semiconductor substrate; and a gate structure formed on a portion of the semiconductor substrate, the portion being located between the source region and the drain region. The gate structure includes a tunnel insulating layer, a resistance variable layer formed above the tunnel insulating layer and made of a metal oxide, and a first electrode formed on the resistance variable layer.09-04-2008
20090045453NONVOLATILE MEMORY DEVICES INCLUDING GATE CONDUCTIVE LAYERS HAVING PEROVSKITE STRUCTURE AND METHODS OF FABRICATING THE SAME - A nonvolatile memory device includes a tunneling insulating layer on a semiconductor layer. A charge storage layer is on the tunneling insulating layer. A blocking insulating layer having a Perovskite structure is on the charge storage layer. A gate conductive layer having a Perovskite structure is on the blocking insulating layer.02-19-2009
20120018797NONVOLATILE MEMORY DEVICE, AND METHODS OF MANUFACTURING AND DRIVING THE SAME - A nonvolatile memory device includes a device isolation film defining an active region in a semiconductor substrate, a pocket well region formed in an upper portion of the active region and having a first conductivity type, a gate electrode formed on the active region and extending to intersect the active region, a tunnel insulating film, a charge storage film, and a blocking insulating film sequentially disposed between the active region and the gate electrode, a source region and a drain region respectively formed in a first region and a second region of the active region exposed on both sides of the gate electrode, and each having a second conductivity type opposite to the first conductivity type, a pocket well junction region formed in the first region adjacent to the source region and contacting the pocket well region, and having the first conductivity type, and a metal silicide layer formed in the first region and contacting the source region and the pocket well junction region.01-26-2012
20120018796NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a nonvolatile semiconductor memory device includes first and second stacked structures, first and second semiconductor pillars, first and second memory units, and a semiconductor connection portion. The stacked structures include electrode films and first inter-electrode insulating films alternately stacked in a first direction. The second stacked structure is aligned with the first stacked structure in a second direction perpendicular to the first. The first and second semiconductor pillars pierce the first and second stacked structures, respectively. The first and second memory units are provided between the electrode films and the semiconductor pillar, respectively. The semiconductor connection portion connects the first and second semiconductor pillars and includes: an end connection portion; and a first protrusion having a side face continuous with a side face of the first semiconductor pillar. The semiconductor connection portion does not include a portion smaller than a diameter of the first semiconductor pillar.01-26-2012
20120018795NON-VOLATILE MEMORY AND MANUFACTURING METHOD THEREOF - A manufacturing method of a non-volatile memory is disclosed. A gate structure is formed on a substrate and includes a gate dielectric layer and a gate conductive layer. The gate dielectric layer is partly removed, thereby a symmetrical opening is formed among the gate conductive layer, the substrate and the gate dielectric layer, and a cavity is formed on end sides of the gate dielectric layer. A first oxide layer is formed on a sidewall and bottom of the gate conductive layer, and a second oxide layer is formed on a surface of the substrate. A nitride material layer is formed covering the gate structure, the first and second oxide layer and the substrate and filling the opening. An etching process is performed to partly remove the nitride material layer, thereby a nitride layer is formed on a sidewall of the gate conductive layer and extending into the opening.01-26-2012
20130193506SEMICONDUCTOR DEVICE HAVING DIFFERENT NON-VOLATILE MEMORIES HAVING NANOCRYSTALS OF DIFFERING DENSITIES AND METHOD THEREFOR - A method for forming a semiconductor device includes forming a first plurality of nanocrystals over a surface of a substrate having a first region and a second region, wherein the first plurality of nanocrystals is formed in the first region and the second region and has a first density; and, after forming the first plurality of nanocrystals, forming a second plurality of nanocrystals over the surface of the substrate in the second region and not the first region, wherein the first plurality of nanocrystals together with the second plurality of nanocrystals in the second region result in a second density, wherein the second density is greater than the first density.08-01-2013
20120025296SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method for manufacturing the same are disclosed. The method for manufacturing the semiconductor device comprises: forming a plurality of first pillar patterns each of which includes a sidewall contact by selectively etching a semiconductor substrate; forming a buried bit line at a lower portion of a region between two neighboring first pillar patterns; forming a plurality of second pillar patterns by selectively etching upper portions of the first pillar patterns; and forming a gate coupling second pillar patterns arranged in a direction crossing the bit line, the gate enclosing the second pillar patterns.02-02-2012
20120032250SEMICONDUCTOR DEVICES - A semiconductor device can include a first substrate and conductive patterns on the first substrate, where the conductive patterns are disposed in stacks vertically extending from the substrate. An active pillar can be on the first substrate vertically extend from the first substrate through the conductive patterns to provide vertical string transistors on the first substrate. A second substrate can be on the conductive patterns and the active pillar opposite the first substrate. A peripheral circuit transistor can be on the second substrate opposite the first substrate, where the peripheral circuit transistor can be adjacent to and overlap an uppermost pattern of the conductive patterns.02-09-2012
20120061744THREE DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES - Three dimensional semiconductor memory devices are provided. The three dimensional semiconductor memory device includes a first stacked structure and a second stacked structure sequentially stacked on a substrate. The first stacked structure includes first insulating patterns and first gate patterns which are alternately and repeatedly stacked on a substrate, and the second stacked structure includes second insulating patterns and second gate patterns which are alternately and repeatedly stacked on the first stacked structure. A plurality of first vertical active patterns penetrate the first stacked structure, and a plurality of second vertical active patterns penetrate the second stacked structure. The number of the first vertical active patterns is greater than the number of the second vertical active patterns.03-15-2012
20120068257SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, there is provided a semiconductor memory device including an element region, a first gate insulating film, a charge accumulation layer, a second gate insulating film, a control gate electrode, and a control gate electrode. The charge accumulation layer covers the first gate insulating film. The second gate insulating film has a first portion and a second portion. The first portion covers an upper surface of the charge accumulation layer when a side of a surface on which the element region of the semiconductor substrate is demarcated is an upper side. The second portion covers a side surface of the charge accumulation layer. The control gate electrode covers the upper surface and the side surface of the charge accumulation layer via the second gate insulating film. A breakdown voltage of the first portion is higher than a breakdown voltage of the second portion.03-22-2012
20120068252SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a substrate, a multilayer body, a semiconductor member and a charge storage layer. The multilayer body is provided on the substrate, with a plurality of insulating films and electrode films alternately stacked, and includes a first staircase and a second staircase opposed to each other. The semiconductor member is provided in the multilayer body outside a region provided with the first staircase and the second staircase, and the semiconductor member extends in stacking direction of the insulating films and the electrode films. The charge storage layer is provided between each of the electrode films and the semiconductor member. The each of the electrode films includes a first terrace formed in the first staircase, a second terrace formed in the second staircase and a bridge portion connecting the first terrace and the second terrace.03-22-2012
20120068251SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a multilayer body, a block layer, a charge storage layer, a tunnel layer, and a semiconductor pillar. The multilayer body includes a plurality of insulating films and electrode films alternately stacked. The multilayer body includes a through hole extending in stacking direction of the insulating films and the electrode films. The block layer is provided on an inner surface of the through hole. The charge storage layer is surrounded by the block layer. The tunnel layer is surrounded by the charge storage layer. The semiconductor pillar is surrounded by the tunnel layer. Dielectric constant of a portion of the tunnel layer on a side of the semiconductor pillar is higher than dielectric constant of a portion of the tunnel layer on a side of the charge storage layer.03-22-2012
20120086070FABRICATION METHOD AND STRUCTURE OF SEMICONDUCTOR NON-VOLATILE MEMORY DEVICE - A non-volatile semiconductor memory device with good write/erase characteristics is provided. A selection gate is formed on a p-type well of a semiconductor substrate via a gate insulator, and a memory gate is formed on the p-type well via a laminated film composed of a silicon oxide film, a silicon nitride film, and a silicon oxide film. The memory gate is adjacent to the selection gate via the laminated film. In the regions on both sides of the selection gate and the memory gate in the p-type well, n-type impurity diffusion layers serving as the source and drain are formed. The region controlled by the selection gate and the region controlled by the memory gate located in the channel region between said impurity diffusion layers have the different charge densities of the impurity from each other.04-12-2012
20120086069NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - In one embodiment, a nonvolatile semiconductor memory device includes a substrate; a tunnel insulating film on the substrate; a charge storage layer on the tunnel insulating film; a block insulating film on the charge storage layer; a first element isolation insulating film in an element isolation trench in the substrate, having a bottom surface lower than an interface between the substrate and the tunnel insulating film, and having a top surface lower than an interface between the charge storage layer and the block insulating film; a second element isolation insulating film on the first element isolation insulating film, protruding to a top surface of the block insulating film, in contact with a side surface of the block insulating film, and having a higher Si concentration than the block insulating film; and a control gate electrode on the block insulating film and on the second element isolation insulating film.04-12-2012
20130207177NONVOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - The nonvolatile memory device includes a semiconductor layer including trenches formed in a first direction, isolation layers filling the trenches, and active regions divided by the isolation layer, first insulating patterns formed on the semiconductor substrate in a second direction crossing the first direction, charge storage layer patterns formed over the respective active regions between the first insulating patterns, and second insulating patterns formed on the isolation layers between the charge storage layer patterns.08-15-2013