Inventors list

Assignees list

Classification tree browser

Top 100 Inventors

Top 100 Assignees


With additional contacted control electrode

Subclass of:

257 - Active solid-state devices (e.g., transistors, solid-state diodes)

257213000 - FIELD EFFECT DEVICE

257288000 - Having insulated electrode (e.g., MOSFET, MOS diode)

257314000 - Variable threshold (e.g., floating gate memory device)

257315000 - With floating gate electrode

Patent class list (only not empty are listed)

Deeper subclasses:

Class / Patent application numberDescriptionNumber of patent applications / Date published
257321000 With thin insulator region for charging or discharging floating electrode by quantum mechanical tunneling 167
257319000 Plural additional contacted control electrodes 72
257317000 With irregularities on electrode to facilitate charging or discharging of floating electrode 5
20100032746USE OF DILUTE STEAM AMBIENT FOR IMPROVEMENT OF FLASH DEVICES - The present invention provides a flash memory integrated circuit and a method for fabricating the same. The method includes etching a gate stack that includes an initial oxide layer directly in contact with a silicon layer, defining an oxide-silicon interface therebetween. By exposing the etched gate stack to elevated temperatures and a dilute steam ambient, additional oxide material is formed substantially uniformly along the oxide-silicon interface. Polysilicon grain boundaries at the interface are thereby passivated after etching. In the preferred embodiment, the interface is formed between a tunnel oxide and a floating gate, and passivating the grain boundaries reduces erase variability due to enhanced charge transfer along grain boundaries. At the same time, oxide in an upper storage dielectric layer (oxide-nitride-oxide or ONO) is enhanced in the dilute steam oxidation. Thermal budget can be radically conserved by growing thin oxide layers on either side of a nitride layer prior to etching, and enhancing the oxide layers by dilute steam oxidation through the exposed sidewall after etching. The thin oxide layers, like the initial tunnel oxide, serve as diffusion paths to enhance uniform distribution of OH species across the buried interfaces being oxidized.02-11-2010
20080230827SCALABLE FLASH/NV STRUCTURES AND DEVICES WITH EXTENDED ENDURANCE - Devices and methods are provided with respect to a gate stack for a nonvolatile structure. According to one aspect, a gate stack is provided. One embodiment of the gate stack includes a tunnel medium, a high K charge blocking and charge storing medium, and an injector medium. The high K charge blocking and charge storing medium is disposed on the tunnel medium. The injector medium is operably disposed with respect to the tunnel medium and the high K charge blocking and charge storing medium to provide charge transport by enhanced tunneling. According to one embodiment, the injector medium is disposed on the high K charge blocking and charge storing medium. According to one embodiment, the tunnel medium is disposed on the injector medium. Other aspects and embodiments are provided herein.09-25-2008
20090212344FLASH MEMORY DEVICE - Disclosed herein is a flash memory device in which the distribution of threshold voltage is significantly reduced and the durability is improved even though a floating gate has a micro- or nano-size length. It comprises a tunneling insulation film formed on a semiconductor substrate; a multilayer floating gate structure comprising a first thin storage electrode, a second thick storage electrode, and a third thin storage electrode, defined in that order on the tunneling insulation film; an interelectrode insulation film and a control electrode formed in that order on the floating gate structure; and a source/drain provided in the semiconductor substrate below the opposite sidewalls of the floating gate structure. The novel flash memory device can be readily fabricated at a high yield through a process compatible with a conventional one.08-27-2009
20080224201Flash Memory Devices and Methods of Fabricating the Same - Flash memory devices and methods of fabricating the same are disclosed. A disclosed method comprises doping at least one active region of a substrate, and forming an etching mask layer on the active region. The etching mask layer defines an opening exposing a portion of the active region. The disclosed method further comprises forming an etching groove in the active region. The etching groove separates a source region and a drain region. The disclosed method also comprises growing an epitaxial layer within the etching groove; forming a gate insulating layer on the epitaxial layer; depositing a first polysilicon layer on inner sidewalls of the opening and on the gate insulating layer; forming a dielectric layer on the first polysilicon layer; and depositing a second polysilicon layer on the dielectric layer.09-18-2008
20110303964NONVOLATILE MEMORY, METHOD FOR MANUFACTURING SAME, AND DISPLAY DEVICE - Provided is a nonvolatile memory 12-15-2011
257322000 With charging or discharging by control voltage applied to source or drain region (e.g., by avalanche breakdown of drain junction) 3
20090194806SINGLE POLY TYPE EEPROM AND METHOD FOR MANUFACTURING THE EEPROM - Embodiments relate to a single poly type EEPROM and a method for manufacturing an EEPROM. According to embodiments, a single poly type EEPROM may include unit cells. A unit cell may include a floating gate at a side of a control node formed on and/or over a semiconductor substrate having an activation region and a device isolation area, not overlapping a device isolation region but overlapping only a top of the activation region. A select gate may be formed on and/or over a top of the activation region. According to embodiments, a ratio of a capacitance of a control node side to a capacitance of a bit line side may increase, which may improve a coupling ratio. According to embodiments, a junction capacitance may be maximized by not doping the floating gate with an impurity, which may allow for a reduction in chip size by securing design margins.08-06-2009
20080211010Semiconductor device - A semiconductor device includes: a package; two semiconductor chip fixing parts located adjacently to each other in the package; and first and the second semiconductor chips, each of which is fixed on the semiconductor chip fixing part and has a field effect transistor formed therein. A gate lead G09-04-2008
20090101962Semiconductor devices and methods of manufacturing and operating same - A semiconductor device and methods of manufacturing and operating the semiconductor device may be disclosed. The semiconductor device may comprise different nanostructures. The semiconductor device may have a first element formed of nanowires and a second element formed of nanoparticles. The nanowires may be ambipolar carbon nanotubes (CNTs). The first element may be a channel layer. The second element may be a charge trap layer. In this regard, the semiconductor device may be a transistor or a memory device.04-23-2009
257318000 Additional control electrode is doped region in semiconductor substrate 1
20090283814SINGLE-POLY NON-VOLATILE MEMORY CELL - A non-volatile memory cell includes an ion well of a semiconductor substrate; a first half-transistor having a firs select gate, a first diffusion region in the ion well, and a first gate dielectric layer between the first select gate and the ion well; a second half-transistor disposed adjacent to the first half-transistor, wherein the second half-transistor has a second select gate spaced apart from the first select gate, a second diffusion region in the ion well, and a second gate dielectric layer between the second select gate and the ion well. The first and second half-transistors are mirror-symmetrical to each other.11-19-2009
Entries
DocumentTitleDate
20130069136SINGLE-GATE NON-VOLATILE FLASH MEMORY CELL, MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A single-gate non-volatile flash memory cell, a memory device including the memory cell, and a manufacturing method thereof are provided. The memory cell includes a semiconductor structure and a movable switch (03-21-2013
20130069135SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes an interelectrode insulating film formed between a charge storage layer and a control electrode layer. The interelectrode insulating film is formed in a first region above an upper surface of an element isolation insulating film, a second region along a sidewall of the charge storage layer, and a third region above an upper surface of the charge storage layer. The interelectrode insulating film includes a first stack including a first silicon nitride film or a high dielectric constant film interposed between a first and a second silicon oxide film or a second stack including a second high dielectric constant film and a third silicon oxide film, and a second silicon nitride film formed between the control electrode layer and the first or the second stack. The second silicon nitride film is relatively thinner in the third region than in the first region.03-21-2013
20130043522SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME - A method of forming a semiconductor structure is provided. A substrate having a cell area and a periphery area is provided. A stacked structure including a gate oxide layer, a floating gate and a first spacer is formed on the substrate in the cell area and a resistor is formed on the substrate in the periphery area. At least two doped regions are formed in the substrate beside the stacked structure. A dielectric material layer and a conductive material layer are sequentially formed on the substrate. A patterned photoresist layer is formed on the substrate to cover the stacked structure and a portion of the resistor. The dielectric material layer and the conductive material layer not covered by the patterned photoresist layer are removed, so as to form an inter-gate dielectric layer and a control gate on the stacked structure, and simultaneously form a salicide block layer on the resistor.02-21-2013
20090140317Multiple Layer floating gate non-volatile memory device - The disclosed systems and methods relate to floating gate non-volatile memory cells, with a floating gate comprising at least two layers constructed in different conductive or semiconductive materials. At least two of the layers of the floating gate are separated by an intermediate dielectric layer having a predetermined thickness enabling direct tunneling current between the layers06-04-2009
20130026555NONVOLATILE SEMICONDUCTOR MEMORY DEVICE INCLUDING MEMORY CELLS FORMED TO HAVE DOUBLE-LAYERED GATE ELECTRODES - A nonvolatile semiconductor memory device includes a plurality of floating gate electrodes respectively formed above a semiconductor substrate with first insulating films disposed therebetween, and a control gate electrode formed above the plurality of floating gate electrodes with a second insulating film disposed therebetween. In each of the plurality of floating gate electrodes is formed to have a width of an upper portion thereof in a channel width direction which is smaller than a width of a lower portion thereof in the channel width direction and one of contact surfaces thereof on at least opposed sides which contact the second insulating film is formed to have one surface, and the second insulating film has a maximum film thickness in a vertical direction, the maximum film thickness being set smaller than a distance from a lowest surface to a highest surface of the second insulating film in the vertical direction.01-31-2013
20130026552SPLIT-GATE FLASH MEMORY EXHIBITING REDUCED INTERFERENCE - A split gate memory cell is fabricated with a dielectric spacer comprising a high-k material between the word gate and the memory gate stack. Embodiments include memory cells with a dielectric spacer comprising low-k and high-k layers. Other embodiments include memory cells with an air gap between the word gate and the memory gate stack.01-31-2013
20130026554NAND TYPE FLASH MEMORY FOR INCREASING DATA READ/WRITE RELIABILITY - A NAND type flash memory for increasing data read/write reliability includes a semiconductor substrate unit, a base unit, and a plurality of data storage units. The semiconductor substrate unit includes a semiconductor substrate. The base unit includes a first dielectric layer formed on the semiconductor substrate. The data storage units are adjacent to each other and formed on the first dielectric layer. Each data storage unit includes at least two floating gates formed on the first dielectric layer, a second dielectric layer formed on the first dielectric layer and between the two floating gates, an inter-gate dielectric layer formed on the two floating gates and the second dielectric layer, at least one control gate formed on the inter-gate dielectric layer, and a third dielectric layer formed on the first dielectric layer and surrounding and tightly connecting with the two floating gates, the inter-gate dielectric layer, and the control gate.01-31-2013
20130026553NVM Bitcell with a Replacement Control Gate and Additional Floating Gate - Embodiments relate to a nonvolatile memory (“NVM”) bitcell with a replacement metal control gate and an additional floating gate. The bitcell may be created using a standard complementary metal-oxide-semiconductor manufacturing processes (“CMOS processes”) without any additional process steps, thereby reducing the cost and time associated with fabricating a semiconductor device incorporating the NVM bitcell.01-31-2013
20090212342Asymmetric Single Poly NMOS Non-Volatile Memory Cell - An asymmetric non-volatile memory (NVM) cell for a CMOS IC formed by a standard CMOS process flow used to form both low voltage and high voltage transistors on a substrate. The NVM cell includes an NMOS floating gate transistor and an optional select transistor. The floating gate transistor includes an elongated floating gate having a first portion disposed over the channel region C08-27-2009
20100155809SEMICONDUCTOR DEVICE OF COMMON SOURCE STRUCTURE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE OF COMMON SOURCE STRUCTURE - A semiconductor device having a common source structure and method of manufacturing the same are provided. In one embodiment, the method includes: forming a plurality of gate lines on a semiconductor substrate, each constituted by a floating gate, a dielectric layer, and a control gate having a line form; forming a first dielectric layer on the semiconductor substrate including the gate line; forming a trench having the line form in the first dielectric layer, wherein the trench exposes the semiconductor substrate between the gate lines; and forming a common source in the trench. According to an embodiment, the common source is implemented as a poly line in the trench. Therefore, etching the substrate to provide a trench for a common source can be excluded. Accordingly, it is possible to inhibit the common source from being opened due to a remaining material in a trench, and reduce damage to the semiconductor substrate.06-24-2010
20100090266SEMICONDUCTOR DEVICE HAVING CONTROLLABLE TRANSISTOR THRESHOLD VOLTAGE - A semiconductor device of this invention is a single-layer gate nonvolatile semiconductor memory in which a floating gate having a predetermined shape is formed on a semiconductor substrate. This floating gate opposes a diffusion layer serving as a control gate via a gate oxide film and is capacitively coupled with the diffusion layer by using the gate oxide film as a dielectric film. The diffusion layer immediately below the dielectric film is insulated from the semiconductor substrate by an insulating film such as a silicon oxide film. A pair of diffusion layers are formed in surface regions of the semiconductor substrate on the two sides of the floating gate extending on a tunnel oxide film. This invention can realize a reliable semiconductor device which is a single-layer gate semiconductor device by which a low-cost process is possible, has a control gate which can well withstand a high voltage applied when data is erased or written, and can prevent an operation error by minimizing variations in the threshold value.04-15-2010
20100052034FLASH MEMORY GATE STRUCTURE FOR WIDENED LITHOGRAPHY WINDOW - A first portion of a semiconductor substrate belonging to a flash memory device region is recessed to a recess depth to form a recessed region, while a second portion of the semiconductor substrate belonging to a logic device region is protected with a masking layer. A first gate dielectric layer and a first gate conductor layer formed within the recessed region such that the first gate conductive layer is substantially coplanar with the top surfaces of the shallow trench isolation structures. A second gate dielectric layer, a second gate conductor layer, and a gate cap hard mask layer, each having a planar top surface, is subsequently patterned. The pattern of the gate structure in the flash memory device region is transferred into the first gate conductor layer and the first gate dielectric layer to form a floating gate and a first gate dielectric, respectively.03-04-2010
20120168843SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device includes a bit line formed over a substrate, an insulation layer formed over the bit line, a gate line crossing the bit line and formed over the insulation layer, and a channel layer formed on both sidewalls of the gate line and coupled to the bit line.07-05-2012
20110186921NONVOLATILE SEMICONDUCTOR MEMORY DEVICE HAVING ELEMENT ISOLATING REGION OF TRENCH TYPE - Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, the element isolating region isolating a element region and being self-aligned with the first electrode layer, a second insulating film formed on the first electrode layer and the element isolating region, an open portion exposing a surface of the first electrode layer being formed in the second insulating film, and a second electrode layer formed on the second insulating film and the exposed surface of the first electrode layer, the second electrode layer being electronically connected to the first electrode layer via the open portion.08-04-2011
20110186920SEMICONDUCTOR DEVICE WITH GATE STACK STRUCTURE - A semiconductor device includes a first conductive layer, a first intermediate structure over the first conductive layer, a second intermediate structure over the first intermediate structure, and a second conductive layer over the second intermediate structure. The first intermediate structure includes a metal silicide layer and a nitrogen containing metal layer. The second intermediate structure includes at least a nitrogen containing metal silicide layer.08-04-2011
20080258202NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device includes a semiconductor substrate having a first trench, an element isolation insulating film, a floating gate electrode, a second gate insulating film and a control gate electrode. The element isolation insulating film includes a sidewall having such a height as to be in contact with the floating gate electrode. The floating gate electrode includes a sidewall further including a lower portion opposed to the control gate electrode with the element isolation insulating film and the second gate insulating film being interposed between them. The control gate electrode is buried in the second trench with the second gate insulating film being interposed between them.10-23-2008
20080258200Memory cell having a shared programming gate - A semiconductor memory device includes a substrate, and a trench formed in the substrate. First and second floating gates, each associated with corresponding first and second memory cells, extend into the trench. Since the trench can be made relatively deep, the floating gates may be made relatively large while the lateral dimensions of the floating gates remains small. Moreover, the insulator thickness between the floating gate and a sidewall of the trench where a channel region is formed can be made relatively thick, even though the lateral extent of the memory cell is reduced. A programming gate extends into the trench between the first and second floating gates, and is shared, along with a source region, by the two memory cells.10-23-2008
20080258199FLASH MEMORY DEVICE AND FABRICATING METHOD THEREOF - The present invention relates to a flash memory device and its fabrication method, in more detail, it relates to a novel device structure for improving a scaling-down characteristic/performance and increasing memory capacity of the MOS-based flash memory device.10-23-2008
20110193152HIGH-VOLTAGE TRANSISTOR HAVING SHIELDING GATE - A semiconductor device includes a plurality of high-voltage insulated-gate field-effect transistors arranged in a matrix form on the main surface of a semiconductor substrate and each having a gate electrode, a gate electrode contact formed on the gate electrode, and a wiring layer which is formed on the gate electrode contacts adjacent in a gate-width direction to electrically connect the gate electrodes arranged in the gate-width direction. And the device includes shielding gates provided on portions of an element isolation region which lie between the transistors adjacent in the gate-width direction and gate-length direction and used to apply reference potential or potential of a polarity different from that of potential applied to the gate of the transistor to turn on the current path of the transistor to the element isolation region.08-11-2011
20110193151NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a nonvolatile semiconductor memory device includes a semiconductor substrate including a first region in which a memory cell transistor is arranged, a second region in which an electrode that extracts a word line electrically connected to the memory cell transistor is arranged, and a third region in which a peripheral transistor is arranged, the semiconductor substrate including an element isolation layer which separates adjacent active regions, first active regions provided in the first region and each having a first width, second active regions provided in the second region and each having a second width greater than the first width, third active regions provided in the third region and each having a third with greater than the first width. An upper surface of an element isolation layer in the second region is higher than that of an element isolation layer in the first region.08-11-2011
20100163957NONVOLATILE SEMICONDUCTOR MEMORY DEVICE INCLUDING MEMORY CELLS FORMED TO HAVE DOUBLE-LAYERED GATE ELECTRODES - A nonvolatile semiconductor memory device includes a plurality of floating gate electrodes respectively formed above a semiconductor substrate with first insulating films disposed therebetween, and a control gate electrode formed above the plurality of floating gate electrodes with a second insulating film disposed therebetween. In each of the plurality of floating gate electrodes is formed to have a width of an upper portion thereof in a channel width direction which is smaller than a width of a lower portion thereof in the channel width direction and one of contact surfaces thereof on at least opposed sides which contact the second insulating film is formed to have one surface, and the second insulating film has a maximum film thickness in a vertical direction, the maximum film thickness being set smaller than a distance from a lowest surface to a highest surface of the second insulating film in the vertical direction.07-01-2010
20130037877DOUBLE GATED FLASH MEMORY - A split gate memory cell is fabricated with a fin structure between a memory gate stack and a select gate. Embodiments include a first channel region under the memory gate stack and a second channel region under the select gate.02-14-2013
20100072534NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A nonvolatile semiconductor memory device includes a gate insulating film formed on a semiconductor substrate, a first gate electrode corresponding to a memory cell transistor and a second gate electrode. The first gate electrode includes a floating gate electrode film, a first interelectrode insulating film and a control gate electrode film. The floating gate electrode film has a polycrystalline silicon film and the control gate electrode film having a silicide film. The second gate electrode includes a lower electrode film, a second interelectrode insulating film and an upper electrode film. The second interelectrode insulating film includes an opening. The lower electrode film includes a void below the opening of the second interelectrode insulating film. The upper electrode film includes a silicide film. The lower electrode film includes a polycrystalline silicon film and a silicide film which is located between the opening and the void.03-25-2010
20100032744Reduced Area Single Poly EEPROM - A single poly EEPROM cell in which the read transistor is integrated in either the control gate well or the erase gate well. The lateral separation of the control gate well from erase gate well may be reduced to the width of depletion regions encountered during program and erase operations. A method of forming a single poly EEPROM cell where the read transistor is integrated in either the control gate well or the erase gate well.02-11-2010
20080290395SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of realizing a flash floating poly gate using an MPS process can include forming a tunnel oxide layer on an active region of a semiconductor substrate; and then forming a first floating gate on and contacting the tunnel oxide layer; and then forming second and third floating gates on and contacting the first floating gate, wherein the second and third floating gates extend perpendicular to the first floating gate; and then forming a poly meta-stable polysilicon layer on the first, second and third floating gates; and then forming a control gate on the semiconductor substrate including the poly meta-stable polysilicon layer. Therefore, it is possible to increase the surface area of the capacitor by a limited area in comparison with a flat floating gate. As a result, it is possible to improve the coupling ratio essential to the flash memory device and to improve the yield and reliability of the semiconductor device.11-27-2008
20100096683Structure of semiconductor device - A structure of a semiconductor device including a substrate and a patterned layer is provided. The patterned layer being patterned to have an open area and a dense area is disposed on the substrate. The patterned layer includes, in the dense area, a first pattern adjacent to the open area and a second pattern. The first pattern has a first bottom. The second pattern has a second bottom width. The bottom of the first pattern includes a recess facing the open area, so that the first bottom width is close to the second bottom width.04-22-2010
20080203462Finfet-Based Non-Volatile Memory Device - A non-volatile memory device on a substrate layer (08-28-2008
20090159953METHOD FOR MANUFACTURING FLASH MEMORY DEVICE - Embodiments relate to a flash memory device and a method for manufacturing a flash memory device. According to embodiments, a method may include forming a gate on and/or over a semiconductor substrate on and/or over which a device isolation film may be formed, forming a first spacer including a first oxide pattern and a first nitride pattern on and/or over side walls of the gate, forming a source and drain area on and/or over the semiconductor substrate using the gate and spacer as masks, removing the first nitride pattern of the first spacer, and forming a second spacer including a second oxide film pattern and a second nitride film pattern on and/or over the side walls of the gate by performing an annealing process on and/or over the semiconductor substrate on and/or over which the first oxide film pattern is formed.06-25-2009
20090212343NON-VOLATILE TWO-TRANSISTOR PROGRAMMABLE LOGIC CELL AND ARRAY LAYOUT - A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.08-27-2009
20100109068Lanthanide dielectric with controlled interfaces - Methods and devices for a dielectric are provided. One method embodiment includes forming a passivation layer on a substrate, wherein the passivation layer contains a composition of silicon, oxygen, and nitrogen. The method also includes forming a lanthanide dielectric film on the passivation layer, and forming an encapsulation layer on the lanthanide dielectric film.05-06-2010
20100109067SiH4 soak for low hydrogen SiN deposition to improve flash memory device performance - Prior to deposition of a silicon nitride (SiN) layer on a structure, a non-plasma enhanced operation is undertaken wherein the structure is exposed to silane (SiH05-06-2010
20110309424STRUCTURE OF MEMORY DEVICE AND PROCESS FOR FABRICTING THE SAME - A structure of a memory cell of a static random memory device and a process for fabricating the same are disclosed. The memory cell includes a substrate having an active region including an N-well and a shallow trench isolation structure; a first gate and a second gate formed over the substrate; a halo region, a LLD, and a source and drain region formed on two sides of the first gate; an interlevel dielectric layer covering the substrate, the first and second gates; and a contact penetrating the interlevel dielectric layer and extending to the source and drain region, no halo region is formed under the contact.12-22-2011
20090146203NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - In one aspect of the present invention, a nonvolatile semiconductor memory device may include a semiconductor substrate; a plurality of tunnel insulating films formed on the semiconductor substrate at predetermined intervals in a first direction; a plurality of floating gate electrodes each having a first portion and a second portion, the first portions being formed on the respective tunnel insulating films, the second portions being formed on the respective first portions and having smaller width than the first portions in the first direction; an inter-gate insulating film formed on the floating gate electrodes; and first and second control gate electrodes respectively formed on sidewalls, in the first direction, of the second portion of each of the plurality of floating gate electrodes with the inter-gate insulating film interposed therebetween.06-11-2009
20130082317SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY ELEMENT - A semiconductor memory element for writing by a drain-avalanche hot electron includes a MOS transistor having a first semiconductor layer of a second conductivity type formed on a semiconductor substrate of a first conductivity type; a floating gate provided on the first semiconductor layer through intermediation of an insulating film; a channel region formed in a surface of the first semiconductor layer under the floating gate; and a source region and a drain region of the first conductivity type provided on the first semiconductor layer so as to be in contact with the channel region in which the channel region has a distribution of at least two kinds of carrier densities.04-04-2013
20120181598NONVOLATILE SEMICONDUCTOR MEMORY - A nonvolatile semiconductor memory includes first and second memory cells having a floating gate and a control gate. The floating gate of the first and second memory cells is comprised a first part, and a second part arranged on the first part, and a width of the second part in an extending direction of the control gate is narrower than that of the first part. A first space between the first parts of the first and second memory cells is filled with one kind of an insulator. The control gate is arranged at a second space between the second parts of the first and second memory cells.07-19-2012
20120181597SEMICONDUCTOR MEMORY DEVICE - To provide a semiconductor memory device having a floating gate which operates with a short channel. A high-work-function compound semiconductor having a work function of greater than or equal to 5.5 eV, such as indium nitride or zinc nitride, is used for the floating gate. Accordingly, the potential barrier of the floating gate insulating film between the substrate and the floating gate is higher than that of a conventional one, so that leakage of electric charge due to a tunnel effect can be reduced even if the thickness of the floating gate insulating film is made small. Since the thickness of the floating gate insulating film can be made small, the channel can be further shortened.07-19-2012
20120181596STRINGS OF MEMORY CELLS HAVING STRING SELECT GATES, MEMORY DEVICES INCORPORATING SUCH STRINGS, AND METHODS OF ACCESSING AND FORMING THE SAME - Strings of memory cells having a string select gate configured to selectively couple ends of a string to a data line and a source line concurrently, memory devices incorporating such strings and methods for accessing and forming such strings are provided. For example, non-volatile memory devices are disclosed that utilize vertical structure NAND strings of serially-connected non-volatile memory cells. One such string including two or more serially-connected non-volatile memory cells where each end of the string shares a string select gate with the other end of the string is disclosed.07-19-2012
20120181595NON-VOLATILE MEMORY CELL STRUCTURE AND A METHOD OF FABRICATING THE SAME - A non-volatile memory cell structure and a method of fabricating the same. The method comprising the steps of: fabricating a portion of a floating gate from one or more first metal local interconnection layer (LIL) slit contacts deposited on a patterned dielectric layer; and fabricating a portion of a control gate from one or more second metal LIL slit contacts deposited on the patterned dielectric layer; wherein the first and second metal LIL slit contacts form a capacitive structure between the floating gate and the control gate.07-19-2012
20120181594EEPROM CELL STRUCTURE AND A METHOD OF FABRICATING THE SAME - An electrically erasable programmable read only memory (EEPROM) cell structure and a method of fabricating the same. The EEPROM cell comprising a substrate comprising two shallow trench isolation (STI) structures separated by a substrate portion; an intermediate patterned layer formed on the substrate such that the patterned layer covers respective portions of each STI structure; a floating gate bridging between the STI structures such that the floating gate extends over the intermediate patterned layer; a dielectric layer formed over the floating gate; and a control gate formed over the dielectric layer.07-19-2012
20090045451Semiconductor device and method of manufacturing the same - A method of manufacturing a semiconductor device that comprises the steps of: removing a second insulating film on a contact region of a first conductor; forming a second conductive film on the second insulating film; removing the second conductive film on the contact region of the first conductor to make the second conductive film into a second conductor; forming an interlayer insulating film (a third insulating film) covering the second conductor; forming a first hole in the interlayer insulating film on the contact region; and forming a conductive plug, which is electrically connected with the contact region, in the first hole.02-19-2009
20100133600Semiconductor devices having increased sensing margin - One transistor (1-T) dynamic random access memories (DRAM) having improved sensing margins that are relatively independent of the amount of carriers stored in a body region thereof.06-03-2010
20100133601SEMICONDUCTOR DEVICE - A semiconductor device is provided, which comprises at least a cell including a plurality of memory elements connected in series. Each of the plurality of memory elements includes a channel formation region, a source and drain regions, a floating gate, and a control gate. Each of the source and drain regions is electrically connected to an erasing line through a semiconductor impurity region.06-03-2010
20090026524Stacked Circuits - An integrated circuit includes a first integrated circuit layer including at least one first transistor channel region and having a wafer bonding interface. The integrated circuit may further include at least one second integrated circuit layer including at least one second transistor channel region and being arranged at the wafer bonding interface of the first integrated circuit layer.01-29-2009
20090302367METHOD OF FABRICATING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE FABRICATED BY THE METHOD - A method of fabricating a semiconductor device includes forming a first polycrystalline silicon layer on a gate insulating film so that a vertically intermediate portion has a higher dopant concentration than vertically upper and lower portions, forming a second polycrystalline silicon layer on an intergate insulating film so that a vertically intermediate portion has a higher dopant concentration than vertically upper and lower portions, executing a thermal oxidation treatment for the polycrystalline silicon layers with side surfaces of gate electrodes being exposed, thereby forming a silicon oxide film, selectively removing the silicon oxide film by an etch with use of a chemical solution, thereby forming recesses in side surfaces of the first and second polycrystalline silicon layers respectively, and burying insulating films between the gate electrodes respectively and forming air gaps in portions of the buried insulating films corresponding to the recesses respectively.12-10-2009
20120217566NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - An object is to suppress reading error even in the case where writing and erasing are repeatedly performed. Further, another object is to reduce writing voltage and erasing voltage while increase in the area of a memory transistor is suppressed. A floating gate and a control gate are provided with an insulating film interposed therebetween over a first semiconductor layer for writing operation and erasing operation and a second semiconductor layer for reading operation which are provided over a substrate; injection and release of electrons to and from the floating gate are performed using the first semiconductor layer; and reading is performed using the second semiconductor layer.08-30-2012
20130056816NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a nonvolatile semiconductor memory device includes: a substrate; a memory unit provided on the substrate; and a non-memory unit provided on the substrate. The memory unit includes: a first stacked body including a plurality of first electrode films and a first inter-electrode insulating film, the plurality of first electrode films being stacked along a first axis perpendicular to the major surface, the first inter-electrode insulating film being provided between two of the first electrode films mutually adjacent along the first axis; a first semiconductor layer opposing side surfaces of the first electrode films; a first memory film provided between the first semiconductor layer and the first electrode films; and a first conductive film provided on the first stacked body apart from the first stacked body. The non-memory unit includes a resistance element unit of the same layer as the conductive film.03-07-2013
20130161720EEPROM CELL - A method of forming a device is disclosed. The method includes providing a substrate prepared with a cell area and forming first and second gates of first and second transistors in the cell area. The first gate includes a second sub-gate surrounding a first sub-gate. The first and second sub-gates of the first gate are separated by a first intergate dielectric layer. The second gate includes a second sub-gate surrounding a first sub-gate. The first and second sub-gates of the second gate are separated by a second intergate dielectric layer. The method also includes forming first and second junctions of the first and second transistors. A first gate terminal is formed and coupled to the second sub-gate of the first transistor. A second gate terminal is formed and coupled to at least the first sub-gate of the second transistor.06-27-2013
20120112263SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate, a first insulating film formed on the semiconductor substrate, a charge storage layer formed on the first insulating film, a second insulating film formed on the charge storage layer, and a control electrode formed on the second insulating film, the second insulating film including a lower silicon nitride film, a lower silicon oxide film formed on the lower silicon nitride film, an intermediate insulating film formed on the lower silicon oxide film and containing a metal element, the intermediate insulating film having a relative dielectric constant of greater than 7, an upper silicon oxide film formed on the intermediate insulating film, and an upper silicon nitride film formed on the upper silicon oxide film.05-10-2012
20120112262Method for producing a floating gate memory structure - Disclosed are methods for manufacturing floating gate memory devices and the floating gate memory devices thus manufactured. In one embodiment, the method comprises providing a monocrystalline semiconductor substrate, forming a tunnel oxide layer on the substrate, and depositing a protective layer on the tunnel oxide layer to form a stack of the tunnel oxide layer and the protective layer. The method further includes forming at least one opening in the stack, thereby exposing at least one portion of the substrate, and cleaning the at least one exposed portion with a cleaning liquid. The method still further includes loading the substrate comprising the stack into a reactor and, thereafter, performing an in-situ etch to remove the protective layer, using the at least one exposed portion as a source to epitaxially grow a layer comprising the monocrystalline semiconductor material, and forming the layer into at least one columnar floating gate structure.05-10-2012
20120112261FLASH MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - The present invention provides a FinFET flash memory device and the method for manufacturing the same. The flash memory device is on an insulating layer, comprising: a first fin and a second fin, wherein the second fin is a control gate of the device; a gate dielectric layer, at side walls and top of the first fin and the second fin; source/drain regions, inside the first fin at both sides of a floating gate.05-10-2012
20090294826Semiconductor Device and Method of Fabricating the Same - Provided are semiconductor devices and methods of fabricating the same. The semiconductor device comprises: a floating gate pattern formed in a cell area of a semiconductor substrate; a dummy floating gate pattern extending from the floating gate pattern into an interface area around the cell area; and a control gate pattern intersecting the floating gate pattern at the cell area of the semiconductor substrate.12-03-2009
20090283812NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - An object is to suppress reading error even in the case where writing and erasing are repeatedly performed. Further, another object is to reduce writing voltage and erasing voltage while increase in the area of a memory transistor is suppressed. A floating gate and a control gate are provided with an insulating film interposed therebetween over a first semiconductor layer for writing operation and erasing operation and a second semiconductor layer for reading operation which are provided over a substrate; injection and release of electrons to and from the floating gate are performed using the first semiconductor layer; and reading is performed using the second semiconductor layer.11-19-2009
20090267131NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - To reduce capacitance between each adjacent two word lines in a semiconductor memory device, a first insulating film is formed, with a first gate insulating film thereunder, in an interstice between gates respectively of each adjacent two memory transistors, and in an interstice between a gate of a selective transistor and a gate of a memory transistor adjacent thereto. Additionally, a second insulating film is formed on the first insulating film, sides of the gate of each memory transistor, and a side, facing the memory transistor, of the gate of the selective transistor. A third insulating film is formed parallel to a semiconductor substrate so as to cover a metal silicide film, the first and second insulating films and fourth and fifth insulating films. A void part is provided in the interstice between each adjacent two gates of the memory transistors, and in the interstice between the gate of the selective transistor and the gate of the memory transistor adjacent thereto. A bottom and two sides of each void part are shielded by the second insulating film, and a top of each void part is shielded by the third insulating film.10-29-2009
20130062680SEMICONDUCTOR MEMORY AND MANUFACTURING METHOD OF THE SAME - According to one embodiment, a semiconductor memory includes a memory cell in a memory cell array which is provided in a semiconductor substrate and which includes a first active region surrounded by a first isolation insulator, a transistor in a transistor region which is provided in the semiconductor substrate and which includes second active regions surrounded by a second isolation insulator. The second isolation insulator includes a first film, and a second film between the first film and the second active region, and the upper surface of the first film is located closer to the bottom of the semiconductor substrate than the upper surface of the second film.03-14-2013
20110012186ISOLATION TRENCHES FOR MEMORY DEVICES - A first dielectric plug is formed in a portion of a trench that extends into a substrate of a memory device so that an upper surface of the first dielectric plug is recessed below an upper surface of the substrate. The first dielectric plug has a layer of a first dielectric material and a layer of a second dielectric material formed on the layer of the first dielectric material. A second dielectric plug of a third dielectric material is formed on the upper surface of the first dielectric plug.01-20-2011
20110012185SEMICONDUCTOR MEMORY DEVICE AND WRITE METHOD OF THE SAME - A write and erase method of a semiconductor memory device includes a floating gate type transistor having a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a floating gate electrode formed on the gate insulating film, and a control gate electrode opposing the floating gate electrode with a hollow portion being sandwiched therebetween. A capacitance between the semiconductor substrate and the control gate electrode is controlled by one of an operation of forming, in the hollow portion, an electrical path which electrically connects the floating gate electrode and the control gate electrode, and an operation of eliminating the electrical path.01-20-2011
20110037116SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The method of manufacturing a semiconductor device, including a first region where a transistor including a gate electrode of a stacked structure is formed, a second region where a transistor including a gate electrode of a single-layer structure is formed, and a third region positioned in a boundary part between the first region and the second region, includes: depositing a first conductive film, patterning the first conductive film in the first region and the third region so that the outer edge is positioned in the third region, depositing the second conductive film, patterning the second conductive film to form a control gate in the first region while leaving the second conductive film, covering the second region and having the inner edge positioned inner of the outer edge of the first conductive film, and patterning the second conductive film in the second region to form the gate electrode.02-17-2011
20110037114SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device is formed to include: a substrate; a floating gate formed on the substrate via a gate insulating film; a control gate formed on an adjacent position to the floating gate via a tunnel insulating film; a spacer insulating film formed on the floating gate; and a protection film formed between the spacer insulating film and the control gate. In such a semiconductor memory device (MC), the protection film functions as a stopper of a side surface of the spacer insulating film when a part other than the spacer insulating film is etched.02-17-2011
20130161719Integrated Nanostructure-Based Non-Volatile Memory Fabrication - Nanostructure-based charge storage regions are included in non-volatile memory devices and integrated with the fabrication of select gates and peripheral circuitry. One or more nanostructure coatings are applied over a substrate at a memory array area and a peripheral circuitry area. Various processes for removing the nanostructure coating from undesired areas of the substrate, such as target areas for select gates and peripheral transistors, are provided. One or more nanostructure coatings are formed using self-assembly based processes to selectively form nanostructures over active areas of the substrate in one example. Self-assembly permits the formation of discrete lines of nanostructures that are electrically isolated from one another without requiring patterning or etching of the nanostructure coating.06-27-2013
20090236652SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device according to an embodiment of the present invention includes a resistance element which is constructed with a first conductor which extends in a first direction and is connected to a first contact; a second conductor which extends in said first direction and is connected to a second contact; and a first insulation film which exists between said first conductor and said second conductor, said first insulation film also having an opening in which a third conductor which connects said first conductor and said second conductor is arranged.09-24-2009
20090026526INTEGRATED CIRCUIT DEVICES INCLUDING A MULTI-LAYER STRUCTURE WITH A CONTACT EXTENDING THERETHROUGH AND METHODS OF FORMING THE SAME - Integrated circuit devices have a first substrate layer and a first transistor on the first substrate layer. A first interlayer insulating film covers the first transistor. A second substrate layer is on the first interlayer insulating film and a second transistor is on the second substrate layer. A second interlayer insulating film covers the second transistor. A contact extends through the second interlayer insulating film, the second substrate layer and the first interlayer insulating film. The contact includes a lower contact and an upper contact that contacts an upper surface of the lower contact to define an interface therebetween. The interface is located at a height no greater than a height of a top surface of the second substrate and greater than a height of a bottom surface of the second substrate layer.01-29-2009
20090026523PARTIALLY GATED FINFET - A gate dielectric and a gate conductor layer are formed on sidewalls of at least one semiconductor fin. The gate conductor layer is patterned so that a gate electrode is formed on a first sidewall of a portion of the semiconductor fin, while a second sidewall on the opposite side of the first sidewall is not controlled by the gate electrode. A partially gated finFET, that is, a finFET with a gate electrode on the first sidewall and without a gate electrode on the second sidewall is thus formed. Conventional dual gate finFETs may be formed with the inventive partially gated finFETs on the same substrate to provide multiple finFETs having different on-current in the same circuit such as an SRAM circuit.01-29-2009
20130161721EEPROM CELL - A method of forming a device is disclosed. The method includes providing a substrate prepared with a cell area separated by other active areas by isolation regions. First and second gates of first and second transistors in the cell area are formed. The first gate includes first and second sub-gates separated by a first intergate dielectric layer. The second gate includes a second sub-gate surrounding a first sub-gate. The first and second sub-gates of the second gate are separated by a second intergate dielectric layer. First and second junctions of the first and second transistors are formed. The method also includes forming a first gate terminal coupled to the second sub-gate of the first transistor and a second gate terminal coupled to at least the first sub-gate of the second transistor.06-27-2013
20080315283SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes a semiconductor substrate having a plurality of element regions and a plurality of element isolation regions in a first direction, a plurality of floating gate electrodes formed via a gate insulating film on the respective element regions, an intergate insulating film formed on the floating gate electrodes, a plurality of control gate electrodes formed on the intergate insulating film so as to extend over the adjacent floating gate electrodes, and an element isolation insulating film formed in the element isolation region and having an upper end located higher than the upper surface of the gate insulating film, the element isolation insulating film including a part formed between the control gate electrodes so that the central sidewall of the element isolation insulating film is located lower than the end of the sidewall of the element isolation insulating film.12-25-2008
20110031546METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND APPARATUS FOR MANUFACTURING SAME - A method for manufacturing a semiconductor device includes: forming a first layer on a substrate; forming a first contact hole in the first layer; burying a sacrificial film in the first contact hole; forming a second layer on the first layer and the first contact hole after burying; forming a second contact hole reaching the sacrificial film in the second layer; removing the sacrificial film from the first contact hole via the second contact hole; and providing a contact electrode in the first contact hole and the second contact hole.02-10-2011
20100006916NON-VOLATILE MEMORY - Non-volatile memory is described. The non-volatile memory includes a substrate having a source region, a drain region and a channel region. The channel region separates the source region and the drain region. An electrically insulating layer is adjacent to the source region, drain region and channel region. A floating gate electrode is adjacent to the electrically insulating layer. The electrically insulating layer separates the floating gate electrode from the channel region. The floating gate electrode has a floating gate major surface. A control gate electrode has a control gate major surface and the control gate major surface opposes the floating gate major surface. A vacuum layer or gas layer at least partially separates the control gate major surface from the floating gate major surface.01-14-2010
20090127613NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A nonvolatile semiconductor memory device comprises a memory cell array of plural memory cells arranged in matrix. Each memory cell includes a first gate insulator layer formed on a semiconductor substrate, a floating gate formed on the semiconductor substrate with the first gate insulator layer interposed therebetween, a second gate insulator layer formed on the floating gate, and a control gate formed on the floating gate with the second gate insulator layer interposed therebetween. The first gate insulator layer is a first cavity layer.05-21-2009
20110278658NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A non-volatile semiconductor memory device comprises a plurality of memory cells, each including a semiconductor substrate, a first insulating film formed on the semiconductor substrate, a floating gate formed on the semiconductor substrate with the inclusion of the first insulating film, a second insulating film formed on the floating gate, and a control gate formed on the floating gate with the inclusion of the second insulating film; an element isolation insulating film formed in the semiconductor substrate and extending in a gate-length direction to isolate between memory cells adjoining in a gate-width direction; and an air gap formed on the element isolation insulating film and between floating gates adjoining in the gate-width direction.11-17-2011
20110278657APPARATUS, SYSTEM, AND METHOD FOR CAPACITANCE CHANGE NON-VOLATILE MEMORY DEVICE - An apparatus, system, and method for a capacitance change non-volatile memory device. The apparatus may include a substrate, a source region in the substrate, a drain region in the substrate, a tunnel oxide layer on the substrate substantially between the source region and the drain region, a floating gate layer on the tunnel oxide layer, a resistance changing material layer on the floating gate layer, and a control gate on the resistance changing material layer.11-17-2011
20080230826Construction of flash memory chips and circuits from ordered nanoparticles - Methods, apparatus and systems form memory structures, such as flash memory structures from nanoparticles by providing a source of nanoparticles as a conductive layer. The particles are moved by application of a field, such as an electrical field, magnetic field and even electromagnetic radiation. The nanoparticles are deposited onto an insulating surface over a transistor in a first distribution of the nanoparticles. A field is applied to the nanoparticles on the surface that applies a force to the particles, rearranging the nanoparticles on the surface by the force from the field to form a second distribution of nanoparticles on the surface. A protective and enclosing insulating layer is deposited on the nanoparticle second distribution. The addition of a top conductive layer completes a basic flash memory structure.09-25-2008
20080237684Method of manufacturing a nanowire transistor, a nanowire transistor structure, a nanowire transistor field - A method of manufacturing a nanowire transistor includes oxidizing at least a portion of a semiconductor carrier. The semiconductor carrier includes a first carrier portion and a second carrier portion above the first carrier portion. A portion of the oxidized portion is removed, thereby forming an oxide spacer between a portion of the second carrier portion and the first carrier portion. A gate region is formed above at least a portion of the second carrier portion, and a first source/drain region and a second source/drain region are formed.10-02-2008
20090020801TWO-BIT FLASH MEMORY CELL STRUCTURE AND METHOD OF MAKING THE SAME - A flash memory cell includes a control gate oxide layer on a substrate, a T-shaped control gate on the control gate oxide layer, a floating gate disposed on two recessed sidewalls of the T-shaped control gate, an insulating layer between the control gate and the floating gate, a dielectric layer between the floating gate and the substrate, a spacer on the sidewall of the floating gate, a P01-22-2009
20110298032ARRAY ARCHITECTURE FOR EMBEDDED FLASH MEMORY DEVICES - A method for manufacturing Flash memory devices includes forming a well region in a substrate, depositing a gate dielectric layer overlying the well region, and depositing a first polysilicon layer overlying the gate dielectric layer. The method also includes depositing a dielectric layer overlying the first polysilicon layer and depositing a second polysilicon layer overlying the dielectric layer to form a stack layer. The method simultaneously patterns the stack layer to form a first flash memory cell, which includes a first portion of the second polysilicon layer overlying a first portion of the dielectric layer overlying a first portion of first polysilicon layer and to form a select device, which includes a second portion of second polysilicon layer overlying a second portion of dielectric layer overlying a second portion of first polysilicon layer. The method further includes forming source/drain regions using ion implant. The select device is activated by applying voltage to the second portion of first polysilicon layer.12-08-2011
20110298034MEMORY CELL - A non-volatile memory cell (12-08-2011
20110298033SEMICONDUCTOR STORAGE DEVICE - According to one embodiment, a semiconductor storage device includes a charge storage layer, a control gate. The charge storage layer is formed above a semiconductor substrate with first insulating film disposed therebetween. The control gate is formed above the charge storage layer with second insulating film disposed therebetween. The control gate includes a nickel silicide region. The side surface expands outwardly in at least a partial region thereof, and height of the control gate from a portion at which the side surface thereof starts to expand outwardly to a top of the control gate is greater than maximum width of the control gate in a region above the portion at which the side surface starts to expand outwardly.12-08-2011
20100001334ATOMIC LAYER DEPOSITION EPITAXIAL SILICON GROWTH FOR TFT FLASH MEMORY CELL - A method of growing an epitaxial silicon layer is provided. The method comprising providing a substrate including an oxygen-terminated silicon surface and forming a first hydrogen-terminated silicon surface on the oxygen-terminated silicon surface. Additionally, the method includes forming a second hydrogen-terminated silicon surface on the first hydrogen-terminated silicon surface through atomic-layer deposition (ALD) epitaxy from SiH01-07-2010
20100171166NON-VOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A non-volatile memory device and a method of fabricating the same are provided. The method can include disposing an isolation layer on a semiconductor substrate. The isolation layer may protrude from the main surface of the semiconductor substrate and define an active region. In a recess defined by the protrusion of the isolation layer and the active region, a diffusion-retarding poly pattern and a floating gate may be formed in sequence. A control gate may be disposed on the isolation layer to cover the diffusion-retarding poly pattern and the floating gate.07-08-2010
20100171167Gated Semiconductor Device and Method of Fabricating Same - A method for fabricating a gated semiconductor device, and the device resulting from performing the method. In a preferred embodiment, the method includes forming a hard mask for use in gate formation on one or more layers of alternately insulating and conducting material that have been formed on a substrate. The hard mask preferably includes three layers; a lower nitride layer, a middle oxide, and an upper nitride layer. In this embodiment, the middle oxide layer is formed with the rest of the hard mask, and then reduced in a lateral dimension, preferably using a DHF dip. A dielectric layer formed over the gate structure, including the hard mask, then etched back, self-aligns to be reduced-dimension oxide layer. In addition, where two conducting, that is gate layers are present, the lower layer is laterally reduced in dimension on at least one side to create an undercut.07-08-2010
20100171165NON-VOLATILE MEMORY - A non-volatile memory including a substrate, two first conductive layers, a second conductive layer, a first dielectric layer, a second dielectric layer and two heavily doped regions is provided. The substrate has at least two isolation structures therein and an active region between the isolation structures. The first conductive layers are respectively disposed on the isolation structures. The second conductive layer is disposed on the substrate and covering a portion of the active region and a portion of each first conductive layer. The first dielectric layer is disposed between each first conductive layer and the second conductive layer. The second dielectric layer is disposed between the second conductive layer in the active region and the substrate. The heavily doped regions are disposed in the substrate beside the second conductive layer in the active region.07-08-2010
20120286347Semiconductor device - In the trap type memory chip the withstanding voltage is raised up, and then the electric current for reading out is increased. There are formed on the p-type semiconductor substrate11-15-2012
20090206382FLASH MEMORY DEVICE AND PROGRAMMING AND ERASING METHODS THEREWITH - A flash memory device and programming and erasing methods therewith is disclosed, to secure the programming and erasing characteristics by changing a structure of a floating gate, in which the flash memory device includes a first conductive type semiconductor substrate defined as a field area and an active area; a tunnel oxide layer on the active area of the first conductive type semiconductor substrate; a floating gate on the tunnel oxide layer, having at least first and second floating gates having different levels of energy band gap; a dielectric layer on the floating gate; a control gate on the dielectric layer; and second conductive type source/drain regions in the active area of the first conductive type semiconductor substrate at both sides of the floating gate.08-20-2009
20120001248METHODS OF FORMING NANOSCALE FLOATING GATE - A memory cell is provided including a tunnel dielectric layer overlying a semiconductor substrate. The memory cell also includes a floating gate having a first portion overlying the tunnel dielectric layer and a second portion in the form of a nanorod extending from the first portion. In addition, a control gate layer is separated from the floating gate by an intergate dielectric layer.01-05-2012
20100006917SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - This semiconductor device comprises a semiconductor substrate, a gate insulating film formed thereon, and a gate electrode formed through the gate insulating film on the semiconductor substrate. The first silicon nitride film is formed on the upper surface of the gate electrode, and a protection insulating film is formed on the side thereof. The second silicon nitride film is formed on the side of the protection insulating film. The third silicon nitride film is formed on the upper surface of the protection insulating film, and the bottom thereof is formed on a higher position than the bottom of the first silicon nitride film.01-14-2010
20120007164SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a method is disclosed for manufacturing a semiconductor memory device. The method can include forming a plurality of protruding portions in band configurations on a major surface of a semiconductor layer to extend along a first direction parallel to the major surface. The method can include forming an inter-layer insulating film to cover the protruding portions and an inner surface of a trench between the protruding portions. The method can include forming a buried conductive portion by filling a first conductive material into a space inside the trench. The method can include exposing a buried conductive portion side surface by dividing the buried conductive portion along the first direction. The method can include filling a second conductive material into a void of the buried conductive portion exposed at the side surface. In addition, the method can include removing one portion of the second conductive material.01-12-2012
20110284945 Semiconductor Device and a Method of Manufacturing the Same - A semiconductor device having a nonvolatile memory is reduced in size. In an AND type flash memory having a plurality of nonvolatile memory cells having a plurality of first electrodes, a plurality of word lines crossing therewith, and a plurality of floating gate electrodes disposed at positions which respectively lie between the plurality of adjacent first electrodes and overlap the plurality of word lines, as seen in plan view, the plurality of floating gate electrodes are formed in a convex shape, as seen in cross section, so as to be higher than the first electrodes. As a result, even when nonvolatile memory cells are reduced in size, it is possible to process the floating gate electrodes with ease. In addition, it is possible to improve the coupling ratio between floating gate electrodes and control gate electrodes of the word lines without increasing the area occupied by the nonvolatile memory cells.11-24-2011
20090278185DEVICE STRUCTURES FOR A MEMORY CELL OF A NON-VOLATILE RANDOM ACCESS MEMORY AND DESIGN STRUCTURES FOR A NON-VOLATILE RANDOM ACCESS MEMORY - Device and design structures for memory cells in a non-volatile random access memory (NVRAM). The device structure includes a semiconductor body in direct contact with the insulating layer, a control gate electrode, and a floating gate electrode in direct contact with the insulating layer. The semiconductor body includes a source, a drain, and a channel between the source and the drain. The floating gate electrode is juxtaposed with the channel of the semiconductor body and is disposed between the control gate electrode and the insulating layer. A first dielectric layer is disposed between the channel of the semiconductor body and the floating gate electrode. A second dielectric layer is disposed between the control gate electrode and the floating gate electrode.11-12-2009
20110291175Non-Volatile Memory Devices and Methods of Manufacturing the Same - A non-volatile memory device includes a field region that defines an active region in a semiconductor substrate, a floating gate pattern on the active region, a dielectric layer on the floating gate pattern and a control gate on the dielectric layer. The control gate includes a first conductive pattern that has a first composition that crystallizes in a first temperature range, and a second conductive pattern that has a second composition that is different from the first composition and that crystallizes in a second temperature range that is lower than the first temperature range, the first conductive pattern being between the dielectric layer and the second conductive pattern.12-01-2011
20080283899CONDUCTIVE SPACERS EXTENDED FLOATING GATES - A method for manufacturing on a substrate (11-20-2008
20090127610NON-VOLATILE MEMORY AND THE MANUFACTURING METHOD THEREOF - A non-volatile memory disposed on a substrate includes active regions, a memory array, and contacts. The active regions defined by isolation structures disposed in the substrate are extended in a first direction. The memory array is disposed on the substrate and includes memory cell columns, control gate lines and select gate lines. Each of the memory cell columns includes memory cells connected to one another in series and a source/drain region disposed in the substrate outside the memory cells. The contacts are disposed on the substrate at a side of the memory array and arranged along a second direction. The second direction crosses over the first direction. Each of the contacts extends across the isolation structures and connects the source/drain regions in the substrate at every two of the adjacent active regions.05-21-2009
20090078985SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND A METHOD OF MANUFACTURING THE SAME - The memory cell transistor includes, in a first well region, a pair of memory electrodes, one of which serves as source electrode and the other serves as drain electrode and a channel region interposed between the pair of memory electrodes. There is, on a channel region, a first gate electrode disposed near its corresponding memory electrode with an insulating film interposed therebetween, and a second gate electrode disposed through insulating films and a charge storage region and electrically isolated from the first gate electrode. A first negative voltage is applied to the first well region to form a state of reverse bias greater than or equal to a junction withstand voltage between the second gate electrode and the memory electrode near the second gate electrode, thereby enabling injection of hot electrons into the charge storage region and injection of electrons from the well region to the charge storage region.03-26-2009
20120025295SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory device includes first and second element isolation insulating films, first and second gate insulating films, first and second gate wiring and first and second mask layer. First and second upper surfaces of the first and second element isolation insulating films are higher than an upper surface of the substrate, first and second bottom surfaces of the first and second element isolation insulating films are lower than the upper surface of the substrate, a second height from the upper surface of the substrate to the second upper surface is larger than a first height from the upper surface of the substrate to the first upper surface. A height from the upper surface of the substrate to an upper surface of the first mask layer equals a height from the upper surface of the substrate to an upper surface of the second mask layer.02-02-2012
20120025293SEMICONDUCTOR MEMORY DEVICE HAVING A FLOATING GATE AND A CONTROL GATE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a semiconductor memory device having a memory cells and word lines is provided. The memory cells are formed in a semiconductor layer and arranged in matrix. Each of the memory cells has a floating gate and a control gate. Each plurality of the memory cells is connected in series in a row direction. Each of the word lines is connected to each plurality of the control gates in a column direction. First and second intervals are provided for the memory cells alternately in the column direction. The second interval is larger than the first interval.02-02-2012
20120025291NONVOLATILE SEMICONDUCTOR MEMORY TRANSISTOR AND METHOD FOR MANUFACTURING NONVOLATILE SEMICONDUCTOR MEMORY - A nonvolatile semiconductor memory transistor includes an island-shaped semiconductor having a source region, a channel region, and a drain region formed in this order from the silicon substrate side, a floating gate arranged so as to surround the outer periphery of the channel region with a tunnel insulating film interposed between the floating gate and the channel region, a control gate arranged so as to surround the outer periphery of the floating gate with an inter-polysilicon insulating film interposed between the control gate and the floating gate, and a control gate line electrically connected to the control gate and extending in a predetermined direction. The inter-polysilicon insulating film is arranged so as to be interposed between the floating gate and the lower and inner side surfaces of the control gate and between the floating gate and the lower surface of the control gate line.02-02-2012
20100102375SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - This semiconductor device comprises a semiconductor substrate with a first impurity type; a plurality of active areas formed in the semiconductor substrate; an element isolation trench including a first trench part and a second trench part surrounding the plurality of active areas, the first trench part being extended from a surface of the semiconductor substrate to a depth direction, the second trench part being extended from the center of a bottom surface of the first trench part to the depth direction with a narrower width than the width of the first trench part in a width direction; an element isolation insulator film filled in the element isolation trench; a gate electrode formed on the plurality of active areas via a gate insulator film; a plurality of diffusion layers with a second impurity type formed in a surface of the plurality of active areas, the plurality of diffusion layers being located on each side of the element isolation trench and separated each other on each side of the gate electrode; and a channel stop region extended from the bottom surface of the second trench part to the depth direction in a predetermined depth with the first impurity type, the channel stop region having a higher impurity concentration than the impurity concentration of the semiconductor substrate.04-29-2010
20120025290SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A conductive film having a first width in a first direction, an ONO film, and a control gate are formed above a tunnel gate insulating film. With the control gate as a mask, the conductive film is etched to form a floating gate. Then, an inter-layer insulating film is formed. A contact hole whose width in the first direction is larger than the first width is formed in the inter-layer insulating film. Then, sidewall spacer is formed on an inside wall of the contact hole.02-02-2012
20120025289METAL CONTROL GATE FORMATION IN NON-VOLATILE STORAGE - Methods for fabricating control gates in non-volatile storage are disclosed. When forming stacks for floating gate memory cells and transistor control gates, a sacrificial material may be formed at the top of the stacks. After insulation is formed between the stacks, the sacrificial material may be removed to reveal openings. In some embodiments, cutouts are then formed in regions in which control gates of transistors are to be formed. Metal is then formed in the openings, which may include the cutout regions. Therefore, floating gate memory cells having at least partially metal control gates and transistors having at least partially metal control gates may be formed in the same process. A barrier layer may be formed prior to depositing the metal in order to prevent silicidation of polysilicon in the control gates.02-02-2012
20090014774NONVOLATILE SEMICONDUCTOR MEMORY ELEMENT AND NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A memory element includes: a semiconductor region formed in a semiconductor substrate; source and drain regions formed at a distance from each other in the semiconductor region; a first insulating layer formed on the semiconductor region between the source and drain regions; a charge accumulating layer formed on the first insulating layer, and having a stacked structure including at least three conductor films and inter-conductor insulating films provided between the adjacent conductor films, a dielectric constant of any one of the inter-conductor insulating films located at a greater distance from the semiconductor substrate being higher than that of any one of the inter-conductor insulating films closer to the semiconductor substrate, a dielectric constant of each of the inter-conductor insulating films being lower than that of the first insulating layer; and a second insulating layer formed on the charge accumulating layer, and having a higher dielectric constant than that of any one of the inter-conductor insulating films.01-15-2009
20090014773TWO BIT MEMORY STRUCTURE AND METHOD OF MAKING THE SAME - A method for fabricating the memory structure includes: providing a substrate having a pad, forming an opening in the pad, forming a first spacer on a sidewall of the opening, filling the opening with a sacrificial layer, removing the first spacer and exposing a portion of the substrate, removing the exposed substrate to define a first trench and a second trench, removing the sacrificial layer to expose a surface of the substrate to function as a channel region, forming a first dielectric layer on a surface of the first trench, a surface of the second trench and a surface of the channel region, filling the first trench and the second trench with a first conductive layer, forming a second dielectric layer on a surface of the first conductive layer and the surface of the channel region, filling the opening with a second conductive layer, and removing the pad.01-15-2009
20090189210Semiconductor Flash Memory Device and Method of Fabricating the Same - A semiconductor flash memory device. The flash memory device includes a floating gate electrode disposed in a recess having slanted sides in a semiconductor substrate. A gate insulation film is interposed between the floating gate electrode and the semiconductor substrate. A control gate electrode is disposed over the floating gate electrode. The floating gate electrode includes projections adjacent to the slanted sides of the recess.07-30-2009
20090152615SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - Embodiments relate to a semiconductor device that may include a floating gate, an inter poly dielectric formed on and/or over both sides of the floating gate in a bit line direction and on and/or over both side of the floating gate in a word line direction, and a control gate formed on and/or over the IPD. According to embodiments, an IPD may be formed on and/or over a top and four sides of a floating gate. This may increase a coupling ratio of a semiconductor device.06-18-2009
20090121274SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A salicide treatment is performed on a common source line to reduce surface resistance and contact resistance, thereby improving a cell current characteristic. Therefore, a chip can be reduced in size and chips per wafer can be increased, thereby achieving high yield. In addition, it is possible to overcome the structural limitation of the flash cell when the semiconductor memory device is highly integrated and shrunken.05-14-2009
20090121273Low-voltage memory having flexible gate charging element - In a non-volatile semiconductor memory device including a source region separated from a drain region by a channel region and with an electrically floating gate electrode spaced from and overlying the channel region, a flexible member is spaced from the floating gate and capable of being flexed towards the floating gate for depositing or removing electrical charge on the floating gate in response to a voltage potential between the flexible member and the channel region. In one embodiment, the flexible member comprises a contact gate electrode. In another embodiment, only a single gate electrode is employed without a separate floating gate.05-14-2009
20120228692NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A non-volatile memory device includes a plurality of stacked patterns where a tunnel insulation layer, a floating gate, and a dielectric layer are sequentially stacked over a substrate, trenches formed in the substrate between the stacked patterns, an isolation layer gap-filling the trenches and space between the stacked patterns, and a control gate formed over the dielectric layer.09-13-2012
20090096008NONVOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A nonvolatile memory device having a blocking insulating layer with an excellent data retention property and a method of fabricating the same are provided. The nonvolatile memory device may include a semiconductor substrate having a channel region formed therein; and a gate stack including a tunneling insulating layer, a charge storing layer, a blocking insulating layer and a control gate electrode sequentially stacked on the channel region of the semiconductor substrate. The blocking insulating layer may comprise a lanthanum aluminum oxide having a formula of La04-16-2009
20090096007SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory device comprises a plurality of transistors having a stacked-gate structure. Each transistor includes a semiconductor substrate, a gate insulator formed on the semiconductor substrate, a lower gate formed on the semiconductor substrate with the gate insulator interposed, an intergate insulator formed on the lower gate, and an upper gate formed and silicided on the lower gate with the intergate insulator interposed. A portion of the transistors has an aperture formed through the intergate insulator to connect the lower gate with the upper gate and further includes a block film composed of an insulator and formed smaller than the upper gate and larger than the aperture above the upper gate to cover the aperture.04-16-2009
20090096005SEMICONDUCTOR MEMORY DEVICE INCLUDING DOUBLE SPACERS ON SIDEWALL OF FLATING GATE, ELECTRONIC DEVICE INCLUDING THE SAME - A semiconductor memory device includes a device isolation layer formed in a semiconductor substrate to define a plurality of active regions. Floating gates are disposed on the active regions. A control gate line overlaps top surfaces of the floating gates and crosses over the active regions. The control gate line has an extending portion disposed in a gap between adjacent floating gates and overlapping sidewalls of the adjacent floating gates. First spacers are disposed on the sidewalls of the adjacent floating gates. Each of the first spacers extends along a sidewall of the active region and along a sidewall of the device isolation layer. Second spacers are disposed between outer sidewalls of the first spacers and the extending portion and are disposed above the device isolation layer. An electronic device including a semiconductor memory device and a method of fabricating a semiconductor memory device are also disclosed.04-16-2009
20090146205Floating Gate of Flash Memory Device and Method of Forming the Same - Disclosed is a floating gate of a flash memory device, wherein a tunneling oxide layer is formed on a semiconductor substrate, and a floating gate is formed in the shape of a lens having a convex top surface.06-11-2009
20090146204SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes a first poly layer over a semiconductor substrate, an IPD layer over the first poly layer, a second poly layer over the IPD layer, an oxide layer over a sidewall of the second poly layer, a first insulating layer over a sidewall of the oxide layer, and a second insulating layer over a sidewall of the first insulating layer.06-11-2009
20080237690SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - To provide a semiconductor device in which a high-performance and high-breakdown-voltage p-channel type MOS transistor having a surface channel structure and a memory cell are formed on the same substrate, and a method of manufacturing the semiconductor device. A method of manufacturing a semiconductor device including a stacked gate type nonvolatile memory cell and a p-channel type first transistor, includes: forming a gate insulating film of the first transistor on a semiconductor substrate; forming a tunnel insulating film of the stacked gate type nonvolatile memory cell on the semiconductor substrate; forming a first conductive layer containing an n-type impurity on the tunnel insulating film and the gate insulating film; and implanting p-type impurity ions to a region of the first conductive layer for forming the first transistor to turn the region of the first conductive layer into a p-type region.10-02-2008
20080237689NONVOLATILE SEMICONDUCTOR MEMORY DEVICE, METHOD FOR MANUFACTURING THE SAME, AND SEMICONDUCTOR DEVICE - A nonvolatile semiconductor memory device includes a first insulating film formed on a semiconductor substrate, a floating gate formed on the first insulating film, a second insulating film on the floating gate, a semiconductor layer formed on the second insulating film, a gate insulating film formed on the semiconductor layer, and a control gate formed on the gate insulating film. The semiconductor substrate is provided with a first source and a first drain both for writing of data, and the semiconductor layer below both sides of the control gate is provided with a second source and a second drain both for readout of the data.10-02-2008
20080237688MEMORY CELL OF NONVOLATILE SEMICONDUCTOR MEMORY - A memory cell of a nonvolatile semiconductor memory includes a first insulating film whose principal constituent elements are Si, O and N, a charge storage layer whose principal constituent elements are Hf, O and N, formed on the first insulating film, a second insulating film having dielectric constant higher than that of the first insulating film and formed on the charge storage layer, and a control gate electrode formed on the second insulating film. Relation between a composition of the first insulating film and a composition of the charge storage layer is determined under the conditions that (A) a valence band offset of the first insulating film is larger than a valence band offset of the charge storage layer, and (B) a trap energy level of electrons due to oxygen vacancies in the charge storage layer exists within a band gap of the charge storage layer.10-02-2008
20100123179Two-Step Self-Aligned Source Etch With Large Process Window - System and method for self-aligned etching. According to an embodiment, the present invention provides a method for performing self-aligned source etching process. The method includes a step for providing a substrate material. The method also includes a step for forming a layer of etchable oxide material overlying at least a portion of the substrate material. The layer of etchable oxide material can characterized by a first thickness. The layer of etchable oxide material includes a first portion, a second portion, and a third portion. The second portion is positioned between the first portion and the third portion. The method additionally includes a step for forming a plurality of structures overlying the layer of etchable oxide material. The plurality of structures includes a first structure and a second structure.05-20-2010
20090309150Semiconductor Device And Method For Making Semiconductor Device - One or more embodiments relate to a memory device, comprising: a substrate; a gate stack disposed over the substrate, the gate stack comprising a charge storage layer and a high-k dielectric layer; and a cover layer disposed over at least the sidewall surfaces of the high-k dielectric layer.12-17-2009
20090267132GATE STRUCTURES IN SEMICONDUCTOR DEVICES - A gate structure includes an insulation layer on a substrate, a first conductive layer pattern on the insulation layer, a metal ohmic layer pattern on the first conductive layer pattern, a diffusion preventing layer pattern on the metal ohmic layer pattern, an amorphous layer pattern on the diffusion preventing layer pattern, and a second conductive layer pattern on the amorphous layer pattern. The gate structure may have a low sheet resistance and desired thermal stability.10-29-2009
20090267130STRUCTURE AND PROCESS INTEGRATION FOR FLASH STORAGE ELEMENT AND DUAL CONDUCTOR COMPLEMENTARY MOSFETS - A method is provided for simultaneously fabricating a flash storage element, an NFET and a PFET having metal gates with different workfunctions. A first gate metal layer of the NFET having a first workfunction is deposited simultaneously with a first metal layer for forming the floating gate of the flash storage element. A second gate metal layer of the PFET having a second workfunction different from the first workfunction is deposited simultaneously with a second metal layer for forming the control gate of the flash storage element. A semiconductor layer is deposited over the first and second metal layers and gate metal layers and patterned to form first, second and third gates. Source and drain regions of the flash storage element, the NFET and the PFET are formed adjacent to the first, second and third gates, respectively.10-29-2009
20110147819SEMICONDUCTOR DEVICE - p-type wells are provided within an n-type embedded well of a semiconductor substrate lying in an area for forming a flash memory, in a state of being isolated from one another. A capacitance section, a data write/erase charge injection/discharge section and a data read MIS•FET are disposed in each of the p-type wells. The capacitance section is disposed between the data write/erase charge injection/discharge section and the data read MIS•FET. In the data write/erase charge injection/discharge section, writing and erasing of data by an FN tunnel current at a channel entire surface are performed.06-23-2011
20110147820Non-Volatile Memory Cell Having a Heating Element and a Substrate-Based Control Gate - The number of times that a non-volatile memory (NVM) can be programmed and erased is substantially increased by utilizing a localized heating element that anneals the oxide that is damaged by tunneling charge carriers when the NVM is programmed and erased. The program and erase voltages are also reduced when heat from the heating element is applied prior to programming and erasing.06-23-2011
20100084701SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - A semiconductor device having a nonvolatile memory is reduced in size. In an AND type flash memory having a plurality of nonvolatile memory cells having a plurality of first electrodes, a plurality of word lines crossing therewith, and a plurality of floating gate electrodes disposed at positions which respectively lie between the plurality of adjacent first electrodes and overlap the plurality of word lines, as seen in plan view, the plurality of floating gate electrodes are formed in a convex shape, as seen in cross section, so as to be higher than the first electrodes. As a result, even when nonvolatile memory cells are reduced in size, it is possible to process the floating gate electrodes with ease. In addition, it is possible to improve the coupling ratio between floating gate electrodes and control gate electrodes of the word lines without increasing the area occupied by the nonvolatile memory cells.04-08-2010
20100084700EEPROM and Method for Manufacturing EEPROM - An electrically erasable programmable read only memory (EEPROM) is disclosed. The EEPROM includes a tunneling region in a semiconductor substrate, a control gate region in the semiconductor substrate and separated from the tunneling region by a device isolating layer, a tunnel oxide layer in a trench in the semiconductor substrate between the tunneling region and the control gate region, and a polysilicon layer on the tunnel oxide layer.04-08-2010
20110062507SEMICONDUCTOR DEVICE AND A METHOD OF FABRICATING THE SAME - A semiconductor device is provided. The semiconductor device includes a memory device, and the memory device includes a substrate, two stacked gates, two spacers, an insulating layer, and a dielectric layer. The stacked gates having a gap therebetween are located on the substrate. The spacers having a pipe or a seam therebetween are respectively located at sidewalls of each of the stacked gates in the gap. The pipe or the seam is filled with the insulating layer. The dielectric layer is located on the substrate and covers the insulating layer and the stacked gates.03-17-2011
20120193698NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a nonvolatile semiconductor memory device includes an element region, a gate insulating film, a first gate electrode, an intergate insulating film, a second gate electrode and an element isolation region. The gate insulating film is formed on the element region. The first gate electrode is formed on the gate insulating film. The intergate insulating film is formed on the first gate electrode and has an opening. The second gate electrode is formed on the intergate insulating film and in contact with the first gate electrode via the opening. The element isolation region encloses a laminated structure formed by the element region, the gate insulating film, and the first gate electrode. The air gap is formed between the element isolation region and side surfaces of the element region, the gate insulating film and the first gate electrode.08-02-2012
20100032745SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF - A semiconductor device includes: a memory cell transistor which has a floating gate, a control gate, and a source and a drain formed in a semiconductor substrate on both sides of the floating gate via a channel area; and a selecting transistor which has a select gate and a source and a drain formed in the semiconductor substrate on both sides of the select gate, wherein the source of the selecting transistor is connected to the drain of the memory cell transistor, the source of the memory cell transistor has an N-type first impurity diffusion layer, an N-type second impurity diffusion layer deeper than the first impurity diffusion layer, and an N-type third impurity diffusion layer which is shallower than the second impurity diffusion layer, and an impurity density of the second impurity diffusion layer is lower than that of the third impurity diffusion layer.02-11-2010
20090206384ILLUMINATING EFFICIENCY-INCREASABLE AND LIGHT-ERASABLE MEMORY - An illuminating efficiency-increasable and light-erasable memory including a substrate, a memory device, many dielectric layers, and many cap layers is provided. The substrate includes a memory region. The memory device includes a select gate and a floating gate, and the select gate and the floating gate are disposed adjacently on the substrate in the memory region. The dielectric layers are disposed on the substrate and cover the memory device. The dielectric layers have an opening located above the floating gate. Each of the cap layers is disposed on each of the dielectric layers, respectively.08-20-2009
20090206383Semiconductor Devices Having Tunnel and Gate Insulating Layers - A semiconductor device includes a semiconductor substrate having a surface, buried isolation regions protruding from the surface of the semiconductor substrate, and a first insulating layer on the surface of the semiconductor substrate between the isolation regions and including a fluorine, nitrogen, and/or heavy hydrogen impurity. A floating electrode is on the first insulating layer, a second insulating layer is on the floating electrode and the isolation regions, and a control gate electrode is on the second insulating layer. Related methods of forming semiconductor devices are also disclosed.08-20-2009
20090184359Split-gate non-volatile memory devices having nitride tunneling layers - A memory device having a cell stack and a select gate formed adjacent to the cell stack. The cell stack includes a first trap-free-nitride layer formed on a channel region of a substrate, a second nitride layer formed on the first nitride layer, an oxide layer formed on the second nitride layer, a control gate formed on the high-K oxide layer, and a poly spacer as the select gate formed adjacent to the control gate.07-23-2009
20090273016NANOCRYSTAL FORMATION USING ATOMIC LAYER DEPOSITION AND RESULTING APPARATUS - Nanocrystal structures formed using atomic layer deposition (ALD) processes are useful in the formation of integrated circuits such as memory devices. Rather than continuing the ALD process until a continuous layer is formed, the ALD process is halted prematurely to leave a discontinuous formation of nanocrystals which are then capped by a different material, thus forming a layer with a discontinuous portion and a bulk portion. Such nanocrystals can serve as charge-storage sites within the bulk portion, and the resulting structure can serve as a floating gate of a floating-gate memory cell. A floating gate may contain one or more layers of such nanocrystal structures.11-05-2009
20090045450Non-volatile memory device and method of fabricating the same - Provided are a non-volatile memory device, which may have higher integration density, improved or optimal structure, and/or reduce or minimize interference between adjacent cells without using an SOI substrate, and a method of fabricating the non-volatile memory device. The non-volatile memory device may include: a semiconductor substrate comprising a body, and a pair of fins protruding from the body; a buried insulating layer filling between the pair of fins; a pair of floating gate electrodes on outer surfaces of the pair of fins to a height greater than that of the pair of fins; and a control gate electrode on the pair of floating gate electrodes.02-19-2009
20080290393Nonvolatile semiconductor memory device and manufacturing method thereof, semiconductor device and manufacturing method thereof, and manufacturing method of insulating film - An object is to provide a technique to manufacture an insulating film having excellent film characteristics. In particular, an object is to provide a technique to manufacture a dense insulating film with a high withstand voltage. Moreover, an object is to provide a technique to manufacture an insulating film with few electron traps. An insulating film including oxygen is subjected to plasma treatment using a high frequency under the conditions where the electron density is 1×1011-27-2008
20090090958Semiconductor Constructions - Some embodiments include methods of forming a NAND cell unit having a NAND string gate closest to a select gate with a different width than other NAND string gates more distant from the select gate. Some embodiments include utilization of an etch comprising HBr and O04-09-2009
20090090955ELEVATED CHANNEL FLASH DEVICE AND MANUFACTURING METHOD THEREOF - A FLASH device including a substrate having a protrusive portion integrally formed thereon, two floating gates, a control gate and a dielectric layer is provided. The two floating gates are disposed on two sides of the protrusive portion and respectively covering a portion of the protrusive portion. The control gate is disposed on top of the protrusive portion and sandwiched between the two floating gates. The dielectric layer is disposed between each of the two floating gates and the control gate. Because the control gate of the FLASH device is disposed on the protrusive portion, an elevated channel can be formed. Moreover, because of the position of the two floating gates, an effective floating gate (FG) length can be increased without impacting the cell density.04-09-2009
20090090954NONVOLATILE MEMORY AND MANUFACTURING METHOD THEREOF - Memory elements, switching elements, and peripheral circuits to constitute a nonvolatile memory are integrally formed on a substrate by using TFTs. Since semiconductor active layers of memory element TFTs are thinner than those of other TFTs, impact ionization easily occurs in channel regions of the memory element TFTs. This enables low-voltage write/erase operations to be performed on the memory elements, and hence the memory elements are less prone to deteriorate. Therefore, a nonvolatile memory capable of miniaturization can be provided.04-09-2009
20090283813NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to an aspect of the present invention, there is provided a method for fabricating a nonvolatile semiconductor memory device including a memory cell being formed in a first region of a semiconductor substrate and a periphery circuit being formed in a second region of the semiconductor substrate, including forming a first gate electrode material film over the semiconductor substrate via a first gate insulator in the first region, etching the first gate electrode material film and the first gate insulator using a mask having a first opening in a first element isolation of the first region, etching the semiconductor substrate to a first depth to form a first isolation groove, forming a first insulation isolation layer in the first isolation groove, forming a second insulator on the first insulation isolation layer and on the first gate electrode, removing the second insulator by anisotropic etching, etching an upper portion of the first gate electrode to a second depth to form a first concave portion on the upper portion of the first gate electrode, etching the first side-wall film and the first insulation isolation layer to a depth at a bottom surface of the first concave portion, forming a second gate insulator on the upper portion of the first gate electrode, and forming a second gate electrode material film on the second gate insulator.11-19-2009
20110198681SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND A METHOD OF MANUFACTURING THE SAME - A semiconductor device having a nonvolatile memory cell which includes a semiconductor substrate, a first insulating film formed over the semiconductor substrate, a control electrode formed over the first insulating film, the first insulating film acting as a gate insulator for the control gate electrode, a second insulating film formed over the semiconductor substrate, and a memory gate electrode formed over the second insulating film and being adjacent to the control gate electrode, the second insulating film acting as a gate insulator for the memory gate electrode and featuring a non-conductive charge trap film, the control gate electrode having a different type conductivity than that of the memory gate electrode. A manufacturing technique for a semiconductor device including a nonvolatile memory cell having control gate and memory gate electrodes is also featured.08-18-2011
20080211007Self-Aligned Trenches With Grown Dielectric For High Coupling Ratio In Semiconductor Devices - Self-aligned trench filling to isolate active regions in high-density integrated circuits is provided. A deep, narrow trench is etched into a substrate between active regions. The trench is filled by growing a suitable dielectric such as silicon dioxide. The oxide grows from the substrate to fill the trench and into the substrate to provide an oxide of greater width and depth than the trench. Storage elements for a NAND type flash memory system, for example, can be fabricated by etching the substrate to form the trench after or as part of etching to form NAND string active areas. This can ensure alignment of the NAND string active areas between isolation trenches. Because the dielectric growth process is self-limiting, an open area resulting from the etching process can be maintained between the active areas. A subsequently formed inter-gate dielectric layer and control gate layer can fill the open area to provide sidewall coupling between control gates and floating gates.09-04-2008
20080211006NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A nonvolatile semiconductor memory including a semiconductor substrate having an upper surface; a plurality of memory cell transistors formed in the semiconductor substrate, each memory cell transistor including a gate electrode having a gate insulating layer on the upper surface of the semiconductor substrate, a floating gate electrode layer on the gate insulating layer, an inter-gate insulating layer on the floating gate electrode layer, and a control gate electrode layer on the inter-gate insulating layer; a first oxide-based insulating film formed above the upper surface of the semiconductor substrate between the gate electrodes, and including an upper surface as high or higher than that of the floating gate electrode layer but lower than that of the control gate electrode layer; a nitride-based insulating film containing boron formed on the first oxide-based insulating film and the control gate layer; and a second oxide-based insulating film formed on the nitride-based insulating film.09-04-2008
20090114973METHOD FOR FORMING SELF-ALIGNED CONTACTS AND LOCAL INTERCONNECTS SIMULTANEOUSLY - The present invention relates generally to semiconductors, and more specifically to semiconductor memory device structures and an improved fabrication process for making the same. The improved fabrication process allows the self-aligned contacts and local interconnects to the processed simultaneously. The process allows the minimal distance requirement between the self-aligned contacts and the local interconnects to be widened, which makes the patterning of self-aligned contacts and local interconnects easier. The widened minimal distance requirement also allows further memory cell shrinkage. The improved structures of self-aligned contacts and local interconnects also have excellent isolation characteristic.05-07-2009
20090289293SEMICONDUCTOR DEVICE HAVING TRI-GATE STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor device of an example of the invention comprises a memory cell and a select gate transistor provided for the memory cell. A gate electrode of the select gate transistor has a Tri-gate structure in which an upper surface of a gate insulating film formed above a channel of the select gate transistor is set higher than a portion of an upper surface of an element isolation region of the select gate transistor.11-26-2009
20090278190Nonvolatile semiconductor memory - A nonvolatile semiconductor memory according to the present invention includes memory cell units, which include data select lines formed in parallel to each other, data transfer lines crossing the data select lines and aligned in parallel to each other, and electrically rewritable memory cell transistors disposed at intersections of the data transfer lines and the data select lines. It further includes: a memory cell array block in which the memory cell units are disposed along the data select lines; first source lines, connected to one end of the memory cell units, and aligned along the data select lines; and second source lines electrically connected to the first source lines, and disposed along the data select lines.11-12-2009
20090294825STORAGE CELL HAVING A T-SHAPED GATE ELECTRODE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing an integrated circuit including at least one storage cell is provided. The method includes providing a substrate having a first and second side, and a plurality of parallel trenches so that a dividing wall is formed between adjacent trenches, filling the trenches with an insulating compound, providing a first insulating layer having a first and second side on the top surface of the dividing wall, wherein the first side is arranged on the substrate's first side, providing a first conductive layer having a first and second side, wherein the first side is arranged on the insulating layer's second side, wherein the conductive layer protrudes from the substrate surface, providing a second conductive layer having a first and second side, wherein the first side is located on the first conductive layer's second side, and removing parts of the second conductive layer by an anisotropic etching means.12-03-2009
20090278188NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - To reduce the writing and erasing voltages of a memory transistor without increasing the area of a memory cell, and to reduce the area of a memory cell without increasing the writing and erasing voltages. The memory cell includes a memory transistor having a first island-shaped semiconductor region, a floating gate and a control gate. In addition, a second island-shaped semiconductor region is formed under the floating gate with an insulating film interposed therebetween. Since the second island-shaped semiconductor region is electrically connected to the control gate, a capacitance is formed between the second island-shaped semiconductor region and the floating gate. This capacitance contributes to an increase in the coupling ratio of the memory transistor, which makes it possible to increase the coupling ratio without increasing the area of the memory cell. Furthermore, the area of the memory cell can be reduced without reducing the coupling ratio.11-12-2009
20090278189SEMICONDUCTOR DEVICE WITH RESISTOR AND METHOD OF FABRICATING SAME - A semiconductor device includes a cell array region disposed on a semiconductor substrate and comprising a first cell gate pattern, a cell semiconductor pattern disposed on the first cell gate pattern, and a second cell gate pattern disposed on the cell semiconductor pattern. The semiconductor device also includes a peripheral circuit region disposed on the semiconductor substrate and comprising a peripheral gate pattern, and a resistor disposed in the peripheral circuit region at level above the semiconductor substrate similar to that of the cell semiconductor pattern.11-12-2009
20090278187SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device of an aspect of the present invention includes a semiconductor substrate, two diffusion layers provided in the semiconductor substrate, a gate insulating film provided on a channel region between the two diffusion layers, and a gate electrode which is composed of a stack of a plurality of conductive films and a plurality of insulating films provided on the gate insulating film and a silicide layer provided on the stack, wherein of the plurality of films included in the stack, the conductive film different in configuration from the silicide layer is in contact with the gate insulating film.11-12-2009
20090278186Double Gate Transistor and Method of Manufacturing Same - A double gate transistor on a semiconductor substrate (11-12-2009
20130099301NONVOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THEREOF - A nonvolatile memory device and a method of manufacturing thereof are provided. The method includes forming a floating gate on a substrate, forming a dielectric layer to conform to a shape of the floating gate, forming a conductive layer to form a control gate on the substrate, the control gate covering the floating gate and the dielectric layer, forming a photoresist pattern on one side of the conductive layer, forming the control gate in the form of a spacer to surround sides of the floating gate, the forming of the control gate including performing an etch-back on the conductive layer until a portion of the dielectric layer on the floating gate is exposed, and forming a poly pad, to which a plurality of contact plugs are connected, on one side of the control gate, the forming of the poly pad including removing the photoresist pattern.04-25-2013
20130099302SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory device according to embodiment of the present invention includes a tunnel insulating layer formed over a semiconductor substrate, a floating gate formed over the tunnel insulating layer, a dielectric layer formed over the floating gate, and a control gate including a third silicon layer formed over the dielectric layer, a fourth silicon layer formed over the third silicon layer, and a conductive layer formed over the fourth silicon layer, wherein the fourth silicon layer has a greater width than the third silicon layer.04-25-2013
20110169067STRUCTURE AND PRODUCTION PROCESS OF A MICROELECTRONIC 3D MEMORY DEVICE OF FLASH NAND TYPE - A microelectronic flash memory device including a plurality of memory cells including transistors fitted with a matrix of channels connecting a block of common source to a second block on which bit lines rest, the transistors also being formed by a plurality of gates including at least one gate material, including a first selection gate coating the channels, a plurality of control gates coating the channels, a plurality of second selection gates each coating the channels of the same row and the matricial arrangement, at least one or more of the gates based on superposition of layers including at least one first layer of dielectrical material, at least one charge store zone, and at least one second layer of dielectrical material.07-14-2011
20090294827SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor memory device includes: a semiconductor substrate; a first impurity region; a second impurity region; a channel region; a first gate formed on a main surface on a side of the first impurity region; a second gate formed on the main surface on a side of the second impurity region, with a second insulating film being interposed; and a third insulating film formed on a side surface of the first gate. An interface between the third insulating film and the semiconductor substrate directly under the third insulating film is located above an interface between the second insulating film and the main surface of the semiconductor substrate directly under the second insulating film. The total number of steps can thus be reduced, and lower cost is achieved.12-03-2009
20100213533NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR MANUFACTURING THE SAME - A non-volatile semiconductor storage device includes: a semiconductor substrate; a source region and a drain region formed in the semiconductor substrate so as to be separated from each other; a first insulating film formed between the source region and the drain region, on the semiconductor substrate; a floating electrode formed on the first insulating film and including a semiconductor conductive material layer having extension strain; a second insulating film formed on the floating electrode; and a control electrode formed on the second insulating film. The extension strain of the floating electrode becomes gradually small as the location advances from the second insulating film toward the first insulating film, and the floating electrode has extension strain of 0.01% or more at an interface between the floating electrode and the second insulating film, and has extension strain less than 0.01% at an interface between the floating electrode and the first insulating film.08-26-2010
20090261399Nonvolatile semiconductor memory device and manufacturing method thereof - A nonvolatile semiconductor memory device includes a semiconductor substrate of a first conductivity type, a pair of source and drain diffusion regions of a second conductivity type oppositely formed on a surface of the semiconductor substrate, and a stacked structure having a gate insulating film, a charge accumulation film, an interlayer insulating film and a control gate which are formed in order on a channel region of the surface of the semiconductor substrate interposed between the source and drain diffusion regions. An edge of the stacked structure in the vicinity of the source region is formed away from a junction position between the source diffusion region and the channel region.10-22-2009
20090261398NON-VOLATILE MEMORY WITH SIDEWALL CHANNELS AND RAISED SOURCE/DRAIN REGIONS - A non-volatile storage system in which a sidewall insulating layer of a floating gate is significantly thinner than a thickness of a bottom insulating layer, and in which raised source/drain regions are provided. During programming or erasing, tunneling occurs predominantly via the sidewall insulating layer and the raised source/drain regions instead of via the bottom insulating layer. The floating gate may have a uniform width or an inverted T shape. The raised source/drain regions may be epitaxially grown from the substrate, and may include a doped region above an undoped region so that the channel length is effectively extended from beneath the floating gate and up into the undoped regions, so that short channel effects are reduced. The ratio of the thicknesses of the sidewall insulating layer to the bottom insulating layer may be about 0.3 to 0.67.10-22-2009
20090261397Integrated Circuit with Floating-Gate Electrodes Including a Transition Metal and Corresponding Manufacturing Method - An integrated circuit is described. The integrated circuit may comprise a multitude of floating-gate electrodes, wherein at least one of the floating-gate electrodes has a lower width and an upper width, the lower width being larger than the upper width, and wherein the at least one of the floating-gate electrodes comprises a transition metal. A corresponding manufacturing method for an integrated circuit is also described.10-22-2009
20090166705NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THEREOF - In a nonvolatile semiconductor memory device, second conductivity type source and drain regions are formed separately from each other in a first conductivity type semiconductor region on a surface thereof. A second conductivity type semiconductor region is formed in the first conductivity type semiconductor region arranged between the source and drain regions and is formed separately from the source and drain regions. A first gate insulating film is formed on the semiconductor substrate arranged between the source and drain regions. A floating gate is formed on the first gate insulating film. An intermediate gate insulating film is formed on the floating gate. A control gate is formed on the floating gate over the intermediate gate insulating film.07-02-2009
20120292685SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - It is made possible to provide a method for manufacturing a semiconductor device that has a high-quality insulating film in which defects are not easily formed, and experiences less leakage current. A method for manufacturing a semiconductor device, includes: forming an amorphous silicon layer on an insulating layer; introducing oxygen into the amorphous silicon layer; and forming a silicon oxynitride layer by nitriding the amorphous silicon layer having oxygen introduced thereinto.11-22-2012
20110266609SiH4 SOAK FOR LOW HYDROGEN SIN DEPOSITION TO IMPROVE FLASH MEMORY DEVICE PERFORMANCE - Prior to deposition of a silicon nitride (SiN) layer on a structure, a non-plasma enhanced operation is undertaken wherein the structure is exposed to silane (SiH11-03-2011
20100102376Atomic Layer Deposition Processes for Non-Volatile Memory Devices - Embodiments of the invention provide memory devices and methods for forming such memory devices. In one embodiment, a method for fabricating a non-volatile memory device on a substrate is provided which includes depositing a first polysilicon layer on a substrate surface, depositing a silicon oxide layer on the first polysilicon layer, depositing a first silicon oxynitride layer on the silicon oxide layer, depositing a silicon nitride layer on the first silicon oxynitride layer, depositing a second silicon oxynitride layer on the silicon nitride layer, and depositing a second polysilicon layer on the second silicon oxynitride layer. In some examples, the first polysilicon layer is a floating gate and the second polysilicon layer is a control gate.04-29-2010
20080246075SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device includes forming a plurality of gate electrodes for a plurality of memory cell transistors on a surface of a semiconductor substrate, each gate electrode including a polycrystalline layer on an upper portion thereof; filling a first silicon oxide film between the plurality of gate electrodes; exposing the polycrystalline layers; depositing a metal layer on the polycrystalline layers; alloying the metal layer with the polycrystalline layers to form silicide layers and removing a remainder metal layer unused as the silicide layer; forming a second silicon oxide film on and between the gate electrodes, an upper surface of the second silicon oxide film being higher than an upper surface of the gate electrode in regions over the gate electrodes and regions between the gate electrodes; and forming a silicon nitride film on the second silicon oxide film.10-09-2008
20080246076Methods for nanopatterning and production of nanostructures - Methods for nanopatterning and methods for production of nanoparticles utilizing such nanopatterning are described herein. In exemplary embodiments, masking nanoparticles are disposed on various substrates and to form a nanopatterned mask. Using various etching and filling techniques, nanoparticles and nanocavities can be formed using the masking nanoparticles and methods described throughout.10-09-2008
20090166707FLASH MEMORY DEVICE AND METHOD FOR MANUFACTURING THE DEVICE - A flash memory device and a method for manufacturing the device includes forming a device isolation layer in a semiconductor substrate defining active regions, forming a control gate layer over the entire upper surface of the semiconductor substrate, forming a gate mask over the control gate layer, the gate mask being used to provide gate lines on the device isolation layer with grooves at positions opposite each other, and forming the grooves by etching the control gate layer using the gate mask as an etching mask, and forming the gate lines on the device isolation layer. A common source line can be more easily defined during a SAS process including photography and etching processes, and a reduced source resistance can be accomplished, resulting in an improvement in characteristics of the flash memory device.07-02-2009
20090166706Semiconductor Device and Method of Manufacturing the Same - A semiconductor device according to an embodiment of the present invention has a bit line and a word line. The device includes a substrate which is provided with first trenches extending in a bit-line direction and has side surfaces forming sidewalls of the first trenches, the substrate being provided with bird's beaks at upper edges of the side surfaces, a first gate insulator formed on the substrate between the first trenches, a floating gate formed on the first gate insulator between the first trenches and located between second trenches extending in a word-line direction, the floating gate not being provided with bird's beaks at lower edges of side surfaces facing the first trenches, a second gate insulator formed on the floating gate between the second trenches, and a control gate formed on the second gate insulator between the second trenches.07-02-2009
20090166704NON-VOLATILE STORAGE WITH SUBSTRATE CUT-OUT AND PROCESS OF FABRICATING - Shallow trench isolation regions are positioned between NAND strings (or other types of non-volatile storage). These isolation regions include sections that form concave cut-out shapes in the substrate for the NAND string (or other types of non-volatile storage). The floating gates (or other charge storage devices) of the NAND strings hang over the sections of the isolation region that form the concave cut-out shape in the substrate. To manufacture such a structure, a two step etching process is used to form the isolation regions. In the first step, isotropic etching is used to remove substrate material in multiple directions, including removing substrate material underneath the floating gates. In the second step, anisotropic etching is used to create the lower part of the isolation region.07-02-2009
20080277713SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor memory includes a memory cell array area provided with first and second memory cells and having a first active area and a first element isolation area constituting a line & space structure, and having a floating gate electrode and a control gate electrode in the first active area, a word line contact area adjacent to the memory cell array area and having a second active area, first and second word lines with a metal silicide structure, functioning respectively as the control gate electrodes of the first and second memory cells and arranged to straddle the memory cell array area and the word line contact area. A dummy gate electrode is arranged just below the first and second word lines in the second active area.11-13-2008
20080283897FLASH MEMORY DEVICE AND FABRICATION METHOD THEREOF - The invention provides a flash memory device and a method for fabricating thereof. The device comprises a gate stack layer of a gate dielectric layer and a gate polysilicon layer formed on a substrate, a stack layer comprising a floating polysilicon layer and gate spacer formed on the sidewall of the gate stack layer. A metal layer is formed on the gate stack layer and is utilized in place of a portion of the gate polysilicon layer. Because the metal layer has relatively high conductivity and is electrically connected to a metal plug later formed, current velocity of the device is increased to improve performance.11-20-2008
20080290394GATE ELECTRODE FOR A NONVOLATILE MEMORY CELL - A nonvolatile memory cell includes a substrate comprising a source, drain, and channel between the source and the drain. A tunnel dielectric layer overlies the channel, and a localized charge storage layer is disposed between the tunnel dielectric layer and a control dielectric layer. A gate electrode has a first surface adjacent to the control dielectric layer, and the first surface includes a midsection and two edge portions. According to one embodiment, the midsection defines a plane, and at least one edge portion extends away from the plane. Preferably, the edge portion extending away from the plane converges toward an opposing second surface of the gate electrode. According to another embodiment, the gate electrode of the nonvolatile memory cell includes a first sublayer and a second sublayer of a different width on the first sublayer.11-27-2008
20080303078NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND FABRICATION METHOD FOR THE SAME - The fabrication method for a nonvolatile semiconductor memory device having a memory cell area including memory cells and a peripheral circuit area adjacent to the memory cell area and including peripheral transistors, the method including the steps of: (1) forming a first active region in the memory cell area and a second active region in the peripheral circuit area in a substrate by forming isolation insulating films in the memory cell area and the peripheral circuit area so as to be away from a boundary therebetween; (2) forming a bottom insulating film and an intermediate charge trap film sequentially over the entire surface of the substrate; (3) removing a portion of the intermediate charge trap film formed in the peripheral circuit area using a first mask film; (4) forming a gate insulating film in the peripheral circuit area and also at least part of a top insulating film in the memory cell area; (5) forming a gate electrode film on the top insulating film and the gate insulating film; and (6) forming gate electrodes of memory cells and peripheral transistors by patterning the gate electrode film. The step (3) includes a step of aligning an end of the first mask film with the boundary in the substrate.12-11-2008
20120292686VERTICAL-TYPE NON-VOLATILE MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - In a semiconductor device, and a method of manufacturing thereof, the device includes a substrate of single-crystal semiconductor material extending in a horizontal direction and a plurality of interlayer dielectric layers on the substrate. A plurality of gate patterns are provided, each gate pattern being between a neighboring lower interlayer dielectric layer and a neighboring upper interlayer dielectric layer. A vertical channel of single-crystal semiconductor material extends in a vertical direction through the plurality of interlayer dielectric layers and the plurality of gate patterns, a gate insulating layer being between each gate pattern and the vertical channel that insulates the gate pattern from the vertical channel.11-22-2012
20080308857Systems and Methods for Self Convergence During Erase of a Non-Volatile Memory Device - A non-volatile memory device implements self-convergence during the normal erase cycle through control of physical aspects, such as thickness, width, area, etc., of the dielectric layers in the gate structure as well as of the overall gate structure. Self-convergence can also be aided during the normal erase cycle by ramping the erase voltage applied to the control gate during the erase cycle.12-18-2008
20080308859SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device including a semiconductor substrate, and a memory cell and a peripheral circuit provided on the semiconductor substrate, the memory cell having a first insulating film, a first electrode layer, a second insulating film, and a second electrode layer provided on the semiconductor substrate in order, and the peripheral circuit having the first insulating film, the first electrode layer, the second insulating film having an opening for the peripheral circuit, and the second electrode layer electrically connected to the first electrode layer through the opening for the peripheral circuit, wherein a thickness of the first electrode layer under the second insulating film of the peripheral circuit is thicker than a thickness of the first electrode layer of the memory cell.12-18-2008
20080308858SEMICONDUCTOR DEVICES AND ELECTRONIC SYSTEMS COMPRISING FLOATING GATE TRANSISTORS AND METHODS OF FORMING THE SAME - Semiconductor devices include one or more transistors having a floating gate and a control gate. In at least one embodiment, the floating gate comprises an intermediate portion extending between two end portions. The intermediate portion has an average cross-sectional area less than one or both of the end portions. In some embodiments, the intermediate portion may comprise a single nanowire. In additional embodiments, semiconductor devices have one or more transistors having a control gate and a floating gate in which a surface of the control gate opposes a lateral side surface of a floating gate that defines a recess in the floating gate. Electronic systems include such semiconductor devices. Methods of forming semiconductor devices include, for example, forming a floating gate having an intermediate portion extending between two end portions, and configuring the intermediate portion to have an average cross-sectional area less than one or both of the end portions.12-18-2008
20080308856Integrated Circuit Having a Fin Structure - Embodiments of the invention relate generally to a method for manufacturing an integrated circuit, a method for manufacturing a cell arrangement, an integrated circuit, a cell arrangement, and a memory module. In an embodiment of the invention, a method for manufacturing an integrated circuit having a cell arrangement is provided, including forming at least one semiconductor fin structure having an area for a plurality of fin field effect transistors, wherein the area of each fin field effect transistor includes a first region having a first fin structure width, a second region having a second fin structure width, wherein the second fin structure width is smaller than the first fin structure width. Furthermore, a plurality of charge storage regions are formed on or above the second regions of the semiconductor fin structure.12-18-2008
20090032859FINFET FLASH MEMORY DEVICE WITH AN EXTENDED FLOATING BACK GATE - A floating gate is formed on one side of the semiconductor fin on a floating gate dielectric. A control gate dielectric is formed on the opposite side of the semiconductor fin and on the floating gate. A gate conductor is formed on the control gate dielectric across the semiconductor fin. A gate spacer reaching above a gate cap layer and the control gate dielectric thereupon is formed by a conformal deposition of a dielectric layer and a reactive ion etch. The control gate dielectric and the material of the floating gate are removed from exposed portions of the semiconductor fin. The gate spacer is thereafter removed and source and drain regions are formed in the semiconductor fin. The overlap between the drain and the floating gate is extended by the thickness of the gate spacer, resulting in an enhanced efficiency in charge trapping in the floating gate.02-05-2009
20120292683MEMORY WITH DISCRETE STORAGE ELEMENTS - A method of making a non-volatile memory cell includes forming a plurality of discrete storage elements. A tensile dielectric layer is formed among the discrete storage elements and provides lateral tensile stress to the discrete storage elements. A gate is formed over the discrete storage elements.11-22-2012
20080290396SEMICONDUCTOR MEMORY - A semiconductor memory according to an aspect of this invention comprises a semiconductor substrate which includes a memory cell array region and an interconnect line region adjoining the memory cell array region, memory cells which are provided in the memory cell array region, contact plugs which are provided in the interconnect line region, and control gate lines which are provided so as to extend from the interconnect line region to the memory cell array region and which connect the contact plugs with the memory cells, wherein the control gate lines provided in the memory cell array region include metal silicide and the control gate lines provided in the interconnect line region include no metal silicide at any part of the interconnect line region.11-27-2008
20130119451INTERLAYER POLYSILICON DIELECTRIC CAP AND METHOD OF FORMING THEREOF - In some embodiments, an interlayer polysilicon dielectric cap disposed atop a substrate having a first floating gate, a second floating gate and an isolation layer disposed between the first floating gate and the second floating gate may include: a first nitrogen containing layer disposed atop an upper portion and sidewalls of the first floating gate and second floating gate; a first oxygen containing layer disposed atop the first nitrogen containing layer and an upper surface of the isolation layer; a second nitrogen containing layer disposed atop an upper portion and sidewalls of the first oxygen containing layer; and a second oxygen containing layer disposed atop the second nitrogen containing layer and an upper surface of the first oxygen containing layer.05-16-2013
20130119452SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF PRODUCING THE SAME - Provided is a semiconductor integrated circuit that uses a novel vertical MOS transistor that is free of interference between cells, that enables the short-channel effect to be minimized, that does not have hot electron injection, and that does not require the formation of shallow junction. Also provided is a method of producing the semiconductor integrated circuit. A memory cell 05-16-2013
20080265305INTEGRATED CIRCUITS WITH SUBSTRATE PROTRUSIONS, INCLUDING (BUT NOT LIMITED TO) FLOATING GATE MEMORIES - A floating gate memory cell's channel region (10-30-2008
20080265304Nonvolatile semiconductor device including a floating gate, method of manufacturing the same and associated systems - A memory device includes a first floating gate electrode on a substrate between adjacent isolation layers in the substrate, at least a portion of the first floating gate protruding above a portion of the adjacent isolation layers, a second floating gate electrode, electrically connected to the first floating gate electrode, on at least one of the adjacent isolation layers, a dielectric layer over the first and second floating gate electrodes, and a control gate over the dielectric layer and the first and second floating gate electrodes.10-30-2008
20100270607NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - It is made possible to provide a memory device that can be made very small in size and have a high capacity while being able to effectively suppress short-channel effects. A nonvolatile semiconductor memory device includes: a first insulating film formed on a semiconductor substrate; a semiconductor layer formed above the semiconductor substrate so that the first insulating film is interposed between the semiconductor layer and the semiconductor substrate; a NAND cell having a plurality of memory cell transistors connected in series, each of the memory cell transistors having a gate insulating film formed on the semiconductor layer, a floating gate formed on the gate insulating film, a second insulating film formed on the floating gate, and a control gate formed on the second insulating film; a source region having an impurity diffusion layer formed in one side of the NAND cell; and a drain region having a metal electrode formed in the other side of the NAND cell.10-28-2010
20100140679STACKED DUAL-GATE NMOS DEVICES WITH ANTIMONY SOURCE-DRAIN REGIONS AND METHODS FOR MANUFACTURING THEREOF - A three-dimensional memory structure includes multiple layers of memory devices, each memory device including a dual-gate device. A dual-gate device includes an active layer between a first gate structure and a second gate structure. Each gate structure is isolated from the active layer by a dielectric layer and is located above a semiconductor or channel region in the active layer defined by spaced-apart diffusion regions formed by implanting antimony ions. The antimony-doped diffusion regions are particularly suitable in stacked memory devices because antimony can be implanted and activated at a temperature less than 900° C. and show little movement of the implanted antimony ions even after numerous thermal steps in the manufacturing process. As a result, dual-gate devices in a stacked memory device with well-controlled channel lengths may be achieved.06-10-2010
20080258201SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A manufacturing method of a semiconductor memory device for manufacturing a first semiconductor device and a second semiconductor device wherein a cell array ratio is smaller than that of the first semiconductor device, said manufacturing method has forming the height of first element-isolating insulating films of first memory cell array region of said first semiconductor device so as to be a predetermined height, by performing etching treatment under predetermined conditions using a first etching mask having a first opening for exposing the entirety of said first memory cell array region, and forming the height of second element-isolating insulating films of second memory cell array region and part of peripheral circuit region of said second semiconductor device so as to be the predetermined height, by performing etching treatment under said predetermined conditions using a second etching mask having a second opening for exposing the entirety of said second memory cell array region and a third opening for exposing part of said peripheral circuit region.10-23-2008
20100270605NONVOLATILE MEMORY CELL AND METHOD FOR FABRICATING THE SAME - A nonvolatile memory cell and a method for fabricating the same can secure stable operational reliability as well as reducing a cell size. The nonvolatile memory cell includes a drain region formed in a substrate, a source region formed in the substrate to be separated from the drain region, a floating gate formed over the substrate between the drain region and the source region, a halo region formed in the substrate in a direction that the drain region is formed, a dielectric layer formed on sidewalls of the floating gate, and a control gate formed over the dielectric layer to overlap with at least one sidewall of the floating gate.10-28-2010
20090090956Flash Memory Device and Method of Manufacturing Flash Memory Device - Provided is a flash memory device and a method of manufacturing the same. In the method, a tunnel oxide layer pattern and a first polysilicon pattern are formed on a semiconductor substrate. A first dielectric layer including a first oxide layer, a first nitride layer, a second oxide layer, a second nitride layer and a third oxide layer is formed on the semiconductor substrate including the first polysilicon pattern. A second polysilicon pattern is formed on the dielectric layer pattern. The flash memory device includes a tunnel oxide layer pattern and a first polysilicon pattern on a semiconductor substrate; a dielectric layer on the first polysilicon pattern, including a first oxide layer pattern, a first nitride layer pattern, a second oxide layer pattern, a second nitride layer pattern and a third oxide layer pattern; and a second polysilicon pattern on the dielectric layer pattern.04-09-2009
20100140680Double Polysilicon Process for Non-Volatile Memory - A process flow for creating a non-volatile memory cell, the process flow including the steps of forming a doped well in a semiconducting portion of a substrate, forming a gate dielectric layer on top of the substrate, depositing a first polysilicon layer on top of the gate dielectric layer, patterning and etching the first polysilicon layer, selectively oxidizing the first polysilicon layer, implanting lightly-doped source/drain regions into the well, forming sidewall spacers adjacent the first polysilicon layer, implanting source/drain regions into the well, thereby forming a channel area, depositing a dielectric layer on top of the first polysilicon layer, depositing a second polysilicon layer on top of the dielectric layer, forming a masking layer on the second polysilicon layer, and etching both the second polysilicon layer and the dielectric layer using the masking layer.06-10-2010
20110266610MEMORY DEVICES HAVING REDUCED INTERFERENCE BETWEEN FLOATING GATES AND METHODS OF FABRICATING SUCH DEVICES - A memory array comprising transistors having isolated inter-gate dielectric regions with respect to one another. Transistors are formed such that each of the transistors in the array has a charge storage region such as a floating gate, a control gate and an inter-gate dielectric layer therebetween. The inter-gate dielectric layer for each transistor is isolated from the inter-gate dielectric of each of the other transistors in the array.11-03-2011
20090127611NON-VOLATILE MEMORY DEVICE AND MEMORY CARD AND SYSTEM INCLUDING THE SAME - A non-volatile memory device includes a semiconductor layer including source and drain regions and a channel region between the source and drain regions; a tunneling insulating layer on the channel region of the semiconductor layer; a charge storage layer on the tunneling insulating layer; a blocking insulating layer on the charge storage layer and including a first oxide layer with a first thickness, a high-k dielectric layer, and a second oxide layer with a second thickness different from the first thickness that are stacked sequentially on the charge storage layer; and a control gate on the blocking insulating layer.05-21-2009
20090026528Flash Memory Cell and Method of Manufacturing the Same and Programming/Erasing Reading Method of Flash Memory Cell - Disclosed is a flash memory cell and method of manufacturing the same, and programming/erasing/reading method thereof. The flash memory cell comprises a first tunnel oxide film formed at a given region of a semiconductor substrate, a first floating gate formed on the first tunnel oxide film, a second tunnel oxide film formed over the semiconductor substrate and along one sidewall of the first floating gate, a second floating gate isolated from the first floating gate while contacting the second tunnel oxide film, a dielectric film formed on the first floating gate and the second floating gate, a control gate formed on the dielectric film, a first junction region formed in the semiconductor substrate below one side of the second tunnel oxide film, and a second junction region formed in the semiconductor substrate below one side of the first tunnel oxide film. Therefore, the present invention can implement 2-bit cell or 3-bit cell of a high density using the existing process technology. Further, it can reduce the manufacture cost and implement a high-integrated flash memory cell that is advantageous than a conventional flash memory cell in view of charge storage/retention as well as programming time.01-29-2009
20090140315SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory device comprises: a plurality of transistors having a stacked-gate structure, each transistor including a semiconductor substrate, a gate insulator formed on the semiconductor substrate, a lower gate formed on the semiconductor substrate with the gate insulator interposed, an intergate insulator formed on the lower gate, and an upper gate formed and silicided on the lower gate with the intergate insulator interposed. A portion of the transistors has an aperture formed through the intergate insulator to connect the lower gate with the upper gate and further includes a silicide suppression region between the aperture and the gate insulator to suppress diffusion of metal atoms from the silicided upper gate.06-04-2009
20090014775SEMICONDUCTOR NONVOLATILE MEMORY DEVICE - An operation scheme for operating stably a semiconductor nonvolatile memory device is provided.01-15-2009
20120139024NONVOLATILE SEMICONDUCTOR MEMORY AND METHOD FOR MANUFACTURING THE SAME - In one embodiment, a nonvolatile semiconductor memory includes a memory cell array, a first silicon nitride film and a second silicon nitride film. The memory cell array includes NAND cell units. Each of the NAND cell units has memory cell transistors, a source-side select gate transistor and a drain-side select gate transistor. The source-side select gate transistors is disposed in such a manner as to face each other and the drain-side select gate transistors is disposed in such a manner as to face each other. The first silicon nitride film is present in a region between the source-side select gate transistors and is disposed at a position lowest from the upper surface of the semiconductor substrate. The second silicon nitride film is formed in a region between the drain-side select gate transistors and is disposed at a position lowest from the upper surface of the semiconductor substrate.06-07-2012
20090001444SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - This disclosure concerns a semiconductor memory device comprising a plurality of gate electrodes extending to a first direction; a reinforced insulation film extending to a second direction crossing the first direction, and connected to the adjacent gate electrodes; and an interlayer dielectric film provided between the adjacent gate electrodes, and having a void inside.01-01-2009
20120068248POWER SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device, includes an element unit including a vertical-type MOSFET, the vertical-type MOSFET in including a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a fourth semiconductor layer, a fifth semiconductor layer sequentially stacked in order, an impurity concentration of the second semiconductor layer being lower than the first semiconductor layer, an insulator covering inner surfaces of a plurality of trenches, the adjacent trenches being provided with a first interval in between, and a diode unit including basically with the units of the element unit, the adjacent trenches being provided with a second interval in between, the second interval being larger than the first interval.03-22-2012
20120068247THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE - Provided are three-dimensional semiconductor devices. The devices may include gap-fill insulating patterns configured to upwardly extend from a substrate and an electrode structure defined by sidewalls of the gap-fill insulating patterns. Vertical structures may be provided between adjacent ones of the gap-fill insulating patterns to penetrate the electrode structure, and the vertical structures may include first and second rows of the vertical structures. A separation pattern may be provided between the first and second rows of vertical structures and include a separation semiconductor layer. The separation pattern extends along a direction parallel to the first and second rows of vertical structures.03-22-2012
20120068246SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - In one embodiment, a method of manufacturing a semiconductor memory device is disclosed. The method can comprise forming a tunnel insulating film on a substrate, forming a charge storage layer including a conductor on the tunnel insulating film, forming an isolation trench which isolate the charge storage layer and the tunnel insulating film in the substrate, embedding an isolation insulating film in the isolation trench, removing a native oxide film which is formed on a surface of the charge storage layer, and forming an insulating film on a surface of the isolation insulating film and the surface of the charge storage layer. The process from the removing the native oxide film to the forming the insulating film carried out in a manufacture apparatus in which an oxygen concentration is controlled.03-22-2012
20090212341SEMITUBULAR METAL-OXIDE-SEMICONDUCTOR FIELD EFFECT TRANSISTOR - An epitaxial semiconductor layer or a stack of a silicon germanium alloy layer and an epitaxial strained silicon layer is formed on outer sidewalls of a porous silicon portion on a substrate. The porous silicon portion and any silicon germanium alloy material are removed and a semitubular epitaxial semiconductor structure in a three-walled configuration is formed. A semitubular field effect transistor comprising inner and outer gate dielectric layers, an inner gate electrode, an outer gate electrode, and source and drain regions is formed on the semitubular epitaxial semiconductor structure. The semitubular field effect transistor may operate as an SOI transistor with a tighter channel control through the inner and outer gate electrodes, or as a memory device storing electrical charges in the body region within the semitubular epitaxial semiconductor structure.08-27-2009
20090321808STRUCTURES, FABRICATION METHODS, AND DESIGN STRUCTURES FOR MULTIPLE BIT FLASH MEMORY CELLS - A semiconductor structure, a fabrication method, and a design structure of the same. The semiconductor structure includes (i) a semiconductor substrate which includes a top substrate surface perpendicular to the top substrate surface, (ii) a control gate electrode region and a first semiconductor body region on the semiconductor substrate, and (iii) a second semiconductor body region on the first semiconductor body region. The semiconductor structure further includes (i) a first gate dielectric region sandwiched between the first semiconductor body region and the control gate electrode region and (ii) a second gate dielectric region sandwiched between the second semiconductor body region and the control gate electrode region. The second semiconductor body region overlaps the first semiconductor body region in the reference direction. A first thickness of the first gate dielectric region is different from a second thickness of the second gate dielectric region.12-31-2009
20090039408NONVOLATILE SEMICONDUCTOR MEMORY AND MANUFACTURING METHOD THEREOF - A nonvolatile semiconductor memory of an aspect of the present invention comprises a first element isolation insulating film containing an organic substance which surrounds a first region, a memory cell arranged in the first region, a second element isolation insulating film containing an organic substance which surrounds a second region, a peripheral transistor arranged in the second region, and a first impurity layer which is provided in the semiconductor substrate along a side surface of the second element isolation insulating film.02-12-2009
20090039409SEMICONDUCTOR MEMORY DEVICE INCLUDING MULTI-LAYER GATE STRUCTURE - A semiconductor memory device includes a first select transistor, first stepped portion, and a first contact plug. The first select transistor is formed on a side of an upper surface of a substrate and has a first multi-layer gate. The first stepped portion is formed by etching the substrate adjacent to the first multi-layer gate of the first select transistor such that the first stepped portion forms a cavity in the upper surface of the substrate. The first contact plug is formed in the first stepped portion.02-12-2009
20090050951Semiconductor Device and Method of Manufacturing the Same - A method of manufacturing a semiconductor device according to an embodiment of the present invention includes depositing first to third mask layers above a substrate, processing the third mask layer, processing the second mask layer, slimming the second mask layer in an L/S section and out of the L/S section, peeling the third mask layer in the L/S section and out of the L/S section, forming spacers on sidewalls of the second mask layer in the L/S section and out of the L/S section, etching the second mask layer in the L/S section, under a condition that the second mask layer out of the L/S section Is covered with a resist, to remove the second mask layer in the L/S section while the second mask layer out of the L/S section remains, and processing the first mask layer by etching, using the spacers in the L/S section and out of the L/S section and the second mask layer out of the L/S section as a mask, the spacers in the L/S section and out of the L/S section and the second mask layer out of the L/S section being thinned by the etching.02-26-2009
20110220982NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND PROCESS OF MANUFACTURING THE SAME - In device isolation trenches, a first device-isolation insulator film is formed to have recesses thereon and a second device-isolation insulator film is formed in the recesses. The uppermost portions at both ends of the first device-isolation insulator film are located higher than the uppermost portions at both ends of the second device-isolation insulator film.09-15-2011
20090065843Semiconductor Constructions, Semiconductor Processing Methods, And Methods Of Forming Flash Memory Structures - Some embodiments include methods of reflecting ions off of vertical regions of photoresist mask sidewalls such that the ions impact foot regions along the bottom of the photoresist mask sidewalls and remove at least the majority of the foot regions. In some embodiments, trenches may be formed adjacent the photoresist mask sidewalls in a material that is beneath the photoresist mask. Another material may be formed to have projections extending into the trenches. Such projections may assist in anchoring said other material to the material that is beneath the photoresist mask. In some embodiments, the photoresist mask is utilized for patterning flash memory structures. Some embodiments include semiconductor constructions having materials anchored to underlying materials through fang-like projections.03-12-2009
20110220981NON-VOLATILE FINFET MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - Methods for fabricating an electronic device and electronic devices therefrom are provided. A method includes forming one or more masking layers on a semiconducting surface of a substrate and forming a plurality of dielectric isolation features and a plurality of fin-type projections using the masking layer. The method also includes processing the masking layers and the plurality of fin-type projections to provide an inverted T-shaped cross-section for the plurality of fin-type projections that includes a distal extension portion and a proximal base portion. The method further includes forming a plurality of bottom gate layers on the distal extension portion and forming a plurality of control gate layers on the plurality of dielectric isolation features and the plurality of bottom gate layers.09-15-2011
20090200596FABRICATION METHOD AND STRUCTURE FOR PROVIDING A RECESSED CHANNEL IN A NONVOLATILE MEMORY DEVICE - A method of fabricating a nonvolatile memory device includes preparing a semiconductor substrate including a cell array region. The method also includes forming a recessed region in the cell array region by etching the semiconductor substrate. The method includes etching at least a portion of the semiconductor substrate that partially includes the recessed region and forming first and second trenches that differ in depth, intersect the recessed region, and link with each other. The method includes forming a device isolation layer having rugged bottoms and defining an active region by filling an insulating material in the first and second trenches. The method includes forming a gate insulation layer on the semiconductor substrate of the active region including the recessed region and forming a gate structure on the gate insulation layer, to fill the recessed region, the gate structure including a floating gate, an intergate insulating pattern, and a control gate.08-13-2009
20090200595Nonvolatile semiconductor memory device and method of manufacturing the same - A nonvolatile semiconductor memory device has: a semiconductor substrate; a control gate and a floating gate that are formed side by side on a gate insulating film on a channel region in the semiconductor substrate; an erase gate facing an upper surface of the floating gate; a first device isolation structure having a first projecting portion; and a second device isolation structure having a second projecting portion. The first and second projecting portions have a first sloping surface and a second sloping surface, respectively. The first sloping surface and the second sloping surface face each other, and an interval between the first and second sloping surfaces becomes larger away from the semiconductor substrate. The floating gate is sandwiched between the first and second projecting portions and at least has a portion located on the semiconductor substrate side of the first and second sloping surfaces.08-13-2009
20090200594Nonvolatile semiconductor memory device and method of manufacturing the same - A nonvolatile semiconductor memory device has: a semiconductor substrate; a control gate and a floating gate that are formed side by side on a gate insulating film on a channel region in the semiconductor substrate; and an erase gate facing an upper surface of the floating gate. Side surfaces of the floating gate include a first side surface and a second side surface that face each other. An interval between the first side surface and the second side surface becomes narrower from the upper surface towards a side of the semiconductor substrate.08-13-2009
20090085089TWO-BIT FLASH MEMORY - A flash memory includes a substrate with a protrusion, a control gate, two floating gates, and a dielectric layer. The protrusion extends from a top face of the substrate. The control gate is formed on the protrusion of the substrate and extendedly covers opposite sidewalls of the protrusion. The floating gates are respectively formed on top of the protrusion and being on two opposite sides of the control gate. The dielectric layer is sandwiched the control gate and each of the two floating gates. Because of the arcuate control gate used in the flash memory, the controllability of the control gate is increased and the memory cell window is enhanced.04-02-2009
20090085092Non-volatile semiconductor memory device having an erasing gate - A non-volatile semiconductor memory device includes: a floating gate formed above the semiconductor substrate; an erasing gate formed above the floating gate; a control gate formed above a channel region of a surface layer of the semiconductor substrate at a position corresponding to one lateral side of the floating gate and the erasing gate; a diffusion layer formed on the semiconductor substrate at a position corresponding to another lateral side of the floating gate and the erasing gate; a plug formed above the diffusion layer, the plug coupled to the diffusion layer; a first silicide film formed on an upper surface of the erasing gate; and a second silicide film formed on an upper surface of the plug, in which a height of the upper surface of the plug is flush with/or lower than a height of the upper surface of the erasing gate.04-02-2009
20090085090Non-volatile semiconductor memory device having an erasing gate - A non-volatile semiconductor memory device includes a semiconductor substrate; a floating gate formed above the semiconductor substrate; an erasing gate formed above the floating gate; a control gate formed above a channel region of a surface layer of the semiconductor substrate at a position corresponding to one lateral side of the floating gate and the erasing gate; a first silicide film formed on an upper surface of the erasing gate; and a second silicide film formed on an upper surface of the control gate, in which a height of the upper surface of the control gate is flush with/or lower than a height of the upper surface of the erasing gate. With such a device structure, the distance between the upper surface of the erasing gate and the upper surface of the control gate is large, and hence the probability of occurrence of the silicide short between the first silicide film formed on the upper surface of the erasing gate and the second silicide film formed on the upper surface of the control gate may be extremely lowered. Thus, further high speed, operation, miniaturization, and the lower voltage operation of the non-volatile semiconductor memory device having an erasing gate may be achieved.04-02-2009
20090085093SEMICONDUCTOR DEVICES AND METHOD OF FABRICATING THE SAME - A semiconductor device and a fabricating method thereof are provided. The semiconductor device fabricating method includes forming a nitride layer pattern over a semiconductor substrate, forming a trench by etching the semiconductor substrate using the nitride layer pattern as a mask, forming a first insulation layer over an entire face of the semiconductor substrate, forming a device isolation pattern by polishing the first insulation layer to expose the nitride layer pattern, removing the nitride layer pattern, forming a first polysilicon layer over an entire face of the semiconductor substrate, etching the first polysilicon layer to expose the device isolation pattern and thus forming a floating gate electrode between the device isolation patterns, forming a second insulation layer covering the floating gate electrode, forming a second polysilicon layer over the insulation layer, and patterning the second polysilicon layer and the second insulation layer and thus forming a control gate electrode and a second insulation layer pattern.04-02-2009
20090085091Non-volatile semiconductor memory device having an erasing gate - A non-volatile semiconductor memory device includes a floating gate formed above a semiconductor substrate; an erasing gate formed above the floating gate; a control gate formed above a channel region of a surface layer of the semiconductor substrate at a position corresponding to one lateral side of the floating gate and the erasing gate; a first diffusion layer formed on the semiconductor substrate at a position corresponding to another lateral side of the floating gate and the erasing gate; a plug formed above the first diffusion layer, the plug coupled to the first diffusion layer; and a second diffusion layer formed on the semiconductor substrate at a position adjacent to the control gate. With such a device structure, the first diffusion layer and the plug connected thereto are formed in a self-alignment method, thereby contributing to a size reduction of the memory cells. Thus, further miniaturization of the non-volatile semiconductor memory device having an erasing gate may be achieved.04-02-2009
20120104482SEMICONDUCTOR DEVICES HAVING A CONTROL GATE ELECTRODE INCLUDING A METAL LAYER FILLING A GAP BETWEEN ADJACENT FLOATING GATES AND METHODS OF FABRICATING THE SAME - A semiconductor device includes a device isolation layer defining a plurality of active regions of a semiconductor substrate, floating gates and a control gate electrode in which the lowermost part of the electrode is constituted by a metal layer. The control gate electrode crosses over the active regions. The floating gates are disposed between the control gate electrode and the active regions. The tops of the floating gates are disposed at a level above the level of the top of the device isolation layer such that a gap is defined between adjacent ones of the floating gates. A region of the gap is filled with the metal layer of the control gate electrode.05-03-2012
20080296654Non-volatile memory device and method for fabricating the same - A non-volatile memory device and a method for fabricating the same are provided. The method includes: forming a gate structure on a substrate, the gate structure including a first insulation layer, a first electrode layer for a floating gate and a second insulation layer; forming a third insulation layer on the gate structure covering predetermined regions of the substrate adjacent to the gate structure; and forming a second electrode layer for a control gate on the third insulation layer disposed on sidewalls of the gate structure and the predetermined regions of the substrate.12-04-2008
20130214341SCALABLE GATE LOGIC NON-VOLATILE MEMORY CELLS AND ARRAYS - Scalable Gate Logic Non-Volatile Memory (SGLNVM) devices fabricated with the conventional CMOS process is disclosed. Floating gates of SGLNVM with the minimal length and width of the logic gate devices form floating gate Metal-Oxide-Semiconductor Field Effect Transistor. The floating gates with the minimal gate length extend over silicon active areas to capacitively couple control gates embedded in silicon substrate (well) through an insulation dielectric. The embedded control gate is formed by a shallow semiconductor type opposite to the type of the silicon substrate or well. Plurality of SGLNVM devices are configured into a NOR-type flash array where a pair of SGLNVM devices share a common source electrode connected to a common ground line with two drain electrodes connected to two separate bitlines. The pairs of the NOR-type SGLNVM cells are physically separated and electrically isolated by dummy floating gates to minimize cell sizes.08-22-2013
20120126304FLOATING GATE TYPE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A floating gate type semiconductor memory device includes a tunnel insulating layer, a floating gate formed on the tunnel insulating layer, a control gate electrode formed over the floating gates, a charge blocking layer formed between the floating gates and the control gate electrode, and a barrier layer formed in one or more areas of an area between the charge blocking layer and the control gate electrode and an area between the floating gate and the charge blocking layer and on an area corresponding to the sidewall of the floating gate.05-24-2012
20090250741Semiconductor device and gate structure having a composite dielectric layer and methods of manufacturing the same - A semiconductor device and/or gate structure having a composite dielectric layer and methods of manufacturing the same is provided. In the semiconductor device, gate structure, and methods provided, a first conductive layer may be formed on a substrate. A native oxide layer formed on the first conductive layer may be removed. A surface of the first conductive layer may be nitrided so that the surface may be altered into a nitride layer. A composite dielectric layer including the first and/or second dielectric layers may be formed on the nitride layer. A second conductive layer may be formed on the composite dielectric layer. The first dielectric layer may include a material having a higher dielectric constant. The second dielectric layer may be capable of suppressing crystallization of the first dielectric layer.10-08-2009
20090242957ATOMIC LAYER DEPOSITION PROCESSES FOR NON-VOLATILE MEMORY DEVICES - Embodiments of the invention provide memory devices and methods for forming memory devices. In one embodiment, a memory device is provided which includes a floating gate polysilicon layer disposed over source/drain regions of a substrate, a silicon oxynitride layer disposed over the floating gate polysilicon layer, a first aluminum oxide layer disposed over the silicon oxynitride layer, a hafnium silicon oxynitride layer disposed over the first aluminum oxide layer, a second aluminum oxide layer disposed over the hafnium silicon oxynitride layer, and a control gate polysilicon layer disposed over the second aluminum oxide layer. In another embodiment, a memory device is provided which includes a control gate polysilicon layer disposed over an inter-poly dielectric stack disposed over a silicon oxide layer disposed over the floating gate polysilicon layer. The inter-poly dielectric stack contains two silicon oxynitride layers separated by a silicon nitride layer.10-01-2009
20090242956TUNNEL DIELECTRICS FOR SEMICONDUCTOR DEVICES - Tunnel dielectrics for semiconductor devices are generally described. In one example, an apparatus includes a semiconductor substrate, a first tunnel dielectric having a first bandgap coupled to the semiconductor substrate, a second tunnel dielectric having a second bandgap coupled to the first tunnel dielectric, and a third tunnel dielectric having a third bandgap coupled to the second tunnel dielectric wherein the second bandgap is relatively smaller than the first bandgap and the third bandgap.10-01-2009
20090256190SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - According to an aspect of the present invention, there is provided a semiconductor device including: a semiconductor substrate; active areas with island-like shapes formed on the semiconductor substrate; an element isolation area surrounding the active areas and including an element isolation groove formed on the semiconductor substrate and an element isolation film embedded into the element isolation groove; gate insulating films each formed on corresponding one of the active areas and having a first end portion that overhangs from the corresponding active area onto the element isolation area at one side and a second end portion that overhangs from the corresponding active area onto the element isolation area at the other side, wherein an overhang of the first end portion has a different length from a length of an overhang of the second end portion.10-15-2009
20090256189TWO BIT U-SHAPED MEMORY STRUCTURE AND METHOD OF MAKING THE SAME - A memory structure includes: a substrate; a control gate positioned on the substrate; floating gates positioned at two sides of the control gate, wherein the floating gates have a U-shaped bottom embedded in the substrate; a first dielectric layer positioned between the control gate and the substrate; a second dielectric layer positioned between the U-shaped bottom of the floating gates and the substrate; a third dielectric layer positioned between the control gate and the floating gates; a local doping region positioned around the floating gates channel; and a source/drain doping region positioned in the substrate at a side of the floating gates.10-15-2009
20100155813SEMICONDUCTOR MEMORY DEVICE HAVING STACK GATE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor memory device includes select transistors, cell transistors, and cell units. The select transistors formed on a substrate and include first electrodes. The cell transistors include second electrodes with a charge storage layer and a control. The cell units including a plurality of the cell transistors connected together in series between the two select transistors. A distance between the first electrodes and a distance between the first electrodes which is adjacent to the second electrodes and adjacent second electrodes are each at least double a distance between second electrodes. A surface of the substrate between second electrodes is flush with the surface of the substrate between the first electrode and the adjacent second electrodes. The surface of the substrate between the first electrodes is positioned lower than the surface of the substrate between the first electrodes and the second electrodes.06-24-2010
20100155810MULTI-LAYER NONVOLATILE MEMORY DEVICES HAVING VERTICAL CHARGE STORAGE REGIONS - Some embodiments of the present invention provide nonvolatile memory devices including a plurality of intergate insulating patterns and a plurality of cell gate patterns that are alternately and vertically stacked on a substrate, an active pattern disposed on the substrate, the active pattern extending upwardly along sidewalls of the intergate insulating patterns and the cell gate patterns, a plurality of charge storage patterns disposed between the plurality of cell gate patterns and the active pattern, respectively, the plurality of the charge storage patterns being separated from each other, tunnel insulating patterns disposed between the plurality of cell gate patterns and the active pattern, respectively, and the tunnel insulating patterns extending to be directly connected to each other and a plurality of blocking insulating patterns disposed between the plurality of cell gate patterns and the plurality of charge storage patterns, respectively. A sidewall of the cell gate pattern may be recessed laterally so that an undercut region is defined and the charge storage pattern is disposed in the undercut region.06-24-2010
20100155811SEMICONDUCTOR DEVICE, METHOD OF FABRICATING THE SAME AND FLASH MEMORY DEVICE - A semiconductor device includes a semiconductor substrate, a gate formed over the semiconductor substrate, a source region formed in the semiconductor substrate at one side of the gate, a drain region formed in the semiconductor substrate at another side of the gate, and a channel region formed between the source region and the drain region, the channel region including a first channel region having a first threshold voltage and a second channel region having a second threshold voltage higher than the first threshold voltage. Accordingly, the semiconductor device has two channel regions having different threshold voltages.06-24-2010
20100155808SEMICONDUCTOR MEMORY, SEMICONDUCTOR MEMORY SYSTEM USING THE MEMORY, AND METHOD FOR MANUFACTURING QUANTUM DOT USED IN SEMICONDUCTOR MEMORY - A semiconductor memory has a composite floating structure in which quantum dots composed of Si and coated with a Si oxide thin film are deposited on an insulating film formed on a semiconductor substrate, quantum dots coated with a high-dielectric insulating film are deposited on the quantum dots, and quantum dots composed of Si and coated with a high-dielectric insulating film are further deposited. Each of the quantum dots includes a core layer and a clad layer which covers the core layer. The electron occupied level in the core layer is lower than that in the clad layer.06-24-2010
20100148238NON-VOLATILE MEMORY AND FABRICATING METHOD THEREOF - A non-volatile memory is formed on a substrate. The non-volatile memory includes an isolation structure, a floating gate, and a gate dielectric layer. The isolation structure is disposed in the substrate to define an active area. The floating gate is disposed on the substrate and crosses over the active area. The gate dielectric layer is disposed between the floating gate and the substrate. The floating gate includes a first region and a second region. An energy band of the second region is lower than an energy band of the first region, so that charges stored in the floating gate are away from an overlap region of the floating gate and the gate dielectric layer.06-17-2010
20100181611DIELECTRIC STRUCTURE IN NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A dielectric structure in a nonvolatile memory device and a method for fabricating the same are provided. The dielectric structure includes: a first oxide layer; a first high-k dielectric film formed on the first oxide layer, wherein the first high-k dielectric film includes one selected from materials with a dielectric constant of approximately 9 or higher and a compound of at least two of the materials; and a second oxide layer formed on the first high-k dielectric film.07-22-2010
20100155812SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A non-volatile memory of a semiconductor device has a tunnel insulation film provided on the active area; a floating gate electrode provided on the tunnel insulation film; a control gate electrode provided over the floating gate electrode; and an inter-electrode insulation film provided between the floating gate electrode and the control gate electrode, wherein, in a section of the non-volatile memory cell in a channel width direction, a dimension of a top face of the active area in the channel width direction is equal to or less than a dimension of a top face of the tunnel insulation film in the channel width direction, and the dimension of the top face of the tunnel insulation film in the channel width direction is less than a dimension of a bottom face of the floating gate electrode in the channel width direction.06-24-2010
20100155807Apparatus and methods for improved flash cell characteristics - Embodiments of an apparatus and methods for providing improved flash memory cell characteristics are generally described herein. Other embodiments may be described and claimed.06-24-2010
20100258850SEMICONDUCTOR INTEGRATED DEVICE - A semiconductor integrated device including a capacitor having a structure suitable for a larger capacitance is disclosed. A first electrode layer is electrically isolated by a first device isolation layer. An interelectrode insulating film is formed on the first electrode layer and the first device isolation layer and having an opening extending to the first electrode layer. A first electrode portion is formed on the interelectrode insulating film and electrically connected to the first electrode layer through the opening. A second electrode portion is formed on the interelectrode insulating film and electrically isolated from the first electrode layer. A third electrode portion is formed so as to penetrate through the interelectrode insulating film from a lower surface of the second electrode portion formed above the first device isolation layer, then to protrude inside the first device isolation layer, and to face side surfaces of the first electrode layer.10-14-2010
20100187592HIGH PERFORMANCE FLASH MEMORY DEVICES - Disclosed herein is a flash memory device comprising: a wafer; a gate oxide layer disposed upon the wafer; a floating gate disposed upon the gate oxide layer, the wafer, or a combination thereof; the floating gate comprising a flat floating gate portion and a generally rectangular floating gate portion disposed upon selected areas of the flat floating gate portion; a high K dielectric material disposed upon the floating gate; and a control gate disposed upon the high K dielectric material; wherein the high K dielectric material forms a zigzag pattern coupling the floating gate with the control gate.07-29-2010
20100176432Memory Cells, Methods Of Forming Dielectric Materials, And Methods Of Forming Memory Cells - Some embodiments include memory cells. The memory cells may include a tunnel dielectric material, a charge-retaining region over the tunnel dielectric material, crystalline ultra-high k dielectric material over the charge-retaining region, and a control gate material over the crystalline ultra-high k dielectric material. Additionally, the memory cells may include an amorphous region between the charge-retaining region and the crystalline ultra-high k dielectric material, and/or may include an amorphous region between the crystalline ultra-high k dielectric material and the control gate material. Some embodiments include methods of forming memory cells which contain an amorphous region between a charge-retaining region and a crystalline ultra-high k dielectric material, and/or which contain an amorphous region between a crystalline ultra-high k dielectric material and a control gate material.07-15-2010
20090078983NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A MONOS type non-volatile semiconductor memory device which is capable of electrically writing, erasing, reading and retaining data, the memory device including source/drain regions, a first gate insulating layer, a first charge trapping layer formed on the first gate insulating layer, a second gate insulating layer formed on the first charge trapping layer, and a controlling electrode formed on the second gate insulating layer. The first charge trapping layer includes an insulating film containing Al and O as major elements and having a defect pair formed of a complex of an interstitial O atom and a tetravalent cationic atom substituting for an Al atom, the insulating film also having electron unoccupied levels within the range of 2 eV-6 eV as measured from the valence band maximum of Al03-26-2009
20130214342NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURE THEREOF - A nonvolatile semiconductor storage device includes a semiconductor substrate including a protruding active area, a gate insulating layer on the active area, floating gate electrodes on the gate insulating layer, an insulating layer on the floating gate electrodes extending in a row direction, and a control gate electrode on the insulating layer extending in the row direction. The floating gate electrodes include a semiconductor layer on the gate insulating layer and a metal layer on the semiconductor layer. The width of the semiconductor layer of the floating gate electrodes in the row direction is narrower than the width of the metal layer in the row direction.08-22-2013
20130214343SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a gate insulating film formed on the semiconductor substrate; a floating gate formed on the gate insulating film; a control gate formed on the floating gate and has a side coplanar with a side of the floating gate; a tunnel diffusion layer facing a portion of the floating gate; and a tunnel window formed in a portion of the gate insulating film between the floating gate and the tunnel diffusion layer, the tunnel window being formed to be thinner than a remaining peripheral portion of the gate insulating film.08-22-2013
20100187594SEMICONDUCTOR MEMORY AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory includes a semiconductor substrate, a buried insulating film formed on a part of an upper surface of the semiconductor substrate, and a semiconductor layer formed on another part of the upper surface of the semiconductor substrate. Each of the memory cell transistors comprises a first-conductivity-type source region, a first-conductivity-type drain region, and a first-conductivity-type channel region arranged in the semiconductor layer in the column direction, and a gate portion formed on a side surface of the channel region in the row direction.07-29-2010
20100187593NAND FLASH MEMORY AND METHOD FOR MANUFACTURING THE SAME - A memory cell of NAND flash memory has a floating gate electrode taking a pillared shape formed on the first element region via a gate insulation film; diffusion layers formed in regions located on both sides of the floating gate electrode in the first element region; an IPD film formed on a top face of the floating gate electrode so as to extend over side faces of the floating gate electrode in a second direction perpendicular to the first direction; and a control gate electrode formed on the floating gate electrode and between adjacent floating gate electrodes via the IPD film so as to be continuous in the second direction. The IPD film is a low-k film.07-29-2010
20100213531NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A nonvolatile memory element which is provided with a floating gate electrode and a high withstand voltage transistor which is provided with a thick gate insulating film are formed over one substrate without increase in a driving voltage of the nonvolatile memory element. A stacked film of a first insulating film and a second insulating film is formed between an island-like semiconductor region and a floating gate electrode of the nonvolatile memory element and between an island-like semiconductor region and a gate electrode of the transistor. The first insulating film overlapping with the floating gate electrode is removed, and the insulating film between the island-like semiconductor region and the floating gate electrode is formed thinner than the gate insulating film of the transistor. The transistor includes a conductive film which is formed in the same layer as the floating gate electrode and a conductive film which is formed in the same layer as a control gate electrode, and these two conductive films are electrically connected to each other and function as the gate electrodes of the transistor.08-26-2010
20100176433SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a pair of select gate structures which are opposed to each other and which are formed in a select transistor formation area, each of the select gate structures including a gate insulating film formed on a semiconductor substrate and a gate electrode formed on the gate insulating film, and a pair of memory cell gate structure groups which are formed in a pair of memory cell formation areas between which the select transistor formation area is interposed and each of which has a plurality of memory cell gate structures arranged at the same pitch, the pair of select gate structures having sides which are opposed to each other, and at least the upper portion of each of the opposed sides of the select gate structures being inclined.07-15-2010
20100207189NON-VOLATILE MEMORY DEVICE WITH REDUCED WRITE-ERASE CYCLE TIME - A transistor includes a substrate having a surface, where a first region and a second region of the substrate are doped with a first type of dopant, and where a third region of the substrate between the first region and the second region is doped with a second type of dopant. An insulator layer is deposited above a portion of the surface, which includes the third region, and a gate layer is deposited above the insulator layer. An encapsulation layer encloses ends of the gate layer, thereby defining gaps between ends of the insulator layer and the encapsulation layer. These gaps have a depth relative to the ends of the gate layer, with one end of the insulator layer proximate to a boundary between the first region and the third region and another end of the insulator layer proximate to a boundary between the second region and the third region.08-19-2010
20110175154NONVOLATILE FLOATING GATE ANALOG MEMORY CELL - A nonvolatile floating gate analog memory cell (07-21-2011
20100230739NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND PROCESS OF MANUFACTURING THE SAME - In device isolation trenches, a first device-isolation insulator film is formed to have recesses thereon and a second device-isolation insulator film is formed in the recesses. The uppermost portions at both ends of the first device-isolation insulator film are located higher than the uppermost portions at both ends of the second device-isolation insulator film.09-16-2010
20100213532SEMICONDUCTOR DEVICES - A semiconductor device is provide, which includes a semiconductor region containing Ge as a major component, an insulating film formed on the semiconductor region, and a metallic film formed on the insulating film. At least a portion of the insulating film in contact with the semiconductor region is constituted by an oxide containing at least one rare-earth element M08-26-2010
20100213530Nonvolatile Memory Device and Method of Manufacturing the Same - A nonvolatile memory device comprises a gate insulating layer formed on a semiconductor substrate, gate patterns formed on the gate insulating layer, insulating layer spacers defining seams and being coupled together in spaces between the gate patterns, the insulating layer spacers being formed on sidewalls of the gate patterns, a height of the insulating layer spacers being lower than a height of the gate patterns, and an auxiliary layer filling the seams.08-26-2010
20100237398SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor storage device includes a semiconductor substrate, a first insulator, a laminated insulator including a second insulator having fixed charges more than those of the first insulator, a single-layer insulator, memory cells between the semiconductor substrate and the first insulator, each memory cells separated from an adjacent memory cell by a cavity portion and including a tunnel insulator, a charge accumulation layer, an insulator, and a control gate electrode, a first selection gate transistor between the semiconductor substrate and the first insulator, a second selection gate transistor between the semiconductor substrate and the first insulator, between one memory cell and the first selection gate transistor, and in contact with the laminated insulator on a first side face on a memory cell side thereof, and a high-voltage peripheral circuit transistor between the semiconductor substrate and the first insulator, and in contact with the single-layer insulator on a side face thereof.09-23-2010
20120126305Strained Semiconductor Device and Method of Making Same - In a method of making a semiconductor device, a gate dielectric is formed over the semiconductor body. A floating gate is formed over the gate dielectric, an insulating region over the floating gate, and a control gate over the insulating region. The gate dielectric, floating gate, insulating region, and control gate constitute a gate stack. A stress is caused in the gate stack, whereby the band gap of the gate dielectric is changed by the stress.05-24-2012
20110006355Novel Structure for Flash Memory Cells - A flash memory cell structure is provided. A semiconductor structure includes a semiconductor substrate, a floating gate overlying the semiconductor substrate, a word-line adjacent to the floating gate, an erase gate adjacent to a side of the floating gate opposite the word-line, a first sidewall disposed between the floating gate and the word-line, and a second sidewall disposed between the floating gate and the erase gate. The first sidewall has a first characteristic and the second sidewall has a second characteristic. The first characteristic is different from the second characteristic.01-13-2011
20100123178High ultraviolet light absorbance silicon oxynitride film for improved flash memory device performance - An ultraviolet light absorbent silicon oxynitride layer overlies a memory cell including a pair of source/drains, a gate insulator, a floating gate, a dielectric layer, and a control gate. A conductor is disposed through the silicon oxynitride layer for electrical connection to the control gate, and another conductor is disposed through the silicon oxynitride layer for electrical connection to a source/drain.05-20-2010
20100140681SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREFOR - An active region on a semiconductor substrate is electrically isolated by trench isolation. A structure of the trench isolation is constituted of a trench; a silicon oxide film formed on the inner wall of trench; an oxidation preventive film formed between silicon oxide film and semiconductor substrate; and a filling oxide film filling trench. Gate oxide film is formed by oxidation having a high capability by which radicals of at least one kind of hydrogen radicals and oxygen radicals are generated. Thereby, gate oxide film is formed so as to have a almost uniform thickness such that a thickness of a region directly above oxidation preventive film and a thickness of a region directly below gate electrode are almost the same is each other. According to the above procedure, there are obtained a semiconductor device having good transistor characteristics and a fabrication process therefor.06-10-2010
20110108906NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND ITS MANUFACTURING METHOD - In a non-volatile semiconductor memory device and a method for manufacturing the device, each memory cell and its select Tr have the same gate insulating film as a Vcc Tr. Further, the gate electrodes of a Vpp Tr and Vcc Tr are realized by the use of a first polysilicon layer. A material such as salicide or a metal, which differs from second polysilicon (which forms a control gate layer), may be provided on the first polysilicon layer. With the above features, a non-volatile semiconductor memory device can be manufactured by reduced steps and be operated at high speed in a reliable manner.05-12-2011
20090020802INTEGRATED SCHEME FOR FORMING INTER-POLY DIELECTRICS FOR NON-VOLATILE MEMORY DEVICES - Electronic devices and methods for forming electronic devices that allow for a reduction in device dimensions while also maintaining or reducing leakage current for non-volatile memory devices are provided. In one embodiment, a method of fabricating a non-volatile memory device is provided. The method comprises depositing a floating gate polysilicon layer on a substrate, forming a silicon oxide layer on the floating gate polysilicon layer, depositing a first silicon oxynitride layer on the silicon oxide layer, depositing a high-k dielectric material layer on the first silicon oxynitride layer, depositing a second silicon oxynitride on the high-k dielectric material, and forming a control gate polysilicon layer on the second silicon oxynitride layer. In one embodiment, the high-k dielectric material layer comprises hafnium silicon oxynitride.01-22-2009
20090020803AGING DEVICE - An aging device according to an embodiment of the present invention includes a semiconductor substrate, first and second diffusion layers provided in a first element region, a floating gate provided above a channel region between the first and second diffusion layers, and a control gate electrode provided beside the floating gate with an interval in the lateral direction. A coupling capacitance between the floating gate and the control gate electrode is larger than a coupling capacitance between the floating gate and the semiconductor substrate.01-22-2009
20090020800Semiconductor Device and Method of Making Same - A semiconductor device and method of making a semiconductor device are disclosed. A semiconductor body, a floating gate poly and a source/drain region are provided. A metal interconnect region with a control gate node is provided that capacitively couples to the floating gate poly.01-22-2009
20080230825NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - The invention relates to a nonvolatile semiconductor memory device including a semiconductor layer which has a source region, a drain region, and a channel forming region which is provided between the source region and the drain region; and a first insulating layer, a first gate electrode, a second insulating layer, and a second gate electrode which are layered over the semiconductor layer in that order. Part or all of the source and drain regions is formed using a metal silicide layer. The first gate electrode contains a noble gas element.09-25-2008
20110057244SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device, comprising: forming, on a semiconductor substrate a gate insulating film for a high-voltage transistor of a peripheral circuit; forming on the gate insulating film a gate electrode for the high-voltage transistor; removing the gate insulating film positioned on the semiconductor substrate on both side portions of the gate electrode; forming an impurity diffusion region in a surface of the semiconductor substrate; depositing a first silicon oxide film to extend over surfaces of the gate electrode and the impurity diffusion region; etching the first silicon oxide film to form a spacer such that the spacer is formed on a side wall portion of the gate electrode and also extends over the surface of the semiconductor substrate; and forming a silicon nitride film on a surface of the spacer.03-10-2011
20090289294SEMICONDUCTOR DEVICE - The semiconductor device according to the present invention includes: a semiconductor layer; a trench dug downward from the surface of the semiconductor layer; a source region formed on the surface layer portion of the semiconductor layer adjacently to a first side of the trench in a prescribed direction; a drain region formed on the surface layer portion of the semiconductor layer adjacently to a second side of the trench opposite to the first side in the prescribed direction; a first insulating film formed on the bottom surface and the side surface of the trench; a floating gate stacked on the first insulating film and opposed to the bottom surface and the side surface of the trench through the first insulating film; a second insulating film formed on the floating gate; and a control gate at least partially embedded in the trench so that the portion embedded in the trench is opposed to the floating gate through the second insulating film.11-26-2009
20090273015NON-VOLATILE MEMORY CELL - This document discloses non-volatile memory cells and methods of manufacturing the same. The non-volatile memory cells are self-aligned and have a reduced tunnel window area that is within an active region of a substrate. The tunnel window area can be reduced using mask openings without optical proximity correction that define tunnels having one or more curvatures.11-05-2009
20090114974Semiconductor device including a plurality of memory cells and method of manufacturing semiconductor device - A semiconductor device includes a semiconductor substrate, a plurality of memory cells, a plurality of bit lines, and a plurality of source lines. The memory cells are located in the semiconductor substrate. Each of the memory cells includes a trench provided in the semiconductor substrate, an oxide layer disposed on a sidewall of the trench, a tunnel oxide layer disposed at a bottom portion of the trench, a floating gate disposed in the trench so as to be surrounded by the oxide layer and the tunnel oxide layer, and an erasing electrode disposed on an opposing side of the tunnel oxide layer from the floating gate. The bit lines and the source lines are alternately arranged on the memory cells in parallel with each other.05-07-2009
20100219459METHOD FOR MANUFACTURING A NON-VOLATILE MEMORY, NON-VOLATILE MEMORY DEVICE, AND AN INTEGRATED CIRCUIT - A method of manufacturing a non-volatile memory device, including providing at least one control gate layer on a substrate. A passage may be created between the at least one control gate layer and the substrate. In the passage at least one filling layer may be provided. A floating gate structure including the filling layer may be formed, as well as a control gate structure including the at least one control gate layer, the control gate structure being in a stacked configuration with the floating gate structure.09-02-2010
20090140316SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor memory device includes an insulating film formed on a semiconductor substrate, a plurality of active areas formed on the insulating film from a semiconductor layer which is formed integrally with the substrate through openings of the insulating film, the active areas being formed by being divided into a striped shape by a plurality of trenches reaching an upper surface of the insulating film, the active areas having upper surfaces and sides respectively, a first gate insulating film formed so as to cover the upper surfaces and sides of the active areas, a charge trap layer having a face located on the first gate insulating film and confronting the upper surfaces and the sides of the active areas with the first gate insulating film being interposed therebetween, a second gate insulating film formed on the charge trap layer, and a gate electrode formed on the second gate insulating film.06-04-2009
20090039407Vertically integrated flash EPROM for greater density and lower cost - A nonvolative memory in the form of a vertical flash EPROM with high density and low cost. A vertical MOS transistor is formed in well etched into a semiconductor substrate, the substrate having source, body and drain regions formed by ion implantation. A thin gate oxide or oxide-nitride-oxide (ONO) layer is formed in the well and a self-aligned floating gate of polysilicon is formed over the gate oxide in the well to overlie the body region. An anisotropic etch is used to form the self aligned floating gate so as to remove all horizontal components and leave no portion of said floating gate extending beyond the perimeter of said well such that its lateral extents are determined by the anisotropic etch and not photolithography. L02-12-2009
20090039406SEMICONDUCTOR DEVICE MANUFACTURING METHOD, SEMICONDUCTOR DEVICE, PLASMA NITRIDING TREATMENT METHOD, CONTROL PROGRAM AND COMPUTER STORAGE MEDIUM - A nitrided region is formed on a surface of a polysilicon layer by a nitriding treatment wherein plasma of a processing gas is generated by introducing microwaves into a processing chamber by a planar antenna having a plurality of slots. Then, a CVD oxide film or the like is formed on the nitrided region and after patterning the polysilicon layer and the like after the prescribed shape, and then, a thermal oxide film is formed by thermal oxidation on exposed side walls and the like of the polysilicon layer by having the nitrided region as an oxidation barrier layer. Thus, generation of bird's beak can be suppressed in the process at a temperature lower than the temperature in a conventional process.02-12-2009
20080283898NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A non-volatile semiconductor memory device comprises a plurality of memory cells, each including a semiconductor substrate, a first insulating film formed on the semiconductor substrate, a floating gate formed on the semiconductor substrate with the inclusion of the first insulating film, a second insulating film formed on the floating gate, and a control gate formed on the floating gate with the inclusion of the second insulating film; an element isolation insulating film formed in the semiconductor substrate and extending in a gate-length direction to isolate between memory cells adjoining in a gate-width direction; and an air gap formed on the element isolation insulating film and between floating gates adjoining in the gate-width direction.11-20-2008
20090108324SEMICONDUCTOR FIN BASED NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATION THEREOF - A semiconductor structure and a method for fabricating the semiconductor structure include a semiconductor fin having a first side and a second side opposite the first side. A first gate dielectric and a charge storage layer are successively layered upon the first side of the semiconductor fin. A second gate dielectric and a gate electrode are layered upon the second side and the charge storage layer. The semiconductor structure comprises a nonvolatile semiconductor device.04-30-2009
20090072293Flash Memory and Method for Manufacturing the Same - Provided are a flash memory and a method for manufacturing the same. The flash memory includes a semiconductor substrate having a device isolation region and an active region; a stacked gate on the semiconductor substrate; an insulation layer covering the semiconductor substrate and the stacked gate; a drain contact penetrating the insulation layer on one side of the stacked gate; and a source line penetrating the insulation layer on an opposite side of the stacked gate.03-19-2009
20090072292SEMICONDUCTOR DEVICE AND METHOD OF MAKING SEMICONDUCTOR DEVICE - One or more embodiments are related to a semiconductor device, comprising: a high-K dielectric material; and a nitrogen-doped silicon material disposed over said high-k dielectric material.03-19-2009
20110108903Method for fabricating a flash memory cell utilizing a high-K metal gate process and related structure - According to one exemplary embodiment, a method for fabricating a flash memory cell in a semiconductor die includes forming a control gate stack overlying a floating gate stack in a memory region of a substrate, where the floating gate stack includes a floating gate overlying a portion of a dielectric one layer. The floating gate includes a portion of a metal one layer and the dielectric one layer includes a first high-k dielectric material. The control gate stack can include a control gate including a portion of a metal two layer, where the metal one layer can include a different metal than the metal two layer.05-12-2011
20110108904DUAL CONDUCTING FLOATING SPACER METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR (DCFS MOSFET) AND METHOD TO FABRICATE THE SAME - Dual Conducting Floating Spacer Metal Oxide Semiconductor Field Effect Transistors (DCFS MOSFETs) and methods for fabricate them using a process that is compatible with forming conventional MOSFETs are disclosed. A DCFS MOSFET can provide multi-bit storage in a single Non-Volatile Memory (NVM) memory cell. Like a typical MOSFET, a DCFS MOSFET includes a control gate electrode on top of a gate dielectric-silicon substrate, thereby forming a main channel of the device. Two electrically isolated conductor spacers are provided on both sides of the control gate and partially overlap two source/drain diffusion areas, which are doped to an opposite type to the conductivity type of the substrate semiconductor. The DCFS MOSFET becomes conducting when a voltage that exceeds a threshold is applied at the control gate and is coupled through the corresponding conducting floating spacer to generate an electrical field strong enough to invert the carriers near the source junction. By storing charge in the two independent conducting floating spacers, DCFS MOSFET can have two independent sets of threshold voltages associated with the source junctions.05-12-2011
20090108326SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device has a semiconductor substrate, a plurality of first conductive patterns, a second conductive pattern having a top surface of which stepwisely or gradually decreases in height in a direction from a side facing the first conductive pattern toward an opposite side, a first insulation film formed over the plurality of first conductive patterns and the second conductive pattern, and a third conductive pattern formed over the first insulation film.04-30-2009
20090108325SPLIT GATE DEVICE AND METHOD FOR FORMING - A method of making a semiconductor device on a semiconductor layer includes forming a select gate, a recess, a charge storage layer, and a control gate. The select gate is formed have a first sidewall over the semiconductor layer. The recess is formed in the semiconductor layer adjacent to the first sidewall of the select gate. The thin layer of charge storage material is formed in which a first portion of the thin layer of charge storage material is formed in the first recess and a second portion of the thin layer of charge storage material is formed along the first sidewall of the first select gate. The control gate is formed over the first portion of the thin layer of charge storage material. The result is a semiconductor device useful a memory cell.04-30-2009
20100295112SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device has a semiconductor substrate, a plurality of first insulating films formed on the semiconductor substrate with predetermined spacing therebetween, an element isolation region formed between the first insulating films in a first direction, a floating gate electrode comprising a first charge accumulation film formed on the first insulating film, a second charge accumulation film formed on the first charge accumulation film and having a width in a second direction orthogonal to the first direction smaller than the width of the first charge accumulation film, and a third charge accumulation film formed on the second charge accumulation film and having the width in the second direction larger than the width of the second charge accumulation film, a second insulating film formed on the second charge accumulation film and between the second charge accumulation film and the element isolation region, a third insulating film formed on the charge accumulation film and the element isolation region along the second direction, and a control gate electrode formed on the third insulating film.11-25-2010
20100295114Semiconductor Constructions - Some embodiments include formation of polymer spacers along sacrificial material, removal of the sacrificial material, and utilization of the polymer spacers as masks during fabrication of integrated circuitry. The polymer spacer masks may, for example, be utilized to pattern flash gates of a flash memory array. In some embodiments, the polymer is simultaneously formed across large sacrificial structures and small sacrificial structures. The polymer is thicker across the large sacrificial structures than across the small sacrificial structures, and such difference in thickness is utilized to fabricate high density structures and low-density structures with a single photomask.11-25-2010
20100295113SEMICONDUCTOR DEVICES COMPRISING A PLURALITY OF GATE STRUCTURES - Semiconductor devices including a plurality of gate structures disposed on a semiconductor substrate are provided. Each of the gate structures includes a tunnel dielectric layer, a floating gate, an inter-gate dielectric layer, a control gate, and a mask layer. Liners cover opposing sidewalls of adjacent floating gates. Spacers are disposed on the liners, the spacers protruding from opposing sidewalls of adjacent ones of the gate structures, and a top of each of the spacers is disposed below a top of a corresponding one of the gate structures. The liners define sidewalls of respective air gaps and the spacers define tops of the respective air gaps.11-25-2010
20100320524SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND A METHOD OF MANUFACTURING THE SAME - A semiconductor device having a nonvolatile memory cell which includes a semiconductor substrate, a first insulating film formed over the semiconductor substrate, a control electrode formed over the first insulating film, the first insulating film acting as a gate insulator for the control gate electrode, a second insulating film formed over the semiconductor substrate, and a memory gate electrode formed over the second insulating film and being adjacent to the control gate electrode, the second insulating film acting as a gate insulator for the memory gate electrode and featuring a non-conductive charge trap film, the control gate electrode having a different type conductivity than that of the memory gate electrode. The second insulating film may be a laminated multi-layered insulator featuring a non-conductive charge trap film as an intermediate layer therein which is made of a silicon nitride film.12-23-2010
20110001179SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - In a non-volatile memory in which charge is injected from a gate electrode to a charge accumulating layer, charge injection efficiency, charge retention characteristic and reliability are all improved compared with a conventional gate structure. In a nonvolatile memory which carries out write/erasure by changing the total charge amount by injecting electrons and holes into a silicon nitride film which makes up a charge accumulating layer, in order to highly efficiently carry out charge injection from a gate electrode, the gate electrode of a memory cell is made up of a two-layer film of a non-doped polysilicon layer and a metal material electrode layer.01-06-2011
20120132979Memory Devices And Methods Of Forming Memory Devices - Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures.05-31-2012
20120132977SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes an interface, a power supply, a driver, and a switch section. The interface includes a first MOSFET and converts a terminal switch signal of input serial data into parallel data. The first MOSFET is provided on the SOI substrate and has a back gate in a floating state. The power supply includes a second MOSFET and generates an ON potential higher than a potential of a power supply to be supplied to the interface. The second MOSFET is provided on the SOI substrate and has a back gate connected to a source. The driver includes a third MOSFET and outputs a control signal for controlling the ON potential to be in a high level according to the parallel data. The third MOSFET is provided on the SOI substrate and has a back gate connected to a source.05-31-2012
20120132978SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device with a nonvolatile memory is provided which has improved characteristics. The semiconductor device includes a control gate electrode, a memory gate electrode disposed adjacent to the control gate electrode, a first insulating film, and a second insulating film including therein a charge storing portion. Among these components, the memory gate electrode is formed of a silicon film including a first silicon region positioned over the second insulating film, and a second silicon region positioned above the first silicon region. The second silicon region contains p-type impurities, and the concentration of p-type impurities of the first silicon region is lower than that of the p-type impurities of the second silicon region.05-31-2012
20110018048Semiconductor device and method of manufacturing the same - According to an aspect of the invention, there is provided a semiconductor device comprising a semiconductor substrate, a first insulating layer formed on the semiconductor substrate, a first conductive layer formed as a floating gate on the first insulating layer, a second insulating layer formed as an interelectrode insulating film on the first conductive layer, and comprising three layers of a first film mainly including silicon and oxygen, a second film mainly including silicon and nitrogen, and a third film mainly including silicon and oxygen, wherein a silicon and nitrogen composition ratio of the second film is in a state in which the silicon is in excess of a stoichiometric composition, and a second conductive layer formed as a control gate on the second insulating film.01-27-2011
20120032246NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A nonvolatile semiconductor memory device according to an embodiment includes a semiconductor substrate, a memory cell transistor formed in a memory cell region, and a field-effect transistor formed in a peripheral circuit region. The memory cell transistor includes: a floating gate electrode; a first inter-electrode insulating film; and a control gate electrode. The field-effect transistor includes: a lower gate electrode; a second inter-electrode insulating film having an opening; and an upper gate electrode electrically connected to the lower gate electrode via the opening. The control gate electrode and the upper gate electrode are formed by a plurality of conductive films that are stacked. The control gate electrode and the upper gate electrode include a barrier film formed in one of interfaces between the stacked conductive films and configured to suppress diffusion of metal atoms. The control gate electrode and the upper gate electrode have a part that is silicided.02-09-2012
20110042737METHOD OF FABRICATING A NONVOLATILE SEMICONDUCTOR MEMORY - A nonvolatile semiconductor memory fabrication method including forming a first insulating film and a floating gate electrode material on a semiconductor substrate; forming a gate insulating film and a floating gate electrode by etching the first insulating film and the floating gate electrode material, respectively, and forming a groove for an element isolation region by etching the semiconductor substrate; and forming an element region and the element isolation region by burying a second insulating film in the groove and planarizing the second insulating film.02-24-2011
20110042736SEMICONDUCTOR MEMORY HAVING BOTH VOLATILE AND NON-VOLATILE FUNCTIONALITY AND METHOD OF OPERATING - Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor memory cell includes a fin structure extending from a substrate, the fin structure including a floating substrate region having a first conductivity type configured to store data as volatile memory, first and second regions interfacing with the floating substrate region, each of the first and second regions having a second conductivity type; first and second floating gates or trapping layers positioned adjacent opposite sides of the floating substrate region; a first insulating layer positioned between the floating substrate region and the floating gates or trapping layers, the floating gates or trapping layers being configured to receive transfer of data stored by the volatile memory and store the data as nonvolatile memory in the floating gates or trapping layers upon interruption of power to the memory cell; a control gate wrapped around the floating gates or trapping layers and the floating substrate region; and a second insulating layer positioned between the floating gates or trapping layers and the control gate; the substrate including an isolation layer that isolates the floating substrate region from a portion of the substrate below the isolation layer.02-24-2011
20110115012METHOD FOR FABRICATING AN ENLARGED OXIDE-NITRIDE-OXIDE STRUCTURE FOR NAND FLASH MEMORY SEMICONDUCTOR DEVICES - A method of processing a flash memory device provides a semiconductor substrate including a surface region and forming a gate dielectric layer overlying the surface region. The method forms a floating gate layer having a thickness and including a first floating gate structure overlying a first portion of the gate dielectric layer and a second floating gate structure overlying a second portion of the gate dielectric layer. The method forms a trench region interposed between the first and second floating gate structures and extending through the entire thickness and through a portion of the surface region into a depth of the substrate. The method fills the entire depth of the trench region in the substrate and a portion of the trench region over the substrate using a dielectric fill material. The method forms an oxide on nitride on oxide (ONO) layer overlying the first and second floating gate structures and the dielectric material and a control gate overlying the ONO layer.05-19-2011
20110084328NON-VOLATILE MEMORY HAVING NANO CRYSTALLINE SILICON HILLLOCKS FLOATING GATE - A method for making a non-volatile memory device provides a semiconductor substrate including a surface region and a tunnel dielectric layer overlying the surface region. Preferably the tunnel dielectric layer is a high-K dielectric, characterized by a dielectric constant higher than 3.9. The method forms a source region within a first portion and a drain region within a second portion of the semiconductor substrate. The method includes forming a first and second nanocrystalline silicon structures overlying the first and second portions between the source region and the drain region to form a first and second floating gate structures while maintaining a separation between the first and second nanocrystalline silicon structures. The method includes forming a second dielectric layer overlying the first and second floating gate structures. The method also includes forming a control gate structure overlying the first and second floating gate structures.04-14-2011
20100163956EEPROM DEVICE AND METHOD OF MANUFACTURING THE SAME - An EEPROM device may have, at the region where the control gate is formed, a gate oxide layer having a relatively smaller thickness than the gate oxide layer of the tunneling region by removing the gate oxide layer, at a predetermined thickness, at the region where the control gate is formed. Thus, integration of an EEPROM device may be maximized as a result of minimizing the area of the control gate.07-01-2010
20100163955SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device is provided including: a spacer shaped floating gate formed on a semiconductor substrate; a dielectric layer spacer formed at one side wall of the floating gate; a third oxide layer formed over the floating gate and the dielectric layer; and a control gate formed over the third oxide layer. According to an embodiment, the structure of the floating gate in a plate shape whose center is concave is improved to the spacer structure, making it possible to minimize the size of the semiconductor memory device and to improve density. Moreover, a LOCOS process can be excluded while forming the floating gate, making it possible to more efficiently fabricate the device.07-01-2010
20090078984SEMICONDUCTOR APPARATUS AND METHOD FOR MANUFACTURING THE SAME - According to an aspect of the present invention, there is provided a semiconductor apparatus including: a semiconductor substrate; a gate dielectric film that is formed on the semiconductor substrate; a floating gate electrode film that is formed on the gate dielectric film; an inter-gate dielectric film that includes: a metal oxide film that is formed on the floating gate electrode film; an electron trap film that is formed on the metal oxide film; and a silicon oxide film that is formed on the electron trap film; and a control gate electrode film that is formed on the inter-gate dielectric film.03-26-2009
20110241095NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - In one embodiment, a semiconductor memory device, including a memory cell having a floating gate electrode above a semiconductor substrate via a first gate insulator and a control gate electrode above the floating gate electrode via a first inter-gate insulator, a contact electrode having a bottom electrode contacted to an upper surface of the semiconductor substrate, top electrodes via a second inter-gate insulators on both edge portions of the bottom electrode and a plug electrode between the top electrodes, the plug electrode contacted to an upper surface of the bottom electrode.10-06-2011
20090218612MEMORY UTILIZING OXIDE-CONDUCTOR NANOLAMINATES - Structures, systems and methods for floating gate transistors utilizing oxide-conductor nanolaminates are provided. One floating gate transistor embodiment includes a first source/drain region, a second source/drain region, and a channel region therebetween. A floating gate is separated from the channel region by a first gate oxide. The floating gate includes oxide-conductor nanolaminate layers to trap charge in potential wells formed by different electron affinities of the oxide-conductor nanolaminate layers.09-03-2009
20100038697NON-VOLATILE TWO-TRANSISTOR PROGRAMMABLE LOGIC CELL AND ARRAY LAYOUT - A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.02-18-2010
20100038696Semiconductor Device and Method for Making Same - One or more embodiments, relate to a field effect transistor, comprising: a substrate; a gate stack disposed over the substrate, the gate stack comprising a gate electrode overlying a gate dielectric; and a sidewall spacer may be disposed over the substrate and laterally disposed from the gate stack, the spacer comprising a polysilicon material.02-18-2010
20100065901Electrically programmable and erasable memory device and method of fabrication thereof - The present memory device includes a substrate, a tunneling layer over the substrate, a floating gate over the tunneling layer, a dielectric over the floating gate and including silicon oxynitride, and a control gate over the dielectric. A method for fabricating such a memory device is also provided, including various approaches for forming the silicon oxynitride.03-18-2010
20110101438Nonvolatile Memory Devices Having Gate Structures Therein with Improved Blocking Layers - Nonvolatile memory devices include a tunnel insulating layer on a substrate and a charge storing layer on the tunnel insulating layer. A charge transfer blocking layer is provided on the charge storing layer. The charge transfer blocking layer is formed as a composite of multiple layers, which include a first oxide layer having a thickness of about 1 Å to about 10 Å. This first oxide layer is formed directly on the charge storing layer. The charge transfer blocking layer includes a first dielectric layer on the first oxide layer. The charge transfer blocking layer also includes a second oxide layer on the first dielectric layer and a second dielectric layer on the second oxide layer. The first and second dielectric layers have a higher dielectric constant relative to the first and second oxide layers, respectively. The memory cell includes an electrically conductive electrode on the charge transfer blocking layer.05-05-2011
20110073928Non-Volatile Memory Devices Having Semiconductor Barrier Patterns and Methods of Forming Such Devices - Provided are a non-volatile memory device and a method of forming the same. The non-volatile memory device includes: a tunnel insulation layer on a substrate; a floating gate on the tunnel insulation layer; a blocking insulation layer on the floating gate; a first barrier pattern, between the top of the floating gate and the blocking insulation layer, having a higher conduction band energy level than the floating gate; and a control gate on the blocking insulation layer.03-31-2011
20100127318BICMOS INTEGRATION OF MULTIPLE-TIMES-PROGRAMMABLE NON-VOLATILE MEMORIES - A BiCMOS substrate includes a bipolar area having a buried carrier layer, and a deep trench isolation (DTI) trench extending into the buried carrier layer to form a surface well implant above a buried well implant within the DTI trench, the buried well implant being the buried carrier layer portion within the DTI trench. A floating gate is disposed on the carrier well. Optionally, a high voltage control gate is formed of a stack of the buried well implant and the surface well implant within the DTI trench. Optionally, a poly layer formed of a bipolar process base poly layer is disposed on the floating gate. Optionally, a shallow well isolation region is formed on the substrate, a floating gate is disposed on the shallow well region, and an overlaying control gate, formed of a bipolar process base poly, is disposed above the floating gate.05-27-2010
20110101439INTERCONNECTION STRUCTURES FOR SEMICONDCUTOR DEVICES - An interconnection structure for a semiconductor device includes an inter-level insulation layer disposed on a semiconductor substrate. First contact constructions penetrate the inter-level insulation layer. Second contact constructions penetrate the inter-level insulation layer. Metal interconnections connect the first contact constructions to the second contact constructions on the inter-level insulation layer. The first contact constructions include first and second plugs stacked in sequence and the second contact constructions include the second plug.05-05-2011
20110057245NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND A MANUFACTURING METHOD THEREOF - A nonvolatile semiconductor memory device according to an exemplary embodiment of the present invention including, a first gate electrode formed above a semiconductor substrate via a first insulating film, having a projecting part which projects in upper direction with a certain width; a second gate electrode formed beside a side surface of the first gate electrode via a second insulating film; two side walls having insulation properties formed on a side surface of the second gate electrode and a side surface of the projecting part respectively; and a silicide layer formed on an upper surface of the projecting part and a part of a surface of the second gate electrode, wherein a width of the projecting part is smaller than a width of the first gate electrode below the projecting part.03-10-2011
20090026527METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - According to an aspect of the present invention, there is provided a method for manufacturing a semiconductor device including: sequentially forming a first insulating film, a first electrode film, a second insulating film, and a second electrode film on a substrate; forming a groove that separates the second electrode film, the second insulating film and the first electrode film; forming an insulating film inside the groove so that an upper surface thereof is positioned between upper surfaces of the second electrode film and the second insulating film; forming an overhung portion on the second electrode film so as to overhang on the insulating film by performing a selective growth process; and forming a low resistance layer at the overhung portion and the second electrode film by performing an alloying process.01-29-2009
20090026525MEMORY AND METHOD FOR FABRICATING THE SAME - A method for fabricating a memory is provided. A tunneling dielectric layer, a first conductive layer, and a mask layer are formed on a substrate. The mask layer, the first conductive layer, the tunneling dielectric layer, and the substrate are patterned to form trenches in the substrate. A passivation layer and isolation structures are formed in sequence to fill the trenches, and the etching rate of the isolation structures is greater than that of the passivation layer. After the mask layer is removed, a second conductive layer is formed on the first conductive layer. Portions of the isolation structures are removed to expose the sidewalls of the first and the second conductive layers. Further, a third conductive layer is formed on the exposed sidewalls of the first and the second conductive layers. An inter-gate dielectric layer and a control gate are formed on the substrate.01-29-2009
20110254072CHARGE STORAGE STRUCTURES AND METHODS - Methods, devices, and systems associated with charge storage structures in semiconductor devices are described herein. In one or more embodiments, a method of forming nanodots includes forming at least a portion of a charge storage structure over a material by reacting a single-source precursor and a reactant, where the single-source precursor includes a metal and a semiconductor.10-20-2011
20100301403SEMICONDUCTOR DEVICE WITH MULTIPLE GATES AND DOPED REGIONS AND METHOD OF FORMING - A semiconductor device includes a source region within a semiconductor substrate, a drain region within the semiconductor substrate, a control gate over the semiconductor substrate and between the source region and the drain region, a first gate between the control gate and the drain region, and a first doped region within the semiconductor region and between the control gate and the first gate. The method of forming the semiconductor device may include depositing an electrode material over the semiconductor substrate, patterning the electrode material to form a control gate and a first gate, implanting a first doped region within the semiconductor substrate between the control gate and the first gate while using the control gate and the first gate as a mask, and implanting a source region within the semiconductor substrate.12-02-2010
20110248329METHOD OF MANUFACTURING A NON-VOLATILE NAND MEMORY SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit device includes first, second gate electrodes, first, second diffusion layers, contact electrodes electrically connected to the first diffusion layers, a first insulating film which has concave portions between the first and second gate electrodes and does not contain nitrogen as a main component, a second insulating film which is formed on the first insulating film and does not contain nitrogen as a main component, and a third insulating film formed on the first diffusion layers, first gate electrodes, second diffusion layers and second gate electrodes with the second insulating film disposed therebetween in a partial region. The second insulating film is formed to fill the concave portions and a portion between the first and second gate electrodes has a multi-layered structure containing at least the first and second insulating films.10-13-2011
20100301404SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREOF - An object of the present invention is to provide a semiconductor device having a nonvolatile memory cell of a high operation speed and a high rewrite cycle and a nonvolatile memory cell of high reliability. In a split gate type nonvolatile memory in which memory gate electrodes are formed in the shape of sidewalls of control gate electrodes, it is possible to produce a memory chip having a memory of a high operation speed and a high rewrite cycle and a memory of high reliability at a low cost by jointly loading memory cells having different memory gate lengths in an identical chip.12-02-2010
20110248330METHOD OF MANUFACTURING A NON-VOLATILE NAND MEMORY SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit device includes first, second gate electrodes, first, second diffusion layers, contact electrodes electrically connected to the first diffusion layers, a first insulating film which has concave portions between the first and second gate electrodes and does not contain nitrogen as a main component, a second insulating film which is formed on the first insulating film and does not contain nitrogen as a main component, and a third insulating film formed on the first diffusion layers, first gate electrodes, second diffusion layers and second gate electrodes with the second insulating film disposed therebetween in a partial region. The second insulating film is formed to fill the concave portions and a portion between the first and second gate electrodes has a multi-layered structure containing at least the first and second insulating films.10-13-2011
20100258851NANOCRYSTAL MEMORIES AND METHODS OF FORMING THE SAME - Nanocrystal memories and methods of making the same are disclosed. In one embodiment, a memory device comprises a substrate, a tunneling oxide, a silicide nanocrystal floating gate, and a control oxide. The tunneling oxide is positioned upon a first surface of the substrate, the silicide nanocrystal floating gate is positioned upon the tunneling oxide, and the control oxide positioned upon the nanocrystal floating gate.10-14-2010
20110163367Semiconductor Devices Comprising a Plurality of Gate Structures - Semiconductor devices are provided. The semiconductor devices may include a plurality of gate structures disposed on a semiconductor substrate, each of the gate structures including a floating gate, an inter-gate dielectric layer, and a control gate. The semiconductor devices may also include liners on opposing sidewalls of adjacent ones of the gate structures. The liners may define a gap. A first width of the gap may be less than a second width of the gap.07-07-2011
20090001446FLASH MEMORY DEVICE AND METHODS FOR FABRICATING THE SAME - A method of fabricating a flash memory device includes forming a stack electrode on a semiconductor substrate; forming a side spacer on a side wall of the stack electrode; forming a photo-resist film pattern with a predetermined thickness on the side wall of the side spacer; and forming a source/drain junction on the semiconductor substrate through ion implant using the photo-resist film as a mask for ion implant.01-01-2009
20090001445Non-Volatile Memory Device and Method of Fabricating the Same - Provided are a non-volatile memory device and a method of fabricating the same. The non-volatile memory device comprises: a control gate region formed by doping a semiconductor substrate with second impurities; an electron injection region formed by doping the semiconductor substrate with first impurities, where a top surface of the electron injection region includes a tip portion at an edge; a floating gate electrode covering at least a portion of the control gate region and the tip portion of the electron injection region; a first tunnel oxide layer interposed between the floating gate electrode and the control gate region; a second tunnel oxide layer interposed between the floating gate electrode and the electron injection region; a trench surrounding the electron injection region in the semiconductor substrate; and a device isolation layer pattern filled in the trench.01-01-2009
20090001443NON-VOLATILE MEMORY CELL WITH MULTI-LAYER BLOCKING DIELECTRIC - Disclosed is a non-volatile memory cell. The non-volatile memory cell includes a substrate having an active area. A bottom dielectric layer is disposed over the active area of the substrate which provides tunneling migration to the charge carriers towards the active area. A charge storage node is disposed above the bottom dielectric layer. Further, the non-volatile memory cell includes a plurality of top dielectric layers disposed above the charge storage node. Each of the plurality of top dielectric layers can be tuned with a set of attributes for reducing a leakage current through the plurality of top dielectric layers. Over the plurality of top dielectric layers, a control gate is disposed.01-01-2009
20090309151Semiconductor Constructions - Some embodiments include methods of forming flash memory cells and semiconductor constructions, and some embodiments include semiconductor constructions. Some embodiments may include a method in which a semiconductor substrate is provided to have a plurality of active area locations. Floating gates are formed over the active area locations, with the floating gates having widths that are entirely sub-lithographic. Adjacent floating gates are spaced from one another by gaps. Dielectric material and control gate material are formed over the floating gates and within the gaps. Some embodiments may include a construction in which a pair of adjacent floating gates are over a pair of adjacent active areas, with the floating gates being spaced from one another by a distance which is greater than a distance that the active areas are spaced from one another.12-17-2009
20090230453NON-VOLATILE SEMICONDUCTOR MEMORY AND METHOD OF MAKING SAME, AND SEMICONDUCTOR DEVICE AND METHOD OF MAKING DEVICE - A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.09-17-2009
20080315286SEMICONDUCTOR DEVICE - A decease in reliability of a memory element having a floating gate is suppressed. The invention relates to a semiconductor device having an island-like semiconductor film, which is formed over an insulating surface and includes a channel formation region and a high-concentration impurity region, a tunneling insulating film formed over the island-like semiconductor film, a floating gate formed over the tunneling insulating film, a gate insulating film formed over the floating gate, a control gate formed over the gate insulating film, and a first insulating film formed between the tunneling insulating film and the floating gate. The first insulating film is formed of an oxide film of the material of the floating gate, so that the material of the floating gate is prevented from diffusing into the tunneling insulating film.12-25-2008
20080315285Non-volatile memory devices and methods of fabricating the same - Non-volatile memory devices and methods of fabricating the same are provided. The non-volatile memory devices may include a semiconductor substrate having a pair of sidewall channel regions extending from the semiconductor substrate and opposite to each other, and a floating gate electrode between the pair of sidewall channel regions and protruding from the semiconductor substrate. A control gate electrode may be formed on the semiconductor substrate and a portion of the floating gate electrode.12-25-2008
20080315284Flash memory structure and method of making the same - A flash memory cell includes a substrate, a T-shaped control gate disposed above the substrate, a floating gate embedded in a lower recess of the T-shaped control gate, a dielectric layer between the T-shaped control gate and the floating gate; a cap layer above the T-shaped control gate, a control gate oxide between the T-shaped control gate and the substrate, a floating gate oxide between the floating gate and the substrate, a liner covering the cap layer and the floating gate, and a source/drain region adjacent to the floating gate. The floating gate has a vertical wall surface that is coplanar with one side of the dielectric layer.12-25-2008
20090001447SEMICONDUCTOR DEVICE WITH DUMMY ELECTRODE - A semiconductor device includes a gate electrode having a straight portion, a dummy electrode located at a point on the extension of the straight portion, a stopper insulating film, a sidewall insulating film, an interlayer insulating film, and a linear contact portion extending, when viewed from above, parallel to the straight portion. The longer side of the rectangle defined by the linear contact portion is, when viewed from above, located beyond the sidewall insulating film and within the top region of the gate electrode and the dummy electrode. A gap G between the gate electrode and the dummy electrode appearing, when viewed from above, in the linear contact portion is filled with the sidewall insulating film such that the semiconductor substrate is not exposed.01-01-2009
20110156125NONVOLATILE SEMICONDUCTOR DEVICE INCLUDING A FLOATING GATE AND ASSOCIATED SYSTEMS - A memory device includes a first floating gate electrode on a substrate between adjacent isolation layers in the substrate, at least a portion of the first floating gate protruding above a portion of the adjacent isolation layers, a second floating gate electrode, electrically connected to the first floating gate electrode, on at least one of the adjacent isolation layers, a dielectric layer over the first and second floating gate electrodes, and a control gate over the dielectric layer and the first and second floating gate electrodes.06-30-2011
20090278191NONVOLATILE SEMICONDUCTOR MEMORY DEVICE IN WHICH DECREASE IN COUPLING RATIO OF MEMORY CELLS IS SUPPRESSED - A first insulation film is formed on a semiconductor substrate. A first gate electrode is formed on the first insulation film. A second insulation film is formed on an upper surface and a side surface of the first gate electrode. A second gate electrode is formed on the second insulation film. The entirety of that part of the second gate electrode, which is located above the second insulation film formed on the upper surface of the first gate electrode, is a silicide layer. At least a portion of that part of the second gate electrode, which is located on the side surface of the first gate electrode, is a silicon layer.11-12-2009
20100308394SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD - A semiconductor storage device includes a semiconductor substrate having a first region of a first conductivity type in between respective regions of an opposite conductivity type, at least the first region being covered by a first dielectric layer, a polysilicon floating gate placed on the first dielectric layer over the first region, said floating gate being surrounded by an insulating material; and a metal control gate structure adjacent to the polysilicon floating gate, the metal control gate structure being capacitively coupled to said floating gate. A method of manufacturing such a semiconductor storage device is also disclosed.12-09-2010
20080251833Integrated circuits and methods of manufacture - In various embodiments of the invention, integrated circuits and methods of manufacturing integrated circuits are provided. In an embodiment of the invention, an integrated circuit having at least one memory cell is provided. The memory cell includes a dielectric layer disposed above a charge storage region, a word line disposed above the dielectric layer, and a control line disposed at least partially above at least one sidewall of the dielectric layer.10-16-2008
20080251834NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND ITS MANUFACTURING METHOD - In a non-volatile semiconductor memory device and a method for manufacturing the device, each memory cell and its select Tr have the same gate insulating film as a Vcc Tr. Further, the gate electrodes of a Vpp Tr and Vcc Tr are realized by the use of a first polysilicon layer. A material such as salicide or a metal, which differs from second polysilicon (which forms a control gate layer), may be provided on the first polysilicon layer. With the above features, a non-volatile semiconductor memory device can be manufactured by reduced steps and be operated at high speed in a reliable manner.10-16-2008
20120032247NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell transistor obtained by sequentially stacking the gate insulation film, the floating gate electrode, the interelectrode insulation film, and the control gate electrode over the channel semiconductor layer. The control gate electrode has a structure obtained by sequentially stacking the semiconductor film, the silicide phase-change suppressing layer, and the silicide film. In addition, the silicide phase-change suppressing layer includes a polycrystalline silicon film in which at least one of C, F, and N is doped in a concentration range of 1×1002-09-2012
20100320523FINNED MEMORY CELLS - For an embodiment, a memory array has a plurality fins protruding from a substrate. A tunnel dielectric layer overlies the fins. A plurality floating gates overlie the tunnel dielectric layer, and the floating gates correspond one-to-one with the fins protruding from the substrate. An intergate dielectric layer overlies the floating gates. A control gate layer overlies the intergate dielectric layer. Each fin includes an upper surface rounded by isotropic etching.12-23-2010
20100320522Semiconductor device - A semiconductor device includes a tunnel insulation film formed on a semiconductor substrate, a floating gate electrode formed on the tunnel insulation film, an inter-electrode insulation film formed on the floating gate electrode, a control gate electrode formed on the inter-electrode insulation film, a pair of oxide films which are formed between the tunnel insulation film and the floating gate electrode and are formed near lower end portions of a pair of side surfaces of the floating gate electrode, which are parallel in one of a channel width direction and a channel length direction, and a nitride film which is formed between the tunnel insulation film and the floating gate electrode and is formed between the pair of oxide films.12-23-2010
20110133266Flash Memory Having a Floating Gate in the Shape of a Curved Section - The floating gate of a flash memory may be formed with a flat lower surface facing a substrate and a curved upper surface facing the control gate. In some embodiments, such a device has improved capacitive coupling to the control gate and reduced capacitive coupling to its neighbors.06-09-2011
20110133267METHOD OF FABRICATING SEMICONDUCTOR DEVICE AND THE SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device includes forming a gate insulating film on a semiconductor substrate, forming a charge accumulation layer, an intermediate insulating film and a conductive layer sequentially on the gate insulating film, forming an electrode isolating trench in the conductive layer, the intermediate insulating film and the charge accumulation layer, forming a nitride film on upper and side surfaces of the conductive layer, side surfaces of the intermediate insulating film, side surfaces of the charge accumulation layer and an upper surface of the gate insulating film, removing the nitride film formed on the upper surface of the gate insulating film, and filling the electrode isolating trench with an insulating film.06-09-2011
20110073929HIGH COUPLING MEMORY CELL - A first dielectric layer is formed over a substrate. A single layer first conductive layer that acts as a floating gate is formed over the first dielectric layer. A trough is formed in the first conductive layer to increase the capacitive coupling of the floating gate with a control gate. An intergate dielectric layer is formed over the floating gate layer. A second conductive layer is formed over the second dielectric layer to act as a control gate.03-31-2011
20110254073NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - Nonvolatile semiconductor memory device includes; a first element isolation insulation layer within a first dummy cell region; a second element isolation insulation layer within a second dummy cell region; and a third element isolation insulation layer at boundary between the first and second dummy cell regions. Top surface of the first element isolation insulation layer is located lower than that of first floating electrode layers. Top surface of the second element isolation insulation layer is located at the same height as that of second floating electrode layers. The third element isolation insulation layer has a top surface. The end portion of the top surface adjoining the first floating electrode layer is located at a height lower than the top surface of the first floating electrode layer. The top surface of the third element isolation insulation layer has gradient ascending from the side surface of the first floating electrode layer toward that of the second floating electrode layer.10-20-2011
20110079838NON-VOLATILE MEMORY DEVICE - A method of fabricating a semiconductor device includes forming a fin-shaped active region including opposing sidewalls and a surface therebetween protruding from a substrate, forming a gate structure on the surface of the active region, and performing an ion implantation process to form source/drain regions in the active region at opposite sides of the gate structure. The source/drain regions respectively include a first impurity region in the surface of the active region and second impurity regions in the opposing sidewalls of the active region. The first impurity region has a doping concentration that is greater than that of the second impurity regions. Related devices are also discussed.04-07-2011
20110095351SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - A semiconductor device includes a device isolation layer in a semiconductor substrate, an active region defined by the device isolation layer, the active region including a main surface and a recess region including a bottom surface that is lower than the main surface, and a gate electrode formed over the recess region, wherein a top surface of the device isolation layer adjacent to the recess region is lower than the bottom surface of the recess region.04-28-2011
20110175153Semiconductor Device Having Transistor with Vertical Gate Electrode and Method of Fabricating the Same - A semiconductor device includes transistors with a vertical gate electrode. In a transistor structure, a semiconductor pattern has first and second sides facing in a transverse direction, and third and fourth sides facing in a longitudinal direction. Gate patterns are disposed adjacent to the first and second sides of the semiconductor pattern. Impurity patterns directly contact the third and fourth sides of the semiconductor pattern. A gate insulating pattern is interposed between the gate patterns and the semiconductor pattern.07-21-2011
20110260234NON-VOLATILE MEMORY DEVICE - A semiconductor device may include a tunnel insulating layer disposed on an active region of a substrate, field insulating patterns disposed in surface portions of the substrate to define the active region, each of the field insulating patterns having an upper recess formed at an upper surface portion thereof, a stacked structure disposed on the tunnel insulating layer, and impurity diffusion regions disposed at surface portions of the active region adjacent to the stacked structure.10-27-2011
20110260233DEVICE COMPRISING A FIELD-EFFECT TRANSISTOR IN A SILICON-ON-INSULATOR - The present invention relates to a semiconductor device that has a semiconductor-on-insulator (SeOI) structure, which includes a substrate, an insulating layer such as an oxide layer on the substrate and a semiconductor layer on the insulating layer with a field-effect-transistor (FET) formed in the SeOI structure from the substrate and deposited layers, wherein the FET has a channel region in the substrate, a gate dielectric layer that is made from at least a part of the oxide layer of the SeOI structure; and a gate electrode that is formed at least partially from a part of the semiconductor layer of the SeOI structure. The invention further relates to a method of forming one or more field-effect-transistors or metal-oxide-semiconductor transistors from a semiconductor-on-insulator structure that involves patterning and etching the SeOI structure, forming shallow trench isolations, depositing insulating, metal or semiconductor layers, and removing mask and/or pattern layers.10-27-2011
20100025751SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor memory device and a method of fabricating the same which is suitable for fabrication of a non-volatile memory, such as an EEPROM, using a polysilicon-insulator-polysilicon (PIP) process. The semiconductor memory device includes isolation layers defining a tunneling region and a read transistor region of a semiconductor substrate, a lower polysilicon film formed on and/or over the tunneling region and the read transistor region, a dielectric film formed on and/or over the lower polysilicon film in the tunneling region, and an upper polysilicon film formed on and/or over the dielectric film.02-04-2010
20100025750MEMORY AND METHOD OF FABRICATING THE SAME - A memory and a method of fabricating the same are provided. The memory is disposed on a substrate in which a plurality of trenches is arranged in parallel. The memory includes a gate structure and a doped region. The gate structure is disposed between the trenches. The doped region is disposed at one side of the gate structure, in the substrate between the trenches and in the sidewalls and bottoms of the trenches. The top surface of the doped region in the substrate between the trenches is lower than the surface of the substrate under the gate structure by a distance, and the distance is greater than 300 Å.02-04-2010
20110215393ON-CHIP PLASMA CHARGING SENSOR - A device for monitoring charging effects includes a semiconductor substrate having a surface region. The device also includes first, second, and third doped regions spaced apart in the semiconductor substrate and a dielectric layer overlying the surface region. The device also includes a first gate overlying a first portion of the dielectric layer disposed between the first and the second doped regions, and a second gate overlying a second portion of the dielectric layer disposed between the second and the third doped regions, the second gate being characterized by a first surface area. Moreover, the device has a conductive layer electrically coupled to the second gate for collecting plasma charges. The conductive layer is characterized by a second surface area. The first gate is connected to a conductor that is coupled to a bias voltage, and the second gate is a floating gate that is not connected to any voltage.09-08-2011
20100019307METHOD OF FABRICATING FLASH MEMORY DEVICE - A method of fabricating a flash memory which increases a coupling ratio between a floating gate and a control gate in a cell. The method comprises sequentially forming a tunnel oxide film, and polysilicon and first insulation films for a floating gate on an active area of a semiconductor substrate; forming a photoresist as a mask on the first insulation film, and performing an etching process using the photoresist as the mask; forming a hard mask by depositing a second insulation film for prevention of oxidation on the semiconductor substrate; forming an STI by using the hard mask; oxidizing sidewalls of the STI and gap-filling the STI; forming a floating gate by removing the second insulation film remaining as the hard mask; and sequentially forming an ONO film and a control gate on the floating gate.01-28-2010
20100019306Semiconductor Fabrication - This document discloses devices fabricated on a semiconductor substrate and methods of fabricating the same. The devices can be memory cells having a tunnel window that is defined by dry-etching oxide to expose the semiconductor substrate and growing a tunnel oxide layer on the exposed semiconductor substrate. The semiconductor substrate can be decontaminated and/or repaired by exposing the semiconductor substrate to an optical irradiated energy source having a predefined energy that is sufficient to break molecular bonds of the contaminants and exposing the semiconductor substrate to a temperature that is sufficient to recrystallize the crystal lattice of the substrate.01-28-2010
20120146123SCALABLE FLASH EEPROM MEMORY CELL WITH FLOATING GATE SPACER WRAPPED BY CONTROL GATE AND METHOD OF MANUFACTURE - A flash memory cell includes a substrate having a surface region and a flash memory cell structure on the surface region. The flash memory cell structure includes a gate dielectric layer on the surface region, a select gate on the gate dielectric layer, a cap oxide layer on the select gate, an oxide spacer on a first edge of the select gate, a tunnel oxide layer on a first region and on a second region of the surface region. The second region is an active region. The flash memory cell structure further includes a poly spacer on the first edge of the oxide spacer and a portion of the tunnel oxide layer on the first region, an ONO layer on at least the poly spacer and a control gate layer on the ONO layer.06-14-2012
20080303077FLASH MEMORY WITH 4-BIT MEMORY CELL AND METHOD FOR FABRICATING THE SAME - A memory device having at least one memory cell, and each memory cell is configured to store multiple bits. Each bit is stored in a charge storage layer of the memory cell. The memory device can include a double gate structure that can store 4-bits per cell that expands the density of the non-volatile memory device such as flash memory.12-11-2008
20090173987FLASH MEMORY DEVICE WITH ISOLATION STRUCTURE - A flash memory device includes trenches that are formed at regions on a semiconductor substrate spaced apart from one another at predetermined distances, buried floating gates buried into the trenches, a plurality of isolation structures formed between the buried floating gates, and a dielectric film and a control gate formed on the buried floating gates07-09-2009
20090065844NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A nonvolatile semiconductor memory device includes a plurality of nonvolatile memory cells each having a double-layered gate structure in which a floating gate and a control gate formed of a nickel silicide film are laminated, a first contact plug formed on a substrate contact portion of a surface of the semiconductor substrate, the first contact plug having a lower layer formed of a semiconductor film and an upper layer formed of a nickel silicide film, and second contact plugs formed on the control gates and first contact plug.03-12-2009
20120037973NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A memory cell includes a floating gate electrode, a first inter-electrode insulating film and a control gate electrode. A peripheral transistor includes a lower electrode, a second inter-electrode insulating film and an upper electrode. The lower electrode and the upper electrode are electrically connected via an opening provided on the second inter-electrode insulating film. The first and second inter-electrode insulating films include a high-permittivity material, the first inter-electrode insulating film has a first structure, and the second inter-electrode insulating film has a second structure different from the first structure.02-16-2012
20110108905NONVOLATILE SEMICONDUCTOR MEMORY - A nonvolatile semiconductor memory includes first and second memory cells having a floating gate and a control gate. The floating gate of the first and second memory cells is comprised a first part, and a second part arranged on the first part, and a width of the second part in an extending direction of the control gate is narrower than that of the first part. A first space between the first parts of the first and second memory cells is filled with one kind of an insulator. The control gate is arranged at a second space between the second parts of the first and second memory cells.05-12-2011
20110163368Semiconductor Memory Device and Manufacturing Method Thereof - A nonvolatile semiconductor memory device having high charge retention characteristics and capable of improving leakage characteristics of a dielectric film disposed between a charge storage layer and a control gate electrode, and manufacturing method thereof is disclosed. According to one aspect, there is provided a semiconductor memory device comprising a first electrode disposed on a first insulator on a semiconductor substrate, a second insulator disposed on the first electrode, a second electrode disposed on the second insulator, and diffusion layers disposed in the semiconductor substrate, wherein the second insulator including a silicon-rich silicon nitride film containing more silicon than that in a stoichiometric silicon nitride film, and a silicon oxide film formed on the silicon-rich silicon nitride film, and wherein the silicon-rich silicon nitride film has a ratio of a silicon concentration and a nitrogen concentration set to 1:0.9 to 1:1.2.07-07-2011
20110316067ELECTRONIC DEVICE INCLUDING A TUNNEL STRUCTURE - An electronic device can include a tunnel structure that includes a first electrode, a second electrode, and tunnel dielectric layer disposed between the electrodes. In a particular embodiment, the tunnel structure may or may not include an intermediate doped region that is at the primary surface, abuts a lightly doped region, and has a second conductivity type opposite from and a dopant concentration greater than the lightly doped region. In another embodiment, the electrodes have opposite conductivity types. In a further embodiment, an electrode can be formed from a portion of a substrate or well region, and the other electrode can be formed over such portion of the substrate or well region.12-29-2011
20120043600Floating-Gate Device and Method Therefor - Non-volatile floating gate devices and approaches involve setting or maintaining threshold voltage characteristics relative to thermal processing. In connection with various embodiments, a floating gate device includes a polycrystalline silicon material having an impurity therein. The impurity interacts with the polycrystalline material to resist changes in grain size of the polycrystalline silicon material during thermal processing, and setting charge storage characteristics relative to threshold voltages for the floating gate device.02-23-2012
20120001247ULTRAHIGH DENSITY VERTICAL NAND MEMORY DEVICE AND METHOD OF MAKING THEREOF - Monolithic, three dimensional NAND strings include a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate, the blocking dielectric comprising a plurality of blocking dielectric segments, a plurality of discrete charge storage segments, and a tunnel dielectric located between each one of the plurality of the discrete charge storage segments and the semiconductor channel.01-05-2012
20110156124NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - The invention enhances program performance by increasing a coupling ratio between an N+ type source layer and a floating gate and reduces a memory cell area. Trenches are formed on the both sides of an N+ type source layer. The sidewalls of the trench includes first and second trench sidewalls that are parallel to end surfaces of two element isolation layers, a third trench sidewall that is perpendicular to the STIs, and a fourth trench sidewall that is not parallel to the third trench sidewall. The N+ type source layer is formed so as to extend from the bottom surface of the trench to the fourth trench sidewall, largely overlapping a floating gate, by performing ion-implantation of arsenic ion or the like in a parallel direction to the third trench sidewall and in a perpendicular direction or at an angle to a P type well layer from above the trench having this structure.06-30-2011
20110156126SEMICONDUCTOR DEVICE HAVING AN OXIDE FILM FORMED ON A SEMICONDUCTOR SUBSTRATE SIDEWALL OF AN ELEMENT REGION AND ON A SIDEWALL OF A GATE ELECTRODE - A first isolation is formed on a semiconductor substrate, and a first element region is isolated via the first isolation. A first gate insulating film is formed on the first element region, and a first gate electrode is formed on the first gate insulating film. A second isolation is formed on the semiconductor substrate, and a second element region is isolated via the second isolation. A second gate insulating film is formed on the second element region, and a second gate electrode is formed on the second gate insulating film. A first oxide film is formed between the first isolation and the first element region. A second oxide film is formed between the second isolation and the second element region. The first isolation has a width narrower than the second isolation, and the first oxide film has a thickness thinner than the second oxide film.06-30-2011
20120056258ELECTRICAL SWITCH USING GATED RESISTOR STRUCTURES AND THREE-DIMENSIONAL INTEGRATED CIRCUITS USING THE SAME - An electrical switch using a gated resistor structure includes an isolation layer, a doped silicon layer arranged on the isolation layer and having a recessed portion with reduced thickness, the doped silicon layer having a predetermined doping type and a predetermined doping profile; a gate layer arranged corresponding to the recessed portion. The recessed portion in the doped silicon layer has such thickness that a channel defined under the gate can be fully depleted to form a high resistivity region. The recessed channel gated resistor structure can be advantageously used to achieve high interconnect density with low thermal budget for 3D integration.03-08-2012
20120007165SEMICONDUCTOR DEVICES - A semiconductor device includes a substrate, a plurality of gate structures, a first insulating interlayer pattern, and a second insulation layer pattern. The substrate has an active region and a field region, each of the active region and the field region extends in a first direction, and the active region and the field region are alternately and repeatedly arranged in a second direction substantially perpendicular to the first direction. The gate structures are spaced apart from each other in the first direction, each of the gate structures extends in the second direction. The first insulation layer pattern is formed on a portion of a sidewall of each gate structure. The second insulation layer pattern covers the gate structures and the first insulation layer pattern, and has an air tunnel between the gate structures, the air tunnel extending in the second direction.01-12-2012
20120007163NONVOLATILE MEMORY DEVICE - According to one embodiment, a nonvolatile memory device includes a substrate, first and second tunnel insulating films, first and second floating gate electrodes, an intergate insulating film and a control gate electrode. The substrate has first and second active regions isolated from each other by an element isolation trench. The first and second tunnel insulating films are located in the first and second active regions, respectively. The first and second floating gate electrodes are located on the first and second tunnel insulating films, respectively. The intergate insulating film includes a first insulating layer of a first insulating material, an electron trap layer of a second insulating material on the first insulating layer, and a second insulating layer of the first insulating material on the electron trap layer. The control gate electrode is located on the intergate insulating film.01-12-2012
20120012916Stacked gate nonvolatile semiconductor memory and method for manufacturing the same - A stacked gate nonvolatile semiconductor memory includes at least a memory cell transistor and a selective gate transistor which are formed on a semiconductor substrate. The memory cell transistor includes a floating gate made of a semiconductor material below an interlayer insulating layer and a control gate made of a silicide above the interlayer insulating layer. The selective gate transistor includes a semiconductor layer made of the semiconductor material, a silicide layer made of the silicide and a conductive layer made of a conductive material not subject to silicide process which is formed through the interlayer insulating film so as to electrically connect the semiconductor layer and the silicide layer.01-19-2012
20120012918SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor structure and the method for manufacturing the same, wherein the structure comprising a semiconductor substrate: a flash memory device formed on the semiconductor substrate; wherein the flash memory device comprising: a channel region formed on the semiconductor substrate; a gate stack structure formed on the channel region; wherein the gate stack structure comprises: a first gate dielectric layer formed on the channel region; a first conductive layer formed on the first gate dielectric layer; a second gate dielectric layer formed on the first conductive layer; a second conductive layer formed on the second gate dielectric layer; a heavily doped first-conduction-type region and a heavily doped second-conduction-type region at both sides of the channel region respectively, wherein the first conduction type is opposite to the second conduction type in the type of conduction.01-19-2012
20120012917Semiconductor device and method for manufacturing the same - It is made possible to provide a method for manufacturing a semiconductor device that has a high-quality insulating film in which defects are not easily formed, and experiences less leakage current. A method for manufacturing a semiconductor device, includes: forming an amorphous silicon layer on an insulating layer; introducing oxygen into the amorphous silicon layer; and forming a silicon oxynitride layer by nitriding the amorphous silicon layer having oxygen introduced thereinto.01-19-2012
20110049605SPLIT GATE NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING SPLIT GATE NONVOLATILE SEMICONDUCTOR STORAGE DEVICE - A split gate nonvolatile semiconductor storage device includes: a substrate; a floating gate; a control gate; a first source/drain diffusion layer; a second source/drain diffusion layer; and a silicide. The floating gate is formed on the substrate through a gate insulating film. The control gate is formed adjacent to the floating gate through a tunnel insulating film. The first source/drain diffusion layer is formed in a surface region of the substrate on a side of the floating gate. The second source/drain diffusion layer is formed in a surface region of the substrate on a side of the control gate. The silicide contacts the first source/drain diffusion layer.03-03-2011
20110049604NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a nonvolatile semiconductor memory device includes: a semiconductor substrate; an element isolation insulator formed in an upper portion of the semiconductor substrate and dividing the upper portion into first and second active areas extending in a first direction; a first contact connected to the first active area; and a second contact connected to the second active area. Each of the first and second active area includes: a first portion connected to one of the first contact and the second contact; and a second portion having an upper surface being placed lower than an upper surface of the first portion. The first contact and the second contact are mutually shifted in the first direction. The first portion of the first active area is disposed adjacent to the second portion of the second active area.03-03-2011
20110049603Reverse Disturb Immune Asymmetrical Sidewall Floating Gate Devices and Methods - Circuits and methods for providing a floating gate structure comprising floating gate cells having improved reverse tunnel disturb immunity. A floating gate structure is formed over a semiconductor substrate comprising a floating gate, a charge trapping dielectric layer is formed, and a control gate is formed. The floating gate structure has vertical sidewalls, one side adjacent a source region and one side adjacent a drain region. A symmetric sidewall dielectric is formed over the floating gate structure on both the source side and drain side regions. An asymmetric dielectric layer is formed over the drain side sidewall only. The use of the asymmetric sidewall on the drain side sidewall provides improved RTD immunity. Methods for forming the structure are disclosed.03-03-2011
20110049602NON-VOLATILE MEMORY SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A gate insulating film layer, a floating gate electrode layer, an interelectrode insulating film layer, and a control gate electrode layer are stacked on a silicon substrate, and the control gate electrode film layer is etched to form a plurality of the control gate electrodes having the same width with the width of the memory cell. An arbitrary of the plurality of control gate electrodes is a transistor unit, and an interelectrode insulating film, a floating gate electrode, and a gate insulating film are formed in the transistor unit. In the transistor unit, a conductive material is buried into a contact hole to form a transistor, the contact hole is formed along the plurality of control gate electrodes.03-03-2011
20110062508SEMICONDUCTOR DEVICE INCLUDING RESISTOR AND METHOD OF FABRICATING THE SAME - Embodiments of a semiconductor device including a resistor and a method of fabricating the same are provided. The semiconductor device includes a mold pattern disposed on a semiconductor substrate to define a trench, a resistance pattern including a body region and first and second contact regions, wherein the body region covers the bottom and sidewalls of the trench, the first and second contact regions extend from the extending from the body region over upper surfaces of the mold pattern, respectively; and first and second lines contacting the first and second contact regions, respectively.03-17-2011
20120025294SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - There is provided a semiconductor device in which degradation of reliability originating in the interface between an upper insulating layer and an element isolation insulating layer is suppressed. The semiconductor device includes: a semiconductor region; a plurality of stacked structures each of which is disposed on the semiconductor region and has a tunnel insulating film, a charge storage layer, an upper insulating layer, and a control electrode stacked sequentially; an element isolation insulating layer disposed on side faces of the plurality of stacked structures; and a source-drain region disposed on the semiconductor region and among the plurality of stacked structures. The element isolation insulating layer includes at least one of SiO02-02-2012
20120025292NONVOLATILE SEMICONDUCTOR MEMORY TRANSISTOR AND METHOD FOR MANUFACTURING NONVOLATILE SEMICONDUCTOR MEMORY - A nonvolatile semiconductor memory transistor includes an island-shaped semiconductor having a source region, a channel region, and a drain region formed in this order from the Si substrate side, a floating gate surrounding the outer periphery of the channel region with a tunnel insulating film interposed therebetween, a control gate surrounding the outer periphery of the floating gate with an inter-polysilicon insulating film interposed therebetween, and a control gate line connected to the control gate and extending in a predetermined direction. The floating gate extends to regions below and above the control gate and to a region below the control gate line. The inter-polysilicon insulating film is interposed between the floating gate and the upper surface, lower surface, and inner side surface of the control gate and between the control gate line and a portion of the floating gate that extends to the region below the control gate line.02-02-2012
20120153375Nonvolatile semiconductor memory device - Provided is an electrically erasable and programmable nonvolatile semiconductor memory device whose tunnel region formed in the drain region has the second conductivity-type low-impurity-concentration region with the first tunnel insulating film for solely injecting electrons disposed thereon, and the first conductivity-type low-impurity-concentration region with the second tunnel insulating film for solely ejecting electrons disposed thereon, both regions fixed to the same potential as the drain region and having a lower impurity concentration than that of the drain region.06-21-2012
201100843273-D ELECTRICALLY PROGRAMMABLE AND ERASABLE SINGLE-TRANSISTOR NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - A non-volatile memory device includes a source region, a drain region, and a channel region therebetween. The channel region has a length extending from the source region to the drain region and a channel width in the direction perpendicular to the channel length direction. The device includes a floating gate positioned between the source and the drain in the channel length direction. The width of the floating gate is less than the channel width. A control gate covers a top surface and a side surface of the floating gate. The control gate also overlies an entirety of the channel region. Erasure of the cell is accomplished by Fowler-Nordheim tunneling from the floating gate to the control gate. Programming is accomplished by electrons migrating through an electron concentration gradient from a channel region underneath the control gate into a channel region underneath the floating gate and then injecting into the floating gate.04-14-2011
20120153374SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device including a semiconductor substrate; a memory cell region formed in the semiconductor substrate and including a plurality of memory cells; a peripheral circuit region formed in the semiconductor substrate; a first element isolation trench with a first width formed in the memory cell region; a second element isolation trench with a second width greater than the first width formed in the peripheral circuit region; a first oxide film formed along an inner surface of the first element isolation trench; a first coating oxide film formed along the first oxide film and filling the first element isolation trench; a second oxide film formed along a sidewall of the second element isolation trench; a third oxide film formed above a bottom of the second element isolation trench; and a second coating oxide film formed above the third oxide film and filling the second element isolation trench.06-21-2012
20100096686ELECTRONIC DEVICE INCLUDING TRENCHES AND DISCONTINUOUS STORAGE ELEMENTS - An electronic device can include a substrate including a first trench having a first bottom and a first wall. The electrode device can also include a first gate electrode within the first trench and adjacent to the first wall and overlying the first bottom of the first trench, and a second gate electrode within the first trench and adjacent to the first gate electrode and overlying the first bottom of the first trench. The electronic device can further include discontinuous storage elements including a first set of discontinuous storage elements, wherein the first set of the discontinuous storage elements lies between (i) the first gate electrode or the second gate electrode and (ii) the first bottom of the first trench. Processes of forming and using the electronic device are also described.04-22-2010
20100096685Strained Semiconductor Device and Method of Making Same - In a method of making a semiconductor device, a gate dielectric is formed over the semiconductor body. A floating gate is formed over the gate dielectric, an insulating region over the floating gate, and a control gate over the insulating region. The gate dielectric, floating gate, insulating region, and control gate constitute a gate stack. A stress is caused in the gate stack, whereby the band gap of the gate dielectric is changed by the stress.04-22-2010
20100096684SEMICONDUCTOR DEVICE AND ITS MANUFACTURE METHOD - A semiconductor device includes non-volatile memory cells and a peripheral circuit including field effect transistors having an insulated gate. The semiconductor device has memory cells with a high retention ability and field effect transistors having an insulated gate with large drive current. The semiconductor device has a semiconductor substrate (04-22-2010
20090134445SEMICONDUCTOR DEVICE WITH DIELECTRIC STRUCTURE AND METHOD FOR FABRICATING THE SAME - A semiconductor device with a dielectric structure and a method for fabricating the same are provided. A capacitor in the semiconductor device includes: a bottom electrode formed on a substrate; a first dielectric layer made of titanium dioxide (TiO05-28-2009
20090134444Memory Cells, And Methods Of Forming Memory Cells - Some embodiments include methods of forming memory cells. Dopant is implanted into a semiconductor substrate to form a pair of source/drain regions that are spaced from one another by a channel region. The dopant is annealed within the source/drain regions, and then a plurality of charge trapping units are formed over the channel region. Dielectric material is then formed over the charge trapping units, and control gate material is formed over the dielectric material. Some embodiments include memory cells that contain a plurality of nanosized islands of charge trapping material over a channel region, with adjacent islands being spaced from one another by gaps. The memory cells can further include dielectric material over and between the nanosized islands, with the dielectric material forming a container shape having an upwardly opening trough therein. The memory cells can further include control gate material within the trough.05-28-2009
20120119283METHODS FOR FORMING ETCH STOP LAYERS, SEMICONDUCTOR DEVICES HAVING THE SAME, AND METHODS FOR FABRICATING SEMICONDUCTOR DEVICES - A plurality of vertical channels of semiconductor material are formed to extend in a vertical direction through the plurality of insulation layers and the plurality of conductive patterns, a gate insulating layer between the conductive pattern and the vertical channels that insulates the conductive pattern from the vertical channels. Conductive contact regions of the at least two of the conductive patterns are in a stepped configuration. An etch stop layer is positioned on the conductive contact regions, wherein the etch stop layer has a first portion on a first one of the plurality of conductive patterns and has a second portion on a second one of the plurality of conductive patterns, wherein the first portion is of a thickness that is greater than a thickness of the second portion.05-17-2012
20120119282SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A system, method, and layout for a semiconductor integrated circuit device allows for improved scaling down of various back-end structures, which can include contacts and other metal interconnection structures. The resulting structures can include a semiconductor substrate, a buried diffusion region formed on the semiconductor substrate, and at least one of a silicide film, for example tungsten silicide (WSi05-17-2012
20120211818SEMICONDUCTOR DEVICES - In a semiconductor device, a first gate structure is provided in a cell transistor region and includes a floating gate electrode, a first dielectric layer pattern, and a control gate electrode including a first metal silicide pattern. A second gate structure is provided in a selecting transistor region and includes a first conductive layer pattern, a second dielectric layer pattern, and a first gate electrode including a second metal silicide pattern. A third gate structure is provided in a peripheral circuit region and includes a second conductive layer pattern, a third dielectric layer pattern including opening portions on the second conductive layer pattern, and a second gate electrode including a concavo-convex portion at an upper surface portion thereof and a third metal silicide pattern. The third metal silicide pattern has a uniform thickness.08-23-2012
20120126303NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a part of a buried insulating film buried in a trench is removed; accordingly, an air gap is formed between adjacent floating gate electrodes in a word line direction, and the air gap is formed continuously along the trench in a manner of sinking below a control gate electrode.05-24-2012
20120161221NON-VOLATILE MEMORY AND FABRICATING METHOD THEREOF - A non-volatile memory having a tunneling dielectric layer, a floating gate, a control gate, an inter-gate dielectric layer and a first doping region and a second doping region is provided. The tunneling dielectric layer is disposed on a substrate. The floating gate is disposed on the tunneling dielectric layer, and has a protruding portion. The control gate is disposed over the floating gate to cover and surround the protruding portion. The protruding portion of the floating gate is fully covered and surrounded by the control gate in any direction, including extending directions of bit lines, word lines and an included angle formed between the word line and the bit line. The inter-gate dielectric layer is disposed between the floating gate and the control gate. The first doping region and the second doping region are respectively disposed in the substrate at two sides of the control gate.06-28-2012
20100207187NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device comprises a memory cell. The memory cell includes a first gate insulating film formed on a semiconductor substrate, a floating gate formed on the first gate insulating film, a second gate insulating film formed on the floating gate, and a control gate formed on the second gate insulating film. The floating gate includes a first semiconductor film which contacts the first gate insulating film, and a metal film stacked on the semiconductor film. An effective tunneling thickness between the semiconductor substrate and the floating gate in a read operation is thicker than an effective tunneling thickness between the semiconductor substrate and the floating in a write operation.08-19-2010
20100207188Semiconductor device and method of fabricating the same - A semiconductor device according to an embodiment of the present invention includes: a semiconductor substrate; an isolation structure formed in a trench, formed in the semiconductor substrate, through a semiconductor oxide film; a floating gate formed on the semiconductor substrate between the isolation structures through an insulating film; a gate oxidation protection film formed on a side surface, on the isolation structure side, of the floating gate so that each of a part of a side surface and a bottom surface of the gate oxidation protection film contacts the insulating film; and a control gate formed on the floating gate through an inter-gate insulating film.08-19-2010
20120132980 NONVOLATILE SEMICONDUCTOR MEMORY - A nonvolatile semiconductor memory fabrication method including forming a first insulating film and a floating gate electrode material on a semiconductor substrate; forming a gate insulating film and a floating gate electrode by etching the first insulating film and the floating gate electrode material, respectively, and forming a groove for an element isolation region by etching the semiconductor substrate; and forming an element region and the element isolation region by burying a second insulating film in the groove and planarizing the second insulating film.05-31-2012
20120313158SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - The present invention provides a semiconductor structure and a method for manufacturing the same. The method comprises: providing a substrate, forming sequentially a first high-k dielectric layer, an adjusting layer, a second high-k dielectric layer and a metal gate on the substrate, etching the first high-k dielectric layer, the adjusting layer, the second high-k dielectric layer and the metal gate to form a gate stack. Accordingly, the present invention further provides a semiconductor structure. The present invention proposes to arrange an adjusting layer between two layers of high-k dielectric layer, which effectively avoids reaction of the adjusting layer with the metal gate because of their direct contact, so as to maintain the performance of semiconductor devices.12-13-2012
20090057749NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A memory cell includes a floating gate electrode, a first inter-electrode insulating film and a control gate electrode. A peripheral transistor includes a lower electrode, a second inter-electrode insulating film and an upper electrode. The lower electrode and the upper electrode are electrically connected via an opening provided on the second inter-electrode insulating film. The first and second inter-electrode insulating films include a high-permittivity material, the first inter-electrode insulating film has a first structure, and the second inter-electrode insulating film has a second structure different from the first structure.03-05-2009
20090057748Memory and manufacturing method thereof - A memory and a manufacturing method thereof are provided. The memory includes a dielectric layer, a polysilicon layer, a first buried diffusion, a second buried diffusion, a charge storage structure and a gate. The polysilicon layer is disposed on the dielectric layer and electrically connected to at least a voltage. The first buried diffusion and the second buried diffusion are separately disposed in the surface of the polysilicon layer. The charge storage structure is disposed on the polysilicon layer and positioned between the first buried diffusion and the second buried diffusion. The gate is disposed on the charge storage structure.03-05-2009
20120168844Nonvolatile semiconductor memory device - Provided is an electrically erasable and programmable nonvolatile semiconductor memory device having a tunnel region; the tunnel region and the peripheral of the tunnel region are dug down to be made lower, and a depletion electrode, to which an arbitral potential is given to deplete a part of the tunnel region through a depletion electrode insulating film, is arranged in the lowered drain region.07-05-2012
20110303961NONVOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING SAME - A nonvolatile memory device including a cell array area in which a plurality of unit cells are arranged at least in one direction includes a plurality of memory transistors formed in the respective unit cells. Each memory transistor includes a gate pattern in which a tunnel insulating layer, a floating gate, an inter-gate insulating layer, and a control gate are laminated, and first and second junction areas arranged on opposite sides of the gate pattern, wherein the gate patterns are separated in the one direction by unit cells. The to nonvolatile memory device also includes a first conduction interconnection which extends in the one direction and is arranged in a position that overlaps the control gate and a plurality of first contacts, at least one of which is arranged for each of the control gates to connect the control gates and the first conduction interconnection.12-15-2011
20120168842SPLIT GATE FLASH CELL AND METHOD FOR MAKING THE SAME - A method for forming a split gate flash cell device provides for forming floating gate transistors. Each floating gate transistor is formed by providing a floating gate transistor substructure including an oxide disposed over a polysilicon gate disposed over a gate oxide disposed on a portion of a common source. Nitride spacers are formed along sidewalls of the floating gate transistor substructure and cover portions of the gate oxide that terminate at the sidewalls. An isotropic oxide etch is performed with the nitride spacers intact. The isotropic etch laterally recedes opposed edges of the oxide inwardly such that a width of the oxide is less than a width of the polysilicon gate. An inter-gate dielectric is formed over the floating gate transistor substructure and control gates are formed over the inter-gate dielectric to form the floating gate transistors.07-05-2012
20120168846NONVOLATILE SEMICONDUCTOR MEMORY DEVICE HAVING ELEMENT ISOLATING REGION OF TRENCH TYPE - Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, the element isolating region isolating a element region and being self-aligned with the first electrode layer, a second insulating film formed on the first electrode layer and the element isolating region, an open portion exposing a surface of the first electrode layer being formed in the second insulating film, and a second electrode layer formed on the second insulating film and the exposed surface of the first electrode layer, the second electrode layer being electronically connected to the first electrode layer via the open portion.07-05-2012
20120168845Nonvolatile semiconductor memory device - Provided is an electrically erasable and programmable nonvolatile semiconductor memory device having a small hole in a second conductivity-type drain region, a tunnel insulating film formed on the surface of the hole, and a protrusion extended from the floating gate electrode and arranged to fill the hole. Further a tunneling restriction region which is an electrically floating first conductivity type region arranged in a vicinity of the surface of the drain region around the hole to define the size of the tunnel region through which the tunnel current flows.07-05-2012
20120248523NON-VOLATILE MEMORY AND LOGIC CIRCUIT PROCESS INTEGRATION - An integrated circuit is disclosed that includes a split gate memory device comprising a select gate is located over a substrate. A charge storage layer includes a layer of discrete storage elements and a layer of high-k dielectric material covering at least one side of the layer of discrete storage elements. At least a portion of a control gate is located over the charge storage layer. The control gate includes a layer of barrier work function material and a layer of gate material located over the layer of barrier work function material.10-04-2012
20090127612SEMICONDUCTOR DEVICE HAVING A GATE STRUCTURE - A gate structure in a semiconductor device includes a dielectric layer pattern on a substrate, a floating gate on the dielectric layer pattern, a gate mask on the floating gate, a tunnel insulation layer on the substrate, and a word line on the tunnel insulation layer. The dielectric layer pattern includes a first portion and a second portion having a thickness different from a thickness of the first portion. The floating gate includes a step and tips. The tunnel insulation layer makes contact with a sidewall of the floating gate. The word line extends on a portion of the gate mask.05-21-2009
20090114975SEMICONDUCTOR DEVICE - The present invention provides a semiconductor device, which includes a substrate and a sensing memory device. The substrate includes a metal-oxide-semiconductor transistor having a gate. The sensing memory device is disposed on the gate of the metal-oxide-semiconductor transistor and includes followings. The second conductive layer is covering the first conductive layer. The charge trapping layer is disposed between the first conductive layer and the second conductive layer, wherein the first conductive layer has a sensing region therein when charges stored in the charge trapping layer, and the sensing region is adjacent to the charge trapping layer. The first dielectric layer and the second dielectric layer are respectively disposed between the charge trapping layer and the first conductive layer and between the charge trapping layer and the second conductive layer, wherein a third dielectric layer is disposed between the gate and the sensing memory device.05-07-2009
20080211005SEMICONDUCTOR DEVICE - There is provided a MOSFET-type semiconductor device having a coating insulating film formed to cover the surface portions of MOS transistors formed on a semiconductor substrate. The insulating film is formed of a silicon nitride film or silicon oxynitride film and the ratio (N—H/Si—H) of the density of N—H bonds to the density of Si—H bonds in the insulating film is set to 3 or less.09-04-2008
20090096006NONVOLATILE SEMICONDUCTOR STORAGE APPARATUS AND METHOD FOR MANUFACTURING THE SAME - According to an aspect of the present invention, there is provided a nonvolatile semiconductor storage apparatus including: a semiconductor substrate on which element isolation trenches are formed to define element formation regions on the semiconductor substrate; gate insulating films that are formed on the element formation regions of the semiconductor substrate; floating gate electrodes that are formed on the gate insulating films; element isolation insulating films that each includes: a coating type insulating film that is formed in a corresponding one of the element isolation trenches; and a non-coating type insulating film that is formed to cover a top surface of the coating type insulating film; a interelectrode insulating film that is formed on the element isolation insulating films and floating gate electrodes; and a control gate electrode that is formed on the interelectrode insulating film.04-16-2009
20120175696MULTILAYER FLOATING GATE FIELD-EFFECT TRANSISTOR (FET) DEVICES AND RELATED METHODS - Multilayer floating gate field-effect transistor (FET) devices and related methods are provided. A multilayer floating gate FET device can include a first floating gate separated via a first dielectric layer from a channel of the device and a second floating gate separated via a second dielectric layer from the first floating gate. The second dielectric layer between the first floating gate and the second floating gate permits a redistribution of charge between the first and second floating gates from one of the floating gates to the other when under the influence of a first electrical field from a first voltage. In some embodiments, a redistribution of charge between the first and second floating gates with electrons being supplied through a channel to the first and second floating gates can occur when under the influence of a second electrical field from a second voltage that is greater than the first voltage.07-12-2012
20100270606NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FORMING THE SAME - A peripheral circuit area is formed around a memory cell array area. The peripheral circuit area has element regions, an element isolation region isolating the element regions, and field-effect transistor formed in each of the element regions and including a gate electrode extending in a channel width direction, on a semiconductor substrate. An end portion and a corner portion of the gate electrode are on the element isolation region. A radius of curvature of the corner portion of the gate electrode is smaller than a length from the end portion of the element region in the channel width direction to the end portion of the gate electrode in the channel width direction, and is less than 85 nm.10-28-2010
20120074485Nonvolatile Memory Device and Manufacturing Method Thereof - A nonvolatile memory device comprises a gate insulating layer, a floating gate and a dielectric layer sequentially formed over a semiconductor substrate, a capping layer formed over the dielectric layer, and a control gate formed over the capping layer, wherein the control gate includes nitrogen or carbon as an additive.03-29-2012
20120074484SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES - A method of manufacturing a semiconductor device including forming a plurality of gate structures spaced apart from each other on a substrate; forming a first insulation layer covering the gate structures, the first insulation layer including a void between the gate structures; removing an upper portion of the first insulation layer to form a first insulation layer pattern on sidewalls of lower portions of the gate structures and on the substrate between the gate structures, the first insulation layer pattern including a first recess thereon; forming a conductive layer on upper portions of the gate structures exposed by the first insulation layer pattern; reacting the conductive layer with the gate structures; and forming a second insulation layer on the upper portions of the gate structures, the second insulation layer including a second recess therebeneath in fluid communication with the first recess.03-29-2012
20120074483EEPROM CELL - A method of forming a device is disclosed. The method includes providing a substrate prepared with a cell area and forming first and second gates of first and second transistors in the cell area. The first gate includes a second sub-gate surrounding a first sub-gate. The first and second sub-gates of the first gate are separated by a first intergate dielectric layer. The second gate includes a second sub-gate surrounding a first sub-gate. The first and second sub-gates of the second gate are separated by a second intergate dielectric layer. The method also includes forming first and second junctions of the first and second transistors. A first gate terminal is formed and coupled to the second sub-gate of the first transistor. A second gate terminal is formed and coupled to at least the first sub-gate of the second transistor.03-29-2012
20120074482EEPROM CELL - A method of forming a device is disclosed. The method includes providing a substrate prepared with a cell area separated by other active areas by isolation regions. First and second gates of first and second transistors in the cell area are formed. The first gate includes first and second sub-gates separated by a first intergate dielectric layer. The second gate includes a second sub-gate surrounding a first sub-gate. The first and second sub-gates of the second gate are separated by a second intergate dielectric layer. First and second junctions of the first and second transistors are formed. The method also includes forming a first gate terminal coupled to the second sub-gate of the first transistor and a second gate terminal coupled to at least the first sub-gate of the second transistor.03-29-2012
20100006918HAFNIUM TANTALUM TITANIUM OXIDE FILMS - Embodiments of a dielectric layer containing a hafnium tantalum titanium oxide film structured as one or more monolayers include the dielectric layer disposed in an integrated circuit. Embodiments of methods of fabricating such a dielectric layer provide a dielectric layer for use in a variety of electronic devices. An embodiment may include forming hafnium tantalum titanium oxide film using atomic layer deposition.01-14-2010
20100244117NROM MEMORY CELL, MEMORY ARRAY, RELATED DEVICES AND METHODS - An array of memory cells configured to store at least one bit per one F09-30-2010
20100244116METHOD OF FORMING AN EEPROM DEVICE AND STRUCTURE THEREFOR - In one embodiment, an EEPROM device is formed to include a metal layer having an opening therethrough. The opening overlies a portion of a floating gate of the EEPROM device.09-30-2010
20090065845Embedded semiconductor device and method of manufacturing an embedded semiconductor device - Provided are an embedded semiconductor device and a method of manufacturing an embedded semiconductor device. In a method of manufacturing the embedded semiconductor device, layers of at least one cell gate stack may be formed in a cell area of a substrate. A logic gate structure may be formed in a logic area of the substrate. First source/drain regions may be formed adjacent to the logic gate structure, and metal silicide patterns may be formed on the logic gate structure and the first source/drain regions. At least one hard mask may be formed on the layers of the at least one cell gate stack, and a blocking pattern may be formed to cover the logic gate structure and the first source/drain regions. The at least one cell gate stack may be formed in the cell area by etching the layers of the at least one cell gate stack using the at least one hard mask as an etching mask. A memory transistor in the cell area may have an increased integration degree and a logic transistor in the logic area may have an increased response speed and a decreased resistance.03-12-2009
20120223378Floating Gate Semiconductor Memory Device and Method for Producing Such a Device - Disclosed are methods for manufacturing a floating gate memory device and the floating gate memory device thus obtained. In one embodiment, a method is disclosed that includes providing a semiconductor-on-insulator substrate, forming at least two trenches in the semiconductor-on-insulator substrate, and, as a result of forming the at least two trenches, forming at least one elevated structure. The method further includes forming isolation regions at a bottom of the at least two trenches by partially filling the at least two trenches, thermally oxidizing sidewall surfaces of at least a top portion of the at least one elevated structure, thereby providing a gate dielectric layer on at least the exposed sidewall surfaces; and forming a conductive layer over the at least one elevated structure, the gate dielectric layer, and the isolation regions to form at least one floating gate semiconductor memory device.09-06-2012
20090032860PROGRAMMABLE MEMORY, PROGRAMMABLE MEMORY CELL AND THE MANUFACTURING METHOD THEREOF - A programmable memory structure includes a substrate, an active area, a common-source and a common-drain respectively disposed on each side of the active area, a first and a second source contact electrically connected to the common-source, a first and a second drain contact electrically connected to the common-drain, and between the first and the second source contact and the first and the second drain contact a plurality of programmable memory cells including a first and a second dielectric layer respectively encapsulating a first and a second floating gate.02-05-2009
20120256246SEMICONDUCTOR DEVICE INCLUDING A FLOATING GATE - A semiconductor device includes a semiconductor layer with a trench dug downward from its surface, a source region formed on a surface layer portion adjacent to a first side of the trench in a prescribed direction, a drain region formed on the surface layer portion, adjacent to a second side of the trench opposite to the first side in the prescribed direction, a first insulating film on the bottom surface and the side surface of the trench, a floating gate stacked on the first insulating film and opposed to the bottom surface and the side surface of the trench through the first insulating film, a second insulating film formed on the floating gate, and a control gate at least partially embedded in the trench so that the portion embedded in the trench is opposed to the floating gate through the second insulating film.10-11-2012
20120139025DUAL GATE ELECTRONIC MEMORY CELL AND DEVICE WITH DUAL GATE ELECTRONIC MEMORY CELLS - A memory cell including: 06-07-2012
20080296653Semiconductor memory - A semiconductor memory device of an aspect of the present invention comprises a plurality of memory cell transistors arranged in a memory cell array, a select transistor which is disposed in the memory cell array and which selects the memory cell transistor, and a peripheral circuit transistor provided in a peripheral circuit which controls the memory cell array, the memory cell transistor including a gate insulating film provided on a semiconductor substrate, a floating gate electrode provided on the gate insulating film, a between-storage-layer-and-electrode insulating film which is provided on the floating gate electrode and through which the amount of passing charge is greater than that through the gate insulating film during the application of an electric field in write and erase operations of the semiconductor memory, and a control gate electrode on the between-storage-layer-and-electrode insulating film.12-04-2008
20120319186MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A method for forming a memory device includes: forming a tunnel insulation layer, a conductive layer for a floating gate electrode, a charge blocking layer and a conductive layer for a control gate electrode over a substrate; and selectively etching the conductive layer for the control gate electrode, the charge blocking layer and the conductive layer for the floating gate electrode, thereby forming a plurality of gate lines, a plurality of select lines and at least two dummy lines disposed in a gap region between adjacent select lines, wherein the gate lines, the select lines and the dummy lines together construct strings.12-20-2012
20120261740FLASH MEMORY AND METHOD FOR FABRICATING THE SAME - The present invention discloses a flash memory and a method for fabricating the same, and relates to the technical field of the semiconductor memory. The flash memory includes a buried oxygen layer on which a source terminal, a channel, and a drain terminal are disposed, wherein the channel is between the source terminal and the drain terminal, and a tunneling oxide layer, a polysilicon floating gate, a blocking oxide layer, and a polysilicon control gate are sequentially disposed on the channel, and a thin silicon nitride layer is disposed between the source terminal and the channel. The method includes: 1) performing a shallow trench isolation on a SOI silicon substrate to form an active region; 2) sequentially forming a tunneling oxide layer and a first polysilicon layer on the SOI silicon substrate to form a polysilicon floating gate, and forming a blocking oxide layer and a second polysilicon layer to form a polysilicon control gate; 3) etching the resultant structure to form a gate stack structure; 4) forming a drain terminal at one side of the gate stack structure, etching the silicon film at the other side of the gate stack structure, growing a thin silicon nitride layer, and then refilling the hole structure with silicon material, to form a source terminal. The method has the advantages of high programming efficiency, low power consumption, effectively preventing source-drain punchthrough effect.10-18-2012
20120261741Novel High Speed High Density NAND-Based 2T-NOR Flash Memory Design - A two transistor NOR flash memory cell has symmetrical source and drain structure manufactured by a NAND-based manufacturing process. The flash cell comprises a storage transistor made of a double-poly NMOS floating gate transistor and an access transistor made of a double-poly NMOS floating gate transistor, a poly1 NMOS transistor with poly1 and poly2 being shorted or a single-poly poly1 or poly2 NMOS transistor. The flash cell is programmed and erased by using a Fowler-Nordheim channel tunneling scheme. A NAND-based flash memory device includes an array of the flash cells arranged with parallel bit lines and source lines that are perpendicular to word lines. Write-row-decoder and read-row-decoder are designed for the flash memory device to provide appropriate voltages for the flash memory array in pre-program with verify, erase with verify, program and read operations in the unit of page, block, sector or chip.10-18-2012
20120261739SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device including a first doped region of a first conductivity type, a second doped region of a second conductivity type, a gate, and a dielectric layer is provided. The first doped region is located in a substrate and has a trench. The second doped region is located at the bottom of the trench to separate the first doped region into a source doped region and a drain doped region. A channel region is located between the source doped region and the drain doped region. The gate is located in the trench. The dielectric layer covers the sidewall and the bottom of the trench and separates the gate and the substrate.10-18-2012
20120299079FIELD SIDE SUB-BITLINE NOR FLASH ARRAY AND METHOD OF FABRICATING THE SAME - Field Side Sub-bitline NOR-type (FSNOR) flash array and the methods of fabrication are disclosed. The field side sub-bitlines of the invention formed with the same impurity type as the memory cells' source/drain electrodes along the two sides of field trench oxide link all the source electrodes together and all the drain electrodes together, respectively, for a string of semiconductor Non-Volatile Memory (NVM) cells in a NOR-type flash array of the invention. Each field side sub-bitline is connected to a main metal bitline through a contact at its twisted point in the middle. Because there are no contacts in between the linked NVM cells' electrodes in the NOR-type flash array of the invention, the wordline pitch and the bitline pitch can be applied to the minimum geometrical feature of a specific technology node. The NOR-type flash array of the invention provides at least as high as those in the conventional NAND flash array in cell area density.11-29-2012
20120299081NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A nonvolatile memory device includes a floating gate formed over a semiconductor substrate, an insulator formed on a first sidewall of the floating gate, a dielectric layer formed on a second sidewall and an upper surface of the floating gate, and a control gate formed over the dielectric layer.11-29-2012
20120299080STRUCTURE FOR CMOS ETSOI WITH MULTIPLE THRESHOLD VOLTAGES AND ACTIVE WELL BIAS CAPABILITY - A structure includes a semiconductor substrate having a first type of conductivity and a top surface; an insulating layer disposed over the top surface; a semiconductor layer disposed over the insulating layer and a plurality of transistor devices disposed upon the semiconductor layer. Each transistor device includes a source, a drain and a gate stack defining a channel between the source and the drain, where some transistor devices have a first type of channel conductivity and the remaining transistor devices have a second type of channel conductivity. The structure further includes a well region formed adjacent to the top surface of the substrate and underlying the plurality of transistor devices, the well region having a second type of conductivity and extending to a first depth within the substrate. The structure further includes first isolation regions between adjacent transistor devices and extending through the semiconductor layer to a depth sufficient for electrically isolating the adjacent transistor devices from one another, and second isolation regions between selected adjacent transistor devices. The second isolation regions extend through the silicon layer, through the insulating layer and into the substrate to a second depth that is greater than the first depth to electrically separate the well region into a first well region and a second well region. The structure further includes at least one back gate region disposed wholly within a well region and underlying one of the plurality of transistor devices, the at least one back gate region has the first type of conductivity and is electrically floating within the well region, where during operation the at least one back gate region having the first type of conductivity is biased by leakage and capacitive coupling by a bias potential applied to the well region within which it is disposed.11-29-2012
20110024821PUSH-PULL FPGA CELL - A flash memory cell includes a p-channel flash transistor having a source, a drain, a floating gate, and a control gate, an n-channel flash transistor having a source, a drain coupled to the drain of the p-channel flash transistor, a floating gate, and a control gate, a switch transistor having a gate coupled to the drains of the p-channel flash transistor and the n-channel flash transistor, a source, and a drain, and an n-channel assist transistor having a drain coupled to the drains of the p-channel flash transistor and the n-channel flash transistor, a source coupled to a fixed potential, and a gate.02-03-2011
20110037115SYSTEM AND METHOD FOR IMPROVING MESA WIDTH IN A SEMICONDUCTOR DEVICE - A method for forming a memory device is provided. A nitride layer is formed over a substrate. The nitride layer and the substrate are etched to form a trench. The nitride layer is trimmed on opposite sides of the trench to widen the trench within the nitride layer. The trench is filled with an oxide material. The nitride layer is stripped from the memory device, forming a mesa above the trench.02-17-2011
20120267698FLOATING-GATE NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MAKING - The present invention provides a floating-gate non-volatile semiconductor memory device and a method of making the same. The floating-gate non-volatile semiconductor memory device comprises a semiconductor substrate, a source, a drain, a first insulator layer, a first polysilicon layer, a second insulator layer, a second polysilicon layer, a protective layer and sidewalls. The source and drain are disposed on the semiconductor substrate. The first insulator layer is disposed over a region of the semiconductor substrate other than regions corresponding to the source and drain. The first polysilicon layer is disposed over the first insulator layer, forming a floating gate. The second insulator layer is disposed over the first polysilicon layer. The second polysilicon layer is disposed over the second insulator layer, forming a control gate and a wordline. The sidewalls are disposed on two sides of the wordline, and the protective layer is disposed over the second polysilicon layer. A semiconductor junction at a drain region is a P-N junction, while a semiconductor junction at a source region is a metal-semiconductor junction.10-25-2012
20110227139NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF, SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF, AND MANUFACTURING METHOD OF INSULATING FILM - An object is to provide a technique to manufacture an insulating film having excellent film characteristics. In particular, an object is to provide a technique to manufacture a dense insulating film with a high withstand voltage. Moreover, an object is to provide a technique to manufacture an insulating film with few electron traps. An insulating film including oxygen is subjected to plasma treatment using a high frequency under the conditions where the electron density is 1×1009-22-2011
20120280303NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a first trench extending in a first direction is formed in a stacked structure in which a plurality of spacer films and a plurality of channel semiconductor films are alternately stacked. A first space is formed by forming a recess in the channel semiconductor films from the first trench. A tunnel dielectric film is formed in the first space, and the first space is further filled with a floating gate electrode film. Second trenches that divide the stacked structure at predetermined interval in the first direction are formed so as to divide the floating gate electrode film between memory cells adjacent to each other in the first direction but not to divide the channel semiconductor films.11-08-2012
20120280304NON-VOLATILE MEMORY DEVICE HAVING A VERTICAL STRUCTURE AND METHOD OF FABRICATING THE SAME - A non-volatile memory device having a vertical structure includes a semiconductor layer, a sidewall insulation layer extending in a vertical direction on the semiconductor layer, and having one or more protrusion regions, first control gate electrodes arranged in the vertical direction on the semiconductor layer, and respectively contacting one of portions of the sidewall insulation layer where the one or more protrusion regions are not formed and second control gate electrodes arranged in the vertical direction on the semiconductor layer, and respectively contacting one of the one or more protrusion regions.11-08-2012
20110284944NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A MONOS type non-volatile semiconductor memory device which is capable of electrically writing, erasing, reading and retaining data, the memory device including source/drain regions, a first gate insulating layer, a first charge trapping layer formed on the first gate insulating layer, a second gate insulating layer formed on the first charge trapping layer, and a controlling electrode formed on the second gate insulating layer. The first charge trapping layer includes an insulating film containing Al and O as major elements and having a defect pair formed of a complex of an interstitial O atom and a tetravalent cationic atom substituting for an Al atom, the insulating film also having electron unoccupied levels within the range of 2 eV-6 eV as measured from the valence band maximum of Al11-24-2011
20110291174NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - In one embodiment, a nonvolatile semiconductor memory device includes a substrate, and a well region formed in the substrate. The device further includes device regions formed in the well region and defined by isolation trenches formed in the well region, the device regions extending in a first direction parallel to a principal surface of the substrate, and being adjacent to one another in a second direction that is perpendicular to the first direction. The device further includes isolation insulators buried in the isolation trenches to isolate the device regions from one another. The device further includes floating gates disposed on the device regions via gate insulators, and a control gate disposed on the floating gates via an intergate insulator. The device further includes first diffusion suppressing layers formed inside the respective device regions to divide each of the device regions into an upper device region and a lower device region. The device further includes second diffusion suppressing layers formed on side surfaces of the respective upper device regions, the side surfaces being perpendicular to the second direction.12-01-2011
20130020628PROCESS FOR FABRICATING A TRANSISTOR COMPRISING NANOCRYSTALS - A process for fabricating a transistor may include forming source and drain regions in a substrate, and forming a floating gate having electrically conductive nanoparticles able to accumulate electrical charge. The process may include deoxidizing part of the floating gate located on the source side, and oxidizing the space resulting from the prior deoxidation so as to form an insulating layer on the source side.01-24-2013
20130020629SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor memory device includes a plurality of word lines formed on a semiconductor substrate at predetermined intervals, selecting transistors arranged on at least one side of the plurality of word lines, an interlayer insulating film formed to cover upper surfaces of the word lines and the selecting transistors, a first air gap located between each pair of adjacent ones of the word lines and covered by the interlayer insulating film, a second air gap located at a first side wall portion of a word line adjacent to the selecting transistors covered by the interlayer insulating film, the first side wall portion facing the selecting transistors, and a third air gap located at a second side wall portion of each of the selecting transistors and covered by the interlayer insulating film. The first, second, and third air gaps are filled with air.01-24-2013
20130020627SHIFT REGISTER MEMORY AND METHOD OF MANUFACTURING THE SAME - In one embodiment, a shift register memory includes first and second control electrodes extending in a first direction parallel to a surface of a substrate, and facing each other in a second direction perpendicular to the first direction. The memory further includes a plurality of first floating electrodes provided in a line on a first control electrode side between the first and second control electrodes. The memory further includes a plurality of second floating electrodes provided in a line on a second control electrode side between the first and second control electrodes. Each of the first and second floating electrodes has a planar shape which is mirror-asymmetric with respect to a plane perpendicular to the first direction.01-24-2013
20100213529SEMICONDUCTOR FIELD-EFFECT TRANSISTOR, MEMORY CELL AND MEMORY DEVICE - Semiconductor device formed by a first conductive strip of semiconductor material; a control gate region of semiconductor material, facing a channel portion of the first conductive strip, and an insulation region arranged between the first conductive strip and the control gate region. The first conductive strip includes a conduction line having a first conductivity type and a control line having a second conductivity type, arranged adjacent and in electrical contact with each other, and the conduction line forms the channel portion, a first conduction portion and a second conduction portion arranged on opposite sides of the channel portion.08-26-2010
20130009231Method for Efficiently Fabricating Memory Cells with Logic FETs and Related Structure - According to one exemplary embodiment, a method for concurrently fabricating a memory region with a logic region in a common substrate includes forming a lower dielectric segment in the common substrate in the memory and logic regions. The method also includes forming a polysilicon segment over the lower dielectric segment in the memory region, while concurrently forming a sacrificial polysilicon segment over the lower dielectric segment in the logic region. Furthermore, the method includes removing from the logic region the lower dielectric segment and the sacrificial polysilicon segment. The method additionally includes forming a high-k segment in the logic region over the common substrate, and in the memory region over the polysilicon segment and forming a metal segment over the high-k segment in the logic and memory regions. An exemplary structure achieved by the described exemplary method is also disclosed.01-10-2013
20130015517Semiconductor Memory Device Having Electrically Floating Body Transistor, Semiconductor Memory Device Having Both Volatile and Non-Volatile Functionality and Method of Operating - A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; and a gate positioned between said first and second regions. The cell may be a multi-level cell. Arrays of memory cells are disclosed for making a memory device. Methods of operating memory cells are also provided.01-17-2013
20130015516ASYMMETRICAL NON-VOLATILE MEMORY CELL AND METHOD FOR FABRICATING THE SAMEAANM Kim; Sang Y.AACI KulimAACO MYAAGP Kim; Sang Y. Kulim MYAANM Lee; Sang H.AACI KulimAACO MYAAGP Lee; Sang H. Kulim MYAANM May; Norhafizah CheAACI KulimAACO MYAAGP May; Norhafizah Che Kulim MY - The asymmetrical non-volatile memory cell is provided on a substrate of first conductivity type and comprises a control region and a floating region, wherein the control region is adjacent to the floating region and isolated from the floating region. The control region further comprises an implant region, having second conductivity type, disposed entirely across the control region and a polycrystalline silicon control gate disposed entirely over the implant region. The floating region further comprises a first voltage state of a drain implant region and a second voltage state of a source implant region, both having second conductivity type, the first voltage state is different from the second voltage state, a channel region that separates the drain implant region and the source implant region, and a polycrystalline silicon floating gate disposed entirely over the channel region and at least partially over the source implant region and drain implant region.01-17-2013
20110147821NON-VOLATILE TWO-TRANSISTOR PROGRAMMABLE LOGIC CELL AND ARRAY LAYOUT - A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.06-23-2011
20130020626MEMORY CELL WITH DECOUPLED CHANNELS - A device having a substrate prepared with a memory cell region having a memory cell is disclosed. The memory cell includes an access transistor and a storage transistor. The access transistor includes first and second source/drain (S/D) regions and the storage transistor includes first and second storage S/D regions. The access and storage transistors are coupled in series and the second S/D regions being a common S/D region. An erase gate is disposed over the common S/D region. A program gate is disposed over the first storage S/D region. Such an arrangement of the memory cell decouples a program channel and an erase channel.01-24-2013
20120241836SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - According to one embodiment, a method of manufacturing a semiconductor device including a memory cell transistor in a first region of a substrate and a select gate transistor in a second region of the substrate includes: forming a gate insulating film, a lower gate electrode, an inter-electrode insulating film, an upper gate electrode, and a hard mask on the substrate; forming a groove passing through the hard mask, the upper gate electrode, and the inter-electrode insulating film and reaching the lower gate electrode in the second region; and forming a connection layer having a crystal structure which preferentially has a specific crystal orientation and that electrically connects between the lower gate electrode and the upper gate electrode by being selectively crystal-grown while being subjected to an influence from a crystal structure of the lower gate electrode in the groove09-27-2012
20120241835NONVOLATILE SEMICONDUCTOR MEMORY DEVICE INCLUDING RESISTIVE ELEMENT - According to one embodiment, a second conductive layer is provided on a second insulating film and connected to a first conductive layer via an opening portion in the second insulating film. A first contact is connected to the second conductive layer. A third conductive layer is provided on the second insulating film and connected to the first conductive layer via an opening portion in the second insulating film. A second contact is connected to the third conductive layer. A fourth conductive layer is provided on the second insulating film and connected to the first conductive layer via an opening portion in the second insulating film. A third contact is connected to the fourth conductive layer. The floating gate layer and the first conductive layer are made of the same material, and the control gate layer, the second, third and fourth conductive layers are made of the same material.09-27-2012
20120241839SPLIT-GATE NON-VOLATILE MEMORY CELLS HAVING IMPROVED OVERLAP TOLERANCE - Embodiments include a split-gate non-volatile memory cell that is formed having a control gate and a select gate, where at least a portion of the control gate is formed over the select gate. A charge storage layer is formed between the select gate and the control gate. The select gate is formed using a first conductive layer and a second conductive layer. The second conductive layer is formed over the first conductive layer and has a lower resistivity than the first conductive layer. In one embodiment, the first conductive layer is polysilicon and the second conductive layer is titanium nitride (TiN). In another embodiment, the second conductive layer may be a silicide or other conductive material, or combination of conductive materials having a lower resistivity than the first conductive layer.09-27-2012
20120241838SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor storage device includes: a plurality of word lines that are formed at predetermined intervals in a first direction on the element region; a select gate transistor that is arranged in each of both sides of the word lines and has a width in the first direction wider than the word line; a first air gap that is positioned between the word lines; and a second air gap that is formed on a side wall portion opposite to a side of the word line of the select gate transistor. Further, according to one embodiment, the semiconductor storage device is provided in which an oxide film is formed on a surface of a substrate between the select gate transistors that are adjacent to each other, and a cross-sectional surface in a direction perpendicular to the first direction under the oxide film has a convex shape.09-27-2012
20120241837NON-VOLATILE MEMORY HAVING CHARGE STORAGE LAYER AND CONTROL GATE - According to one embodiment, a non-volatile memory includes a first non-volatile memory cell and a first selected transistor. A first cell block is formed by connecting a plurality of first non-volatile memory cells in series. An area S1 of the first insulating film at which the first floating gate is in contact with the first silicon channel is larger than an area S2 of the second insulating film at which the first floating gate is in contact with the first gate electrode.09-27-2012
20120241834SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes interconnects extending from a element formation area to the drawing area, and connected with semiconductor elements in the element formation area and connected with contacts in the drawing area. The interconnects are formed based on a pattern of a (n+1)09-27-2012
20080237687Flash memory device - Provided is a flash memory device including a gate structure on a substrate. The flash memory device includes a charge supply layer including a ZnO based material formed between a substrate and a gate structure or formed on the gate structure. Accordingly, the flash memory device can be formed to be of a bottom gate type or of a top gate type by including the charge supply layer. Also, the flash memory device may be realized to be any of a charge trap type and a floating gate type.10-02-2008
20080237686SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes: a control gate electrode having a first layer of polycrystalline silicon. The first layer is formed by decreasing a thickness of a first film of doped polycrystalline silicon. The first layer retains a dopant activation ratio of the first film. A method for manufacturing a semiconductor device, includes: forming a first film of doped polycrystalline silicon; and decreasing a thickness of the first film. The first film is formed by heat treating an amorphous silicon film provided on an insulating film.10-02-2008
20080237683HIGH-K TRILAYER DIELECTRIC DEVICE AND METHODS - Methods and structures are described for reducing a gate leakage current and increasing gate coupling ratio in a semiconductor device. In some embodiments, nitride layers are used to limit the oxidation of adjacent silicon gate regions due to oxygen in an intermediate insulator. In various embodiments, the intermediate insulator includes a high-κ dielectric material. Apparatus according to embodiments of the invention are also disclosed.10-02-2008
20080224200METHOD OF FABRICATING NAND-TYPE FLASH EEPROM WITHOUT FIELD OXIDE ISOLATION - Methods are described for fabricating NAND-type EEPROMs without field oxide isolation. P+ implantations are employed to isolate adjacent memory cells.09-18-2008
20130175597NANOWIRE FLOATING GATE TRANSISTOR - A floating gate transistor, memory cell, and method of fabricating a device. The floating gate transistor includes one or more gated wires substantially cylindrical in form. The floating gate transistor includes a first gate dielectric layer at least partially covering the gated wires. The floating gate transistor further includes a plurality of gate crystals discontinuously arranged upon the first gate dielectric layer. The floating gate transistor also includes a second gate dielectric layer covering the plurality of gate crystals and the first gate dielectric layer.07-11-2013
20130181276NON-SELF ALIGNED NON-VOLATILE MEMORY STRUCTURE - A non-self aligned non-volatile memory structure includes a semiconductor substrate; a first gate insulation layer on said semiconductor substrate; a floating gate on first gate insulation layer; two doped regions in said semiconductor substrate, which are respectively on two sides of said first gate insulation layer, and adjoining said first gate insulation layer; a second gate insulation layer on said floating gate; and a control gate on said second gate insulation layer. Width of said control gate on said floating gate is less than that of said floating gate, and width of said control gate not on said floating gate is equal to or greater than width of said floating gate. Through the two non-self aligned gates, the non-volatile memory does not need to meet the requirement of gate line-to-line alignment, thus reducing complexity and cost of manufacturing process.07-18-2013
20080217674SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATION OF THE SAME - A semiconductor memory device includes a first memory cell transistor. The first memory cell transistor includes a tunnel insulation film provided on a semiconductor substrate, a floating electrode provided on the tunnel insulation film, an inter-gate insulation film provided on the floating electrode, and a control electrode provided on the inter-gate insulation film. The floating electrode includes a first floating electrode provided on the tunnel insulation film and a second floating electrode provided on one end portion of the first floating electrode, the floating electrode having an L-shaped cross section in a wiring direction of the control electrode.09-11-2008
20120248524NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND PROCESS OF MANUFACTURING THE SAME - In device isolation trenches, a first device-isolation insulator film is formed to have recesses thereon and a second device-isolation insulator film is formed in the recesses. The uppermost portions at both ends of the first device-isolation insulator film are located higher than the uppermost portions at both ends of the second device-isolation insulator film.10-04-2012
20130134495FLASH MEMORY AND METHOD FOR FORMING THE SAME - A flash memory cell is provided. The flash memory cell includes: a substrate with a source line thereon; a word line and a word line dielectric layer on each side of the source line; an isolating dielectric layer which isolates the source line from the word line and the word line dielectric layer on each side of the source line; a gate stack on an outer side of each word line dielectric layer, including a floating gate dielectric layer, a floating gate, a control gate dielectric layer and a control gate; a first spacer, disposed on an outer sidewall of each word line dielectric layer and on each control gate; and a source region in the substrate and in contact with the source line. The space may be saved and the costs may be reduced.05-30-2013
20130134494SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - A semiconductor device includes a metal pattern filling a trench formed through at least a portion of an insulating interlayer on a substrate and including copper, and a wetting improvement layer pattern in the metal pattern including at least one of tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, cobalt and manganese.05-30-2013
20130113031KINK POLY STRUCTURE FOR IMPROVING RANDOM SINGLE BIT FAILURE - A memory cell having a kinked polysilicon layer structure, or a polysilicon layer structure with a top portion being narrower than a bottom portion, may greatly reduce random single bit (RSB) failures and may improve high density plasma (HDP) oxide layer fill-in by reducing defects caused by various impurities and/or a polysilicon layer short path. A kinked polysilicon layer structure may also be applied to floating gate memory cells either at the floating gate structure or the control gate structure.05-09-2013
20130119453NON-VOLATILE MEMORY UNIT CELL WITH IMPROVED SENSING MARGIN AND RELIABILITY - A non-volatile memory unit cell includes a transistor pair, and first, second, third and fourth control gates. The transistor pair has a first transistor and a second transistor that are connected in parallel and of opposite types. The first transistor and the second transistor have a first floating polysilicon gate and a second floating polysilicon gate, respectively, wherein the first floating polysilicon gate and the second floating polysilicon gate are electrically or physically isolated. The first control gate is capacitively coupled to the first floating polysilicon gate through a first coupling junction. The second control gate is capacitively coupled to the second floating polysilicon gates through a second coupling junction. The third control gate is capacitively coupled to the first floating polysilicon gate through a first tunneling junction. The fourth control gate is capacitively coupled to the second floating polysilicon gates through a second tunneling junction.05-16-2013
20110272755SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device comprising a first insulating film provided on a semiconductor substrate in a cell transistor region, a first conductive film provided on the first insulating film, an inter-electrode insulating film provided on the first conductive film, a second conductive film provided on the inter-electrode insulating film and having a first metallic silicide film on a top surface thereof, first source/drain regions formed on a surface of the semiconductor substrate, a second insulating film provided on the semiconductor substrate in at least one of a selection gate transistor region and a peripheral transistor region, a third conductive film provided on the second insulating film and having a second metallic silicide film having a thickness smaller than a thickness of the first metallic silicide film on a top surface thereof, and a second source/drain regions formed on the surface of the semiconductor substrate.11-10-2011
20100276744NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A non-volatile memory device includes a peripheral circuit region and a cell region. A method for fabricating the non-volatile memory device includes forming gate patterns over a substrate, the gate pattern including a tunnel insulation layer, a floating gate electrode, a charge blocking layer and a control gate electrode, and removing the control gate electrode and the charge blocking layer of the gate pattern formed in the peripheral circuit region.11-04-2010
20080203461GATE STRUCTURE OF NAND FLASH MEMORY HAVING INSULATORS EACH FILLED WITH BETWEEN GATE ELECTRODES OF ADJACENT MEMORY CELLS AND MANUFACTURING METHOD THEREOF - A semiconductor device includes first and second gate electrodes arranged adjacent to each other, an oxide film formed between the first and second gate electrodes, and a nitride film formed on control gates and upper surfaces and sidewalls of the oxide film. Each of the first and second gate electrodes has a stacked gate structure which has a first insulating film, charge storage layer, second insulating film and control gate stacked on a semiconductor substrate. The uppermost surface of the oxide film is set higher than the uppermost surface of the control gate.08-28-2008
20130146963METHODS OF FORMING NON-VOLATILE MEMORY - Methods of forming non-volatile memory is described. The non-volatile memory includes a substrate having a source region, a drain region and a channel region. The channel region separates the source region and the drain region. An electrically insulating layer is adjacent to the source region, drain region and channel region. A floating gate electrode is adjacent to the electrically insulating layer. The electrically insulating layer separates the floating gate electrode from the channel region. The floating gate electrode has a floating gate major surface. A control gate electrode has a control gate major surface and the control gate major surface opposes the floating gate major surface. A vacuum layer or gas layer at least partially separates the control gate major surface from the floating gate major surface.06-13-2013
20080197402Methods of Forming Nonvolatile Memory Devices and Memory Devices Formed Thereby - Methods of forming non-volatile memory devices include forming a device isolation layer and a gate pattern of a non-volatile memory cell transistor, on a semiconductor substrate. This gate pattern includes a floating gate electrode and a control gate line that extends on the floating gate electrode and on the device isolation layer. At least a first portion of a first sidewall of the gate pattern is then covered with a first mask that exposes upper corners of the control gate line. The device isolation layer is then selectively etched at a first rate to define an at least partial opening therein. During this etching step, the upper corners of the control gate line are also etched back at a second rate less than the first rate.08-21-2008
20080197401NONVOLATILE MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - A method of manufacturing a nonvolatile memory device is provided. The method includes forming an isolation layer in a semiconductor substrate defining an active region and forming a molding pattern on the isolation layer. A first conductive layer is formed on a sidewall and a top surface of the molding pattern and on the semiconductor substrate. The first conductive layer on the top surface of the molding pattern is selectively removed forming a conductive pattern. The conductive pattern includes a body plate disposed on the active region and a protrusion which extends from an edge of the body plate onto the sidewall of the molding pattern. The molding pattern is then removed. An inter-gate dielectric layer is formed on the isolation layer and the conductive pattern. Nonvolatile memory devices manufactured using the method are also provided.08-21-2008
20110220984SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to an aspect of the invention, there is provided a semiconductor device including a plurality of memory cells, comprising a plurality of floating gate electrodes which are formed on a tunnel insulating film formed on a semiconductor substrate and have an upper portion which is narrower in a channel width direction than a lower portion, an interelectrode insulating film formed on the floating gate electrodes, and a control gate electrode which is formed on the interelectrode insulating film formed on the floating gate electrodes and partially buried between the floating gate electrodes opposing each other.09-15-2011
20110220983METHOD FOR DELETING DATA FROM NAND TYPE NONVOLATILE MEMORY - To provide a method of releasing charges which have been injected into charge accumulating layers of nonvolatile memory elements without using a substrate terminal such as a p well or an n well, as a method for deleting data from a NAND-type nonvolatile memory. In the method for deleting data from the NAND-type nonvolatile memory, charges stored in a charge accumulating layer of a first nonvolatile memory element are released by applying a first potential to a bit line and a source line, a second potential to a control gate of the first nonvolatile memory element, and a third potential which is different from the second potential to a control gate of a second nonvolatile memory element.09-15-2011
20110241096ISOLATION REGIONS - Methods and apparatus are provided. An isolation region is formed by lining a trench formed in a substrate with a first dielectric layer by forming the first dielectric layer adjoining exposed substrate surfaces within the trench using a high-density plasma process, forming a layer of spin-on dielectric material on the first dielectric layer so as to fill a remaining portion of the trench, and densifying the layer of spin-on dielectric material.10-06-2011
20080237685Semiconductor memory device, method of fabricating the same, and devices employing the semiconductor memory device - In one embodiment, the semiconductor memory device includes a semiconductor substrate having projecting portions, a tunnel insulation layer formed over at least one of the projecting semiconductor substrate portions, and a floating gate structure disposed over the tunnel insulation layer. An upper portion of the floating gate structure is wider than a lower portion of the floating gate structure, and the lower portion of the floating gate structure has a width less than a width of the tunnel insulating layer. First insulation layer portions are formed in the semiconductor substrate and project from the semiconductor substrate such that the floating gate structure is disposed between the projecting first insulation layer portions. A dielectric layer is formed over the first insulation layer portions and the floating gate structure, and a control gate is formed over the dielectric layer.10-02-2008
20110248328STUCTURE FOR FLASH MEMORY CELLS - A semiconductor structure is provided. The semiconductor structure includes a first floating gate on the semiconductor substrate, the floating gate having a concave side surface; a first control gate on the first floating gate; a first spacer adjacent to the first control gate; a first word line adjacent a first side of the first floating gate with a first distance; and an erase gate adjacent a second side of the first floating gate with a second distance less than the first distance, the second side being opposite the first side.10-13-2011
20130146962SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a plurality of first trenches having a first depth formed in a semiconductor substrate, a plurality of second trenches having a second depth formed in the semiconductor substrate, wherein the second depth is different from the first depth and the second trenches are formed between the first trenches, a plurality of isolation layers formed at the plurality of first trenches and the plurality of second trenches, wherein the isolation layers have upper portions formed above the semiconductor substrate, and a plurality of memory cells formed over the semiconductor substrate between the isolation layers.06-13-2013
20100308395Nonvolatile Memory Device and Method of Manufacturing the Same - A method of manufacturing a nonvolatile memory device comprises forming a gate insulating layer and a first conductive layer over a semiconductor substrate that defines a first area in which selection lines will be formed and a second area in which word lines will be formed, performing an etch process to lower a height of the first conductive layer in the first area, forming a dielectric layer and a second conductive layer over the first conductive layer with a height that is different from the height of the first conductive layer, and performing a gate patterning process to form the selection lines and the word lines.12-09-2010
20100308393SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device including a semiconductor substrate having an active region isolated by an element isolation insulating film; a floating gate electrode film formed on a gate insulating film residing on the active region; an interelectrode insulating film formed above an upper surface of the element isolation insulating film and an upper surface and sidewalls of the floating gate electrode film, the interelectrode insulating film being configured by multiple film layers including a high dielectric film having a dielectric constant equal to or greater than a silicon nitride film; a control gate electrode film formed on the interelectrode insulating film; and a silicon oxide film formed between the upper surface of the floating gate electrode film and the interelectrode insulating film; wherein the high dielectric film of the interelectrode insulating film is placed in direct contact with the sidewalls of the floating gate electrode film.12-09-2010
201202738653-D NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A three dimensional (3-D) non-volatile memory device includes a pipe gate including a first pipe gate, a second pipe gate formed on the first pipe gate, and a first interlayer insulating layer interposed between the first pipe gate and the second pipe gate, word lines alternately stacked with second interlayer insulating layers on the pipe gate, a pipe channel buried within the pipe gate, and memory cell channels coupled to the pipe channel and arranged to pass through the word lines and the second interlayer insulating layers.11-01-2012
20130187216NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - Provided is a P-channel non-volatile semiconductor memory device with improved write characteristics. In the P-channel non-volatile semiconductor memory device, a resistive element is formed and connected to a control gate. A delay effect of the resistive element connected to the control gate is utilized to increase a potential of the control gate so as to cancel out a decrease in floating gate potential caused by hot electrons injected by writing. This can prevent the weakening of an electric field between a pinch-off point and a drain, which leads to a decrease in amount of generated DAHEs in writing. Thus, write characteristics can be improved.07-25-2013
20110233642SEMICONDUCTOR DEVICE - One or more embodiments relate to a memory device, comprising: a substrate; a gate stack disposed over the substrate, the gate stack comprising a control gate disposed over a charge storage layer; and a spacer select gate disposed over the substrate and laterally disposed from the gate stack, the select gate comprising a carbon allotrope.09-29-2011
20110233641NON-VOLATILE MEMORY CELL DEVICES AND METHODS - A method of fabricating a memory cell including forming nanodots over a first dielectric layer and forming an intergate dielectric layer over the nanodots, where the intergate dielectric layer encases the nanodots. To form sidewalls of the memory cell, a portion of the intergate dielectric layer is removed with a dry etch, where the sidewalls include a location where a nanodot has been deposited. A spacing layer is formed over the sidewalls to cover the location where a nanodot has been deposited and the remaining portion of the intergate dielectric layer and the nanodots can be removed with an etch selective to the intergate dielectric layer.09-29-2011
20110233640SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SEMICONDUCTOR DEVICE - In one embodiment, a semiconductor device includes a substrate; a gate insulating film; first trenches in a cell array region; first embedded insulating films in the first trenches; second trenches in a peripheral circuit region; second embedded insulating films in the second trenches; a third trench in an isolation region; a third embedded insulating film in the third trench; gate structures; and inter-gate insulating films between the gate structures covering the first, second and third embedded insulating films. An upper surface of the third embedded insulating film covered with the inter-gate insulating film is substantially flat. Upper surfaces of the first, second, and third embedded insulating films are higher than an upper surface of the gate insulating film. The upper surfaces of the first and third embedded insulating films are lower than the upper surfaces of the second embedded insulating films.09-29-2011
20110233639SEMICONDUCTOR DEVICE - To improve performance of a semiconductor device having a nonvolatile memory. Further to improve reliability of the semiconductor device. Furthermore, to improve performance of a semiconductor device as well as improving reliability of the semiconductor device.09-29-2011
20130153980NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A nonvolatile semiconductor storage device manufacturing method including forming a gate insulating film, a first silicon film, an inter-electrode insulating film, a second silicon film, and a processing insulating film on a semiconductor substrate; embedding an inter-gate insulating film between the gate electrodes of the memory cell transistors and the selector gate transistors; detaching the processing insulating film to expose an upper surface of the second silicon film, and processing the inter-gate insulating film so that an upper surface of the inter-gate insulating film is substantially at the same level as the upper surface of the second silicon film; exposing an upper portion of the second silicon film by etching the inter-gate insulating film between the gate electrodes of two adjacent ones of the selector gate transistors down to a first depth while leaving a contact region of a first width between the gate electrodes; performing silicidation of the upper portion of the second silicon film of each of the gate electrodes; and forming an inter-layer insulating film after the silicidation.06-20-2013
20090090957Multi-valued mask ROM - A mask ROM is provided with a plurality of memory cells each including first and second nodes, and a transistor having a source and drain connected to the first and second nodes, respectively. A first memory cell out of the plurality of memory cells further includes a first resistive interconnection which provides an electrical connection between the first and second nodes. The resistance of the first resistive interconnection is adjusted depending on data stored onto the first memory cell.04-09-2009
20110298035MEMORY DEVICE TRANSISTORS - Method and device embodiments are described for fabricating MOSFET transistors in a semiconductor also containing non-volatile floating gate transistors. MOSFET transistor gate dielectric smiling, or bird's beaks, are adjustable by re-oxidation processing. An additional re-oxidation process is performed by opening a poly-silicon layer prior to forming an inter-poly oxide dielectric provided for the floating gate transistors.12-08-2011
20130119454NON-VOLATILE MEMORY SEMICONDUCTOR DEVICE - A technique capable of improving the reliability of a non-volatile memory semiconductor device is provided and, in particular, a technique capable of supplying electricity without fail to a memory gate electrode of split gate transistor is provided.05-16-2013
20110303963SEMICONDUCTOR DEVICES - A method of forming a semiconductor device includes forming line patterns on a substrate, the line patterns defining narrow and wide gap regions, forming spacer patterns in the narrow and wide gap regions on sidewalls of the line patterns, spacer patterns in the wide gap regions exposing an upper surface of the substrate, and spacer patterns in the narrow gap regions contacting each other to fill the narrow gap regions, forming an insulating interlayer to cover the spacer patterns and the line patterns, forming at least one opening through the insulating interlayer, the opening including at least one contact hole selectively exposing the upper surface of the substrate in the wide gap region, the contact hole being formed by using the spacer patterns in the narrow gap region as an etching mask, and forming a conductive pattern to fill the opening.12-15-2011
20110303962NON-VOLATILE MEMORY DEVICES WITH NON-UNIFORM FLOATING GATE COUPLING - A memory device includes a substrate having an active region defined therein that extends linearly along a first direction. The device also includes a select line on the substrate and extending along a second direction to perpendicularly cross the active region, first and second floating gate patterns on the active region and spaced apart along the first direction, and first and second dielectric patterns on respective ones of the first and second floating gate patterns. The device further includes first and second word lines on respective ones of the first and second dielectric patterns and extending in parallel with the select line along the first direction. A first area of overlap of the first word line with the first floating gate pattern and the first dielectric pattern is less than a second area of overlap of the second word line with the second floating gate pattern and the second dielectric pattern. The first word line may be disposed between the select line and the second word line.12-15-2011
20110309428SEMICONDUCTOR DEVICE - A semiconductor device includes a plurality of nonvolatile memory cells (12-22-2011
20110309427SWITCHING DEVICE AND TESTING APPARATUS - There is provided a switching device that electrically connects or disconnects a first terminal and a second terminal to/from each other. The switching device includes a semiconductor layer, a drain electrode that is formed in the semiconductor layer, where the drain electrode is connected to the first terminal, a source electrode that is formed in the semiconductor layer, where the source electrode is connected to the second terminal, a gate insulator that is formed on the semiconductor layer between the drain electrode and the source electrode, a floating gate that is formed on the gate insulator, where the floating gate retains a charge therein, and a tunnel gate that is formed on the floating gate, the tunnel gate supplying a tunnel current determined by a driving voltage applied thereto to charge or discharge the floating gate.12-22-2011
20110309426Metal Control Gate Structures And Air Gap Isolation In Non-Volatile Memory - High-density semiconductor memory utilizing metal control gate structures and air gap electrical isolation between discrete devices in these types of structures are provided. During gate formation and definition, etching the metal control gate layer(s) is separated from etching the charge storage layer to form protective sidewall spacers along the vertical sidewalls of the metal control gate layer(s). The sidewall spacers encapsulate the metal control gate layer(s) while etching the charge storage material to avoid contamination of the charge storage and tunnel dielectric materials. Electrical isolation is provided, at least in part, by air gaps that are formed in the row direction and/or air gaps that are formed in the column direction.12-22-2011
20110309425Air Gap Isolation In Non-Volatile Memory - Air gap isolation in non-volatile memory arrays and related fabrication processes are provided. Electrical isolation between adjacent active areas of a substrate can be provided, at least in part, by bit line air gaps that are elongated in a column direction between the active areas. At least one cap is formed over each isolation region, at least partially overlying air to provide an upper endpoint for the corresponding air gap. The caps may be formed at least partially along the sidewalls of adjacent charge storage regions. In various embodiments, selective growth processes are used to form capping strips over the isolation regions to define the air gaps. Word line air gaps that are elongated in a row direction between adjacent rows of storage elements are also provided.12-22-2011
20120286346SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a semiconductor substrate, a trench formed in an element isolating area of the semiconductor substrate, and a silicon oxide film that is embedded in the trench and contains an alkali metal element or alkali earth metal element.11-15-2012
20120012919NONVOLATILE FLASH MEMORY STRUCTURES INCLUDING FULLERENE MOLECULES AND METHODS FOR MANUFACTURING THE SAME - Embodiments of tunneling barriers and methods for same can embed molecules exhibiting a monodispersion characteristic into a dielectric layer (e.g., between first and second layers forming a dielectric layer). In one embodiment, by embedding C01-19-2012
20120018794NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE WITH INTRINSIC CHARGE TRAPPING LAYER - A non-volatile semiconductor memory device includes a substrate, a first gate formed on a first region of a surface of the substrate, a second gate formed on a second region of the surface of the substrate, a charge storage layer filled between the first gate and the second gate, a first diffusion region formed on a first side of the charge storage layer, and a second diffusion region formed opposite the charge storage layer from the first diffusion region. The first region and the second region are separated by a distance sufficient for forming a self-aligning charge storage layer therebetween.01-26-2012
20120018793Device structure and manufacturing method using HDP deposited using deposited source-body implant block - This invention discloses a semiconductor power device. The trenched semiconductor power device includes a trenched gate, opened from a top surface of a semiconductor substrate, surrounded by a source region encompassed in a body region near the top surface above a drain region disposed on a bottom surface of a substrate. The semiconductor power device further includes an implanting-ion block disposed above the top surface on a mesa area next to the body region having a thickness substantially larger than 0.3 micron for blocking body implanting ions and source ions from entering into the substrate under the mesa area whereby masks for manufacturing the semiconductor power device can be reduced.01-26-2012
20120018792NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a nonvolatile semiconductor memory device according to an embodiment, includes: forming a first insulating film on a semiconductor substrate; forming a charge trapping film on the first insulating film, the forming of the charge trapping film including; forming a first nitride layer on the first insulating film at a heat treatment temperature of 550° C. or higher, forming a first oxynitride layer on the first nitride layer by oxidizing a surface of the first nitride layer, and forming a second nitride layer on the first oxynitride layer; forming a second insulating film on the charge trapping film; and forming a control gate on the second insulating film.01-26-2012
20120018791FLASH MEMORY DEVICE AND MANUFACTURING METHOD OF THE SAME - A flash memory device includes a semiconductor substrate, a gate stack formed on the semiconductor substrate; a channel region below the gate stack; spacers outside the gate stack; and source/drain regions outside the channel region and in the semiconductor substrate, in which the gate stack includes a first gate dielectric layer on the channel region; a first conductive layer covering an upper surface of the first gate dielectric layer and inner walls of the spacers; a second gate dielectric layer covering a surface of the first conductive layer; and a second conductive layer covering a surface of the second gate dielectric layer. A method for manufacturing a flash memory device disclosed herein.01-26-2012
20130193505Memory Devices and Methods of Forming Memory Devices - Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures.08-01-2013
20120032248NONVOLATILE SEMICONDUCTOR MEMORY ELEMENT, NONVOLATILE SEMICONDUCTOR MEMORY, AND METHOD FOR OPERATING NONVOLATILE SEMICONDUCTOR MEMORY ELEMENT - According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory element including: a semiconductor substrate including: a source region; a drain region; and a channel region; a lower insulating film that is formed on the channel region; a charge storage film that is formed on the lower insulating film and that stores data; an upper insulating film that is formed on the charge storage film; and a control gate that is formed on the upper insulating film, wherein the upper insulating film includes: a first insulting film; and a second insulating film that is laminated with the first insulating film, and wherein the first insulating film is formed to have a trap level density larger than that of the second insulating film.02-09-2012
20120292684NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A non-volatile memory device includes a first storage layer making contact with a sidewall of an active region in an isolation trench and a second charge storage layer making contact with an opposite sidewall of the active region in the isolation trench, first and second tunnel insulation layers interposed between the first charge storage layer and the active region and between the second charge storage layer and the active region, a first charge blocking layer disposed over the first and second charge storage layers, and a control gate disposed over the first charge blocking layer.11-22-2012
20130207175NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - A nonvolatile semiconductor storage device including a first transistor comprising a first gate electrode including a charge storage layer, an interelectrode insulating film, and a control electrode layer; a second transistor comprising a second gate electrode including a lower electrode, an upper electrode, and an upper silicide portion above the upper electrode; and a third transistor comprising a third gate electrode including a lower electrode, an upper electrode, and an upper silicide portion above the upper electrode; wherein the lower electrodes of the second and the third gate electrodes have a first side and a second side taken along a length direction of the second and the third gate electrodes, the lower electrodes of the second and the third gate electrodes including a lower silicide portion in which at least the first side of the lower electrodes are partially silicided.08-15-2013
20130207176SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a gate pattern formed by patterning a tunnel insulating layer, a conductive film for a floating gate, a dielectric film, a conductive film for a control gate, and a gate metal film sequentially formed on a semiconductor substrate; a first barrier film formed on side walls of the gate metal film; and a second barrier film formed on an upper surface of the gate metal film.08-15-2013
20130207174SPLIT-GATE DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes a substrate; a storage element disposed over the substrate in a first region; a control gate disposed over the storage element; a high-k dielectric layer disposed on the substrate in a second region adjacent the first region; and a metal select gate disposed over the high-k dielectric layer and adjacent to the storage element and the control gate.08-15-2013

Patent applications in class With additional contacted control electrode

Patent applications in all subclasses With additional contacted control electrode