Inventors list

Assignees list

Classification tree browser

Top 100 Inventors

Top 100 Assignees


With floating gate electrode

Subclass of:

257 - Active solid-state devices (e.g., transistors, solid-state diodes)

257213000 - FIELD EFFECT DEVICE

257288000 - Having insulated electrode (e.g., MOSFET, MOS diode)

257314000 - Variable threshold (e.g., floating gate memory device)

Patent class list (only not empty are listed)

Deeper subclasses:

Class / Patent application numberDescriptionNumber of patent applications / Date published
257316000 With additional contacted control electrode 734
Entries
DocumentTitleDate
20130069134MEMORY INCLUDING TRANSISTORS WITH DOUBLE FLOATING GATE STRUCTURES - In a memory of an embodiment, first and second P-channel transistors are formed on a first semiconductor region, and each of the first and second P-channel transistors has a structure formed by stacking a first insulating film, a first floating gate, a second insulating film, a second floating gate, a third insulating film, and a first control gate in this order on the first semiconductor region. In the memory, first and second N-channel transistors are formed on a second semiconductor region, and each of the first and second N-channel transistors has a structure formed by stacking a fourth insulating film, a third floating gate, a fifth insulating film, a fourth floating gate, a sixth insulating film, and a second control gate in this order on the second semiconductor region.03-21-2013
201300435213-DIMENSIONAL NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a 02-21-2013
20090267129DIELECTRIC MULTILAYER STRUCTURES OF MICROELECTRONIC DEVICES AND METHODS FOR FABRICATING THE SAME - A dielectric multilayer structure of a microelectronic device, in which a leakage current characteristic and a dielectric constant are improved, is provided in an embodiment. The dielectric multilayer structure includes a lower dielectric layer, which is made of amorphous silicate (M10-29-2009
20080265301Self-aligned patterning method by using non-conformal film and etch back for flash memory and other semiconductor applications - A method for fabricating a memory device with a self-aligned trap layer which is optimized for scaling is disclosed. In the present invention, a non-conformal film is deposited over the charge trapping layer to form a thick film on top of the core source/drain region and a pinch off and a void or a narrow channel at the top of the STI trench. An etch is performed on the non-conformal film to open pinch-off or widen the narrow channel in the non-conformal. The trapping layer is then completely or partially etched between the core cells. The non-conformal film is removed. And a top oxide is formed. The top oxide converts the remaining trap layer to oxide if the trapping layer is partially etched and thus isolate the trap layer.10-30-2008
20100084699FLOTOX-TYPE EEPROM AND METHOD FOR MANUFACTURING THE SAME - A FLOTOX-TYPE EEPROM of the invention has a configuration wherein an N region 04-08-2010
20130037876SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a polysilicon film formed above a semiconductor substrate, and a silicide film of a metal formed on the polysilicon film. The semiconductor device of the embodiment includes an oxide film of the metal formed above the silicide film, and a film containing tungsten or molybdenum formed on the oxide film.02-14-2013
20130032871SEMICONDUCTOR DEVICE HAVING AIR GAP AND METHOD OF FABRICATING THE SAME - A semiconductor device includes tunneling insulating layers on active regions of a substrate, floating gate electrodes on the tunneling insulating layers, an isolation trench within the substrate and the isolation trench defines the active region, spaces the tunneling insulating layers, and isolates the floating gate electrodes. A bottom of the isolation trench is directly in contact with the substrate. The semiconductor device further includes a lower insulating layer on the floating gate electrodes, and a middle insulating layer, an upper insulating layer, and a control gate electrode stacked on the lower insulating layer. The lower insulating layer is configured to hermetically seal a top portion of the isolation trench to define and directly abut an air gap within the isolation trench.02-07-2013
20130032870METHODS OF FORMING A MULTI-TIERED SEMICONDUCTOR DEVICE AND APPARATUSES INCLUDING THE SAME - Methods of forming multi-tiered semiconductor devices are described, along with apparatuses that include them. In one such method, a silicide is formed in a tier of silicon, the silicide is removed, and a device is formed at least partially in a void that was occupied by the silicide. One such apparatus includes a tier of silicon with a void between tiers of dielectric material. Residual silicide is on the tier of silicon and/or on the tiers of dielectric material and a device is formed at least partially in the void. Additional embodiments are also described.02-07-2013
20130075803Flash-To-ROM Conversion - Flash-to-ROM conversion is performed by converting single transistor flash memory cells to single transistor ROM cells. An S-Flash memory cell is converted to a programmed ROM cell by introducing a threshold voltage implant into the channel region of the S-Flash memory cell. Alternately, an S-Flash memory cell is converted to a programmed ROM cell by introducing a threshold voltage implant into a substrate region in alignment with an edge of the gate electrode of the S-Flash memory cell. The width of the mask through which this threshold voltage implant is performed can be varied, such that the threshold voltage implant region can have different dopant concentrations, thereby allowing multiple bits to be represented by the programmed ROM cell. In another embodiment, a Y-flash memory cell is converted to a programmed ROM cell by adjusting the length of a floating gate extension region of the Y-Flash memory cell.03-28-2013
20130075804HIGH DENSITY SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - Provided are a high density semiconductor memory device capable of precisely reading data by suppressing the occurrence of a leakage current due to the high-integration of the semiconductor memory device, and a method for manufacturing the semiconductor memory device. The high density semiconductor memory device includes: source and drain electrodes disposed over a substrate, and forming a Schottky junction with a channel region; and a floating gate disposed over the substrate of the channel region, and configured with a plurality of nanodots. The nanodots may be formed of a silicon compound or any material that can be charged.03-28-2013
20130207173FLASH MEMORY AND METHOD FOR FABRICATING THE SAME - A flash memory and a method for fabricating the same are provided. The flash memory comprises: a semiconductor substrate; a storage medium layer formed on the semiconductor substrate and comprising from bottom to top: a tunneling oxide layer, a silicon nitride layer and a blocking oxide layer; a semiconductor layer formed on the storage medium layer and comprising a channel region and a source region and a drain region located on both sides of the channel region respectively; and a gate stack formed on the channel region and comprising a gate dielectric and a gateformed on the gate dielectric.08-15-2013
20100044771Zr-Sn-Ti-O FILMS - A dielectric layer containing a Zr—Sn—Ti—O film and a method of fabricating such a dielectric layer produce a reliable dielectric layer having an equivalent oxide thickness thinner than attainable using SiO02-25-2010
20100044770SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A method for fabricating a semiconductor device includes forming an insulation layer over a substrate, forming a diffusion barrier for preventing metal diffusion over the insulation layer, forming a gate electrode layer over the diffusion barrier, forming a metal layer over the gate electrode layer, and performing a thermal treatment process on the substrate structure to form a metal silicide layer having a uniform thickness.02-25-2010
20090159951FLASH MEMORY DEVICE - Embodiments relate to a flash memory device and a method of manufacturing a flash memory device, which may increase a coupling coefficient between a control gate and a floating gate by increasing a surface area of floating gate. In embodiments, a flash memory device may be formed by forming a photoresist pattern for forming a floating gate on a semiconductor substrate including an oxide film, a floating gate poly film, and a BARC (Bottom AntiReflect Coating), performing a first etching process using the photoresist pattern as a mask, to etch the floating gate poly film to a predetermined depth, depositing and forming a polymer to cover the photoresist pattern, forming spacers of the polymer at both sidewalls of the photoresist pattern, forming a second etching process using the spacers as a mask, to expose the oxide film, and removing the BARC, the photoresist pattern and the spacers by ashing and stripping.06-25-2009
20090159952METHOD OF FABRICATING NON-VOLATILE MEMORY INTEGRATED CIRCUIT DEVICE AND NON-VOLATILE MEMORY INTEGRATED CIRCUIT DEVICE FABRICATED USING THE SAME - A method of fabricating a non-volatile memory integrated circuit device and a non-volatile memory integrated circuit device fabricated by using the method are provided. A device isolation region is formed in a substrate to define a cell array region and a peripheral circuit region. A plurality of first and second pre-stacked gate structures is formed in the cell array region, and each has a structure in which a lower structure, a conductive pattern and a first sacrificial layer pattern are stacked. Junction regions are formed in the cell array region. Spacers are formed on side walls of the first and second pre-stacked gate structures. A second sacrificial layer pattern filling each space between the second pre-stacked gate structures is formed. The first sacrificial layer pattern is removed from each of the first and second pre-stacked gate structures. A damascene metal layer pattern is formed in each of spaces of the first and second pre-stacked gate structures from which the first sacrificial layer pattern is removed, thus completing first and second stacked gate structures. The second sacrificial layer pattern is removed. A stop layer is formed on top surfaces of the first stacked gate structures, top surfaces and side walls of the second stacked gate structures, and a top surface of the substrate.06-25-2009
20090159950Semiconductor Device and manufacturing Method of Semiconductor Device - A conductor pattern including a gate electrode and an auxiliary pattern spaced apart by a narrow gap is formed on a substrate, an insulating film for a gate insulating film is formed so as to cover the same, a resist film is formed thereon, and the resist film is exposed from a back surface side of the substrate. In the exposure, the conductor pattern functions as a mask, but a resolution is reduced so that the resist film cannot resolve the dimension of the gap, whereby a portion corresponding to the gap is not formed in the resist pattern after development. By the lift-off method using the resist pattern, the source and drain electrodes aligned with the gate electrode are formed. The shape of the source and drain electrodes can be adjusted to an arbitrary shape by adjusting the shape of the auxiliary pattern.06-25-2009
20130099300Floating Gate Structure of Flash Memory Device and Method for Fabricating the Same - The present invention discloses a floating gate structure of a flash memory device and a method for fabricating the same, which relates to a nonvolatile memory in a manufacturing technology of an ultra-large-scaled integrated circuit. In the invention, by modifying a manufacturing of a floating gate in the a standard process for the flash memory, that is, by adding three steps of deposition, two steps of etching and one step of CMP, an I-shaped floating gate is formed. In addition to these steps, all the other steps are the same as those of the standard process for the flash memory process. By the invention, a coupling ratio may be improved effectively and a crosstalk between adjacent devices may be lowered, without adding additional photomasks and barely increasing a process complexity, which are very important to improve programming speed and reliability.04-25-2013
20100109066COMMON DRAIN NON-VOLATILE MULTIPLE-TIME PROGRAMMABLE MEMORY - An array of programmable non-volatile devices use a floating gate that functions as a FET gate that overlaps a portion of a common source/drain region. This allows a programming voltage for the device to be imparted to the floating gate through capacitive coupling, thus changing the state of the device. The invention can be used in environments such as data encryption, reference trimming, manufacturing ID, security ID, and many other applications.05-06-2010
20110309423SEMICONDUCTOR DEVICE HAVING A TRENCH GATE AND METHOD FOR MANUFACTURING - A semiconductor device having a trench gate and method for manufacturing is disclosed. One embodiment includes a first semiconductor area and a second semiconductor area, a semiconductor body area between the first semiconductor area and the second semiconductor area, and a gate arranged in a trench and separated from the semiconductor body by an insulation layer, wherein the trench has a top trench portion which extends from the semiconductor surface at least to a depth which is greater than a depth of the first semiconductor area, wherein the trench further has a bottom trench portion extending subsequent to the top trench portion at least up to the second semiconductor area, and wherein the top trench portion has a first lateral dimension and the bottom trench portion has a second lateral dimension which is greater than the first lateral dimension.12-22-2011
20130082315SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device of the present invention has a first insulating film formed between a control gate electrode and a semiconductor substrate and a second insulating film formed between a memory gate electrode and the semiconductor substrate and between the control gate electrode and the memory gate electrode, the second insulating film having a charge accumulating part therein. The second insulating film has a first film, a second film serving as a charge accumulating part disposed on the first film, and a third film disposed on the second film. The third film has a sidewall film positioned between the control gate electrode and the memory gate electrode and a deposited film positioned between the memory gate electrode and the semiconductor substrate. In this structure, the distance at a corner part of the second insulating film can be increased, and electric-field concentration can be reduced.04-04-2013
20130082316THREE-DIMENSIONAL NONVOLATILE MEMORY DEVICES INCLUDING INTERPOSED FLOATING GATES - Provided are three-dimensional nonvolatile memory devices and methods of fabricating the same. The memory devices include semiconductor pillars penetrating interlayer insulating layers and conductive layers alternately stacked on a substrate and electrically connected to the substrate and floating gates selectively interposed between the semiconductor pillars and the conductive layers. The floating gates are formed in recesses in the conductive layers.04-04-2013
20100133599Nonvolatile memory device and method for fabricating the same - A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes.06-03-2010
20130087843SEMICONDUCTOR DEVICE AND CAPACITOR - The present invention relates to a semiconductor device including nanodots and a capacitor. A semiconductor device includes a channel layer, a tunnel insulating layer formed on the channel layer, a memory layer formed on the tunnel insulating layer and including first nanodots, a charge blocking layer formed on the memory layer, a gate electrode conductive layer formed on the charge blocking layer, and a buffer layer located, at least one of, inside the tunnel insulating layer, inside the charge blocking layer, at an interface between the tunnel insulating layer and the memory layer and at the interface between the charge blocking layer and the memory layer, wherein the buffer layer includes second nanodots.04-11-2013
20120217564SEMICONDUCTOR CHARGE STORAGE APPARATUS AND METHODS - Methods of forming multi-tiered semiconductor devices are described, along with apparatus and systems that include them. In one such method, an opening is formed in a tier of semiconductor material and a tier of dielectric. A portion of the tier of semiconductor material exposed by the opening is processed so that the portion is doped differently than the remaining semiconductor material in the tier. At least substantially all of the remaining semiconductor material of the tier is removed, leaving the differently doped portion of the tier of semiconductor material as a charge storage structure. A tunneling dielectric is formed on a first surface of the charge storage structure and an an intergate dielectric is formed on a second surface of the charge storage structure. Additional embodiments are also described.08-30-2012
20130161718INTEGRATED CIRCUIT DIE AND METHOD OF MAKING - Integrated circuit dies and methods of making dies are disclosed. An embodiment of a die includes at least one transistor gate, wherein the gate has an area. A conductor is connected to the gate, and wherein the conductor has an area. The area of the conductor is proportional to the area of the gate raised to a power, wherein the power is a function of the failure rate of the gate.06-27-2013
20120112260THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES - Provided are three-dimensional semiconductor devices. The device includes conductive patterns stacked on a substrate, and an active pattern penetrating the conductive patterns to be connected to the substrate. The active pattern includes a first doped region disposed adjacent to at least one of the conductive patterns, and a diffusion-resistant doped region overlapped with at least a portion of the first doped region. The diffusion-resistant doped region may be a region doped with carbon.05-10-2012
20090236651SEMICONDUCTOR DEVICES HAVING A CONVEX ACTIVE REGION - Methods of forming a semiconductor device include forming a trench mask pattern on a semiconductor substrate having active regions and device isolation regions. A thermal oxidation process is performed using the trench mask pattern as a diffusion mask to form a thermal oxide layer defining a convex upper surface of the active regions. The thermal oxide layer and the semiconductor substrate are etched using the trench mask pattern as an etch mask to form trenches defining convex upper surfaces of the active regions. The trench mask pattern is removed to expose the convex upper surfaces of the active regions. Gate patterns are formed extending over the active regions.09-24-2009
20100052031MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A memory device includes gate lines and select lines formed over a substrate, and at least two dummy lines formed in a gap region between adjacent select lines. The memory device is able to reduce a width of the select line by enhancing uniformity of the line pattern density. Therefore, a degree of integration of the memory device is enhanced and the cost of production is reduced. Furthermore, by forming a source line in a gap region between adjacent dummy lines, it is possible to secure a process margin of photolithography for forming a contact hole and to reduce contact resistance.03-04-2010
20090008697SRAM CELLS WITH REPRESSED FLOATING GATE MEMORY, LOW TUNNEL BARRIER INTERPOLY INSULATORS - Structures and methods are provided for SRAM cells having a novel, non-volatile floating gate transistor, e.g. a non-volatile memory component, within the cell which can be programmed to provide the SRAM cell with a definitive asymmetry so that the cell always starts in a particular state. The SRAM cells include a pair of cross coupled transistors. At least one of the cross coupled transistors includes a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposes the channel region and separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by a low tunnel barrier intergate insulator.01-08-2009
20090321807SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SYSTEM - A semiconductor device includes a semiconductor substrate, a first and second semiconductor regions formed on the semiconductor substrate insulated and separated from each other, a gate dielectric film formed on the substrate to overlap the first and second semiconductor regions, a floating gate electrode formed on the gate dielectric film and in which a coupling capacitance of the first semiconductor region is larger than that of the second semiconductor region, first source and drain layers formed on the first semiconductor region to interpose the floating gate electrode therebetween, a first and second wiring lines connected to the first source and drain layers, respectively, second source and drain layers formed on the second semiconductor region to interpose the floating gate electrode therebetween, and a third wiring line connected to the second source and drain layers in common.12-31-2009
20130207172TRENCH MOSFET HAVING A TOP SIDE DRAIN - This invention discloses a trench MOSFET comprising a top side drain region in a wide trench in a termination area besides a BV sustaining area, wherein said top side drain comprises a top drain metal connected to an epitaxial layer and a substrate through a plurality of trenched drain contacts, wherein the wide trench is formed simultaneously when a plurality of gate trenches are formed in an active area, and the trenched drain contacts are formed simultaneously when a trenched source-body contact is formed in the active area.08-15-2013
20110121378ZrXHfYSn1-X-YO2 FILMS AS HIGH K GATE DIELECTRICS - The use of atomic layer deposition (ALD) to form a nanolaminate dielectric of zirconium oxide (ZrO05-26-2011
20110133265MEMORY CELL - A memory cell has a tunnel dielectric over a first silicon-containing material, a second silicon-containing material over the tunnel dielectric, a first silicon oxide layer on an edge of the second silicon-containing material and extending across a first portion of an edge of the tunnel dielectric, and a second silicon oxide layer on a side of the first silicon-containing material and extending across a second portion of the edge of the tunnel dielectric. The first and second silicon oxide layers are two distinct layers and are in contact with the tunnel dielectric layer.06-09-2011
20090078982ALPHA HYDROXY CARBOXYLIC ACID ETCHANTS FOR SILICON MICROSTRUCTURES - α-Hydroxy carboxylic acid etchants for silicon microstructures are generally described. In one example, a method includes fabricating a protruding structure on a semiconductor substrate, the protruding structure comprising a first layer of silicon coupled with the semiconductor substrate, the first layer of silicon defining a bottom gate, a sacrificial layer of silicon germanium (SiGe) coupled with the first layer of silicon, and a second layer of silicon coupled with the layer of SiGe, fabricating a top gate that traverses the protruding structure, and selectively etching the sacrificial layer of SiGe using an etchant including hydrofluoric acid (HF), nitric acid (HNO03-26-2009
20120286345NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A non-volatile memory device includes a substrate including a cell region and a peripheral circuit region, a first insulation layer formed over the substrate to cover the peripheral circuit region thereof, and interlayer dielectric patterns and first conductive patterns alternately formed over the substrate of the cell region. Each of the interlayer dielectric patterns and the first conductive patterns includes a horizontal part extending along a surface of the substrate and a vertical part extending along a sidewall of the first insulation layer.11-15-2012
20100006915DIELECTRIC LAYER ABOVE FLOATING GATE FOR REDUCING LEAKAGE CURRENT - A memory system is disclosed that includes a set of non-volatile storage elements. A given memory cell has a dielectric cap above the floating gate. In one embodiment, the dielectric cap resides between the floating gate and a conformal IPD layer. The dielectric cap reduces the leakage current between the floating gate and a control gate. The dielectric cap achieves this reduction by reducing the strength of the electric field at the top of the floating gate, which is where the electric field would be strongest without the dielectric cap for a floating gate having a narrow stem.01-14-2010
20110291173SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The invention provides a semiconductor device and its manufacturing method in which a memory transistor and a plurality of thin film transistors that have gate insulating films with different thicknesses are fabricated over a substrate. The invention is characterized by the structural difference between the memory transistor and the plurality of thin film transistors. Specifically, the memory transistor and some of the plurality of thin film transistors are provided to have a bottom gate structure while the other thin film transistors are provided to have a top gate structure, which enables the reduction of characteristic defects of the transistor and simplification of its manufacturing process.12-01-2011
20100090265High density nanodot nonvolatile memory - A nanodot nonvolatile memory element comprises a substrate having a source and a drain region formed therein, and an insulating layer formed on the substrate. The insulating layer contains a nanocrystalline floating gate of approximately three to six nanometers in diameter formed at a distance of approximately two to five nanometers from the substrate, and a carbon nanotube control gate having a diameter of approximately six nanometers or less is formed at a distance of approximately 10-15 nanometers from the substrate.04-15-2010
20090014771SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device including a semiconductor substrate; a plurality of memory cell transistors aligned in a predetermined direction on the semiconductor substrate, each memory cell transistor provided with a first gate electrode including a floating gate electrode comprising a polycrystalline silicon layer of a first thickness, a control gate electrode provided above the floating gate electrode, and an inter-gate insulating film between the floating and the control gate electrode; a pair of select gate transistors on the semiconductor substrate with a pair of second gate electrodes neighboring in alignment with the first gate electrode, each second gate electrode including a lower-layer gate electrode comprising the polycrystalline silicon layer of the first thickness, an upper-layer gate electrode provided above the lower-layer gate electrode; a polyplug of the first thickness situated between the second gate electrodes of the pair of select gate transistors; and a metal plug provided on the polyplug.01-15-2009
20090121272FABRICATION METHOD OF NANOPARTICLES BY CHEMICAL CURING - Disclosed is a method of producing nanoparticles by using chemical curing. The method includes depositing a metal thin film on a substrate, applying an insulator precursor on a metal thin film, and adding a curing agent and a catalyst to the insulator precursor to perform the chemical curing. The method also includes mixing metal powder and an insulator precursor, applying a mixture on a substrate, and adding a curing agent and a catalyst to the mixture to perform the chemical curing. Since the chemical curing process is used in the method, it is possible to form nanoparticles by using a simple process at low cost while a high temperature process such as thermal curing is not used.05-14-2009
20090121271Vertical-type non-volatile memory devices - In a semiconductor device, and a method of manufacturing thereof, the device comprises a substrate of single-crystal semiconductor material extending in a horizontal direction and a plurality of interlayer dielectric layers on the substrate. A plurality of gate patterns are provided, each gate pattern being between a neighboring lower interlayer dielectric layer and a neighboring upper interlayer dielectric layer. A vertical channel of single-crystal semiconductor material extends in a vertical direction through the plurality of interlayer dielectric layers and the plurality of gate patterns, a gate insulating layer being between each gate pattern and the vertical channel that insulates the gate pattern from the vertical channel.05-14-2009
20120228691PN FLOATING GATE NON-VOLATILE STORAGE ELEMENT - Non-volatile storage elements having a PN floating gate are disclosed herein. The floating gate may have a P− region near the tunnel oxide, and may have an N+ region near the control gate. In some embodiments, a P− region near the tunnel oxide helps provide good data retention. In some embodiments, an N+ region near the control gate helps to achieve a good coupling ratio between the control gate and floating gate. Therefore, programming of non-volatile storage elements is efficient. Also erasing the non-volatile storage elements may be efficient. In some embodiments, having a P− region near the tunnel oxide (as opposed to a strongly doped p-type semiconductor) may improve erase efficiency relative to P+.09-13-2012
20080237681SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - This disclosure concerns a semiconductor device comprising: a bulk substrate; an insulation layer provided on the bulk substrate; a semiconductor layer containing an active area on which a semiconductor element is formed, and a dummy active area isolated from the active area and not formed with a semiconductor element thereon, the semiconductor layer being provided on the insulation layer; and a supporting unit provided beneath the dummy active area to reach the bulk substrate piercing through the insulation layer, the supporting unit supporting the dummy active area.10-02-2008
20090309149Memory cell arrangements and methods for manufacturing a memory cell arrangement - In an embodiment, a memory cell arrangement is provided which may include a charge storing memory cell comprising a first active area running along a first direction, a second active area disposed next to the charge storing memory cell, the second active area running along a second direction, the second direction being different from the first direction, and a select structure disposed above the second active area configured to control a current flow through the second active area.12-17-2009
20090101960SEMICONDUCTOR MEMORY DEVICE - According to an aspect of the present invention, there is provided a semiconductor memory device including: a semiconductor substrate having: a contact region; a select gate region; and a memory cell region; a first element isolation region formed in the contact region and having a first depth; a second element isolation region formed in the select gate region and having a second depth; and a third element isolation region formed in the memory cell region and having a third depth which is smaller than the first depth.04-23-2009
20080211004SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a silicon crystal layer on an insulating layer, the silicon crystal layer containing a crystal lattice mismatch plane, a memory cell array portion on the silicon crystal layer, the memory cell array portion including memory strings, each of the memory strings including nonvolatile memory cell transistors connected in series in a first direction, the memory strings being arranged in a second direction orthogonal to the first direction, the crystal lattice mismatch plane crossing the silicon crystal along the second direction without passing under gates of the nonvolatile memory cell transistors as viewed from a top of the silicon crystal layer, or crossing the silicon crystal along the first direction with passing under gates of the nonvolatile memory cell transistors as viewed from the top of the silicon crystal layer.09-04-2008
20090273013METHOD OF FORMING A SPLIT GATE MEMORY DEVICE AND APPARATUS - A split-gate memory device has a select gate having a first work function overlying a first portion of a substrate. A control gate having a second work function overlies a second portion of the substrate proximate the first portion. When the majority carriers of the split-gate memory device are electrons, the first work function is greater than the second work function. When the majority carriers of the split-gate memory device are holes, the first work function is less than the second work function. First and second current electrodes in the substrate are separated by a channel that underlies the control gate and select gate. The differing work functions of the control gate and the select gate result in differing threshold voltages for each gate to optimize device performance. For an N-channel device, the select gate is P conductivity and the control gate is N conductivity.11-05-2009
20090273014NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - Each of a memory gate, a control gate, a source diffusion layer, and a drain diffusion layer is connected to a control circuit for controlling potential, and the control circuit operates so as to supply a first potential to the memory gate, a second potential to the control gate, a third potential to the drain diffusion layer, and a fourth potential to the source diffusion layer. Here, after setting the memory gate to be in a floating state by shifting a switch transistor from an ON state to an OFF state, the control circuit operates so as to supply a sixth potential which is higher than the second potential to the control gate to make the memory gate have a fifth potential which is higher than the first potential, thereby boosting the memory gate.11-05-2009
20090008696SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FORMING THE SAME - According to one embodiment, a semiconductor memory device can be generally characterized as including a gate insulating layer on a semiconductor substrate, a floating gate on the gate insulating layer and a word line disposed on one side of the floating gate. A first side of the floating gate facing the word line may include a projecting portion projecting toward the word line. A tip of the projecting portion may include a corner that extends substantially perpendicularly with respect to a top surface of the semiconductor substrate.01-08-2009
20090008695SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device is provided. The semiconductor device comprises a substrate. A lamination structure is on the substrate along a first direction. The lamination structure comprises a plurality of conductive layers arranged from bottom to top and separated from each other, and each of the conductive layers has a channel region and an adjacent source/drain doped region along the first direction. A first gate structure is on a sidewall of the channel region of each conductive layer. The first gate structure comprises an inner first gate insulating layer and an outer first gate conductive layer.01-08-2009
20120292682Electrically Erasable Programmable Non-Volatile Memory - In an embodiment of the invention, a method of fabricating a floating-gate PMOSFET (p-type metal-oxide semiconductor field-effect transistor) is disclosed. A silicide blocking layer (e.g. oxide, nitride) is used not only to block areas from being silicided but to also form an insulator on top of a poly-silicon gate. The insulator along with a top electrode (control gate) forms a capacitor on top of the poly-silicon gate. The poly-silicon gate also serves at the bottom electrode of the capacitor. The capacitor can then be used to capacitively couple charge to the poly-silicon gate. Because the poly-silicon gate is surrounded by insulating material, the charge coupled to the poly-silicon gate may be stored for a long period of time after a programming operation.11-22-2012
20080246074Two-Bits Per Cell Not-And-Gate (NAND) Nitride Trap Memory - A non-volatile memory array includes a semiconductor substrate having a main surface, a first source/drain region and a second source/drain region. The second source/drain region is spaced apart from the first source/drain region. A well region is disposed in a portion of the semiconductor substrate between the first source/drain region and the second source/drain region. A plurality of memory cells are disposed on the main surface above the well region. Each memory cell includes a first oxide layer formed on the main surface of the substrate, a charge storage layer disposed above the blocking oxide layer relative to the main surface of the semiconductor substrate and second oxide layer disposed above the charge storage layer relative to the main surface of the semiconductor substrate. A plurality of wordlines are disposed above the second oxide layer relative to the main surface of the semiconductor substrate.10-09-2008
20080296652SPLIT GATE FLASH MEMORY CELL WITH BALLISTIC INJECTION - A split floating gate flash memory cell is comprised of source/drain regions in a substrate. The split floating gate is insulated from the substrate by a first layer of oxide material and from a control gate by a second layer of oxide material. The sections of the floating gate are isolated from each other by a depression in the control gate. The cell is programmed by creating a positive charge on the floating gate and biasing the drain region while grounding the source region. This creates a virtual source/drain region near the drain region such that the hot electrons are accelerated in the narrow pinched off region. The electrons become ballistic and are directly injected onto the floating gate section adjacent to the pinched off channel region.12-04-2008
20080283895Memory structure and fabricating method thereof - A memory structure including a substrate, dielectric patterns, spacer patterns, a first dielectric layer, a conductor pattern, a second dielectric layer and doped regions is described. The dielectric patterns are disposed on the substrate. The spacer patterns are disposed on each sidewall of each of the dielectric patterns respectively. The first dielectric layer is disposed between the spacer patterns and the substrate. The conductor pattern is disposed on the substrate and covers the spacer patterns. The second dielectric layer is disposed between the spacer patterns and the conductor pattern. The doped regions are disposed in the substrate under each of the dielectric patterns respectively.11-20-2008
20080303076Shallow Trench Isolation in Floating Gate Devices - The present invention provides a method for manufacturing a floating gate type semiconductor device on a substrate having a surface (12-11-2008
20090315096NON-VOLATILE MEMORY AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a non-volatile memory is provided. An insulating layer, a conductive material layer and a polish stop layer are sequentially on a substrate. Trenches are formed in a portion of the substrate, the polish stop layer, the conductive material layer and the insulating layer, and the conductive material layer is segmented to form conductive blocks. A dielectric material layer is formed to cover the polish stop layer and fill the trenches. A chemical mechanical polishing process is performed until exposing a surface of the polish stop layer. A portion of the dielectric layer is removed to form trench isolation structures. A portion of sidewalls of each conductive block is removed to form floating gates. A width of each floating gate is decreased gradually from bottom to top.12-24-2009
20080277711MEMORY CELL - A memory cell including a substrate with a protruding portion, the protruding portion having a side wall and a bottom, an upper doped region connected to a bit line, a lower region being closer to a bottom of the protruding portion than the upper region, a substrate contact, a control element configured to control a current flow between the lower region and the substrate contact, and a wordline portion, a first insulator near the wordline portion, a floating gate near the wordline portion, and a second insulator between the floating gate and the side wall of the protruding portion, wherein the wordline portion and the floating gate are arranged so that the channel is generateable in the substrate near the side wall between the upper doped region and the lower region.11-13-2008
20080277712Flash memory cell with a flair gate - An embodiment of the present invention is directed to a method of forming a memory cell. The method includes etching a trench in a substrate and filling the trench with an oxide to form a shallow trench isolation (STI) region. A portion of an active region of the substrate that comes in contact with the STI region forms a bitline-STI edge. The method further includes forming a gate structure over the active region of the substrate and over the STI region. The gate structure has a first width substantially over the center of the active region of the substrate and a second width substantially over the bitline-STI edge, and the second width is greater than the first width.11-13-2008
20080251832Logic compatible arrays and operations - An array of memory cells arranged in a plurality of rows and a plurality of columns are provided. The array includes a first program line in a first direction, wherein the first program line is connected to program gates of memory cells in a first row of the array; a first erase line in the first direction, wherein the first erase line is connected to erase gates of the memory cells in the first row of the array; and a first word-line in the first direction, wherein the first word-line is connected to word-line nodes of the memory cells in the first row of the array.10-16-2008
20080265302MEMORY STRUCTURE AND FABRICATING METHOD THEREOF - A memory structure including a substrate, a first dielectric layer, a first conducting layer, a second conducting layer, a second dielectric layer, a spacer and a doped region is provided. The substrate has a trench wherein. The first dielectric layer is disposed on the interior surface of the trench. The first conducting layer is disposed on the first dielectric layer of the lower portion of the trench. The second conducting layer is disposed above the first conducting layer and filling the trench. The second dielectric layer is disposed between the first conducting layer and the second conducting layer. The spacer is disposed between the first dielectric layer and the second conducting layer. The doped region is disposed in the substrate of a side of the trench.10-30-2008
20100052033LANTHANIDE YTTRIUM ALUMINUM OXIDE DIELECTRIC FILMS - Electronic apparatus and methods of forming the electronic apparatus include a lanthanide yttrium aluminum oxide dielectric film on a substrate for use in a variety of electronic systems. The lanthanide yttrium aluminum oxide film may be structured as one or more monolayers. The lanthanide yttrium aluminum oxide film may be formed by atomic layer deposition.03-04-2010
20100052032Nonvolatile semiconductor memory and method for fabricating the same - A nonvolatile semiconductor memory includes a first semiconductor layer; second semiconductor regions formed on the first semiconductor layer having device isolating regions extended in a column direction; a first interlayer insulator film formed above the first semiconductor layer; a lower conductive plug connected to the second semiconductor regions; a first interconnect extended in a row direction; a second interlayer insulator formed on the lower conductive plug and the first interlayer insulator film; an upper conductive plug; and a second interconnect formed on the second interlayer insulator contacting with the top of the upper conductive plug extended in the column direction.03-04-2010
20080315280SEMICONDUCTOR MEMORY DEVICE HAVING MEMORY CELL UNIT AND MANUFACTURING METHOD THEREOF - A semiconductor memory device includes a silicon substrate including a first region which has a buried insulating layer below a single-crystal silicon layer and a second region which does not have the buried insulating layer below the single-crystal silicon layer, at least one memory cell transistor which has a first gate electrode, the first gate electrode being provided on the single-crystal silicon layer in the first region, and at least one selective gate transistor which has a second gate electrode and is provided on the single-crystal silicon layer in the first region. The one selective gate transistor is provided in such a manner that a part of the second gate electrode is placed on the single-crystal silicon layer in the second region.12-25-2008
20090026522SEMICONDUCTOR DEVICE COMPRISING TRANSISTOR STRUCTURES AND METHODS FOR FORMING SAME - A method for forming an opening within a semiconductor material comprises forming a neck portion, a rounded portion below the neck portion and, in some embodiments, a protruding portion below the rounded portion. This opening may be filled with a conductor, a dielectric, or both. Embodiments to form a transistor gate, shallow trench isolation, and an isolation material separating a transistor source and drain are disclosed. Device structures formed by the method are also described.01-29-2009
20090140314FLASH MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - Embodiments relate to a flash memory device and a method of manufacturing the same that may include a tunnel oxide layer on and/or over a semiconductor substrate having source and drain regions. The tunnel oxide layer may have a first width The flash memory device may include a first polysilicon pattern and a second polysilicon pattern on and/or over the tunnel oxide layer and a dielectric pattern on and/or over the tunnel oxide layer, where the first and second polysilicon patterns may be provided. It may also include a third polysilicon pattern on and/or over the dielectric pattern, the third polysilicon pattern having a second width, and a spacer formed on and/or over sidewalls of the first, second and third polysilicon patterns, the dielectric pattern and the tunnel oxide pattern. According to embodiments, the second width may be greater than the first width.06-04-2009
20120068244SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to an embodiment, a semiconductor memory device includes a plurality of multi-level memory cells provided on a major surface of a semiconductor substrate of a first conductivity type. A first semiconductor region of a second conductivity type is selectively provided in the surface of the semiconductor substrate between the multi-level memory cells. A second semiconductor region is provided deeper than the first semiconductor region and includes a first conductivity type impurity. A plurality of binary memory cells are provided on the major surface of the semiconductor substrate, and a third semiconductor region of the second conductivity type is selectively provided in the surface of the semiconductor substrate between the binary memory cells. Amount of the first conductivity type impurity compensating a second conductivity type impurity of the first semiconductor region is larger than that of the third semiconductor region.03-22-2012
20120068243SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - An improvement is achieved in the performance of semiconductor device including a nonvolatile memory. In a split-gate nonvolatile memory, between a memory gate electrode and a p-type well and between a control gate electrode and the memory gate electrode, an insulating film is formed. Of the insulating film, the portion between the lower surface of the memory gate electrode and the upper surface of a semiconductor substrate has silicon oxide films, and a silicon nitride film interposed between the silicon oxide films. Of the insulating film, the portion between a side surface of the control gate electrode and a side surface of the memory gate electrode is formed of a silicon oxide film, and does not have the silicon nitride film.03-22-2012
20090057745Inverted nonvolatile memory device, stack module, and method of fabricating the same - Example embodiments provide a nonvolatile memory device that may be integrated through stacking, a stack module, and a method of fabricating the nonvolatile memory device. In the nonvolatile memory device according to example embodiments, at least one bottom gate electrode may be formed on a substrate. At least one charge storage layer may be formed on the at least one bottom gate electrode, and at least one semiconductor channel layer may be formed on the at least one charge storage layer.03-05-2009
20110140188NON-VOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A non-volatile memory device including a substrate, a dielectric layer, a floating gate, source and drain regions, a channel region, and a doped layer is provided. The substrate includes a first region and a second region, and the substrate has an uneven surface in the second region. The dielectric layer is located on the substrate in the first region and in the second region to cover the uneven surface. The floating gate is located on the dielectric layer in the first region and is continuously extended to the second region. The source and drain regions are located in the substrate at opposite sides of the floating gate in the first region. The channel region is located in the substrate between the source and drain regions. The doped layer is located on the uneven surface or in the substrate in the second region to serve as a control gate.06-16-2011
20080290391MEMORY CELL AND METHOD FOR MANUFACTURING THE SAME - The invention provides a memory cell. The memory cell is disposed on a substrate and comprises a plurality of isolation structures defining at least a fin structure in the substrate. Further, the surface of the fin structure is higher than the surface of the isolation structure. The memory cell comprises a doped region, a gate, a charge trapping structure and a source/drain region. The doped region is located in a top of the fin structure and near a surface of the top of the fin structure and the doped region has a first conductive type. The gate is disposed on the substrate and straddled the fin structure. The charge trapping structure is disposed between the gate and the fin structure. The source/drain region with a second conductive type is disposed in the fin structures exposed by the gate and the first conductive type is different from the second conductive type.11-27-2008
20090230451Semiconductor device capable of suppressing short channel effect and method of fabricating the same - A semiconductor device includes a semiconductor substrate including at least one memory channel region and at least one memory source/drain region, the memory channel region and the memory source/drain region being arranged alternately, and at least one word line on the memory channel region, wherein the memory source/drain region has a higher net impurity concentration than the memory channel region.09-17-2009
20090194803SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - The present invention provides a semiconductor device capable of being mass-produced and a manufacturing method of the semiconductor device. The present invention also provides a semiconductor device using an extreme thin integrated circuit and a manufacturing method of the semiconductor device. Further, the present invention provides a low power consumption semiconductor device and a manufacturing method of the semiconductor device. According to one aspect of the present invention, a semiconductor device that has a semiconductor nonvolatile memory element transistor over an insulating surface in which a floating gate electrode of the memory transistor is formed by a plurality of conductive particles or semiconductor particles is provided.08-06-2009
20090212339Flash Memory Device and Method of Fabricating the Same - The present invention relates to flash memory devices and a method of fabricating the same. In an aspect of the present invention, the flash memory device includes trenches formed in a semiconductor substrate and having a step at their lower portion, a tunnel insulating layer formed in an active region of the semiconductor substrate, first conductive layers formed on the tunnel insulating layer, an isolation layer gap-filling between the trenches and the first conductive layers, and a second conductive layer formed on the first conductive layer and having one side partially overlapping with the isolation layers.08-27-2009
20090242955Integrated Circuit, Memory Device and Methods of Manufacturing the Same - An integrated circuit includes: a contact structure with a first stack of at least two conductive layers, and a gate electrode with a second stack of conductive layers, the second stack of layers having the same sequence of conductive layers as the first stack.10-01-2009
20090256188METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND THE SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device which includes: alternately supplying a silicon source and an oxidant to deposit a silicon oxide film on a surface of a semiconductor substrate, wherein the silicon source is supplied under a supply condition where an adsorption amount of molecules of the silicon source on the semiconductor substrate is increased without causing an adsorption saturation of the molecules of the silicon source on the semiconductor substrate, and wherein the oxidant is supplied under a supply condition where impurities remain in the molecules of the silicon source adsorbed on the semiconductor substrate.10-15-2009
20100171164Nonvolatile semiconductor memory device and method of manufacturing the same - A nonvolatile semiconductor memory device including a semiconductor substrate having a semiconductor layer and an insulating material provided on a surface thereof, a surface of the insulating material is covered with the semiconductor layer, and a plurality of memory cells provided on the semiconductor layer, the memory cells includes a first dielectric film provided by covering the surface of the semiconductor layer, a plurality of charge storage layers provided above the insulating material and on the first dielectric film, a plurality of second dielectric films provided on the each charge storage layer, a plurality of conductive layers provided on the each second dielectric film, and an impurity diffusion layer formed partially or overall at least above the insulating material and inside the semiconductor layer and at least a portion of a bottom end thereof being provided by an upper surface of the insulating material.07-08-2010
20100155806SEMICONDUCTOR DEVICE - A semiconductor device includes an active zone doped according to a first type; a drain zone formed in the active zone and doped according to a second type; a source zone formed in the active zone and doped according to the second type; an insulated gate zone separated from the active zone by an insulating layer; a deep well, doped according to the second type such that the active zone is located between the gate zone and the well; a floating gate zone formed in the active zone under a space existing between the drain zone and the source zone, the floating gate zone including defects introducing deep levels in the bandgap of the semiconductor material, the deep levels being suited to trap carriers corresponding to the first type such that a charge state of the floating gate zone is modified and a drain source current varies due to the presence of a supplementary potential on the floating gate zone, a concentration of defects in the floating gate zone being strictly greater than 1006-24-2010
20100155804Shallow Trench Isolation For A Memory - In some embodiments, a gate structure with a spacer on its side may be used as a mask to form self-aligned trenches in a microelectronic memory, such as a flash memory. A first portion of the gate structure may be used to form the mask, together with sidewall spacers, in some embodiments. Then, after forming the shallow trench isolations, a second portion of the gate structure may be added to form a mushroom shaped gate structure.06-24-2010
20100155805NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND FABRICATING THE SAME - There is provided a nonvolatile semiconductor memory device, including, a tunnel insulator, a floating gate electrode including a first floating gate electrode and a second floating gate electrode being constituted with a nondegenerate state semiconductor, an intergate insulating film formed to cover at least continuously an upper and a portion of a side surface of the floating gate electrode, and a control gate electrode in order, and an isolation insulating film, a lower portion of the isolation insulating film being embedded in the semiconductor substrate in both sides of the floating gate electrode along a channel width direction, an upper portion of the isolation insulating film contacting with a side surface of the first floating gate electrode and protruding to a level between an upper surface of the semiconductor substrate and an upper surface of the first floating gate electrode.06-24-2010
20090045449FINNED MEMORY CELLS - For an embodiment, a memory array has a plurality fins protruding from a substrate. A tunnel dielectric layer overlies the fins. A plurality floating gates overlie the tunnel dielectric layer, and the floating gates correspond one-to-one with the fins protruding from the substrate. An intergate dielectric layer overlies the floating gates. A control gate layer overlies the intergate dielectric layer. Each fin includes an upper surface rounded by isotropic etching.02-19-2009
20100276743SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - A laminated body is formed by alternately laminating a plurality of dielectric films and electrode films on a silicon substrate. Next, a through hole extending in the lamination direction is formed in the laminated body. Next, a selective nitridation process is performed to selectively form a charge layer made of silicon nitride in a region of an inner surface of the through hole corresponding to the electrode film. Next, a high-pressure oxidation process is performed to form a block layer made of silicon oxide between the charge layer and the electrode film. Next, a tunnel layer made of silicon oxide is formed on an inner side surface of the through hole. Thus, a flash memory can be manufactured in which the charge layer is split for each electrode film.11-04-2010
20110108902MEMORY WITH A READ-ONLY EEPROM-TYPE STRUCTURE - A non-volatile memory including at least first and second memory cells each including a storage MOS transistor with dual gates and an insulation layer provided between the two gates. The insulation layer of the storage transistor of the second memory cell includes at least one portion that is less insulating than the insulation layer of the storage transistor of the first memory cell.05-12-2011
20100252874Memory Device - One or more embodiments relate to a floating gate memory device, comprising: a substrate; a floating gate disposed over the substrate; and a control gate substantially laterally surrounding at least a portion of the floating gate.10-07-2010
20080230824Double Gate Non-Volatile Memory Device and Method of Manufacturing - The present invention relates to a non-volatile memory device on a substrate layer comprising semiconductor source and drain regions, a semiconductor channel region, a charge storage stack and a control gate; the channel region being fin-shaped having two sidewall portions and a top portion, and extending between the source region and the drain region; the charge storage stack being positioned between the source and drain regions and extending over the fin-shaped channel, substantially perpendicularly to the length direction of the fin-shaped channel; the control gate being in contact with the charge storage stack, wherein—an access gate is provided adjacent to one sidewall portion and separated therefrom by an intermediate gate oxide layer, and—the charge storage stack contacts the fin-shaped channel on the other sidewall portion and is separated from the channel by the intermediate gate oxide layer.09-25-2008
20090114972Integrated Circuit Embedded With Non-Volatile One-Time-Programmable And Multiple-Time Programmable Memory - A programmable non-volatile device uses a floating gate that functions as a FET gate that overlaps a portion of a source/drain region. This allows a programming voltage for the device to be imparted to the floating gate through capacitive coupling, thus changing the state of the device. The invention can be used in environments such as data encryption, reference trimming, manufacturing ID, security ID, and many other applications.05-07-2009
20090152614NAND flash memory device having a contact for controlling a well potential - A NAND flash memory device includes a plurality of active regions extending in a first direction on a substrate, the active regions including a first well of a first conductivity, a plurality of word lines extending on the first well in a second direction perpendicular to the first direction, first and second dummy word lines extending in a second direction on the first well, the first and second dummy word lines being separated from each other to define an intermediate region therebetween, the first and second dummy word lines being adapted to receive a substantially constant bias voltage of about 0 V, and at least one contact in an active region in the intermediate region between the first and second dummy word lines.06-18-2009
20090108323Method of forming nonvolatile memory device having floating gate and related device - A method of manufacturing a non-volatile memory device is provided. The method includes forming isolation patterns defining an active region on a substrate, forming a floating gate pattern on the active region, and forming a gate line on the floating gate pattern. The floating gate pattern is self-aligned on the active region and has an impurity ion concentration that becomes relatively low as the floating gate pattern gets nearer to the active region.04-30-2009
20080265303METHODS OF FORMING SHALLOW TRENCH ISOLATION STRUCTURES WITH BURIED BIT LINES IN NON-VOLATILE MEMORIES AND DEVICES, CARDS, AND SYSTEMS SO FORMED - Methods of forming buried bit lines in a non-volatile memory device can include forming impurity regions in a substrate of a non-volatile memory device to provide immediately neighboring buried bit lines for the device and then forming a shallow trench isolation region in the substrate between the immediately neighboring buried bit lines to substantially equalize lengths of the immediately neighboring buried bit lines.10-30-2008
20090065842Ta-lined tungsten plugs for transistor-local hydrogen gathering - The present electronic device includes a dielectric body having an opening therein. A tantalum layer is provided in the opening of the dielectric body, the layer having the characteristic of absorbing hydrogen with decrease in temperature, and releasing hydrogen with increase in temperature. A conductive tungsten plug is provided on the layer in the opening.03-12-2009
20110127598FLASH MEMORY DEVICE HAVING A GRADED COMPOSITION, HIGH DIELECTRIC CONSTANT GATE INSULATOR - A graded composition, high dielectric constant gate insulator is formed between a substrate and floating gate in a flash memory cell transistor. The gate insulator comprises amorphous germanium or a graded composition of germanium carbide and silicon carbide. If the composition of the gate insulator is closer to silicon carbide near the substrate, the electron barrier for hot electron injection will be lower. If the gate insulator is closer to the silicon carbide near the floating gate, the tunnel barrier can be lower at the floating gate.06-02-2011
20110001178NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - A nonvolatile semiconductor memory device includes: a substrate; a stacked body with a plurality of dielectric films and electrode films alternately stacked therein, the stacked body being provided on the substrate and having a step in its end portion for each of the electrode films; an interlayer dielectric film burying the end portion of the stacked body; a plurality of semiconductor pillars extending in the stacking direction of the stacked body and penetrating through a center portion of the stacked body; a charge storage layer provided between one of the electrode films and one of the semiconductor pillars; and a plug buried in the interlayer dielectric film and connected to a portion of each of the electrode films constituting the step, a portion of each of the dielectric films in the center portion having a larger thickness than a portion of each of the dielectric films in the end portion.01-06-2011
20090184358METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE AND THE SEMICONDUCTOR DEVICE MADE THEREOF - A method for fabricating a semiconductor device and the device made thereof are disclosed. In one aspect, the method includes providing a substrate comprising a semiconductor material. The method further includes patterning at least one fin in the substrate, the fin comprising a top surface, at least one sidewall surface, and at least one corner. A supersaturation of point defects is created in the at least one fin. The at least one fin is annealed and then cooled down such that semiconductor atoms of the semiconductor material migrate via the point defects.07-23-2009
20110024820METHOD OF MANUFACTURING A NONVOLATILE SEMICONDUCTOR MEMORY DEVICE, AND A NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - For enhancing the high performance of a non-volatile semiconductor memory device having an MONOS type transistor, a non-volatile semiconductor memory device is provided with MONOS type transistors having improved performance in which the memory cell of an MONOS non-volatile memory comprises a control transistor and a memory transistor. A control gate of the control transistor comprises an n-type polycrystal silicon film and is formed over a gate insulative film comprising a silicon oxide film. A memory gate of the memory transistor comprises an n-type polycrystal silicon film and is disposed on one of the side walls of the control gate. The memory gate comprises a doped polycrystal silicon film with a sheet resistance lower than that of the control gate comprising a polycrystal silicon film formed by ion implantation of impurities to the undoped silicon film.02-03-2011
20120132976SEMICONDUCTOR DEVICES HAVING DUAL TRENCH, METHODS OF FABRICATING THE SAME, AND ELECTRONIC SYSTEM HAVING THE SAME - A semiconductor device having a dual trench and methods of fabricating the same, a semiconductor module, an electronic circuit board, and an electronic system are provided. The semiconductor device includes a semiconductor substrate having a cell region including a cell trench and a peripheral region including a peripheral trench. The cell trench is filled with a core insulating material layer, and the peripheral trench is filled with a padding insulating material layer conformably formed on an inner surface thereof and a core insulating material layer formed on an inner surface of the padding insulating material layer. The core insulating material layer has a greater fluidity than the padding insulating material layer.05-31-2012
20110018047NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A nonvolatile semiconductor memory device comprises: element isolation insulating films formed in a semiconductor substrate in a first direction; and element regions formed in a region sandwiched by the element isolation insulating film, with MONOS type memory cells. The MONOS type memory cell comprises: a tunnel insulating film disposed on the element region; a charge storage film disposed continuously on the element regions and the element isolation insulating films. The charge storage film comprises: a charge film disposed on the element region and having a certain charge trapping characteristic; and a degraded charge film disposed on the element isolation insulating film and having a charge trapping characteristic inferior to that of the charge film. The degraded charge film has a length of an upper surface thereof set shorter than a length of a lower surface thereof in a cross-section along the first direction.01-27-2011
20110024819HIGH QUALITY GATE DIELECTRIC FOR SEMICONDUCTOR DEVICES AND METHOD OF FORMATION THEREOF - Improved high quality gate dielectrics and methods of preparing such dielectrics are provided. Preferred dielectrics comprise a rare earth doped dielectric such as silicon dioxide or silicon oxynitride. In particular, cerium doped silicon dioxide shows an unexpectedly high charge-to-breakdown Q02-03-2011
20090146202ORGANIC MEMORY DEVICE AND METHOD OF MANUFACTURE - An organic memory device is disclosed that has an active layer, at least one charge storage layer of a film of an organic dielectric material, and nanostractures and/or nano-particles of a charge-storing material on or in the film of dielectric material. Each of the nanostructures and/or nano-particles is separated from the others of the nanostractures and/or nano-particles by the organic dielectric material of the organic dielectric film. A method of manufacturing the organic memory device is also disclosed.06-11-2009
20100163953SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Disclosed are a semiconductor device and a method of manufacturing the same. The semiconductor device includes a first polysilicon pattern formed on a semiconductor substrate, a second polysilicon pattern formed at a lateral side of the first polysilicon pattern such that the second polysilicon pattern extends to a height higher than the first polysilicon pattern, a third polysilicon pattern formed in a region restricted by a top surface of the first polysilicon pattern and a lateral side of the second polysilicon pattern, and a contact electrically connected with the second polysilicon pattern and the third polysilicon pattern.07-01-2010
20100163952Flash Cell with Integrated High-K Dielectric and Metal-Based Control Gate - A semiconductor device is described having an integrated high-k dielectric layer and metal control gate. A method of fabricating the same is described. Embodiments of the semiconductor device include a high-k dielectric layer disposed on a floating gate. The high-k dielectric layer defines a recess. A metal control gate is formed in the recess.07-01-2010
20100163954FLASH MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - Disclosed are a dual bit type NROM flash memory device and a method for manufacturing the same using a self-aligned scheme. The flash memory device includes a plurality of bit lines buried in a substrate in one direction while being spaced apart from each other at a regular interval; floating gates aligned at both sides of each of the bit lines on the substrate; and a plurality of word lines spaced apart from each other at a regular interval while crossing the bit lines. In the flash memory device of an embodiment, polysilicon is used for a trapping layer, so the programming and erasing operations can be performed at a higher speed, a threshold voltage (Vt) window is widened, and retention characteristics are improved.07-01-2010
20120068242SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - A semiconductor device includes horizontal patterns on a substrate and the horizontal patterns have at least one opening therein, a pad pattern in an upper region of the opening, an insulating gap fill structure in the opening, the insulating gap fill structure is between the pad pattern and the substrate, and the insulating gap fill structure includes a first gap fill pattern and a second gap fill pattern. The first gap fill pattern includes a first oxide and the second gap fill pattern includes a second oxide, and the second oxide has a different etching selectivity from that of the first oxide. The device further includes a semiconductor pattern that is between a sidewall of the gap fill structure and sidewalls of the horizontal patterns and between a sidewall of the pad pattern and the sidewalls of the horizontal patterns.03-22-2012
201000129973-DIMENSIONAL FLASH MEMORY DEVICE, METHOD OF FABRICATION AND METHOD OF OPERATION - Disclosed are a flash memory device and method of operation. The flash memory device includes a bottom memory cell array and a top memory cell array disposed over the bottom memory cell array. The bottom memory cell array includes a bottom semiconductor layer, a bottom well, and a plurality of bottom memory cell units. The top memory cell array includes a top semiconductor layer, a top well, and a plurality of top memory cell units. A well bias line is disposed over the top memory cell array and includes a bottom well bias line and a top well bias line, The bottom well bias line is electrically connected to the bottom well, and the top well bias line is electrically connected to the top well.01-21-2010
20090218611HIGH DENSITY STEPPED, NON-PLANAR FLASH MEMORY - A first plurality of memory cells is in a first plane in a first column of the array. A second plurality of memory cells is in a second plane in the same column. The second plurality of memory cells are coupled to the first plurality of memory cells through a series connection of their source/drain regions.09-03-2009
20110101437METHOD OF FORMING NONVOLATILE MEMORY DEVICE HAVING FLOATING GATE AND RELATED DEVICE - A method of manufacturing a non-volatile memory device is provided. The method includes forming isolation patterns defining an active region on a substrate, forming a floating gate pattern on the active region, and forming a gate line on the floating gate pattern. The floating gate pattern is self-aligned on the active region and has an impurity ion concentration that becomes relatively low as the floating gate pattern gets nearer to the active region.05-05-2011
20110101436SUBSTRATE FOR SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE, AND ELECTRONIC APPARATUS - A substrate for a semiconductor device includes: a base substrate; a semiconductor layer that has a source region, a drain region, a plurality of channel regions, and at least one intermediate region; a source electrode being in contact with the source region; a drain electrode being in contact with the drain region; a gate electrode that overlaps the plurality of channel regions, the intermediate region, and each of a part of the source electrode and a part of the drain electrode; and a floating electrode being in contact with the intermediate region. The size of an area where the floating electrode and the gate electrode overlap each other is smaller than the sum of the size of an area where the source electrode and the gate electrode overlap each other and the size of an area where the drain electrode and the gate electrode overlap each other.05-05-2011
20110248327Three-Dimensional Semiconductor Memory Devices and Methods of Forming the Same - Nonvolatile memory devices include a string of nonvolatile memory cells on a substrate. This string of nonvolatile memory cells includes a first vertical stack of nonvolatile memory cells on the substrate and a string selection transistor on the first vertical stack of nonvolatile memory cells. A second vertical stack of nonvolatile memory cells is also provided on the substrate and a ground selection transistor is provided on the second vertical stack of nonvolatile memory cells. This second vertical stack of nonvolatile memory cells is provided adjacent the first vertical stack of nonvolatile memory cells. A conjunction doped semiconductor region is provided in the substrate. This conjunction doped region electrically connects the first vertical stack of nonvolatile memory cells in series with the second vertical stack of nonvolatile memory cells so that these stacks can operate as a single NAND-type string of memory cells.10-13-2011
20090001440Semiconductor device with buried source rail - In one embodiment of the invention, a NOR Flash memory includes a buried source rail that directly connects to a source strap. Furthermore, a drain plug connects directly to a bit line.01-01-2009
20110254070TRENCH MOSFET WITH TRENCHED FLOATING GATES IN TERMINATION - A trench MOSFET comprising a plurality of transistor cells, multiple trenched floating gates in termination area is disclosed. The trenched floating gates have trench depth equal to or deeper than body junction depth of body regions in active area. In some preferred embodiments, the trench MOSFET further comprises a gate metal runner surrounding outside the source metal and extending to the gate metal pad. Furthermore, the termination area further comprises an EPR surrounding outside the trenched floating gates.10-20-2011
20090294824NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A first select transistor is connected to one end of a plurality of memory cell transistors that are serially connected. A second select transistor is connected to the other end of the serially connected memory cell transistors. A first impurity diffusion region is formed in a semiconductor substrate and constitutes a first main electrode of the first select transistor. A second impurity diffusion region is formed in the semiconductor substrate and constitutes a second main electrode of the second select transistor. A depth of the first impurity diffusion region is greater than a depth of the second impurity diffusion region.12-03-2009
20090230452SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device which has a semiconductor substrate, an isolation insulating film formed in the semiconductor substrate, a conductive pattern formed over the semiconductor substrate and the isolation insulating film, so that a side face of the conductive pattern is formed over the isolation insulating film, and an insulating film is formed over the isolation insulating film, the conductive pattern and the side face of the conductive pattern, and the side face of the conductive pattern comprises a notch.09-17-2009
20080315282Semiconductor Devices Including Transistors Having Three Dimensional Channels - Semiconductor devices including a gate electrode crossing over a semiconductor fin on a semiconductor substrate are provided. A gate insulating layer is provided between the gate electrode and the semiconductor fin. A channel region having a three-dimensional structure defined at the semiconductor fin under the gate electrode is also provided. Doped region is provided in the semiconductor fin at either side of the gate electrode and an interlayer insulating layer is provided on a surface of the semiconductor substrate. A connector region is coupled to the doped region and provided in an opening, which penetrates the interlayer insulating layer. A recess region is provided in the doped region and is coupled to the connector region. The connector region contacts an inner surface of the recess region. Related methods of fabricating semiconductor devices are also provided herein.12-25-2008
20080315281Flash Memory Device and Method of Manufacturing the Same - Disclosed are a flash memory device and a method of manufacturing the same. In the method of manufacturing the flash memory device, gate patterns of a cell area and a logic area are formed by sequentially depositing and patterning a first polysilicon layer, an ONO layer and a second polysilicon layer without separately performing a photolithography process for one of the gate patterns. A mask process for removing a dummy gate pattern in the logic area is performed to form transistors in the cell area and the logic area, so that the manufacturing process is simplified.12-25-2008
20090001442NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A nonvolatile semiconductor memory device including a semiconductor substrate having a semiconductor layer and an insulating material provided on a surface thereof, a surface of the insulating material is covered with the semiconductor layer, and a plurality of memory cells provided on the semiconductor layer, the memory cells includes a first dielectric film provided by covering the surface of the semiconductor layer, a plurality of charge storage layers provided above the insulating material and on the first dielectric film, a plurality of second dielectric films provided on the each charge storage layer, a plurality of conductive layers provided on the each second dielectric film, and an impurity diffusion layer formed partially or overall at least above the insulating material and inside the semiconductor layer and at least a portion of a bottom end thereof being provided by an upper surface of the insulating material.01-01-2009
20080283896NONVOLATILE SEMICONDUCTOR MEMORY DEVICE WITH TWIN-WELL - A nonvolatile semiconductor memory device includes a first well of a first conductivity type, which is formed in a semiconductor substrate of the first conductivity type, a plurality of memory cell transistors that are formed in the first well, a second well of a second conductivity type, which includes a first part that surrounds a side region of the first well and a second part that surrounds a lower region of the first well, and electrically isolates the first well from the semiconductor substrate, and a third well of the second conductivity type, which is formed in the semiconductor substrate. The third well has a less depth than the second part of the second well.11-20-2008
20080251831Semiconductor structure and process for reducing the second bit effect of a memory device - A non-volatile memory cell capable of storing two bits of information having a non-conducting charge trapping dielectric, such as silicon nitride, layered in association with at least one electrical dielectric layer, such as an oxide, with a P-type substrate and an N-type channel implanted in the well region of the substrate between two source/drain regions is disclosed. The N-type channel achieves an inversion layer without the application of bias voltage to the gate of the memory cell. A method that implants the N-type channel in the P-type substrate of the cell wherein the N-type channel lowers the un-programmed or programmed voltage threshold of the memory cell to a value lower than would exist without the N-type channel is disclosed. The N-type channel reduces the second bit effect such that the window of operation between the programmed and un-programmed voltage thresholds of the bits is widened.10-16-2008
20080203460MANUFACTURING METHOD FOR A NANOCRYSTAL BASED DEVICE COVERED WITH A LAYER OF NITRIDE DEPOSITED BY CVD - The invention relates to a manufacturing method for a structure comprising semi-conductor material nanocrystals on a dielectric material substrate by chemical vapour deposition (CVD), the nanocrystals being covered by a layer of semi-conductor material nitride. The method comprises a step for forming stable nuclei on the substrate by CVD from a first gaseous precursor of the nuclei; a step of nanocrystal growth from stable nuclei by CVD from a second gaseous precursor; and a step for forming a layer of semi-conductor material nitride on the nanocrystals. The method is characterised in that the passivation step is carried out by selective and stoichiometric CVD of semi-conductor material nitride only on the nanocrystals from a mixture of the second and a third gaseous precursor selected to cause selective and stoichiometric deposition of the nitride only on said nanocrystals, wherein steps for forming the nuclei, forming the nanocrystals and passivation are carried out inside a same, single chamber.08-28-2008
20130168754METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE WITH INCREASED RELIABILITY - A method of forming a semiconductor device is provided. The method includes providing a semiconductor substrate, and forming a first conductive layer over the substrate. In one example, an insulating layer may be formed over the semiconductor substrate, with the first conductive layer being formed over the insulating layer. The method also includes forming an interpoly dielectric layer over the first conductive layer. In this regard, forming the interpoly dielectric layer includes forming a silicon oxide layer, and subjecting the silicon oxide layer to oxide densification to form an oxide-densified silicon oxide layer. And the method includes forming a second conductive layer over the interpoly dielectric layer.07-04-2013
20130168755SINGLE POLY EEPROM AND METHOD FOR FABRICATING THE SAME - A single poly EEPROM (Electrically Erasable Programmable Read Only Memory), which may include at least one of the following: (1) A second conductive type well formed on and/or over a semiconductor substrate. (2) A first conductive type source and drain regions formed in the second conductive type well. The single poly EEPROM may include at least one of: (a) A tunnel oxide layer formed on and/or over the second conductive type well. (b) A floating gate formed on and/or over the tunnel oxide layer and doped with second conductive type impurity ions. (c) A first conductive type impurity region formed in the second conductive type well adjacent to the floating gate. The floating gate may be configured such that a concentration of a region of the floating gate adjacent to the drain region is higher than that of the other region of the floating gate adjacent to the impurity region.07-04-2013
20110254069FLOATING GATE TYPE NONVOLATILE MEMORY DEVICE AND RELATED METHODS OF MANUFACTURE AND OPERATION - A floating gate type nonvolatile memory device comprises a semiconductor layer, wordlines crossing over the semiconductor layer, and a memory element disposed between the wordlines and facing the semiconductor layer.10-20-2011
20110254071SHIELDED TRENCH MOSFET WITH MULTIPLE TRENCHED FLOATING GATES AS TERMINATION - A trench MOSFET comprising a plurality of transistor cells having shielded trenched gates and multiple trenched floating gates as termination region is disclosed. The trenched floating gates have trench depth equal to or deeper than body junction depth of body regions in termination area. In some preferred embodiments, the trenched floating gates in the termination area are implemented by using shielded electrode structure.10-20-2011
20110133264SYSTEM AND METHOD FOR EEPROM ARCHITECTURE - A method for manufacturing an Electrically Erasable Programmable Read-Only Memory (EEPROM) device includes providing a substrate and forming a gate oxide over the substrate. Also, the method includes providing a mask overlying the gate oxide layer, the mask defining a tunnel opening. The method additionally includes performing selective etching over the mask to form a tunnel oxide layer. The method includes forming a floating gate over the tunnel oxide layer and a selective gate over the gate oxide layer. The method includes angle doping a region of the substrate using the floating gate as a mask to obtain a first doped region. The method further includes forming a dielectric layer over the floating gate and a control gate over the dielectric layer. The method additionally includes angle doping a second region of the substrate using the selective gate as a mask to obtain a second doped region, wherein the first and second doped regions partially overlap.06-09-2011
20090212340FLASH MEMORY DEVICES - A gate electrode line which extends in a second direction crossing a first direction on a substrate including an active region which is defined by a device isolation layer and extends in the first direction and a charge trap layer disposed between the active region and the gate electrode line, wherein a bottom surface of the gate electrode line disposed on the device isolation layer is lower than a top surface of the charge trap layer disposed on the active region and higher than a top surface of the active region.08-27-2009
20100148237NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - A non-volatile semiconductor storage device includes a plurality of memory strings each having a plurality of electrically rewritable memory cells connected in series. Each of the memory strings comprising: a first semiconductor layer including a columnar portion extending in a vertical direction with respect to a substrate; a plurality of first conductive layers formed to surround side surfaces of the columnar portions via insulation layers, and formed at a certain pitch in the vertical direction, the first conductive layers functioning as floating gates of the memory cells; and a plurality of second conductive layers formed to surround the first conductive layers via insulation layers, and functioning as control electrodes of the memory cells. Each of the first conductive layers has a length in the vertical direction that is shorter than a length in the vertical direction of each of the second conductive layers.06-17-2010
20120146121SEMICONDUCTOR DEVICE INCLUDING LINE-TYPE ACTIVE REGION AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device having a line-type active region and a method for manufacturing the same are disclosed. The semiconductor device includes an active region configured in a successive line type, at least one active gate having a first width and crossing the active region, and an isolation gate having a second width different from the first width and being formed between the active gates. The isolation gate's width and the active gate's width are different from each other to guarantee a large storage node contact region, resulting in increased device operation characteristics (write characteristics).06-14-2012
201201461223-D NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A three-dimensional (3-D) non-volatile memory device includes a plurality of word line structures extended in parallel and including a plurality of interlayer dielectric layers and a plurality of word lines that are alternately stacked over a substrate, a plurality of channels protruding from the substrate configured to penetrate the plurality of interlayer dielectric layers and the plurality of word lines, and an air gap formed between the plurality of word line structures.06-14-2012
20110215392Semiconductor Devices and Methods of Manufacturing the Same - Provided are a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes a charge storage pattern formed on a substrate; a dielectric pattern formed on the charge storage pattern; a first conductive pattern including silicon doped with a first impurity of a first concentration, the first conductive pattern being disposed on the dielectric pattern; and a second conductive pattern including metal silicide doped with a second impurity of a second concentration, the second conductive pattern being disposed on the first conductive pattern. The first concentration may be higher than the second concentration.09-08-2011
20100019305SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The semiconductor device of the present invention includes a semiconductor substrate, a plurality of floating gate electrodes formed in a memory cell forming region of the semiconductor substrate, a word line electrically connecting the floating gate electrodes and a conductor portion formed on the word line so as to reduce a resistance of the word line.01-28-2010
20090173986Semiconductor Devices Including Gate Structures and Leakage Barrier Oxides - Methods of forming a semiconductor device may include forming a tunnel oxide layer on a semiconductor substrate, forming a gate structure on the tunnel oxide layer, forming a leakage barrier oxide, and forming an insulating spacer. More particularly, the tunnel oxide layer may be between the gate structure and the substrate, and the gate structure may include a first gate electrode on the tunnel oxide layer, an inter-gate dielectric on the first gate electrode, and a second gate electrode on the inter-gate dielectric with the inter-gate dielectric between the first and second gate electrodes. The leakage barrier oxide may be formed on sidewalls of the second gate electrode. The insulating spacer may be formed on the leakage barrier oxide with the leakage barrier oxide between the insulating spacer and the sidewalls of the second gate electrode. In addition, the insulating spacer and the leakage barrier oxide may include different materials. Related structures are also discussed.07-09-2009
20090173985Dense arrays and charge storage devices - There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.07-09-2009
20090173984INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING AN INTEGRATED CIRCUIT - The present invention provides an integrated circuit with a floating body transistor comprising two source/drain regions and a floating body region arranged between the two source/drain regions comprising: a back gate electrode separated from the floating body by a first dielectric layer; a control gate electrode, separated from the floating body by a second dielectric layer and overlying the back gate electrode; and a third dielectric layer arranged between the back gate electrode and the control gate electrode. The present invention provides also a method of manufacturing an integrated circuit and a method of operating an integrated circuit.07-09-2009
20090114971CMOS EPROM AND EEPROM DEVICES AND PROGRAMMABLE CMOS INVERTERS - A CMOS EPROM, EEPROM or inverter device includes an nFET device with a thin gate dielectric layer and a pFET device juxtaposed with the nFET device with a thick gate dielectric layer and a floating gate electrode. The thick gate dielectric layer is substantially thicker than the thin gate dielectric layer. A common drain node connected both FET devices has no external connection in the case of a memory device and has an external connection in the case of an inverter. There are external circuit connections to the source regions of both FET devices and to the gate electrode of the nFET device. The pFET and nFET devices can be planar, vertical or FinFET devices.05-07-2009
20110316066SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor memory device includes a semiconductor substrate, a tunnel insulating film, a first electrode, an interelectrode insulating film and a second electrode. The tunnel insulating film is provided on the semiconductor substrate. The first electrode is provided on the tunnel insulating film. The interelectrode insulating film is provided on the first electrode. The second electrode is provided on the interelectrode insulating film. The interelectrode insulating film includes a stacked insulating layer, a charge storage layer and a block insulating layer. The charge storage layer is provided on the stacked insulating layer. The block insulating layer is provided on the charge storage layer. The stacked insulating layer includes a first insulating layer, a quantum effect layer and a second insulating layer. The quantum effect layer is provided on the first insulating layer. The second insulating layer is provided on the quantum effect layer.12-29-2011
20110156123METHOD FOR MANUFACTURING TWIN BIT STRUCTURE CELL WITH HAFNIUM OXIDE LAYER - A method for manufacturing a twin bit cell structure of with a hafnium oxide material includes providing a semiconductor substrate having a surface region and forming a gate dielectric layer overlying the surface region. The method forms a polysilicon gate structure overlying the gate dielectric layer and subjects the polysilicon gate structure to an oxidizing environment to cause formation of a first silicon oxide layer overlying the polysilicon gate structure. The method forms an undercut region underneath the polysilicon gate structure and subjects the polysilicon gate structure to an oxidization environment. Thereafter, the method forms a hafnium oxide material overlying the polysilicon gate structure including the undercut region and exposed portions of the gate dielectric layer. The hafnium oxide material is then selectively etched to form an insert region in a portion of the undercut region. A sidewall spacer is formed to isolate and protect the exposed hafnium oxide material.06-30-2011
20120007162METHOD OF FORMING SEMICONDUCTOR DEVICES - A semiconductor device includes an insulating layer and an undoped polysilicon layer that are stacked over a semiconductor substrate. The semiconductor substrate is exposed by removing the portions of the undoped polysilicon layer and the insulating layer. The trenches are formed by etching the exposed semiconductor substrate. Isolation layers are formed in the trenches, and a doped polysilicon layer is formed by implanting impurities into the undoped polysilicon layer.01-12-2012
20120205734Very Dense NVM Bitcell - An asymmetric non-volatile memory bitcell is described. The bitcell comprises source and drain regions comprising carriers of the same conductivity type. A floating gate rests on top of the well, and extends over a channel region, and at least a portion of the source and drain regions. The drain region comprises additional carriers of a second conductivity type, allowing band to band tunneling. The source region comprises additional carriers of a first conductivity type, thereby increasing source-gate capacitance. Thus, the bitcell incorporates a select device, thereby decreasing the overall size of the bitcell. The bitcell may be created without any additional CMOS process steps, or through the addition of a single extra mask step.08-16-2012
20120012915SEMICONDUCTOR MEMORY HAVING ELECTRICALLY FLOATING BODY TRANSISTOR - A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; a gate positioned between said first and second regions; and a back-bias region configured to inject charge into or extract charge out of said floating body region to maintain said state of the memory cell. Application of back bias to the back bias region offsets charge leakage out of the floating body and performs a holding operation on the cell. The cell may be a multi-level cell. Arrays of memory cells are disclosed for making a memory device.01-19-2012
20110049601SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a substrate, conductive members, an interlayer insulating film, and a plurality of contacts. The conductive members are provided in an upper portion of the substrate or above the substrate to extend in one direction. The interlayer insulating film is provided on the substrate and the conductive members. The plurality of contacts is provided in the interlayer insulating film. In a first region on the substrate, the contacts are located at some of lattice points of an imaginary first lattice. In a second region on the substrate, the contacts are located at some of lattice points of an imaginary second lattice. The second lattice is different from the first lattice. Each of the first lattice and the second lattice includes some of the lattice points located on the conductive members or on an extension region extended in the one direction of the conductive members. A position of each of the lattice points located on the conductive members and the extension region in the one direction is periodically displaced based on every n consecutively-arranged conductive members (n is a natural number).03-03-2011
20120153373GATE STRUCTURE - A gate structure is described, including a dielectric layer, a gate conductive layer and a stacked cap structure. The dielectric layer is disposed between a substrate and the gate conductive layer. The gate conductive layer is disposed between the dielectric layer and the stacked cap structure. The stacked cap structure disposed on the gate conductive layer includes at least two insulating layers having different materials and contacting each other.06-21-2012
20090014772EEPROM MEMORY CELL WITH FIRST-DOPANT-TYPE CONTROL GATE TRANSISTOR, AND SECOND-DOPANT TYPE PROGRAM/ERASE AND ACCESS TRANSISTORS FORMED IN COMMON WELL - A memory device including a plurality of memory cells, each with a control gate NMOS transistor sharing a floating gate with a program/erase PMOS transistor which is, in turn, connected in series with an access PMOS transistor. The memory cells are formed in a common N-Well formed in a P-substrate, the NMOS transistor being formed in a p-doped pocket or base. The program/erase PMOS includes a gate, and first and second P+ doped regions formed in the N-Well, wherein the first P+ region is electrically connected to a corresponding bit line. The access PMOS includes a gate, and first and second P+ regions formed within the N-Well, wherein the first P+ region is electrically connected to the second P+ region of the program/erase PMOS, and the gate is electrically connected to a corresponding word line. The control gate NMOS includes source, drain, and gate, wherein the source and third drain as well as the p-doped pocket are electrically connected to a corresponding control gate line, and the gate is electrically connected to the gate of the program/erase PMOS, forming floating gate of the cell.01-15-2009
20090134443FLOATING-GATE STRUCTURE WITH DIELECTRIC COMPONENT - Floating-gate memory cells having a floating gate with a conductive portion and a dielectric portion facilitate increased levels of charge trapping sites within the floating gate. The conductive portion includes a continuous component providing bulk conductivity to the floating gate. The dielectric portion is discontinuous within the conductive portion and may include islands of dielectric material and/or one or more contiguous layers of dielectric material having discontinuities.05-28-2009
20110089478Semiconductor device and method for manufacturing the same - It is made possible to provide a method for manufacturing a semiconductor device that has a high-quality insulating film in which defects are not easily formed, and experiences less leakage current. A method for manufacturing a semiconductor device, includes: forming an amorphous silicon layer on an insulating layer; introducing oxygen into the amorphous silicon layer; and forming a silicon oxynitride layer by nitriding the amorphous silicon layer having oxygen introduced thereinto.04-21-2011
20120119280Charge Trap Non-Volatile Memory - A charge trapping non-volatile memory may be made with a charge trapping medium including a pair of dielectric layers sandwiching a metal or semimetal layer. The metal or semimetal layer may exhibit a lower energy level than either of the adjacent sandwiching charge trapping layers, creating a good electron sink and, in some embodiments, resulting in a thinner charge trapping medium.05-17-2012
20120119281INTEGRATED CIRCUIT SYSTEM WITH BANDGAP MATERIAL AND METHOD OF MANUFACTURE THEREOF - A method of manufacturing an integrated circuit system includes: providing a substrate having a channel region; forming a gate stack over a portion of the channel region with the gate stack having a floating gate for storing an electrical charge; forming a source recess in the substrate adjacent to the gate stack; and forming a source by layering a first bandgap material in the source recess.05-17-2012
20110108901SEMICONDUCTOR STORAGE DEVICE - Device isolation/insulation films each have a first height within a first area and a second height higher than the first height within a second area. At least the device isolation/insulation films adjacent to a contact diffusion region exist in the second area, and the device isolation/insulation films adjacent to memory transistors exist in the first area. The device isolation/insulation films are implanted with an impurity of a first conductivity type, and device formation regions each have a diffusion region of the first conductivity type, the diffusion region being formed by diffusion of the impurity of the first conductivity type from the device isolation/insulation films.05-12-2011
20100289070METHODS FOR ISOLATING PORTIONS OF A LOOP OF PITCH-MULTIPLIED MATERIAL AND RELATED STRUCTURES - Different portions of a continuous loop of semiconductor material are electrically isolated from one another. In some embodiments, the end of the loop is electrically isolated from mid-portions of the loop. In some embodiments, loops of semiconductor material, having two legs connected together at their ends, are formed by a pitch multiplication process in which loops of spacers are formed on sidewalls of mandrels. The mandrels are removed and a block of masking material is overlaid on at least one end of the spacer loops. In some embodiments, the blocks of masking material overlay each end of the spacer loops. The pattern defined by the spacers and the blocks are transferred to a layer of semiconductor material. The blocks electrically connect together all the loops. A select gate is formed along each leg of the loops. The blocks serve as sources/drains. The select gates are biased in the off state to prevent current flow from the mid-portion of the loop's legs to the blocks, thereby electrically isolating the mid-portions from the ends of the loops and also electrically isolating different legs of a loop from each other.11-18-2010
20120126302NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD OF THE SAME - According to one embodiment, a nonvolatile semiconductor memory device includes memory transistors, an interlayer insulating film, a peripheral transistor and a sidewall. The memory transistors are formed on a semiconductor substrate. Each of the memory transistors includes a first stack gate which includes a floating gate electrode, a second gate insulating film, and a control gate electrode. The interlayer insulating film is formed between the first stack gates. The interlayer insulating film includes a first air gap. The peripheral transistor is formed on the substrate. The peripheral transistor includes a second stack gate which includes a first gate electrode, a third gate insulating film, and a second gate electrode. The sidewall is formed on a side surface of the second stack gate and includes a second air gap. An upper end of the second air gap is located at a position lower than the third gate insulating film.05-24-2012
20090065841SILICON OXY-NITRIDE (SiON) LINER, SUCH AS OPTIONALLY FOR NON-VOLATILE MEMORY CELLS - An improved contact etch stop liner (CESL) is provided, to reduce stress effects in NVM cells using a nitride charge-trapping layer (such as NROM). SiON (silicon oxy-nitride) may be used in lieu of SiN (silicon nitride), for the CESL. Or, the CESL may be processed to be discontinuous, to reduce stress effects, using either conventional SiN (silicon nitride) or SiON. Or, the CESL layer may be eliminated entirely, to reduce stress effects.03-12-2009
20090057746SEMICONDUCTOR DEVICE - A semiconductor device having a passive element whose characteristic is adjustable even after manufacture by applying back bias voltage is provided. Formed on a main surface of a SOI substrate comprising a supporting substrate, a BOX layer, and an SOI layer is a MOS varactor comprising a gate dielectric formed on a surface of the SOI layer, a gate electrode formed on the gate dielectric, and a n03-05-2009
20090057747NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A nonvolatile memory device including a floating gate formed on a tunnel oxide layer that is formed on a semiconductor substrate. The device also includes a drain region formed in the substrate adjacent to one side of the floating gate, a source region formed in the substrate adjacent to another side of the floating gate, where the source region is apart from the floating gate, and an inter-gate insulating layer formed on a portion of an active region between the source region and the floating gate and on a sidewall of the floating gate directing toward the source region, as well as on a sidewall of the floating gate directing toward the drain region. The device includes a word line formed over the floating gate and being across the substrate in one direction, and a field oxide layer interposing between the word line and the source region and between the word line and the drain region, and intersecting the word line.03-05-2009
20110303960LOW RESISTIVITY TUNGSTEN PVD WITH ENHANCED IONIZATION AND RF POWER COUPLING - Embodiments described herein provide a semiconductor device and methods and apparatuses of forming the same. The semiconductor device includes a substrate having a source and drain region and a gate electrode stack on the substrate between the source and drain regions. The gate electrode stack includes a conductive film layer on a gate dielectric layer, a refractory metal nitride film layer on the conductive film layer, a silicon-containing film layer on the refractory metal nitride film layer, and a tungsten film layer on the silicon-containing film layer. In one embodiment, the method includes positioning a substrate within a processing chamber, wherein the substrate includes a source and drain region, a gate dielectric layer between the source and drain regions, and a conductive film layer on the gate dielectric layer. The method also includes depositing a refractory metal nitride film layer on the conductive film layer, depositing a silicon-containing film layer on the refractory metal nitride film layer, and depositing a tungsten film layer on the silicon-containing film layer.12-15-2011
20110303959Ultraviolet Energy Shield for Non-Volatile Charge Storage Memory - An integrated circuit with non-volatile memory cells shielded from ultraviolet light by a shielding structure compatible with chemical-mechanical processing. The disclosed shielding structure includes a roof structure with sides; along each side are spaced-apart contact posts, each with a width on the order of the wavelength of ultraviolet light to be shielded, and spaced apart by a distance that is also on the order of the wavelength of ultraviolet light to be shielded. The contact posts may be provided in multiple rows, and extending to a diffused region or to a polysilicon ring or both. The multiple rows may be aligned with one another or staggered relative to one another.12-15-2011
20100270604Non-Volatile Memories and Methods of Fabrication Thereof - Non-volatile memories and methods of fabrication thereof are described. In one embodiment, a method of fabricating a semiconductor device includes forming an oxide layer over a semiconductor substrate, and exposing the oxide layer to a first nitridation step to form a first nitrogen rich region. The first nitrogen rich region is disposed adjacent an interface between the oxide layer and the semiconductor substrate. After the first nitridation step, the oxide layer is exposed to a second nitridation step to form a second nitrogen rich region. A first gate electrode is formed on the oxide layer, wherein the second nitrogen rich region is disposed adjacent an interface between the oxide layer and the first gate electrode.10-28-2010
20120217565PROCESS FOR OBTAINING AN ARRAY OF NANODOTS - A process for obtaining an array of nanodots (08-30-2012
20120187467FLOATING GATES AND METHODS OF FORMATION - The present invention generally relates to a floating gate structure and method of forming the same. The floating gate structure has an upper portion which is wider than a middle portion of the floating gate structure. The upper portion may have a flared, rounded or bulbous shape instead of being pointed or having sharp corners. The reduction in pointed or sharp features of the upper portion reduces the electric field intensity near the upper portion, which decreases current leakage through the interpoly dielectric. The method includes forming a nitride cap on the upper surface of the floating gate structure to assist in shaping the floating gate. The floating gate is then formed using multiple selective oxidation and etching processes.07-26-2012
20110121379Three-Terminal Single Poly NMOS Non-Volatile Memory Cell With Shorter Program/Erase Times - A three terminal non-volatile memory (NVM) cell for a CMOS IC is formed by either a standard CMOS process flow or a slightly modified CMOS process flow. The NVM cell includes read and injection transistors that share a common floating gate. The floating gate includes a portion disposed over the channel region of the read transistor, a portion disposed over the channel region of the injection transistor, and a portion extending into an enlarged drain diffusion area away from the channel regions, whereby the gate-to-drain capacitance is higher than the gate-to-source capacitances. The source/drain of the injection transistor are formed using different LDD implants to achieve faster program/erase. Alternatively, an optional CHE enhancing implant is added to the source/drain of the injection transistor to enhance CHE programming. Both HV LDD and LV LDD implants are introduced together enabling LDD implant merging under the floating gate extension.05-26-2011
20080296651SEMICONDUCTOR DEVICE - A disclosed semiconductor device comprises a non-volatile memory cell including a PMOS write transistor and an NMOS read transistor. The PMOS write transistor includes a write memory gate oxide film formed on a semiconductor substrate and a write floating gate of electrically-floating polysilicon formed on the write memory gate oxide film. The NMOS read transistor includes a read memory gate oxide film formed on the semiconductor substrate and a read floating gate of electrically-floating polysilicon formed on the read memory gate oxide film. The write floating gate and the read floating gate are electrically connected to each other. The PMOS write transistor is configured to perform writing in the non-volatile memory cell, and the NMOS read transistor is configured to perform reading from the non-volatile memory cell.12-04-2008
20120261738N-Well/P-Well Strap Structures - Embodiments of N-well or P-well strap structures are disclosed with lower space requirements achieved by forming the strap on both sides of one or more floating polysilicon gate fingers.10-18-2012
20120261736NON-VOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A non-volatile memory device includes a substrate, a gate stack, a selecting gate, an erasing gate, a source region, and a drain region. The gate stack on the substrate includes from bottom to top a tunneling dielectric layer, a floating gate, an inter-gate dielectric layer, a control gate, and a spacer that is located between sidewalls of the control gate and the inter-gate dielectric layer. A side of the floating gate adjacent to the erasing gate has a warp-around profile and a sharp corner protruding from a vertical surface of the spacer. The selecting and erasing gates are respectively located at first and second sides of the substrate of the gate stack. The source region is located in the substrate under the erasing gate. The drain region is located in the substrate at a side of the selecting gate.10-18-2012
20120261737TRENCH MOSFET WITH TRENCHED FLOATING GATES AND TRENCHED CHANNEL STOP GATES IN TERMINATION - A trench MOSFET comprising multiple trenched floating gates in termination area is disclosed. The trenched floating gates have trench depth equal to or deeper than body junction of body regions in active area The trench MOSFET further comprises at least one trenched channel stop gate around outside of the trenched floating gates and connected to at least one sawing trenched gate extended into scribe line for prevention of leakage path formation between drain and source regions.10-18-2012
20110037113SEMICONDUCTOR STRUTURE AND METHOD OF FORMING THE SAME - A semiconductor structure including a substrate, at least one power MOSFET, a floating diode or a body diode, and at least one Schottky diode is provided. The substrate has a first area, a second area and a third area. The second area is between the first area and the third area. The at least one power MOSFET is in the first area. The floating diode or the body diode is in the second area. The at least one Schottky diode is in the third area. Further, the contact plugs of the power MOSFET and the Schottky diode include tungsten and are electronically connected to each other.02-17-2011
20080290392Semiconductor device having n-channel type MOS transistor with gate electrode layer featuring small average polycrystalline silicon grain size - In a semiconductor device including a semiconductor substrate, and an n-channel type MOS transistor produced in the semiconductor substrate, the n-channel type MOS transistor includes a gate insulating layer formed on the semiconductor substrate and having a thickness of at most 1.6 nm, and a gate electrode layer on the gate insulating layer, and the gate electrode layer is composed of polycrystalline silicon which has an average grain size falling within a range between 10 nm and 150 nm in the vicinity of the gate insulating layer.11-27-2008
20120280301PHASE TRANSITION MEMORIES AND TRANSISTORS - In one embodiment there is set forth a method comprising providing a semiconductor structure having an electrode, wherein the providing includes providing a phase transition material region and wherein the method further includes imparting energy to the phase transition material region to induce a phase transition of the phase transition material region. By inducing a phase transition of the phase transition material region, a state of the semiconductor structure can be changed. There is further set forth an apparatus comprising a structure including an electrode and a phase transition material region, wherein the apparatus is operative for imparting energy to the phase transition material region to induce a phase transition of the phase transition material region without the phase transition of the phase transition material region being dependent on electron transport through the phase transition material region.11-08-2012
20120080738SHALLOW TRENCH ISOLATION FOR A MEMORY - In some embodiments, a gate structure with a spacer on its side may be used as a mask to form self-aligned trenches in a microelectronic memory, such as a flash memory. A first portion of the gate structure may be used to form the mask, together with sidewall spacers, in some embodiments. Then, after forming the shallow trench isolations, a second portion of the gate structure may be added to form a mushroom shaped gate structure.04-05-2012
20120080737SEMICONDUCTOR DEVICE PROVIDED WITH A NON-VOLATILE MEMORY UNIT AND A MEMS SWITCH - According to one embodiment, a semiconductor device is provided. The semiconductor is provided with a MEMS switch element having a control terminal and a pair of signal terminals, and a non-volatile memory unit having first and second non-volatile semiconductor elements. The first non-volatile semiconductor element has a first source, a first drain and a first control gate terminal. The first drain is electrically connected to the control terminal of the MEMS switch element. The second non-volatile semiconductor element has a second source, a second drain and a second control gate terminal. The second drain gate terminal is electrically connected to the control terminal of the MEMS switch element.04-05-2012
20120280302MEMORY CELL STRUCTURES AND METHODS - Memory cell structures and methods are described herein. One or more memory cells include a transistor having a charge storage node, a dielectric material positioned between the charge storage node and a channel region of the transistor, the channel region positioned between a source region and a drain region, and a first electrode of a diode coupled to the charge storage node.11-08-2012
20120280300SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes gates formed over a semiconductor substrate that are spaced apart from one another and each have a stack structure of a tunnel insulation layer, a floating gate, a dielectric layer, a first conductive layer, and a metal silicide layer, a first insulation layer formed along the sidewalls of the gates and a surface of the semiconductor substrate between the gates and configured to have a height lower than the top of the metal silicide layer; and a second insulation layer formed along surfaces of the first insulation layer and surfaces of the metal silicide layer and configured to cover an upper portion of a space between the gates, wherein an air gap is formed between the gates.11-08-2012
20120086067SEMICONDUCTOR DEVICE AND STRUCTURE - A device, comprising: a first layer and a second layer wherein both said first layer and said second layer are mono-crystalline, wherein said first layer comprises first transistors, wherein said second layer comprises second transistors, wherein at least one of said second transistors substantially overlays one of said first transistors, and wherein both said first transistors and said second transistors are processed following the same lithography step.04-12-2012
20120326221MULTI-TIERED SEMICONDUCTOR DEVICES AND ASSOCIATED METHODS - Methods of fabricating multi-tiered semiconductor devices are described, along with apparatus and systems that include them. In one such method, a first dielectric is formed, and a second dielectric is formed in contact with the first dielectric. A channel is formed through the first dielectric and the second dielectric with a first etch chemistry, a void is formed in the first dielectric with a second etch chemistry, and a device is formed at least partially in the void in the first dielectric. Additional embodiments are also described.12-27-2012
20130020625MANUFACTURING METHOD AND STRUCTURE OF NON-VOLATILE MEMORY - A non-volatile memory structure includes a substrate; a poly gate structure formed on the substrate; a contact etching stop layer formed over the poly gate structure and including at least a silicon nitride layer and a first silicon oxide layer overlying the silicon nitride layer; and an inter-layer dielectric layer formed on the first silicon oxide layer. The first silicon oxide layer has a density higher than that of the inter-layer dielectric layer.01-24-2013
20120241833NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, the storage device further includes: a first electrode that is formed in a reverse convex and in contact with an upper surface of a first region, parts of a side and an upper surface of a first isolation region that face a second isolation region, and parts of a side and an upper surface of the second isolation region that face the first isolation region; and a third electrode that is positioned in a different direction from a second direction with respect to the first electrode, formed in a reverse convex and in contact with an upper surface of a second region, parts of a side and the upper surface of the second isolation region that face a third isolation region, and parts of a side and an upper surface of the third isolation region that face the second isolation region.09-27-2012
20080237682Semiconductor memory with conductive carbon - A non-volatile memory capable of storing binary information on a semiconductor substrate comprising: a dual gate structure formed over the semiconductor substrate, wherein the dual gate structure including a gate dielectric layer formed over the semiconductor substrate, and first and second gates formed over the gate dielectric layer, an isolation layer formed between the first and second gates; a conductive carbon material with nano-scale formed under the gate dielectric layer; and a doped regions formed adjacent to the conductive carbon material.10-02-2008
20080237680Enabling flash cell scaling by shaping of the floating gate using spacers - According to embodiments of the invention, an inverted “T” shaped gate can be formed for transistor flash memory cells to reduce feature sizes, to reduce pitch size, to increase gate coupling ratio and/or to reduce parasitic capacitive effects between adjacent flash cells or cell floating gates, such as with optimization of control gate distance between field gates. Such feature sizes include channel width; isolation region width; width of a portion of a gate electrode and/or half-pitch distance between adjacent cells or rows of transistors (e.g., cells).10-02-2008
20090001441Three dimensional quantum dot array - In one embodiment of the invention, oxidation of silicon in a silicon germanium/silicon lattice may convert a two dimensional array of silicon germanium pillars into a structured three dimensional quantum dot array. The array may be included in, for example, flash memory floating gate, optical detector, or quantum computing device.01-01-2009
20110260232DEVICE INCLUDING MEMORY ARRAY AND METHOD THEREOF - An electronic device includes a first memory cell and a second memory cell, of a nonvolatile memory array. The first memory cell includes a body region, a gate structure, a source region, and a drain region. The second memory cell includes a body region, a gate structure, a source region, and a drain region. In one embodiment, the body of the second memory cell is physically isolated from the body region of the first memory cell. A bitline segment is electrically connected to the drain region of the first memory cell and to the drain region of the second memory cell.10-27-2011
20130181275MANUFACTURING METHOD OF NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND A NONVOLATILE SEMICONDUCTOR STORAGE DEVICE - A nonvolatile semiconductor storage device has a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, multiple floating gate electrodes formed on the gate insulating film, an inter-electrode insulating film formed on the multiple floating gate electrodes, and word lines formed on the inter-electrode insulating film. The word lines have lower and upper layers containing polysilicon doped with an impurity and are formed with a separating layer between the lower layer and the upper layer. A portion of the separating layer is located between multiple floating gate electrodes, and the height of the lower layer is less than the height of the upper layer.07-18-2013
20130092995ELECTRICAL ERASABLE PROGRAMMABLE READ-ONLY MEMORY AND MANUFACTURING METHOD THEREOF - An electrical erasable programmable read-only memory (EEPROM) including a floating transistor formed on a semiconductor substrate and a tunneling transistor formed on a semiconductor substrate and configured to erase electrons trapped in the floating transistor. The tunneling transistor has a source junction region and a drain junction region that are integrally joined by lateral diffusion. The EPROM maintains a small cell size without any additional mask process, and is useable as an MTP EEPROM because electrical erasure is enabled. In addition, the adjustment of the width of a gate constituting the tunneling transistor ensures an improved degree of freedom to adjust an erasure voltage can be enhanced.04-18-2013
20130092996NAND FLASH MEMORY DEVICES - NAND flash memory device includes a common bit line, a first cell string including a first string selecting transistor having a first gate length, a second string selecting transistor having a second gate length, first cell transistors each having a third gate length and a first ground selecting transistor having a fourth gate length, a second cell string including a third string selecting transistor having the first gate length, a fourth string selecting transistor having the second gate length, second cell transistors each having the third gate length and a second ground selecting transistor having the fourth gate length and a common source line commonly connected to end portions of the first and second ground selecting transistors included in the first and second cell strings. At least one of the first gate length and the second gate length is smaller than the fourth gate length.04-18-2013
20130113030SEMICONDUCTOR DEVICE - The performance of a semiconductor device including a nonvolatile memory is enhanced. Each of nonvolatile memory cells arranged over a silicon substrate includes: a first n-well; a second n-well formed in a place different from the place thereof; a selection transistor formed in the first n-well; and an electric charge storage portion having a floating gate electrode and a storage portion p-well. The floating gate electrode is so placed that it overlaps with part of the first n-well and the second n-well. The storage portion p-well is placed in the first n-well so that it partly overlaps with the floating gate electrode. In this nonvolatile memory cell, memory information is erased by applying positive voltage to the second n-well to discharge electrons in the floating gate electrode to the second n-well.05-09-2013
20110266608NONVOLATILE MEMORY DEVICES HAVING GATE STRUCTURES DOPED BY NITROGEN - Nonvolatile memory devices are provided including an integrated circuit substrate and a charge storage pattern on the integrated circuit substrate. The charge storage pattern has a sidewall and a tunnel insulating layer is provided between the charge storage pattern and the integrated circuit substrate. A gate pattern is provided on the charge storage pattern. A blocking insulating layer is provided between the charge storage pattern and the gate pattern. The sidewall of the charge storage pattern includes a first nitrogen doped layer. Related methods of fabricating nonvolatile memory devices are also provided herein.11-03-2011
20130126958Array Of Split Gate Non-volatile Floating Gate Memory Cells Having Improved Strapping Of The Coupling Gates - An array of non-volatile memory cells with spaced apart first regions extending in a row direction and second regions extending in a column direction, with a channel region defined between each second region and its associated first region. A plurality of spaced apart word line gates each extending in the row direction and positioned over a first portion of a channel region. A plurality of spaced apart floating gates are positioned over second portions of the channel regions. A plurality of spaced apart coupling gates each extending in the row direction and over the floating gates. A plurality of spaced apart metal strapping lines each extending in the row direction and overlying a coupling gate. A plurality of spaced apart erase gates each extending in the row direction and positioned over a first region and adjacent to a floating gate and coupling gate.05-23-2013
20080203459Method of manufacturing a semiconductor device and semiconductor device - A carrier is structured with isolation regions in a precise fashion. First structures and second structures are formed above a carrier. At least one of the second structures is removed selectively with respect to the first structures. At least one recess in the carrier is formed according to the structure thus obtained. An embodiment of a semiconductor device that may be produced in this way is provided with at least one insulating striplike region and/or a plurality of insulating regions that are arranged at distances from one another along a line.08-28-2008
20080197400Transistor constructions and processing methods - A transistor construction includes a first floating gate having a first conductive or semiconductive surface and a second floating gate having a second conductive or semiconductive surface. A dielectric region is circumferentially surrounded by the first surface. The region is configured to reduce capacitive coupling between the first and second surfaces. Another transistor construction includes a floating gate having a cavity extending completely through the floating gate from a first surface of the floating gate to an opposing second surface of the floating gate. The floating gate otherwise encloses the cavity, which is filled with at least one dielectric. A method includes closing an upper portion of an opening in insulator material with a gate material during the deposition before filling a lower portion with the gate material. The depositing and closing provide an enclosed cavity within the lower portion of the opening.08-21-2008
20110241094NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - According to one embodiment, a semiconductor memory device includes each of memory cells including a floating electrode above a semiconductor substrate via the gate insulator, a control gate electrode above the floating gate electrode via a first inter-gate insulator, first diffusion layers as source or drain, a contact electrode portion including a bottom electrode with an opening and a top electrode on the bottom electrode, the bottom electrode being arranged on the first gate insulator having the opening, the top electrode being electrically connected to the semiconductor substrate via the first opening, and a connection diffusion layer formed in the semiconductor substrate below the first opening.10-06-2011
20120256245SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device in accordance with one embodiment of the invention can include a semiconductor substrate having a groove, a bit line, a pocket implantation region, a bottom insulating membrane, and a charge accumulation region. The bit line is formed on a side of the groove in the semiconductor substrate and acts as a source and a drain. The pocket implantation region is formed to touch (or contact) the bit line, has a similar conductivity type as the semiconductor substrate, and has a dopant concentration higher than that of the semiconductor substrate. The bottom insulating membrane is formed on and touches (or contacts) a side surface of the groove. The charge accumulation layer is formed on and touches (or contacts) a side surface of the bottom insulating membrane.10-11-2012
20090321806NONVOLATILE MEMORY WITH FLOATING GATES WITH UPWARD PROTRUSIONS - Substrate isolation regions (12-31-2009
20100308392NONVOLATILE SEMICONDUCTOR STORAGE DEVICE - A control gate of a nonvolatile semiconductor storage device includes a first side surface on a side near a floating gate, a second side surface opposite to the first side surface, a silicide region formed in an upper portion of the control gate above the first side surface, and a protruding portion formed in an upper portion of the control gate above the second side surface. A side wall insulating film of the nonvolatile semiconductor storage device includes a first portion which covers at least a portion of the protruding portion without covering the silicide region, and a second portion which is provided continuously from the first portion and covers the second side surface with contacting the second side surface.12-09-2010
20120273864HIGH ENDURANCE NON-VOLATILE MEMORY CELL AND ARRAY - Systems of electrically programmable and erasable memory cell are disclosed. In one exemplary implementation, a cell may have two storage transistors in a substrate of semiconductor material of a first conductivity type. The first storage transistor is of the type having a first region and a second region each of a second conductivity type in the substrate. The second storage transistor is of the type having a third region and a fourth region each of a second conductivity type in the substrate. Arrays formed of such memory cells and non-volatile memory cells are also disclosed.11-01-2012
20130187215METHODS OF FORMING NANOSCALE FLOATING GATE - A memory cell is provided including a tunnel dielectric layer overlying a semiconductor substrate. The memory cell also includes a floating gate having a first portion overlying the tunnel dielectric layer and a second portion in the form of a nanorod extending from the first portion. In addition, a control gate layer is separated from the floating gate by an intergate dielectric layer.07-25-2013
20110233638SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THEREOF - The present invention provides a semiconductor device including a semiconductor substrate provided with a trench section; a tunnel insulating film covering an inner surface of the trench section; a trap layer provided in contact with the tunnel insulating film on an inner surface of an upper portion of the trench section; a top insulating film provided in contact with the trap layer; a gate electrode embedded in the trench section, and provided in contact with the tunnel insulating film at a lower portion of the trench section and in contact with the top insulating film at the upper portion of the trench section, in which the trap layer and the top insulating film, in between the lower portion of the trench section and the upper portion of the trench section, extend and protrude from both sides of the trench section so as to be embedded in the gate electrode, and a method for manufacturing thereof.09-29-2011
20110233637SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a method for manufacturing a semiconductor device comprises forming a first insulating film on a semiconductor substrate, processing the first insulating film into a predetermined pattern, forming a first gate electrode structure on the first insulating film, the first gate electrode structure having a smaller width than that of the processed first insulating film in a channel length direction, introducing a first impurity of a first conductivity type into the semiconductor substrate via the processed first insulting film using the first gate electrode structure as a mask, and introducing a second impurity of the first conductivity type into the semiconductor substrate using the first gate electrode structure and the first insulating film as a mask.09-29-2011
20120018790NON-VOLATILE MEMORY AND FABRICATING METHOD THEREOF - A non-volatile memory including a substrate, a stacked gate structure, two doped regions and a plurality of spacers is provided. The stacked gate structure is disposed on the substrate, wherein the stacked gate structure includes a first dielectric layer, a charge storage layer, a second dielectric layer and a conductive layer in sequence from bottom to top relative to the substrate. The doped regions are disposed in the substrate at two sides of the stacked gate structure, respectively, and bottom portions of the doped regions contact with the substrate under the doped regions. The spacers are respectively disposed between each side of each of the doped regions and the substrate, and top portions of the spacers are lower than top portions of the doped regions.01-26-2012
20130193504SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor device includes a substrate, a plurality of interconnects, and a plurality of gap control units. The substrate includes silicon. The plurality of interconnects is provided above the substrate. The plurality of gap control units is provided respectively on the plurality of interconnects to have width dimensions greater than width dimension of the plurality of interconnects. A gap is provided between adjacent interconnects of the plurality of interconnects. An apical portion of the gap is provided between adjacent gap control units of the plurality of gap control units and between a lower surface position and an upper surface position of each of the adjacent gap control units.08-01-2013
20120068245NON-VOLATILE MEMORY DEVICES INCLUDING BLOCKING INSULATION PATTERNS WITH SUB-LAYERS HAVING DIFFERENT ENERGY BAND GAPS - A non-volatile memory device may include a semiconductor substrate and an isolation layer on the semiconductor substrate wherein the isolation layer defines an active region of the semiconductor substrate. A tunnel insulation layer may be provided on the active region of the semiconductor substrate, and a charge storage pattern may be provided on the tunnel insulation layer. An interface layer pattern may be provided on the charge storage pattern, and a blocking insulation pattern may be provided on the interface layer pattern. Moreover, the block insulation pattern may include a high-k dielectric material, and the interface layer pattern and the blocking insulation pattern may include different materials. A control gate electrode may be provided on the blocking insulating layer so that the blocking insulation pattern is between the interface layer pattern and the control gate electrode. Related methods are also discussed.03-22-2012

Patent applications in class With floating gate electrode

Patent applications in all subclasses With floating gate electrode