Class / Patent application number | Description | Number of patent applications / Date published |
257312000 | Voltage variable capacitor (i. e., capacitance varies with applied voltage) | 22 |
20080203457 | FAST SWITCHING POWER INSULATED GATE SEMICONDUCTOR DEVICE - An insulated gate semiconductor device ( | 08-28-2008 |
20080237676 | Varactor and method for manufacturing the same - Disclosed is a varactor and/or variable capacitor. The varactor/variable capacitor includes a plurality of first conductive-type wells vertically formed on a substrate, a plurality of second conductive-type ion implantation areas formed in the first conductive-type wells, at least one second conductive-type plug electrically connected to the second conductive-type ion implantation areas, an isolation layer formed at sides of an uppermost second conductive-type ion implantation area, and a first conductive-type ion implantation area in an uppermost first conductive-type well electrically disconnected from the uppermost second conductive-type ion implantation area by the isolation area. | 10-02-2008 |
20080237677 | SEMICONDUCTOR VARIABLE CAPACITOR AND METHOD OF MANUFACTURING THE SAME - The semiconductor variable capacitor includes a capacitor including an n-well | 10-02-2008 |
20080246071 | MOS VARACTORS WITH LARGE TUNING RANGE - A MOS varactor includes a shallow PN junction beneath the surface of the substrate of a MOS structure. In depletion mode, the depletion region of the MOS structure merges with the depletion region of the shallow PN junction. This increases the total width of the depletion region of the MOS varactor to reduce C | 10-09-2008 |
20080315277 | SEMICONDUCTOR DEVICE - A semiconductor device | 12-25-2008 |
20090045446 | POWER SEMICONDUCTOR DEVICE - A power semiconductor device having a first active semiconductor component and a second active semiconductor component, the electrical connections of which are routed out of the semiconductor components in the form of connecting legs is disclosed. In one embodiment, the first semiconductor component is at least partially electrically connected to the second semiconductor component by means of a plug-in connection. The plug-in connection is realized by virtue of the connecting legs of the second semiconductor component engaging in the electrical connections of the first semiconductor component. | 02-19-2009 |
20090057742 | CMOS VARACTOR - A varactor and method of fabricating the varactor. The varactor includes a silicon body in a silicon layer of an SOI substrate; a polysilicon electrode comprising a gate region and a plate region separated from the body by a gate dielectric layer, the gate and plate regions contiguous, the electrode electrically connected to a first pad; and a source formed in the body on a first side of the gate region, a drain formed in the body on a second and opposite side of the gate region, and a body contact formed in the body on a side of the plate region away from the gate region, the source, drain and body contact, separated from each other by regions of the body under the electrode, the source, drain and body contact electrically connected to each other and to a second pad. | 03-05-2009 |
20090108320 | TUNABLE CAPACITOR - Disclosed are embodiments of a design structure transistor that operates as a capacitor and an associated method of tuning capacitance within such a capacitor. The embodiments of the capacitor comprise a field effect transistor with front and back gates above and below a semiconductor layer, respectively. The capacitance value exhibited by the capacitor can be selectively varied between two different values by changing the voltage condition in a source/drain region of the transistor, e.g., using a switch or resistor between the source/drain region and a voltage supply. Alternatively, the capacitance value exhibited by the capacitor can be selectively varied between multiple different values by changing voltage conditions in one or more of multiple channel regions that are flanked by multiple source/drain regions within the transistor. The capacitor will exhibit different capacitance values depending upon the conductivity in each of the channel regions. | 04-30-2009 |
20090250739 | Device Structures with a Hyper-Abrupt P-N Junction, Methods of Forming a Hyper-Abrupt P-N Junction, and Design Structures for an Integrated Circuit - Device structures with hyper-abrupt p-n junctions, methods of forming hyper-abrupt p-n junctions, and design structures for an integrated circuit containing devices structures with hyper-abrupt p-n junctions. The hyper-abrupt p-n junction is defined in a SOI substrate by implanting a portion of a device layer to have one conductivity type and then implanting a portion of this doped region to have an opposite conductivity type. The counterdoping defines the hyper-abrupt p-n junction. A gate structure carried on a top surface of the device layer operates as a hard mask during the ion implantations to assist in defining a lateral boundary for the hyper-abrupt-n junction. | 10-08-2009 |
20100117133 | MOS VARACTORS WITH LARGE TUNING RANGE - A device is presented. The device includes a substrate with a first well of a first polarity type. The first well defines a varactor region and comprises a lower first well boundary located above a bottom surface of the substrate. A second well in the varactor region is also included in the device. The second well comprises a buried well of a second polarity type having an upper second well boundary disposed below an upper portion of the first well from an upper first well boundary to the upper second well boundary and a lower second well boundary disposed above the lower first well boundary, wherein an interface of the second well and the upper portion of the first well forms a shallow PN junction in the varactor region. The device also includes a gate structure in the varactor region. The upper portion of the first well beneath the gate structure forms a channel region of the device. In depletion mode, a depletion region under the gate structure in the channel region merges with a depletion region of the shallow PN junction. | 05-13-2010 |
20100244113 | MOS VARACTOR AND FABRICATING METHOD OF THE SAME - The present invention provides a MOS varactor for use in circuits and elements of a millimeter-wave frequency band, which is capable of reducing series resistance and enhancing a Q-factor by using a plurality of island-like gates seated in a well region of a substrate and gate contacts directly over the gates, and a method of fabricating the MOS varactor. The MOS varactor include: island-like gate insulating layers which are arranged at equal intervals in the form of a (n×m) matrix (where, n and m are integers equal to or larger than one), and a gate electrode of a first height (t1) placed on the gate insulating layers in a well region of a substrate; a gate contact which contacts the gate electrode; a first metal wire of a second height (t2) (where, t109-30-2010 | |
20110089477 | NANOSTRUCTURED MOS CAPACITOR - The present invention provides nanostructured MOS capacitor that comprises a nanowire (2) at least partly enclosed by a dielectric layer (5) and a gate electrode (4) that encloses at least a portion of the dielectric layer (5). Preferably the nanowire (2) protrudes from a substrate (12). The gate electrode (4) defines a gated portion (7) of the nanowire (2), which is allowed to be fully depleted when a first predetermined voltage is applied to the gate electrode (4). A method for providing a variable capacitance in an electronic circuit by using such an nanostructured MOS capacitor is also provided. Thanks to the invention it is possible to provide a MOS capacitor having an increased capacitance modulation range. It is a further advantage of the invention to provide a MOS capacitor which has relatively low depletion capacitance compared to prior art MOS capacitances. | 04-21-2011 |
20110291171 | VARACTOR - A variable capacitance device including a plurality of FETs, the sources and drains of each FET being coupled to a first terminal, the gates of each FET being coupled to a second terminal, the capacitance of said device between said first and second terminals varying as a function of the voltage across said terminals, the device further including a biasing providing a respective backgate bias voltage to each the FETs setting a respective gate threshold voltage thereof. The aggregate V-C characteristic can be tuned as desired, either at design time or dynamically. The greater the number of FETs forming the varactor, the greater the number of possible Vt values that can be individually set, so that arbitrary V-C characteristics can be more closely approximated. | 12-01-2011 |
20110309420 | Capacitors Integrated with Metal Gate Formation - A semiconductor structure including a capacitor having increased capacitance and improved electrical performance is provided. The semiconductor structure includes a substrate and a MIM capacitor over the substrate. The MIM capacitor includes a bottom plate, an insulating layer over the bottom plate, and a top plate over the insulating layer. The semiconductor structure further includes a MOS device including a gate dielectric over the substrate and a metal-containing gate electrode free from polysilicon on the gate dielectric, wherein the metal-containing gate electrode is formed of a same material and has a same thickness as the bottom plate. | 12-22-2011 |
20110316062 | SEMICONDUCTOR DEVICE - In terms of achieving a reduction in the cost of an antenna switch, there is provided a technology capable of minimizing harmonic distortion generated in the antenna switch even when the antenna switch is particularly formed of field effect transistors formed over a silicon substrate. Between the source region and the drain region of each of a plurality of MISFETs coupled in series, a distortion compensating capacitance circuit is coupled which has a voltage dependency such that, in either of the cases where a positive voltage is applied to the drain region based on the potential of the source region and where a negative voltage is applied to the drain region based on the potential of the source region, the capacitance decreases to a value smaller than that in a state where the potential of the source region and the potential of the drain region are at the same level. | 12-29-2011 |
20130009228 | DIFFERENTIAL VARACTOR DEVICE - The present invention provides a differential varactor device including a substrate having a first conductive type, a well having a second conductive type, five doped regions having the second conductive type, a first gate, a second gate, a third gate, and a fourth gate. The well is disposed in the substrate, and the doped regions are disposed in the well and arranged along a direction. The first gate, the second gate, the third gate and the fourth gate are respectively disposed on the well between any two of the adjacent doped regions, and are arranged sequentially along the direction. | 01-10-2013 |
20130119449 | SEMICONDUCTOR DEVICE WITH SEAL RING WITH EMBEDDED DECOUPLING CAPACITOR - A seal ring for semiconductor devices is provided with embedded decoupling capacitors. The seal ring peripherally surrounds an integrated circuit chip in a seal ring area. The at least one embedded decoupling capacitor may include MOS capacitors, varactors, MOM capacitors and interdigitized capacitors with multiple capacitor plates coupled together. The opposed capacitor plates are coupled to different potentials and may advantageously be coupled to V | 05-16-2013 |
20140239364 | MOS Varactor Optimized Layout and Methods - Apparatus and methods for a MOS varactor structure are disclosed. An apparatus is provided, comprising an active area defined in a portion of a semiconductor substrate; a doped well region in the active area extending into the semiconductor substrate; at least two gate structures disposed in parallel over the doped well region; source and drain regions disposed in the well region formed on opposing sides of the gate structures; a gate connector formed in a first metal layer overlying the at least two gate structures and electrically coupling the at least two gate structures; source and drain connectors formed in a second metal layer and electrically coupled to the source and drain regions; and interlevel dielectric material separating the source and drain connectors in the second metal layer from the gate connector formed in the first metal layer. Methods for forming the structure are disclosed. | 08-28-2014 |
20150318406 | CONTINUOUS TUNABLE LC RESONATOR USING A FET AS A VARACTOR - A varactor includes a field effect transistor (FET) integrated with at least a portion of a bipolar junction transistor (BJT), in which a back gate of the FET shares an electrical connection with a base of the BJT, and in which a reverse voltage applied to the back gate of the FET creates a continuously variable capacitance in a channel of the FET. | 11-05-2015 |
20150372155 | Controllable Integrated Capacitive Device - An integrated circuit includes several metallization levels separated by an insulating region. A hollow housing whose walls comprise metallic portions is produced within various metallization levels. A controllable capacitive device includes a suspended metallic structure situated in the hollow housing within a first metallization level including a first element fixed on two fixing zones of the housing and at least one second element extending in cantilever fashion from the first element and includes a first electrode of the capacitive device. A second electrode includes a first fixed body situated at a second metallization level adjacent to the first metallization level facing the first electrode. The first element is controllable in flexion from a control zone of this first element so as to modify the distance between the two electrodes. | 12-24-2015 |
20160204282 | Multi-Gate and Complementary Varactors in FinFET Process | 07-14-2016 |
20160379993 | TUNABLE CAPACITOR FOR FDSOI APPLICATIONS - The present disclosure provides in one aspect a semiconductor device including an SOI substrate with an active semiconductor layer disposed on a buried insulating material layer, which, in turn, is formed on a base substrate material, a gate structure formed on the active semiconductor layer, and a back gate region provided in the base substrate material below the gate structure opposing the gate structure. Herein, the back gate region may be electrically insulated from the surrounding base substrate material via an isolation region surrounding the back gate region. | 12-29-2016 |