| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 257303000 | Stacked capacitor | 26 |
| 20100072532 | Recessed Access Device For A Memory - Semiconductor memory devices having recessed access devices are disclosed. In some embodiments, a method of forming the recessed access device includes forming a device recess in a substrate material that extends to a first depth in the substrate that includes a gate oxide layer in the recess. The device recess may be extended to a second depth that is greater that the first depth to form an extended portion of the device recess. A field oxide layer may be provided within an interior of the device recess that extends inwardly into the interior of the device recess and into the substrate. Active regions may be formed in the substrate that abut the field oxide layer, and a gate material may be deposited into the device recess. | 03-25-2010 |
| 20130087841 | PLATED STRUCTURES - A method and structure is directed to eDRAM cells with high-conductance electrodes. The method includes forming upper layers on a semiconductor substrate and forming an opening in the upper layers. The method further includes forming a trench in the semiconductor substrate, aligned with the opening. The method further includes forming a metal plate on all exposed surface in the trench by applying a metallic aqueous solution with an electrical bias to a backside of the semiconductor substrate | 04-11-2013 |
| 20090008693 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - A technique for enhancing the performance of a memory- and logic-equipped semiconductor device is provided. The semiconductor device comprises a semiconductor substrate ( | 01-08-2009 |
| 20080211002 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - This semiconductor device includes: a first cylinder interlayer insulating film; a second cylinder interlayer insulating film; a cylinder hole including a first cylinder hole and a second cylinder hole communicating with the first cylinder hole; and a capacitor including a lower electrode and an upper electrode. The first cylinder interlayer insulating film has an etching rate for etchant, which is two to six times as high as an etching rate for the second cylinder interlayer insulating film, a hole diameter of the first cylinder hole is larger than that of the second cylinder hole, and the hole diameter of the second cylinder hole near an interface between the first cylinder interlayer insulating film and the second cylinder interlayer insulating film increases as the second cylinder hole approaches the interface. | 09-04-2008 |
| 20100283093 | Structure and Method to Form EDRAM on SOI Substrate - A memory device is provided that in one embodiment includes a trench capacitor located in a semiconductor substrate including an outer electrode provided by the semiconductor substrate, an inner electrode provided by a conductive fill material, and a node dielectric layer located between the outer electrode and the inner electrode; and a semiconductor device positioned centrally over the trench capacitor. The semiconductor device includes a source region, a drain region, and a gate structure, in which the semiconductor device is formed on a semiconductor layer that is separated from the semiconductor substrate by a dielectric layer. A first contact is present extending from an upper surface of the semiconductor layer into electrical contact with the semiconductor substrate, and a second contact from the drain region of the semiconductor device in electrical contact to the conductive material within the at least one trench. | 11-11-2010 |
| 20090166702 | TRENCH-TYPE SEMICONDUCTOR DEVICE STRUCTURE - A trench-type semiconductor device structure is disclosed. The structure includes a semiconductor substrate, a gate dielectric layer and a substrate channel structure. The semiconductor substrate includes a trench having an upper portion and a lower portion. The upper portion includes a conductive layer formed therein. The lower portion includes a trench capacitor formed therein. The gate dielectric layer is located between the semiconductor substrate and the conductive layer. The substrate channel structure with openings, adjacent to the trench, is electrically connected to the semiconductor substrate via the openings. | 07-02-2009 |
| 20090315092 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device provided with a field-effect transistor, the field-effect transistor including: a active region defined by element isolating region | 12-24-2009 |
| 20080258197 | SEMICONDUCTOR-INSULATOR-SILICIDE CAPACITOR - A semiconductor-insulator-silicide (SIS) capacitor is formed by depositing a thin silicon containing layer on a salicide mask dielectric layer, followed by lithographic patterning of the stack and metallization of the thin silicon containing layer and other exposed semiconductor portions of a semiconductor substrate. The thin silicon containing layer is fully reacted during metallization and consequently converted to a silicide alloy layer, which is a first electrode of a capacitor. The salicide mask dielectric layer is the capacitor dielectric. The second electrode of the capacitor may be a doped polycrystalline silicon containing layer, a doped single crystalline semiconductor region, or another doped polycrystalline silicon containing layer disposed on the doped polycrystalline silicon containing layer. The SIS insulator may further comprise other dielectric layers and conductive layers to increase capacitance per area. | 10-23-2008 |
| 20090184357 | SOI BASED INTEGRATED CIRCUIT AND METHOD FOR MANUFACTURING - A SOI based integrated circuit and method for manufacturing a SOI based integrated circuit is disclosed. One embodiment provides an integrated circuit having a silicon-on-insulator carrier including a substrate, a buried insulating layer on the substrate and a semiconductor layer on the buried insulating layer. A trench extends at least through the semiconductor layer and into the buried insulating layer. A conductive region is formed in the buried insulating layer, wherein the conductive region partly surrounds the trench and is configured to interconnect the semiconductor layer and the substrate. | 07-23-2009 |
| 20090101958 | TRENCH SOI-DRAM CELL AND METHOD FOR MAKING THE SAME - The present invention relates to a trench silicon-on-insulator (SOI) dynamic random access memory (DRAM) cell and a method for making the same. A source and a drain are utilized to each connect to one of two semiconductor conductive units on an external side of a main body having a plurality of semiconductor conductive units, and the semiconductor conductive units are utilized to accumulate electric charges generated from the drain so as to decrease a threshold voltage. In addition, the DRAM cell only uses one field effect transistor (FET) device ( | 04-23-2009 |
| 20090166703 | MEMORY DEVICE WITH A LENGTH-CONTROLLABLE CHANNEL - A memory device is provided. The memory device includes a substrate, a trench having an upper portion and a lower portion formed in the substrate, a trench capacitor formed in the lower portion of the trench, a collar dielectric layer formed on a sidewall of the trench capacitor and extending away from a top surface of the substrate, a first doping region formed on a side of the upper portion of the trench in the substrate for serving as source/drain, a conductive layer formed in the trench and electrically connected to the first doping region, a top dielectric layer formed on conductive layer, a gate formed on the top dielectric layer, an epitaxy layer formed on both sides of the gate and on the substrate and a second doping area formed on a top of the epitaxy layer for serving as source/drain. | 07-02-2009 |
| 20120091519 | METHOD AND APPARATUS FOR IMPROVING CAPACITOR CAPACITANCE AND COMPATIBILITY - A semiconductor device includes a semiconductor substrate, an isolation structure disposed in the semiconductor substrate, a conductive layer disposed over the isolation structure, a capacitor disposed over the isolation structure, the capacitor including a top electrode, a bottom electrode, and a dielectric disposed between the top electrode and the bottom electrode, and a first contact electrically coupling the conductive layer and the bottom electrode, the bottom electrode substantially engaging the first contact on at least two faces. | 04-19-2012 |
| 20100187587 | MEMORY CELL STRUCTURE AND METHOD FOR FABRICATION THEREOF - A memory cell includes a substrate, an access transistor and a storage capacitor. The access transistor comprising a gate stack disposed on the substrate, and a first and second diffusion region located on a first and second opposing sides of the gate stack. The storage capacitor comprises a first capacitor plate comprising a portion embedded within the substrate below the first diffusion region, a second capacitor plate and a capacitor dielectric sandwiched between the embedded portion of the first capacitor plate. At least a portion of the first diffusion region forms the second capacitor plate. | 07-29-2010 |
| 20090020798 | TRANSISTOR STRUCTURE AND METHOD OF MAKING THE SAME - A transistor structure includes a gate trench. The gate trench includes a bottle-shape bottom. The bottle-shape bottom includes a first conductive material wider than its top. The top includes a second material in a substrate, a gate structure on the gate trench and electrically connected to the first conductive material, a source/drain doping region adjacent to the gate trench and a gate channel between the source/drain doping region. | 01-22-2009 |
| 20110057240 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a plurality of conduction plugs disposed on an active region, a bit line connected to a conduction plug of the plurality of conduction plugs which is disposed in a central portion of the active region, and storage nodes connected with conduction plugs of the plurality of conduction plugs which are disposed at both peripherals of the active region and passing over the active region. | 03-10-2011 |
| 20090039403 | SEMICONDUCTOR DEVICE INCLUDING AN IMPROVED CAPACITOR AND METHOD FOR MANUFACTURING THE SAME - In a semiconductor device according to embodiments of the invention, a capacitor includes a storage electrode having a cylindrical storage conductive layer pattern and connecting members formed on the upper portion of the cylindrical storage conductive layer pattern. The connecting member connects to an adjacent connecting member of another storage electrode. A dielectric layer and a plate electrode are successively formed on the storage electrode. All of the capacitors are connected by one another by forming cylindrical storage electrodes so that the storage electrode does not fall down when the capacitors have an extremely large aspect ratio. Thus, the capacitance of the capacitors may be improved to the desired level. A semiconductor device that includes these capacitors may have improved reliability and the throughput of a semiconductor manufacturing process may be increased. | 02-12-2009 |
| 20090072290 | SOI CMOS COMPATIBLE MULTIPLANAR CAPACITOR - An isolated shallow trench isolation portion is formed in a top semiconductor portion of a semiconductor-on-insulator substrate along with a shallow trench isolation structure. A trench in the shape of a ring is formed around a doped top semiconductor portion and filled with a conductive material such as doped polysilicon. The isolated shallow trench isolation portion and the portion of a buried insulator layer bounded by a ring of the conductive material are etched to form a cavity. A capacitor dielectric is formed on exposed semiconductor surfaces within the cavity and above the doped top semiconductor portion. A conductive material portion formed in the trench and above the doped top semiconductor portion constitutes an inner electrode of a capacitor, while the ring of the conductive material, the doped top semiconductor portion, and a portion of a handle substrate abutting the capacitor dielectric constitute a second electrode. | 03-19-2009 |
| 20100038694 | SPLIT-GATE DRAM WITH MUGFET, DESIGN STRUCTURE, AND METHOD OF MANUFACTURE - A semiconductor structure for a dynamic random access memory cell, the structure including: a fin of a fin-type field effect transistor (FinFET) device formed over and spaced apart from a conductive region of a substrate; a storage capacitor connected to a first end of the fin; and a back-gate at a first lateral side of the fin and in electrical contact with the conductive region. | 02-18-2010 |
| 20080237675 | Capacitor, method of increasing a capacitance area of same, and system containing same - A capacitor includes a substrate ( | 10-02-2008 |
| 20110049600 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In a method of manufacturing a semiconductor device, first contact holes reaching diffusion regions of a cell transistor, bit line contact holes reaching diffusion regions of the cell transistor, and interconnect grooves communicating with the bit line contact holes are buried in a first insulating film. In addition, first contact plugs and bit line contacts are respectively formed by burying conductive materials in the first contact holes, the bit line contact holes and the interconnect grooves, and the first contact plugs are electrically connected to a capacitor formed in a third insulating film through an opening formed in a second insulating film. | 03-03-2011 |
| 20110095349 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - A technique for enhancing the performance of a memory- and logic-equipped semiconductor device is provided. The semiconductor device comprises a semiconductor substrate ( | 04-28-2011 |
| 20100019301 | Dynamic random access memory structure - A dynamic random access memory structure includes a recessed-gate transistor disposed in the substrate; a trench capacitor structure disposed in the substrate and electrically connected to a first source/drain of the recessed-gate transistor; a first conductive structure disposed on and contacting the trench capacitor structure; a stack capacitor structure disposed on and contacting the first conductive structure, wherein a bottom electrode of the trench capacitor structure and a top electrode of the stack capacitor structure are electrically connected to serve as a common electrode; and a bit line disposed above a second source/drain of the recessed-gate transistor and electrically connected to the second source/drain, wherein the top of the bit line is lower than the top of the gate conductive layer of the recessed-gate transistor. | 01-28-2010 |
| 20120001245 | Recessed Access Device for a Memory - Semiconductor memory devices having recessed access devices are disclosed. In some embodiments, a method of forming the recessed access device includes forming a device recess in a substrate material that extends to a first depth in the substrate that includes a gate oxide layer in the recess. The device recess may be extended to a second depth that is greater that the first depth to form an extended portion of the device recess. A field oxide layer may be provided within an interior of the device recess that extends inwardly into the interior of the device recess and into the substrate. Active regions may be formed in the substrate that abut the field oxide layer, and a gate material may be deposited into the device recess. | 01-05-2012 |
| 20080246069 | Folded Node Trench Capacitor - A trench capacitor is filled with a set of two or more storage plates by consecutively depositing layers of dielectric and conductor and making contact to the ground plates by etching an aperture through the plates to the buried plate in the substrate and connecting the one or more ground plate to the substrate; the charge storage plates are connected at the top of the capacitor by blocking the end of the first plate during the formation of the second ground plate and exposing the material of the first storage plate during deposition of the second storage plate. | 10-09-2008 |
| 20090096001 | Integrated Circuit and Method of Manufacturing the Same - A method of manufacturing an integrated circuit includes: forming a trench in a substrate, forming a high-k dielectric layer lining the trench, and removing a section of the high-k dielectric layer from the trench via an isotropic dry etch process. | 04-16-2009 |
| 20120091520 | SEMICONDUCTOR DEVICE, METHOD FOR FORMING THE SAME, AND DATA PROCESSING SYSTEM - A semiconductor device includes a semiconductor substrate, a first interlayer insulating film over the semiconductor substrate, a first interconnect over the first interlayer insulating film, and a via plug penetrating the semiconductor substrate and the first interlayer insulating film. The via plug is coupled to the first interconnect. | 04-19-2012 |
