| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 257300000 | Capacitor coupled to, or forms gate of, insulated gate field effect transistor (e.g., non-destructive readout dynamic memory cell structure) | 51 |
| 20100109063 | Semiconductor device having MOS gate capacitor - To provide a PMOS transistor that is arranged within an N-well formed in a P-type semiconductor substrate and that is connected to an external terminal; and an MOS gate capacitor that is positioned adjacent to the PMOS transistor and of which one end and the other end are supplied with a power supply potential and a ground potential, respectively. An N-type diffusion layer that becomes a cathode of a PNPN parasitic thyristor configured by the PMOS transistor and the MOS gate capacitor is fixed to the power supply potential. This structure does not permit turning on of the PNPN parasitic thyristor, and thus a problem that a device is broken by a latch-up phenomenon is eliminated. | 05-06-2010 |
| 20090267125 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - An isolation region comprises a step structure comprising a step surface that is perpendicular to a depth direction, an upper isolation region and a lower isolation region. An RC transistor is enclosed by the isolation region. | 10-29-2009 |
| 20100327335 | METHOD OF BUILDING COMPENSATED ISOLATED P-WELL DEVICES - Electrical device structures constructed in an isolated p-well that is wholly contained within a core n-well. Methods of forming electrical devices within an isolated p-well that is wholly contained within a core n-well using a baseline CMOS process flow. | 12-30-2010 |
| 20100308390 | MEMORY CELL SUITABLE FOR DRAM MEMORY - The present invention relates to a memory cell with a memory capacitor ( | 12-09-2010 |
| 20090152613 | SEMICONDUCTOR MEMORY DEVICE HAVING A FLOATING BODY CAPACITOR AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory device having a floating body capacitor. The semiconductor memory device can perform a memory operation using the floating body capacitor. The semiconductor memory device includes an SOI substrate having a staked structure in which a base substrate having a conducting surface, a buried insulating layer and a device-forming layer are staked, a transistor formed in a portion of the device-forming layer, having a gate, a source region and a drain region, and a capacitor formed by the buried insulating layer, the conducting surface of the base substrate, and accumulated holes generated in the device-forming layer when the transistor is driven. | 06-18-2009 |
| 20110291169 | REDUCED CORNER LEAKAGE IN SOI STRUCTURE AND METHOD - A structural alternative to retro doping to reduce transistor leakage is provided by providing a liner in a trench, undercutting a conduction channel region in an active semiconductor layer, etching a side, corner and/or bottom of the conduction channel where the undercut exposes semiconductor material in the active layer and replacing the removed portion of the conduction channel with insulator. This shaping of the conduction channel increases the distance to adjacent circuit elements which, if charged, could otherwise induce a voltage and cause a change in back-channel threshold in regions of the conduction channel and narrows and reduces cross-sectional area of the channel where the conduction in the channel is not well-controlled; both of which effects significantly reduce leakage of the transistor. | 12-01-2011 |
| 20110291170 | Semiconductor Device Comprising a Buried Capacitor Formed in the Contact Level - In a semiconductor device, capacitors may be formed so as to be in direct contact with a transistor by using a shared transistor region, such as a drain region or a source region of closely spaced transistors, as one capacitor electrode, while the other capacitor electrode is provided in the form of a buried electrode in the dielectric material of the contact level. To this end, dielectric material may be deposited so as to reliably form a void, wherein, at any appropriate manufacturing stage, a capacitor dielectric material may be provided so as to separate the capacitor electrodes. | 12-01-2011 |
| 20090140311 | Method of fabricating semiconductor device having storage capacitor and higher voltage resistance capacitor and semiconductor device fabricated using the same - Provided are a method of fabricating a semiconductor device having different kinds of capacitors, and a semiconductor device formed using the same. In a fabrication process, after preparing a substrate including a storage capacitor region and a higher voltage resistance capacitor region, a lower electrode layer may be formed on the storage capacitor region and the higher voltage resistance capacitor region. A first dielectric film may be formed on the lower electrode layer, and the first dielectric film of the storage capacitor region may be selectively removed to expose the lower electrode layer of the storage capacitor region. After forming a second dielectric film on the first dielectric film and the exposed lower electrode layer of the storage capacitor region, an upper electrode layer may be formed on the second dielectric film. | 06-04-2009 |
| 20080237674 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate and a metal-oxide semiconductor transistor. A first dielectric layer of the metal oxide semiconductor transistor overlaps source and drain electrodes and a channel region of the transistor. A first drain region is away from the channel region and the first dielectric layer. A second drain region is between the first drain region and the channel region. A gate electrode is on the first dielectric layer and connected to a gate wire, and includes first and second gate layers and a dielectric layer therebetween. The first gate layer has one edge laterally spaced from the first drain region and resting over the second drain region, and is isolated from the gate wire. The second gate layer is over the first gate layer and is connected to the gate wire. | 10-02-2008 |
| 20080290388 | Semiconductor contructions - The invention includes a method in which a semiconductor substrate is provided to have a memory array region, and a peripheral region outward of the memory array region. Paired transistors are formed within the memory array region, with such paired transistors sharing a source/drain region corresponding to a bitline contact location, and having other source/drain regions corresponding to capacitor contact locations. A peripheral transistor gate is formed over the peripheral region. Electrically insulative material is formed over the peripheral transistor gate, and also over the bitline contact location. The insulative material is patterned to form sidewall spacers along sidewalls of the peripheral transistor gate, and to form a protective block over the bitline contact location. Subsequently, capacitors are formed which extend over the protective block, and which electrically connect with the capacitor contact locations. The invention also includes semiconductor constructions. | 11-27-2008 |
| 20090206381 | Anti-fuse and method for forming the same, unit cell of nonvolatile memory device with the same - An anti-fuse includes a gate dielectric layer formed over a substrate, a gate electrode including a body portion and a plurality of protruding portions extending from the body portion, wherein the body portion and the protruding portions are formed to contact on the gate dielectric layer, and a junction region formed in a portion of the substrate exposed by sidewalls of the protruding portions. | 08-20-2009 |
| 20090289290 | NON-VOLATILE MEMORY WITH PROGRAMMABLE CAPACITANCE - Non-volatile memory with programmable capacitance is disclosed. Illustrative data memory units include a substrate including a source region and a drain region. A first insulating layer is over the substrate. A second insulating layer is over the substrate and between the source region and drain region. A solid electrolyte layer is between the first insulating layer and second insulating layer. The solid electrolyte layer has a capacitance that is controllable between at least two states. A first electrode is electrically coupled to a first side of the solid electrolyte layer and is electrically coupled to a voltage source. A second electrode is electrically coupled to a second side of the solid electrolyte layer and is electrically coupled to the voltage source. Multi-bit memory units are also disclosed. | 11-26-2009 |
| 20120292680 | SEMICONDUCTOR INTEGRATED CIRCUIT - To reduce power consumption of a memory device. To reduce the area of a memory device. To reduce the number of transistors included in a memory device. The memory device includes a comparator comparing a first output signal with a second output signal, a first memory portion including a first oxide semiconductor transistor and a first silicon transistor, a second memory portion including a second oxide semiconductor transistor and a second silicon transistor, and an output potential determiner determining a potential of the first output signal and a potential of the second output signal. One of a source and a drain of the first oxide semiconductor transistor is electrically connected to a gate of the first silicon transistor. One of a source and a drain of the second oxide semiconductor transistor is electrically connected to a gate of the second silicon transistor. | 11-22-2012 |
| 20080290387 | Semiconductor device having reduced sub-threshold leakage - A semiconductor device fabricated in the semiconductor substrate includes a FinFET transistor having opposed source and drain pillars, and a fin interposed between the source and drain pillars. A cavity is formed in the semiconductor substrate extending at least partially between the fin and the semiconductor substrate. The cavity may be formed within a shallow trench isolation structure, and it may also extend at least partially between the semiconductor substrate and one or both of the pillars. The cavities increase the impedance between the semiconductor substrate and the fin and/or pillars to decrease the sub-threshold leakage of the FinFET transistor. | 11-27-2008 |
| 20110204428 | IMPLEMENTING EDRAM STACKED FET STRUCTURE - A method and circuit for implementing an embedded dynamic random access memory (eDRAM), and a design structure on which the subject circuit resides are provided. The embedded dynamic random access memory (eDRAM) circuit includes a stacked field effect transistor (FET) and capacitor. The capacitor is fabricated directly on top of the FET to build the eDRAM. | 08-25-2011 |
| 20090321804 | SEMICONDUCTOR COMPONENT INCLUDING A DRIFT ZONE AND A DRIFT CONTROL ZONE - A semiconductor component including a drift zone and a drift control zone. One embodiment provides a transistor component having a drift zone, a body zone, a source zone and a drain zone. The drift zone is arranged between the body zone and the drain zone. The body zone is arranged between the source zone and the drift zone. | 12-31-2009 |
| 20090242952 | INTEGRATED CIRCUIT INCLUDING A CAPACITOR AND METHOD - An integrated circuit including a capacitor and a method of fabricating an integrated circuit. The capacitor has a first electrode. A plurality of conductive lines is separated from each other and is configured to be held at a potential being the same for all conductive lines. A second electrode encloses individual ones of the conductive lines at a top side and at least one lateral side and is separated from the first electrode by a dielectric layer. The second electrode includes a polycrystalline semiconductor material, a metal or a metal-semiconductor compound. | 10-01-2009 |
| 20110233633 | Semiconductor Device and Electronic Apparatus Having the Same - With an offset circuit including transistors of the same conductivity type, offset of an input signal is performed. Then, the input signal after the offset is supplied to a logic circuit including transistors of the same conductivity type as that of the offset circuit, thereby H and L levels of the input signal can be shifted at the same time. Further, since the offset circuit and the logic circuit are formed using the transistors of the same conductivity type, a display device can be manufactured at a low cost. | 09-29-2011 |
| 20100187586 | SOI DEVICE AND METHOD FOR ITS FABRICATION - A silicon on insulator (SOI) device is provided. The device includes an MOS capacitor coupled between voltage busses and formed in a monocrystalline semiconductor layer overlying an insulator layer and a semiconductor substrate. The device includes at least one electrical discharge path for discharging potentially harmful charge build up on the MOS capacitor. The MOS capacitor has a conductive electrode material forming a first plate of the MOS capacitor and an impurity doped region in the monocrystalline silicon layer beneath the conductive electrode material forming a second plate. A first voltage bus is coupled to the first plate of the capacitor and to an electrical discharge path through a diode formed in the semiconductor substrate and a second voltage bus is coupled to the second plate of the capacitor. | 07-29-2010 |
| 20100224924 | TECHNIQUES FOR FORMING A CONTACT TO A BURIED DIFFUSION LAYER IN A SEMICONDUCTOR MEMORY DEVICE - Techniques for forming a contact to a buried diffusion layer in a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device. The semiconductor memory device may comprise a substrate comprising an upper layer. The semiconductor memory device may also comprise an array of dummy pillars formed on the upper layer of the substrate and arranged in rows and columns. Each of the dummy pillars may extend upward from the upper layer and have a bottom contact that is electrically connected with the upper layer of the substrate. The semiconductor memory device may also comprise an array of active pillars formed on the upper layer of the substrate and arranged in rows and columns. Each of the active pillars may extend upward from the upper layer and have an active first region, an active second region, and an active third region. Each of the active pillars may also be electrically connected with the upper layer of the substrate. | 09-09-2010 |
| 20100237395 | SEMICONDUCTOR DEVICE WITH GATE DIELECTRIC CONTAINING MIXED RARE EARTH ELEMENTS - A semiconductor device, such as a transistor or capacitor, is provided. The device includes a substrate, a gate dielectric over the substrate, and a conductive gate electrode film over the gate dielectric. The gate dielectric includes a mixed rare earth nitride or oxynitride film containing at least two different rare earth metal elements. | 09-23-2010 |
| 20100224923 | Semiconductor memory device and method of manufacturing the same - Provided are a semiconductor memory device and a method of manufacturing the same. The semiconductor memory device may include a plurality of active pillars projecting from a semiconductor substrate, a gate pattern disposed on at least a portion of each of the active pillars with a gate insulator interposed therebetween, and a conductive line disposed on each of the active pillars and below the corresponding gate pattern, the conductive line may be insulated from the semiconductor substrate and the gate pattern, wherein each of the active pillars may include a drain region above the corresponding gate pattern, a body region adjacent to the corresponding gate pattern, and a source region that is in contact with the conductive line below the gate pattern. | 09-09-2010 |
| 20090273012 | High Voltage Tolerant Metal-Oxide-Semiconductor Device - A method for increasing a voltage tolerance of a MOS device having a first capacitance value associated therewith is provided. The method includes the steps of: connecting at least a first capacitor in series with the MOS device, the first capacitor having a first capacitance value associated therewith, the first capacitor having a first terminal coupled to a gate of the MOS device and a second terminal adapted to receive a first signal; and adjusting a ratio of the first capacitance value and a second capacitance value associated with the MOS device such that a second signal present at the gate of the MOS device will be an attenuated version of the first signal. An amount of attenuation of the first signal is a function of the ratio of the first and second capacitance values. | 11-05-2009 |
| 20110233632 | SEMICONDUCTOR SEAL-RING STRUCTURE AND THE MANUFACTURING METHOD THEREOF - A seal-ring structure includes a substrate, a source/drain layer, a first dielectric layer, a first lower metal layer, a gate layer and a second lower metal layer. The source/drain layer is disposed within the substrate. The first dielectric layer is disposed over the substrate. The first lower metal layer is disposed over the first dielectric layer and coupled to the source/drain layer via a first contact. The gate layer is disposed within the first dielectric layer. The second lower metal layer is disposed over the first dielectric layer and coupled to the gate layer via a second contact. | 09-29-2011 |
| 20090108313 | REDUCING SHORT CHANNEL EFFECTS IN TRANSISTORS - Microelectronic structures and associated methods for reducing short channel effects in transistors are generally described. In one example, an apparatus includes a semiconductor channel, one or more transistor gates coupled with the semiconductor channel, a spacer film coupled to the one or more transistor gates, and a semiconductor material epitaxially grown (epi-growth) on the semiconductor channel wherein the epi-growth is coupled to the to the spacer film to reduce short channel effects of the one or more transistor gates by effectively increasing the transistor gate length. | 04-30-2009 |
| 20100295110 | DEVICE AND MANUFACTURING METHOD THEREOF - A device manufacturing method includes forming a first insulation film on a semiconductor substrate. A first mask is formed on the first insulation film to extend in a first direction and have a linear pattern. The first insulation film is etched using the first mask as mask to process the insulation film into a linear body. A second mask is formed on the linear body to extend in a second direction different from the first direction and have a linear pattern. The linear body is etched using the second mask as mask to process the linear body into a pillar element. A first conductive film is formed to cover the pillar body. The first conductive film is etched to form a first electrode of the first conductive film on side surfaces of the pillar body. | 11-25-2010 |
| 20110049598 | MANUFACTURING METHOD OF FLEXIBLE SEMICONDUCTOR DEVICE AND FLEXIBLE SEMICONDUCTOR DEVICE - A layered film of a three-layer clad foil formed with a first metal layer | 03-03-2011 |
| 20110248326 | STRUCTURE AND METHOD TO INTEGRATE EMBEDDED DRAM WITH FINFET - A transistor includes a first fin structure and at least a second fin structure formed on a substrate. A deep trench area is formed between the first and second fin structures. The deep trench area extends through an insulator layer of the substrate and a semiconductor layer of the substrate. A high-k metal gate is formed within the deep trench area. A polysilicon layer is formed within the deep trench area adjacent to the metal layer. The polysilicon layer and the high-k metal layer are recessed below a top surface of the insulator layer. A poly strap in the deep trench area is formed on top of the high-k metal gate and the polysilicon material. The poly strap is dimensioned to be below a top surface of the first and second fin structures. The first fin structure and the second fin structure are electrically coupled to the poly strap. | 10-13-2011 |
| 20090001437 | Integrated Circuit Devices Including Recessed Conductive Layers and Related Methods - An integrated circuit device may include a first insulating layer on a substrate with an opening through the first insulating layer. A conductive layer may be on the first insulating layer with the first insulating layer between the conductive layer and the substrate and with the conductive layer set back from the opening. A second insulating layer may be on the conductive layer with the conductive layer between the first and second insulating layers. The second insulating layer may be set back from the opening, and a sidewall of the conductive layer adjacent the opening may be recessed relative to a sidewall of the second insulating layer adjacent the opening. An insulating spacer on portions of the first insulating layer may surround the opening, and the insulating spacer may be on the sidewall of the second insulating layer adjacent the opening so that the insulating spacer is between the sidewall of the second conductive layer and the opening. A conductive contact may be in the opening through the first insulating layer and on portions of the insulating spacer so that the insulating spacer is between the conductive contact and the conductive layer. Related methods are also discussed. | 01-01-2009 |
| 20100320520 | DIELECTRIC, CAPACITOR USING DIELECTRIC, SEMICONDUCTOR DEVICE USING DIELECTRIC, AND MANUFACTURING METHOD OF DIELECTRIC - To make it possible to significantly suppress the leakage current in a semiconductor device having a capacitor structure using a dielectric film. There is provided a composite oxide dielectric which is mainly composed of Zr, Al and O, and which has a composition ratio of Zr and Al in a range of (1−x):x where 0.01≦x≦0.15, and has a crystal structure. When the dielectric is set to have the Al composition in the above described range and is crystallized, the relative dielectric constant of the dielectric can be significantly increased. When the dielectric is used as a dielectric film of a capacitor of a semiconductor device, the leakage current of the capacitor can be significantly reduced. | 12-23-2010 |
| 20080197394 | METHODS OF MANUFACTURING SEMICONDUCTOR STRUCTURES - A method of manufacturing semiconductor structures is disclosed. In one embodiment, a first mask is provided above a substrate. The first mask includes first mask lines extending along a first axis. A second mask is provided above the first mask. The second mask includes second mask lines extending along a second axis that intersects the first axis. At least one of the first and second masks is formed by a pitch fragmentation method. Structures may be formed in the substrate, wherein the first and the second mask are effective as a combined mask. The structures may be equally spaced at a pitch in the range of a minimum lithographic feature size for repetitive line structures. | 08-21-2008 |
| 20100117131 | Transistor for Preventing or Reducing Short Channel Effect and Method for Manufacturing the Same - A transistor for preventing or reducing short channel effect includes a substrate; a gate stack disposed over the substrate; a first junction region disposed on the substrate at a first side surface of the gate stack, said first junction layer being formed of an epitaxial layer; a trench formed within the substrate at a second side surface of the gate stack; and a second junction region disposed below the trench, said second junction layer being lower than the first junction region. | 05-13-2010 |
| 20120037972 | SEMICONDUCTOR DEVICE - It is an object to give excellent data retention characteristics to a semiconductor device in which stored data is judged in accordance with the potential of a gate of a specified transistor, by achieving both reduction in variation of the threshold voltage of the transistor and data retention for a long time. Charge is held (data is stored) in a node electrically connected only to a source or a drain of a transistor whose channel region is formed using an oxide semiconductor. There may be a plurality of transistors whose sources or drains are electrically connected to the node. The oxide semiconductor has a wider band gap and a lower intrinsic carrier density than silicon. By using such an oxide semiconductor for the channel region of the transistor, the transistor with an extremely low off-state current (leakage current) can be realized. | 02-16-2012 |
| 20110006353 | DRAM DEVICES - A DRAM device includes a plug on a substrate, a conductive plate electrically connected to the plug and overlapping the substrate, at least one capacitor on the substrate and spaced apart from the plug, and at least one word line under the conductive plate and spaced apart from the conductive plate. The DRAM device further includes at least one first conductive pad under the conductive plate, the at least one first conductive pad being spaced apart from the conductive plate in a first state and being electrically connected to the conductive plate in a second state, the at least one first conductive pad being disposed between the plug and an adjacent word line of the at least one word line, and the at least one first conductive pad being electrically connected to a respective capacitor of the at least one capacitor. | 01-13-2011 |
| 20110316061 | STRUCTURE AND METHOD TO CONTROL BOTTOM CORNER THRESHOLD IN AN SOI DEVICE - Semiconductor structures and methods to control bottom corner threshold in a silicon-on-insulator (SOI) device. A method includes doping a corner region of a semiconductor-on-insulator (SOI) island. The doping includes tailoring a localized doping of the corner region to reduce capacitive coupling of the SOI island with an adjacent structure. | 12-29-2011 |
| 20120043598 | POWER FET WITH A RESONANT TRANSISTOR GATE - A semiconductor FET provides a resonant gate and source and drain electrodes, wherein the resonant gate is electromagnetically resonant at one or more predetermined frequencies. | 02-23-2012 |
| 20110156117 | SEMICONDUCTOR DEVICE - An object of the present invention is to provide a semiconductor device having a novel structure in which in a data storing time, stored data can be stored even when power is not supplied, and there is no limitation on the number of writing. A semiconductor device includes a first transistor including a first source electrode and a first drain electrode; a first channel formation region for which an oxide semiconductor material is used and to which the first source electrode and the first drain electrode are electrically connected; a first gate insulating layer over the first channel formation region; and a first gate electrode over the first gate insulating layer. One of the first source electrode and the first drain electrode of the first transistor and one electrode of a capacitor are electrically connected to each other. | 06-30-2011 |
| 20120056257 | Non-Volatile Memory System with Modified Memory Cells - A method and system in which an embedded memory is fabricated in accordance with a conventional logic process includes one or more non-volatile memory cells, each having an access transistor and a capacitor, which share a common floating gate electrode. The coupling capacitor is provided with a dielectric layer having a thickness greater than the dielectric layer of the access transistor. Regions under the capacitor are implanted with a high dose implant to form an electrically shorted doped area in the channel region of the capacitor. The high dose implant improves the coupling ratio of the capacitor and enhances the uniformity of the capacitor's oxide layer. | 03-08-2012 |
| 20120119277 | MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A memory device includes a plurality of isolations and trench fillers arranged in an alternating manner in a direction, a plurality of mesa structures between the isolations and trench fillers, and a plurality of word lines each overlying a side surface of the respective mesa. In one embodiment of the present invention, the width measured in the direction of the trench filler is smaller than that of the isolation, each mesa structure includes at least one paired source/drain regions and at least one channel base region corresponding to the paired source/drain regions, and each of the word lines is on a side surface of the mesa structure, adjacent the respective isolation, and is arranged adjacent the channel base region. | 05-17-2012 |
| 20120119276 | MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A memory device includes a mesa structure and a word line. The mesa structure, having two opposite side surfaces, includes at least one pair of source/drain regions and at least one channel base region corresponding to the pair of source/drain regions formed therein. The word line includes two linear sections and at least one interconnecting portion. Each linear section extends on the respective side surface of the mesa structure, adjacent to the channel base region. The at least one interconnecting portion penetrates through the mesa structure, connecting the two linear sections. | 05-17-2012 |
| 20100181606 | Semiconductor Device - Provided is a semiconductor device having a high switching speed. A semiconductor device ( | 07-22-2010 |
| 20100314675 | Power Semiconductor Device and Method for Manufacturing the Same - Disclosed are a power semiconductor device and a method for manufacturing the same. The power semiconductor device has a PIP capacitor and an LDMOS transistor, the LDMOS transistor having second and third gate electrodes separate from a first gate electrode, which may be formed in the process of forming the upper electrode of the PIP capacitor, so it is possible to realize an LDMOS having a higher breakdown voltage and lower Ron and Rsp without additional processing. A drain voltage, which may be different from a voltage applied to the first gate electrode, may be applied to the third gate electrode, so it is possible to realize an LDMOS having a high breakdown voltage and low Ron and Rsp. | 12-16-2010 |
| 20080296649 | SEMICONDUCTOR DEVICE EMPLOYING BURIED INSULATING LAYER AND METHOD OF FABRICATING THE SAME - A semiconductor device employs an asymmetrical buried insulating layer, and a method of fabricating the same. The semiconductor device includes a lower semiconductor substrate. An upper silicon pattern is located on the lower semiconductor substrate. The upper silicon pattern includes a channel region, and a source region and a drain region spaced apart from each other by the channel region. A gate electrode is electrically insulated from the upper silicon pattern and intersects over the channel region. A bit line and a cell capacitor are electrically connected to the source region and the drain region, respectively. A buried insulating layer is interposed between the drain region and the lower semiconductor substrate. The buried insulating layer has an extension portion partially interposed between the channel region and the lower semiconductor substrate. | 12-04-2008 |
| 20080296648 | FIN MEMORY STRUCTURE AND METHOD FOR FABRICATION THEREOF - A semiconductor fin memory structure and a method for fabricating the semiconductor fin memory structure include a semiconductor fin-channel within a finFET structure that is contiguous with and thinner than a conductor fin-capacitor node within a fin-capacitor structure that is integrated with the finFET structure. A single semiconductor layer may be appropriately processed to provide the semiconductor fin-channel within the finFET structure that is contiguous with and thinner than the conductor fin-capacitor node within the fin-capacitor structure. | 12-04-2008 |
| 20120299074 | SEMICONDUCTOR DEVICE - A semiconductor device in which light leakage due to misalignment is prevented even when a black matrix layer is not expanded to a designed value or more is provided. In a semiconductor device including a dual-gate thin film transistor in which a semiconductor layer is sandwiched between a bottom gate electrode and a top gate electrode, the top gate electrode is formed of a first black matrix layer, and the top gate electrode overlaps with the semiconductor layer. | 11-29-2012 |
| 20100230734 | SEMICONDUCTOR DEVICE AND ARRANGEMENT METHOD OF COMPENSATION CAPACITOR OF SEMICONDUCTOR DEVICE - A semiconductor device comprises a circuit cell and a basic end cell. The circuit cell includes a plurality of elements aligned in a first direction, and the basic end cell is arranged adjacent to the circuit cell in the first direction and has a compensation capacitor capable of being connected to a supply voltage of the circuit cell. In the semiconductor device, a diffusion layer forming the compensation capacitor extends along the first direction in a predetermined region of the circuit cell. | 09-16-2010 |
| 20120086063 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate having a memory cell region and a peripheral circuit region; a bit line extending over the memory cell region and the peripheral circuit region, the bit line including a first portion in the peripheral circuit region; and a sense amplifier in the peripheral circuit region. The sense amplifier includes a transistor having a gate electrode which includes the first portion of the bit line. | 04-12-2012 |
| 20120086062 | SWITCHING POWER SUPPLY DEVICE AND A SEMICONDUCTOR INTEGRATED CIRCUIT - In a switching power source which controls a current which flows in an inductor through a switching element which performs a switching operation in response to a PWM signal, and forms an output voltage by a capacitor which is provided in series in the inductor, a booster circuit which is constituted of a bootstrap capacity and a MOSFET is provided between an output node of the switching element and a predetermined voltage terminal. The boosted voltage is used as an operational voltage of a driving circuit of the switching element, another source/drain region and a substrate gate are connected with each other such that when the MOSFET is made to assume an OFF state, and a junction diode between one source/drain region and the substrate gate is inversely directed with respect to the boosted voltage which is formed by the bootstrap capacity. | 04-12-2012 |
| 20080197395 | Semiconductor device - In order to effectively miniaturize elements of a semiconductor device while improving the characteristics of each semiconductor element on a single chip of a silicon substrate or without impairing the characteristics, at least three different silicon surface directions are applied to the elements. Accordingly, at least the characteristics required for each element, on which the surface directions have influence, can be determined as the best characteristics. | 08-21-2008 |
| 20130009227 | SEMICONDUCTOR DEVICE WITH A DYNAMIC GATE-DRAIN CAPACITANCE - A semiconductor device with a dynamic gate drain capacitance. One embodiment provides a semiconductor device. The device includes a semiconductor substrate, a field effect transistor structure including a source region, a first body region, a drain region, a gate electrode structure and a gate insulating layer. The gate insulating layer is arranged between the gate electrode structure and the body region. The gate electrode structure and the drain region partially form a capacitor structure including a gate-drain capacitance configured to dynamically change with varying reverse voltages applied between the source and drain regions. The gate-drain capacitance includes at least one local maximum at a given threshold or a plateau-like course at given reverse voltage. | 01-10-2013 |
| 20130020623 | STRUCTURE AND METHOD FOR SINGLE GATE NON-VOLATILE MEMORY DEVICE - The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate having a periphery region and a memory region; a field effect transistor disposed in the periphery region and having silicide features; and a single floating gate non-volatile memory device disposed in the memory region, free of silicide and having a first gate electrode and a second gate electrode laterally spaced from each other. | 01-24-2013 |
