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With ferroelectric material layer

Subclass of:

257 - Active solid-state devices (e.g., transistors, solid-state diodes)

257213000 - FIELD EFFECT DEVICE

257288000 - Having insulated electrode (e.g., MOSFET, MOS diode)

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DocumentTitleDate
20090194801 FERROELECTRIC CAPACITOR MANUFACTURING PROCESS - A method of manufacturing a semiconductor device. The method comprises forming conductive and ferroelectric material layers on a semiconductor substrate. The material layers are patterned to form electrodes and a ferroelectric layer of a ferroelectric capacitor, wherein a conductive residue is generated on sidewalls of the ferroelectric capacitor as a by-product of the patterning. The method also comprises removing the conductive residue using a physical plasma etch clean-up process that includes maintaining a substrate temperature that is greater than about 60° C.08-06-2009
20120168837Ferroelectric Memory Electrical Contact - A ferroelectric apparatus includes a circuit having a first capacitor electrically coupled to a plate line via a top terminal connection of the first ferroelectric capacitor and to a storage node via a bottom terminal connection of the first ferroelectric capacitor. The circuit also includes a second ferroelectric capacitor electrically coupled to a second plate line via a second bottom terminal connection of the second ferroelectric capacitor and to the storage node via a second top terminal connection of the second ferroelectric capacitor.07-05-2012
20080258195SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A ferroelectric capacitor is formed above a semiconductor substrate (10-23-2008
20080258194FLIP FERAM CELL AND METHOD TO FORM SAME - A method of forming an integrated ferroelectric/CMOS structure which effectively separates incompatible high temperature deposition and annealing processes is provided. The method of the present invention includes separately forming a CMOS structure and a ferroelectric delivery wafer. These separate structures are then brought into contact with each and the ferroelectric film of the delivery wafer is bonded to the upper conductive electrode layer of the CMOS structure by using a low temperature anneal step. A portion of the delivery wafer is then removed providing an integrated FE/CMOS structure wherein the ferroelectric capacitor is formed on top of the CMOS structure. The capacitor is in contact with the transistor of the CMOS structure through all the wiring levels of the CMOS structure.10-23-2008
20080258193FERROELECTRIC MEMORY AND METHOD OF MANUFACTURING THE SAME - A ferroelectric memory that stores information by using a hysteresis characteristic of a ferroelectric, has a semiconductor substrate; a lower electrode formed above said semiconductor substrate; a ferroelectric film formed on said lower electrode; and an upper electrode formed on said ferroelectric film, wherein said upper electrode includes an AO10-23-2008
20080258192SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - This disclosure concerns a semiconductor device comprising an insulating film provided on a semiconductor substrate; a lower contact formed in the insulating film; a ferroelectric capacitor including a first lower electrode provided on the lower contact and connected to the lower contact, a second lower electrode provided on the first lower electrode and made of SRO (Strontium Ruthenium Oxide), a ferroelectric film including crystals, and an upper electrode provided on the ferroelectric film, grain diameters of the crystals being set to 30 nm to 150 nm by forming the ferroelectric film on the second lower electrode; and a wiring connected to the upper electrode.10-23-2008
20110193148MAGNET-ASSISTED TRANSISTOR DEVICES - A transistor device includes a magnetic field source adapted to deflect a flow of free electron carriers within a channel of the device, between a source region and a drain region thereof. According to preferred configurations, the magnetic field source includes a magnetic material layer extending over a side of the channel that is opposite a gate electrode of the transistor device.08-11-2011
20130082314LOW RESISTANCE STACKED ANNULAR CONTACT - An integrated circuit contains lower components in the substrate, a PMD layer, upper components over the PMD layer, lower contacts in the PMD layer connecting some upper components to some lower components, an ILD layer over the upper components, metal interconnect lines over the ILD layer, and upper contacts connecting some upper components to some metal interconnect lines, and also includes annular stacked contacts of lower annular contacts aligned with upper annular contacts. The lower contacts and upper contacts each have a metal liner and a contact metal on the liner. The lower annular contacts have at least one ring of liner metal and contact metal surrounding a pillar of PMD material, and the upper contacts have at least one ring of liner metal and contact metal surrounding a pillar of ILD material. The annular stacked contacts connect the metal interconnects to the lower components.04-04-2013
20130037872METHOD FOR FABRICATING A DAMASCENE SELF-ALIGNED FERROELECTRIC RANDOM ACCESS MEMORY (F-RAM) HAVING A FERROELECTRIC CAPACITOR ALIGNED WITH A THREE DIMENSIONAL TRANSISTOR STRUCTURE - Disclosed is a non-volatile, ferroelectric random access memory (F-RAM) device and a method for fabricating a damascene self-aligned F-RAM that allows for the formation of a ferroelectric capacitor with separated PZT layers aligned with a preexisting, three dimensional (3-D) transistor structure.02-14-2013
20130037871INTEGRATED CIRCUIT DEVICE AND METHOD FOR MANUFACTURING SAME - An integrated circuit device includes a plurality of fins on an upper surface of a semiconductor substrate and extending in a first direction, a device isolation insulating film placed between the fins, a gate electrode extending in a second direction crossing the first direction on the insulating film; and an insulating film insulating the fin from the gate electrode. In a first region where a plurality of the fins are consecutively arranged, an upper surface of the device isolation insulating film is located at a first position below an upper end of the fin. In a second region located in the second direction as viewed from the first region, the upper surface of the device isolation insulating film is located at a second position above the upper end of the fin. In the second region, the device isolation insulating film covers entirely a side surface of the fin.02-14-2013
20100163944SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREFOR - A semiconductor memory device includes a switching transistor provided on a semiconductor substrate; an interlayer dielectric film on the switching transistor; a contact plug in the interlayer dielectric film; a ferroelectric capacitor above the contact plug and the interlayer dielectric film, the ferroelectric capacitor comprising a lower electrode, a ferroelectric film and an upper electrode; a diffusion layer in the semiconductor substrate, the diffusion layer electrically connecting the contact plug to the switching transistor; a hydrogen barrier film on a side surface of the ferroelectric capacitor; and an interconnection comprising a TiN film or a TiAl07-01-2010
20100117128SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor memory device has a semiconductor substrate, an impurity diffusion layer that is formed at a surface portion of the semiconductor substrate, an interlayer insulating film that is formed on the semiconductor substrate, a contact plug that penetrates the interlayer insulating film, has a top surface formed higher than a top surface of the interlayer insulating film, a region having a convex shape formed higher than the top surface of the interlayer insulating film, and contacts the impurity diffusion layer, a lower capacitor electrode film that is formed on the contact plug and a predetermined region of the interlayer insulating film, a ferroelectric film that is formed on the lower capacitor electrode film, and an upper capacitor electrode film that is formed on the ferroelectric film.05-13-2010
20100072530MAGNETIC RANDOM ACCESS MEMORTY - A magnetic random access memory of an aspect of the present invention including a magnetoresistive effect element having a fixed layer whose magnetization direction is fixed, a recording layer whose magnetization direction is reversible, and a non-magnetic layer provided between the fixed and recording layers, wherein the magnetization directions of the fixed and recording layers are in a parallel state or in an anti-parallel state depending on a direction of a current flowing between the fixed and recording layers, a first transistor having a gate and a first current path having one end connected to the fixed layer, a second transistor having a gate and a second current path having one end connected to the recording layer, a first bit line to which other end of the first current path is connected, and a second bit line to which other end of the second current path is connected.03-25-2010
20100072527SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor memory device includes: a transistor on a semiconductor substrate; an interlayer dielectric film covering the transistor; a ferroelectric capacitor comprising a first upper electrode, a ferroelectric film, and a lower electrode on the interlayer dielectric film; a contact plug which is in the interlayer dielectric film and electrically connects the lower electrode to the transistor; a second upper electrode on the first upper electrode, a side surface of the second upper electrode being formed in a forward tapered shape; and an interconnection electrically connected via the second upper electrode to the first upper electrode.03-25-2010
20100072526SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a semiconductor substrate; a ferroelectric capacitor comprising an upper electrode, a ferroelectric film, and a lower electrode above the semiconductor substrate; and an upper interlayer dielectric film surrounding a periphery of the ferroelectric capacitor, wherein a gap is provided between the ferroelectric capacitor and the upper interlayer dielectric film.03-25-2010
20100072525SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to a method for manufacturing a semiconductor memory device of the present invention, a capacitor lower electrode film is left on the wiring layer located above a dummy transistor. In this manner, when processing of the capacitors is performed by removing a capacitor upper electrode film and a ferroelectric film, removal of the wiring layer can be prevented, and the connection between the diffusion layer of a select transistor and a bit line can be secured.03-25-2010
20100072529STACK HAVING HEUSLER ALLOY, MAGNETORESISTIVE ELEMENT AND SPIN TRANSISTOR USING THE STACK, AND METHOD OF MANUFACTURING THE SAME - A stack includes a crystalline MgO layer, crystalline Heusler alloy layer, and amorphous Heusler alloy layer. The crystalline Heusler alloy layer is provided on the MgO layer. The amorphous Heusler alloy layer is provided on the crystalline Heusler alloy layer.03-25-2010
20100072528SPIN TRANSISTOR, INTEGRATED CIRCUIT, AND MAGNETIC MEMORY - A spin transistor includes a first ferromagnetic layer, a second ferromagnetic layer, a semiconductor layer between the first and second ferromagnetic layers, and a gate electrode on or above a surface of the semiconductor layer, the surface being between the first and second ferromagnetic layers. The first ferromagnetic layer comprises a ferromagnet which has a first minority spin band located at a high energy side and a second minority spin band located at a low energy side, and has a Fermi level in an area of the high energy side higher than a middle of a gap between the first and second minority spin bands.03-25-2010
20100072524Magnetic Devices Having Oxide Antiferromagnetic Layer Next To Free Ferromagnetic Layer - Magnetic multilayer structures, such as magnetic or magnetoresistive tunnel junctions (MTJs) and spin valves, having a magnetic biasing layer formed next to and magnetically coupled to the free ferromagnetic layer to achieve a desired stability against fluctuations caused by, e.g., thermal fluctuations and astray fields. Stable MTJ cells with low aspect ratios can be fabricated using CMOS processing for, e.g., high-density MRAM memory devices and other devices, using the magnetic biasing layer. Such multilayer structures can be programmed using spin transfer induced switching by driving a write current perpendicular to the layers to switch the magnetization of the free ferromagnetic layer.03-25-2010
20100032738MAGNETIC MEMORY WITH STRAIN-ASSISTED EXCHANGE COUPLING SWITCH - A magnetic tunnel junction cell having a free layer and first pinned layer with perpendicular anisotropy, the cell including a coupling layer between the free layer and a second pinned layer, the coupling layer comprising a phase change material switchable from an antiferromagnetic state to a ferromagnetic state. In some embodiments, at least one actuator electrode proximate the coupling layer transfers a strain from the electrode to the coupling layer to switch the coupling layer from the antiferromagnetic state to the ferromagnetic state. Memory devices and methods are also described.02-11-2010
20090121267Spin field effect transistor using half metal and method of manufacturing the same - A spin field effect transistor may include at least one gate electrode, a channel layer, a first stack and a second stack separate from each other on a substrate, wherein the channel layer is formed of a half metal. The half metal may be at least one material selected from the group consisting of chrome oxide (CrO05-14-2009
20090121266METHODS AND STRUCTURES FOR EXCHANGE-COUPLED MAGNETIC MULTI-LAYER STRUCTURE WITH IMPROVED OPERATING TEMPERATURE BEHAVIOR - Exchange-coupled magnetic multilayer structures for use with toggle MRAM devices and the like include a tunnel barrier layer (05-14-2009
20100102369FERROELECTRIC MEMORY WITH MAGNETOELECTRIC ELEMENT - A ferroelectric memory cell that has a magnetoelectric element between a first electrode and a second electrode, the magnetoelectric element comprising a ferromagnetic material layer and a multiferroic material layer with an interface therebetween. The magnetization orientation of the ferromagnetic material layer and the multiferroic material layer may be in-plane or out-of-plane. FeRAM memory devices are also provided.04-29-2010
20100109061SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD FOR SEMICONDUCTOR MEMORY DEVICE - A channel layer is deposited on a first impurity layer, a second impurity layer is deposited on the channel layer, a gate electrode is placed to surround a circumference of the channel layer with a gate insulating film interposed therebetween, a spin-injection magnetization-reversal element is deposited on the second impurity layer, a bit line is placed on the spin-injection magnetization-reversal element, and a word line is placed on the bit line to be electrically connected to the gate electrode.05-06-2010
20100327333SPIN TRANSPORT DEVICE - A spin transport device which comprises a channel, first and second insulating layers, a magnetization fixed layer, a magnetization free layer, first and second wirings, and satisfies at least one of following conditions A and B, Condition A: The first wiring includes a vertical portion which extends in a thickness direction of the magnetization fixed layer on the magnetization fixed layer, and a horizontal portion which extends from the vertical portion that is apart from the magnetization fixed layer side in a direction crossing the thickness direction of the magnetization fixed layer, and Condition B: The second wiring includes a vertical portion which extends in a thickness direction of the magnetization free layer on the magnetization free layer, and a horizontal portion which extends from the vertical portion that is apart from the magnetization free layer side in a direction crossing the thickness direction of the magnetization free layer.12-30-2010
20100001325SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes an insulating film provided over a semiconductor substrate, a conductive plug buried in the insulating film, an underlying conductive film which is provided on the conductive plug and on the insulating film and which has a flat upper surface, and a ferroelectric capacitor provided on the underlying conductive film. At least in a region on the conductive plug, the concentration of nitrogen in the underlying conductive film gradually decreases from the upper surface to the inside.01-07-2010
20100001324SEMICONDUCTOR DEVICE WITH A SUPERPARAELECTRIC GATE INSULATOR - A semiconductor device includes a channel region 01-07-2010
20100133597SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor memory device including a ferroelectric capacitor, the ferroelectric capacitor includes a lower electrode having a plurality of protrusions; a ferroelectric film on the lower electrode, the ferroelectric film having a plurality of protrusions engaging with the protrusions of the lower electrode; and an upper electrode on the ferroelectric film, the upper electrode having a plurality of protrusions engaging with the protrusions of the lower electrode.06-03-2010
20090302363SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - Provided is a semiconductor device that includes: a base insulating film 12-10-2009
20090302362SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A lower electrode film, a ferroelectric film, and an upper electrode film are formed on an insulation film covering a transistor formed on a semiconductor substrate. Furthermore, a Pt film is formed as a cap layer on the upper electrode film. Then, a hard mask (a TiN film and an SiO12-10-2009
20130056812SEMICONDUCTOR MEMORY DEVICES INCLUDING VERTICAL TRANSISTOR STRUCTURES - A semiconductor memory device may include a common source region on a substrate, an active pattern between the substrate and the common source region, a gate pattern facing a sidewall of the active pattern, a gate dielectric pattern between the gate pattern and the active pattern, a variable resistance pattern between the common source region and the active pattern, and an interconnection line.03-07-2013
20130056811Hydrogen-Blocking Film for Ferroelectric Capacitors - An ammonia-free method of depositing silicon nitride by way of plasma-enhanced chemical vapor deposition (PECVD). Source gases of silane (SiH03-07-2013
20130056810SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor device includes, a semiconductor substrate including a plurality of fins formed in an upper surface of the semiconductor substrate in a first region to extend in a first direction, a first gate electrode extending in a second direction intersecting the first direction to straddle the fins, a first gate insulating film provided between the first gate electrode and the fins, a second gate electrode provided on the semiconductor substrate in the second region; and a second gate insulating film provided between the semiconductor substrate and the second gate electrode. A layer structure of the first gate electrode is different from a layer structure of the second gate electrode.03-07-2013
20090294817FERROELECTRIC MEMORY DEVICE - A ferroelectric memory device comprising a dielectric layer comprising a mixture and/or a compound that comprises a ferroelectric organic polymer and an oxidiser and/or deioniser, and a pair of electrodes configured to apply an electric field to the dielectric layer. Also a method of fabricating a memory device.12-03-2009
20100084696FERROELECTRIC MEMORY DEVICE - A ferroelectric memory device having plural memory cells, each composed of a memory cell transistor and a memory cell capacitor including a lower electrode that is independent for each memory cell capacitor, a ferroelectric layer formed on the lower electrode, and an upper electrode layer formed on the ferroelectric layer. A plurality of the upper electrode layers are connected together and constitute a plate electrode, and the width of the upper electrode is narrower than the width of the ferroelectric layer. Accordingly, by making the width of the upper electrode narrower than the width of the ferroelectric layer, it is possible to prevent current leakage between the upper electrode and the lower electrode, which reduces the placement interval of the memory cell capacitors without causing current leakage between the upper electrode and the lower electrode, and results in a smaller memory cell size.04-08-2010
20090267123SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor substrate; a plurality of transistors on the semiconductor substrate, each of the transistors has a source and drain region; an interlayer insulating film on the semiconductor substrate and the plurality of transistors; and at least three capacitors on the interlayer insulation film, each of them has a top electrode, a bottom electrode and an insulating film interposed therebetween; wherein the 1st and 2nd capacitors have an shared electrode, with the top electrodes of the 1st and 2nd capacitors, which has a 1st longer direction, the 2nd and 3rd capacitors have an shared electrode, with the bottom electrodes of the 2nd and 3rd capacitors, which has a 2nd longer direction different from the 1st direction.10-29-2009
20090267122Semiconductor device and method of manufacturing the semiconductor device - A semiconductor device has a substrate, an insulator, an yttrium oxide film, a ferroelectric film (STN film), and an upper electrode.10-29-2009
20130062674SPIN TRANSFER TORQUE RANDOM ACCESS MEMORY - A spin transfer torque random access memory includes a substance unit, a source line unit, an insulation unit, a transistor unit, a MTJ unit, and a bit line unit. The substance unit includes a substance layer. The source line unit includes a plurality of source lines formed inside the substance layer. The transistor unit includes a plurality of transistors respectively disposed on the source lines. Each transistor includes a source region formed on each corresponding source line, a drain region formed above the source region, a channel region formed between the source region and the drain region, and a surrounding gate region surrounding the source region, the drain region, and the channel region. The MTJ unit includes a plurality of MTJ structures respectively disposed on the transistors. The bit line unit includes at least one bit line disposed on the MTJ unit.03-14-2013
20110012180METHOD OF FORMING A CMOS STRUCTURE HAVING GATE INSULATION FILMS OF DIFFERENT THICKNESSES - The semiconductor integrated circuit device employs on the same silicon substrate a plurality of kinds of MOS transistors with different magnitudes of tunnel current flowing either between the source and gate or between the drain and gate thereof. These MOS transistors include tunnel-current increased MOS transistors at least one of which is for use in constituting a main circuit of the device. The plurality of kinds of MOS transistors also include tunnel-current reduced or depleted MOS transistors at least one of which is for use with a control circuit. This control circuit is inserted between the main circuit and at least one of the two power supply units.01-20-2011
20110012179MAGNETORESISTIVE RANDOM ACCESS MEMORY DEVICE - An aspect of the present disclosure, there is provided a magnetoresistive random access memory device, including, an active area formed on a semiconductor substrate in a first direction, a magnetoresistive effect element formed on the active area and storing data by a change in resistance value, a gate electrode of a cell transistor formed on each side of the magnetoresistive effect element on the active area in a second direction, a bit line contact formed on the active area and arranged alternately with the magnetoresistive effect element, a first bit line connected to the magnetoresistive effect, and a second bit line connected to the bit line contact.01-20-2011
20100123175SEMICONDUCTOR DEVICE - According to an aspect of the present invention, there is provided a semiconductor device, including: a semiconductor substrate; a transistor that is formed on the semiconductor substrate; an interlayer insulating film that is formed on the semiconductor substrate so as to cover the transistor and that has a through hole formed thereinside so as to reach the transistor; a plug lower-electrode that is formed in the through hole and that is connected to the transistor; a ferroelectric film that is formed on the plug lower-electrode; and an upper-electrode that is formed on the ferroelectric film.05-20-2010
20090236646Field-effect transistor with spin-dependent transmission characteristics and non-volatile memory using the same - When a gate voltage V09-24-2009
20090008689Spin Transistor Using Ferromagnet - A spin transistor comprises a semiconductor substrate part having a lower cladding layer, a channel layer and an upper cladding layer sequentially stacked therein, a ferromagnetic source and drain on the substrate part, and a gate on the substrate part to control spins of electrons passing through the channel layer. The lower cladding layer comprises a first lower cladding layer and a second lower cladding layer having a higher band gap than that of the first lower cladding layer. The upper cladding layer comprises a first upper cladding layer and a second upper cladding layer having a higher band gap than that of the first upper cladding layer. The source and the drain are buried in an upper surface of the substrate part and extend downwardly to or under the first upper cladding layer.01-08-2009
20090095994SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device comprises a substrate; an insulating layer formed over the substrate; a contact hole formed through the insulating layer; a plurality of first plug electrodes each formed inside the contact hole to the surface of the insulating layer; a capacitor layer formed on the first plug electrode in a first region; and a second plug electrode formed on the first plug electrode in a second region different from the first region. The capacitor layer includes a lower electrode, a ferroelectric film, and an upper electrode stacked in turn. The first plug electrode includes a plug conduction layer formed from the surface of the substrate, and a plug barrier layer formed from above the plug conduction layer up to an upper surface of the insulating layer, the plug barrier layer having a higher etching selection ratio than the lower electrode.04-16-2009
20100171158METHOD OF FORMING FERROMAGNETIC MATERIAL, TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - The present invention provides a method of forming a ferromagnetic material, characterized by including: forming a magnetic element layer 07-08-2010
20120286340CONTROLLING FERROELECTRICITY IN DIELECTRIC FILMS BY PROCESS INDUCED UNIAXIAL STRAIN - A method of controlling ferroelectric characteristics of integrated circuit device components includes forming a ferroelectrically controllable dielectric layer over a substrate; and forming a stress exerting structure proximate the ferroelectrically controllable dielectric layer such that a substantially uniaxial strain is induced in the ferroelectrically controllable dielectric layer by the stress exerting structure; wherein the ferroelectrically controllable dielectric layer comprises one or more of: a ferroelectric oxide layer and a normally non-ferroelectric material layer that does not exhibit ferroelectric properties in the absence of an applied stress.11-15-2012
20120286339SEMICONDUCTOR STORAGE DEVICE - A memory includes a semiconductor substrate. Magnetic tunnel junction elements are provided above the semiconductor substrate. Each of the magnetic tunnel junction elements stores data by a change in a resistance state, and the data is rewritable by a current. Cell transistors are provided on the semiconductor substrate. Each of the cell transistors is in a conductive state when the current is applied to the corresponding magnetic tunnel junction element. Gate electrodes are included in the respective cell transistors. Each of the gate electrodes controls the conductive state of the corresponding cell transistor. In active areas, the cell transistors are provided, and the active areas extend in an extending direction of intersecting the gate electrodes at an angle of (90-a tan(⅓)) degrees.11-15-2012
20090206379SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device which can prevent the degradation of contact yield even when subjected to a high-temperature and long-time thermal process, and a manufacturing method thereof are provided. The semiconductor device includes: a first semiconductor circuit formed on a semiconductor substrate; a second semiconductor circuit formed above the first semiconductor circuit; an interlayer insulating film formed between the first semiconductor circuit and the second semiconductor circuit; and a contact plug formed in a state of penetrating the interlayer insulating film, the contact plug including a contact plug body made up of a conductor, and a contact plug coating which is insulating and which covers at least a portion of a side face of the contact plug body in contact with the interlayer insulating film.08-20-2009
20110284938SPIN TRANSISTOR AND INTEGRATED CIRCUIT - A spin transistor according to an embodiment includes: a first magnetic region supplying a first polarized signal polarized in a first magnetization direction in accordance with a first input signal; a second magnetic region supplying a second polarized signal polarized in a second magnetization direction opposite from the first magnetization direction in accordance with a second input signal, the second input signal being different from the first input signal; and a third magnetic region outputting the first polarized signal supplied from the first magnetic region in accordance with a third input signal, and outputting the second polarized signal supplied from the second magnetic region in accordance with a fourth input signal different from the third input signal.11-24-2011
20090315088FERROELECTRIC MEMORY USING MULTIFERROICS - Ferroelectric memory using multiferroics is described. The multiferrroic memory includes a substrate having a source region, a drain region and a channel region separating the source region and the drain region. An electrically insulating layer is adjacent to the source region, drain region and channel region. A data storage cell having a composite multiferroic layer is adjacent to the electrically insulating layer. The electrically insulating layer separated the data storage cell form the channel region. A control gate electrode is adjacent to the data storage cell. The data storage cell separates at least a portion of the control gate electrode from the electrically insulating layer.12-24-2009
20100001326ONE TRANSISTOR DRAM CELL STRUCTURE AND METHOD FOR FORMING - A one-transistor dynamic random access memory (DRAM) cell includes a transistor which has a first source/drain region, a second source/drain region, a body region between the first and second source/drain regions, and a gate over the body region. The first source/drain region includes a Schottky diode junction with the body region and the second source/drain region includes an n-p diode junction with the body region.01-07-2010
20100264475MAGNETIC TUNNEL JUNCTION TRANSISTOR - A magnetic tunnel junction transistor and method of operating the same. In a particular embodiment, the magnetic tunnel junction transistor includes electrically conductive source, drain and gate electrodes. An electrically insulating material having a non-magnetoelectric region and a magnetoelectric region is positioned such that the non-magnetoelectric region is, at least partially, between the source electrode and the drain electrode. The magnetoelectric region of the insulating material, when energized, is configured to change magnetic state of the insulating material. The gate electrode is positioned proximate the magnetoelectric region of the insulating material.10-21-2010
20100102370NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING NON-VOLATILE MEMORY DEVICE - A non-volatile memory device including a ferroelectric capacitor is disclosed. A method of manufacturing a non-volatile memory device including a ferroelectric capacitor is also disclosed. A first electrode is formed on an insulating film provided on a semiconductor substrate. A first ferroelectric film is formed on the first electrode. The first ferroelectric film has a convexo-concave surface portion. A second ferroelectric film is formed on the first ferroelectric film so as to bury the convexo-concave surface portion. The second ferroelectric film has a surface flatter than that of the first ferroelectric film. A second electrode is formed on the second ferroelectric film. A protective film is formed at least on a portion of an upper surface of the second electrode. The protective film serves as a barrier against hydrogen.04-29-2010
20090152606Spin Transistor Using Epitaxial Ferromagnet-Semiconductor Junction - A spin transistor conducive to the miniaturization and large scale integration of devices, because a magnetization direction of a source and a drain is determined by a direction of the epitaxial growth of a ferromagnet. The spin transistor includes a semiconductor substrate having a channel layer formed thereinside; ferromagnetic source and drain epitaxially grown on the semiconductor substrate and magnetized in a longitudinal direction of the channel layer due to magnetocrystalline anisotropy—the source and drain being disposed spaced apart from each other in a channel direction and magnetized in the same direction—; and a gate disposed between the source and the drain to be insulated with the semiconductor substrate and formed on the semiconductor substrate to control the spin of electrons that are passed through the channel layer.06-18-2009
20090309145METHOD AND SYSTEM FOR PATTERNING OF MAGNETIC THIN FLIMS USING GASEOUS TRANSFORMATION - A magnetic thin film includes a magnetic tunnel junction defined by a surrounding region including a fluorinated, non-magnetic, electrically insulating material.12-17-2009
20100078693Semiconductor device and method of manufacturing semiconductor device - The semiconductor device according to the present invention includes a ferroelectric film and an electrode stacked on the ferroelectric film. The electrode has a multilayer structure of an electrode lower layer in contact with the ferroelectric film and an electrode upper layer stacked on the electrode lower layer. The electrode upper layer is made of a conductive material having an etching selection ratio with respect to the materials for the ferroelectric film and the electrode lower layer. The upper surface of the electrode upper layer is planarized.04-01-2010
20110062504SEMICONDUCTOR MEMORY DEVICE INCLUDING FERROELECTRIC CAPACITOR - An aspect of the present disclosure, there is provided semiconductor memory device including a ferroelectric capacitor and a field effect transistor as a memory cell, the ferroelectric capacitor including a lower electrode connected to one of the pair of the impurity diffusion layers, a bit line formed below the lower electrode, wherein each of the memory cells shares the bit line contact with an adjacent memory cell at one side in the first direction to connect to the bit line, and three of the word lines are formed between the bit line contacts in the first direction.03-17-2011
20110062503SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a plurality of transistors on a semiconductor substrate; a first interlayer dielectric film on the transistors; a plurality of ferroelectric capacitors on the first interlayer dielectric film; a first hydrogen barrier film covering an upper surface and a side surface of each of the ferroelectric capacitors; a second interlayer dielectric film above the ferroelectric capacitors, the second interlayer dielectric film being buried to have a void or hole between two adjacent ferroelectric capacitors out of the ferroelectric capacitors; a cover dielectric film covering the second interlayer dielectric film to close an opening of the void or hole; and a second hydrogen barrier film covering the cover dielectric film.03-17-2011
20120193693MAGNETIC RANDOM ACCESS MEMORY AND A METHOD OF FABRICATING THE SAME - An aspect of the present embodiment, there is provided magnetic random access memory device including a semiconductor substrate, a selection transistor on the semiconductor substrate, the selection transistor including a diffusion layer, a contact plug on diffusion layer, an amorphous film on the contact plug, a lower electrode provided on the amorphous film, a first magnetic layer, a nonmagnetic layer, a second magnetic layer, an upper electrode stacked in an order and a sidewall contact film on the contact plug, the sidewall contact film being in contact with a sidewall of the upper electrode.08-02-2012
20100123177SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING SEMICONDUCTOR MEMORY DEVICE - According to an aspect of the present invention, there is provided a semiconductor memory device, including a TC unit series-type FeRAM in which a plurality of memory cells, each of the memory cells comprising a memory transistor and a ferroelectric capacitor connected each other in parallel, are serially connected, including, a first electrode over and electrically connected to one of a source and a drain in the memory transistor, a second electrode opposed to the first electrode over and electrically connected to the other of the source and the drain in the memory transistor, a third electrode on both sidewalls of the second electrode other than an under portion of the second electrode, and a ferroelectric film between the first electrode and the two electrodes, the second electrode and the third electrode, wherein the ferroelectric capacitor comprises the first and the third electrode, and the ferroelectric film.05-20-2010
20090152607FERROELECTRIC STACKED-LAYER STRUCTURE, FIELD EFFECT TRANSISTOR, AND FERROELECTRIC CAPACITOR AND FABRICATION METHODS THEREOF - A ferroelectric stacked-layer structure is fabricated by forming a first polycrystalline ferroelectric film on a polycrystalline or amorphous substrate, and after planarizing a surface of the first ferroelectric film, laminating on the first ferroelectric film a second thin ferroelectric film having the same crystalline structure as the first ferroelectric film. A field effect transistor or a ferroelectric capacitor includes the ferroelectric stacked-layer structure as a gate insulating film or a capacitor film.06-18-2009
20090294818FERROELECTRIC POLYMER - A ferroelectric film comprising polyaminodifluoroborane (PADFB). Also a memory device utilizing the ferroelectric film, a method of fabricating a ferroelectric polymer and a ferroelectric solution.12-03-2009
20090261395Integrated Circuit Including a Ferroelectric Memory Cell and Method of Manufacturing the Same - A method for manufacturing an integrated circuit including a ferroelectric memory cell is disclosed. One embodiment of the method includes: forming a amorphous oxide layer over a carrier, the amorphous layer including: O and any of the group of: Hf, Zr and (Hf,Zr), forming a covering layer on the amorphous layer, and heating the amorphous layer up to a temperature above its crystallization temperature to at least partly alter its crystal state from amorphous to crystalline, resulting in a crystallized oxide layer.10-22-2009
20120292677FERROELECTRIC SEMICONDUCTOR TRANSISTOR DEVICES HAVING GATE MODULATED CONDUCTIVE LAYER - Ferroelectric semiconductor switching devices are provided, including field effect transistor (FET) devices having gate stack structures formed with a ferroelectric layer disposed between a gate contact and a thin conductive layer (“quantum conductive layer”) . The gate contact and ferroelectric layer serve to modulate an effective work function of the thin conductive layer. The thin conductive layer with the modulated work function is coupled to a semiconductor channel layer to modulate current flow through the semiconductor and achieve a steep sub-threshold slope.11-22-2012
20110266600SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor memory device according to embodiments includes a semiconductor substrate and plural switching transistors provided on the semiconductor substrate. In the semiconductor memory device, a contact plug is embedded between adjacent two of the switching transistors, and is insulated from gates of the adjacent two switching transistors. The contact plug is also electrically connected to a source or a drain of each of the adjacent two switching transistors, and an upper surface of the contact plug is at a position higher than an upper surface of the switching transistors. A memory element is provided on the upper surface of the contact plug and stores data. A wiring is provided on the memory element.11-03-2011
20080277706FERROELECTRIC MEMORY DEVICE, FERROELECTRIC MEMORY MANUFACTURING METHOD, AND SEMICONDUCTOR MANUFACTURING METHOD - A ferroelectric memory device manufacturing method includes the steps of forming an interlayer isolating film for covering a transistor formed on a semiconductor substrate; forming a conductive plug in the interlayer insulating film to contact a diffusion region of the transistor formed on the semiconductor substrate; forming a ferroelectric capacitor including a lower electrode, a ferroelectric film and an upper electrode; and forming a compound film including silicon (Si) and a CH group on a surface of the interlayer insulating film and a surface of the conductive plug by depositing a Si compound containing Si atoms and the CH groups; wherein the compound film is formed after forming the conductive plug, and the compound film is formed before forming the lower electrode; and a self-orientation film is formed on a surface of the compound film.11-13-2008
20080277703MAGNETORESISTIVE RANDOM ACCESS MEMORY AND METHOD OF MANUFACTURING THE SAME - A magnetic random access memory includes a single tunnel junction element which includes a first fixed layer, a first recording layer, and a first nonmagnetic layer, a double tunnel junction element which includes a second fixed layer and a third fixed layer, a second recording layer, a second nonmagnetic layer formed between the second fixed layer and the second recording layer, and a third nonmagnetic layer formed between the third fixed layer and the second recording layer, and in which the magnetization directions in the second fixed layer and the second recording layer take one of the parallel state and the antiparallel state in accordance with a direction of an electric current flowing between the second fixed layer and the second recording layer, and a transistor connected to a memory cell having the single tunnel junction element and the double tunnel junction element connected in parallel.11-13-2008
20080283888SPIN TRANSISTOR, PROGRAMMABLE LOGIC CIRCUIT, AND MAGNETIC MEMORY - A spin transistor includes a non-magnetic semiconductor substrate having a channel region, a first area, and a second area. The channel region is between the first and the second areas. The spin transistor also includes a first conductive layer located above the first area and made of a ferromagnetic material magnetized in a first direction; and a second conductive layer located above the second area and made of a ferromagnetic material magnetized in one of the first direction and a second direction that is antiparallel with respect to the first direction. The channel region introduces electron spin between the conductive layers. The spin transistor also includes a gate electrode located between the conductive layers and above the channel region; and a tunnel barrier film located between the non-magnetic semiconductor substrate and at least one of the conductive layers.11-20-2008
20080290385METHOD FOR MANUFACTURING FERROELECTRIC CAPACITOR, AND FERROELECTRIC CAPACITOR - A method for manufacturing a ferroelectric capacitor includes the steps of: forming a base dielectric film on a substrate, and forming a first plug conductive section in the base dielectric film at a predetermined position; forming, on the base dielectric film, a charge storage section formed from a lower electrode, a ferroelectric film and an upper electrode; forming a stopper film from an insulation material that covers the charge storage section; forming a hydrogen barrier film that covers the stopper film; forming an interlayer dielectric film on the base dielectric film including the hydrogen barrier film; forming, in the interlayer dielectric film, a first contact hole that exposes the first plug conductive section; forming a second contact hole that exposes the upper electrode of the charge storage section by successively etching the interlayer dielectric film, the hydrogen barrier film and the stopper film by using a resist pattern as a mask, and then removing the resist pattern by a wet cleaning treatment; forming an adhesion layer from a conductive material having hydrogen barrier property inside the second contact hole in a manner to cover an upper surface of the upper electrode; forming a second plug conductive section inside the first contact hole; and forming a third plug conductive section inside the second contact hole, wherein the stopper film is formed from a material having a lower etching rate for a cleaning liquid used for the wet cleaning treatment to remove the resist pattern than an etching rate of the hydrogen barrier film for the cleaning liquid.11-27-2008
20080290384Microelectronic Device Provided with Transistors Coated with a Piezoelectric Layer - An improved microelectronic device, and method for making such a microelectronic device. The device includes one or plural transistors and piezoelectric mechanisms, with an arrangement capable of applying a variable mechanical strain on transistor channels.11-27-2008
20080303074SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD - A semiconductor device is equipped with a plug conductive layer formed in an interlayer dielectric film on a substrate, and a conductive member provided on the plug conductive layer. The semiconductor device further includes a spacer dielectric film formed on the interlayer dielectric film and having a hole section connecting to the plug conductive layer; and a spacer conductive section embedded in the hole section of the spacer dielectric film, connected to the plug conductive layer and connected to the conducive member, wherein the spacer conductive section is formed from a conductive material having self-orientation characteristic, and a top surface of the spacer dielectric film and a top surface of the spacer conductive section are planarized.12-11-2008
20080265298SEMICONDUCTOR DEVICE - According to an aspect of the present invention, there is provided a semiconductor device including: a transistor including: a source, a drain and a gate; first and second plugs on the source and the drain; a third plug on the gate to have a top face higher than that of the first plug; an interlayer insulating film covering the transistor and the first to the third plugs; a ferroelectric capacitor on the interlayer insulating film, one electrode thereof being connected to the first plug; a barrier film covering surfaces of the ferroelectric capacitor and the interlayer insulating film to prevent a substance affecting the ferroelectric capacitor from entering therethrough; and fourth and fifth plugs disposed on the second and the third plugs and connected thereto through connection holes formed in the barrier film.10-30-2008
20100270601Semiconductor Device Having Reduced Single Bit Fails and a Method of Manufacture Thereof - One aspect of the invention provides a method of manufacturing a FeRAM semiconductor device having reduce single bit fails. This aspect includes forming an electrical contact within a dielectric layer located over a semiconductor substrate and forming a first barrier layer over the dielectric layer and the electrical contact. The first barrier layer is formed by depositing multiple barrier layers and densifying each of the barrier layers after its deposition. This forms a stack of multiple barrier layers of a same elemental composition. The method further includes forming a second barrier layer over the first barrier layer and forming a lower capacitor electrode, a ferroelectric dielectric layer over the lower capacitor, and forming an upper capacitor electrode over the ferroelectric dielectric layer. A device made by this method is also provided herein.10-28-2010
20080258191CAPACITOR DEVICE PROVIDING SUFFICIENT RELIABILITY - A capacitor device includes a dielectric layer configured to have a composition represented as (Ba10-23-2008
20090072287SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD - A semiconductor device includes: a ferroelectric capacitor including a first electrode provided above a substrate, a ferroelectric film provided on the first electrode and a second electrode provided on the ferroelectric film; a hydrogen barrier film that covers a top surface and a side surface of the ferroelectric capacitor; an interlayer dielectric film that covers the ferroelectric capacitor and the substrate; a contact hole that penetrates the interlayer dielectric film and the hydrogen barrier film and exposes the second electrode; a barrier metal that covers a top surface of the second electrode exposed in the contact hole and an inner wall surface of the contact hole and is composed of a conductive material having hydrogen barrier property; and a plug conductive section that is embedded in the contact hole and conductively connects to the barrier metal, wherein the inner wall surface of the contact hole at the hydrogen barrier film includes a concave curved surface facing the interior of the contact hole, and the contact hole at the hydrogen barrier film has an inner diameter that gradually becomes smaller toward the second electrode.03-19-2009
20090127604FERROELECTRIC MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A ferroelectric memory device includes: a substrate; a ferroelectric capacitor forming above the substrate, and having a lower electrode layer, a ferroelectric layer and an upper electrode layer; a first hydrogen barrier layer that covers the ferroelectric capacitor; an interlayer dielectric layer formed above the first hydrogen barrier layer; and a contact section that penetrates the interlayer dielectric layer and the first hydrogen barrier layer and connects to the upper electrode layer, wherein the contact section includes a first barrier layer in contact with the upper electrode layer, a second hydrogen barrier layer formed above the first barrier layer and a plug layer formed above the second hydrogen barrier layer.05-21-2009
20090127603SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor memory device according to an embodiment comprises: a field-effect transistor formed on a substrate; an interlayer insulation film formed on the substrate on which the field-effect transistor is formed; and a ferroelectric capacitor including a lower electrode connected via a plug to one of source/drain regions of the field-effect transistor, and formed on the interlayer insulation film, a ferroelectric film having a perovskite crystal structure used as a basic structure, and an upper electrode, wherein a lattice matching region in which a lattice of the ferroelectric film is matched with a lattice of the lower electrode is formed in a range of a predetermined thickness of the ferroelectric film from the lower electrode.05-21-2009
20090127602SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - This disclosure concerns a memory including transistors provided on a substrate; ferroelectric capacitors provided on the transistors, the ferroelectric capacitors respectively including a ferroelectric film provided between a lower electrode and an upper electrode; and a barrier film covering a first side surface of the ferroelectric capacitor, and blocking passing of hydrogen, wherein adjacent two of the ferroelectric capacitors connected in the lower electrode form one capacitor unit, a plurality of the capacitor units connected in the upper electrode form one capacitor chain, the capacitor units are arranged with a deviation of a half pitch of the capacitor unit in adjacent plurality of capacitor chains, and when D05-21-2009
20090315089ATOMIC LAYER DEPOSITED BARIUM STRONTIUM TITANIUM OXIDE FILMS - Apparatus and methods of forming the apparatus include a dielectric layer containing barium strontium titanium oxide layer, an erbium-doped barium strontium titanium oxide layer, or a combination thereof. Embodiments of methods of fabricating such dielectric layers provide dielectric layers for use in a variety of devices. Embodiments include forming barium strontium titanium oxide film using atomic layer deposition. Embodiments include forming erbium-doped barium strontium titanium oxide film using atomic layer deposition.12-24-2009
20100200900MAGNETORESISTIVE ELEMENT AND METHOD OF MANUFACTURING THE SAME - A magnetoresistive element of an aspect of the present invention including a lower electrode provided on an insulating layer on a semiconductor substrate, a first ferromagnetic layer provided on the lower electrode, a first tunnel barrier layer provided on the first ferromagnetic layer, a second ferromagnetic layer provided on the first tunnel barrier layer, and an upper electrode provided on the second ferromagnetic layer, wherein the upper electrode has a hexagonal cross-sectional shape, and a maximum size of the upper electrode in a first direction is larger than a size of the first tunnel barrier layer in the first direction, the first direction being horizontal relative to a surface of the semiconductor substrate.08-12-2010
20100200899SPIN TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - A spin transistor includes a source electrode, a drain electrode, and a gate electrode on a semiconductor substrate. At least one of the source electrode and the drain electrode includes a semiconductor region and a magnetic layer. The semiconductor region is formed in the semiconductor substrate. The magnetic layer is formed on the semiconductor region, and contains a crystalline Heusler alloy containing at least one of cobalt (Co) and iron (Fe). The semiconductor region and the magnetic layer contain the same impurity element.08-12-2010
20120068236NON-UNIFORM SWITCHING BASED NON-VOLATILE MAGNETIC BASED MEMORY - A non-uniform switching based non-volatile magnetic memory element includes a fixed layer, a barrier layer formed on top of the fixed layer, a first free layer formed on top of the barrier layer, a non-uniform switching layer (NSL) formed on top of the first free layer, and a second free layer formed on top of the non-uniform switching layer. Switching current is applied, in a direction that is substantially perpendicular to the fixed layer, barrier layer, first free layer, non-uniform switching layer and the second free layer causing switching between states of the first free layer, second free layer and non-uniform switching layer with substantially reduced switching current.03-22-2012
20120068235INTEGRATED CIRCUIT - In accordance with an embodiment, an integrated circuit includes a first spin transistor and a second spin transistor. The first spin transistor has a first channel length. The first spin transistor includes a first node and a second node apart from the first node The second spin transistor is connected to the first transistor in series and has a second channel length different from the first channel length. The second spin transistor includes a third node and a fourth node apart from the third node The second node and the fourth node are electrically connected to each other.03-22-2012
20090050949SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - The present invention is to provide a semiconductor memory device capable of providing excellent storage properties, scaling and high integration and a method of fabricating the same. A semiconductor memory device has a multiferroic film exhibiting ferroelectricity and ferromagnetism, a channel region on an interface of a semiconductor substrate below the multiferroic film, source and drain regions formed on both sides of the channel region, a gate electrode (data write electrode) applying gate voltage to the multiferroic film to write data in such a way that the orientation of magnetization is changed as corresponding to the orientation of dielectric polarization, and source and drain electrodes (data read electrodes) that read data based on a deviation in a flow of the carrier, the deviation caused by applying the Lorentz force to the carrier flowing in the channel region from a magnetic field occurring in the channel region because of magnetization.02-26-2009
20090101954Capacitor and semiconductor device having a ferroelectric material - A capacitor includes a pair of electrodes and a ferroelectric film sandwiched between the electrodes. The electrodes are provided perpendicular to the direction of the polarization axis of the ferroelectric film.04-23-2009
20090230445Magnetic Memory Devices Including Conductive Capping Layers - A magnetic memory device includes a first magnetic layer having opposing sidewalls, a tunnel barrier layer on the first magnetic layer, the tunnel barrier layer having a top surface and having opposing sidewalls aligned with the opposing sidewalls of the first magnetic layer, and a second magnetic layer on the tunnel barrier layer, the second magnetic layer having a bottom surface that is narrower than the top surface of the tunnel barrier layer and opposing sidewalls that are spaced apart from the opposing sidewalls of the tunnel barrier layer. A conductive capping layer having opposing sidewalls aligned with the opposing sidewalls of the second magnetic layer is on the second magnetic layer.09-17-2009
20090200592SEMICONDUCTOR DEVICE - A semiconductor device includes: a first source region and a first drain region formed at a distance from each other in a semiconductor substrate; a first gate insulating film formed on the semiconductor substrate between the first source region and the first drain region; a first gate electrode formed on the first gate insulating film; a first source electrode formed above the first source region and including a ferromagnetic layer having an easy axis of magnetization in a first direction; a first drain electrode formed above the first drain region and including a ferromagnetic layer magnetized in a second direction at an angle larger than 0 degrees but not larger than 180 degrees with respect to the first direction; and a second drain electrode formed above the first drain region, being located at a distance from the first drain electrode, and including a ferromagnetic layer magnetized in a direction substantially antiparallel to the second direction.08-13-2009
20090278182SPIN INJECTOR - A spin injector for use in a microelectronic device such as a field effect transistor (FET) is disclosed. The spin injector includes an array of ferromagnetic elements disposed within a semiconductor. The ferromagnetic elements within the array are arranged and spaced with respect to one another in a close arrangement such that electrons or holes are spin-polarized when passing through. The spin injector may be located above or at least partially within a source region of the FET. A spin injector structure may also be located above or at least partially within the drain region of the FET. The spin injector includes a semiconductor material containing an array of ferromagnetic elements disposed in the semiconductor material, wherein adjacent ferromagnetic elements within the array are separated by a distance within the range between about 1 nm and 100 nm.11-12-2009
20090078979SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes: a semiconductor substrate and a transistor formed on the semiconductor substrate. The semiconductor device also includes: a first interlayer insulation film formed on the semiconductor substrate including the upper portion of the transistor, a first contact formed to be connected through the first interlayer insulation film to the transistor, a ferroelectric capacitor formed to be connected to the first contact, a second interlayer insulation film formed on the first interlayer insulation film, and a second contact formed to connect the ferroelectric capacitor to a wiring through the second interlayer insulation film. The contact surfaces between the second contact and the ferroelectric capacitor have the same planar shape.03-26-2009
20100193849SEMICONDUCTOR MEMORY DEVICE INCLUDING FERROELECTRIC FILM AND A METHOD FOR FABRICATING THE SAME - According to one embodiment, a semiconductor memory device having a ferroelectric film, includes a semiconductor substrate, a field effect transistor formed on the semiconductor substrate, an inter-layer insulating film formed on the field effect transistor and the semiconductor substrate, a plug constituted with a single-crystalline structure, the plug being formed in the inter-layer insulating film and being connected with a source or a drain of the field effect transistor, a lower electrode constituted with a single-crystalline structure formed on the plug, a ferroelectric film formed on the lower electrode an upper electrode formed on the ferroelectric film.08-05-2010
20100187583Reconfigurable Electric Circuitry and Method of Making Same - A reconfigurable electric circuit includes first and second crystalline material layers positioned adjacent to each other and forming a first interface, and a first ferroelectric layer positioned adjacent to the first crystalline material layer and having ferroelectric domains applying an electric field to regions of the first interface to induce a quasi two-dimensional electron gas in the regions, wherein at least one of the regions forms a gate and at least one of the regions forms a channel.07-29-2010
20100187584SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes an interlayer insulating film having an opening, an adhesion layer formed on at least a side wall of the opening, a lower electrode formed on a bottom surface of the opening and at least a side surface of the adhesion layer, a capacitor insulating film made of a ferroelectric formed on the lower electrode, and an upper electrode formed on the capacitor insulating film. The lower electrode, the capacitor insulating film and the upper electrode constitute a capacitor, and the capacitor has a cross-section having a recessed shape in the opening. The lower electrode has a protruding portion protruding from the opening. The capacitor insulating film is formed, covering at least the protruding portion of the lower electrode, of the lower electrode and the adhesion layer. The upper electrode is formed, covering the capacitor insulating film formed on the protruding portion.07-29-2010
20100258849MAGNETIC TUNNEL JUNCTION TRANSISTOR - A magnetic tunnel junction transistor. In a particular embodiment, the magnetic tunnel junction transistor includes a tunnel barrier having a high resistance when in a non-ferromagnetic state, and a low resistance when in a ferromagnetic state. The tunnel barrier is switchable between the non-ferromagnetic and the ferromagnetic states.10-14-2010
20100193850SEMICONDUCTOR MEMORY DEVICE - First and second transistors are formed on a substrate. An interlayer insulating film is formed on the first transistor. A first contact is formed in the interlayer film on a source or a drain of the first transistor. A second contact is formed in the interlayer film on the other of the source or the drain. A first interconnect is formed on the first contact. A magnetoresistive element is formed on the second contact. The magnetoresistive element is arranged in a layer having a height equal to that of the first interconnect from a substrate surface. A third contact is formed in the interlayer film on a source or a drain of the second transistor. A second interconnect is formed on the third contact. The second interconnect is arranged in a layer having a height equal to those of the first interconnect and the magnetoresistive element from the substrate surface.08-05-2010
20100213519MANUFACTURING METHOD OF SILICON SPIN TRANSPORT DEVICE AND SILICON SPIN TRANSPORT DEVICE - An object of the present invention is to provide a silicon spin transport device manufacturing method and silicon spin transport device whereby improved voltage output characteristics can be obtained. The silicon spin transport device manufacturing method comprises: a first step of patterning a silicon film by wet etching and forming a silicon channel layer; and a second step of forming a magnetization free layer and a magnetization fixed layer, which are apart from each other, on the silicon channel layer.08-26-2010
20100176427HARDMASK MANUFACTURE IN FERROELECTRIC CAPACITORS - A method of manufacturing a semiconductor device. The method comprises fabricating a ferroelectric capacitor. The capacitor's fabrication includes forming conductive and ferroelectric material layers on a semiconductor substrate, forming a hardmask layer on the conductive and ferroelectric material layers, forming an organic bottom antireflective coating layer on the hardmask layer, and, patterning the organic bottom antireflective coating layer. Seasoning in a hardmask etching chamber is substantially unaffected by the patterning.07-15-2010
20100176429MRAM with storage layer and super-paramagnetic sensing layer - An MRAM is disclosed that has a MTJ comprised of a ferromagnetic layer with a magnetization direction along a first axis, a super-paramagnetic (SP) free layer, and an insulating layer formed therebetween. The SP free layer has a remnant magnetization that is substantially zero in the absence of an external field, and in which magnetization is roughly proportional to an external field until reaching a saturation value. In one embodiment, a separate storage layer is formed above, below, or adjacent to the MTJ and has uniaxial anisotropy with a magnetization direction along its easy axis which parallels the first axis. In a second embodiment, the storage layer is formed on a non-magnetic conducting spacer layer within the MTJ and is patterned simultaneously with the MTJ. The SP free layer may be multiple layers or laminated layers of CoFeB. The storage layer may have a SyAP configuration and a laminated structure.07-15-2010
20100224920MAGNETORESISTIVE MEMORY CELL AND METHOD OF MANUFACTURING MEMORY DEVICE INCLUDING THE SAME - A magnetoresistive memory cell includes a magnetic tunnel junction element; and a selection transistor, wherein the selection transistor includes a first conductive type semiconductor layer, a gate electrode formed on the first conductive type semiconductor layer with a gate insulation film interposed between the first conductive type semiconductor layer and the gate electrode, and second conductive type first and second diffusion regions formed in the first conductive type semiconductor such that the first and second diffusion regions are spaced apart from each other. The magnetic tunnel junction element includes a free magnetization layer, a fixed magnetization layer, and a tunnel barrier layer interposed between the free magnetization layer and the fixed magnetization layer, and the free magnetization layer of the magnetic tunnel junction element is electrically connected to any one of the first and second diffusion regions of the selection transistor.09-09-2010
20100224919Ferroic Component - A ferroic component is described, comprising a ferroic layer (09-09-2010
20100224921SEMICONDUCTOR DEVICE INCLUDING FERROELECTRIC CAPACITOR - A semiconductor device includes a ferroelectric capacitor formed above the lower interlevel insulating film covering a MOS transistor formed on a semiconductor substrate, including lamination of a lower electrode, an oxide ferroelectric film, a first upper electrode made of conductive oxide having a stoichiometric composition AO09-09-2010
20120139019MAGNETORESISTIVE EFFECT ELEMENT AND METHOD OF MANUFACTURING MAGNETORESISTIVE EFFECT ELEMENT - A method of manufacturing a magnetoresistive effect element includes forming a first electrode above a substrate, forming a metal layer of a metal material above the first electrode, forming a first magnetic layer above the metal layer, forming a tunnel insulating film above the first magnetic layer, forming a second magnetic layer above the tunnel insulating film, forming a second electrode layer above the second magnetic layer, patterning the second electrode layer, patterning the second magnetic layer, the tunnel insulating film, the first magnetic layer and the metal layer, while depositing sputtered particles of the metal film on side walls of the second magnetic layer, the tunnel insulating film, the first magnetic layer and the metal layer to form a sidewall metal layer, and oxidizing the sidewall metal layer to form an insulative sidewall metal oxide layer.06-07-2012
20100148232SURFACE TREATMENT OF HYDROPHOBIC FERROELECTRIC POLYMERS FOR PRINTING - An embodiment is a method and apparatus to treat surface of polymer for printing. Surface of a polymer having a surface energy modified for a time period to control a feature characteristic and/or provide a hysteresis behavior. A material is printed on the surface to form a circuit pattern having at least one of the controlled feature characteristic and the hysteresis behavior.06-17-2010
20090250735SEMICONDUCTOR MEMORY - A semiconductor memory according to an embodiment of the present invention including first and second adjacent bit lines extending in a first direction and provided in the same interconnect layer, an active provided in a memory cell array, a first and second adjacent word lines extending in a second direction intersecting the first direction, a cell group having two transistor provided in the active region and two resistive storage element, wherein the active region has a striped structure, and extends from one end of the memory cell array to the other.10-08-2009
20090020797SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - An FeRAM is produced by a method including the steps of forming a lower electrode layer (01-22-2009
20100032737Nano-magnetic memory device and method of manufacturing the device - A nano-magnetic memory device capable of writing/reading multi data in the nano-magnetic memory cell by controlling an amount of an induced current which is formed after a magnetic nanodot is perturbed and rearranged according to a word line current flowing from the first electrode through a nanowire of the nano-magnetic memory device to the second electrode. Consequently, a size of the memory device is reduced and a density of the memory device may be improved by providing a simplified nano-magnetic memory device of which a cell size is smaller.02-11-2010
20100012994SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device has the ferroelectric capacitor has: a capacitor film formed above the MOS transistor with an interlayer insulating film interposed therebetween; a first capacitor electrode electrically connected to a source region of the MOS transistor and formed in contact with one side wall of the capacitor film; and a second capacitor electrode electrically connected to a drain region of the MOS transistor and formed in contact with the other side wall of the capacitor film, and the capacitor film is composed of a film stack including a plurality of films including a first insulating film intended to orient a film formed on an upper surface thereof in a predetermined direction and a ferroelectric film formed on the first insulating film to be oriented in a direction perpendicular to the semiconductor substrate.01-21-2010
20080308853Tunnel transistor having spin-dependent transfer characteristics and non-volatile memory using the same - A MISFET the channel region of which is a ferromagnetic semi-conductor has a feature that the drain current can be controlled by the gate voltage and a feature that the transfer conductance can be controlled by the relative directions of magnetization in the ferromagnetic channel region and the ferromagnetic source (or the ferromagnetic drain, or both the ferromagnetic source and ferromagnetic drain). As a result, binary information can be stored in the form of the relative magnetization directions, and the relative magnetization directions are electrically detected. If the magnetism is controlled by the electric field effect of the channel region of a ferromagnetic semiconductor, the current needed to rewrite the information can be greatly reduced. Thus, the MISFET can constitute a high-performance non-volatile memory cell suited to high-density integration.12-18-2008
20110108898SPIN MEMORY AND SPIN FET - A spin memory includes a magneto-resistance element having a first ferromagnetic layer in which a magnetization direction is pinned, a second ferromagnetic layer in which a magnetization direction changes, and a first nonmagnetic layer between the first and second ferromagnetic layers, a lower electrode and an upper electrode extending in a direction between 45 degrees and 90 degrees relative to an axis of hard magnetization of the second ferromagnetic layer, and sandwiching the magneto-resistance element at one end in a longitudinal direction, a switching element connected to another end in a longitudinal direction of the lower electrode, and a bit line connected to another end in a longitudinal direction of the upper electrode, wherein writing is carried out by supplying spin-polarized electrons to the second ferromagnetic layer and applying a magnetic field from the lower electrode and the upper electrode to the second ferromagnetic layer.05-12-2011
20090039401Logic Circuit and Single-Electron Spin Transistor - A logic circuit that can reconfigure its functions in a nonvolatile manner and a single-electron transistor to be used in the logic circuits are provided. The logic circuit has a single-electron spin transistor that includes: a source; a drain; an island that is provided between the source and the drain, and has tunnel junctions between the island and the source and drain; and a gate that is capacitively coupled to the island. In this logic circuit, at least one of the source, the drain, and the island includes a ferromagnetic material having a variable magnetization direction.02-12-2009
20090072286SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD - A semiconductor device includes: a ferroelectric capacitor that is provided above a base substrate and includes a first electrode, a ferroelectric film provided on the first electrode and a second electrode provided on the ferroelectric film; a stopper film that covers a top surface of the second electrode of the ferroelectric capacitor; a hydrogen barrier film that covers a top surface and a side surface of the stopper film and a side surface of the ferroelectric capacitor; an interlayer dielectric film that covers the hydrogen barrier film and the base substrate; a contact hole that penetrates the interlayer dielectric film, the hydrogen barrier film and the stopper film and exposes the second electrode; a barrier metal that covers the second electrode exposed in the contact hole and an inner wall surface of the contact hole and is composed of a conductive material having hydrogen barrier property; and a plug conductive section that is embedded in the contact hole and conductively connects to the barrier metal, wherein the stopper film is formed from a dielectric material having a smaller etching rate than an etching rate of the interlayer dielectric film.03-19-2009
20100019297Multi-Stacked Spin Transfer Torque Magnetic Random Access Memory and Method of Manufacturing the Same - A spin transfer torque magnetic random access memory (STT-MRAM) device comprises adjacent magnetic tunneling junctions (MTJ), respectively, formed in different layers, thereby preventing interference between the MTJs and securing thermal stability.01-28-2010
20100187585Spin MOS field effect transistor and tunneling magnetoresistive effect element using stack having Heusler alloy - A spin MOS field effect transistor includes a source electrode and a drain electrode each having a structure obtained by stacking an impurity diffusion layer, a (001)-oriented MgO layer and a Heusler alloy. The impurity diffusion layer is formed in a surface region of a semiconductor layer. The (001)-oriented MgO layer is formed on the impurity diffusion layer. The Heusler alloy is formed on the MgO layer.07-29-2010
20110018043SEMICONDUCTOR MEMORY DEVICE - A memory includes first contact plugs; ferroelectric capacitors above the first contact plugs; second contact plugs in a first interlayer film being below an area which is between two adjacent ferroelectric capacitors, the second contact plug; first interconnections connected to the second contact plugs, the first interconnections extending in a first direction substantially perpendicular to an arrangement direction, in which the two ferroelectric capacitors are arranged, on the first interlayer film; a second interlayer film above the first interlayer film and the first interconnection; third contact plugs in the second interlayer film, the third contact plugs being respectively connected to the first interconnections at positions shifted from the second contact plugs in the first direction; and second interconnections electrically connecting the third contact plug to the upper electrodes of the two ferroelectric capacitors.01-27-2011
20110031544SEMICONDUCTOR APPARATUS AND METHOD FOR MANUFACTURING THE SAME - According to an aspect of the present invention, there is provided a semiconductor apparatus including: a semiconductor substrate; an element isolation region formed in the semiconductor substrate so as to extend in a first direction; a gate electrode formed in the semiconductor substrate so as to extend in a second direction crossing the first direction and to penetrate through the element isolation region; a gate insulating film interposed between the gate electrode and the semiconductor substrate; an interlayer dielectric film formed on the gate electrode; a ferroelectric capacitor including: first and second electrodes disposed on the interlayer dielectric film and a ferroelectric between the first and second electrodes; and first and second semiconductor pillars being in contact respectively with the first and second electrodes.02-10-2011
20110031545Spin transistor based on the spin-filter effect, and non-volatile memory using spin transistors - A spin transistor comprises a spin injector for injecting, from a first nonmagnetic electrode carriers with a spin parallel to a spin band forming the band edge of a first ferromagnetic barrier layer, to a second nonmagnetic electrode layer, as hot carriers. It also comprises a spin analyzer whereby, due to spin-splitting at the band edge of a second ferromagnetic barrier layer, the spin-polarized hot carriers are transported to a third nonmagnetic electrode when the direction of the spin of the carriers injected into the second nonmagnetic electrode is parallel to that of the spin of the spin band at the band edge of the second ferromagnetic barrier layer, whereas the hot carriers are not transported to the third nonmagnetic electrode in the case of antiparallel spin. A memory element is also provided that comprises such a spin transistor.02-10-2011
20090050948SPIN MOS FIELD EFFECT TRANSISTOR AND TUNNELING MAGNETORESISTIVE EFFECT ELEMENT USING STACK HAVING HEUSLER ALLOY - A spin MOS field effect transistor includes a source electrode and a drain electrode each having a structure obtained by stacking an impurity diffusion layer, a (001)-oriented MgO layer and a Heusler alloy. The impurity diffusion layer is formed in a surface region of a semiconductor layer. The (001)-oriented MgO layer is formed on the impurity diffusion layer. The Heusler alloy is formed on the MgO layer.02-26-2009
20100163943SEMICONDUCTOR MEMORY DEVICE - A memory includes a first interlayer on transistors; a first and second plugs connected to the transistor; ferroelectric capacitors; a second interlayer covering a side surface of the capacitor; a local interconnection connecting the second plug to the upper electrode, wherein two upper electrodes adjacent to each other on the second plug are connected to the second plug, the lower electrodes adjacent to each other on the first plug are connected to the first plug, cell blocks comprising the connected capacitors are arranged, cell blocks adjacent to each other are arranged to be shifted by a half pitch of the local interconnection, a first gap between two capacitors adjacent to each other on the second plug is larger than twice a thickness of the second interlayer, and a second gap between the cell blocks adjacent to each other is smaller than twice the thickness of the second interlayer.07-01-2010
20100176428Spin field effect logic devices - Provided are spin field effect logic devices, the logic devices including: a gate electrode; a channel formed of a magnetic material above the gate electrode to selectively transmit spin-polarized electrons; a source on the channel; and a drain and an output electrode on the channel outputting electrons transmitted from the source. The gate electrode may control a magnetization state of the channel in order to selectively transmit the electrons injected from the source to the channel.07-15-2010
20090218607NONVOLATILE SEMICONDUCTOR MEMORY AND MANUFACTURING METHOD THEREOF - A nonvolatile semiconductor memory of an aspect of the invention includes memory cells in the memory cell forming area, and select gate transistors in the select gate forming area. Each memory cell has two first diffusion layers formed in a semiconductor substrate, a first gate insulating film formed on the semiconductor substrate, a charge storage layer formed on the first gate insulating film, a first intermediate insulating film formed on the charge storage layer and a first gate electrode formed on the first intermediate insulating film. Each select gate transistor has two second diffusion layers formed in the semiconductor substrate, a second gate insulating film formed on the semiconductor substrate, a second intermediate insulating film formed in direct contact with the second gate insulating film and having the same structure as the first intermediate insulating film, and a second gate electrode formed on the second intermediate insulating film.09-03-2009
20110248325SPIN TRANSISTOR, PROGRAMMABLE LOGIC CIRCUIT, AND MAGNETIC MEMORY - A spin transistor includes a non-magnetic semiconductor substrate having a channel region, a first area, and a second area. The channel region is between the first and the second areas. The spin transistor also includes a first conductive layer located above the first area and made of a ferromagnetic material magnetized in a first direction; and a second conductive layer located above the second area and made of a ferromagnetic material magnetized in one of the first direction and a second direction that is antiparallel with respect to the first direction. The channel region introduces electron spin between the conductive layers. The spin transistor also includes a gate electrode located between the conductive layers and above the channel region; and a tunnel barrier film located between the non-magnetic semiconductor substrate and at least one of the conductive layers.10-13-2011
20110101432SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a capacitor, the capacitor includes a lower electrode, which includes platinum, provided above a semiconductor substrate; a first ferroelectric film, which includes lead zirconate titanate added with La, provided on the lower electrode; a second ferroelectric film, which includes lead zirconate titanate added with La, Ca, and Sr, provided directly on the first ferroelectric film, the second ferroelectric film having a thickness smaller than that of the first ferroelectric film and includes amounts of Ca and Sr greater than amounts of Ca and Sr that may be present in the first ferroelectric film; and an upper electrode, which includes a conductive oxide, provided on the second ferroelectric film.05-05-2011
20110101431SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - To provide a technology capable of improving the property of an MRAM in a semiconductor device containing the MRAM.05-05-2011
20090026514SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A ferroelectric memory is constituted to comprise a capacitor being formed above a semiconductor substrate (01-29-2009
20090026513Method for forming ferroelectric thin films, the use of the method and a memory with a ferroelectric oligomer memory material - In a method for forming ferroelectric thin films of vinylidene fluoride oligomer or vinylidene fluoride co-oligomer, oligomer material is evaporated in vacuum chamber and deposited as a thin film on a substrate which is cooled to a temperature in a range determined by process parameters and physical properties of the deposited VDF oligomer or co-oligomer thin film. In an application of the method of the invention for fabricating ferroelectric memory cells or ferroelectric memory devices, a ferroelectric memory material is provided in the form of a thin film of VDF oligomer or VDF co-oligomer located between electrode structures. A ferroelectric memory cell or ferroelectric memory device fabricated in this manner has the memory material in the form of a thin film of VDF oligomer or VDF co-oligomer provided on at least one of first and second electrode structures, such that the thin film is provided on at least one of the electrode structures or between first and second electrode structures.01-29-2009
20100295108FERROELECTRIC MEMORY DEVICE AND FABRICATION PROCESS THEREOF, FABRICATION PROCESS OF A SEMICONDUCTOR DEVICE - A method for fabricating a ferroelectric memory device, including terminating a surface of the interlayer insulation film and a surface of the contact plug with an OH group; forming a layer containing Si, oxygen and a CH group on the surface of the interlayer insulation film and the contact hole terminated with the OH group by coating a Si compound containing a Si atom and a CH group in a molecule thereof; converting the layer containing Si, oxygen and the CH group to a layer containing nitrogen at a surface thereof, by substituting the CH group in the layer containing Si, oxygen and the CH group at least at a surface part thereof with nitrogen atoms; and forming a layer showing self-orientation on the surface containing nitrogen.11-25-2010
20100264476FERROELECTRIC MEMORY AND ITS MANUFACTURING METHOD - To securely prevent hydrogen from entering a ferroelectric layer of a ferroelectric memory. A first hydrogen barrier layer 10-21-2010
20100252872NONVOLATILE FERROELECTRIC MEMORY DEVICE - A nonvolatile ferroelectric memory device includes a plurality of unit cell arrays, wherein each of the plurality of unit cell arrays includes: a bottom word line; a plurality of insulating layers formed on the bottom word line, respectively; a floating channel layer comprising a plurality of channel regions located on the plurality of insulating layers and a plurality of drain and source regions which are alternately electrically connected in series to the plurality of channel regions; a plurality of ferroelectric layers formed respectively on the plurality of channel regions of the floating channel layer; and a plurality of word lines formed on the plurality of ferroelectric layers, respectively. The unit cell array reads and writes a plurality of data by inducing different channel resistance to the plurality of channel regions depending on polarity states of the plurality of ferroelectric layers.10-07-2010
20110248324DUAL-GATE NON-VOLATILE FERROELECTRIC MEMORY - A dual-gate non-volatile memory cell includes a first dielectric layer extending over a first gate, a semiconductor region extending over the first dielectric layer, a second dielectric layer comprising tunnel oxide extending over the semiconductor region, a ferroelectric layer extending over the second dielectric layer, and a second gate extending over the ferroelectric layer.10-13-2011
20080230819SPIN TRANSFER MAGNETIC ELEMENT WITH FREE LAYERS HAVING HIGH PERPENDICULAR ANISOTROPY AND IN-PLAN EQUILIBRIUM MAGNETIZATION - A method and system for providing a magnetic element that can be used in a magnetic memory is disclosed. The magnetic element includes pinned, nonmagnetic spacer, and free layers. The spacer layer resides between the pinned and free layers. The free layer can be switched using spin transfer when a write current is passed through the magnetic element. The free layer includes a first ferromagnetic layer and a second ferromagnetic layer. The second ferromagnetic layer has a very high perpendicular anisotropy and an out-of-plane demagnetization energy. The very high perpendicular anisotropy energy is greater than the out-of-plane demagnetization energy of the second layer.09-25-2008
20080230818NON-VOLATILE MEMORY DEVICE - According to an aspect of the present invention, there is provided a non-volatile memory including: a transistor formed on a semiconductor substrate, the transistor including: two diffusion layers and a gate therebetween; a first insulating film formed on a top and a side surfaces of the gate; a first and a second contact plugs formed on corresponding one of the diffusion layers to contact the first insulating film; a ferroelectric capacitor formed on the first contact plug and on the first insulating film, the ferroelectric capacitor including: a first and a second electrodes and a ferroelectric film therebetween; a third contact plug formed on the second electrode; and a fourth contact plug formed on the second contact plug.09-25-2008
20080277705SEMICONDUCTOR DEVICE, SEMICONDUCTOR WAFER STRUCTURE AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR WAFER STRUCTURE - There is provided a semiconductor device including, a semiconductor substrate having a circuit forming region and a peripheral region, a base insulating film formed over the semiconductor substrate, a capacitor formed of a lower electrode, a capacitor dielectric film made of a ferroelectric material, and an upper electrode in this order over the base insulating film in the circuit forming region, an uppermost interlayer insulating film formed over the capacitor, a seal ring formed over the semiconductor substrate in the peripheral region, the seal ring having a height that reaches at least the upper surface of the interlayer insulating film, and surrounding the circuit forming region, a block film formed over the seal ring and over the interlayer insulating film in the circumference of the seal ring, and an electrode conductor pattern which is formed over the interlayer insulating film in the peripheral region, the electrode conductor pattern having an electrode pad, and having a cross-section exposed to a dicing surface.11-13-2008
20080277704SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - This disclosure concerns a semiconductor device comprising a switching transistor provided on a semiconductor substrate; an interlayer dielectric film formed on the switching transistor; a ferroelectric capacitor including an upper electrode, a ferroelectric film, and a lower electrode formed on the interlayer dielectric film; a contact plug provided within the interlayer dielectric film and electrically connected to the lower electrode; a diffusion layer connected to between the contact plug and the switching transistor; a barrier metal covering a whole upper surface of the upper electrode; and an insulation sidewall film provided on a side surface of the barrier metal and provided substantially on a same plane as a side surface of the upper electrode.11-13-2008
20100320519FERROELECTRIC MEMORY AND MANUFACTURING METHOD THEREOF, AND MANUFACTURING METHOD OF FERROELECTRIC CAPACITOR - Provided is a ferroelectric memory including a silicon substrate, a transistor formed on the silicon substrate, and a ferroelectric capacitor formed above the transistor. The ferroelectric capacitor includes a lower electrode, a ferroelectric film formed on the lower electrode, an upper electrode formed on the ferroelectric film, and a metal film formed on the upper electrode.12-23-2010
20100320518SEMICONDUCTOR DEVICE - According to an aspect of the present invention, there is provided a semiconductor device including: a transistor including: a source, a drain and a gate; first and second plugs on the source and the drain; a third plug on the gate to have a top face higher than that of the first plug; an interlayer insulating film covering the transistor and the first to the third plugs; a ferroelectric capacitor on the interlayer insulating film, one electrode thereof being connected to the first plug; a barrier film covering surfaces of the ferroelectric capacitor and the interlayer insulating film to prevent a substance affecting the ferroelectric capacitor from entering therethrough; and fourth and fifth plugs disposed on the second and the third plugs and connected thereto through connection holes formed in the barrier film.12-23-2010
20110108899FERROELECTRIC ORGANIC MEMORIES WITH ULTRA-LOW VOLTAGE OPERATION - A method of manufacturing a patterned ferroelectric polymer memory medium is disclosed, which includes forming an electrode on a substrate; forming a ferroelectric polymer thin film on the electrode; and patterning and orienting the polymer thin film into a plurality of nanostructures by embossing techniques. Also disclosed are two methods which include forming nanofeatures in an interlayer dielectric (ILD) layer deposited on a substrate; forming a ferroelectric polymer thin film on the ILD layer in the nanofeatures; and patterning and orienting the polymer thin film into a plurality of nanostructures by pressing. The patterning process followed by an annealing process promotes specific crystal orientation, which significantly reduces the operation voltage, and increases the signal-to-noise ratio. The invention also covers devices made of a ferroelectric polymer layer oriented by such an embossing method and the use of such devices at a coercive field of 10 MV/m or less.05-12-2011
20110084323Transistor Performance Modification with Stressor Structures - A transistor structure with stress enhancement geometry aligned above the channel region. Also, a transistor structure with stress enhancement geometries located above and aligned with opposite sides of the channel region. Furthermore, methods for fabricating integrated circuits containing transistors with stress enhancement geometries.04-14-2011
20120199895SEMICONDUCTOR DEVICE - A semiconductor device includes: a spin torque written in-plane magnetization magnetoresistive element, placed over the main surface of a semiconductor substrate, whose magnetization state can be changed according to the direction of a current flow; and a first wiring electrically coupled with the magnetoresistive element and extended toward the direction along the main surface. The aspect ratio of the magnetoresistive element as viewed in a plane is a value other than 1. In a memory cell area where multiple memory cells in which the magnetoresistive element and a switching element are electrically coupled with each other are arranged, the following measure is taken: multiple magnetoresistive elements adjoining to each other in the direction of length of each magnetoresistive element as viewed in a plane are so arranged that they are not on an identical straight line extended in the direction of length.08-09-2012
20100117127SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor storage device includes a memory cell having a ferroelectric capacitor and a cell transistor connected in parallel. The memory cell includes: a first conductive layer provided above a substrate; a ferroelectric layer formed on a top surface of the first conductive layer; a second conductive layer formed on a top surface of the ferroelectric layer; and a stopper layer formed in the same layer as the ferroelectric layer. A selection ratio of the stopper layer under CMP is higher than that of the ferroelectric layer under CMP.05-13-2010
20110260224THIN FILM MAGNETIC MEMORY DEVICE CAPABLE OF CONDUCTING STABLE DATA READ AND WRITE OPERATIONS - A tunnel magnetic resistive element forming a magnetic memory cell includes a fixed magnetic layer having a fixed magnetic field of a fixed direction, a free magnetic layer magnetized by an applied magnetic field, and a tunnel barrier that is an insulator film provided between the fixed and free magnetic layers in a tunnel junction region. In the free magnetic layer, a region corresponding to an easy axis region having characteristics desirable as a memory cell is used as the tunnel junction region. A hard axis region having characteristics undesirable as a memory cell is not used as a portion of the tunnel magnetic resistive element.10-27-2011
20080217669SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING SEMICONDUCTOR MEMORY DEVICE - According to an aspect of the present invention, there is provided a semiconductor memory device comprising, a first transistor and a second transistor formed on a semiconductor substrate, a memory capacitor formed above the first transistor, the memory capacitor being connected to the first transistor, a dummy memory capacitor formed above the second transistor, a wiring layer formed above the memory capacitor and the dummy memory capacitor, the wiring layer being connected to the first transistor and the memory capacitor, a first plug connecting between the second transistor and the dummy memory capacitor, and a second plug connecting between the dummy memory capacitor and the wiring layer.09-11-2008
20080217668Semiconductor device and method of manufacturing the same - After a ferroelectric capacitor (09-11-2008
20110147816SPIN TORQUE MAGNETIC INTEGRATED CIRCUITS AND DEVICES THEREFOR - Spin torque magnetic integrated circuits and devices therefor are described. A spin torque magnetic integrated circuit includes a first free ferromagnetic layer disposed above a substrate. A non-magnetic layer is disposed above the first free ferromagnetic layer. A plurality of write pillars and a plurality of read pillars are included, each pillar disposed above the non-magnetic layer and including a fixed ferromagnetic layer.06-23-2011
20100025747METHOD FOR INITIALIZING FERROELECTRIC MEMORY DEVICE, FERROELECTRIC MEMORY DEVICE, AND ELECTRONIC EQUIPMENT - A method for initializing a ferroelectric memory device is provided. The method includes the steps of: packaging a ferroelectric memory device having memory cells arranged in an array, each of the memory cells having a ferroelectric film disposed between a lower electrode and an upper electrode; applying a potential between the lower electrode and the upper electrode in an examination step; and after the examination step, applying a first potential to the upper electrode and applying a second voltage higher than the first potential to the lower electrode, and thereafter conducting a heat treatment at a first temperature higher than an operation guarantee temperature.02-04-2010
20100019298Assemblies Comprising Magnetic Elements And Magnetic Barrier Or Shielding - The invention includes a method of forming a semiconductor construction, such as an MRAM construction. A block is formed over a semiconductor substrate. First and second layers are formed over the block, and over a region of the substrate proximate the block. The first and second layers are removed from over the block while leaving portions of the first and second layers over the region proximate the block. At least some of the first layer is removed from under the second layer to form a channel over the region proximate the block. A material, such as a soft magnetic material, is provided within the channel. The invention also includes semiconductor constructions.01-28-2010
20090173978SEMICONDUCTOR MEMORY CELL AND SEMICONDUCTOR MEMORY ARRAY USING THE SAME - A memory element including a first FET, and a selection switch including a second FET are connected in series, and a semiconductor film and a dielectric film stacked over a substrate form a common channel and a common gate insulating film in the first and second FETs. A first gate electrode of the first FET and a second gate electrode of the second FET are formed on the dielectric film, and a drain electrode and a source electrode are formed on the semiconductor film. Under the semiconductor film, a back-gate electrode is formed with a ferroelectric film interposed therebetween, and the ends of the semiconductor film that forms the channel are located inwardly of the ends of the back-gate electrode.07-09-2009
20090173977Method of MRAM fabrication with zero electrical shorting - An MTJ cell without footings and free from electrical short-circuits across a tunneling barrier layer is formed by using a Ta hard mask layer and a combination of etches. A first etch patterns the Ta hard mask, while a second etch uses O07-09-2009
20100283090MAGNETIC NANOTRANSISTOR - The present invention discloses methods and processes for producing magnetic nanotransistors containing carbon nanotubes. The nanotube is attached to at least one magnetic particle, the nanotube is then placed in between the two fixed magnetic moments, and subjected to an external magnetic field. The current passing through the nanotube can be controlled using the external magnetic field.11-11-2010
20100123176SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device has a plurality of first cell selection MOS transistors of a first conductivity type formed on a first element region and connected in series between a bit line and a plate line; a plurality of first ferroelectric capacitors connected to the first cell selection MOS transistors in parallel in one-to-one correspondence; a plurality of second cell selection MOS transistors of the first conductivity type formed on a second element region and connected in series between a bit line and a plate line; and a plurality of second ferroelectric capacitors connected to the second cell selection MOS transistors in parallel in one-to-one correspondence, wherein the first ferroelectric capacitors and the second ferroelectric capacitors are disposed alternately on the first element region and the second element region in the first direction.05-20-2010
20110316059FLEXIBLE FERROELECTRIC MEMORY DEVICE AND MANUFACTURING METHOD FOR THE SAME - The present disclosure relates to a flexible nonvolatile ferroelectric memory device, a 1T-1R (1Transistor-1Resistor) flexible ferroelectric memory device, and a manufacturing method for the same.12-29-2011
20110316058FERRO-ELECTRIC CAPACITOR MODULES, METHODS OF MANUFACTURE AND DESIGN STRUCTURES - Ferro-electric capacitor modules, methods of manufacture and design structures. The method of manufacturing the ferro-electric capacitor includes forming a barrier layer on an insulator layer of a CMOS structure. The method further includes forming a top plate and a bottom plate over the barrier layer. The method further includes forming a ferro-electric material between the top plate and the bottom plate. The method further includes encapsulating the barrier layer, top plate, bottom plate and ferro-electric material with an encapsulating material. The method further includes forming contacts to the top plate and bottom plate, through the encapsulating material. At least the contact to the top plate and a contact to a diffusion of the CMOS structure are in electrical connection through a common wire.12-29-2011
20110156115APPARATUS FOR VARIABLE RESISTIVE MEMORY PUNCHTHROUGH ACCESS METHOD - Variable resistive punchthrough access methods are described. The methods include switching a variable resistive data cell from a high resistance state to a low resistance state by passing a write current through the magnetic tunnel junction data cell in a first direction. The write current is provided by a transistor being electrically coupled to the variable resistive data cell and a source line. The write current passes through the transistor in punchthrough mode.06-30-2011
20120056254SPIN INJECTION ELECTRODE STRUCTURE, SPIN TRANSPORT ELEMENT, AND SPIN TRANSPORT DEVICE - The present invention provides a spin injection electrode structure, a spin transport element, and a spin transport device which enable effective spin injection in a silicon channel layer at room temperature. A spin injection electrode structure IE comprises a silicon channel layer 03-08-2012
20120007158NON-VOLATILE MEMORY TRANSISTOR HAVING DOUBLE GATE STRUCTURE - Provided is a non-volatile memory transistor having a double gate structure, including a first gate electrode formed on a substrate and to which an operating voltage is applied, a first gate insulating layer formed on the first gate electrode, source and drain electrodes formed on the first gate insulating layer at predetermined intervals, a channel layer formed on the first gate insulating layer between the source and drain electrodes, a second gate insulating layer formed on the channel layer, and a second gate electrode formed on the second gate insulating layer and connected to the first gate electrode such that the operating voltage is applied thereto. Accordingly, a turn-on voltage of the memory transistor can be easily controlled.01-12-2012
20120153368SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD - To realize miniaturization/high integration and increase in the amount of accumulated charges, and to give a memory structure having a high reliability. A 1 transistor 1 capacitor (1T1C) structure having 1 ferroelectric capacitor structure and 1 selection transistor every memory cell is adopted, and respective capacitor structures are disposed respectively in either one layer of interlayer insulating films of 2 layers having different heights from the surface of a semiconductor substrate.06-21-2012
20110049593Semiconductor Component - A semiconductor component comprising a semiconductor body, a channel zone in the semiconductor body, a channel control electrode adjacent to the channel zone, and a dielectric layer between the channel zone and the channel control electrode, wherein the dielectric layer has a relative dielectric constant ε03-03-2011
20110049592NONVOLATILE MEMORY CELL AND METHOD OF MANUFACTURING THE SAME - Provided are a nonvolatile memory cell and a method of manufacturing the same. The nonvolatile memory cell includes a memory transistor and a driver transistor. The memory transistor includes a semiconductor layer, a buffer layer, an organic ferroelectric layer, and a gate electrode, which are disposed on a substrate. The driver transistor includes the semiconductor layer, the buffer layer, a gate insulating layer, and the gate electrode, which are disposed on the substrate. The memory transistor and the driver transistor are disposed on the same substrate. The nonvolatile memory cell is transparent in a visible light region.03-03-2011
20100096679FET, FERROELECTRIC MEMORY DEVICE, AND METHODS OF MANUFACTURING THE SAME - Disclosed herein are a field-effect transistor (FET), a ferroelectric memory device, and methods of manufacturing the same. The FET and the ferroelectric memory device in accordance with the present invention include: a substrate 04-22-2010
20090140306Semiconductor device and manufacturing method thereof - There is formed a gate electrode (word line) via a gate insulating film on a semiconductor substrate, the gate electrode extending in the direction inclining at an angle of approximately 45 degrees to the extending direction of an element region. The element region is divided into three portions by the two gate electrodes. In each element region portion, two MOS transistors are provided. A bit line is connected to a W plug provided in the central region portion and lower electrodes of two ferroelectric capacitors are connected to other W plugs provided in both end region portions. The extending direction of the bit line inclines approximately 45 degrees to the extending direction of the element region.06-04-2009
20100193851SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is a semiconductor device including a semiconductor substrate having transistors formed thereon, a first interlayer insulating film formed above the semiconductor substrate and the transistors, a ferroelectric capacitor formed above the first interlayer insulating film, a second interlayer insulating film formed above the first interlayer insulating film and the ferroelectric capacitor, a first metal wiring formed on the second interlayer insulating film, and a protection film formed on an upper surface of the wiring but not on a side surface of the wiring.08-05-2010
20090134440SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device comprising a substrate and a ferroelectric capacitor formed on the substrate. The ferroelectric capacitor includes a lower electrode, an upper electrode and a ferroelectric film interposed between the lower and upper electrodes. The ferroelectric capacitor having sidewalls receded from sidewalls of the upper electrode.05-28-2009
20120119273HYDROGEN BARRIER LINER FOR FERRO-ELECTRIC RANDOM ACCESS MEMORY (FRAM) CHIP - A ferro-electric random access memory (FRAM) chip, including a substrate; a first dielectric layer over the substrate; a gate over the first dielectric layer; a first aluminum oxide layer over the first dielectric layer and the gate; a second dielectric layer over the first aluminum oxide layer; a trench through the second dielectric layer and the first aluminum oxide layer to the gate; a hydrogen barrier liner over the second dielectric layer and lining the trench, and contacting the gate; and a silicon dioxide plug over the hydrogen barrier liner substantially filling the trench.05-17-2012
20120119274NONVOLATILE MEMORY CIRCUIT USING SPIN MOS TRANSISTORS - Certain embodiments provide a nonvolatile memory circuit in which a first p-channel MOS transistor and a first n-channel spin MOS transistor are connected in series, a second p-channel MOS transistor and a second n-channel spin MOS transistor are connected in series, gates of the first p-channel MOS transistor and the first n-channel spin MOS transistor are connected, gates of the second p-channel MOS transistor and the second n-channel spin MOS transistor are connected, a first n-channel transistor includes a drain connected to a drain of the first p-channel transistor and the gate of the second p-channel transistor, a second n-channel transistor includes a drain connected to a drain of the second p-channel transistor and the gate of the first p-channel transistor, and gates of the first and second n-channel transistors are connected.05-17-2012
20120211811MAGNETIC MEMORY AND MANUFACTURING METHOD THEREOF - A magnetic memory has a magnetic recording layer, a reference layer connected via a non-magnetic layer to the magnetic recording layer, first and second magnetization pinning layers disposed below the magnetic recording layer. The magnetic recording layer and the reference layer have a perpendicular magnetic anisotropy. The magnetic recording layer has a magnetization reversal region having a reversible magnetization and overlapping the difference layer, a first magnetization pinned region connected to a first boundary of the magnetization reversal region with the direction of the magnetization being fixed in a first direction, and a second magnetization pinned region connected to a second boundary of the magnetization reversal region with the direction of magnetization being fixed in a second direction anti-parallel to the first direction. The first and the second magnetization pinning layers fix the magnetization of the first and the second magnetization pinned regions.08-23-2012
20100207178SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a semiconductor device comprises: forming a lower electrode on a semiconductor substrate, sputtering a ferroelectric film on the lower electrode using a target, thermal treating the ferroelectric film in an atmosphere containing oxygen in accordance with an accumulated period of use of the target for fabricating the ferroelectric film, and forming an upper electrode on the ferroelectric film.08-19-2010
20110180861MAGNETIC RANDOM ACCESS MEMORY HAVING MAGNETORESISTIVE EFFECT ELEMENT - A magnetic random access memory includes the following structure. A first magnetoresistive effect element is formed on a semiconductor substrate. The first magnetoresistive effect element includes a first fixed layer, a first nonmagnetic layer and a first free layer. The first fixed layer has an invariable magnetization direction. The first nonmagnetic layer is formed on the first fixed layer. The first free layer is formed on the first nonmagnetic layer and has a variable magnetization direction. An active region is formed on the substrate. A first select transistor includes a first diffusion region and a second diffusion region which are formed in the active region. The first diffusion region is electrically connected to the first free layer. A second select transistor includes the first diffusion region and a third diffusion region which are formed in the active region. A first interconnect layer is electrically connected to the first fixed layer.07-28-2011
20120248517MAGNETIC MEMORY DEVICE - According to one embodiment, a magnetic memory device includes a substrate and a plurality of magneto-resistive effect devices provided on a substrate. Two of the plurality of magneto-resistive effect devices, that are nearest to each other when viewed from above, differ from each other in distance from the substrate.10-04-2012
20090057737INTEGRATED CIRCUIT WITH DIELECTRIC LAYER - A method of fabricating an integrated circuit with a dielectric layer on a substrate is disclosed. One embodiment provides forming the dielectric layer in an amorphous state on the substrate, the dielectric layer having a crystallization temperature; a doping the dielectric layer; a forming of a covering layer on the dielectric layer at a temperature being equal to or below the crystallization temperature; and a heating of the dielectric layer to a temperature being equal to or greater than the crystallization temperature.03-05-2009
20090057736Semiconductor Device Having Reduced Single Bit Fails and a Method of Manufacture Thereof - One aspect of the invention provides a method of manufacturing a FeRAM semiconductor device having reduce single bit fails. This aspect includes forming an electrical contact within a dielectric layer located over a semiconductor substrate and forming a first barrier layer over the dielectric layer and the electrical contact. The first barrier layer is formed by depositing multiple barrier layers and densifying each of the barrier layers after its deposition. This forms a stack of multiple barrier layers of a same elemental composition. The method further includes forming a second barrier layer over the first barrier layer and forming a lower capacitor electrode, a ferroelectric dielectric layer over the lower capacitor, and forming an upper capacitor electrode over the ferroelectric dielectric layer. A device made by this method is also provided herein.03-05-2009
20120168838SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device according to an embodiment includes: a semiconductor layer; source and drain regions in the semiconductor layer; a magnetic metal semiconductor compound film on each of the source and drain regions, the magnetic metal semiconductor compound film including the same semiconductor as a semiconductor of the semiconductor layer and a magnetic metal; a gate insulating film on the semiconductor layer between the source region and the drain region; a gate electrode on the gate insulating film; a gate sidewall formed at a side portion of the gate electrode, the gate sidewall being made of an insulating material; a film stack formed on the magnetic metal semiconductor compound film on each of the source and drain regions, the film stack including a magnetic layer; and an oxide layer formed on the gate sidewall, the oxide layer containing the same element as an element in the film stack.07-05-2012
20100052023SEMICONDUCTOR DEVICE HAVING A FERROELECTRIC CAPACITOR AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate, a plurality of transistors connected in series and including a transistor having first and second diffusion regions arranged in the semiconductor substrate. The device also includes an insulating film columnar body arranged above the semiconductor substrate, and having a side which is inclined to a top surface of the substrate by an inclination angle greater than 0 degrees and less than 90 degrees. The device includes a memory cell including a first electrode arranged on the side of the insulating film columnar body and connected to the first diffusion region via a first contact plug, a ferroelectric film arranged on the first electrode, and a second electrode arranged on the ferroelectric film, and connected to the second diffusion region via a second contact plug.03-04-2010
20100052022NONVOLATILE MEMORY AND MANUFACTURING METHOD THEREOF - According to an aspect of the present invention, there is provided a nonvolatile memory including: a cell transistor including: a gate electrode and first and second diffusion layers; a second insulating film covering the cell transistor; first and second plugs penetrating the second insulating film to reach the first and second diffusion layers, respectively; a ferroelectric capacitor having a ferroelectric film and first and second electrodes, the first electrode contacting with the first plug; a first conductive spacer contacting with the second plug and including the same material as the first electrode; a third insulating film covering side faces of the first electrode, the ferroelectric film and the first conductive spacer; and a first wiring that is continuously formed with the second electrode and connected to the first conductive spacer and that includes the same material as the second electrode.03-04-2010
20100052021SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes: a MOS transistor; a bit line provided above a memory region, and electrically connected to an impurity diffusion layer; a capacitor which has a capacitive insulating film including a ferroelectric material or a high-k material, and is provided at a position higher than that of the bit line; a lower hydrogen barrier film which covers a lower side of the capacitor; an upper hydrogen barrier film which covers lateral and upper sides of the capacitor; an interconnect formed above a peripheral circuit region; and a conductive layer which is formed at a position lower than that of the bit line, and extends from the memory region to the peripheral circuit region when viewed from above, for electrically connecting the bit line and the interconnect to each other.03-04-2010
20090095993SEMICONDUCTOR MEMORY DEVICE AND FABRICATING METHOD FOR SEMICONDUCTOR MEMORY DEVICE - According to an aspect of the present invention, there is provided a semiconductor memory device including a ferroelectric capacitor, including a semiconductor substrate, a transistor having diffusion layers being a source and a drain, the transistor being formed on a surface of the semiconductor substrate, a ferroelectric capacitor being formed over the transistor, the ferroelectric capacitor including a lower electrode, a ferroelectric film and an upper electrode stacked in order, an interlayer insulator separating between the transistor and the ferroelectric capacitor, a first contact plug being embedded in the interlayer insulator formed beneath the ferroelectric capacitor, the first contact plug directly connecting between one of the diffusion layers and the lower electrode, a first hydrogen barrier film covering the transistor a second hydrogen barrier film, a portion of the second hydrogen barrier film being formed on the first hydrogen barrier film, another portion of the second hydrogen barrier film covering at least the ferroelectric capacitor, and a second contact plug being embedded in the interlayer insulator, the second hydrogen barrier film and the first hydrogen barrier film, one end of the second contact plug connecting to the other of the diffusion layers.04-16-2009
20120074476INTEGRATED CIRCUIT - In accordance with an embodiment, an integrated circuit includes a circuit in which first and second spin transistors are connected in series. The first spin transistor has a first node and a second node that are equal to each other in magnetization direction. The second spin transistor has a third node and a fourth node that are opposite to each other in magnetization direction. The second node and the fourth node are electrically connected to each other.03-29-2012
20120074475METAL GATE STRUCTURE OF A SEMICONDUCTOR DEVICE - The applications discloses a semiconductor device comprising a substrate having a first active region, a second active region, and an isolation region having a first width interposed between the first and second active regions; a P-metal gate electrode over the first active region and extending over at least ⅔ of the first width of the isolation region; and an N-metal gate electrode over the second active region and extending over no more than ⅓ of the first width. The N-metal gate electrode is electrically connected to the P-metal gate electrode over the isolation region.03-29-2012
20120223374SEMICONDUCTOR DEVICE - A semiconductor device according to an embodiment includes: a semiconductor region on a semiconductor substrate, an upper face and side faces of the semiconductor region forming a saddle-like shape, convex portions being formed at both ends of a region including a saddle point in the upper face; a gate insulating film on the upper face of the semiconductor region except upper faces of the convex portions, and on side faces of the convex portions on a side of the region including the saddle point in the upper face; a gate electrode on the gate insulating film and including: a main body part located immediately above the region including the saddle point in the upper face; and leg portions leading to the main body portion and covering the side faces of the semiconductor region, a length of the leg portions being greater than a length of the main body portion.09-06-2012
20120228683SPIN DEVICE, AND MAGNETIC SENSOR AND SPIN FET USING THE SAME - This spin device includes a semiconductor layer 09-13-2012
20120228685MAGNETIC MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A magnetic memory device and a method for manufacturing the same are disclosed. The magnetic memory device includes a plurality of gates formed on a semiconductor substrate, a source line connected to a source/drain region shared between the gates neighboring with each other, a plurality of magnetic tunnel junctions connected to non-sharing source/drain regions of the gates on a one-to-one basis, and a bit line connected to the magnetic tunnel junctions. The magnetic memory device applies a magnetic memory cell to a memory so as to manufacture a higher-integration magnetic memory, and uses the magnetic memory cell based on a transistor of a DRAM cell, resulting in an increase in the availability of the magnetic memory.09-13-2012
20120228684SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A transistor is formed on a semiconductor substrate, and thereafter a first insulating film is formed. Subsequently, a ferroelectric capacitor is formed on the first insulating film, and then a second insulating film is formed on the ferroelectric capacitor. Thereafter, the upper surface of the second insulating film is planarized. Subsequently, a contact hole which reaches one of impurity regions of the transistor is formed, and thus a plug is formed by embedding a conductor in the contact hole. Thereafter, a hydrogen barrier layer is formed of aluminum oxide or the like. Then, a third insulating film is formed on the hydrogen barrier layer. Subsequently, contact holes which are connected to the ferroelectric capacitor and the plug are formed. Thereafter, a conductor is embedded in the contact holes, and thus interconnections are formed.09-13-2012
20080296646SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - According to an aspect of the present invention, there is provided a semiconductor memory device including: a semiconductor substrate; a transistor that is formed on the semiconductor substrate; a ferroelectric capacitor including a bottom electrode that is formed above the semiconductor to be connected with the transistor, a ferroelectric film that is formed on the bottom electrode, and a top electrode that is formed on the ferroelectric film; a first reaction preventing film that covers a lower side surface of the ferroelectric capacitor; and a second reaction preventing film that covers an upper side surface and a top surface of the ferroelectric capacitor.12-04-2008
20110037108MAGNETORESISTIVE MEMORY AND MANUFACTURING METHOD THEREOF - According to one embodiment, a magnetoresistive memory includes first and second contact plugs in a first interlayer insulating film, a lower electrode on the first interlayer insulating film, a magnetoresistive effect element on the lower electrode, and an upper electrode on the magnetoresistive effect element. The lower electrode has a tapered cross-sectional shape in which a dimension of a bottom surface of the lower electrode is longer than a dimension of an upper surface of the lower electrode, one end of the lower electrode is in contact with an upper surface of the first contact plug. The magnetoresistive effect element is provided at a position shifted from a position immediately above the first contact plug in a direction parallel to a surface of the semiconductor substrate.02-17-2011
20110284937SPIN TRANSISTOR USING N-TYPE AND P-TYPE DOUBLE CARRIER SUPPLY LAYER STRUCTURE - A spin transistor that includes: a semiconductor substrate including an upper cladding layer and a lower cladding layer, and a channel layer interposed between the upper and lower cladding layers; a ferromagnetic source and a ferromagnetic drain formed on the semiconductor substrate and spaced from each other in a length direction of the channel layer; and a gate electrode formed on the semiconductor substrate between the source and the drain and having applied a gate voltage thereto to control a spin precession of an electron passing through the channel layer, wherein the semiconductor substrate includes a first carrier supply layer of a first conductivity type disposed below the lower cladding layer and supplying carriers to the channel layer, and a second carrier supply layer of a second conductivity type opposite to the first conductivity type formed on the upper cladding layer and supplying the carriers to the channel layer.11-24-2011
20100096678NANOSTRUCTURED BARIUM STRONTIUM TITANATE (BST) THIN-FILM VARACTORS ON SAPPHIRE - Varactor shunt switches based on a nonlinear dielectric tunability of Ba04-22-2010
20120241828SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A method for manufacturing a semiconductor memory device includes forming a magnetic tunnel junction layer on a lower electrode, forming a spacer having an annular shape on the magnetic tunnel junction layer, forming upper electrodes on both sidewall surfaces of the annular shaped spacer, removing the spacer, and etching the magnetic tunnel junction layer by using the upper electrodes as an etch mask.09-27-2012
20120241827MAGNETORESISTIVE ELEMENT AND MAGNETIC MEMORY - A magnetoresistive element according to an embodiment includes: a first to third ferromagnetic layers, and a first nonmagnetic layer, the first and second ferromagnetic layers each having an axis of easy magnetization in a direction perpendicular to a film plane, the third ferromagnetic layer including a plurality of ferromagnetic oscillators generating rotating magnetic fields of different oscillation frequencies from one another. Spin-polarized electrons are injected into the first ferromagnetic layer and induce precession movements in the plurality of ferromagnetic oscillators of the third ferromagnetic layer by flowing a current between the first and third ferromagnetic layers, the rotating magnetic fields are generated by the precession movements and are applied to the first ferromagnetic layer, and at least one of the rotating magnetic fields assists a magnetization switching in the first ferromagnetic layer.09-27-2012
20120241826ACCESS TRANSISTOR WITH A BURIED GATE - A magnetic memory cell is formed including a magneto tunnel junction (MTJ) and an access transistor, which is used to access the MTJ in operation. The access transistor, which is formed on a silicon substrate, includes a gate, drain and source with the gate position substantially perpendicular to the plane of the silicon substrate thereby burying the gate and allowing more surface area on the silicon substrate for formation of additional memory cells.09-27-2012
20100090262SPIN TRANSISTOR, PROGRAMMABLE LOGIC CIRCUIT, AND MAGNETIC MEMORY - A spin transistor includes a non-magnetic semiconductor substrate having a channel region, a first area, and a second area. The channel region is between the first and the second areas. The spin transistor also includes a first conductive layer located above the first area and made of a ferromagnetic material magnetized in a first direction; and a second conductive layer located above the second area and made of a ferromagnetic material magnetized in one of the first direction and a second direction that is antiparallel with respect to the first direction. The channel region introduces electron spin between the conductive layers. The spin transistor also includes a gate electrode located between the conductive layers and above the channel region; and a tunnel barrier film located between the non-magnetic semiconductor substrate and at least one of the conductive layers.04-15-2010
20100090261MAGNETIC STACK WITH LAMINATED LAYER - A magnetic stack with a multilayer free layer having a switchable magnetization orientation, the free layer comprising a first ferromagnetic portion and a second ferromagnetic portion with an electrically conducting non-magnetic intermediate layer between the first portion and the second portion. The magnetic stack also includes a first ferromagnetic reference layer having a pinned magnetization orientation, a first non-magnetic spacer layer between the free layer and the first reference layer, a second ferromagnetic reference layer having a pinned magnetization orientation, and a second non-magnetic spacer layer between the free layer and the second reference layer.04-15-2010
20130140614SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a semiconductor device comprises: forming a lower electrode on a semiconductor substrate, sputtering a ferroelectric film on the lower electrode using a target, thermal treating the ferroelectric film in an atmosphere containing oxygen in accordance with an accumulated period of use of the target for fabricating the ferroelectric film, and forming an upper electrode on the ferroelectric film.06-06-2013
20130140615SPIN TORQUE TRANSFER MEMORY CELL STRUCTURES AND METHODS - Spin Torque Transfer (STT) memory cell structures and methods are described herein. One or more STT memory cell structures include a tunneling barrier material positioned between a ferromagnetic storage material and a pinned ferromagnetic material in contact with an antiferromagnetic material and a multiferroic material in contact with the ferromagnetic storage material, wherein the antiferromagnetic material, the ferromagnetic storage material, and the pinned ferromagnetic material are located between a first electrode and a second electrode.06-06-2013
20080224195SEMICONDUCTOR DEVICE WITH FERRO-ELECTRIC CAPACITOR - A semiconductor device has a ferro-electric capacitor with small leak current and less process deterioration even upon miniaturization. The semiconductor device includes: a semiconductor element formed in a semiconductor substrate; lamination of an interlayer insulating film and a lower insulating shielding film having a hydrogen/moisture shielding function, the lamination being formed covering the semiconductor element; a conductive adhesion enhancing film formed above the lower insulating shielding film; and a ferro-electric capacitor including a lower electrode formed above the conductive adhesion enhancing film, a ferro-electric film formed on the lower electrode and being disposed within the lower electrode as viewed in plan, and an upper electrode formed on the ferro-electric film and being disposed within the ferro-electric film as viewed in plan, wherein the conductive adhesion enhancing film has a function of improving adhesion of the lower electrode and reducing leak current of the ferro-electric capacitor.09-18-2008
20080224194SEMICONDUCTOR DEVICE AND FABRICATION PROCESS THEREOF - A semiconductor device includes a semiconductor substrate formed with an active element, an oxidation resistant film formed over the semiconductor substrate so as to cover the active element, a ferroelectric capacitor formed over the oxidation resistance film, the ferroelectric capacitor having a construction of consecutively stacking a lower electrode, a ferroelectric film and an upper electrode, and an interlayer insulation film formed over the oxidation resistance film so as to cover the ferroelectric capacitor, wherein there are formed, in the interlayer insulation film, a first via-plug in a first contact hole exposing the first electrode and a second via-plug in a second contact hole exposing the lower electrode, and wherein there is formed another conductive plug in the interlayer insulation film in an opening exposing the oxidation resistant film.09-18-2008
20130175588COHERENT SPIN FIELD EFFECT TRANSISTOR - A coherent spin field effect transistor is provided by depositing a ferromagnetic base like cobalt on a substrate. A magnetic oxide layer is formed on the cobalt by annealing at temperatures on the order of 1000° K to provide a few monolayer thick layer. Where the gate is cobalt, the resulting magnetic oxide is Co07-11-2013
20130126953Methods and Apparatus for MOS Capacitors in Replacement Gate Process - Methods and apparatus for polysilicon MOS capacitors in a replacement gate process. A method includes disposing a gate dielectric layer over a semiconductor substrate; disposing a polysilicon gate layer over the dielectric layer; patterning the gate dielectric layer and the polysilicon gate layer to form a plurality of polysilicon gates spaced by at least a minimum polysilicon to polysilicon pitch; defining a polysilicon resistor region containing at least one of the polysilicon gates and not containing at least one other of the polysilicon gates, which form dummy gates; depositing a mask layer over an inter-level dielectric layer; patterning the mask layer to expose the dummy gates; removing the dummy gates and the gate dielectric layer underneath the dummy gates to leave trenches in the inter-level dielectric layer; and forming high-k metal gate devices in the trenches in the inter-level dielectric layer. An apparatus produced by the method is disclosed.05-23-2013
20080210998Method for manufacturing material layer, method for manufacturing ferroelectric capacitor using the same, ferroelectric capacitor manufactured by the same method, semiconductor memory device having ferroelectric capacitor and manufacturing method thereof - Provided is a method for manufacturing a material layer capable of increasing the deposition rate of a noble metal layer on a ferroelectric layer, a method for manufacturing a ferroelectric capacitor using the same, a ferroelectric capacitor manufactured by the same method, and a semiconductor memory device having the ferroelectric capacitor and a manufacturing method thereof. According to a method for manufacturing the material layer, a ferroelectric layer is formed. The ferroelectric layer may be exposed to seed plasma, and a material layer including a source material of the seed plasma may be formed on a region of the ferroelectric layer exposed to the seed plasma.09-04-2008
20080197391Semiconductor device and method of manufacturing the same - A semiconductor device has a ferroelectric capacitor having a ferroelectric film, an interlayer insulating film having a first layer formed on the ferroelectric capacitor, a plug and a wiring connecting to the ferroelectric capacitor, and a dummy plug in the vicinity of the ferroelectric capacitor.08-21-2008
20080197390SEMICONDUCTOR APPARATUS AND METHOD FOR MANUFACTURING SEMICONDUCTOR APPARATUS - According to an aspect of the present invention, there is provided a semiconductor apparatus including: a semiconductor substrate; a transistor including: a first diffusion layer formed on the semiconductor substrate, and a second diffusion layer formed on the semiconductor substrate; a ferroelectric capacitor including: a bottom electrode connected to the first diffusion layer, a ferroelectric film formed on the bottom electrode, and a top electrode formed on the ferroelectric film; a side wall disposed on a side surface of the ferroelectric capacitor, the side wall having a lower end positioned upper than a bottom plane of the ferroelectric capacitor; and a contact plug connected to the second diffusion layer and to the top electrode, the contact plug being in touch with the side wall.08-21-2008
20110241091CONTROLLING FERROELECTRICITY IN DIELECTRIC FILMS BY PROCESS INDUCED UNIAXIAL STRAIN - A method of controlling ferroelectric characteristics of integrated circuit device components includes forming a ferroelectrically controllable dielectric layer over a substrate; and forming a stress exerting structure proximate the ferroelectrically controllable dielectric layer such that a substantially uniaxial strain is induced in the ferroelectrically controllable dielectric layer by the stress exerting structure; wherein the ferroelectrically controllable dielectric layer comprises one or more of: a ferroelectric oxide layer and a normally non-ferroelectric material layer that does not exhibit ferroelectric properties in the absence of an applied stress.10-06-2011
20120273856TUNNELING MAGNETORESISTIVE EFFECT ELEMENT AND SPIN MOS FIELD-EFFECT - A magnetoresistive effect element includes a first ferromagnetic layer, Cr layer, Heusler alloy layer, barrier layer, and second ferromagnetic layer. The first ferromagnetic layer has the body-centered cubic lattice structure. The Cr layer is formed on the first ferromagnetic layer and has the body-centered cubic lattice structure. The Heusler alloy layer is formed on the Cr layer. The barrier layer is formed on the Heusler alloy layer. The second ferromagnetic layer is formed on the barrier layer.11-01-2012
20100314673MEMORY DEVICE AND MEMORY - A memory device includes: a memory layer that retains information based on a magnetization state of a magnetic material, a first intermediate layer and a second intermediate layer that are provided to sandwich the memory layer and are each formed of an insulator, a first fixed magnetic layer disposed on an opposite side of the first intermediate layer from the memory layer, a second fixed magnetic layer disposed on an opposite side of the second intermediate layer from the memory layer, and a nonmagnetic conductive layer provided between either the first intermediate layer or the second intermediate layer and the memory layer, the memory device being configured so that spin-polarized electrons are injected thereinto in a stacking direction to change the magnetization direction of the memory layer, thereby storing information in the memory layer.12-16-2010
20090321801CAPACITOR INSULATING FILM, METHOD FOR FABRICATING THE SAME, CAPACITOR ELEMENT, METHOD FOR FABRICATING THE SAME, SEMICONDUCTOR MEMORY DEVICE, AND METHOD FOR FABRICATING THE SAME - A capacitor insulating film is composed of a ferroelectric film formed on a substrate and containing an element functioning as a crystal nucleus which allows the growth of a crystal in a random crystal orientation.12-31-2009
20110309418MAGNETORESISTANCE EFFECT ELEMENT AND MAGNETIC RANDOM ACCESS MEMORY - A magnetoresistance effect element includes: a first ferromagnetic layer having invariable magnetization perpendicular to a film plane; a second ferromagnetic layer having variable magnetization perpendicular to the film plane; a first nonmagnetic layer interposed between the first ferromagnetic layer and the second ferromagnetic layer; a third ferromagnetic layer provided on an opposite side of the second ferromagnetic layer from the first nonmagnetic layer, and having variable magnetization parallel to the film plane; and a second nonmagnetic layer interposed between the second and third ferromagnetic layers. Spin-polarized electrons are injected into the second ferromagnetic layer by flowing a current in the direction perpendicular to the film planes between the first and third ferromagnetic layers, precession movement is induced in the magnetization of the third ferromagnetic layer by injecting the spin-polarized electrons, and a microwave magnetic field of a frequency corresponding to the precession movement is applied to the second ferromagnetic layer.12-22-2011
20120018788MAGNETIC STACK WITH LAMINATED LAYER - A magnetic stack with a multilayer free layer having a switchable magnetization orientation, the free layer comprising a first ferromagnetic portion and a second ferromagnetic portion with an electrically conducting non-magnetic intermediate layer between the first portion and the second portion. The magnetic stack also includes a first ferromagnetic reference layer having a pinned magnetization orientation, a first non-magnetic spacer layer between the free layer and the first reference layer, a second ferromagnetic reference layer having a pinned magnetization orientation, and a second non-magnetic spacer layer between the free layer and the second reference layer.01-26-2012
20120056253SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor memory device according to the present embodiment includes a semiconductor substrate, a select transistor, a lower electrode, a magnetic tunnel junction element, a first protection film, an upper electrode, and a second protection film. The select transistor is formed on the semiconductor substrate. The lower electrode is electrically connected to one diffusion layer of the select transistor. The magnetic tunnel junction element is provided on the lower electrode. The first protection film is provided on a side surface of the magnetic tunnel junction element. The upper electrode is provided on the magnetic tunnel junction element and the first protection film. The second protection film is provided on side surfaces of the upper electrode, the first protection film, and the lower electrode.03-08-2012
20130200446SPIN-BASED DEVICE - A spin-based device comprises a channel, first and second electrodes configured, in response to a bias configuration, to generate an electric field along the channel, and a spin injector arranged to inject spin into the channel at a point between the first and second electrodes. The device may further comprise a spin current detector and/or a spin accumulation detector arranged at different points(s) along the channel.08-08-2013
20120086059ENGINEERING MULTIPLE THRESHOLD VOLTAGES IN AN INTEGRATED CIRCUIT - An integrated circuit and method for forming an integrated circuit. There are at least three field-effect transistors with at least two of the field-effect transistors having the same electrically insulating material which is ferroelectric when unstrained or is capable of being ferroelectric when strain is induced. It is optional for the third field-effect transistor to have an electrically insulating material which is ferroelectric when unstrained or is capable of being ferroelectric when strain is induced. The at least three field-effect transistors are strained to varying amounts so that each of the three field-effect transistors has a threshold voltage, Vt, which is different from the Vt of the two other field-effect transistors.04-12-2012

Patent applications in class With ferroelectric material layer