Entries |
Document | Title | Date |
20080315264 | STRAIN-COMPENSATED FIELD EFFECT TRANSISTOR AND ASSOCIATED METHOD OF FORMING THE TRANSISTOR - Disclosed are embodiments of a field effect transistor (FET) having decreased drive current temperature sensitivity. Specifically, any temperature-dependent carrier mobility change in the FET channel region is simultaneously counteracted by an opposite strain-dependent carrier mobility change to ensure that drive current remains approximately constant or at least within a predetermined range in response to temperature variations. This opposite strain-dependent carrier mobility change is provided by a straining structure that is configured to impart a temperature-dependent amount of a pre-selected strain type on the channel region. Also disclosed are embodiments of an associated method of forming the field effect transistor. | 12-25-2008 |
20090057724 | IMAGE SENSOR AND SENSOR UNIT - An image sensor includes a charge storage portion for storing and transferring signal charges, a first electrode for forming an electric field storing the signal charges in the charge storage portion, a charge increasing portion for increasing the signal charges stored in the charge storage portion and a second electrode for forming another electric field increasing the signal charges in the charge increasing portion, wherein the quantity of the signal charges storable in the charge storage portion is not less than the quantity of the signal charges storable in the charge increasing portion. | 03-05-2009 |
20090057725 | Image Sensor and Manufacturing Method Thereof - Disclosed is an image sensor. The image sensor includes a semiconductor substrate including a lower interconnection, a plurality of upper interconnection sections protruding upward from the semiconductor substrate, a first trench disposed between the upper interconnection sections such that the upper interconnection sections are spaced apart from each other, a bottom electrode disposed on an outer peripheral surfaces of the upper interconnection sections, a first conductive layer disposed on an outer peripheral surface of the bottom electrode, an intrinsic layer disposed on the semiconductor substrate including the first conductive layer and the first trench, and having a second trench on the first trench, a second conductive layer disposed on the intrinsic layer and having a third trench on the second trench, a light blocking part disposed in the third trench, and a top electrode disposed on the light blocking part and the second conductive layer. | 03-05-2009 |
20090090937 | Unit pixels, image sensor containing unit pixels, and method of fabricating unit pixels - Example embodiments provide a unit pixel, an image sensor containing unit pixels, and a method of fabricating unit pixels. The unit pixel may include a semiconductor substrate, photoelectric transducers formed within the semiconductor substrate, multi-layered wiring layers formed on a frontside of the semiconductor substrate, inner lenses formed on a backside of the semiconductor substrate corresponding to the photoelectric transducers, and microlenses formed above the inner lenses. | 04-09-2009 |
20090121259 | PAIRED MAGNETIC TUNNEL JUNCTION TO A SEMICONDUCTOR FIELD-EFFECT TRANSISTOR - A magnetic tunnel junction paired to a semiconductor field-effect transistor is described. In one embodiment, there is a circuit that comprises at least one semiconductor field-effect transistor and a magnetic tunnel junction coupled to the at least one semiconductor field-effect transistor. The magnetic tunnel junction has a control line that is configured to control operational characteristics of the at least one semiconductor field-effect transistor. | 05-14-2009 |
20090218601 | TEMPERATURE MONITORING IN A SEMICONDUCTOR DEVICE BY USING AN PN JUNCTION BASED ON SILICON/GERMANIUM MATERIAL - By incorporating germanium material into thermal sensing diode structures, the sensitivity thereof may be significantly increased. In some illustrative embodiments, the process for incorporating the germanium material may be performed with high compatibility with a process flow for incorporating a silicon/germanium material into P-channel transistors of sophisticated semiconductor devices. Hence, temperature control efficiency may be increased with reduced die area consumption. | 09-03-2009 |
20090273009 | Integrated CMOS porous sensor - A single chip wireless sensor ( | 11-05-2009 |
20100252865 | ELECTRONIC DEVICE - The invention relates to an electronic device having a semiconductor die comprising at least one RF-transistor (RFT) occupying a total RF-transistor active area (ARFT) on the die (DS). The total RF-transistor active area (ARFT) includes at least one transistor channel (C) having a channel width (W) and a channel length (L), and at least one bias cell (BC) for biasing the RF-transistor (RFT). The total bias cell active area (ABC) includes at least one transistor channel (C) having a channel width (W) and a channel length (L). The at least one bias cell (BC) occupies a total bias cell active area (ABC) on the die (SD). The total RF-transistor active area (ARFT) is substantially greater than the total bias cell active area (ABC). The total bias cell active area (ABC) has a common centre of area (COABC). The total RF-transistor active area (ARFT) has a common centre of area (COARF). The active areas (ABC, ARFT) are arranged such that both, the common centre of area or sub-areas of the RF-transistor (COARF) and the common centre of area or sub-areas of the bias cell (COABC) are positioned on an axis (AX | 10-07-2010 |
20100276733 | Solid-state circuit device - A commercially mass-produced ultra-miniaturized solid state system for using an ultraminiaturized atomic or molecular integrated circuit with gigabit memory and picosecond speed to automatically perform self-optimizing tasks selected from the group consisting of searching, tracking, teletraining, telelearning, telemedical diagnosis or treatment, and implanting knowledge or skill | 11-04-2010 |
20100308378 | InSb-BASED SWITCHING DEVICE - The present invention provides an InSb-based switching device operating at room temperature by using a magnetic field controlled avalanche process for applying to magneto-logic elements. A switching device of one embodiment includes a p-type semiconductor layer; an n-type semiconductor layer; and contact layers disposed on one of the p-type and n-type semiconductor layers, the p-type semiconductor layer being in contact with the n-type semiconductor layer such that a current can be applied through the contact layers to the p-type and n-type semiconductor layers to cause a current flow from one of the contact layers to the p-type and n-type semiconductor layers and from the p-type and n-type semiconductor layers to the other of the contact layers, whereby the current flow can be controlled by an intensity of a magnetic field applied to the p-type and n-type semiconductor layers substantially perpendicularly thereto. | 12-09-2010 |
20100314668 | DEVICE WITH INTEGRATED CIRCUIT AND ENCAPSULATED N/MEMS AND METHOD FOR PRODUCTION - A method for producing a device including at least one integrated circuit and at least one N/MEMS. The method produces the N/MEMS in at least one upper layer arranged at least above a first section of a substrate, produces the integrated circuit in a second section of the substrate and/or in a semiconductor layer arranged at least above the second section of the substrate, and further produces a cover encapsulating the N/MEMS from at least one layer used for production of a gate in the integrated circuit and/or for producing at least one electrical contact of the integrated circuit. | 12-16-2010 |
20110006348 | ROUNDED THREE-DIMENSIONAL GERMANIUM ACTIVE CHANNEL FOR TRANSISTORS AND SENSORS - A process is provided for fabricating rounded three-dimensional germanium active channels for transistors and sensors. For forming sensors, the process comprises providing a crystalline silicon substrate; depositing an oxide mask on the crystalline silicon substrate; patterning the oxide mask with trenches to expose linear regions of the silicon substrate; epitaxially grow germanium selectively in the trenches, seeded from the silicon wafer; optionally etching the SiO | 01-13-2011 |
20110089472 | INTEGRATED MOS SENSOR HAVING TEMPERATURE SENSOR - A single chip wireless sensor comprises a microcontroller connected by a transmit/receive interface to a wireless antenna. The microcontroller is also connected to an 8 kB RAM, a USB interface, an RS232 interface, 64 kB flash memory, and a 32 kHz crystal. The device senses humidity and temperature, and a humidity sensor is connected by an 18 bit ΣΔ A-to-D converter to the microcontroller and a temperature sensor is connected by a 12 bit SAR A-to-D converter to the microcontroller. The device is an integrated chip manufactured in a single process in which both the electronics and sensor components are manufactured using standard CMOS processing techniques, applied to achieve both electronic and sensing components in an integrated process. | 04-21-2011 |
20110127583 | SEMICONDUCTOR COMPONENT WITH INTEGRATED HALL EFFECT SENSOR - A semiconductor device with an integrated circuit on a semiconductor substrate comprises a Hall effect sensor in a first active region and a lateral high voltage MOS transistor in a second active region. The semiconductor device of the present invention is characterized in that the structure of the integrated Hall effect sensor is strongly related with the structure of a high-voltage DMOS transistor. The integrated Hall effect sensor is in some features similar to a per se known high-voltage DMOS transistor having a double RESURF structure. The control contacts of the Hall effect sensor correspond to the source and drain contacts of the high-voltage DMOS transistor. The semiconductor device of the present invention allows a simplification of the process integration. | 06-02-2011 |
20110127584 | METHOD FOR MANUFACTURING INFRARED IMAGE SENSOR AND INFRARED IMAGE SENSOR - In the method for manufacturing the infrared image sensor, first, a thermal insulation layer ( | 06-02-2011 |
20110175145 | Infrared Sensor - The infrared sensor ( | 07-21-2011 |
20110193138 | ELECTRONIC DEVICE AND MANUFACTURING METHOD - Provided is an electronic device that generates an output signal corresponding to an input signal, comprising a signal processing section that receives the input signal and outputs the output signal corresponding to the input signal, and a floating electrode that accumulates a charge by being irradiated by an electron beam. The signal processing section adjusts electric characteristics of the output signal according to a charge amount accumulated in the floating electrode, and includes a transistor formed on the semiconductor substrate between an input terminal that receives the input signal and an output terminal that outputs the output signal. The floating electrode is formed between a gate electrode of the transistor and the semiconductor substrate | 08-11-2011 |
20110215382 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device is disclosed. The device includes MOSFET1 and MOSFET2 arranged in a first direction, variable resistive element (hereafter R1) above MOSFET1 and MOSFET2, a lower end of the R1 being connected to drains of MOSFET1 and MOSFET2, MOSFET3 and MOSFET4 arranged in the first direction, variable resistive element (hereafter R2) above MOSFET3 and MOSFET4, and a lower end of the R2 being connected to drains of MOSFET3 and MOSFET4. The device further includes first wiring line extending in the first direction and connected to sources of MOSFET1 and MOSFET2, second wiring line extending in the first direction and connected to sources of MOSFET3 and MOSFET4, upper electrode connecting upper end of the R1 and upper end of the R2, and third wiring line extending in the first direction and connected to the upper electrode. | 09-08-2011 |
20120025276 | TEMPERATURE MONITORING IN A SEMICONDUCTOR DEVICE BY USING A PN JUNCTION BASED ON SILICON/GERMANIUM MATERIALS - By incorporating germanium material into thermal sensing diode structures, the sensitivity thereof may be significantly increased. In some illustrative embodiments, the process for incorporating the germanium material may be performed with high compatibility with a process flow for incorporating a silicon/germanium material into P-channel transistors of sophisticated semiconductor devices. Hence, temperature control efficiency may be increased with reduced die area consumption. | 02-02-2012 |
20120175687 | System and Method for Manufacturing a Temperature Difference Sensor - An embodiment of the invention relates to a Seebeck temperature difference sensor that may be formed in a trench on a semiconductor device. A portion of the sensor may be substantially surrounded by an electrically conductive shield. A plurality of junctions may be included to provide a higher Seebeck sensor voltage. The shield may be electrically coupled to a local potential, or left electrically floating. A portion of the shield may be formed as a doped well in the semiconductor substrate on which the semiconductor device is formed, or as a metal layer substantially covering the sensor. The shield may be formed as a first oxide layer on a sensor trench wall with a conductive shield formed on the first oxide layer, and a second oxide layer formed on the conductive shield. An absolute temperature sensor may be coupled in series with the Seebeck temperature difference sensor. | 07-12-2012 |
20120187456 | MAGNETIC RANDOM ACCESS MEMORY AND MANUFACTURING METHOD THEREOF - According to one embodiment, there is disclosed a magnetic random access memory comprising: a semiconductor substrate; a selective transistor formed at the surface region of the semiconductor substrate and having a gate electrode, a gate insulating film, a source and a drain; and a magnetoresistive element formed on the drain including a magnetic storage layer in which a magnetization direction is variable, a magnetic reference layer in which a magnetization direction is fixed, and a nonmagnetic layer sandwiched between the magnetic storage layer and the magnetic reference layer. | 07-26-2012 |
20120187457 | SEMICONDUCTOR DEVICE - A semiconductor device such as an ID chip of the present invention includes an integrated circuit using a semiconductor element formed by using a thin semiconductor film, and an antenna connected to the integrated circuit. It is preferable that the antenna is formed integrally with the integrated circuit, since the mechanical strength of an ID chip can be enhanced. Note that the antenna used in the present invention also includes a conducting wire that is wound round circularly or spirally and fine particles of a soft magnetic material are arranged between the conducting wires. Specifically, an insulating layer in which fine particles of a soft magnetic material are arranged between the conducting wires. Specifically, an insulating layer in which fine particles of a soft magnetic material are included is arranged between the conducting wires. | 07-26-2012 |
20120256236 | INTEGRATED CMOS POROUS SENSOR - A single chip wireless sensor comprises a microcontroller connected by a transmit/receive interface to a wireless antenna. The microcontroller is also connected to an 8 kB RAM, a USB interface, an RS232 interface, 64 kB flash memory, and a 32 kHz crystal. The device senses humidity and temperature, and a humidity sensor is connected by an 18 bit ΣΔ A-to-D converter to the microcontroller and a temperature sensor is connected by a 12 bit SAR A-to-D converter to the microcontroller. The device is an integrated chip manufactured in a single process in which both the electronics and sensor components are manufactured using standard CMOS processing techniques, applied to achieve both electronic and sensing components in an integrated process. | 10-11-2012 |
20120273844 | MAGNETIC RANDOM ACCESS MEMORY AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a magnetic random access memory includes a first gate electrode and a second gate electrode arranged at a predetermined pitch in a first direction, and extending in a second direction perpendicular to the first direction, a first magnetoresistive element formed above a portion between the first gate electrode and the second gate electrode, an electrode layer formed in a position higher than the first magnetoresistive element, and formed to have a distance which is a half of the pitch from the first magnetoresistive element in the first direction, an interconnection formed in a position higher than the electrode layer, and extending in the first direction, and a first via which connects the first magnetoresistive element and the interconnection, and the electrode layer and the interconnection, by using one conductive layer. | 11-01-2012 |
20130001652 | MAGNETORESISTIVE ELEMENT AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a magnetoresistive element includes a storage layer having a variable and perpendicular magnetization, a tunnel barrier layer on the storage layer, a reference layer having an invariable and perpendicular magnetization on the tunnel barrier layer, a hard mask layer on the reference layer, and a sidewall spacer layer on sidewalls of the reference layer and the hard mask layer. An in-plane size of the reference layer is smaller than an in-plane size of the storage layer. A difference between the in-plane sizes of the storage layer and the reference layer is 2 nm or less. The sidewall spacer layer includes a material selected from a group of a diamond, DLC, BN, SiC, B | 01-03-2013 |
20130026544 | FULLY DEPLETED SILICON ON INSULATOR NEUTRON DETECTOR - A method for forming a neutron detector comprises thinning a backside silicon substrate of a radiation detector; and forming a neutron converter layer on the thinned backside silicon substrate of the radiation detector to form the neutron detector. The neutron converter layer comprises one of boron-10 ( | 01-31-2013 |
20130037862 | MAGNETIC RANDOM ACCESS MEMORY - According to one embodiment, a magnetic random access memory includes a plurality of magnetoresistance elements. The plurality of magnetoresistance elements each include a recording layer having magnetic anisotropy perpendicular to a film surface, and a variable magnetization direction, a reference layer having magnetic anisotropy perpendicular to a film surface, and an invariable magnetization direction, and a first nonmagnetic layer formed between the recording layer and the reference layer. The recording layer is physically separated for each of the plurality of magnetoresistance elements. The reference layer and the first nonmagnetic layer continuously extend over the plurality of magnetoresistance elements. | 02-14-2013 |
20130075793 | FIELD EFFECT TRANSISTOR TYPE BIOSENSOR - Provided is a biosensor that makes it possible to detect the electrical properties of a bio-related material contained in an analyte fluid such as an aqueous solution placed on a sensitive membrane and to observe the bio-related material at a high magnification with an observation device such as a microscope. The biosensor comprises: a substrate | 03-28-2013 |
20130248941 | SPIN TRANSISTORS AND MEMORY - A spin transistor according to an embodiment includes: a semiconductor layer including a p | 09-26-2013 |
20130264610 | TEMPERATURE STABILITIZED MEMS - A semiconductor device with temperature control system. Embodiments of the device may include a MEMS chip including a first heater with a dedicated first temperature control loop and a CMOS chip including a second heater with a dedicated second temperature control loop. Each control loop may have a dedicated temperature sensor for controlling the thermal output of each heater. The first heater and sensor are disposed proximate to a MEMS device in the MEMS chip for direct heating thereof. The temperature of the MEMS chip and CMOS chip are independently controllable of each other via the temperature control loops. | 10-10-2013 |
20130277716 | TERAHERTZ ELECTROMAGNETIC WAVE CONVERSION DEVICE - The purpose of the present invention is to improve the efficiency of conversion between terahertz electromagnetic wave energy and direct current energy via plasma waves in a terahertz electromagnetic wave conversion device with a field effect transistor structure. This invention has an HEMT structure having a substrate, an electron transit layer, an electron supply layer, a source and a drain, and includes a first and second group of gates. The gate length of each finger of the first group of gates is narrower than the gate length of each finger of the second group of gates, and each finger of each group of gates is disposed between the source and the drain on the same cycle. A first and second distance from each finger of the first group of gates to two fingers of the second group of gates adjacent to each finger are unequal lengths. | 10-24-2013 |
20130299880 | Spin Transistors Employing a Piezoelectric Layer and Related Memory, Memory Systems, and Methods - Spin transistors and related memory, memory systems, and methods are disclosed. A spin transistor is provided by at least two magnetic tunnel junctions (MTJs) with a shared multiferroic layer. The multiferroic layer is formed from a piezoelectric (PE) thin film over a ferromagnetic thin film (FM channel) with a metal electrode (metal). The ferromagnetic layer functions as the spin channel and the piezoelectric layer is used for transferring piezoelectric stress to control the spin state of the channel. The MTJ on one side of the shared layer forms a source and the MTJ on the other side is a drain for the spin transistor. | 11-14-2013 |
20140097477 | MAGNETIC RANDOM ACCESS MEMORY AND A METHOD OF FABRICATING THE SAME - An aspect of the present embodiment, there is provided magnetic random access memory device including a semiconductor substrate, a selection transistor on the semiconductor substrate, the selection transistor including a diffusion layer, a contact plug on diffusion layer, an amorphous film on the contact plug, a lower electrode provided on the amorphous film, a first magnetic layer, a nonmagnetic layer, a second magnetic layer, an upper electrode stacked in an order and a sidewall contact film on the contact plug, the sidewall contact film being in contact with a sidewall of the upper electrode. | 04-10-2014 |
20140110763 | NANO RESONANCE APPARATUS AND METHOD - A nano resonance apparatus includes a gate electrode configured to generate a magnetic field, and a nanowire connecting a source electrode to a drain electrode and configured to vibrate in the presence of the magnetic field. The nanowire includes a protruding portion extending in a direction of the gate electrode. | 04-24-2014 |
20140151755 | BACKSIDE CMOS COMPATIBLE BIOFET WITH NO PLASMA INDUCED DAMAGE - The present disclosure provides a bio-field effect transistor (BioFET) device and methods of fabricating a BioFET and a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device includes a gate structure disposed on a first surface of a substrate and an interface layer formed on a second surface of the substrate. The substrate is thinned from the second surface to expose a channel region before forming the interface layer. | 06-05-2014 |
20140159121 | NONVOLATILE MAGNETIC ELEMENT AND NONVOLATILE MAGNETIC DEVICE - Provided is a nonvolatile magnetic device that is capable of realizing low power consumption by performing writing with a voltage and is also excellent in retention characteristics. The nonvolatile magnetic device includes a nonvolatile magnetic element. The nonvolatile magnetic element includes: a first free layer made of a ferromagnetic substance; a first insulating layer made of an insulator, the first insulating layer being provided to be connected to the first free layer; a charged layer provided adjacent to the first insulating layer; a second insulating layer made of an insulator, the second insulating layer being provided adjacent to the charged layer; and an injection layer provided adjacent to the second insulating layer. The charged layer is smaller in electric resistivity than both of the first insulating layer and the second insulating layer. The injection layer is smaller in electric resistivity than the second insulating layer. | 06-12-2014 |
20140231882 | Wireless Processor, Wireless Memory, Information System, And Semiconductor Device - The invention provides a processor obtained by forming a high functional integrated circuit using a polycrystalline semiconductor over a substrate which is sensitive to heat, such as a plastic substrate or a plastic film substrate. Moreover, the invention provides a wireless processor, a wireless memory, and an information processing system thereof which transmit and receive power or signals wirelessly. According to the invention, an information processing system includes an element forming region including a transistor which has at least a channel forming region formed of a semiconductor film separated into islands with a thickness of 10 to 200 nm, and an antenna. The transistor is fixed on a flexible substrate. The wireless processor in which a high functional integrated circuit including the element forming region is formed and the semiconductor device transmit and receive data through the antenna. | 08-21-2014 |
20140264463 | Integration of Magneto-Resistive Random Access Memory and Capacitor - The present disclosure provides one embodiment of a semiconductor structure that includes a first metal layer formed on a semiconductor substrate, wherein the first metal layer includes a first metal feature in a first region and a second metal feature in a second region; a second metal layer disposed on the first metal layer, wherein the second metal layer includes a third metal feature in the first region and a fourth metal feature in a second region; a magneto-resistive memory device sandwiched between the first metal feature and the third metal feature; and a capacitor sandwiched between the second metal feature and the fourth metal feature. | 09-18-2014 |
20150311253 | MEMORY DEVICE - Provided is a memory device, including a memory element on a substrate; a protection insulating pattern covering a side surface of the memory element and exposing a top surface of the memory element; an upper mold layer on the protection insulating pattern; and a bit line on and connected to the memory element, the bit line extending in a first direction, the protection insulating pattern including a first protection insulating pattern covering a lower side surface of the memory element; and a second protection insulating pattern covering an upper side surface of the memory element and including a different material from the first protection insulating pattern. | 10-29-2015 |
20150349021 | CMOS-BASED THERMOELECTRIC DEVICE WITH REDUCED ELECTRICAL RESISTANCE - An integrated circuit containing CMOS transistors and an embedded thermoelectric device may be formed by forming field oxide in isolation trenches to isolate the CMOS transistors and thermoelectric elements of the embedded thermoelectric device. N-type dopants are implanted into the substrate to provide at least 1×10 | 12-03-2015 |
20150349022 | CMOS-BASED THERMOPILE WITH REDUCED THERMAL CONDUCTANCE - An integrated circuit containing CMOS transistors and an embedded thermoelectric device is formed by forming isolation trenches in a substrate, concurrently between the CMOS transistors and between thermoelectric elements of the embedded thermoelectric device. Dielectric material is formed in the isolation trenches to provide field oxide which laterally isolates the CMOS transistors and the thermoelectric elements. Germanium is implanted into the substrate in areas for the thermoelectric elements, and the substrate is subsequently annealed, to provide a germanium density of at least 0.10 atomic percent in the thermoelectric elements between the isolation trenches. The germanium may be implanted before the isolation trenches are formed, after the isolation trenches are formed and before the dielectric material is formed in the isolation trenches, and/or after the dielectric material is formed in the isolation trenches. | 12-03-2015 |
20150349023 | CMOS COMPATIBLE THERMOPILE WITH LOW IMPEDANCE CONTACT - An integrated circuit containing CMOS transistors and an embedded thermoelectric device may be formed by forming active areas which provide transistor active areas for an NMOS transistor and a PMOS transistor of the CMOS transistors and provide n-type thermoelectric elements and p-type thermoelectric elements of the embedded thermoelectric device. Stretch contacts with lateral aspect ratios greater than 4:1 are formed over the n-type thermoelectric elements and p-type thermoelectric elements to provide electrical and thermal connections through metal interconnects to a thermal node of the embedded thermoelectric device. The stretch contacts are formed by forming contact trenches in a dielectric layer, filling the contact trenches with contact metal and subsequently removing the contact metal from over the dielectric layer. The stretch contacts are formed concurrently with contacts to the NMOS and PMOS transistors. | 12-03-2015 |
20150357376 | SEMICONDUCTOR MEMORY DEVICE - The inventive concepts provide a semiconductor memory device including variable resistance memory elements. The semiconductor memory device may include a first bit line disposed at a first height from a semiconductor substrate, a second bit line disposed at a second height, which is different from the first height, from the semiconductor substrate, a first variable resistance memory element connected to the first bit line, and a second variable resistance memory element connected to the second bit line. The first and second variable resistance memory elements may be disposed at substantially the same height from the semiconductor substrate. | 12-10-2015 |
20160033588 | Magnetic-Field Sensing Device - Apparatus and associated methods may relate to Magneto-Resistive Sensing Devices (MRSDs). In accordance with an exemplary embodiment, an MRSD comprises an underlying semiconductor device and a magneto-resistive sensor. In some exemplary embodiments, the semiconductor device is processed through most of a standard process flow. After the standard process flow, in various embodiments, a planarization step may be performed to create a more planar top surface. In some embodiments, the magneto-resistive material, which may be made from a Nickel-Iron alloy, called Permalloy, is deposited on the planar surface. A layer of interconnect metallization also may reside in this top region. The magneto-resistive material may contact the topmost layer of metallization of the semiconductor device via contact openings in the planarized surface. In some embodiments, the magneto-resistive material may similarly contact the topmost layer of metallization through these contact openings. The magneto-resistive material resides directly above the underlying circuitry. | 02-04-2016 |
20160056205 | MAGNETIC MEMORY, MAGNETIC MEMORY DEVICE, AND METHOD FOR MANUFACTURING MAGNETIC MEMORY - According to one embodiment, a magnetic memory including a first magnetic unit, a first nonmagnetic unit, a first fixed magnetic unit, a second fixed magnetic unit, a first electrode, a second electrode, and a third electrode. The first magnetic unit extends in a first direction. The first magnetic unit includes a plurality of magnetic domains arranged in the first direction. The first nonmagnetic unit contacts one end of the first magnetic unit. The first fixed magnetic unit is separated from the first magnetic unit. The first fixed magnetic unit contacts the first nonmagnetic unit. The second fixed magnetic unit is separated from the first magnetic unit and the first fixed magnetic unit. The second fixed magnetic unit is in contact with the first nonmagnetic unit. The second fixed magnetic unit is magnetized in a direction different from a magnetization direction of the first fixed magnetic unit. | 02-25-2016 |
20160056369 | HALL EFFECT DEVICE - A hall effect device includes an active Hall region in a semiconductor substrate, and at least four terminal structures, each terminal structure including a switchable supply contact element and a sense contact element, wherein each supply contact element includes a transistor element with a first transistor terminal, a second transistor terminal, and a control terminal, wherein the second transistor terminal contacts the active Hall region or extends in the active Hall region; and wherein the sense contact elements are arranged in the active Hall region and neighboring to the switchable supply contact elements. | 02-25-2016 |
20160060102 | INTEGRATED CMOS AND MEMS DEVICES WITH AIR DIELETRICS - A monolithically integrated CMOS and MEMS device. The device includes a first semiconductor substrate having a first surface region and one or more CMOS IC devices on a CMOS IC device region overlying the first surface region. The CMOS IC device region can also have a CMOS surface region. A bonding material can be provided overlying the CMOS surface region to form an interface by which a second semiconductor substrate can be joined to the CMOS surface region. The second semiconductor substrate has a second surface region coupled to the CMOS surface region by bonding the second surface region to the bonding material. The second semiconductor substrate includes one or more first air dielectric regions. One or more free standing MEMS structures can be formed within one or more portions of the processed first substrate. | 03-03-2016 |
20160071907 | MAGNETORESISTIVE MEMORY DEVICE AND MANUFACTURING METHOD OF THE SAME - According to one embodiment, there is provided a magnetoresistive memory device. The memory device includes active areas arranged on a semiconductor substrate, resistance change elements arrayed to matrix in an X direction and a Y direction above the substrate, and selective transistors provided to correspond to the respective resistance change elements. A plurality of gate electrodes of the selective transistors are spaced apart at regular intervals in the X direction and arranged along the Y direction. Each of the active areas is provided to cross two of the gate electrodes adjacent to each other, such as to be along the X direction at a portion crossing the gate electrodes, and formed to be inclined with respect to the X direction between the adjacent gate electrodes. | 03-10-2016 |
20160071941 | FIELD EFFECT TRANSISTOR AND MAGNETIC MEMORY - According to one embodiment, a field effect transistor includes a semiconductor layer having a first trench, a first gate insulating layer on a bottom surface of the first trench, a first gate electrode on the first gate insulating layer, first and second impurity regions in the semiconductor layer, the first and second impurity regions exposing on first and second side surfaces of the first trench in a first direction, respectively, a first interlayer insulating layer between the first gate electrode and the first impurity region in the first trench, a second interlayer insulating layer between the first gate electrode and the second impurity region in the first trench, and third and fourth impurity regions in the semiconductor layer, the third and fourth impurity regions exposing on the bottom surface of the first trench. | 03-10-2016 |
20160087004 | MAGNETIC MEMORY AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a magnetic memory includes a magnetic element, and a metal layer stacked on the magnetic element. H/D>1.47 is satisfied, where H denotes a sum of thicknesses of the magnetic element and the metal layer in a first direction in which the magnetic element and the metal layer are stacked, and D denotes a width of the magnetic element in a second direction perpendicular to the first direction. | 03-24-2016 |
20160126289 | SEMICONDUCTOR DEVICE INCLUDING MAGNETO-RESISTIVE DEVICE - A semiconductor device comprises a magneto-resistive device capable of performing multiple functions with low power. The semiconductor device comprises a cell transistor in which a first impurity region and a second impurity region are respectively arranged on both sides of a channel region in a channel direction, a source line connected to the first impurity region of the cell transistor, and the magneto-resistive device connected to the second impurity region of the cell transistor. The first impurity region and the second impurity region are asymmetrical about a center of the cell transistor in the channel direction with respect to at least one of a shape and an impurity concentration distribution. | 05-05-2016 |
20160134287 | EMITTER-COUPLED SPIN-TRANSISTOR LOGIC - A switch comprising a spin-transistor and a first control wire. The spin-transistor is configured so that when a magnetic field applied to the spin-transistor is less than a threshold value, the transistor is in a conductive state in which electric current flows through the spin-transistor. When the magnetic field applied to the spin-transistor is greater than the threshold value, the spin-transistor is in a resistive state in which the electric current flowing through the spin-transistor is substantially reduced. The first control wire is for receiving a current to affect the magnetic field applied to the spin-transistor. | 05-12-2016 |
20160155778 | MAGNETIC MEMORY ELEMENT AND MAGNETIC MEMORY | 06-02-2016 |
20160163369 | MAGNETIC MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - Provided is a semiconductor device including magnetic tunnel junctions, which are spaced apart from each other on a substrate, and each of which includes a free magnetic pattern, a first pinned magnetic pattern, and a tunnel barrier pattern therebetween. The semiconductor device further includes a separation structure interposed between the magnetic tunnel junctions. The separation structure includes a second pinned magnetic pattern and a first insulating pattern stacked to each other. | 06-09-2016 |
20160172396 | SEMICONDUCTOR DEVICE FOR RADIATION DETECTION | 06-16-2016 |
20160176708 | Methods and Structures of Integrated MEMS-CMOS Devices | 06-23-2016 |
20160197120 | SEMICONDUCTOR STORAGE DEVICE | 07-07-2016 |