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Responsive to non-optical, non-electrical signal

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257 - Active solid-state devices (e.g., transistors, solid-state diodes)

257213000 - FIELD EFFECT DEVICE

Patent class list (only not empty are listed)

Deeper subclasses:

Class / Patent application numberDescriptionNumber of patent applications / Date published
257253000 Chemical (e.g., ISFET, CHEMFET) 93
257254000 Physical deformation (e.g., strain sensor, acoustic wave detector) 51
Entries
DocumentTitleDate
20130026544FULLY DEPLETED SILICON ON INSULATOR NEUTRON DETECTOR - A method for forming a neutron detector comprises thinning a backside silicon substrate of a radiation detector; and forming a neutron converter layer on the thinned backside silicon substrate of the radiation detector to form the neutron detector. The neutron converter layer comprises one of boron-10 (01-31-2013
20130037862MAGNETIC RANDOM ACCESS MEMORY - According to one embodiment, a magnetic random access memory includes a plurality of magnetoresistance elements. The plurality of magnetoresistance elements each include a recording layer having magnetic anisotropy perpendicular to a film surface, and a variable magnetization direction, a reference layer having magnetic anisotropy perpendicular to a film surface, and an invariable magnetization direction, and a first nonmagnetic layer formed between the recording layer and the reference layer. The recording layer is physically separated for each of the plurality of magnetoresistance elements. The reference layer and the first nonmagnetic layer continuously extend over the plurality of magnetoresistance elements.02-14-2013
20130075793FIELD EFFECT TRANSISTOR TYPE BIOSENSOR - Provided is a biosensor that makes it possible to detect the electrical properties of a bio-related material contained in an analyte fluid such as an aqueous solution placed on a sensitive membrane and to observe the bio-related material at a high magnification with an observation device such as a microscope. The biosensor comprises: a substrate 03-28-2013
20110006348ROUNDED THREE-DIMENSIONAL GERMANIUM ACTIVE CHANNEL FOR TRANSISTORS AND SENSORS - A process is provided for fabricating rounded three-dimensional germanium active channels for transistors and sensors. For forming sensors, the process comprises providing a crystalline silicon substrate; depositing an oxide mask on the crystalline silicon substrate; patterning the oxide mask with trenches to expose linear regions of the silicon substrate; epitaxially grow germanium selectively in the trenches, seeded from the silicon wafer; optionally etching the SiO01-13-2011
20120187457SEMICONDUCTOR DEVICE - A semiconductor device such as an ID chip of the present invention includes an integrated circuit using a semiconductor element formed by using a thin semiconductor film, and an antenna connected to the integrated circuit. It is preferable that the antenna is formed integrally with the integrated circuit, since the mechanical strength of an ID chip can be enhanced. Note that the antenna used in the present invention also includes a conducting wire that is wound round circularly or spirally and fine particles of a soft magnetic material are arranged between the conducting wires. Specifically, an insulating layer in which fine particles of a soft magnetic material are arranged between the conducting wires. Specifically, an insulating layer in which fine particles of a soft magnetic material are included is arranged between the conducting wires.07-26-2012
20120025276TEMPERATURE MONITORING IN A SEMICONDUCTOR DEVICE BY USING A PN JUNCTION BASED ON SILICON/GERMANIUM MATERIALS - By incorporating germanium material into thermal sensing diode structures, the sensitivity thereof may be significantly increased. In some illustrative embodiments, the process for incorporating the germanium material may be performed with high compatibility with a process flow for incorporating a silicon/germanium material into P-channel transistors of sophisticated semiconductor devices. Hence, temperature control efficiency may be increased with reduced die area consumption.02-02-2012
20090121259PAIRED MAGNETIC TUNNEL JUNCTION TO A SEMICONDUCTOR FIELD-EFFECT TRANSISTOR - A magnetic tunnel junction paired to a semiconductor field-effect transistor is described. In one embodiment, there is a circuit that comprises at least one semiconductor field-effect transistor and a magnetic tunnel junction coupled to the at least one semiconductor field-effect transistor. The magnetic tunnel junction has a control line that is configured to control operational characteristics of the at least one semiconductor field-effect transistor.05-14-2009
20090090937Unit pixels, image sensor containing unit pixels, and method of fabricating unit pixels - Example embodiments provide a unit pixel, an image sensor containing unit pixels, and a method of fabricating unit pixels. The unit pixel may include a semiconductor substrate, photoelectric transducers formed within the semiconductor substrate, multi-layered wiring layers formed on a frontside of the semiconductor substrate, inner lenses formed on a backside of the semiconductor substrate corresponding to the photoelectric transducers, and microlenses formed above the inner lenses.04-09-2009
20110193138ELECTRONIC DEVICE AND MANUFACTURING METHOD - Provided is an electronic device that generates an output signal corresponding to an input signal, comprising a signal processing section that receives the input signal and outputs the output signal corresponding to the input signal, and a floating electrode that accumulates a charge by being irradiated by an electron beam. The signal processing section adjusts electric characteristics of the output signal according to a charge amount accumulated in the floating electrode, and includes a transistor formed on the semiconductor substrate between an input terminal that receives the input signal and an output terminal that outputs the output signal. The floating electrode is formed between a gate electrode of the transistor and the semiconductor substrate08-11-2011
20090273009Integrated CMOS porous sensor - A single chip wireless sensor (11-05-2009
20110127583SEMICONDUCTOR COMPONENT WITH INTEGRATED HALL EFFECT SENSOR - A semiconductor device with an integrated circuit on a semiconductor substrate comprises a Hall effect sensor in a first active region and a lateral high voltage MOS transistor in a second active region. The semiconductor device of the present invention is characterized in that the structure of the integrated Hall effect sensor is strongly related with the structure of a high-voltage DMOS transistor. The integrated Hall effect sensor is in some features similar to a per se known high-voltage DMOS transistor having a double RESURF structure. The control contacts of the Hall effect sensor correspond to the source and drain contacts of the high-voltage DMOS transistor. The semiconductor device of the present invention allows a simplification of the process integration.06-02-2011
20110127584METHOD FOR MANUFACTURING INFRARED IMAGE SENSOR AND INFRARED IMAGE SENSOR - In the method for manufacturing the infrared image sensor, first, a thermal insulation layer (06-02-2011
20090218601TEMPERATURE MONITORING IN A SEMICONDUCTOR DEVICE BY USING AN PN JUNCTION BASED ON SILICON/GERMANIUM MATERIAL - By incorporating germanium material into thermal sensing diode structures, the sensitivity thereof may be significantly increased. In some illustrative embodiments, the process for incorporating the germanium material may be performed with high compatibility with a process flow for incorporating a silicon/germanium material into P-channel transistors of sophisticated semiconductor devices. Hence, temperature control efficiency may be increased with reduced die area consumption.09-03-2009
20110175145Infrared Sensor - The infrared sensor (07-21-2011
20080315264STRAIN-COMPENSATED FIELD EFFECT TRANSISTOR AND ASSOCIATED METHOD OF FORMING THE TRANSISTOR - Disclosed are embodiments of a field effect transistor (FET) having decreased drive current temperature sensitivity. Specifically, any temperature-dependent carrier mobility change in the FET channel region is simultaneously counteracted by an opposite strain-dependent carrier mobility change to ensure that drive current remains approximately constant or at least within a predetermined range in response to temperature variations. This opposite strain-dependent carrier mobility change is provided by a straining structure that is configured to impart a temperature-dependent amount of a pre-selected strain type on the channel region. Also disclosed are embodiments of an associated method of forming the field effect transistor.12-25-2008
20110089472INTEGRATED MOS SENSOR HAVING TEMPERATURE SENSOR - A single chip wireless sensor comprises a microcontroller connected by a transmit/receive interface to a wireless antenna. The microcontroller is also connected to an 8 kB RAM, a USB interface, an RS232 interface, 64 kB flash memory, and a 32 kHz crystal. The device senses humidity and temperature, and a humidity sensor is connected by an 18 bit ΣΔ A-to-D converter to the microcontroller and a temperature sensor is connected by a 12 bit SAR A-to-D converter to the microcontroller. The device is an integrated chip manufactured in a single process in which both the electronics and sensor components are manufactured using standard CMOS processing techniques, applied to achieve both electronic and sensing components in an integrated process.04-21-2011
20110215382SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device is disclosed. The device includes MOSFET1 and MOSFET2 arranged in a first direction, variable resistive element (hereafter R1) above MOSFET1 and MOSFET2, a lower end of the R1 being connected to drains of MOSFET1 and MOSFET2, MOSFET3 and MOSFET4 arranged in the first direction, variable resistive element (hereafter R2) above MOSFET3 and MOSFET4, and a lower end of the R2 being connected to drains of MOSFET3 and MOSFET4. The device further includes first wiring line extending in the first direction and connected to sources of MOSFET1 and MOSFET2, second wiring line extending in the first direction and connected to sources of MOSFET3 and MOSFET4, upper electrode connecting upper end of the R1 and upper end of the R2, and third wiring line extending in the first direction and connected to the upper electrode.09-08-2011
20100252865ELECTRONIC DEVICE - The invention relates to an electronic device having a semiconductor die comprising at least one RF-transistor (RFT) occupying a total RF-transistor active area (ARFT) on the die (DS). The total RF-transistor active area (ARFT) includes at least one transistor channel (C) having a channel width (W) and a channel length (L), and at least one bias cell (BC) for biasing the RF-transistor (RFT). The total bias cell active area (ABC) includes at least one transistor channel (C) having a channel width (W) and a channel length (L). The at least one bias cell (BC) occupies a total bias cell active area (ABC) on the die (SD). The total RF-transistor active area (ARFT) is substantially greater than the total bias cell active area (ABC). The total bias cell active area (ABC) has a common centre of area (COABC). The total RF-transistor active area (ARFT) has a common centre of area (COARF). The active areas (ABC, ARFT) are arranged such that both, the common centre of area or sub-areas of the RF-transistor (COARF) and the common centre of area or sub-areas of the bias cell (COABC) are positioned on an axis (AX10-07-2010
20090057725Image Sensor and Manufacturing Method Thereof - Disclosed is an image sensor. The image sensor includes a semiconductor substrate including a lower interconnection, a plurality of upper interconnection sections protruding upward from the semiconductor substrate, a first trench disposed between the upper interconnection sections such that the upper interconnection sections are spaced apart from each other, a bottom electrode disposed on an outer peripheral surfaces of the upper interconnection sections, a first conductive layer disposed on an outer peripheral surface of the bottom electrode, an intrinsic layer disposed on the semiconductor substrate including the first conductive layer and the first trench, and having a second trench on the first trench, a second conductive layer disposed on the intrinsic layer and having a third trench on the second trench, a light blocking part disposed in the third trench, and a top electrode disposed on the light blocking part and the second conductive layer.03-05-2009
20090057724IMAGE SENSOR AND SENSOR UNIT - An image sensor includes a charge storage portion for storing and transferring signal charges, a first electrode for forming an electric field storing the signal charges in the charge storage portion, a charge increasing portion for increasing the signal charges stored in the charge storage portion and a second electrode for forming another electric field increasing the signal charges in the charge increasing portion, wherein the quantity of the signal charges storable in the charge storage portion is not less than the quantity of the signal charges storable in the charge increasing portion.03-05-2009
20120175687System and Method for Manufacturing a Temperature Difference Sensor - An embodiment of the invention relates to a Seebeck temperature difference sensor that may be formed in a trench on a semiconductor device. A portion of the sensor may be substantially surrounded by an electrically conductive shield. A plurality of junctions may be included to provide a higher Seebeck sensor voltage. The shield may be electrically coupled to a local potential, or left electrically floating. A portion of the shield may be formed as a doped well in the semiconductor substrate on which the semiconductor device is formed, or as a metal layer substantially covering the sensor. The shield may be formed as a first oxide layer on a sensor trench wall with a conductive shield formed on the first oxide layer, and a second oxide layer formed on the conductive shield. An absolute temperature sensor may be coupled in series with the Seebeck temperature difference sensor.07-12-2012
20120187456MAGNETIC RANDOM ACCESS MEMORY AND MANUFACTURING METHOD THEREOF - According to one embodiment, there is disclosed a magnetic random access memory comprising: a semiconductor substrate; a selective transistor formed at the surface region of the semiconductor substrate and having a gate electrode, a gate insulating film, a source and a drain; and a magnetoresistive element formed on the drain including a magnetic storage layer in which a magnetization direction is variable, a magnetic reference layer in which a magnetization direction is fixed, and a nonmagnetic layer sandwiched between the magnetic storage layer and the magnetic reference layer.07-26-2012
20100276733Solid-state circuit device - A commercially mass-produced ultra-miniaturized solid state system for using an ultraminiaturized atomic or molecular integrated circuit with gigabit memory and picosecond speed to automatically perform self-optimizing tasks selected from the group consisting of searching, tracking, teletraining, telelearning, telemedical diagnosis or treatment, and implanting knowledge or skill11-04-2010
20120256236INTEGRATED CMOS POROUS SENSOR - A single chip wireless sensor comprises a microcontroller connected by a transmit/receive interface to a wireless antenna. The microcontroller is also connected to an 8 kB RAM, a USB interface, an RS232 interface, 64 kB flash memory, and a 32 kHz crystal. The device senses humidity and temperature, and a humidity sensor is connected by an 18 bit ΣΔ A-to-D converter to the microcontroller and a temperature sensor is connected by a 12 bit SAR A-to-D converter to the microcontroller. The device is an integrated chip manufactured in a single process in which both the electronics and sensor components are manufactured using standard CMOS processing techniques, applied to achieve both electronic and sensing components in an integrated process.10-11-2012
20100308378InSb-BASED SWITCHING DEVICE - The present invention provides an InSb-based switching device operating at room temperature by using a magnetic field controlled avalanche process for applying to magneto-logic elements. A switching device of one embodiment includes a p-type semiconductor layer; an n-type semiconductor layer; and contact layers disposed on one of the p-type and n-type semiconductor layers, the p-type semiconductor layer being in contact with the n-type semiconductor layer such that a current can be applied through the contact layers to the p-type and n-type semiconductor layers to cause a current flow from one of the contact layers to the p-type and n-type semiconductor layers and from the p-type and n-type semiconductor layers to the other of the contact layers, whereby the current flow can be controlled by an intensity of a magnetic field applied to the p-type and n-type semiconductor layers substantially perpendicularly thereto.12-09-2010
20120273844MAGNETIC RANDOM ACCESS MEMORY AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a magnetic random access memory includes a first gate electrode and a second gate electrode arranged at a predetermined pitch in a first direction, and extending in a second direction perpendicular to the first direction, a first magnetoresistive element formed above a portion between the first gate electrode and the second gate electrode, an electrode layer formed in a position higher than the first magnetoresistive element, and formed to have a distance which is a half of the pitch from the first magnetoresistive element in the first direction, an interconnection formed in a position higher than the electrode layer, and extending in the first direction, and a first via which connects the first magnetoresistive element and the interconnection, and the electrode layer and the interconnection, by using one conductive layer.11-01-2012
20100314668DEVICE WITH INTEGRATED CIRCUIT AND ENCAPSULATED N/MEMS AND METHOD FOR PRODUCTION - A method for producing a device including at least one integrated circuit and at least one N/MEMS. The method produces the N/MEMS in at least one upper layer arranged at least above a first section of a substrate, produces the integrated circuit in a second section of the substrate and/or in a semiconductor layer arranged at least above the second section of the substrate, and further produces a cover encapsulating the N/MEMS from at least one layer used for production of a gate in the integrated circuit and/or for producing at least one electrical contact of the integrated circuit.12-16-2010

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