Class / Patent application number | Description | Number of patent applications / Date published |
257195000 | Combined with diverse type device | 61 |
20080230806 | HBT and field effect transistor integration - Methods and systems for fabricating an integrated BiFET using two separate growth procedures are disclosed. Performance of the method fabricates the FET portion of the BIFET in a first fabrication environment. Performance of the method fabricates the HBT portion of the BiFET in a second fabrication environment. By separating the fabrication of the FET portion and the HBT portion in two or more separate reactors, the optimum device performance can be achieved for both devices. | 09-25-2008 |
20080315257 | SEMICONDUCTOR DEVICE AND POWER CONVERSION DEVICE USING THE SAME - In a semiconductor device in which a diode and a high electron mobility transistor are incorporated in the same semiconductor chip, a compound semiconductor layer of the high electron mobility transistor is formed on a main surface (first main surface) of a semiconductor substrate of the diode, and an anode electrode of the diode is electrically connected to an anode region via a conductive material embedded in a via hole (hole) reaching a p | 12-25-2008 |
20090026501 | ENHANCEMENT - DEPLETION SEMICONDUCTOR STRUCTURE AND METHOD FOR MAKING IT - A ED-HEMT structure includes a buffer layer ( | 01-29-2009 |
20090189191 | SEMICONDUCTOR DEVICE - A semiconductor device includes a field effect transistor formed of a GaN-based compound semiconductor and having a source electrode, a drain electrode, and a gate electrode, and a diode formed of a semiconductor material having a gandgap energy smaller than a bandgap energy of the GaN-based compound semiconductor. A cathode electrode and an anode electrode of the diode are electrically connected to the source electrode and the gate electrode of the field effect transistor, respectively. | 07-30-2009 |
20090230432 | Hybrid Substrates and Method of Manufacture - A hybrid substrate circuit on a common substrate is disclosed. A first circuit formed in a first semiconductor material is isolated via a buried oxide layer from a second circuit formed in a second semiconductor material. The first and second circuits may include CMOS, HEMTs, P-HEMTs, HBTs, radio frequency circuits, MESFETs, and various pFETs and nFETs. | 09-17-2009 |
20100155781 | MONOLITHIC INTEGRATED CIRCUIT OF A FIELD-EFFECT SEMICONDUCTOR DEVICE AND A DIODE - A field-effect semiconductor device such as a HEMT or MESFET is monolithically integrated with a Schottky diode for feedback, regeneration, or protection purposes. The field-effect semiconductor device includes a main semiconductor region having formed thereon a source, a drain, and a gate between the source and the drain. Also formed on the main semiconductor region, preferably between gate and drain, is a Schottky electrode electrically coupled to the source. The Schottky electrode provides a Schottky diode in combination with the main semiconductor region. A current flow is assured from Schottky electrode to drain without interruption by a depletion region expanding from the gate. | 06-24-2010 |
20100301396 | Monolithic Vertically Integrated Composite Group III-V and Group IV Semiconductor Deviceand Method for Fabricating same - According to one disclosed embodiment, a monolithic vertically integrated composite device comprises a double sided semiconductor substrate having first and second sides, a group IV semiconductor layer formed over the first side and comprising at least one group IV semiconductor device, and a group III-V semiconductor body formed over the second side and comprising at least one group III-V semiconductor device electrically coupled to the at least one group IV semiconductor device. The composite device may further comprise a substrate via and/or a through-wafer via providing electric coupling. In one embodiment, the group IV semiconductor layer may comprise an epitaxial silicon layer, and the at least one group IV semiconductor device may be a combined FET and Schottky diode (FETKY) fabricated on the epitaxial silicon layer. In one embodiment, the at least one group III-V semiconductor device may be a III-nitride high electron mobility transistor (HEMT). | 12-02-2010 |
20110024798 | Semiconductor device and method for manufacturing same - A semiconductor device includes: a compound semiconductor substrate; an n-channel field-effect transistor region formed on the compound semiconductor substrate, and that includes a first channel layer; an n-type first barrier layer that forms a heterojunction with the first channel layer, and supplies an n-type charge to the first channel layer; and a p-type gate region that has a pn junction-type potential barrier against the n-type first barrier layer; and a p-channel field-effect transistor region formed on the compound semiconductor substrate, and that includes a p-type second channel layer, and an n-type gate region that has a pn junction-type potential barrier against the p-type second channel layer. | 02-03-2011 |
20110233615 | SEMICONDUCTOR DEVICE - To provide a semiconductor device in which a rectifying element capable of reducing a leak current in reverse bias when a high voltage is applied and reducing a forward voltage drop Vf and a transistor element are integrally formed on a single substrate. | 09-29-2011 |
20110254056 | SEMICONDUCTOR DEVICE HAVING TRANSISTOR AND RECTIFIER - A semiconductor device having a transistor and a rectifier includes: a current path; a first main electrode having a rectifying function and arranged on one end of the current path; a second main electrode arranged on the other end of the current path; an auxiliary electrode arranged in a region of the current path between the first main electrode and the second main electrode; a third main electrode arranged on the one end of the current path apart from the first main electrode along a direction intersecting the current path; and a control electrode arranged in a region of the current path between the second main electrode and the third main electrode. The transistor includes the current path, the second main electrode, the third main electrode, and the control electrode. The rectifier includes the current path, the first main electrode, the second main electrode, and the auxiliary electrode. | 10-20-2011 |
20110284928 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor layer stack formed on a substrate, a first ohmic electrode and a second ohmic electrode which are formed on the semiconductor layer stack, and are spaced from each other, a first control layer formed between the first ohmic electrode and the second ohmic electrode, and a first gate electrode formed on the first control layer. The first control layer includes a lower layer, an intermediate layer which is formed on the lower layer, and has lower impurity concentration than the lower layer, and an upper layer which is formed on the intermediate layer, and has higher impurity concentration than the intermediate layer. | 11-24-2011 |
20120098038 | SEMICONDUCTOR DEVICE - A semiconductor device includes a high-side field-effect transistor including a high-side drain electrode, a high-side gate electrode, and a high-side source electrode; and a first low-side field-effect transistor including a first low-side drain electrode, a first low-side gate electrode and a first low-side source electrode, wherein the high-side source electrode and the first low-side drain electrode are shared as a single source and drain electrode, and the high-side drain electrode, the high-side gate electrode, the source and drain electrode, the first low-side gate electrode and the first low-side source electrode are arranged in this order while being interposed by gaps, respectively. | 04-26-2012 |
20120126291 | SEMICONDUCTOR DEVICE - A semiconductor device including at least a p-channel field-effect transistor region formed above a compound semiconductor substrate. The p-channel field-effect transistor region includes an undoped buffer layer; a p-type channel layer formed in contact with the buffer layer; a p-type source region and a p-type drain region formed in the channel layer, being separated with each other; and an n-type gate region formed above the channel layer and between the source region and the drain region. The buffer layer is formed having either a multilayer structure including a hole diffusion control layer with a band gap larger than the channel layer, or a single layer structure including only the hole diffusion control layer. | 05-24-2012 |
20120175681 | Method and Layer Structure for Preventing Intermixing of Semiconductor Layers - A semiconductor device includes an etch-stop layer between a first layer of a field-effect transistor and a second layer of a bipolar transistor, each of which includes at least one arsenic-based semiconductor layer. A p-type layer is between the second layer and the etch-stop layer, and the device can include an n-type layer deposited between the etch-stop layer and p-type layer. The p-type layer provides an electric field that inhibits intermixing of the InGaP layer with layers in the first and second layers. | 07-12-2012 |
20120241819 | Composite Semiconductor Device with Turn-On Prevention Control - There are disclosed herein various implementations of composite III-nitride semiconductor devices having turn-on prevention control. In one exemplary implementation, a normally OFF composite semiconductor device comprises a normally ON III-nitride power transistor and a low voltage (LV) device cascoded with the normally ON III-nitride power transistor to form the normally OFF composite semiconductor device. The LV device is configured to have a noise-resistant threshold voltage to provide the turn-on prevention control for the normally OFF composite semiconductor device by preventing noise current from flowing through a channel of the normally ON III-nitride power transistor in a noisy system. | 09-27-2012 |
20120241820 | III-Nitride Transistor with Passive Oscillation Prevention - There are disclosed herein various implementations of semiconductor devices having passive oscillation control. In one exemplary implementation, such a device is implemented to include a III-nitride transistor having a source electrode, a gate electrode and a drain electrode. A damping resistor is configured to provide the passive oscillation control for the III-nitride transistor. In one implementation, the damping resistor includes at least one lumped resistor. | 09-27-2012 |
20120256233 | ELECTROSTATIC DISCHARGE SHUNTING CIRCUIT - An integrated electrostatic discharge (ESD) shunting circuit includes a III-V semiconductor layer, and a first drain-less high electron mobility transistor (HEMT) or a metal-semiconductor FET (MESFET) transistor having a first gate and at least a second drain-less HEMT or MESFET having a second gate formed in the substrate. The HEMTs or MESFETs include a donor layer on the semiconductor layer, no drains, and a source including an ohmic contact layer on the donor layer. | 10-11-2012 |
20120326211 | BIPOLAR HIGH ELECTRON MOBILITY TRANSISTOR AND METHODS OF FORMING SAME - An epilayer structure includes a field-effect transistor structure and a heterojunction bipolar transistor structure. The heterojunction bipolar transistor structure contains an n-doped subcollector and a collector formed in combination with the field-effect transistor structure, wherein at least a portion of the subcollector or collector contains Sn, Te, or Se. In one embodiment, a base is formed over the collector; and an emitter is formed over the base. The bipolar transistor and the field-effect transistor each independently contain a III-V semiconductor material. | 12-27-2012 |
20130015501 | Nested Composite Diode - There are disclosed herein various implementations of nested composite diodes. In one implementation, a nested composite diode includes a primary transistor coupled to a composite diode. The composite diode includes a low voltage (LV) diode cascoded with an intermediate transistor having a breakdown voltage greater than the LV diode and less than the primary transistor. In one implementation, the primary transistor may be a group III-V transistor and the LV diode may be an LV group IV diode. | 01-17-2013 |
20130026541 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - In a high-frequency circuit, it is necessary to block galvanically between active elements such as transistors and between an active element and an external terminal, and thus MIM capacitors or the like are used frequently. Among these MIM capacitors, one coupled to the external terminal is easily affected by static electricity from outside, which easily causes a problem of electro-static breakdown or the like. | 01-31-2013 |
20130062667 | ENHANCEMENT/DEPLETION PHEMT DEVICE AND MANUFACTURING METHOD THEREOF - An embodiment of the present invention concerns a layered epitaxial structure for enhancement/depletion PHEMT devices, an enhancement/depletion PHEMT device and a method for manufacturing an enhancement/depletion PHEMT device that finds advantageous, but not exclusive, application in the manufacturing of integrated circuits operating at millimetre-wave and microwave frequencies. | 03-14-2013 |
20130140606 | COMPLEMENTARY LOGIC DEVICE USING SPIN INJECTION - A complementary logic device includes: an insulating layer formed on a substrate; a source electrode formed of a ferromagnetic body on the insulating layer; a gate insulating film; a gate electrode formed on the gate insulating film and controlling a magnetization direction of the source electrode; a channel layer formed on each of a first side surface and a second side surface of the source electrode and transmitting spin-polarized electrons from the source electrode; a first drain electrode formed on the first side surface of the source electrode; and a second drain electrode formed on the second side surface of the source electrode, wherein a magnetization direction of the first drain electrode and a magnetization direction of the second drain electrode are antiparallel to each other. Therefore, not only characteristics of low power and high speed but also characteristics of non-volatility and multiple switching by spin may be obtained. | 06-06-2013 |
20130234208 | Composite Semiconductor Device with Active Oscillation Prevention - There are disclosed herein various implementations of composite semiconductor devices with active oscillation control. In one exemplary implementation, a normally OFF composite semiconductor device comprises a normally ON III-nitride power transistor and a low voltage (LV) device cascoded with the normally ON III-nitride power transistor to form the normally OFF composite semiconductor device. The LV device may be configured to include one or both of a reduced output resistance due to, for example, a modified body implant and a reduced transconductance due to, for example, a modified oxide thickness to cause a gain of the composite semiconductor device to be less than approximately 10,000. | 09-12-2013 |
20130264609 | Semiconductor Structure of Hybrid of Coplanar Ge and III-V and Preparation Method Thereof - The present invention provides a semiconductor structure with a hybrid of Ge and a group III-V material coplanar and a preparation method thereof. A heterogeneously integrated semiconductor structure with Ge and a group III-V semiconductor material coplanar includes at least one Ge substrate formed on a bulk silicon substrate, and the other substrate is the group III-V semiconductor material formed on the Ge semiconductor. The preparation method includes: preparing a Ge semiconductor layer on a bulk silicon substrate; preparing a group III-V semiconductor material layer on the Ge semiconductor layer; performing first photolithography and etching to make a patterned window to a Ge layer so as to form a recess; preparing a spacer in the recess; preparing a Ge film through selective epitaxial growth; performing chemical mechanical polishing to obtain a heterogeneously integrated semiconductor structure with a hybrid of Ge and the group III-V semiconductor material coplanar; removing the spacer and a defect part of the Ge layer close to the spacer; implementing isolation between Ge and the group III-V semiconductor material; and preparing a high performance CMOS device including a Ge channel PMOS and a group III-V channel NMOS by forming an MOS structure. | 10-10-2013 |
20140021514 | NITRIDE-BASED SEMICONDUCTOR DEVICE - A nitride-based semiconductor diode includes a substrate, a first semiconductor layer disposed on the substrate, and a second semiconductor layer disposed on the first semiconductor layer. The first and second semiconductor layers include a nitride-based semiconductor. A first portion of the second semiconductor layer may have a thickness thinner than a second portion of the second semiconductor layer. The diode may further include an insulating layer disposed on the second semiconductor layer, a first electrode covering the first portion of the second semiconductor layer and forming an ohmic contact with the first semiconductor layer and the second semiconductor layer, and a second electrode separated from the first electrode, the second electrode forming an ohmic contact with the first semiconductor layer and the second semiconductor layer. | 01-23-2014 |
20140035004 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device has a first nitride semiconductor layer, a second nitride semiconductor layer provided on the first nitride semiconductor layer and formed of a non-doped or n-type nitride semiconductor having a band gap wider than that of the first nitride semiconductor layer, a heterojunction field effect transistor having a source electrode, a drain electrode, and a gate electrode, a Schottky barrier diode having an anode electrode and a cathode electrode, and first and second element isolation insulating layers. The first element isolation insulating layer has a first end contacting with the drain electrode and the anode electrode, and a second end located in the first nitride semiconductor layer. The second element isolation insulating layer has a third end contacting with the cathode electrode, and a fourth end located in the first nitride semiconductor layer. | 02-06-2014 |
20140042495 | SEMICONDUCTOR ELECTRONIC COMPONENTS AND CIRCUITS - An electronic component includes a high-voltage depletion-mode transistor and a low-voltage enhancement-mode transistor both encased in a single package. A source electrode of the high-voltage depletion-mode transistor is electrically connected to a drain electrode of the low-voltage enhancement-mode transistor, a drain electrode of the high-voltage depletion-mode transistor is electrically connected to a drain lead of the single package, a gate electrode of the low-voltage enhancement-mode transistor is electrically connected to a gate lead of the single package, a gate electrode of the high-voltage depletion-mode transistor is electrically connected to an additional lead of the single package, and a source electrode of the low-voltage enhancement-mode transistor is electrically connected to a conductive structural portion of the single package. | 02-13-2014 |
20140048850 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SEMICONDUCTOR DEVICE - According to example embodiments, a semiconductor device may include a high electron mobility transistor (HEMT) on a first region of a substrate, and a diode on a second region of the substrate. The HEMT may be electrically connected to the diode. The HEMT and the diode may be formed on an upper surface of the substrate such as to be spaced apart from each other in a horizontal direction. The HEMT may include a semiconductor layer. The diode may be formed on another portion of the substrate on which the semiconductor layer is not formed. The HEMT and the diode may be cascode-connected to each other. | 02-20-2014 |
20140084347 | BIDIRECTIONAL HETEROJUNCTION COMPOUND SEMICONDUCTOR PROTECTION DEVICES AND METHODS OF FORMING THE SAME - A protection circuit including a multi-gate high electron mobility transistor (HEMT), a forward conduction control block, and a reverse conduction control block is provided between a first terminal and a second terminal. The multi-gate HEMT includes an explicit drain/source, a first depletion-mode (D-mode) gate, a first enhancement-mode (E-mode) gate, a second E-mode gate, a second D-mode gate, and an explicit source/drain. The drain/source and the first D-mode gate are connected to the first terminal and the source/drain and the second D-mode gate are connected to the second terminal. The forward conduction control block turns on the second E-mode gate when a voltage difference between the first and second terminals is greater than a forward conduction trigger voltage, and the reverse conduction control block turns on the first E-mode gate when the voltage difference is more negative than a reverse conduction trigger voltage. | 03-27-2014 |
20140091366 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - Example embodiments relate to semiconductor devices and/or methods of manufacturing the same. According to example embodiments, a semiconductor device may include a first heterojunction field effect transistor (HFET) on a first surface of a substrate, and a second HFET. A second surface of the substrate may be on the second HFET. The second HFET may have different properties (characteristics) than the first HFET. One of the first and second HFETs may be of an n type, while the other thereof may be of a p type. The first and second HFETs may be high-electron-mobility transistors (HEMTs). One of the first and second HFETs may have normally-on properties, while the other thereof may have normally-off properties. | 04-03-2014 |
20140110760 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device including: a DC/DC converter circuit, wherein the DC/DC converter circuit includes a transistor of a normally-off type, having a first drain electrode connected to an input terminal and a first source electrode connected to an output terminal, which is formed in a first compound semiconductor substrate having a two-dimensional electron gas layer, and a transistor having a second drain electrode connected to the first source electrode and a grounded second source electrode. | 04-24-2014 |
20140117411 | MONOLITHIC INTEGRATED CIRCUIT - A monolithic integrated circuit includes: a substrate having a diode region and a transistor region; a first semiconductor layer on the substrate in the diode region and in the transistor region; a second semiconductor layer on the first semiconductor layer in the diode region and in the transistor region; a third semiconductor layer on the second semiconductor layer in the transistor region, but not located in the diode region; a first electrode in the diode region and connected to the first semiconductor layer; a second electrode in the diode region and connected to the second semiconductor layer; and a source electrode, a gate electrode, and a drain electrode which are on the third semiconductor layer. | 05-01-2014 |
20140175519 | METHOD AND LAYER STRUCTURE FOR PREVENTING INTERMIXING OF SEMICONDUCTOR LAYERS - A semiconductor device includes an etch-stop layer between a first layer of a field-effect transistor and a second layer of a bipolar transistor, each of which includes at least one arsenic-based semiconductor layer. A p-type layer is between the second layer and the etch-stop layer, and the device can include an n-type layer deposited between the etch-stop layer and p-type layer. The p-type layer provides an electric field that inhibits intermixing of the InGaP layer with layers in the first and second layers. | 06-26-2014 |
20140231875 | INTEGRATED CIRCUITS WITH ESD PROTECTION DEVICES - An integrated circuit with ESD protection comprises at least one ESD protection circuit block, which comprises a DC blocking capacitor connected in parallel with at least one compound semiconductor enhancement mode FET as an ESD protection device. The ESD protection circuit block that is built in an integrated circuit provides ESD protection while minimizing the generation of unwanted nonlinear signals resulting from the ESD protection. An integrated circuit comprises a high frequency circuit, a switching element, and two ESD protection circuit blocks, in which the high frequency circuit is connected between a first terminal and a second terminal for inputting or outputting the RF signals, the first ESD protection circuit block is connected from a branch node between the first terminal and the high frequency circuit to the switching element, and the second ESD protection circuit block is connected from the switching element to the ground. | 08-21-2014 |
20140231876 | pHEMT and HBT integrated epitaxial structure - An improved pseudomorphic high electron mobility transistor (pHEMT) and heterojunction bipolar transistor (HBT) integrated epitaxial structure, in which the structure comprises a substrate, a pHEMT structure, an etching-stop spacer layer, and an HBT structure. The pHEMT structure comprises a buffer layer, a bottom barrier layer, a first channel spacer layer, a channel layer, a second channel spacer layer, a Schottky spacer layer, a Schottky donor layer, a Schottky barrier layer, an etching-stop layer, and at least one cap layer. By introducing the first channel spacer layer and the second channel spacer layer to reduce the density of the dislocations and to reduce the compressive strain in the pseudomorphic channel layer. | 08-21-2014 |
20140239350 | SEMICONDUCTOR DEVICE CONTAINING HEMT AND MISFET AND METHOD OF FORMING THE SAME - A semiconductor structure with a MISFET and a HEMT region includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A third III-V compound layer is disposed on the second III-V compound layer is different from the second III-V compound layer in composition. A source feature and a drain feature are disposed in each of the MISFET and HEMT regions on the third III-V compound layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. A gate dielectric layer is disposed under the gate electrode in the MISFET region but above the top surface of the third III-V compound layer. | 08-28-2014 |
20140284662 | SEMICONDUCTOR DEVICE - A semiconductor device of an embodiment includes a normally-off transistor having a first source electrically connected to a source terminal, a first drain, and a first gate electrically connected to a gate terminal, a normally-on transistor having a second source electrically connected to the first drain, a second drain electrically connected to a drain terminal, and a second gate, a capacitor having one end electrically connected to the gate terminal and the other end electrically connected to the second gate; and a first diode having a first anode electrically connected to the capacitor and the second gate and a first cathode electrically connected to the first source. | 09-25-2014 |
20140327048 | Compact Electrostatic Discharge (ESD) Protection Structure - A multi-gate Schottky depletion-mode field effect transistor (FET), at least one diode and two resistors comprise a compact electrostatic discharge (ESD) protection structure. This ESD protection structure can be laid out in a smaller area than typical multiple diode ESD devices. The multi-gate FET may comprise various types of high-electron-mobility transistor (HEMT) devices, e.g., (pseudomorphic) pHEMT, (metamorphic) mHEMT, induced HEMT. The multiple gates of the Schottky field effect device are used to form an ESD trigger and charge draining paths for protection of circuits following the ESD protection device. Both single and dual polarity ESD protection devices may be provided on an integrated circuit die for protection of input-output circuits thereof. | 11-06-2014 |
20140327049 | METHODS OF MANUFACTURING THE GALLIUM NITRIDE BASED SEMICONDUCTOR DEVICES - Gallium nitride (GaN) based semiconductor devices and methods of manufacturing the same. The GaN-based semiconductor device may include a heterostructure field effect transistor (HFET) or a Schottky diode, arranged on a heat dissipation substrate. The HFET device may include a GaN-based multi-layer having a recess region; a gate arranged in the recess region; and a source and a drain that are arranged on portions of the GaN-based multi-layer at two opposite sides of the gate (or the recess region). The gate, the source, and the drain may be attached to the heat dissipation substrate. The recess region may have a double recess structure. While such a GaN-based semiconductor device is being manufactured, a wafer bonding process and a laser lift-off process may be used. | 11-06-2014 |
20140346569 | Gate Voltage Control for III-Nitride Transistors - A semiconductor die includes a III-nitride semiconductor substrate, a power HEMT (high-electron-mobility transistor) disposed in the III-nitride semiconductor substrate, and a first gate driver HEMT monolithically integrated with the power HEMT in the III-nitride semiconductor substrate. The power HEMT and the first gate driver HEMT each have a gate, a source and a drain. The first gate driver HEMT logically forms part of a driver, and is electrically connected to the gate of the power HEMT. The first gate driver HEMT is operable to turn the power HEMT off or on responsive to an externally-generated control signal received from the driver or other device. Additional embodiments of semiconductor dies and methods of manufacturing are also described. | 11-27-2014 |
20140346570 | SEMICONDUCTOR DEVICE - A semiconductor device having high breakdown withstand voltage includes a first element which is a normally-on type transistor made of nitride compound semiconductor, a second element which is connected to the first element in series and is a transistor having withstand voltage between a source and a drain lower than withstand voltage of the first element, a first diode which is connected between a gate of the first element or a gate of the second element and a drain of the first element so that a cathode of the first diode is connected at the drain's side and has predetermined avalanche withstand voltage, and a first resistance connected to the gate to which the first diode is connected. The avalanche withstand voltage of the first diode is lower than breakdown voltage of the first element. | 11-27-2014 |
20140353724 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes: a semiconductor substrate having an upper surface and a lower surface; a field effect transistor having a semiconductor layer on the upper surface of the semiconductor substrate, a gate electrode, a drain electrode, and a source electrode; a P-type diffusion region in the semiconductor substrate and extending to the upper surface of the semiconductor substrate; a first N-type diffusion region in the semiconductor substrate and extending t the upper surface of the semiconductor substrate; a first connection electrode connecting the P-type diffusion region to a grounding point; and a second connection electrode connecting the first N-type diffusion region to the gate electrode or the drain electrode. The P-type diffusion region and the first N-type diffusion region constitute a bidirectional lateral diode. | 12-04-2014 |
20140367744 | Monolithic Integrated Composite Group III-V and Group IV Semiconductor Device and IC - There are disclosed herein various implementations of a monolithic vertically integrated composite device. Such a composite device may include one or more group IV device fabricated in a group IV semiconductor body formed over a first side of a double sided substrate, and one or more group III-V device fabricated in a group III-V semiconductor body formed over a second side of the double sided substrate opposite the first side. In one implementation, the one or more group IV device may be a PN junction diode or a Schottky diode. In another implementation, the one or more group IV device may be a field-effect transistor (PET). In yet another implementation, such a composite device monolithically integrates one or more group III-V device and a group IV integrated circuit (IC). The one or more group III-V device and one or more group IV device and/or IC may be electrically coupled using one or more of a substrate via and a through-wafer via. | 12-18-2014 |
20140374801 | SEMICONDUCTOR DEVICE - A semiconductor device according to one embodiment is provided with a first metal substrate, a second metal substrate separated from the first metal substrate, a normally-off transistor of a silicon semiconductor provided on the first metal substrate, and a normally-on transistor of a nitride semiconductor provided on the second metal substrate. | 12-25-2014 |
20150028391 | COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A compound semiconductor device includes a substrate, a p-type first semiconductor layer over the substrate and contains antimony, a p-type second semiconductor layer over the first semiconductor layer and contains antimony, an n-type third semiconductor layer over the second semiconductor layer, a fourth semiconductor layer between the first semiconductor layer and the second semiconductor layer, the fourth semiconductor layer containing phosphorus and having a thickness in which electrons tunnel between the first semiconductor layer and the second semiconductor layer, a first electrode in ohmic contact with the first semiconductor layer, and a second electrode in ohmic contact with the third semiconductor layer. The first semiconductor layer is made from a material whose contact resistance with the first electrode is lower than contact resistance of the second semiconductor layer. | 01-29-2015 |
20150054036 | Gallium Arsenide Based Device Having Non-Gold Ohmic Contacts - A device includes a semiconductor die. The semiconductor die includes a plurality of semiconductor layers disposed on a GaAs substrate, including a first semiconductor layer having a first band-gap and a second semiconductor layer having a second band-gap. The semiconductor die further includes a contact layer disposed epitaxially upon the first semiconductor layer. The contact layer has a thickness that is less than a critical thickness. The second semiconductor layer is epitaxially disposed upon the contact layer. The contact layer has a third band-gap that is less than the first band-gap and the second band-gap. The semiconductor die further includes a conductive layer disposed upon the contact layer to form an ohmic contact. The conductive layer comprises one or more metal layers compatible with silicon processing techniques. | 02-26-2015 |
20150318276 | GROUP III NITRIDE INTEGRATION WITH CMOS TECHNOLOGY - A method of forming a structure that can be used to integrate Si-based devices, i.e., nFETs and pFETs, with Group III nitride-based devices is provided. The method includes providing a substrate containing an nFET device region, a pFET device region and a Group III nitride device region, wherein the substrate includes a topmost silicon layer and a <111> silicon layer located beneath the topmost silicon layer. Next, a trench is formed within the Group III nitride device region to expose a sub-surface of the <111> silicon layer. The trench is then partially filled with a Group III nitride base material, wherein the Group III nitride material base material has a topmost surface that is coplanar with, or below, a topmost surface of the topmost silicon layer. | 11-05-2015 |
20150325566 | Composite Device with Integrated Diode - There are disclosed herein various implementations of composite semiconductor devices. In one implementation, such a composite semiconductor device includes a transition body formed over a diode, the transition body including more than one semiconductor layer. The composite semiconductor device also includes a transistor formed over the transition body. The diode may be connected across the transistor using through-semiconductor vias, external electrical connectors, or a combination of the two. | 11-12-2015 |
20150340380 | INTEGRATED CIRCUIT INCLUDING A SEMICONDUCTOR-ON-INSULATOR REGION AND A BULK REGION - A structure comprises a semiconductor substrate, a semiconductor-on-insulator region and a bulk region. The semiconductor-on-insulator region comprises a first semiconductor region, a dielectric layer provided between the semiconductor substrate and the first semiconductor region, and a first transistor comprising an active region provided in the first semiconductor region. The dielectric layer provides electrical isolation between the first semiconductor region and the semiconductor substrate. The bulk region comprises a second semiconductor region provided directly on the semiconductor substrate. | 11-26-2015 |
20150371982 | Composite Group III-V and Group IV Transistor Having a Switched Substrate - There are disclosed herein various implementations of a group III-V composite transistor having a switched substrate. Such a group III-V composite transistor includes a composite field-effect transistor (FET) including a depletion mode group III-V high electron mobility transistor (HEMT) situated over a substrate. The depletion mode group III-V HEMT is cascoded with an enhancement mode group IV FET to produce the composite FET. The group III-V composite transistor also includes a transistor configured to selectably couple the substrate of the depletion mode group III-V HEMT to ground and to selectably decouple the substrate from ground. That transistor is configured to ground the substrate when the depletion mode group III-V HEMT is in an off-state and to cause the substrate to float when the depletion mode group III-V HEMT is in an on-state. | 12-24-2015 |
20150371986 | Group III-V HEMT Having a Selectably Floating Substrate - There are disclosed herein various implementations of a group III-V high electron mobility transistor (HEMT) having a selectably floating substrate. Such a group III-V HEMT is situated over a substrate, and includes a transistor configured to selectably couple the substrate to ground and to selectably decouple the substrate from ground. The transistor is configured to ground the substrate when the group III-V HEMT is in an off-state and to cause the substrate to float when the group III-V HEMT is in an on-state. | 12-24-2015 |
20150372096 | High Electron Mobility Transistors and Integrated Circuits with Improved Feature Uniformity and Reduced defects for Microwave and Millimetre Wave Applications - High mobility transistors and microwave integrated circuits with an improved uniformity of the width of the smallest of features, an increased lithographic yield and reduced defects in the active components are provided. Before and during fabrication, a first grooving process is performed to partially or completely remove composite epitaxial layers in the field lanes to reduce the initial bow to be smaller than DOF range and to improve the uniformity of the critical dimension. A second grooving process may also be performed to remove composite epitaxial layers in the dicing lanes to further improve the uniformity of the width of the smallest features for the devices and circuits to be made. | 12-24-2015 |
20160035719 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Both a HEMT and a SBD are formed on a nitride semiconductor substrate. The nitride semiconductor substrate comprises a HEMT gate structure region and an anode electrode region. A first laminated structure is formed at least in the HEMT gate structure region, and includes first to third nitride semiconductor layers. A second laminated structure is formed at least in a part of the anode electrode region, and includes first and second nitride semiconductor layers. The anode electrode contacts the front surface of the second nitride semiconductor layer. At least in a contact region in which the front surface of the second nitride semiconductor layer contacts the anode electrode, the front surface of the second nitride semiconductor layer is finished to be a surface by which the second nitride semiconductor layer forms a Schottky junction with the anode electrode. | 02-04-2016 |
20160104697 | Compact High-Voltage Semiconductor Package - There are disclosed herein various implementations of a compact high-voltage semiconductor package. In one exemplary implementation, such a semiconductor package includes a power transistor, as well as a drain contact, a source contact, and a gate contact to provide external connections to the power transistor. The semiconductor package also includes a contour element formed between the drain contact and the source contact in the semiconductor package. The contour element increases a creepage distance between the drain contact and the source contact in the semiconductor package so as to increase a breakdown voltage of the semiconductor package. | 04-14-2016 |
20160118490 | HETEROJUNCTION SEMICONDUCTOR DEVICE HAVING INTEGRATED CLAMPING DEVICE - In one embodiment, a group III-V transistor structure includes a heterostructure disposed on a semiconductor substrate. A first current carrying electrode and a second current carrying electrode are disposed adjacent a major surface of the heterostructure and a control electrode is disposed between the first and second current carrying electrode. A clamping device is integrated with the group III-V transistor structure and is electrically connected to the first current carrying electrode a third electrode to provide a secondary current path during, for example, an electrical stress event. | 04-28-2016 |
20160163695 | Integrated Circuit Comprising Group III-N Transistors Monolithically Integrated on a Silicon Substrate and a Method for Manufacturing Thereof - An integrated circuit comprising a first III-N transistor having a source region and a second III-N transistor having a source region, both transistors being monolithically integrated on a common silicon substrate of a first doping type and separated from each-other by an isolation region, the substrate comprising underneath the first transistor a well of a first doping type electrically connected to the source region of the first transistor and comprising underneath the second transistor a well of a second doping type electrically connected to the source region of the second transistor, thereby forming a junction diode in the substrate between the sources of the first and the second transistor. | 06-09-2016 |
20160163718 | SEMICONDUCTOR DEVICES INCLUDING A DUMMY GATE STRUCTURE ON A FIN - Semiconductor devices including a dummy gate structure on a fin are provided. A semiconductor device includes a fin protruding from a substrate. The semiconductor device includes a source/drain region in the fin, and a recess region of the fin that is between first and second portions of the source/drain region. Moreover, the semiconductor device includes a dummy gate structure overlapping the recess region, and a spacer that is on the fin and adjacent a sidewall of the dummy gate structure. | 06-09-2016 |
20160172493 | INTEGRATED CIRCUITS WITH DUAL SILICIDE CONTACTS AND METHODS FOR FABRICATING SAME | 06-16-2016 |
20160197186 | FINFET WITH DIELECTRIC ISOLATION AFTER GATE MODULE FOR IMPROVED SOURCE AND DRAIN REGION EPITAXIAL GROWTH | 07-07-2016 |
20160204217 | DEVICES WITH FULLY AND PARTIALLY SILICIDED GATE STRUCTURES IN GATE FIRST CMOS TECHNOLOGIES | 07-14-2016 |
20190148378 | HIGH-MOBILITY SEMICONDUCTOR SOURCE/DRAIN SPACER | 05-16-2019 |