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Doping on side of heterojunction with lower carrier affinity (e.g., high electron mobility transistor (HEMT))

Subclass of:

257 - Active solid-state devices (e.g., transistors, solid-state diodes)

257183000 - HETEROJUNCTION DEVICE

257192000 - Field effect transistor

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Class / Patent application numberDescriptionNumber of patent applications / Date published
257195000 Combined with diverse type device 22
Entries
DocumentTitleDate
20120168822SEMICONDUCTOR DEVICE AND FABRICATION METHOD OF THE SEMICONDUCTOR DEVICE - A semiconductor device and a fabrication method of the semiconductor device, the semiconductor device including: a substrate; a nitride based compound semiconductor layer placed on the substrate and doped with a first transition metal atom; an aluminum gallium nitride layer (Al07-05-2012
20090078966Field-effect transistor, semiconductor chip and semiconductor device - A FET exhibiting excellent uniformity and productivity and having a low noise figure and high associated gain as high-frequency performance, a semiconductor chip having this FET and a semiconductor device having the semiconductor chip. The FET includes a GaAs substrate on which are built up an i-type GaAs layer, an i-type InGaAs two-dimensional electron gas layer and an n-type AlGaAs electron supply layer. A gate electrode is provided on and in linear Schottky contact with the n-type AlGaAs electron supply layer. A n-type InGaP etching stop layer and then an n-type GaAs contact layer at the same lateral position are built up on the n-type AlGaAs electron supply layer, these being spaced away from both sides of the gate electrode. A source electrode and a drain electrode are provided on the n-type GaAs contact layer and are spaced away from edges of the contact layer as electrodes that make band-shaped ohmic contact.03-26-2009
20130075788SEMICONDUCTOR DEVICE AND FABRICATION METHOD - A method for fabricating a semiconductor device is disclosed. The method includes sequentially forming a first semiconductor layer, a second semiconductor layer and a semiconductor cap layer containing a p-type impurity element on a substrate, forming a dielectric layer having an opening after the forming of the semiconductor cap layer, forming a third semiconductor layer containing a p-type impurity element on the semiconductor cap layer exposed from the opening of the dielectric layer, and forming a gate electrode on the third semiconductor layer.03-28-2013
20130075789SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device, comprising: a first semiconductor layer disposed on a substrate; a second semiconductor layer disposed on the first semiconductor layer; a lower insulating film disposed on the second semiconductor layer; a p-type electroconductive oxide film disposed on the lower insulating film; an upper insulating film disposed on the oxide film; and a gate electrode disposed on the upper insulating film, wherein the lower insulating film under the gate electrode has a depressed portion.03-28-2013
20120175680ENHANCEMENT MODE GALLIUM NITRIDE POWER DEVICES - Enhancement mode III-nitride devices are described. The 2DEG is depleted in the gate region so that the device is unable to conduct current when no bias is applied at the gate. Both gallium face and nitride face devices formed as enhancement mode devices.07-12-2012
20120175679Single structure cascode device - A novel semiconductor power transistor is presented. The semiconductor structure is simple and is based on a MOS configuration with a drift region and an additional gate that modulates the carrier density in the drift region, so that the control on the carrier transport is enhanced and the specific on-resistance per area is reduced. This characteristic enables the use of short gate lengths while maintaining the electric field under the gate within reasonable values in high voltage applications, without increasing the device on-resistance. It offers the advantage of extremely lower on-resistance for the same silicon area while improving on its dynamic performances with respect to the standard CMOS technology. Another inherent advantage is that the switching gate losses are smaller due to lower V07-12-2012
20130075790SEMICONDUCTOR INCLUDING LATERAL HEMT - A semiconductor including a lateral HEMT and to a method for production of a lateral HEMT is disclosed. In one embodiment, the lateral HEMT has a substrate and a first layer, wherein the first layer has a semiconductor material of a first conduction type and is arranged at least partially on the substrate. Furthermore, the lateral HEMT has a second layer, wherein the second layer has a semiconductor material and is arranged at least partially on the first layer. In addition, the lateral HEMT has a third layer, wherein the third layer has a semiconductor material of a second conduction type, which is complementary to the first conduction type, and is arranged at least partially in the first layer.03-28-2013
20130032860HFET with low access resistance - A novel semiconductor power transistor is presented. The semiconductor structure is simple and is based on a Hetero-structure FET structure, where the access regions have been eliminated so as to effectively obtain a lower specific on-resistance, and a higher control on the transport properties of the device, drastically reducing the dispersion phenomena associated with these regions. The present invention can be realized both with polar and non-polar (or semi-polar) materials, without requiring delta doping implantation. It can be fabricated as an enhancement or depletion mode device with much higher control on the device threshold voltage with respect to state-of-the-art HFET devices, and achieving superior RF switching performance. Furthermore, due to the absence of access regions, enhancement mode devices can be realized without discontinuity in the channel conductivity, which results in an even lower on-resistance.02-07-2013
20130075787COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - An embodiment of a compound semiconductor device includes: a substrate; a compound semiconductor stacked structure formed over the substrate; and a gate electrode, a source electrode and a drain electrode formed on or above the compound semiconductor stacked structure. The compound semiconductor stacked structure includes: an electron channel layer; and a nitride semiconductor layer which includes an electron supply layer formed over the electron channel layer. An indium (In) fraction at a surface of the nitride semiconductor layer in each of a region between the gate electrode and the source electrode and a region between the gate electrode and the drain electrode is lower than an indium (In) fraction at a surface of the nitride semiconductor layer in a region below the gate electrode.03-28-2013
20130075785SEMICONDUCTOR DEVICE AND FABRICATION METHOD - A semiconductor device includes a first semiconductor layer formed on a substrate, the first semiconductor containing an impurity element; a second semiconductor layer formed on the first semiconductor layer; a third semiconductor layer formed on the second semiconductor layer; and a gate electrode, a source electrode and a drain electrode that are formed on the third semiconductor layer. In the semiconductor device, the second semiconductor layer includes an impurity diffusion region in which an impurity element contained in the first semiconductor layer is diffused, the impurity diffusion region being located directly beneath the gate electrode and being in contact with the first semiconductor layer, and the impurity element causes the impurity diffusion region to be a p-type impurity diffusion region.03-28-2013
20130075786SEMICONDUCTOR DEVICE - A semiconductor device including a high resistance layer formed on a substrate, the high resistance layer being formed with a semiconductor material doped with an impurity element that makes the semiconductor material highly resistant; a multilayer intermediate layer formed on the high resistance layer; an electron transit layer formed with a semiconductor material on the multilayer intermediate layer; and an electron supply layer formed with a semiconductor material on the electron transit layer, wherein the multilayer intermediate layer is formed with a multilayer film in which a GaN layer and an AlN layer are alternately laminated.03-28-2013
20100032717DEVICES BASED ON SI/NITRIDE STRUCTURES - A nitride-based semiconductor device is provided. The nitride-base semiconductor device includes a substrate comprising one or more locally etched regions and a buffer layer comprising one or multiple InAlGaN layers on the substrate. A channel layer includes GaN on the buffer layer. A barrier layer includes one or multiple AlGaN layers on the channel layer.02-11-2010
20130082305STRUCTURE OF A HIGH ELECTRON MOBILITY TRANSISTOR AND A FABRICATION METHOD THEREOF - An improved structure of the high electron mobility transistor (HEMT) and a fabrication method thereof are disclosed. The improved HEMT structure comprises a substrate, a channel layer, a spacing layer, a carrier supply layer, a Schottky layer, a first etch stop layer, a first n type doped layer formed by Al04-04-2013
20100102359 NOVEL FABRICATION TECHNIQUE FOR HIGH FREQUENCY, HIGH POWER GROUP III NITRIDE ELECTRONIC DEVICES - Fabrication methods of a high frequency (sub-micron gate length) operation of AlInGaN/InGaN/GaN MOS-DHFET, and the HFET device resulting from the fabrication methods, are generally disclosed. The method of forming the HFET device generally includes a novel double-recess etching and a pulsed deposition of an ultra-thin, high-quality silicon dioxide layer as the active gate-insulator. The methods of the present invention can be utilized to form any suitable field effect transistor (FET), and are particular suited for forming high electron mobility transistors (HEMT).04-29-2010
20100096667SEMICONDUCTOR DEVICE - There is provided a technique for reducing the occurrence of higher harmonics which occur from a field effect transistor, particularly a field effect transistor configuring a switching element of an antenna switch. In a transistor having a meander structure, the gate width of a partial transistor closest to a gate input side is increased. More specifically, a comb-like electrode is made longer than the other comb-like electrodes. In other words, a finger length is made greater than any other finger length. In particular, the comb-like electrode has the greatest length in all the comb-like electrodes.04-22-2010
20090159930High electron mobility transistor having self-aligned miniature field mitigating plate and protective dielectric layer and fabrication method thereof - A semiconductor device is fabricated to include source and drain contacts including an ohmic metal sunken into the barrier layer and a portion of the channel layer; a protective dielectric layer disposed between the source and drain contacts on the barrier layer; a metallization layer disposed in drain and source ohmic vias between the source contact and the protective dielectric layer and between the protective dielectric layer and the drain contact; and a metal T-gate disposed above the barrier layer including a field mitigating plate disposed on a side portion of a stem of the metal T-gate.06-25-2009
20130126943FIELD-EFFECT TRANSISTOR - An insulator is formed on the upper surface of a first semiconductor layer on at least a part of a portion above which a second semiconductor layer is not formed due to an opening. In the opening, a source electrode is formed to cover an insulator. The source electrode is formed to be in contact with an interface between the first semiconductor layer and the second semiconductor layer.05-23-2013
20100109051HIGH VOLTAGE GAN TRANSISTORS - A multiple field plate transistor includes an active region, with a source, a drain, and a gate. A first spacer layer is over the active region between the source and the gate and a second spacer layer over the active region between the drain and the gate. A first field plate on the first spacer layer is connected to the gate. A second field plate on the second spacer layer is connected to the gate. A third spacer layer is on the first spacer layer, the second spacer layer, the first field plate, the gate, and the second field plate, with a third field plate on the third spacer layer and connected to the source. The transistor exhibits a blocking voltage of at least 600 Volts while supporting a current of at least 2 Amps with an on resistance of no more than 5.0 mΩ-cm05-06-2010
20100109050FIELD EFFECT TRANSISTOR WITH INDEPENDENTLY BIASED GATES - A field effect transistor (FET) having at least two independently biased gates can provide uniform electric field in the channel region of the FET. The same AC voltage may be applied to each gate for modulating the FET. One of the gates is positioned closer to the channel region than the other gate. Such a FET allows tailoring the electric field in the channel region of the FET so that it is substantially uniform. The FET exhibits desirable performance characteristics, including having a constant transconductance.05-06-2010
20130082306ENHANCEMENT OF CHARGE CARRIER MOBILITY IN TRANSISTORS - Transistor devices including stressors are disclosed. One such transistor device includes a channel region, a dielectric layer and a semiconductor substrate. The channel region is configured to provide a conductive channel between a source region and a drain region. In addition, the dielectric layer is below the channel region and is configured to electrically insulate the channel region. Further, the semiconductor substrate, which is below the channel region and below the dielectric layer, includes dislocation defects at a top surface of the semiconductor substrate, where the dislocation defects are collectively oriented to impose a compressive strain on the channel region such that charge carrier mobility is enhanced in the channel region.04-04-2013
20100025730Normally-off Semiconductor Devices and Methods of Fabricating the Same - Normally-off semiconductor devices are provided. A Group III-nitride buffer layer is provided. A Group III-nitride barrier layer is provided on the Group III-nitride buffer layer. A non-conducting spacer layer is provided on the Group III-nitride barrier layer. The Group III-nitride barrier layer and the spacer layer are etched to form a trench. The trench extends through the barrier layer and exposes a portion of the buffer layer. A dielectric layer is formed on the spacer layer and in the trench and a gate electrode is formed on the dielectric layer. Related methods of forming semiconductor devices are also provided herein.02-04-2010
20090045439Heterojunction field effect transistor and manufacturing method thereof - A heterojunction field effect transistor includes a laminated body. The laminated body includes a channel layer of GaN, an electron supply layer of AlN or Al02-19-2009
20120217547FIELD EFFECT TRANSISTOR WITH REDUCED GATE LEAKAGE CURRENT - Disclosed is an HJFET 08-30-2012
20120217546SEMICONDUCTOR DEVICE - An aspect of the present invention inheres in a semiconductor device includes a semiconductor region, a source electrode and a drain electrode, which are provided on a main surface of the semiconductor region, a gate electrode exhibiting normally-off characteristics, the gate electrode being provided above the main surface of the semiconductor region while interposing a p-type material film therebetween, and being arranged between the source electrode and the drain electrode, and a fourth electrode that is provided on the main surface of the semiconductor region, and is arranged between the gate electrode and the drain electrode.08-30-2012
20120217544COMPOUND SEMICONDUCTOR DEVICE - A compound semiconductor device includes a nitride semiconductor stacked structure including a carrier transit layer and a carrier supply layer; a source electrode and a drain electrode provided over the nitride semiconductor stacked structure; a gate electrode provided between the source electrode and the drain electrode, over the nitride semiconductor stacked structure; a field plate provided at least partially between the gate electrode and the drain electrode; and a plurality of insulation films and formed over the nitride semiconductor stacked structure, wherein a number of interfaces of the plurality of insulation films is smaller between the field plate and the drain electrode than in the vicinity of the gate electrode.08-30-2012
20110057234Semiconductor device and method for manufacturing of the same - Disclosed is a semiconductor device including: a base substrate; a semiconductor layer disposed on the base substrate; an ohmic electrode part which has ohmic electrode lines disposed in a first direction, on the semiconductor layer; and a Schottky electrode part which is disposed to be spaced apart from the ohmic electrode lines on the semiconductor layer and includes Schottky electrode lines disposed in the first direction, wherein the Schottky electrode lines and the ohmic electrode lines are alternately disposed in parallel, and the ohmic electrode part further includes first ohmic electrodes covered by the Schottky electrode lines on the semiconductor layer.03-10-2011
20130056797SEMICONDUCTOR DEVICE HAVING SCHOTTKY DIODE STRUCTURE - A semiconductor device including a base substrate; a semiconductor layer which is disposed on the base substrate and has a 2-Dimensional Electron Gas (2DEG) generated within the semiconductor layer; a plurality of first ohmic electrodes which are disposed on the central region of the semiconductor layer and have island-shaped cross sections; a second ohmic electrode which is disposed on edge regions of the semiconductor layer; and a Schottky electrode part has first bonding portions bonded to the first ohmic electrodes, and a second bonding portion bonded to the semiconductor layer. A depletion region is provided to be spaced apart from the 2DEG when the semiconductor device is driven at an on-voltage and is provided to be expanded to the 2DEG when the semiconductor device is driven at an off-voltage, the depletion region being generated within the semiconductor layer by bonding the semiconductor layer and the second bonding portion.03-07-2013
20090267115CLUB EXTENSION TO A T-GATE HIGH ELECTRON MOBILITY TRANSISTOR - A method of fabricating a T-gate HEMT with a club extension comprising the steps of: providing a substrate; providing a bi-layer resist on the substrate; exposing an area of the bi-layer resist to electron beam lithography where the area corresponds to a T-gate opening; exposing an area of the bi-layer resist to electron beam lithography where the area corresponds to the shape of the club extension wherein the area corresponding to the club extension is approximately 1 micron to an ohmic source side of a T-gate and approximately 0.5 microns forward from a front of the T-gate; developing out the bi-layer resist in the exposed area that corresponds to the T-gate opening; developing out the bi-layer resist in the exposed area that corresponds to the club extension; and forming the T-gate and club extension through a metallization process.10-29-2009
20130062666COMPOUND SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A compound semiconductor device includes a substrate; and a compound semiconductor layer disposed over the substrate, wherein the compound semiconductor layer includes a first region having first conductivity-type carriers generated by activating a first impurity and also includes a second region having carriers at lower concentration as compared to the first region, the carriers being generated by activating a second impurity which is the same type as the first impurity.03-14-2013
20090236635WIDE BANDGAP HEMTS WITH SOURCE CONNECTED FIELD PLATES - A HEMT comprising an active region comprising a plurality of active semiconductor layers formed on a substrate. Source electrode, drain electrode, and gate are formed in electrical contact with the active region. A spacer layer is formed on at least a portion of a surface of said active region and covering the gate. A field plate is formed on the spacer layer and electrically connected to the source electrode, wherein the field plate reduces the peak operating electric field in the HEMT.09-24-2009
20130069117NITRIDE SEMICONDUCTOR DEVICE - A nitride semiconductor device includes a substrate, a first In03-21-2013
20130069116METHOD OF FORMING A SEMICONDUCTOR STRUCTURE - A semiconductor structure is disclosed. The semiconductor structure includes a first layer. A second layer is disposed on the first layer and different from the first layer in composition. An interface is between the first layer and the second layer. A third layer is disposed on the second layer. A gate is disposed on the third layer. A source feature and a drain feature are disposed on opposite sides of the gate. Each of the source feature and the drain feature includes a corresponding metal feature at least partially embedded in the second and the third layer. A corresponding intermetallic compound underlies each metal feature. Each intermetallic compound contacts a carrier channel located at the interface.03-21-2013
20090008678SEMICONDUCTOR DEVICE - An electron supply layer (01-08-2009
20090008677COMPOUND SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - An AlN layer (01-08-2009
20090008676NORMALLY-OFF FIELD-EFFECT SEMICONDUCTOR DEVICE, AND METHOD OF FABRICATION - A normally-off HEMT is made by first providing a substrate having its surface partly covered with an antigrowth mask. Gallium nitride is grown by epitaxy on the masked surface of the substrate to provide an electron transit layer comprised of two flat-surfaced sections and a V-notch-surfaced section therebetween. The flat-surfaced sections are formed on unmasked parts of the substrate surface whereas the V-notch-surfaced section, defining a V-sectioned notch, is created by lateral overgrowth onto the antigrowth mask. Aluminum gallium nitride is then deposited on the electron transit layer to provide an electron supply layer which is likewise comprised of two flat-surfaced sections and a V-notch-surfaced section therebetween. The flat-surfaced sections of the electron supply layer are sufficiently thick to normally generate two-dimensional electron gas layers due to heterojunctions thereof with the first and the second flat-surfaced section of the electron transit layer. The V-notch-surfaced section of the electron supply layer is not so thick, normally creating an interruption in the two-dimensional electron gas layer.01-08-2009
20130161698E-MODE HFET DEVICE - The present invention describes a transistor based on a Hetero junction FET structure, where the metal gate has been replaced by a stack formed by a highly doped compound semiconductor and an insulating layer in order to achieve enhancement mode operation and at the same time drastically reduce the gate current leakage. The combination of the insulating layer with a highly doped semiconductor allows the tuning of the threshold voltage of the device at the desired value by simply changing the composition of the semiconductor layer forming the gate region and/or its doping allowing a higher degree of freedom. In one of the embodiment, a back-barrier layer and a heavily doped threshold tuning layer are used to suppress Short Channel Effect phenomena and to adjust the threshold voltage of the device at the desired value. The present invention can be realized both with polar and non-polar (or semi-polar) materials.06-27-2013
20120235210SEMICONDUCTOR DEVICE, MANUFACTURING METHOD AND TRANSISTOR CIRCUIT - A transistor circuit includes a first high electron mobility transistor and a second high electron mobility transistor having a negative threshold voltage, wherein a source of the second high electron mobility transistor is coupled to a gate of the first high electron mobility transistor, and a gate of the second high electron mobility transistor is coupled to a source of the first high electron mobility transistor.09-20-2012
20120235209High Voltage Rectifier and Switching Circuits - According to one exemplary embodiment, a rectifier circuit includes a diode. A first depletion-mode transistor is connected to a cathode of the diode. Also, at least one second depletion-mode transistor is in parallel with the first depletion-mode transistor and is configured to supply a pre-determined current range to a cathode of the diode. A pinch off voltage of the at least one second depletion-mode transistor can be more negative than a pinch off voltage of the first depletion-mode transistor and the at least one second depletion-mode transistor can be configured to supply the pre-determined current range while the first depletion-mode transistor is OFF. Also, the pre-determined current range can be greater than a leakage current of the first depletion-mode transistor.09-20-2012
20110278647III-NITRIDE SEMICONDUCTOR ELECTRONIC DEVICE, AND METHOD OF FABRICATING III-NITRIDE SEMICONDUCTOR ELECTRONIC DEVICE - A III-nitride semiconductor electronic device comprises a semiconductor laminate provided on a primary surface of a substrate, a first electrode in contact with the semiconductor laminate, and a second electrode. The semiconductor laminate includes a channel layer and a barrier layer making a junction with the channel layer. The channel layer comprises first III-nitride semiconductor containing aluminum as a Group III constituent element, and the barrier layer comprises second III-nitride semiconductor containing aluminum as a Group III constituent element. The semiconductor laminate including first, second and third regions arranged along the primary surface, and the third region is located between the first region and the second region. The barrier layer includes first to third portions included in the first to third regions, respectively. A concentration of impurity in the first portion is the same as that of impurity in the second portion, and the first and second electrodes is provided on the first and second regions, respectively. The first electrode includes a drain electrode or a source electrode. An aluminum composition of the first III-nitride semiconductor is not less than 0.16, and a bandgap of the second III-nitride semiconductor being larger than that of the first III-nitride semiconductor.11-17-2011
20080296622BURIED CHANNEL MOSFET USING III-V COMPOUND SEMICONDUCTORS AND HIGH k GATE DIELECTRICS - A semiconductor-containing heterostructure including, from bottom to top, a III-V compound semiconductor buffer layer, a III-V compound semiconductor channel layer, a III-V compound semiconductor barrier layer, and an optional, yet preferred, III-V compound semiconductor cap layer is provided. The barrier layer may be doped, or preferably undoped. The III-V compound semiconductor buffer layer and the III-V compound semiconductor barrier layer are comprised of materials that have a wider band gap than that of the III-V compound semiconductor channel layer. Since wide band gap materials are used for the buffer and barrier layer and a narrow band gap material is used for the channel layer, carriers are confined to the channel layer under certain gate bias range. The inventive heterostructure can be employed as a buried channel structure in a field effect transistor.12-04-2008
20110073912AlGaN/GaN hemt with normally-off threshold minimized and method of manufacturing the same - In a method of forming a gate recess, on a surface of an epitaxial wafer including an epitaxial substrate, having a semiconductor layer having the band gap energy varying therein in the depth-wise direction, and a SiN surface protective layer, having a sidewall forming a gate opening and coating the surface of the epitaxial substrate, ultraviolet light having its energy equivalent to the band gap energy of the specific semiconductor layer is irradiated, while the specific semiconductor layer is photoelectrochemically etched from the gate opening with the SiN surface protective layer used as a mask. The gate recess free from plasma ion-induced damage is thus obtained.03-31-2011
20110140174COMPOUND SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREOF - A compound semiconductor device is comprised of: a compound semiconductor layer including a first active layer and a second active layer forming a hetero junction with the first active layer so as to naturally generate a two-dimensional carrier gas channel in the first active layer along the hetero junction; a first electrode formed on the second active layer; a second electrode in ohmic contact with the first active layer and isolated from the first electrode; and a channel modifier for locally changing a part of the first active layer under the channel modifier into a normally-off state, the channel modifier being formed on the second active layer so as to enclose but be isolated from the first electrode and the second electrode.06-16-2011
20110140173Low OHMIC contacts containing germanium for gallium nitride or other nitride-based power devices - An apparatus includes a substrate, a Group III-nitride layer over the substrate, and an electrical contact over the Group III-nitride layer. The electrical contact includes a stack having multiple layers of conductive material, and at least one of the layers in the stack includes germanium. The layers in the stack may include a contact layer, where the contact layer includes aluminum copper. The stack could include a titanium or titanium alloy layer, an aluminum or aluminum alloy layer, and a germanium or germanium alloy layer. At least one of the layers in the stack could include an aluminum or titanium alloy having a germanium content between about 1% and about 5%.06-16-2011
20100171150METHODS OF FABRICATING TRANSISTORS INCLUDING DIELECTRICALLY-SUPPORTED GATE ELECTRODES AND RELATED DEVICES - Transistors are fabricated by forming a protective layer having a first opening extending therethrough on a substrate, forming a dielectric layer on the protective layer having a second opening extending therethrough that is wider than the first opening, and forming a gate electrode in the first and second openings. A first portion of the gate electrode laterally extends on surface portions of the protective layer outside the first opening, and a second portion of the gate electrode is spaced apart from the protective layer and laterally extends beyond the first portion on portions of the dielectric layer outside the second opening. Related devices and fabrication methods are also discussed.07-08-2010
20110291160FIELD EFFECT TRANSISTOR - A field effect transistor includes a nitride-based semiconductor multi-layer structure, a source electrode (12-01-2011
20110291159Stress release structures for metal electrodes of semiconductor devices - This invention teaches stress release metal electrodes for gate, drain and source in a field effect transistor and stress release metal electrodes for emitter, base and collector in a bipolar transistor. Due to the large difference in the thermal expansion coefficients between semiconductor materials and metal electrodes, significant strain and stresses can be induced in the devices during the fabrication and operation. The present invention provides metal electrode with stress release structures to reduce the strain and stresses in these devices.12-01-2011
20120098035Group III-N HEMT with an Increased Buffer Breakdown Voltage - The buffer breakdown of a group III-N HEMT on a p-type Si substrate is significantly increased by forming an n-well in the p-type Si substrate to lie directly below the metal drain region of the group III-N HEMT. The n-well forms a p-n junction which becomes reverse biased during breakdown, thereby increasing the buffer breakdown by the reverse-biased breakdown voltage of the p-n junction and allowing the substrate to be grounded. The buffer layer of a group III-N HEMT can also be implanted with n-type and p-type dopants which are aligned with the p-n junction to minimize any leakage currents at the junction between the substrate and the buffer layer.04-26-2012
20100264462SEMICONDUCTOR INCLUDING LATERAL HEMT - A semiconductor including a lateral HEMT and to a method for production of a lateral HEMT is disclosed. In one embodiment, the lateral HEMT has a substrate and a first layer, wherein the first layer has a semiconductor material of a first conduction type and is arranged at least partially on the substrate. Furthermore, the lateral HEMT has a second layer, wherein the second layer has a semiconductor material and is arranged at least partially on the first layer. In addition, the lateral HEMT has a third layer, wherein the third layer has a semiconductor material of a second conduction type, which is complementary to the first conduction type, and is arranged at least partially in the first layer.10-21-2010
20090242938Field effect transistor - A field effect transistor formed of a semiconductor of a III group nitride compound, includes an electron running layer formed on a substrate and formed of GaN; an electron supplying layer formed on the electron running layer and formed of Al10-01-2009
20120025271SEMICONDUCTOR WAFER, METHOD OF PRODUCING SEMICONDUCTOR WAFER, METHOD OF JUDGING QUALITY OF SEMICONDUCTOR WAFER, AND ELECTRONIC DEVICE - There is provided a high-performance compound semiconductor epitaxial wafer that has an improved linearity of the voltage-current characteristic, a producing method thereof, and a judging method thereof. Provided is a semiconductor wafer including a compound semiconductor that produces a two-dimensional carrier gas, a carrier supply semiconductor that supplies a carrier to the compound semiconductor, and a mobility lowering semiconductor that is disposed between the compound semiconductor and the carrier supply semiconductor and that has a mobility lowering factor that makes the mobility of the carrier in the mobility lowering semiconductor lower than the mobility of the carrier in the compound semiconductor.02-02-2012
20120025269SEMICONDUCTOR STRUCTURE COMPRISING PILLAR - A semiconductor structure comprises a substrate and a metal layer disposed over the substrate. The metal layer comprises a first electrical trace and a second electrical trace. The semiconductor structure comprises a conductive pillar disposed directly on and in electrical contact with the first electrical trace; and a dielectric layer selectively disposed between the metal layer and the conductive pillar. The dielectric layer electrically isolates the second electrical trace from the pillar.02-02-2012
20120228675HIGH TEMPERATURE PERFORMANCE CAPABLE GALLIUM NITRIDE TRANSISTOR - A transistor device capable of high performance at high temperatures. The transistor comprises a gate having a contact layer that contacts the active region. The gate contact layer is made of a material that has a high Schottky barrier when used in conjunction with a particular semiconductor system (e.g., Group-III nitrides) and exhibits decreased degradation when operating at high temperatures. The device may also incorporate a field plate to further increase the operating lifetime of the device.09-13-2012
20090146185INSULATED GATE E-MODE TRANSISTORS - Enhancement-mode III-nitride transistors are described that have a large source to drain barrier in the off state, low off state leakage, and low channel resistance in the access regions are described. The devices can include a charge depleting layer under the gate and/or a charge enhancing layer outside of the gate region, that is, in the access region.06-11-2009
20080237641Surrounded-Channel Transistors with Directionally Etched Gate or Insulator Formation Regions - An elongate stacked semiconductor structure is formed on a substrate. The stacked semiconductor structure includes a second semiconductor material region disposed on a first semiconductor material region. The first semiconductor material region is selectively doped to produce spaced-apart impurity-doped first semiconductor material regions and a lower dopant concentration first semiconductor material region therebetween. Etching exposes a portion of the second semiconductor material region between the impurity-doped first semiconductor material regions. The etching removes at least a portion of the lower dopant concentration first semiconductor material region to form a hollow between the substrate and the portion of the second semiconductor material region between the impurity-doped first semiconductor material regions. An insulation layer that surrounds the exposed portion of the second semiconductor material region between the impurity-doped first semiconductor material regions is formed. The hollow may be filled with a gate electrode that completely surrounds the exposed portion of the second semiconductor material region, or the gate electrode may partially surround the exposed portion of the second semiconductor material region and an insulation region may be formed in the hollow.10-02-2008
20080237639SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - The objective of the present invention is to provide a semiconductor device of a hetero-junction field effect transistor that is capable of obtaining a high output and a high breakdown voltage and a manufacturing method of the same.10-02-2008
20100038682ELECTRONIC DEVICES WITH IMPROVED OHMIC CONTACT - In one embodiment, the disclosure relates to an electronic device successively comprising from its base to its surface: (a) a support layer, (b) a channel layer adapted to contain an electron gas, (c) a barrier layer and (d) at least one ohmic contact electrode formed by a superposition of metallic layers, a first layer of which is in contact with the barrier layer. The device is remarkable in that the barrier layer includes a contact region under the ohmic contact electrode(s). The contact region includes at least one metal selected from the metals forming the superposition of metallic layers. Furthermore, a local alloying binds the contact region and the first layer of the electrode(s).02-18-2010
20100084687ALUMINUM GALLIUM NITRIDE/GALLIUM NITRIDE HIGH ELECTRON MOBILITY TRANSISTORS - Structures, devices and methods are provided for creating enhanced back barriers that improve the off-state breakdown and blocking characteristics in aluminum gallium nitride AlGaN/GaN high electron mobility transistors (HEMTs). In one aspect, selective fluorine ion implantation is employed when developing HEMTs to create the enhanced back barrier structures. By creating higher energy barriers at the back of the two-dimensional electron gas channel in the unintentionally doped GaN buffer, higher off-state breakdown voltage is advantageously provided and blocking capability is enhanced, while allowing for convenient and cost-effective post-epitaxial growth fabrication. Further non-limiting embodiments are provided that illustrate the advantages and flexibility of the disclosed structures.04-08-2010
20100117119SEMICONDUCTOR DEVICE HAVING HETERO JUNCTION - A semiconductor device 05-13-2010
20100084688ENHANCEMENT-MODE NITRIDE TRANSISTOR - A heterojunction for use in a transistor structure is provided. The heterojunction includes a barrier layer positioned beneath a gate region of the transistor structure. The barrier layer includes nitride-based semiconductor materials. A channel layer provides electrical conduction An intermediate layer near the barrier layer and including nitride-based semiconductor materials having a wider bandgap than the channel layer04-08-2010
20090206369HIGH ELECTRON MOBILITY TRANSISTOR SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - In a method of forming a semiconductor device on a semiconductor substrate (08-20-2009
20090206368Rhombohedral cubic semiconductor materials on trigonal substrate with single crystal properties and devices based on such materials - Growth conditions are developed, based on a temperature-dependent alignment model, to enable formation of cubic group IV, group II-V and group II-VI crystals in the [111] orientation on the basal (0001) plane of trigonal crystal substrates, controlled such that the volume percentage of primary twin crystal is reduced from about 40% to about 0.3%, compared to the majority single crystal. The control of stacking faults in this and other embodiments can yield single crystalline semiconductors based on these materials that are substantially without defects, or improved thermoelectric materials with twinned crystals for phonon scattering while maintaining electrical integrity. These methods can selectively yield a cubic-on-trigonal epitaxial semiconductor material in which the cubic layer is substantially either directly aligned, or 60 degrees-rotated from, the underlying trigonal material.08-20-2009
20090189190High Electron Mobility Transistor, Field-Effect Transistor, Epitaxial Substrate, Method of Manufacturing Epitaxial Substrate, and Method of Manufacturing Group III Nitride Transistor - Affords high electron mobility transistors having a high-purity channel layer and a high-resistance buffer layer. A high electron mobility transistor 07-30-2009
20100090251SURFACE TREATMENT AND PASSIVATION OF AIGaN/GaN HEMT - In the preferred embodiments, a method to reduce gate leakage and dispersion of group III-nitride field effect devices covered with a thin in-situ SiN layer is provided. This can be obtained by introducing a second passivation layer on top of the in-situ SiN-layer, in combination with cleaning of the in-situ SiN before gate deposition and before deposition of the second passivation layer.04-15-2010
20090267116WIDE BANDGAP TRANSISTORS WITH MULTIPLE FIELD PLATES - A transistor comprising a plurality of active semiconductor layers on a substrate, with source and drain electrodes in contact with the semiconductor layers. A gate is formed between the source and drain electrodes and on the plurality of semiconductor layers. A plurality of field plates are arranged over the semiconductor layers, each of which extends from the edge of the gate toward the drain electrode, and each of which is isolated from said semiconductor layers and from the others of the field plates. The topmost of the field plates is electrically connected to the source electrode and the others of the field plates are electrically connected to the gate or the source electrode.10-29-2009
20110024796EPITAXIAL SUBSTRATE FOR SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE, AND PROCESS FOR PRODUCING EPITAXIAL SUBSTRATE FOR SEMICONDUCTOR DEVICE - Provided is an epitaxial substrate having excellent two-dimensional electron gas characteristics and reduced internal stress due to strains. A channel layer is formed of a first group III nitride represented by In02-03-2011
20090261384GALLIUM NITRIDE HIGH ELECTRON MOBILITY TRANSISTOR HAVING INNER FIELD-PLATE FOR HIGH POWER APPLICATIONS - A gallium nitride high electron mobility transistor, in which an inner field-plate is disposed between the gate and drain of the high electron mobility transistor, so that an electric field is distributed between gate and drain regions to reduce a peak value and to reduce gate leakage current while maintaining high frequency performance, thus obtaining a high breakdown voltage, reducing the capacitance between the gate and the drain attributable to a shielding effect, and improving linearity and high power and high frequency characteristics through variation in the input voltage of the inner field-plate.10-22-2009
20110204418TERAHERTZ WAVE RADIATING ELEMENT - A terahertz wave radiating element includes: a first nitride semiconductor layer formed on a substrate; a second nitride semiconductor layer formed over the first nitride semiconductor layer, and having a wider bandgap than the first nitride semiconductor layer; and source, gate, and drain electrodes formed on the second nitride semiconductor layer. The source electrode is formed by a plurality of source electrode fingers that are arranged periodically, and the drain electrode is formed by a plurality of drain electrode fingers that are arranged periodically.08-25-2011
20080290372SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a substrate, a compound semiconductor layer formed over the substrate, and a protective insulating film composed of silicon nitride, which is formed over a surface of the compound semiconductor layer and whose film density in an intermediate portion is lower than that in a lower portion.11-27-2008
20080303064FIELD-EFFECT SEMICONDUCTOR DEVICE AND METHOD OF FABRICATION - After creating an electron transit layer on a substrate, a baffle is formed on midpart of the surface of the electron transit layer, the surface having a pair of spaced-apart parts left on both sides of the baffle. A semiconducting material different from that of the electron transit layer is deposited on its surface thereby conjointly fabricating an electron supply layer grown continuously on the pair of spaced-apart parts of the electron transit layer surface, and a discontinuous growth layer on the baffle in the midpart of the electron transit layer surface. When no voltage is being impressed to the gate electrode on the discontinuous growth layer, this layer creates a hiatus in the two-dimensional electron gas layer generated along the heterojunction between the electron supply layer and electron transit layer. The hiatus is closed upon voltage application to the gate electrode.12-11-2008
20120292665High performance multigate transistor - A novel semiconductor power transistor is presented. The semiconductor structure is simple and is based on a FET structure, where multiple channels and multiple gate regions are formed in order to achieve a lower specific on-resistance, and a higher control on the transport properties of the device. No dielectric layer is present between gate electrodes and device channels, decreasing the parasitic capacitance associated with the gate terminal. The fabrication of the device does not require Silicon On Insulator techniques and it is not limited to Silicon semiconductor materials. It can be fabricated as an enhancement or depletion device with much more control on the threshold voltage of the device, and with superior RF performance.11-22-2012
20080283870FIELD-EFFECT SEMICONDUCTOR DEVICE - A HEMT-type field-effect semiconductor device has a main semiconductor region comprising two layers of dissimilar materials such that a two-dimensional electron gas layer is generated along the heterojunction between the two layers. A source and a drain electrode are placed in spaced positions on the main semiconductor region. Between these electrodes, with spacings therefrom, an insulator is provided with is made from a material capable of developing a stress to reduce carrier concentration in neighboring part of the two-dimensional electron gas layer, creating a discontinuity in this layer. A gate electrode overlies the insulator via a piezoelectric layer which is made from a material capable of developing, in response to a voltage applied to the gate electrode, a stress for canceling out the stress developed by the insulator. Thus the device is physically held off by the action of the insulator while no voltage is being impressed to the gate electrode and, upon voltage application thereto, piezoelectrically turns on by the action of the piezoelectric layer. The turn-on resistance of the device is relatively low as the insulator occupies only part of the source-drain spacing.11-20-2008
20120043588SEMICONDUCTOR DEVICE - A semiconductor device includes: a first semiconductor layer; a second semiconductor layer; a two-dimensional carrier gas layer; a source electrode; a drain electrode; a gate electrode; and an auxiliary electrode located above the two-dimensional carrier gas layer between the gate electrode and the drain electrode. Channel resistance of the two-dimensional carrier gas layer between the gate electrode and the auxiliary electrode is set higher than channel resistance of the two-dimensional carrier gas layer between the gate electrode and the source electrode.02-23-2012
20090085065METHOD TO FABRICATE III-N SEMICONDUCTOR DEVICES ON THE N-FACE OF LAYERS WHICH ARE GROWN IN THE III-FACE DIRECTION USING WAFER BONDING AND SUBSTRATE REMOVAL - A method for fabricating III-N semiconductor devices on the N-face of layers comprising (a) growing a III-nitride semiconductor device structure in a Ga-polar direction on a substrate, (b) attaching a Ga face of the III-nitride semiconductor device structure to a host substrate, and (c) removing the substrate to expose the N-face surface of the III-nitride semiconductor device structure. An N-polar (000-1) oriented III-nitride semiconductor device is also disclosed, comprising one or more (000-1) oriented nitride layers, each having an N-face opposite a group III-face, wherein at least one N-face is an at least partially exposed N-face, and a host substrate attached to one of the group III-faces.04-02-2009
20100140664Methods of Fabricating Nitride-Based Transistors with a Cap Layer and a Recessed Gate and Related Devices - An anneal of a gate recess prior to formation of a gate contact, such as a Schottky contact, may reduce gate leakage and/or provide a high quality gate contact in a semiconductor device, such as a transistor. The use of an encapsulation layer during the anneal may further reduce damage to the semiconductor in the gate recess of the transistor. The anneal may be provided, for example, by an anneal of ohmic contacts of the device. Thus, high quality gate and ohmic contacts may be provided with reduced degradation of the gate region that may result from providing a recessed gate structure as a result of etch damage in forming the recess.06-10-2010
20090085064HETEROJUNCTION SEMICONDUCTOR DEVICE AND METHOD - A semiconductor device includes a first semiconductor substrate of a first band-gap material and a second semiconductor substrate of a second band-gap material. The second band-gap material has a lower band-gap than the first band-gap material. A heterojunction is formed between the first semiconductor substrate and the second semiconductor substrate substantially in a first plane. The semiconductor device further includes, in a cross-section which is perpendicular to the first plane, a first semiconductor region of a first conductivity type and a second semiconductor region of the first conductivity type both of which extend from the second semiconductor substrate at least partially into the first semiconductor substrate. The first and second semiconductor regions are spaced in the first semiconductor substrate from each other in a direction parallel to the first plane by a first distance which is arranged in an area proximate to the heterojunction and which is larger than a second distance which is arranged in an area distal to the heterojunction.04-02-2009
20100193841METHOD FOR FORMING RESIST PATTERN AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - The resist material contains a photo-acid generator having an absorption peak to exposure light having a wavelength of less than 300 nm, and a second photo-acid generator having an absorption peak to exposure light having a wavelength of 300 nm or more. The method for forming a resist pattern comprises a step for selectively exposing which exposes a coating film of the resist material to an exposure light having a wavelength of less than 300 nm, and a step for selectively exposing by using an exposure light having a wavelength of 300 nm or more. The semiconductor device comprises a pattern formed by the resist pattern. The method for forming a semiconductor device comprises a step for forming a resist pattern on an underlying layer by the aforementioned manufacturing method, and a step for patterning the underlying layer by etching using the resist pattern as a mask.08-05-2010
20120139008COMPOUND SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - An i-GaN layer (electron transit layer), an n-GaN layer (compound semiconductor layer) formed over the i-GaN layer (electron transit layer), and a source electrode, a drain electrode and a gate electrode formed over the n-GaN layer (compound semiconductor layer) are provided. A recess portion is formed inside an area between the source electrode and the drain electrode of the n-GaN layer (compound semiconductor layer) and at a portion separating from the gate electrode.06-07-2012
20090072273III-NITRIDE SEMICONDUCTOR DEVICE WITH REDUCED ELECTRIC FIELD BETWEEN GATE AND DRAIN AND PROCESS FOR ITS MANUFACTURE - A conductive field plate is formed between the drain electrode and gate of each cell of a III-Nitride semiconductor and is connected to the source electrode to reduce the electric field between the gate and the drain. The electrodes may be supported on N′ III-Nitride pad layers and the gate may be a Schottky gate or an insulated gate.03-19-2009
20110140172REVERSE SIDE ENGINEERED III-NITRIDE DEVICES - Group III-nitride devices are described that include a stack of III-nitride layers, passivation layers, and conductive contacts. The stack includes a channel layer with a 06-16-2011
20120104462SEMICONDUCTOR WAFER, METHOD OF PRODUCING SEMICONDUCTOR WAFER, AND ELECTRONIC DEVICE - A semiconductor wafer includes a first semiconductor, and a second semiconductor formed directly or indirectly on the first semiconductor. The second semiconductor contains a first impurity atom exhibiting p-type or n-type conductivity, and a second impurity atom selected such that the Fermi level of the second semiconductor containing both the first and second impurity atoms is closer to the Fermi level of the second semiconductor containing neither the first impurity atom nor the second impurity atom, than the Fermi level of the second semiconductor containing the first impurity atom is. For example, the majority carrier of the second semiconductor is an electron, and the Fermi level of the second semiconductor containing the first and second impurity atoms is lower than the Fermi level of the second semiconductor containing the first impurity atom.05-03-2012
20080237640N-FACE HIGH ELECTRON MOBILITY TRANSISTORS WITH LOW BUFFER LEAKAGE AND LOW PARASITIC RESISTANCE - A method for fabricating nitrogen-face (N-face) nitride-based electronic devices with low buffer leakage, comprising isolating a buffer from a substrate with an AlGaInN nucleation layer to suppress impurity incorporation from the substrate into the buffer. A method for fabricating N-face nitride-based electronic devices with low parasitic resistance and high breakdown, comprising capping a device structure with a conductive layer to provide extremely low access and/or contact resistances, is also disclosed.10-02-2008
20090200576SEMICONDUCTOR DEVICE - A semiconductor device includes: a first semiconductor layer including Al08-13-2009
20100264461N-polar aluminum gallium nitride/gallium nitride enhancement-mode field effect transistor - A novel enhancement mode field effect transistor (FET), such as a High Electron Mobility Transistors (HEMT), has an N-polar surface uses polarization fields to reduce the electron population under the gate in the N-polar orientation, has improved dispersion suppression, and low gate leakage.10-21-2010
20090315077MULTI-LAYER STRUCTURE WITH A TRANSPARENT GATE - A multi-layer structure with a transparent gate includes a MHEMT device structure comprising a GaAs substrate, a Schottky layer and a cap layer formed on the Schottky layer; a transparent gate formed on the Schottky layer being an indium tin oxide, ITO; and a drain and a source formed on the cap layer. Moreover, the MHEMT device structure includes a graded buffer, a buffer layer, a first spacer layer, a channel layer, and a second spacer layer formed between the GaAs substrate and the Schottky layer in a stacked fashion. The multi-layer structure is a transparent gate HEMT employing indium tin oxide which can make HEMT more sensitive to the light wave.12-24-2009
20110233612SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - There is provided a semiconductor device having a High Electron Mobility Transistor (HEMT) structure allowing for enhanced performance and a method of manufacturing the same. The semiconductor device includes a base substrate; a semiconductor layer provided on the base substrate; a source electrode, a gate electrode and a drain electrode provided on the semiconductor layer to be spaced apart from one another; and an ohmic-contact layer partially provided at an interface between the drain electrode and the semiconductor layer.09-29-2011
20130214330Transistor Having Increased Breakdown Voltage - There are disclosed herein various implementations of a transistor having an increased breakdown voltage. Such a transistor includes a source finger electrode having a source finger electrode beginning and a source finger electrode end. The transistor also includes a drain finger electrode with a curved drain finger electrode end having an increased radius of curvature. The resulting decreased electric field at the curved drain finger electrode end allows for an increased breakdown voltage and a more robust and reliable transistor. In some implementations, the curved drain finger electrode end may be extended beyond the source finger electrode beginning to achieve the increased breakdown voltage.08-22-2013
20100258846ELECTRONIC DEVICE WITH CONTROLLED ELECTRICAL FIELD - The disclosure relates to electronic devices and associated methods of manufacture including materials of the Group III/N. An exemplary device successively includes, from its base towards its surface: (i) a support substrate, (ii) a layer adapted to contain an electron gas, (iii) a barrier layer, and (iv) a superficial layer extending on at least one part of the surface of the barrier layer, wherein the superficial layer has an electrical field of which the current is controlled so that, in at least one first region of the superficial layer, the electrical field is weaker than in a second region of the superficial layer.10-14-2010
20100258845Semiconductor device and method for manufacturing same - There is provided a semiconductor device capable of deactivating 2-dimensional electron gas (2DEG) layers in a buffer layer having a multi-layer film structure. The buffer layer is formed in a high electron mobility transistor (HEMT) formed on a silicon (Si) substrate. The semiconductor device includes the substrate whose uppermost layer is the Si layer, the buffer layer constructed by alternately stacking a plurality of first layers and a plurality of second layers on the Si layer, third layer serving as an electron transit layer formed on the buffer layer, and fourth layer serving as an electron supplying layer formed on the third layer. The first layer is composed of the same material as for the third layer. A p-type impurity is introduced into the first layers so as to deactivate the 2DEG layers formed in the first layer near interfaces between the first and second layers.10-14-2010
20100176421DAMASCENE CONTACTS ON III-V CMOS DEVICES - A method for manufacturing a III-V CMOS device is disclosed. The device includes a first and second main contact and a control contact. In one aspect, the method includes providing the control contact by using damascene processing. The method thus allows obtaining a control contact with a length of between about 20 nm and 5 μm and with good Schottky behavior. Using low-resistive materials such as Cu allows reducing the gate resistance thus improving the high-frequency performance of the III-V CMOS device.07-15-2010
20100213512High-Mobility Channel Devices on Dislocation-Blocking Layers - A method of forming an integrated circuit structure includes forming a first recess in the semiconductor substrate; and forming a dislocation-blocking layer in the first recess. The dislocation-blocking layer includes a semiconductor material. Shallow trench isolation (STI) regions are formed, wherein inner portions of the STI regions are directly over portions of the dislocation-blocking layer, and wherein inner sidewalls of the STI regions contact the dislocation-blocking layer. A second recess is formed by removing a portion of the dislocation-blocking layer between two of the inner sidewalls of the STI regions, with the two inner sidewalls facing each other. A semiconductor region is epitaxially grown in the second recess.08-26-2010
20100224911Gallium nitride high electron mobility transistor - There is provided a gallium nitride high electron mobility transistor including: a channel layer that lets a carrier travel at high velocity; a carrier supply layer that generates the carrier; and a cap layer, disposed on the carrier supply layer and functioning to prevent oxidation of the carrier supply layer, to reduce gate leakage current, and to increase voltage withstand to gate voltage, wherein a thickness of the cap layer is set at a minimum as thicker than 11 nm.09-09-2010
20100230722HIGH ELECTRON MOBILITY FIELD EFFECT TRANSISTOR (HEMT) DEVICE - A High Electron Mobility Transistor (HEMT) device, which is formed by connecting a plurality of low power flip-chip type High Electron Mobility Transistor (HEMT) elements in parallel, or connected them in parallel and in series in combination into a tree-shaped structure, and then connecting said structure to an input terminal and an output terminal. Distances between each of the flip-chip type HEMT elements, from each element to said input terminal, and from each element to said output terminal are designed to be equal, such that powers consumed by each of the flip-chip type HEMT elements are equal, currents flowing through are evenly distributed, and heat generated is liable to be dissipated. A spike leakage protection layer, such as zinc-oxide (ZnO) amorphous layer or poly-crystal layer, is further included, hereby further enhancing the efficiency of said flip-chip type HEMT element and prolonging its service life.09-16-2010
20100140663CMOS Compatable fabrication of power GaN transistors on a <100> silicon substrate - In an AlGaN channel transistor formed on a <100> orientation silicon wafer, a hole with walls slanted at 54 degrees is etched into the silicon to provide a <111> orientation substrate surface for forming the AlGaN channel transistor.06-10-2010
20100252864SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR THE SAME - A semiconductor device which reduces source resistance and a manufacturing method for the same are provided. A semiconductor device has a nitride based compound semiconductor layer on a substrate and an active region on the nitride based compound semiconductor layer. The semiconductor device has a gate electrode, a source electrode and a drain on the active region, a source terminal electrode connected to the source electrode arranged on the nitride based compound semiconductor layer in a direction which the source electrode extends. Furthermore, the semiconductor device has an end face electrode which is arranged on the end face of the substrate in a source terminal electrode side, is connected to the source terminal electrode, and includes a multilayer metal layer including three or more layers which includes different metals, and prevents solder for die bonding from reaching the source terminal electrode.10-07-2010
20100163930SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD - An object of the present invention is to reduce on-state resistance and increases reliability in a semiconductor device having an electrode formed in a recessed structure.07-01-2010
20110057235SEMICONDUCTOR DEVICE - A semiconductor device according to one embodiment of the present invention includes a substrate, a compound semiconductor layer, a device region, a drain electrode, a source electrode, a source pad, a gate electrode and a metal. The substrate has a first aperture in a back surface thereof. The compound semiconductor layer is formed on the substrate. The device region is formed on the compound semiconductor layer. The drain electrode is formed transversely to the device region. The source electrode is formed transversely to the device region and with a distance from the drain electrode. The source pad is connected to the source electrode and formed on a non-device region surrounding the device region on the compound semiconductor layer. The gate electrode is formed between the source electrode and the drain electrode, above the first aperture and transversely to the device region. The metal is formed on the back surface of the substrate, including the first aperture and a second aperture penetrating the substrate and the compound semiconductor layer in such a manner as to expose a part of the source pad from the back surface of the substrate.03-10-2011
20110057232SEMICONDUCTOR DEVICES INCLUDING SHALLOW IMPLANTED REGIONS AND METHODS OF FORMING THE SAME - Methods of forming a semiconductor device include forming a dielectric layer on a Group III-nitride semiconductor layer, selectively removing portions of the dielectric layer over spaced apart source and drain regions of the semiconductor layer, implanting ions having a first conductivity type directly into the source and drain regions of the semiconductor layer, annealing the semiconductor layer and the dielectric layer to activate the implanted ions, and forming metal contacts on the source and drain regions of the semiconductor layer.03-10-2011
20090321787High voltage GaN-based heterojunction transistor structure and method of forming same - A semiconductor device includes a substrate, a first active layer disposed over the substrate, and a second active layer disposed on the first active layer. The second active layer has a higher bandgap than the first active layer such that a two-dimensional electron gas layer arises between the first active layer and the second active layer. A flash layer is disposed on the second active layer and source, gate and drain contacts are disposed on the flash layer.12-31-2009
20090166678SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device 07-02-2009
20090146186Gate after Diamond Transistor - A gate after diamond transistor and method of making comprising the steps of depositing a first dielectric layer on a semiconductor substrate, depositing a diamond particle nucleation layer on the first dielectric layer, growing a diamond thin film layer on the first dielectric layer, defining an opening for the gate in the diamond thin film layer, patterning of the diamond thin film layer for a gate metal to first dielectric layer surface, etching the first dielectric layer, depositing and defining a gate metal, and forming a contact window opening in the diamond thin film layer and the first dielectric layer to the ohmic contact.06-11-2009
20090108299High electron mobility transistor semiconductor device having field mitigating plate and fabrication method thereof - A semiconductor device includes a T-gate disposed between drain and source regions and above a barrier layer to form a Schottky contact to the channel layer. A first inactive field mitigating plate is disposed above a portion of the T-gate and a second active field plate is disposed above the barrier layer and in a vicinity of the T-gate.04-30-2009
20090072272ENHANCEMENT MODE GALLIUM NITRIDE POWER DEVICES - Enhancement mode III-nitride devices are described. The 2DEG is depleted in the gate region so that the device is unable to conduct current when no bias is applied at the gate. Both gallium face and nitride face devices formed as enhancement mode devices.03-19-2009
20100219452GaN HIGH ELECTRON MOBILITY TRANSISTOR (HEMT) STRUCTURES - A GaN HEMT structure having: a first III-N layer on GaN; a source electrode in contact with a first surface portion the first III-N layer disposed over a first region in the GaN layer; a drain electrode in contact with a second surface portion of the first III-N layer disposed over a second region in the GaN layer; a gate electrode disposed over a third surface portion of the first III-N layer, such third surface portion being disposed over a third region in the GaN layer. The GaN layer has: a fourth region therein disposed between the first region therein and the third region; and a fifth region therein disposed between the third region therein and the second region therein. A second III-N layer is disposed over the first III-N layer for generating a two-dimensional electron gas density in the GaN density in at least one of the fourth region and fifth region greater than the density in the third region of the GaN layer.09-02-2010
20100295098III-V HEMT DEVICES - A semiconductor device has a stacked structure in which a p-GaN layer, an SI-GaN layer, and an AlGaN layer are stacked, and has a gate electrode that is formed at a top surface side of the AlGaN layer. A band gap of the AlGaN layer is wider than a band gap of the p-GaN layer and the SI-GaN layer. Moreover, impurity concentration of the SI-GaN layer is less than 1×1011-25-2010
20100295097FIELD-EFFECT TRANSISTOR - A field-effect transistor according to the present invention includes a silicon substrate that has a resistivity of not more than 0.02 Ω•cm, a channel layer that is formed on the silicon substrate and has a thickness of at least 5 μm, a barrier layer that is formed on the channel layer and supplies the channel layer with electrons, a two dimensional electron gas layer that is formed by a hetero junction between the channel layer and the barrier layer, a source electrode and a drain electrode that each form an ohmic contact with the barrier layer, and a gate electrode that is formed between the source electrode and the drain electrode, and forms a Schottky barrier junction with the barrier layer.11-25-2010
20100308375Rare earth enhanced high electron mobility transistor and method for fabricating same - According to one embodiment, a high electron mobility transistor (HEMT) comprises an insulator layer comprising a first group III-V intrinsic layer doped with a rare earth additive. The HEMT also comprises a second group III-V intrinsic layer formed over the insulator layer, and a group III-V semiconductor layer formed over the second group III-V intrinsic layer. In one embodiment, a method for fabricating a HEMT comprises forming a first group III-V intrinsic layer and doping the first group III-V intrinsic layer with a rare earth additive to produce an insulator layer. The method also comprises forming a second group III-V intrinsic layer over the insulator layer, and further forming a group III-V semiconductor layer over the second group III-V intrinsic layer. A two-dimensional electron gas (2DEG) is formed at a heterojunction interface of the group III-V semiconductor layer and the second group III-V intrinsic layer.12-09-2010
20100301395Asymmetrically recessed high-power and high-gain ultra-short gate HEMT device - A high-power and high-gain ultra-short gate HEMT device has exceptional gain and an exceptionally high breakdown voltage provided by an increased width asymmetric recess for the gate electrode, by a composite channel layer including a thin indium arsenide layer embedded in the indium gallium arsenide channel layer and by double doping through the use of an additional silicon doping spike. The improved transistor has an exceptional 14 dB gain at 110 GHz and exhibits an exceptionally high 3.5-4 V breakdown voltage, thus to provide high gain, high-power and ultra-high frequency in an ultra-short gate device.12-02-2010
20110018034HETEROGENEOUS INTEGRATION OF LOW NOISE AMPLIFIERS WITH POWER AMPLIFIERS OR SWITCHES - A transistor heterogeneously integrating a power amplifier or switch with a low-noise amplifier having a substrate wafer selected from a group consisting of Gallium Arsenide (GaAs), Indium Phosphate (InP) and Gallium Antimonide (GaSb), the substrate having a first end and a second end, a conducting layer above the first end of the substrate, an isolation implant providing lateral isolation in the conducting layer, a first active layer deposited above the conducting layer and configured for the low-noise amplifier, and a buffer layer deposited above the conducting layer and configured for the low-noise amplifier.01-27-2011
20110108886METHOD OF CONTROLLING STRESS IN GROUP-III NITRIDE FILMS DEPOSITED ON SUBSTRATES - Methods of controlling stress in GaN films deposited on silicon and silicon carbide substrates and the films produced therefrom are disclosed. A typical method comprises providing a substrate and depositing a graded gallium nitride layer on the substrate having a varying composition of a substantially continuous grade from an initial composition to a final composition formed from a supply of at least one precursor in a growth chamber without any interruption in the supply. A typical semiconductor film comprises a substrate and a graded gallium nitride layer deposited on the substrate having a varying composition of a substantially continuous grade from an initial composition to a final composition formed from a supply of at least one precursor in a growth chamber without any interruption in the supply.05-12-2011
20110108887MULTILAYER BARRIER III-NITRIDE TRANSISTOR FOR HIGH VOLTAGE ELECTRONICS - An improved high breakdown voltage semiconductor device and method for manufacturing is provided. The device has a substrate and a Al05-12-2011
20110024797NITRIDE-BASED SEMICONDUCTOR DEVICE WITH CONCAVE GATE REGION - In FET, a second nitride semiconductor layer is provided on a first nitride semiconductor layer, and a source electrode and a drain electrode are each provided to have at least a portion thereof in contact with the second nitride semiconductor layer. A concave portion is formed in the upper surface of the second nitride semiconductor layer to be located between the source electrode and the drain electrode. A gate electrode is provided over the concave portion to cover the opening of the concave portion.02-03-2011
20110031533SEMICONDUCTOR DEVICE - The present invention miniaturizes a HEMT element used as a switching element in a radio frequency module. A single gate electrode 02-10-2011
20110031532COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A compound semiconductor device is provided with a substrate, an AlN layer formed over the substrate, an AlGaN layer formed over the AlN layer and larger in electron affinity than the AlN layer, another AlGaN layer formed over the AlGaN layer and smaller in electron affinity than the AlGaN layer. Furthermore, there are provided an i-GaN layer formed over the latter AlGaN layer, and an i-AlGaN layer and an n-AlGaN layer formed over the i-GaN layer.02-10-2011
20110042720Magneto-Electric Field Effect Transistor for Spintronic Applications - The present invention is directed to a magneto-electric field effect transistor comprising a channel region, a source connected to one side of the channel region and adapted to inject electrons into the channel region, a drain connected to the opposite side of the channel region and adapted to detect spin polarized electrons; and a gate comprising at least one magnetic double pair element comprising four magnetic elements each magnetic element being adapted to induce a magnetic field into the channel region, wherein the total induced magnetic field of the magnetic double pair element is controllable to be substantially zero, and wherein the gate is further adapted to induce an electrical field into the channel region.02-24-2011
20130153968Semiconductor Device - A semiconductor device and a method of making the same. The device includes a semiconductor substrate having an AlGaN layer on a GaN layer. The device also includes first contact and a second contact. The average thickness of the AlGaN layer varies between the first contact and the second contact, for modulating the density of an electron gas in the GaN layer between the first contact and the second contact.06-20-2013
20110114997HIGH VOLTAGE GaN TRANSISTORS - A multiple field plate transistor includes an active region, with a source, a drain, and a gate. A first spacer layer is over the active region between the source and the gate and a second spacer layer over the active region between the drain and the gate. A first field plate on the first spacer layer is connected to the gate. A second field plate on the second spacer layer is connected to the gate. A third spacer layer is on the first spacer layer, the second spacer layer, the first field plate, the gate, and the second field plate, with a third field plate on the third spacer layer and connected to the source. The transistor exhibits a blocking voltage of at least 600 Volts while supporting a current of at least 2 Amps with an on resistance of no more than 5.0 mΩ-cm05-19-2011
20110210377NITRIDE SEMICONDUCTOR DEVICE - A semiconductor device is described. In one embodiment, the device includes a Group-III nitride channel layer and a Group-III nitride barrier layer on the Group-III nitride channel layer, wherein the Group-III nitride barrier layer includes a first portion and a second portion, the first portion having a thickness less than the second portion. A p-doped Group-III nitride gate layer section is arranged at least on the first portion of the Group-III nitride barrier layer and a gate contact formed on the p-doped Group-III nitride gate layer.09-01-2011
20100163928COMPOUND SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - An i-GaN layer (electron transit layer), an n-GaN layer (compound semiconductor layer) formed over the i-GaN layer (electron transit layer), and a source electrode, a drain electrode and a gate electrode formed over the n-GaN layer (compound semiconductor layer) are provided. A recess portion is formed inside an area between the source electrode and the drain electrode of the n-GaN layer (compound semiconductor layer) and at a portion separating from the gate electrode.07-01-2010
20100163929COMPOUND SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A compound semiconductor device includes a carrier transit layer formed over a substrate; a carrier supply layer formed over the carrier transit layer; a first metal film and a second metal film formed over the carrier supply layer; a first Al comprising film formed over the first metal film; a second Al comprising film formed over the second metal film; a first Au comprising film formed over the first metal film and is free of direct contact with the first Al comprising film; a second Au comprising film formed over the second metal film and free of direct contact with the second Al comprising film; and a gate electrode that is located over the carrier supply layer between the first metal film and the second metal film.07-01-2010
20100163927Apparatus and methods for forming a modulation doped non-planar transistor - Embodiments of an apparatus and methods for providing three-dimensional complementary metal oxide semiconductor devices comprising modulation doped transistors are generally described herein. Other embodiments may be described and claimed.07-01-2010
20110241074SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A GaN layer and an n-type AlGaN layer are formed over an insulating substrate, and thereafter, a gate electrode, a source electrode and a drain electrode are formed on them. Next, an opening reaching at least a surface of the insulating substrate is formed in the source electrode, the GaN layer and the n-type AlGaN layer. Then, a nickel (Ni) layer is formed in the opening. Thereafter, by conducting dry etching from the back side while making the nickel (Ni) layer serve as an etching stopper, a via hole reaching the nickel (Ni) layer is formed in the insulating substrate. Then, a via wiring is formed extending from an inside the via hole to the back surface of the insulating substrate.10-06-2011
20110210378HIGH ELECTRON MOBILITY TRANSISTOR, EPITAXIAL WAFER, AND METHOD OF FABRICATING HIGH ELECTRON MOBILITY TRANSISTOR - A high electron mobility transistor includes a free-standing supporting base having a III nitride region, a first III nitride barrier layer which is provided on the first III nitride barrier layer, a III nitride channel layer which is provided on the first III nitride barrier layer and forms a first heterojunction with the first III nitride barrier layer, a gate electrode provided on the III nitride channel layer so as to exert an electric field on the first heterojunction, a source electrode on the III nitride channel layer and the first III nitride barrier, and a drain electrode on the III nitride channel layer and the first III nitride barrier. The III nitride channel layer has compressive internal strain, and the piezoelectric field of the III nitride channel layer is oriented in the direction from the supporting base towards the first III nitride barrier layer. The first heterojunction extends along a plane having a normal axis that is inclined at an inclination angle in the range of 40 degrees to 85 degrees or 140 degrees to 180 degrees with respect to the c-axis of the III nitride region.09-01-2011
20090218599POLARIZATION-INDUCED BARRIERS FOR N-FACE NITRIDE-BASED ELECTRONICS - A method for fabricating a potential barrier for a nitrogen-face (N-face) nitride-based electronic device, comprising using a thickness and polarization induced electric field of a III-nitride interlayer, positioned between a first III-nitride layer and a second III-nitride layer, to shift, e.g., raise or lower, the first III-nitride layer's energy band with respect to the second III-nitride layer's energy band by a pre-determined amount. The first III-nitride layer and second III-nitride layer each have a higher or lower polarization coefficient than the III-nitride interlayer's polarization coefficient.09-03-2009
20100012978NORMALLY-OFF FIELD-EFFECT SEMICONDUCTOR DEVICE - A normally-off HEMT is made by first providing a substrate having its surface partly covered with an antigrowth mask. Gallium nitride is grown by epitaxy on the masked surface of the substrate to provide an electron transit layer comprised of two flat-surfaced sections and a V-notch-surfaced section therebetween. The flat-surfaced sections are formed on unmasked parts of the substrate surface whereas the V-notch-surfaced section, defining a V-sectioned notch, is created by lateral overgrowth onto the antigrowth mask. Aluminum gallium nitride is then deposited on the electron transit layer to provide an electron supply layer which is likewise comprised of two flat-surfaced sections and a V-notch-surfaced section therebetween. The flat-surfaced sections of the electron supply layer are sufficiently thick to normally generate two-dimensional electron gas layers due to heterojunctions thereof with the first and the second flat-surfaced section of the electron transit layer. The V-notch-surfaced section of the electron supply layer is not so thick, normally creating an interruption in the two-dimensional electron gas layer.01-21-2010
20100059792METHOD OF RADIATION GENERATION AND MANIPULATION - A method of managing radiation having a frequency in the terahertz and/or microwave regions. The method comprises providing a semiconducting device having a two-dimensional carrier gas. Plasma waves are generated in the carrier gas using a laser pulse. The frequency of the plasma waves, and as a result, the generated radiation are adjusted using a voltage applied to the semiconducting device.03-11-2010
20110068371Group III nitride semiconductor device, production method therefor, power converter - Provided is an HEMT exhibiting a normally-off characteristic and low on-state resistance, which includes a first carrier transport layer; two separate second carrier transport layers formed of undoped GaN and provided on two separate regions of the first carrier transport layer; and carrier supply layers formed of AlGaN and respectively provided on the two separate second carrier transport layers. The second carrier transport layers and the carrier supply layers are respectively formed through crystal growth on the first carrier transport layer. The heterojunction interface between the second carrier transport layer and the carrier supply layer exhibits high flatness, and virtually no growth-associated impurities are incorporated in the vicinity of the heterojunction interface. Therefore, reduction in mobility of 2DEG is prevented, and on-state resistance is reduced.03-24-2011
20110068372SENSORS USING HIGH ELECTRON MOBILITY TRANSISTORS - Embodiments of the invention include sensors comprising AlGaAs/GaAs high electron mobility transistors (HEMTs), inGaP/GaAs HEMTs. InAlAs/InGaAs HEMTs, AlGaAs/InGaAs PHEMTs, InAlAs/InGaAs PHEMTs, Sb based HEMTs, or InAs based HEMTs, the HEMTs having functionalization at a gate surface with target receptors. The target receptors allow sensitivity to targets (or substrates) for detecting breast cancer, prostate cancer, kidney injury, chloride, glucose, metals or pEI where a signal is generated by the HEMI when a solution is contacted with the sensor. The solution can be blood, saliva, urine, breath condensate, or any solution suspected of containing any specific analyte for the sensor.03-24-2011
20090026500Semiconductor Device and Method of Manufacturing Such a Device - A semiconductor device includes a substrate of a first conductivity type, and a first semiconductor region that includes a plurality of sub-regions of the first conductivity type that have a first doping concentration and a further semiconductor region of a second conductivity type opposite to the first conductivity type. The further semiconductor region separates the sub-regions from each other and the first semiconductor region is located on the substrate. The semiconductor device further includes a second semiconductor region of the first conductivity type located on the first semiconductor region, a third semiconductor region of the second conductivity type located on the second semiconductor region, and a fourth semiconductor region of the first conductivity type located on the third semiconductor region. The sub regions extend from the second semiconductor region into the substrate, and the thickness and the doping concentration of the second and the third semiconductor region are such that these regions are completely depleted during operation of the device.01-29-2009
20090026499SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND SEMICONDUCTOR SWITCHING DEVICE USING THEREOF - A semiconductor integrated circuit device having a plurality of semiconductor electronic members including a field effect transistor, intended for suppressing a sidegating effect on the field effect transistor, wherein accumulation of majority carriers of the field effect transistor is suppressed at the interface of heterojunction in the buffering compound semiconductor layer and the interface between the substrate and the buffering compound semiconductor layer in the device isolation region so that the discontinuity of energy forbidden bands of the semiconductors caused at the interfaces does not form a potential barrier upon conduction of the carriers into the substrate, whereby the sidegating effect from the resistor element, etc. placed adjacently to the field effect transistor can be decreased drastically.01-29-2009
20090001423Field-effect transistor and method of making same - A field-effect transistor is composed of a substrate, an electron transport layer and an electron supply layer formed sequentially on the substrate, wherein the electron transport layer and the electron supply layer are formed of a nitride semiconductor, a gate electrode, a source electrode and a drain electrode formed on the electron supply layer; and two high impurity concentration regions located in a depth direction directly below the source electrode and the drain electrode, respectively, the two high impurity concentration regions being formed to sandwich a two-dimensional electron gas layer formed between the electron transport layer and the electron supply layer. The two high impurity concentration regions each have a higher impurity concentration than the electron transport layer and the electron supply layer located directly below the gate electrode. The electron supply layer has a substantially flat surface between the source electrode and the gate electrode and between the drain electrode and the gate electrode.01-01-2009
20080315256Nitride semiconductor device - A nitride semiconductor device according to the present invention includes: a nitride semiconductor laminated structure comprising a first layer made of a Group III nitride semiconductor, a second layer laminated on the first layer and made of an Al-containing Group III nitride semiconductor with a composition that differs from that of the first layer, the nitride semiconductor laminated structure comprising a stripe-like trench exposing a lamination boundary between the first layer and the second layer; a gate electrode formed to oppose the lamination boundary; and a source electrode and a drain electrode, having the gate electrode interposed therebetween, each connected electrically to the second layer.12-25-2008
20110254055FIELD EFFECT TRANSISTOR AND MANUFACTURING METHOD THEREOF - A field effect transistor includes a channel layer of group-III nitride-based compound semiconductor; an interface layer formed on the channel layer and of Al10-20-2011
20130168738SEMICONDUCTOR WAFER, INSULATED GATE FIELD EFFECT TRANSISTOR, AND METHOD FOR PRODUCING SEMICONDUCTOR WAFER - Provided is a semiconductor wafer including a base wafer, a first crystalline layer, a second crystalline layer, and an insulating layer that are positioned in the stated order, the semiconductor wafer further including: a third crystalline layer positioned either between the first crystalline layer and the second crystalline layer or between the base wafer and the first crystalline layer. The second crystalline layer and the third crystalline layer are made of a crystal that either lattice matches or pseudo lattice matches a crystal making the first crystalline layer, and has a wider band gap than the crystal making the first crystalline layer. The third crystalline layer includes a first atom that will be a donor or an acceptor. When the third crystalline layer includes a first atom that will be a donor, the second crystalline layer includes a second atom that will be an acceptor.07-04-2013
20130168739SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SAME - A vertical semiconductor device in which pinch-off characteristics and breakdown voltage characteristics can be stably improved by fixing the electric potential of a p-type GaN barrier layer with certainty is provided. The semiconductor device includes a GaN-based stacked layer having an opening, a regrown layer including a channel located so as to cover a wall surface of the opening, an n07-04-2013
20110169054WIDE BANDGAP HEMTS WITH SOURCE CONNECTED FIELD PLATES - A HEMT comprising a plurality of active semiconductor layers formed on a substrate. Source electrode, drain electrode, and gate are formed in electrical contact with the plurality of active layers. A spacer layer is formed on at least a portion of a surface of said plurality of active layers and covering the gate. A field plate is formed on the spacer layer and electrically connected to the source electrode, wherein the field plate reduces the peak operating electric field in the HEMT.07-14-2011
20120146096NITRIDE BASED SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - Disclosed herein is a nitride based semiconductor device. There is provided a nitride based semiconductor device according to the exemplary embodiment of the present invention including: a base substrate, an epitaxial growth layer disposed on the base substrate and generating 2-dimensional electron gas (06-14-2012
20120146097SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor layer disposed over a substrate, a second semiconductor layer disposed over the first semiconductor layer, a gate recess disposed, through removal of a part of or all the second semiconductor layer, in a predetermined region over the first semiconductor layer, an insulating film disposed over the gate recess and the second semiconductor layer, a gate electrode disposed over the gate recess with the insulating film therebetween, and a source electrode and a drain electrode disposed over the first semiconductor layer or the second semiconductor layer, whereby a central portion of the gate recess is higher than a peripheral portion of the gate recess.06-14-2012
20110147796SEMICONDUCTOR DEVICE WITH METAL CARRIER AND MANUFACTURING METHOD - Semiconductor device including a metal carrier substrate. Above the carrier substrate a first semiconductor layer of Al06-23-2011
20110147798CONDUCTIVITY IMPROVEMENTS FOR III-V SEMICONDUCTOR DEVICES - Conductivity improvements in III-V semiconductor devices are described. A first improvement includes a barrier layer that is not coextensively planar with a channel layer. A second improvement includes an anneal of a metal/Si, Ge or SiliconGermanium/III-V stack to form a metal-Silicon, metal-Germanium or metal-SiliconGermanium layer over a Si and/or Germanium doped III-V layer. Then, removing the metal layer and forming a source/drain electrode on the metal-Silicon, metal-Germanium or metal-SiliconGermanium layer. A third improvement includes forming a layer of a Group IV and/or Group VI element over a III-V channel layer, and, annealing to dope the III-V channel layer with Group IV and/or Group VI species. A fourth improvement includes a passivation and/or dipole layer formed over an access region of a III-V device.06-23-2011
20110147797STRUCTURE OF A pHEMT TRANSISTOR CAPABLE OF NANOSECOND SWITCHING - A method for fabricating a transistor and the resulting transistor is disclosed. The method generally includes steps (A) to (E). Step (A) may form a high mobility layer. The high mobility layer is generally configured to carry a two-dimensional electron gas. Step (B) may form a planar layer on the high mobility layer. Step (C) may form a barrier layer on the planar layer. Step (D) may form a doped layer on the barrier layer. The doped layer is generally a low bandgap III-V semiconductor. Step (E) may form a gate in contact with the doped layer. The gate may be separated from both a source and a drain by corresponding ungated recess regions. The high mobility layer, the planar layer, the barrier layer, the doped layer, the source, the gate and the drain are generally configured as a pseudomorphic high electron mobility transistor.06-23-2011
20100038681TRANSISTOR - An HEMT type transistor is disclosed that is a normally off type, and in which variations in the gate threshold voltage are small. A transistor is provided with a p-type region, a barrier region, an insulation film, a gate electrode. The channel region is connected to an upper surface of the p-type region. The channel region is n-type or i-type and provided with a first channel region and a second channel region. The barrier region is forming a hetero-junction with an upper surface of the first channel region. The insulation film is connected to an upper surface of the second channel region and an upper surface of the barrier region. The gate electrode faces the second channel region and the barrier region via the insulation film. The first channel region and the second channel region are arranged in series in a current pathway.02-18-2010
20110215380ELECTRONIC DEVICES WITH IMPROVED OHMIC CONTACT - In one embodiment, the disclosure relates to an electronic device successively comprising from its base to its surface: (a) a support layer, (b) a channel layer adapted to contain an electron gas, (c) a barrier layer and (d) at least one ohmic contact electrode formed by a superposition of metallic layers, a first layer of which is in contact with the barrier layer. The device is remarkable in that the barrier layer includes a contact region under the ohmic contact electrode(s). The contact region includes at least one metal selected from the metals forming the superposition of metallic layers. Furthermore, a local alloying binds the contact region and the first layer of the electrode(s).09-08-2011
20110215379FIELD EFFECT TRANSISTOR - A field effect transistor includes a semiconductor stack formed on a substrate, and having a first nitride semiconductor layer and a second nitride semiconductor layer. A source electrode and a drain electrode are formed on the semiconductor stack so as to be separated from each other. A gate electrode is formed between the source electrode and the drain electrode so as to be separated from the source electrode and the drain electrode. A hole injection portion is formed near the drain electrode. The hole injection portion has a p-type third nitride semiconductor layer, and a hole injection electrode formed on the third nitride semiconductor layer. The hole injection electrode and the drain electrode have substantially the same potential.09-08-2011
20100019279Integrated HEMT and Lateral Field-Effect Rectifier Combinations, Methods, and Systems - Integrated high efficiency lateral field effect rectifier and HEMT devices of GaN or analogous semiconductor material, methods for manufacturing thereof, and systems which include such integrated devices. The lateral field effect rectifier has an anode containing a shorted ohmic contact and a Schottky contact, and a cathode containing an ohmic contact, while the HEMT preferably has a gate containing a Schottky contact. Two fluorine ion containing regions are formed directly underneath both Schottky contacts in the rectifier and in the HEMT, pinching off the (electron gas) channels in both structures at the hetero-interface between the epitaxial layers.01-28-2010
20120146095NITRIDE BASED SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - Disclosed herein is a nitride based semiconductor device including: a base substrate; an epitaxial growth layer disposed on the base substrate and generating a 2-dimensional electron gas in an inner portion thereof; and an electrode structure disposed on the epitaxial growth layer, wherein the electrode structure includes: a gate electrode; a source electrode disposed at one side of the gate electrode; and a drain electrode disposed at the other side of the gate electrode and having an extension part extended to the inner portion of the epitaxial growth layer to contact the 2-dimensional electron gas.06-14-2012
20110089467OHMIC CONTACT OF III-V SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - Heavily doped epitaxial SiGe material or epitaxial In04-21-2011
20090173969Semiconductor Device - A semiconductor device having an AlGaN—GaN heterojunction structure including an AlGaN layer and a GaN layer which device exhibits no changes over time in sheet resistance.07-09-2009
20090315078INSULATING GATE AlGaN/GaN HEMT - AlGaN/GaN HEMTs are disclosed having a thin AlGaN layer to reduce trapping and also having additional layers to reduce gate leakage and increase the maximum drive current. One HEMT according to the present invention comprises a high resistivity semiconductor layer with a barrier semiconductor layer on it. The barrier layer has a wider bandgap than the high resistivity layer and a 12-24-2009
20110073911SEMICONDUCTOR DEVICE - A semiconductor device including: a substrate, which has a composition represented by the formula: Al03-31-2011
20120098037DEVICE HAVING SERIES-CONNECTED HIGH ELECTRON MOBILITY TRANSISTORS AND MANUFACTURING METHOD THEREOF - A manufacturing method of a device having series-connected HEMTs is presented. Transistors are formed on a substrate and integratedly serial-connected as an integrated device by interconnection wires. Therefore, the voltage of the device is the sum of the voltages across each transistors so that the device can have high breakdown voltage.04-26-2012
20120098036Group III-N HEMT with a Floating Substrate Region and a Grounded Substrate Region - The Si substrate of a group III-N HEMT is formed in layers that define a p-n junction which electrically isolates an upper region of the Si substrate from a lower region of the Si substrate. As a result, the upper region of the Si substrate can electrically float, thereby obtaining a full buffer breakdown voltage, while the lower region of the Si substrate can be attached to a package by way of a conductive epoxy, thereby significantly improving the thermal conductivity of the group III-N HEMT and minimizing undesirable floating-voltage regions.04-26-2012
20120032232SEMICONDUCTOR DEVICE - A semiconductor device protects against concentration of electric current at a front end portion of one of the electrodes thereof The semiconductor device includes a substrate, a compound semiconductor layer formed on the substrate and having a channel layer based on a hetero junction, a first main electrode formed on the compound semiconductor layer, a second main electrode formed on the compound semiconductor surrounding the first main electrode and having a linear region and an arc-shaped region, a control electrode formed on the compound semiconductor layer and disposed opposite to the first main electrode and the second main electrode, an electric current being made to flow between the first main electrode and the second main electrode, and an electric current limiting section formed between the first main electrode and the arc-shaped region of the second main electrode.02-09-2012
20120305991DEVICE HAVING SERIES-CONNECTED HIGH ELECTRON MOBILITY TRANSISTORS AND MANUFACTURING METHOD THEREOF - A manufacturing method of a device having series-connected HEMTs is presented. Transistors are formed on a substrate and integratedly serial-connected as an integrated device by interconnection wires. Therefore, the voltage of the device is the sum of the voltages across each transistors so that the device can have high breakdown voltage.12-06-2012
20120146094NITRIDE BASED SEMICONDUCTOR DEVICE - Disclosed herein is a nitride based semiconductor device. There is provided a nitride based semiconductor device including: a base substrate; a semiconductor layer disposed on the base substrate; and an electrode structure disposed on the semiconductor layer, wherein the electrode structure includes: a cathode structure ohmic-contacting the semiconductor layer; and an anode structure having a schottky electrode schottky-contacting the semiconductor layer and an ohmic electrode ohmic-contacting the nitride layer.06-14-2012
20120037958POWER ELECTRONIC DEVICE AND METHOD OF MANUFACTURING THE SAME - According to an example embodiment, a power electronic device includes a first semiconductor layer, a second semiconductor layer on a first surface of the first semiconductor layer, and a source, a drain, and a gate on the second semiconductor layer. The source, drain and gate are separate from one another. The power electronic device further includes a 2-dimensional electron gas (2DEG) region at an interface between the first semiconductor layer and the second semiconductor layer, a first insulating layer on the gate and a second insulating layer adjacent to the first insulating layer. The first insulating layer has a first dielectric constant and the second insulating layer has a second dielectric constant less than the first dielectric constant.02-16-2012
20110068370Power electronic devices, methods of manufacturing the same, and integrated circuit modules including the same - Power electronic devices including 2-dimensional electron gas (2DEG) channels and methods of manufacturing the same. A power electronic device includes lower and upper material layers for forming a 2DEG channel, and a gate contacting an upper surface of the upper material layer. A region below the gate of the 2DEG channel is an off region where the density of a 2DEG is reduced or zero. The entire upper material layer may be continuous and may have a uniform thickness. A region of the upper material layer under the gate contains an impurity for reducing or eliminating a lattice constant difference between the lower and upper material layers.03-24-2011
20100102358SINGLE VOLTAGE SUPPLY PSEUDOMORPHIC HIGH ELECTRON MOBILITY TRANSISTOR (PHEMT) POWER DEVICE AND PROCESS FOR MANUFACTURING THE SAME - Disclosed herein is a pseudomorphic high electron mobility transistor (PHEMT) power device (04-29-2010
20110316049NITRIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided are a vertical nitride semiconductor device in which occurrence of leak currents can be suppressed, and a method for manufacturing such nitride semiconductor device. A nitride semiconductor device, which is a vertical HEMT, is provided with an n12-29-2011
20120043587SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer formed in contact with the first semiconductor layer, and a third semiconductor layer of a second conductivity type formed in contact with the second semiconductor layer, the first semiconductor layer provided with a first semiconductor region at a given distance from an interface between the first semiconductor layer and the second semiconductor layer, and an impurity concentration of the first semiconductor region higher than an impurity concentration of the first semiconductor layer except where the first semiconductor region is formed.02-23-2012
20120043586SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a substrate, a carrier transit layer disposed above the substrate, a compound semiconductor layer disposed on the carrier transit layer, a source electrode disposed on the compound semiconductor layer, a first groove disposed from the back of the substrate up to the inside of the carrier transit layer while penetrating the substrate, a drain electrode disposed in the inside of the first groove, a gate electrode located between the source electrode and the first groove and disposed on t he compound semiconductor layer, and a second groove located diagonally under the source electrode and between the source electrode and the first groove and disposed from the back of the substrate up to the inside of the carrier transit layer while penetrating the substrate.02-23-2012
20120001230Multi-gate semiconductor devices - A multi-gate semiconductor device with inter-gate conductive regions being connected to balance resistors is provided. The multi-gate semiconductor device comprises a substrate, a multilayer structure formed upon the substrate, a first ohmic electrode, a second ohmic electrode, a plural of gate electrodes, at least one conductive region, and at least one resistive component. When put into practice, the multi-gate semiconductor device is advantageous in reducing the voltage drop along the conductive region with a minimal change in device layout, improving the 01-05-2012
20110156100High Electron Mobility Transistor and Method for Fabricating the Same - A high electron mobility transistor includes a substrate, a buffer layer, a channel layer, a spacer layer, a schottky layer and a cap layer. The buffer layer is formed on the substrate. The channel layer is formed on the buffer layer, in which the channel layer comprises a superlattice structure formed with a plurality of indium gallium arsenide thin films alternately stacked with a plurality of indium arsenide thin films. The spacer layer is formed on the channel layer. The schottky layer is formed on the spacer layer. The cap layer is formed on the schottky layer.06-30-2011
20100270591HIGH-ELECTRON MOBILITY TRANSISTOR - Disclosed are high electron mobility transistors (HEMTs). In some embodiments, a HEMT includes a channel layer composed of a first compound semiconductor material and one or more barrier layers disposed on either one side or both sides of the channel layer and composed of a second compound semiconductor material.10-28-2010
20120205718COMPOUND SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A compound semiconductor device including: a substrate; an electron transit layer formed on and above the substrate; and an electron supply layer formed on and above the electron transit layer, wherein a first region or regions having a smaller thermal expansion coefficient than the electron transit layer and a second region or regions having a larger thermal expansion coefficient than the electron transit layer are mixedly present on a surface of the substrate.08-16-2012
20120205717COMPOUND SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING THE DEVICE AND ELECTRIC DEVICE - A compound semiconductor device includes: a compound semiconductor multilayer structure; a gate insulating film on the compound semiconductor multilayer structure; and a gate electrode, wherein the gate electrode includes a gate base portion on the gate insulating film and a gate umbrella portion, and a surface of the gate umbrella portion includes a Schottky contact with the compound semiconductor multilayer structure.08-16-2012
20110095337SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device reduces the on-resistance and, at the same time, raises the breakdown voltage. The drain electrode 04-28-2011
20110095336LATERAL HEMT AND METHOD FOR THE PRODUCTION OF A LATERAL HEMT - In one embodiment a lateral HEMT has a first layer, the first layer including a semiconducting material, and a second layer, the second layer including a semiconducting material and being at least partially arranged on the first layer. The lateral HEMT further has a passivation layer and a drift region, the drift region including a lateral width w04-28-2011
20120012894PERFORMANCE OF NITRIDE SEMICONDUCTOR DEVICES - A method of forming a transistor over a nitride semiconductor layer includes surface-treating a first region of a nitride semiconductor layer and forming a gate over the first region. Surface-treating the first region can cause the transistor to have a higher intrinsic small signal transconductance than a similar transistor formed without the surface treatment. A portion of the bottom of the gate can be selectively etched. A resulting transistor can include a nitride semiconductor layer having a surface-treated region and a gate formed over or adjacent to the surface-treated region.01-19-2012
20120061729NITRIDE SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A nitride semiconductor device includes a semiconductor layer stack including a first nitride semiconductor layer and a second nitride semiconductor layer stacked in this order on a substrate. A p-type third nitride semiconductor layer is selectively formed on the semiconductor layer stack, and a gate electrode is formed on the third nitride semiconductor layer. A first ohmic electrode and a second ohmic electrode are formed on regions of the semiconductor layer stack located at both sides of the third nitride semiconductor layer, respectively. A first gate electrode forms a Schottky contact with the third nitride semiconductor layer.03-15-2012
20120153356HIGH ELECTRON MOBILITY TRANSISTOR WITH INDIUM GALLIUM NITRIDE LAYER - Disclosed embodiments include a high electron mobility transistor (HEMT) with an indium gallium nitride layer set as one of a plurality of barrier sublayers and methods for forming such a HEMT. Other embodiments are also be described and claimed.06-21-2012
20110057233Semiconductor component and method for manufacturing of the same - The present invention provides a semiconductor component. The semiconductor component in accordance with the present invention includes a lower layer including a low resistance layer and a high resistance layer with higher resistivity than the low resistance layer while surrounding a lateral surface of the low resistance layer; a source electrode disposed on a front surface of the high resistance layer; a gate structure disposed on a front surface of the low resistance layer; a drain structure disposed on a rear surface of the low resistance layer; and a base substrate surrounding the drain structure on a rear surface of the high resistance layer.03-10-2011
20100096668High voltage durability III-Nitride semiconductor device - A high voltage durability III-nitride semiconductor device comprises a support substrate including a first silicon body, an insulator body over the first silicon body, and a second silicon body over the insulator body. The high voltage durability III-nitride semiconductor device further comprises a III-nitride semiconductor body characterized by a majority charge carrier conductivity type, formed over the second silicon body. The second silicon body has a conductivity type opposite the majority charge carrier conductivity type. In one embodiment, the high voltage durability III-nitride semiconductor device is a high electron mobility transistor (HEMT) comprising a support substrate including a <100> silicon layer, an insulator layer over the <100> silicon layer, and a P type conductivity <111> silicon layer over the insulator layer. The high voltage durability HEMT also comprises a III-nitride semiconductor body formed over the P type conductivity <111> silicon layer, the III-nitride semiconductor body forming a heterojunction of the HEMT.04-22-2010
20110089468HEMT Device and a Manufacturing of the HEMT Device - A HEMT device and a manufacturing of the HEMT device, the HEMT device includes: a buffer layer (04-21-2011
20120119260Methods of Forming Semiconductor Contacts and Related Semiconductor Devices - Methods of forming semiconductor devices having customized contacts are provided including providing a first insulator layer and patterning the first insulator layer such that the first insulator layer defines at least one contact window. A second insulator layer is provided on the first insulator layer and in the at least one contact window such that the second insulator layer at least partially fills the at least one contact window. A first portion of the second insulator layer is etched such that a second portion of the second insulator layer remains in the at least one contact window to provide at least one modified contact window having dimensions that are different than dimensions of the at least one contact window. Related methods and devices are also provided.05-17-2012
20120211801GROUP III NITRIDE LAMINATED SEMICONDUCTOR WAFER AND GROUP III NITRIDE SEMICONDUCTOR DEVICE - There is provided a normally-off group III nitride semiconductor device having a high breakdown field strength and minimal crystal defects, and a group III nitride laminated semiconductor wafer used to make the group III nitride semiconductor device. The group III nitride laminated semiconductor wafer 08-23-2012
20120211802FIELD EFFECT TRANSISTOR, SEMICONDUCTOR SWITCH CIRCUIT, AND COMMUNICATION APPARATUS - A field effect transistor includes a source wiring that is formed on a compound semiconductor substrate, and has a plurality of source electrodes arranged in parallel to each other at predetermined intervals, a drain wiring that is formed on the compound semiconductor substrate, and has a plurality of drain electrodes arranged in parallel to each other at predetermined intervals and alternatively disposed in a parallel direction of the plurality of source electrodes, a gate wiring that is formed on the compound semiconductor substrate, and has a portion located between the source electrode and the drain electrode which are adjacent to each other at least in the parallel direction, and a plurality of buried gate layers that is formed under the gate wiring in a region in which the gate wiring is formed, and is independently provided between each electrode of the source electrodes and the drain electrodes.08-23-2012
20120211800GaN HEMTs with a Back Gate Connected to the Source - The present invention reduces the dynamic on resistance in the channel layer of a GaN device by etching a void in the nucleation and buffer layers between the gate and the drain. This void and the underside of the device substrate may be plated to form a back gate metal layer. The present invention increases the device breakdown voltage by reducing the electric field strength from the gate to the drain of a HEMT. This electric field strength is reduced by placing a back gate metal layer below the active region of the channel. The back gate metal layer may be in electrical contact with the source or drain.08-23-2012
20110180854Normally-off gallium nitride-based semiconductor devices - A method includes forming a relaxed layer in a semiconductor device. The method also includes forming a tensile layer over the relaxed layer, where the tensile layer has tensile stress. The method further includes forming a compressive layer over the relaxed layer, where the compressive layer has compressive stress. The compressive layer has a piezoelectric polarization that is approximately equal to or greater than a spontaneous polarization in the relaxed, tensile, and compressive layers. The piezoelectric polarization in the compressive layer could be in an opposite direction than the spontaneous polarization in the compressive layer. The relaxed layer could include gallium nitride, the tensile layer could include aluminum gallium nitride, and the compressive layer could include aluminum indium gallium nitride.07-28-2011
20120132958High performance transistor - A novel semiconductor transistor is presented. The semiconductor structure has a gate region forming a channel with repetitive patterns in the direction perpendicular to the current flow, so that the portion of its channel that is not strictly planar contributes to a significant reduction of the silicon area occupied by the device. It offers the advantage of lower on-resistance for the same silicon area while improving on its dynamic performances. The additional cost to shape the channel region of the device in periodic repetitive patterns is minimum, which makes the present invention easy to implement in any conventional CMOS process technology and very cost effective.05-31-2012
20120132959WIDE BANDGAP TRANSISTOR DEVICES WITH FIELD PLATES - A transistor structure comprising an active semiconductor layer with metal source and drain contacts formed in electrical contact with the active layer. A gate contact is formed between the source and drain contacts for modulating electric fields within the active layer. A spacer layer is formed above the active layer and a conductive field plate formed above the spacer layer, extending a distance L05-31-2012
20120313145SEMICONDUCTOR DEVICE WITH SPACER LAYER BETWEEN CARRIER TRAVELING LAYER AND CARRIER SUPPLYING LAYER - A nitride semiconductor device is disclosed. The device includes a stack of semiconductor layers including the channel layer, the spacer layer, and the doped layer. The spacer layer is made of AlN while the doped layer is InAlN. A feature of the embodiment is that the spacer layer has a thickness of 0.5 to 1.25 nm.12-13-2012
20120223366HIGH VOLTAGE GAN TRANSISTOR - A multiple field plate transistor includes an active region, with a source, drain, and gate. A first spacer layer is between the source and the gate and a second spacer layer between the drain and the gate. A first field plate on the first spacer layer and a second field plate on the second spacer layer are connected to the gate. A third field plate connected to the source is on a third spacer layer, which is on the gate and the first and second field plates and spacer layers. The transistor exhibits a blocking voltage of at least 600 Volts while supporting current of at least 2 or 3 Amps with on resistance of no more than 5.0 or 5.3 mΩ-cm09-06-2012
20090057720Field-Effect Semiconductor Device, and Method of Fabrication - A HEMT-type field-effect semiconductor device has a main semiconductor region comprising two layers of dissimilar materials such that a two-dimensional electron gas layer is generated along the heterojunction between the two layers. A source and a drain electrode are placed in spaced positions on a major surface of the main semiconductor region. Between these electrodes, a gate electrode is received in a recess in the major surface of the main semiconductor region via a p-type metal oxide semiconductor film whereby a depletion zone is normally created in the electron gas layer, with a minimum of turn-on resistance and gate leak current.03-05-2009
20090057719COMPOUND SEMICONDUCTOR DEVICE WITH MESA STRUCTURE - A compound semiconductor device having mesa-shaped element region, and excellent characteristics are provided. The compound semiconductor device has: an InP substrate; an epitaxial lamination mesa formed above the InP substrate and including a channel layer, a carrier supply layer above the channel layer and a contact cap layer above the carrier supply layer; ohmic source electrode and drain electrode formed on the cap layer; a recess formed by removing the cap layer between the source and drain electrodes, and exposing the carrier supply layer; an insulating film formed on the cap layer and retracted from an edge of the cap layer away from the recess; a gate electrode extending from the carrier supply layer in the recess to outside of the mesa; and air gap formed by removing side portion of the channel layer facing the gate electrode outside the mesa.03-05-2009
20100052015SEMICONDUCTOR DEVICE - A semiconductor device includes a first compound semiconductor layer having a two-dimensional carrier gas channel, a second compound semiconductor layer which functions as a barrier layer and is arranged above the first compound semiconductor layer, a first main electrode connected to one end of the two-dimensional carrier gas channel, and a second main electrode connected to another end of the two-dimensional carrier gas channel, these ends being separated, wherein a compound ratio of an elemental compound of the second compound semiconductor layer is different in a direction of the two-dimensional carrier gas channel between the first main electrode and the second main electrode.03-04-2010
20090101939Group III Nitride Field Effect Transistors (FETS) Capable of Withstanding High Temperature Reverse Bias Test Conditions - Group III Nitride based field effect transistor (FETs) are provided having a power degradation of less than about 3.0 dB when operated at a drain-to-source voltage (V04-23-2009
20120217545METHOD OF PRODUCING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method of producing a semiconductor device, includes: forming a semiconductor layer on a substrate; forming an a recess in the semiconductor layer by dry etching with a gas containing fluorine components, the recess having an opening portion on the surface of the semiconductor layer; forming a fluorine-containing region by heating the semiconductor layer and thus diffusing, into the semiconductor layer, the fluorine components attached to side surfaces and a bottom surface of the recess; forming an insulating film on an inner surface of the recess and on the semiconductor layer; and forming an electrode on the insulating film in a region in which the recess is formed.08-30-2012
20100244098SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor layer made of Fe-doped GaN; a first buffer layer that is provided on the semiconductor layer so as to contact an upper surface of the semiconductor layer and is made of AlN or Al09-30-2010
20090140296Epitaxial Growth of Cubic Crystalline Semiconductor Alloys on Basal Plane of Trigonal or Hexagonal Crystal - Hetero-epitaxial semiconductor materials comprising cubic crystalline semiconductor alloys grown on the basal plane of trigonal and hexagonal substrates, in which misfit dislocations are reduced by approximate lattice matching of the cubic crystal structure to underlying trigonal or hexagonal substrate structure, enabling the development of alloyed semiconductor layers of greater thickness, resulting in a new class of semiconductor materials and corresponding devices, including improved hetero-bipolar and high-electron mobility transistors, and high-mobility thermoelectric devices.06-04-2009
20120119261SEMICONDUCTOR DEVICE - A semiconductor device includes: a substrate 05-17-2012
20120223367Method For Fabricating Semiconductor Wafers For The Integration of Silicon Components With Hemts, And Appropriate Semiconductor Layer Arrangement - The invention describes a method for fabricating silicon semiconductor waferswith the layer structures from III-V semiconductor layers for the integration of HEMTs based on semiconductor III-V layers with silicon components. SOI silicon semiconductor wafersare used, the active semiconductor layer of which has the III-V semiconductor layers (09-06-2012
20120223365III-Nitride Semiconductor Structures with Strain Absorbing Interlayer Transition Modules - There are disclosed herein various implementations of semiconductor structures including III-Nitride interlayer modules. One exemplary implementation comprises a substrate and a first transition body over the substrate. The first transition body has a first lattice parameter at a first surface and a second lattice parameter at a second surface opposite the first surface. The exemplary implementation further comprises a second transition body, such as a transition module, having a smaller lattice parameter at a lower surface overlying the second surface of the first transition body and a larger lattice parameter at an upper surface of the second transition body, as well as a III-Nitride semiconductor layer over the second transition body. The second transition body may consist of two or more transition modules, and each transition module may include two or more interlayers. The first and second transition bodies reduce strain for the semiconductor structure.09-06-2012
20100327322Transistor with Enhanced Channel Charge Inducing Material Layer and Threshold Voltage Control - High electron mobility transistors and fabrication processes are presented in which a barrier material layer of uniform thickness is provided for threshold voltage control under an enhanced channel charge inducing material layer (ECCIML) in source and drain regions with the ECCIML layer removed in the gate region.12-30-2010
20120319169CMOS COMPATIBLE METHOD FOR MANUFACTURING A HEMT DEVICE AND THE HEMT DEVICE THEREOF - A method for manufacturing a III-nitride HEMT having a gate electrode and source and drain ohmic contacts is provided, comprising providing a substrate; forming a stack of III-nitride layers on the substrate; forming a first passivation layer comprising silicon nitride overlying and in contact with an upper layer of the stack of III-nitride layers, wherein the first passivation layer is deposited in-situ with the stack of III-nitride layers; forming a dielectric layer overlying and in contact with the first passivation layer; forming a second passivation layer comprising silicon nitride overlying and in contact with the dielectric layer wherein the second passivation layer is deposited at a temperature higher than 450° C. by LPCVD or MOCVD or any equivalent technique; and thereafter forming the source and drain ohmic contacts and the gate electrode.12-20-2012
20120261720METHOD FOR MANUFACTURING A HEMT TRANSISTOR AND CORRESPONDING HEMT TRANSISTOR - A method for manufacturing a HEMT transistor includes: realizing an undoped epitaxial layer on a substrate; realizing a barrier epitaxial layer on the undoped epitaxial layer so as to form a heterojunction; realizing source and drain structures, separated from one other, on the barrier epitaxial layer; depositing an insulating layer on the barrier epitaxial layer and on the source and drain structures; and photolithographic defining the insulating layer, defining first and second insulating portions in correspondence of the source and drain structures, respectively, and exposing a portion of the barrier epitaxial layer. The method further comprises: forming first and second spacers lying at the corners of the first and second insulating portions; and depositing a gate metal structure at least partially covering said first and second insulating portions, and said first and second spacers, said gate metal structure being a field plate of the HEMT transistor.10-18-2012
20120267686Nitride semiconductor device and manufacturing method thereof - Provided is a nitride semiconductor device including: a nitride semiconductor layer over a substrate wherein the nitride semiconductor has a two-dimensional electron gas (2DEG) channel inside; a drain electrode in ohmic contact with the nitride semiconductor layer; a source electrode spaced apart from the drain electrode, in Schottky contact with the nitride semiconductor layer, and having an ohmic pattern in ohmic contact with the nitride semiconductor layer inside; a dielectric layer formed on the nitride semiconductor layer between the drain electrode and the source electrode and on at least a portion of the source electrode; and a gate electrode disposed on the dielectric layer to be spaced apart from the drain electrode, wherein a portion of the gate electrode is formed over a drain-side edge portion of the source electrode with the dielectric layer interposed therebetween, and a manufacturing method thereof.10-25-2012
20120267687Nitride semiconductor device and manufacturing method thereof - Provided is a nitride semiconductor device including: a nitride semiconductor layer over a substrate wherein the nitride semiconductor has a two-dimensional electron gas (2DEG) channel inside; a drain electrode in ohmic contact with the nitride semiconductor layer; a source electrode in Schottky contact with the nitride semiconductor layer wherein the source electrode is spaced apart from the drain electrode; a dielectric layer formed on the nitride semiconductor layer between the drain electrode and the source electrode and on at least a portion of the source electrode, wherein the dielectric layer has a recess formed between the drain electrode and the source electrode; and a gate electrode formed on the dielectric layer and in the recess to be spaced apart from the drain electrode, wherein a portion of the gate electrode is formed over a drain-side edge portion of the source electrode with the dielectric layer interposed therebetween, and a manufacturing method thereof.10-25-2012
20110215378High electron mobility transistors exhibiting dual depletion and methods of manufacturing the same - High electron mobility transistors (HEMT) exhibiting dual depletion and methods of manufacturing the same. The HEMT includes a source electrode, a gate electrode and a drain electrode disposed on a plurality of semiconductor layers having different polarities. A dual depletion region exists between the source electrode and the drain electrode. The plurality of semiconductor layers includes an upper material layer, an intermediate material layer and a lower material layer, and a polarity of the intermediate material layer is different from polarities of the upper material layer and the lower material layer.09-08-2011
20120080724SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor layer, a second semiconductor layer, a two-dimensional carrier gas layer, a first main electrode, a second main electrode, a first gate electrode, and a second gate electrode. The first gate electrode is provided between a part of the first main electrode and a part of the second main electrode opposite to the part of the first main electrode. The second gate electrode is provided between another part of the first main electrode and another part of the second main electrode opposite to the another part of the first main electrode with a separation region interposed between the first gate electrode and the second gate electrode. The second gate electrode is controlled independently of the first gate electrode.04-05-2012
20100230723High Electron Mobility Transistor, Field-Effect Transistor, and Epitaxial Substrate - Affords high electron mobility transistors having a high-purity channel layer and a high-resistance buffer layer. A high electron mobility transistor (09-16-2010
20120280280SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - The invention relates to a semiconductor device and a fabrication method thereof. A semiconductor device according to an aspect of the invention comprising: a semiconductor layer on a substrate; an isolation layer on the semiconductor layer; a source and a drain which are in contact with the semiconductor layer, each of the source and the drain comprises multiple fingers, and the multiple fingers of the source intersect the multiple fingers of the drain; and a gate on the isolation layer, the gate is located between the source and the drain and comprises a closed ring structure which encircles the multiple fingers of the source and the drain.11-08-2012
20120091508COMPOUND SEMICONDUCTOR DEVICE - A compound semiconductor device includes: a compound semiconductor layer; a source electrode; a drain electrode; a gate electrode; a field plate; and a low-conductivity region. The low-conductivity region is arranged within a region immediately below the field plate in a region where the two-dimensional carrier gas layer is formed, and has lower conductivity than a region above which the field plate or the gate electrode is not arranged in the region where the two-dimensional carrier gas layer is formed.04-19-2012
20130009212TRANSISTOR DEVICE - To provide a transistor device, which is composed of a compound semiconductor, having a multilayer structure in which a high electron mobility transistor (HEMT) and a heterojunction bipolar transistor (HBT) are overlapped on the same substrate and epitaxial-grown thereon, wherein a band gap energy of an indium gallium phosphide layer (InGaP) included in an epitaxial layer, is set to 01-10-2013
20130020614DUAL-GATE NORMALLY-OFF NITRIDE TRANSISTORS - A dual-gate normally-off nitride transistor that includes a first gate structure formed between a source electrode and a drain electrode for controlling a normally-off channel region of the dual-gate normally-off nitride transistor. A second gate structure is formed between the first gate structure and the drain electrode for modulating a normally-on channel region underneath the second gate structure. The magnitude of the threshold voltage of the second gate structure is smaller than the drain breakdown of the first gate structure for proper operation of the dual-gate normally-off nitride transistor.01-24-2013
20130168737Integrated Heterojunction Semiconductor Device and Method for Producing an Integrated Heterojunction Semiconductor Device - A method of producing a semiconductor component is provided. The method includes providing a silicon substrate having a <111>-surface defining a vertical direction, forming in the silicon substrate at least one electronic component, forming at least two epitaxial semiconductor layers on the silicon substrate to form a heterojunction above the <111>-surface, and forming a HEMT-structure above the <111>-surface.07-04-2013
20080224173Fabrication Transistors - A method for fabricating transistors such as high electron mobility transistors, each transistor comprising a plurality of epitaxial layers on a common substrate, method comprising: (a) forming a plurality of source contacts on a first surface of the plurality of epitaxial layers; (b) forming at least one drain contact on the first surface; (c) forming at least one gate contact on the first surface; (d) forming at least one insulating layer over and between the gate contacts, source contacts and the drain contacts; (e) forming a conductive layer over at least a part of the at least one insulating layer for connecting the source contacts; and (f) forming at least one heat sink layer over the conductive layer.09-18-2008
20110260217SEMICONDUCTOR APPARATUS AND METHOD OF MANUFACTURING THE SAME - There is provided a semiconductor apparatus capable of achieving both a reverse blocking characteristic and a low on-resistance. The semiconductor apparatus includes a first semiconductor layer including a channel layer, a source electrode formed on the first semiconductor layer, a drain electrode formed at a distance from the source electrode on the first semiconductor layer, and a gate electrode formed between the source electrode and the drain electrode on the first semiconductor layer. The drain electrode includes a first drain region where reverse current between the first semiconductor layer and the first drain region is blocked, and a second drain region formed at a greater distance from the gate electrode than the first drain region, where a resistance between the first semiconductor layer and the second drain region is lower than a resistance between the first semiconductor layer and the first drain region.10-27-2011
20110260216GaN BASED POWER DEVICES WITH INTEGRATED PROTECTION DEVICES: STRUCUTRES AND METHODS - Exemplary embodiments provide structures and methods for power devices with integrated clamp structures. The integration of clamp structures can protect the power device, e.g., from electrical overstress (EOS). In one embodiment, active devices can be formed over a substrate, while a clamp structure can be integrated outside the active regions of the power device, for example, under the active regions and/or inside the substrate. Integrating clamp structure outside active regions of power devices can maximize the active area for a given die size and improve robustness of the clamped device since the current will spread in the substrate by this integration.10-27-2011
20100012977SEMICONDUCTOR DEVICE - A semiconductor device is disclosed. In one aspect, the device has a first and second active layer on a substrate, the second active layer having a higher bandgap than the first active layer, being substantially Ga-free and including at least Al01-21-2010
20130134482SUBSTRATE BREAKDOWN VOLTAGE IMPROVEMENT FOR GROUP III-NITRIDE ON A SILICON SUBSTRATE - A method of making a high-electron mobility transistor (HEMT) includes forming an unintentionally doped gallium nitride (UID GaN) layer over a silicon substrate, a donor-supply layer over the UID GaN layer, a gate, a passivation layer over the gate and portions of the donor-supply layer, an ohmic source structure and an ohmic drain structure over the donor-supply layer and portions of the passivation layer. The source structure includes a source contact portion and an overhead portion. The overhead portion overlaps the passivation layer between the source contact portion and the gate, and may overlap a portion of the gate and a portion of the passivation layer between the gate and the drain structure.05-30-2013
20130175580GALLIUM NITRIDE POWER DEVICES - Enhancement mode III-nitride devices are described. The 07-11-2013
20130099286COMPOUND SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A first GaN layer, a first AlGaN layer, a second GaN layer and a third GaN layer are formed in layers on a substrate. A second AlGaN layer is formed on the sidewall of an opening formed in the multilayer structure. A gate electrode is formed to fill an electrode trench in an insulating film. A portion of the insulating film between the gate electrode and the second AlGaN layer functions as a gate insulating film. A source electrode is formed above the gate electrode and a drain electrode is formed below the gate electrode. This configuration enables implementation of a miniatuarizable, reliable vertical HEMT that has a sufficiently high withstand voltage and high output power and is capable of a normally-off operation without problems that could otherwise result from the use of a p-type compound semiconductor.04-25-2013
20130099284GROUP III-NITRIDE METAL-INSULATOR-SEMICONDUCTOR HETEROSTRUCTURE FIELD-EFFECT TRANSISTORS - Embodiments of the present disclosure describe apparatuses, methods, and systems of an integrated circuit (IC) device such as, for example, a high electron mobility transistor (HEMT) or metal-insulator-semiconductor field-effect transistor (MISFET), or combinations thereof. The IC device includes a buffer layer formed on a substrate, a barrier layer formed on the buffer layer, the barrier layer including aluminum (Al), nitrogen (N), and at least one of indium (In) and gallium (Ga), a cap layer formed on the barrier layer, the cap layer including nitrogen (N) and at least one of indium (In) and gallium (Ga), and a gate formed on the cap layer, the gate being directly coupled with the cap layer. Other embodiments may also be described and/or claimed.04-25-2013
20130099285HIGH ELECTRON MOBILITY TRANSISTOR HAVING REDUCED THRESHOLD VOLTAGE VARIATION AND METHOD OF MANUFACTURING THE SAME - According to example embodiments a transistor includes a channel layer on a substrate, a first channel supply layer on the channel, a depletion layer, a second channel supply layer, source and drain electrodes on the first channel supply layer, and a gate electrode on the depletion layer. The channel includes a 2DEG channel configured to generate a two-dimensional electron gas and a depletion area. The first channel supply layer corresponds to the 2DEG channel and defines an opening that exposes the depletion area. The depletion layer is on the depletion area of the channel layer. The second channel supply layer is between the depletion layer and the depletion area.04-25-2013
20110272743High Electron Mobility Transistors Including Lightly Doped Drain Regions And Methods Of Manufacturing The Same - High electron mobility transistors (HEMTs) including lightly doped drain (LDD) regions and methods of manufacturing the same. A HEMT includes a source, a drain, a gate, a channel supplying layer for forming at least a 2-dimensional electron gas (2DEG) channel, and a channel formation layer in which at least the 2DEG channel is formed. The channel supplying layer includes a plurality of semiconductor layers having different polarizabilities. A portion of the channel supplying layer is recessed. One of the plurality of semiconductor layers, which is positioned below an uppermost layer is an etching buffer layer, as well as a channel supplying layer.11-10-2011
20110272742COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFCTURING SAME - A compound semiconductor device includes a substrate; a compound semiconductor layer formed on the substrate; a first insulating film formed on the compound semiconductor layer; a second insulating film formed on the first insulating film; and a gate electrode, a source electrode, and a drain electrode, each being formed on the compound semiconductor layer, wherein the gate electrode is formed of a first opening filled with a first conductive material via at least a gate insulator, and the first opening is formed in the first insulating film and configured to partially expose the compound semiconductor layer, and wherein the source electrode and the drain electrode are formed of a pair of second openings filled with at least a second conductive material, and the second openings are formed in at least the second insulating film and the first insulating film and configured to partially expose the compound semiconductor layer.11-10-2011
20110272741High electron mobility transistors and methods of manufacturing the same - High electron mobility transistors (HEMTs) and methods of manufacturing the same. A HEMT may include a source electrode, a gate electrode, a drain electrode, a channel formation layer including at least a 2-dimensional electron gas (2DEG) channel, a channel supplying layer for forming the 2DEG channel in the channel formation layer, a portion of the channel supplying layer including a first oxygen treated region. The channel supplying layer may include a second oxygen treated region that extends from the first oxygen treated region towards the drain electrode, and the depth and concentration of oxygen of the second oxygen treated region may be less than those of the first oxygen treated region.11-10-2011
20110220966ROBUST TRANSISTORS WITH FLUORINE TREATMENT - A semiconductor device, and particularly a high electron mobility transistor (HEMT), having a plurality of epitaxial layers and experiencing an operating (E) field. A negative ion region in the epitaxial layers to counter the operating (E) field. One method for fabricating a semiconductor device comprises providing a substrate and growing epitaxial layers on the substrate. Negative ions are introduced into the epitaxial layers to form a negative ion region to counter operating electric (E) fields in the semiconductor device. Contacts can be deposited on the epitaxial layers, either before or after formation of the negative ion region.09-15-2011
20110220965COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a compound semiconductor device, includes: forming a compound semiconductor lamination structure over a substrate; forming a metal film over the compound semiconductor lamination structure; forming a source electrode and a drain electrode over the metal film; forming one of a metal oxide film and a metal nitride film by one of oxidizing and nitriding a part of the metal film; and forming a gate electrode over the metal oxide film or the metal nitride film.09-15-2011
20110233614COMPOUND SEMICONDUCTOR EPITAXIAL SUBSTRATE AND MANUFACTURING METHOD THEREOF - A compound semiconductor epitaxial substrate having a pseudomorphic high electron mobility field effect transistor structure including an InGaAs layer as a strained channel layer and an AlGaAs layer containing n type impurities as a front side electron-donating layer, wherein said substrate contains an InGaP layer in an orderly state on the front side of the above described InGaAs layer as the strained channel layer.09-29-2011
20110233613SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - There are provided a semiconductor device and a method for manufacturing the same. The semiconductor device according to the present invention includes a base substrate; a semiconductor layer that includes a receiving groove and a protrusion part formed on the base substrate, a first carrier injection layer and at least two insulating layers formed to traverse the first carrier injection layer formed in the semiconductor layer, and a second carrier injection layer spaced apart from the first carrier injection layer formed on the protrusion part; a source electrode and a drain electrode that are disposed to be spaced apart from each other on the semiconductor layer; and a gate electrode that is insulated from the source electrode and the drain electrode and has a recess part recessed into the receiving groove, wherein the lowest end portion of the receiving groove contacts the uppermost layer of the first carrier injection layer and the insulating pattern disposed at the innermost side of the semiconductor layer among the insulating patterns traverses the entire layer forming the first carrier injection layer and is disposed at the outer side of both side end portions in the thickness direction of the receiving groove.09-29-2011
20130153967Compound Semiconductor Device with Buried Field Plate - A semiconductor device includes a first compound semiconductor material and a second compound semiconductor material on the first compound semiconductor material. The second compound semiconductor material comprises a different material than the first compound semiconductor material such that the first compound semiconductor material has a two-dimensional electron gas (2DEG). The semiconductor device further includes a buried field plate disposed in the first compound semiconductor material and electrically connected to a terminal of the semiconductor device. The 2DEG is interposed between the buried field plate and the second compound semiconductor material.06-20-2013
20090050938MIS GATE STRUCTURE TYPE HEMT DEVICE AND METHOD OF FABRICATING MIS GATE STRUCTURE TYPE HEMT DEVICE - A normally-off operation type HEMT device excellent in characteristics can be realized. A two-dimensional electron gas region is formed in a periphery of a hetero-junction interface of a base layer and a barrier layer, so that access resistance in an access portion, that is, between a drain and a gate and between a gate and a source is sufficiently lowered, and at the same time, a P-type region is formed immediately under the gate. This realizes a normally-off type HEMT device having a low on-resistance. Further, when a film thickness of an insulating layer is defined as t (nm) and a relative permittivity of a substance forming the insulating layer is defined as k, a threshold voltage as high as +3 V or more can be attained by satisfying k/t≦0.85 (nm02-26-2009
20100065888High mobility tri-gate devices and methods of fabrication - A high mobility semiconductor assembly. In one exemplary aspect, the high mobility semiconductor assembly includes a first substrate having a first reference orientation located at a <110> crystal plane location on the first substrate and a second substrate formed on top of the first substrate. The second substrate has a second reference orientation located at a <100> crystal plane location on the second substrate, wherein the first reference orientation is aligned with the second reference orientation. In another exemplary aspect, the second substrate has a second reference orientation located at a <110> crystal plane location on the second substrate, wherein the second substrate is formed over the first substrate with the second reference orientation being offset to the first reference orientation by about 45 degrees.03-18-2010
20110303952High Electron Mobility Transistors And Methods Of Fabricating The Same - A High electron mobility transistor (HEMT) includes a source electrode, a gate electrode, a drain electrode, a channel forming layer in which a two-dimensional electron gas (2DEG) channel is induced, and a channel supplying layer for inducing the 2DEG channel in the channel forming layer. The source electrode and the drain electrode are located on the channel supplying layer. A channel increase layer is between the channel supplying layer and the source and drain electrodes. A thickness of the channel supplying layer is less than about 15 nm.12-15-2011
20130187197HIGH ELECTRON MOBILITY TRANSISTOR AND MANUFACTURING METHOD THEREOF - Disclosed is a manufacturing method of a high electron mobility transistor. The method includes: forming a source electrode and a drain electrode on a substrate; forming a first insulating film having a first opening on an entire surface of the substrate, the first opening exposing a part of the substrate; forming a second insulating film having a second opening within the first opening, the second opening exposing a part of the substrate; forming a third insulating film having a third opening within the second opening, the third opening exposing a part of the substrate; etching a part of the first insulating film, the second insulating film and the third insulating film so as to expose the source electrode and the drain electrode; and forming a T-gate electrode on a support structure including the first insulating film, the second insulating film and the third insulating film.07-25-2013
20130193486SEMICONDUCTOR DEVICE - A semiconductor device includes: a second nitride semiconductor layer formed on a first nitride semiconductor layer, and having a larger band gap than the first nitride semiconductor layer; and an electrode filling a recess formed in the first and second nitride semiconductor layers. The first nitride semiconductor layer has a two-dimensional electron gas layer immediately below the second nitride semiconductor layer. The electrode and the second nitride semiconductor layer are in contact with each other at a first contact interface. The electrode and a portion of the first nitride semiconductor layer corresponding to the two-dimensional electron gas layer are in contact with each other at a second contact interface connected below the first contact interface. The first contact interface is formed such that a width of the recess increases upward. The second contact interface is more steeply inclined than the first contact interface.08-01-2013
20130193485COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - An embodiment of a compound semiconductor device includes: an electron transit layer; an electron supply layer formed over the electron transit layer; a two-dimensional electron gas suppressing layer formed over the electron supply layer; an insulating film formed over the two-dimensional electron gas suppressing layer and the electron transit layer; and a gate electrode formed over the insulating film. The gate electrode is electrically connected with the two-dimensional electron gas suppressing layer.08-01-2013
20130193487HIGH ELECTRON MOBILITY TRANSISTORS WITH FIELD PLATE ELECTRODE - A high electron mobility transistor comprising: 08-01-2013
20120025270ENHANCEMENT-MODE HIGH-ELECTRON-MOBILITY TRANSISTOR AND THE MANUFACTURING METHOD THEREOF - This invention discloses an enhancement-mode high-electron-mobility transistor and the manufacturing method thereof. The transistor comprises an epitaxial buffer layer on a substrate, a source and drain formed in the buffer layer, a PN-junction stack formed on the buffer layer and located between the source and drain, and a gate formed on the PN-junction stack, wherein the PN-junction stack is composed of alternating layers of a P-type semiconductor and an N-type semiconductor.02-02-2012
20130200435SEMICONDUCTOR DEVICES WITH FIELD PLATES - A III-N device is described with a III-N material layer, an insulator layer on a surface of the III-N material layer, an etch stop layer on an opposite side of the insulator layer from the III-N material layer, and an electrode defining layer on an opposite side of the etch stop layer from the insulator layer. A recess is formed in the electrode defining layer. An electrode is formed in the recess. The insulator can have a precisely controlled thickness, particularly between the electrode and III-N material layer.08-08-2013
20120068227SEMICONDUCTOR DEVICE - A normally off semiconductor device with a reduced off-state leakage current, which is applicable to a power switching element, includes: a substrate; an undoped GaN layer formed above the substrate; an undoped AlGaN layer formed on the undoped GaN layer; a source electrode and a drain electrode, formed on the undoped GaN layer or the undoped AlGaN layer; a P-type GaN layer formed on the undoped AlGaN layer and disposed between the source electrode and the drain electrode; and a gate electrode formed on the P-type GaN layer, wherein the undoped GaN layer includes an active region including a channel and an inactive region not including the channel, and the P-type GaN layer is disposed to surround the source electrode.03-22-2012
20120086049E-Mode High Electron Mobility Transistor And Method Of Manufacturing The Same - According to an example embodiment, a high electron mobility transistor (HEMT) includes a substrate, a buffer layer on the substrate, a channel layer on the buffer layer, and a barrier structure on the channel layer. The buffer layer includes a 2-dimensional electron gas (2DEG). A polarization of the barrier structure varies in a region corresponding to a gate electrode. The HEMT further includes and the gate electrode, a source electrode, and a drain electrode on the barrier structure.04-12-2012

Patent applications in class Doping on side of heterojunction with lower carrier affinity (e.g., high electron mobility transistor (HEMT))

Patent applications in all subclasses Doping on side of heterojunction with lower carrier affinity (e.g., high electron mobility transistor (HEMT))