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Field effect transistor

Subclass of:

257 - Active solid-state devices (e.g., transistors, solid-state diodes)

257183000 - HETEROJUNCTION DEVICE

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Class / Patent application numberDescriptionNumber of patent applications / Date published
257194000 Doping on side of heterojunction with lower carrier affinity (e.g., high electron mobility transistor (HEMT)) 255
Entries
DocumentTitleDate
20090278171High linearity doped-channel FET - A high linearity doped-channel FET, comprises a substrate, a buffer layer, a channel layer and a cap layer stacked downwardly thereon. The cap layer has a source region, a drain region with a distance apart from the source region and a gate region formed by removing part of the cap layer between the source region and the drain region. A source electrode and a drain electrode are respectively formed on the source region and the drain region, and a gate electrode is formed on the gate region, wherein the source region and the drain region of the cap layer are respectively provided with an opening for forming a good ohmic contact between the source region and the drain region with the channel layer respectively.11-12-2009
20130043506Fin-FET and Method of Forming the Same - A method of forming a Fin-FET is provided. A substrate is provided, then a mask layer is formed thereabove. A first trench is formed in the substrate and the mask layer. A semiconductor layer is formed in the first trench. Next, the mask layer is removed such that the semi-conductive layer becomes a fin structure embedded in the substrate and protruded above the substrate. Finally, a gate layer is formed on the fin structure.02-21-2013
20110198670METHOD TO REDUCE MOL DAMAGE ON NiSi - Transistor devices are formed with nickel silicide layers formulated to prevent degradation upon removal of overlying stress liners. Embodiments include transistors with nickel silicide layers having a platinum composition gradient increasing in platinum content toward the upper surfaces thereof, i.e., increasing in platinum in a direction away from the gate electrode and source/drain regions. Embodiments include forming a first layer of nickel having a first amount of platinum and forming, on the first layer of nickel, a second layer of nickel having a second amount of platinum, the second weight percent of platinum being greater than the first weight percent. The layers of nickel are then annealed to form a nickel silicide layer having the platinum composition gradient increasing in platinum toward the upper surface. The platinum concentration gradient protects the nickel silicide layer during subsequent processing, as during etching to remove overlying stress liners, thereby avoiding a decrease in device performance.08-18-2011
20110198669TRANSISTOR AND METHOD FOR FABRICATING THE SAME - The invention provides a transistor having a leak current between a source and drain in a nitride compound semiconductor formed on a substrate that is reduced. A gate electrode, a source electrode and a drain electrode are formed respectively on the surface of the nitride compound semiconductor formed on the silicon substrate in the transistor. At least one of the source electrode and the drain electrode is surrounded by an auxiliary electrode connected with the gate electrode. Because a depletion layer is formed in the nitride compound semiconductor under the auxiliary electrode, a route of the leak current is shut off and the leak current between the source and drain may be effectively reduced.08-18-2011
20120199877MEMORY DEVICES WITH A CONNECTING REGION HAVING A BAND GAP LOWER THAN A BAND GAP OF A BODY REGION - Memory devices are shown that include a body region and a connecting region that is formed from a semiconductor with a lower band gap than the body region. Connecting region configurations can provide increased gate induced drain leakage during an erase operation. Configurations shown can provide a reliable bias to a body region for memory operations such as erasing, and containment of charge in the body region during a boost operation.08-09-2012
20130026540METHODS AND APPARATUS FOR FORMING SEMICONDUCTOR STRUCTURES - Methods and apparatus for forming semiconductor structures are disclosed herein. In some embodiments, a semiconductor structure may include a first germanium carbon layer having a first side and an opposing second side; a germanium-containing layer directly contacting the first side of the first germanium carbon layer; and a first silicon layer directly contacting the opposing second side of the first germanium carbon layer. In some embodiments, a method of forming a semiconductor structure may include forming a first germanium carbon layer atop a first silicon layer; and forming a germanium-containing layer atop the first germanium carbon layer.01-31-2013
20130026539REPLACEMENT SOURCE/DRAIN FINFET FABRICATION - A finFET is formed having a fin with a source region, a drain region, and a channel region between the source and drain regions. The fin is etched on a semiconductor wafer. A gate stack is formed having an insulating layer in direct contact with the channel region and a conductive gate material in direct contact with the insulating layer. The source and drain regions are etched leaving the channel region of the fin. Epitaxial semiconductor is grown on the sides of the channel region that were adjacent the source and drain regions to form a source epitaxy region and a drain epitaxy region. The source and drain epitaxy regions are doped in-situ while growing the epitaxial semiconductor.01-31-2013
20110180850Configuration and manufacturing method of low-resistance gate structures for semiconductor devices and circuits - The present invention provides methods for fabricating devices with low resistance structures involving a lift-off process. A radiation blocking layer is introduced between two resist layers in order to prevent intermixing of the photoresists. Cavities suitable for the formation of low resistance T-gates or L-gates can be obtained by a first exposure, developing, selective etching of blocking layer and a second exposure and developing. In another embodiment, a low resistance gate structure with pillars to enhance mechanical stability or strength is provided.07-28-2011
20130043507Semiconductor Device with a Buried Stressor - A semiconductor device, such as a PMOS or NMOS device, having localized stressors is provided. Recesses are formed on opposing sides of a gate electrode. A stress-inducing region is formed along a bottom of the recess, and a stressed layer is formed over the stress-inducing region. By having a stress-inducing region with a larger lattice structure than the stressed layer, a tensile strain may be created in a channel region of the semiconductor device and may be suitable for an NMOS device. By having a stress-inducing region with a smaller lattice structure than the stressed layer, a compressive strain may be created in the channel region of the semiconductor device and may be suitable for a PMOS device. Embodiments may be applied to various types of substrates and semiconductor devices, such as planar transistors and finFETs.02-21-2013
20130043505APPARATUSES AND METHODS COMPRISING A CHANNEL REGION HAVING DIFFERENT MINORITY CARRIER LIFETIMES - Apparatuses, such as memory devices, memory cell strings, and electronic systems, and methods of forming such apparatuses are shown. One such apparatus includes a channel region that has a minority carrier lifetime that is lower at one or more end portions, than in a middle portion. Other apparatuses and methods are also disclosed.02-21-2013
20090194790Field effect transister and process for producing the same - A field effect transistor has an MOS structure and is formed of a nitride based compound semiconductor. The field effect transistor includes a substrate; a semiconductor operating layer having a recess part and formed on the substrate; an insulating layer formed on the semiconductor operating layer including the recess part; a gate electrode formed on the insulating layer at the recess part; and a source electrode and a drain electrode formed on the semiconductor operating layer with the recess part in between and electrically connected to the semiconductor operating layer. The recess part includes a side wall protruding and inclined relative to the semiconductor operating layer.08-06-2009
20090194791COMPOUND SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A compound semiconductor device including an electron transport layer that is formed on a substrate and includes a III-V nitride compound semiconductor, a gate insulating film that is positioned above the compound semiconductor layer, and a gate electrode that is positioned on the gate insulating film. The gate insulating film includes a first insulating film that includes oxygen, at least a single metal element selected from a metal bonding with the oxygen and forming a metal oxide having a dielectric constant no less than 10, and at least a single metal element selected from Si and Al.08-06-2009
20120168820JUNCTION FIELD EFFECT TRANSISTOR STRUCTURE WITH P-TYPE SILICON GERMANIUM OR SILICON GERMANIUM CARBIDE GATE(S) AND METHOD OF FORMING THE STRUCTURE - Disclosed are embodiments of a junction field effect transistor (JFET) structure with one or more P-type silicon germanium (SiGe) or silicon germanium carbide (SiGeC) gates (i.e., a SiGe or SiGeC based heterojunction JFET). The P-type SiGe or SiGeC gate(s) allow for a lower pinch off voltage (i.e., lower Voff) without increasing the on resistance (Ron). Specifically, SiGe or SiGeC material in a P-type gate limits P-type dopant out diffusion and, thereby ensures that the P-type gate-to-N-type channel region junction is more clearly defined (i.e., abrupt as opposed to graded). By clearly defining this junction, the depletion layer in the N-type channel region is extended. Extending the depletion layer in turn allows for a faster pinch off (i.e., requires lower Voff). P-type SiGe or SiGeC gate(s) can be incorporated into conventional lateral JFET structures and/or vertical JFET structures. Also disclosed herein are embodiments of a method of forming such a JFET structure.07-05-2012
20090309134SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A multilayer structure including a first electron supply layer and a second electron supply layer is used for an electron supply layer. A multilayer structure including an SiN film and an SiO12-17-2009
20120175678REPLACEMENT SPACER FOR TUNNEL FETS - A semiconductor fabrication method includes depositing a dummy gate layer onto a substrate, patterning the dummy gate layer, depositing a hardmask layer over the dummy gate layer, patterning the hardmask layer, etching a recess into the substrate, adjacent the dummy gate layer, depositing a semiconductor material into the recess, removing the hardmask layer, depositing replacement spacers onto the dummy gate layer, performing an oxide deposition over the dummy gate layer and replacement spacers, removing the dummy gate and replacement spacers, thereby forming a gate recess in the oxide and depositing a gate stack into the recess.07-12-2012
20100078681Integrated Circuit Including a Hetero-Interface and Self Adjusted Diffusion Method for Manufacturing the Same - An integrated circuit including a hetero-interface and a manufacturing method thereof is disclosed. One embodiment includes forming a hetero-structure including a hetero-interface at a junction between a first region and a second region, and, thereafter introducing a material into the first region and at least up to the hetero-interface, wherein a diffusion constant of the material is higher in the first region than in the second region.04-01-2010
20100072516NITRIDE SEMICONDUCTOR DEVICE - A nitride semiconductor device includes an active layer formed between an n-type cladding layer and a p-type cladding layer, and a current confining layer having a conductive area through which a current flows to the active layer. The current confining layer includes a first semiconductor layer, a second semiconductor layer and a third semiconductor layer. The second semiconductor layer is formed on and in contact with the first semiconductor layer and has a smaller lattice constant than that of the first semiconductor layer. The third semiconductor layer is formed on and in contact with the second semiconductor layer and has a lattice constant that is smaller than that of the first semiconductor layer and larger than that of the second semiconductor layer.03-25-2010
20130032859EPITAXIAL EXTENSION CMOS TRANSISTOR - A pair of horizontal-step-including trenches are formed in a semiconductor layer by forming a pair of first trenches having a first depth around a gate structure on the semiconductor layer, forming a disposable spacer around the gate structure to cover proximal portions of the first trenches, and by forming a pair of second trenches to a second depth greater than the first depth. The disposable spacer is removed, and selective epitaxy is performed to form an integrated epitaxial source and source extension region and an integrated epitaxial drain and drain extension region. A replacement gate structure can be formed after deposition and planarization of a planarization dielectric layer and subsequent removal of the gate structure and laterally expand the gate cavity over expitaxial source and drain extension regions. Alternately, a contact-level dielectric layer can be deposited directly on the integrated epitaxial regions and contact via structures can be formed therein.02-07-2013
20100032716SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate; a buffer layer; and a compound semiconductor layer laminated on the substrate with the buffer layer in between. The buffer layer has a dislocation density in a plane in parallel to an in-plane direction thereof, so that a volume resistivity of the buffer layer becomes a substantially maximum value.02-11-2010
20100044754STRAINED TRANSISTOR INTEGRATION FOR CMOS - Various embodiments of the invention relate to a CMOS device having (1) an NMOS channel of silicon material selectively deposited on a first area of a graded silicon germanium substrate such that the selectively deposited silicon material experiences a tensile strain caused by the lattice spacing of the silicon material being smaller than the lattice spacing of the graded silicon germanium substrate material at the first area, and (2) a PMOS channel of silicon germanium material selectively deposited on a second area of the substrate such that the selectively deposited silicon germanium material experiences a compressive strain caused by the lattice spacing of the selectively deposited silicon germanium material being larger than the lattice spacing of the graded silicon germanium substrate material at the second area.02-25-2010
20100044753SEMICONDUCTOR DEVICE - A nitride semiconductor device 02-25-2010
20100044752Semiconductor device and manufacturing method - A metal-insulator-semiconductor high electron mobility transistor (MIS-HEMT) has a substrate in which an electron supply layer is interposed between an electron channel layer and the surface of the substrate. A pair of main electrodes are formed on the surface of the substrate. A recess is formed in the surface of the substrate between the main electrodes. A gate insulation film is formed on the surface of the substrate, at least between the first and second main electrodes, covering the inside walls and floor of the recess. A gate electrode is formed on the gate insulation film, filling in the recess. The gate insulation film has a crystal density of at least 2.9 g/cm02-25-2010
20100044751ENHANCEMENT MODE III-NITRIDE DEVICE WITH FLOATING GATE AND PROCESS FOR ITS MANUFACTURE - An enhancement mode III-Nitride device has a floating gate spaced from a drain electrode which is programmed by charges injected into the floating gate to form a permanent depletion region which interrupts the 2-DEG layer beneath the floating gate. A conventional gate is formed atop the floating gate and is insulated therefrom by a further dielectric layer. The device is a normally off E mode device and is turned on by applying a positive voltage to the floating gate to modify the depletion layer and reinstate the 2-DEG layer. The device is formed by conventional semiconductor fabrication techniques.02-25-2010
20120205716Epitaxially Grown Extension Regions for Scaled CMOS Devices - Epitaxially grown extension regions are disclosed for scaled CMOS devices. Semiconductor devices are provided that comprise a field effect transistor (FET) structure having a gate stack on a silicon substrate, wherein the field effect transistor structure comprises at least a channel layer formed below the gate stack. One or more etched extension regions containing an epitaxially grown dopant are provided in the channel layer.08-16-2012
20090159929HETEROSTRUCTURE DEVICE AND ASSOCIATED METHOD - A heterostructure device includes a semiconductor multi-layer structure that has a first region, a second region and a third region. The first region is coupled to a source electrode and the second region is coupled to a drain electrode. The third region is disposed between the first region and the second region. The third region provides a switchable electrically conductive pathway from the source electrode to the drain electrode. The third region includes iodine ions. A system includes a heterostructure field effect transistor that includes the device.06-25-2009
20130082304FinFET Device and Method Of Manufacturing Same - A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a fin structure disposed over the substrate. The fin structure includes one or more fins. The semiconductor device further includes an insulation material disposed on the substrate. The semiconductor device further includes a gate structure disposed on a portion of the fin structure and on a portion of the insulation material. The gate structure traverses each fin of the fin structure. The semiconductor device further includes a source and drain feature formed from a material having a continuous and uninterrupted surface area. The source and drain feature includes a surface in a plane that is in direct contact with a surface in a parallel plane of the insulation material, each of the one or more fins of the fin structure, and the gate structure.04-04-2013
20130087832Tucked Active Region Without Dummy Poly For Performance Boost and Variation Reduction - In one embodiment, a semiconductor device is provided that includes a semiconductor substrate including an active region and at least one trench isolation region at a perimeter of the active region, and a functional gate structure present on a portion of the active region of the semiconductor substrate. Embedded semiconductor regions are present in the active region of the semiconductor substrate on opposing sides of the portion of the active region that the functional gate structure is present on. A portion of the active region of the semiconductor substrate separates the outermost edge of the embedded semiconductor regions from the at least one isolation region. Methods of forming the aforementioned device are also provided.04-11-2013
20130087833SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The present invention discloses a semiconductor device, comprising: a substrate, a channel layer epitaxially grown in the substrate, a gate stack structure on the channel layer, gate spacers on both sides of the gate stack structure, and source/drain areas on both sides of the channel layer in the substrate, characterized in that the carrier mobility of the channel layer is higher than that of the substrate. In accordance with the semiconductor device and the method of manufacturing the same in the present invention, forming the device channel region by filling the trench with epitaxial high-mobility materials in a gate last process can enhance the carrier mobility in the channel region, thereby the device response speed is substantially improved and the device performance is greatly enhanced. Furthermore, traditional materials for a substrate are still used for the source/drain areas of the device to facilitate usage of a gate last process, thereby enhancing the performance while reducing the cost at the same time.04-11-2013
20120181578PRE-GATE, SOURCE/DRAIN STRAIN LAYER FORMATION - A method produces a transistor. The method forms a strain-producing layer on a base layer and then removes at least one portion of the strain-producing layer to create at least one opening in the strain-producing layer. This leaves first and second portions of the strain-producing layer on the substrate. The first and second portions of the strain-producing layer comprise source and drain stressor regions of the transistor. The method then grows a channel region in the opening of the strain-producing layer from the base layer, forms a gate insulator on the channel region, and forms a gate conductor on the gate insulator.07-19-2012
20090045438FIELD EFFECT TRANSISTOR, AND MULTILAYERED EPITAXIAL FILM FOR USE IN PREPARATION OF FIELD EFFECT TRANSISTOR - In a group III nitride-type field effect transistor, the present invention reduces a leak current component by conduction of residual carriers in a buffer layer, and achieves improvement in a break-down voltage, and enhances a carrier confinement effect (carrier confinement) of a channel to improve pinch-off characteristics (to suppress a short channel effect). For example, when applying the present invention to a GaN-type field effect transistor, besides GaN of a channel layer, a composition-modulated (composition-gradient) AlGaN layer in which aluminum composition reduces toward a top gradually or stepwise is used as a buffer layer (hetero buffer). To gate length Lg of a FET to be prepared, a sum a of layer thicknesses of an electron supply layer and a channel layer is selected so as to fulfill Lg/a≧5, and in such a case, the layer thickness of the channel layer is selected in a range of not exceeding 5 times (about 500 Å) as long as a de Broglie wavelength of two-dimensional electron gas accumulated in the channel layer in room temperature.02-19-2009
20130049068FINFET DEVICE HAVING A CHANNEL DEFINED IN A DIAMOND-LIKE SHAPE SEMICONDUCTOR STRUCTURE - The present disclosure provides a FinFET device. The FinFET device comprises a semiconductor substrate of a first semiconductor material; a fin structure of the first semiconductor material overlying the semiconductor substrate, wherein the fin structure has a top surface of a first crystal plane orientation; a diamond-like shape structure of a second semiconductor material disposed over the top surface of the fin structure, wherein the diamond-like shape structure has at least one surface of a second crystal plane orientation; a gate structure disposed over the diamond-like shape structure, wherein the gate structure separates a source region and a drain region; and a channel region defined in the diamond-like shape structure between the source and drain regions.02-28-2013
20090057718High Temperature Ion Implantation of Nitride Based HEMTS - A method is disclosed for forming a high electron mobility transistor. The method includes the steps of implanting a Group III nitride layer at a defined position with ions that when implanted produce an improved ohmic contact between the layer and contact metals, with the implantation being carried out at a temperature higher than room temperature and hot enough to reduce the amount of damage done to the Group III nitride layer, but below a temperature at which surface problems causing leakage at the gate or epitaxial layer dissociation would occur. An ohmic contact selected from the group consisting of titanium, aluminum, nickel and alloys thereof is added to the implanted defined position on the Group III nitride layer.03-05-2009
20090302349STRAINED GERMANIUM FIELD EFFECT TRANSISTOR AND METHOD OF FABRICATING THE SAME - A strained germanium field effect transistor (FET) and method of fabricating the same is related to the strained Ge field effect transistor with a thin and pure Ge layer as a carrier channel. The pure Ge layer with the thickness between 1 nm and 10 nm is formed between an unstrained substrate and a gate insulation layer, and directly contacts with the unstrained substrate. The gate is disposed on the gate insulation layer. The germanium layer is used as a carrier transport channel of the strained Ge FET to improve the drive current and the carrier mobility, and to increase the devices performance effectively. Furthermore, a Si protective layer with extremely thin thickness can be deposed between and directly contacts with the gate insulation layer and the pure Ge layer.12-10-2009
20090302350Tensile Strained NMOS Transistor Using Group III-N Source/Drain Regions - Enhancement mode transistors are described where a Group III-N compound is used in the source and drain regions to place tensile strain on the channel. The source and drain regions may be raised or embedded, and fabricated in conjunction with recessed or raised compression regions for p channel transistors.12-10-2009
20090146183Method of forming a germanium silicide layer, semiconductor device including the germanium silicide layer, and method of manufacturing the semiconductor device - Example embodiments relate to a method of forming a germanium (Ge) silicide layer, a semiconductor device including the Ge silicide layer, and a method of manufacturing the semiconductor device. A method of forming a Ge silicide layer according to example embodiments may include forming a metal layer including vanadium (V) on a silicon germanium (SiGe) layer. The metal layer may have a multiple-layer structure and may further include at least one of platinum (Pt) and nickel (Ni). The metal layer may be annealed to form the germanium silicide layer. The annealing may be performed using a laser spike annealing (LSA) method.06-11-2009
20130056796Novel Method to Increase Breakdown Voltage of Semiconductor Devices - Methods of achieving high breakdown voltages in semiconductor devices by suppressing the surface flashover using high dielectric strength insulating encapsulation material are generally described. In one embodiment of the present invention, surface flashover in AlGaN/GaN heterostructure field-effect transistors (HFETs) is suppressed by using high dielectric strength insulating encapsulation material. Surface flashover in as-fabricated III-Nitride based HFETs limits the operating voltages at levels well below the breakdown voltages of GaN.03-07-2013
20120112243Bipolar and FET Device Structure - A semiconductor structure includes a heterojunction bipolar transistor (HBT) including a collector layer located over a substrate, the collector layer including a semiconductor material, and a field effect transistor (FET) located over the substrate, the FET having a channel formed in the semiconductor material that forms the collector layer of the HBT.05-10-2012
20120305987LATERAL TRENCH MESFET - A transistor includes a trench formed in a semiconductor body, the trench having sidewalls and a bottom. The transistor further includes a first semiconductor material disposed in the trench adjacent the sidewalls and a second semiconductor material disposed in the trench and spaced apart from the sidewalls by the first semiconductor material. The second semiconductor material has a different band gap than the first semiconductor material. The transistor also includes a gate material disposed in the trench and spaced apart from the first semiconductor material by the second semiconductor material. The gate material provides a gate of the transistor. Source and drain regions are arranged in the trench with a channel interposed between the source and drain regions in the first or second semiconductor material so that the channel has a lateral current flow direction along the sidewalls of the trench.12-06-2012
20100084686ASSYMETRIC HETERO-DOPED HIGH-VOLTAGE MOSFET (AH2MOS) - An asymmetric heterodoped metal oxide (AH04-08-2010
20090267114FIELD EFFECT TRANSISTOR - A field effect transistor 10-29-2009
20110012174Structure and Method for Forming Field Effect Transistor with Low Resistance Channel Region - A trench-gate field effect transistor includes trenches extending into a silicon region of a first conductivity type, and a gate electrodes in each trench. Body regions of second conductivity type extend over the silicon region between adjacent trenches. Each body region forms a PN junction with the silicon region. A gate dielectric layer lines at least upper sidewalls of each trench, and insulates the gate electrode from the body region. Source regions of the first conductivity flank the trenches. A silicon-germanium region vertically extends through each source region and through a corresponding body region, and terminates within the corresponding body region before reaching the PN junction.01-20-2011
20110012173SEMICONDUCTOR DEVICE - A semiconductor device includes an undoped GaN layer (01-20-2011
20120193679HETEROJUNCTION TUNNELING FIELD EFFECT TRANSISTORS, AND METHODS FOR FABRICATING THE SAME - The present invention relates to a heterojunction tunneling effect transistor (TFET), which comprises spaced apart source and drain regions with a channel region located therebetween and a gate stack located over the channel region. The drain region comprises a first semiconductor material and is doped with a first dopant species of a first conductivity type. The source region comprises a second, different semiconductor material and is doped with a second dopant species of a second, different conductivity type. The gate stack comprises at least a gate dielectric and a gate conductor. When the heterojunction TFET is an n-channel TFET, the drain region comprises n-doped silicon, while the source region comprises p-doped silicon germanium. When the heterojunction TFET is a p-channel TFET, the drain region comprises p-doped silicon, while the source region comprises n-doped silicon carbide.08-02-2012
20130069115FIELD EFFECT TRANSISTOR - A field effect transistor includes a nitride semiconductor multilayer structure formed on a substrate, a source electrode, a drain electrode, a gate electrode, an insulating film formed on the nitride semiconductor multilayer structure, and a field plate formed on and in contact with the insulating film, and having an end located between the gate electrode and the drain electrode. The insulating film includes a first film, and a second film having a dielectric breakdown voltage lower than that of the first film, and a thin film portion formed between the gate electrode and the drain electrode is formed in the insulating film. The field plate covers the thin film portion, and is connected to the source electrode in an opening.03-21-2013
20130069114High-Voltage Normally-Off Field Effect Transistor - A device having a channel with multiple voltage thresholds is provided. The channel can include a first section located adjacent to a source electrode, which is a normally-off channel and a second section located between the first section and a drain electrode, which is a normally-on channel. The device can include a charge-controlling electrode connected to the source electrode, which extends from the source electrode over at least a portion of the second section of the channel. During operation of the device, a potential difference between the charge-controlling electrode and the channel can control the on/off state of the normally-on section of the channel.03-21-2013
20130069113COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - An embodiment of a compound semiconductor device includes: a Si substrate; a Si oxide layer formed over a surface of the Si substrate; a nucleation layer formed over the Si oxide layer, the nucleation layer exposing a part of the Si oxide layer; and a compound semiconductor stacked structure formed over the Si oxide layer and the nucleation layer.03-21-2013
20130069112SRAM CELL AND METHOD FOR MANUFACTURING THE SAME - A SRAM cell and a method for manufacturing the same are disclosed. In one embodiment, the SRAM cell may comprise a substrate and a first Fin Field Effect Transistor (FinFET) and a second FinFET formed on the substrate. The first FinFET may comprise a first fin which is formed in a semiconductor layer provided on the substrate and abuts the semiconductor layer, and the second FinFET may comprise a second fin which is formed in the semiconductor layer and abuts the semiconductor layer. The semiconductor layer may comprise a plurality of semiconductor sub-layers. The first and second fins can comprise different number of the semiconductor sub-layers and have different heights from each other.03-21-2013
20130069111STRAINED SEMICONDUCTOR DEVICES HAVING ASYMMETRICAL HETEROJUNCTION STRUCTURES AND METHODS FOR THE FABRICATION THEREOF - Embodiments of a strained semiconductor device are provided, as are embodiments of a method for fabricating such a strained semiconductor device. In one embodiment, the method includes providing a partially-fabricated semiconductor device including a semiconductor substrate having a source side and a drain side, a gate stack formed on the semiconductor substrate, and a channel region formed within the semiconductor substrate beneath the gate stack and extending from the source side to the drain side of the semiconductor substrate. A cavity is produced in only one of the source side and the drain side of the semiconductor substrate, and a strain-inducing material is formed within the cavity to create an asymmetric heterojunction structure within the semiconductor substrate.03-21-2013
20130161693THIN HETEREOSTRUCTURE CHANNEL DEVICE - A method of fabricating a semiconductor device that includes providing a substrate having at least a first semiconductor layer atop a dielectric layer, wherein the first semiconductor layer has a first thickness of less than 10 nm. The first semiconductor layer is etched with a a halide based gas at a temperature of less than 675° C. to a second thickness that is less than the first thickness. A second semiconductor layer is epitaxially formed on an etched surface of the first semiconductor layer. A gate structure is formed directly on the second semiconductor layer. A source region and a drain region is formed on opposing sides of the gate structure.06-27-2013
20130161695REDUCTION OF THICKNESS VARIATIONS OF A THRESHOLD SEMICONDUCTOR ALLOY BY REDUCING PATTERNING NON-UNIFORMITIES PRIOR TO DEPOSITING THE SEMICONDUCTOR ALLOY - The growth rate in a selective epitaxial growth process for depositing a threshold adjusting semiconductor alloy, such as a silicon/germanium alloy, may be enhanced by performing a plasma-assisted etch process prior to performing the selective epitaxial growth process. For example, a mask layer may be patterned on the basis of the plasma-assisted etch process, thereby simultaneously providing superior device topography during the subsequent growth process. Hence, the threshold adjusting material may be deposited with enhanced thickness uniformity, thereby reducing overall threshold variability.06-27-2013
20130161696TUNNEL FIELD-EFFECT TRANSISTOR AND METHODS FOR MANUFACTURING THEREOF - A tunnel Field Effect Transistor is provided comprising an interface between a source and a channel, the source side of this interface being a layer of a first crystalline semiconductor material being substantially uniformly doped with a metal to the solubility level of the metal in the first crystalline material and the channel side of this interface being a layer of this first crystalline semiconductor material doped with this metal, the concentration decreasing towards the channel.06-27-2013
20130161697REPLACEMENT GATE MOSFET WITH RAISED SOURCE AND DRAIN - A disposable dielectric spacer is formed on sidewalls of a disposable material stack. Raised source/drain regions are formed on planar source/drain regions by selective epitaxy. The disposable dielectric spacer is removed to expose portions of a semiconductor layer between the disposable material stack and the source/drain regions including the raised source/drain regions. Dopant ions are implanted to form source/drain extension regions in the exposed portions of the semiconductor layer. A gate-level dielectric layer is deposited and planarized. The disposable material stack is removed and a gate stack including a gate dielectric and a gate electrode fill a cavity formed by removal of the disposable material stack. Optionally, an inner dielectric spacer may be formed on sidewalls of the gate-level dielectric layer within the cavity prior to formation of the gate stack to tailor a gate length of a field effect transistor.06-27-2013
20130161692SHIELD WRAP FOR A HETEROSTRUCTURE FIELD EFFECT TRANSISTOR - Devices are disclosed for providing heterojunction field effect transistor (HFETs) having improved performance and/or reduced noise generation. A gate electrode is over a portion of the active region and is configured to modulate a conduction channel in the active region of an HFET. The active region is in a semiconductor film between a source electrode and a drain electrode. A first passivation film is over the active region. An encapsulation film is over the first passivation film. A first metal pattern on the encapsulation film includes a shield wrap over the majority of the active region and is electrically connected to the source electrode06-27-2013
20130161694THIN HETEREOSTRUCTURE CHANNEL DEVICE - A method of fabricating a semiconductor device that includes providing a substrate having at least a first semiconductor layer atop a dielectric layer, wherein the first semiconductor layer has a first thickness of less than 10 nm. The first semiconductor layer is etched with a halide based gas at a temperature of less than 675° C. to a second thickness that is less than the first thickness. A second semiconductor layer is epitaxially formed on an etched surface of the first semiconductor layer. A gate structure is formed directly on the second semiconductor layer. A source region and a drain region is formed on opposing sides of the gate structure.06-27-2013
20110127579STACKED OXIDE MATERIAL, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE - One embodiment is a method for manufacturing a stacked oxide material, including the steps of forming a first oxide component over a base component, causing crystal growth which proceeds from a surface toward an inside of the first oxide component by first heat treatment to form a first oxide crystal component at least partly in contact with the base component, forming a second oxide component over the first oxide crystal component; and causing crystal growth by second heat treatment using the first oxide crystal component as a seed to form a second oxide crystal component.06-02-2011
20120139006DEVICES AND METHODOLOGIES RELATED TO STRUCTURES HAVING HBT AND FET - A semiconductor structure includes a heterojunction bipolar transistor (HBT) including a collector layer located over a substrate, the collector layer including a semiconductor material, and a field effect transistor (FET) located over the substrate, the FET having a channel formed in the semiconductor material that forms the collector layer of the HBT. In some implementations, a second FET can be provided so as to be located over the substrate and configured to include a channel formed in a semiconductor material that forms an emitter of the HBT. One or more of the foregoing features can be implemented in devices such as a die, a packaged module, and a wireless device.06-07-2012
20090108297SEMI-INSULATING NITRIDE SEMICONDUCTOR SUBSTRATE AND METHOD OF MANUFACTURING THE SAME, NITRIDE SEMICONDUCTOR EPITAXIAL SUBSTRATE, AND FIELD-EFFECT TRANSISTOR - A method of manufacturing a semi-insulating nitride semiconductor substrate includes the steps of forming on an underlying substrate, a mask in which dotted or striped coating portions having a width or a diameter Ds from 10 μm to 100 μm are arranged at an interval Dw from 250 μm to 2000 μm, growing a nitride semiconductor crystal on the underlying substrate with an HVPE method at a growth temperature from 1040° C. to 1150° C. by supplying a group III raw material gas and a group V raw material gas of which group V/group III ratio R04-30-2009
20100258843ENHANCEMENT MODE GaN HEMT DEVICE AND METHOD FOR FABRICATING THE SAME - An enhancement-mode GaN transistor and a method of forming it. The enhancement-mode GaN transistor includes a substrate, transition layers, a buffer layer comprised of a III Nitride material, a barrier layer comprised of a III Nitride material, drain and source contacts, a gate III-V compound containing acceptor type dopant elements, and a gate metal, where the gate III-V compound and the gate metal are formed with a single photo mask process to be self-aligned and the bottom of the gate metal and the top of the gate compound have the same dimension. The enhancement mode GaN transistor may also have a field plate made of Ohmic metal, where a drain Ohmic metal, a source Ohmic metal, and the field plate are formed by a single photo mask process.10-14-2010
20090152590METHOD AND STRUCTURE FOR SEMICONDUCTOR DEVICES WITH SILICON-GERMANIUM DEPOSITS - A method of forming a semiconductor device including forming a second deposit of silicon-germanium on a first deposit of silicon-germanium, the first deposit formed in a conduction terminal region of a substrate of the semiconductor device and having a first percentage of germanium, and the second deposit having a second percentage of germanium that is less than the first percentage and supports forming a silicide deposit on the second deposit. A structure is also provided.06-18-2009
20100078683SEMICONDUCTOR DEVICE - A semiconductor device include: a nitride group semiconductor functional layer including a second nitride group semiconductor region on a first nitride group semiconductor region where a two-dimensional carrier gas layer is made, the second nitride group semiconductor region functioning as a barrier layer; a first main electrode electrically connected to one end of the two-dimensional carrier gas layer; a second main electrode electrically connected to the other end of the two-dimensional carrier gas layer; and metal oxide films placed between the first and second main electrodes, electrically connected to the first main electrode, and reducing a carrier density of the two-dimensional carrier gas layer.04-01-2010
20090315076TRANSISTOR GATE ELECTRODE HAVING CONDUCTOR MATERIAL LAYER - Various embodiments of the invention relate to a PMOS device having a transistor channel of silicon germanium material on a substrate, a gate dielectric having a dielectric constant greater than that of silicon dioxide on the channel, a gate electrode conductor material having a work function in a range between a valence energy band edge and a conductor energy band edge for silicon on the gate dielectric, and a gate electrode semiconductor material on the gate electrode conductor material.12-24-2009
20110018033SEMICONDUCTOR WAFER, SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - It is an objective of the present invention to form a favorable interface between an oxide layer and a group 3-5 compound semiconductor using a practical and simple method.01-27-2011
20090294801METHODS OF INTEGRATING REVERSE eSiGe ON NFET AND SiGe CHANNEL ON PFET, AND RELATED STRUCTURE - Methods of integrating reverse embedded silicon germanium (SiGe) on an NFET and SiGe channel on a PFET, and a related structure are disclosed. One method may include providing a substrate including an NFET area and a PFET area; performing a single epitaxial growth of a silicon germanium (SiGe) layer over the substrate; forming an NFET in the NFET area, the NFET including a SiGe plug in a channel thereof formed from the SiGe layer; and forming a PFET in the PFET area, the PFET including a SiGe channel formed from the SiGe layer. As an option, the SiGe layer over the PFET area may be thinned.12-03-2009
20090140295GaN-based semiconductor device and method of manufacturing the same - A GaN-based semiconductor device includes a silicon substrate; an active layer of a GaN-based semiconductor formed on the silicon substrate; a trench formed in the active layer and extending from a top surface of the active layer to the silicon substrate; a first electrode formed on an internal wall surface of the trench so that the first electrode extends from the top surface of the active layer to the silicon substrate; a second electrode formed on the active layer so that a current flows between the first electrode and the second electrode via the active layer; and a bottom electrode formed on a bottom surface of the silicon substrate. The first electrode is formed of a metal capable of being in ohmic contact with the silicon substrate and the active layer.06-04-2009
20110260214SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - The present invention discloses a semiconductor device and a method for manufacturing the same, and relates to the field of semiconductor manufacturing. According to the present invention, the semiconductor device comprises: a semiconductor substrate; a gate region located above the semiconductor substrate; S/D regions located at both sides of the gate region and made of a stress material; wherein a concentrated stress region is formed between the gate region and the semiconductor substrate, and the concentrated stress region comprises an upper SOI layer adjacent to the gate region above, and a lower stress release layer adjacent to the semiconductor substrate below. The present invention applies to the manufacturing of a MOSFET.10-27-2011
20090278172GaN based semiconductor element - The field effect transistor includes a laminated structure in which a buffer layer, and an electron transporting layer (undoped GaN layer), and an electron supplying layer (undoped AlGaN layer) are laminated in sequence on a sapphire substrate. An npn laminated structure is formed on a source region of the electron supplying layer, and a source electrode is formed on the npn laminated structure. A drain electrode is formed in a drain region of the electron supplying layer, and an insulating film is formed in an opening region formed in the gate region. When a forward voltage greater than a threshold is applied to the gate electrode, an inversion layer is formed and the drain current flows. By changing a thickness and an impurity concentration of the p-type GaN layer, the threshold voltage can be controlled. The electrical field concentration between the gate electrode and the drain electrode is relaxed due to the drift layer, and voltage resistance improves.11-12-2009
20120025268SEMICONDUCTOR WAFER, METHOD OF PRODUCING SEMICONDUCTOR WAFER, AND ELECTRONIC DEVICE - There is provided a compound semiconductor wafer that is suitably used as a semiconductor wafer to form a plurality of different types of devices such as an HBT and an FET thereon. The semiconductor wafer includes a first semiconductor, a carrier-trapping layer that is formed on the first semiconductor and has an electron-trapping center or a hole-trapping center, a second semiconductor that is epitaxially grown on the carrier-trapping layer and serves as a channel in which a free electron or a free hole moves, and a third semiconductor including a stack represented by n-type semiconductor/p-type semiconductor/n-type semiconductor or represented by p-type semiconductor/n-type semiconductor/p-type semiconductor, where the stack epitaxially grown on the second semiconductor.02-02-2012
20120025267MOS DEVICE FOR ELIMINATING FLOATING BODY EFFECTS AND SELF-HEATING EFFECTS - A SOI MOS device for eliminating floating body effects and self-heating effects are disclosed. The device includes a connective layer coupling the active gate channel to the Si substrate. The connective layer provides electrical and thermal passages during device operation, which could eliminate floating body effects and self-heating effects. An example of a MOS device having a SiGe connector between a Si active channel and a Si substrate is disclosed in detail and a manufacturing process is provided.02-02-2012
20090189189SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - An exemplary embodiment provides a semiconductor device, in which a junction leakage current is reduced in MISFET including a source/drain impurity layer formed in a semiconductor region containing Ge, and a semiconductor device manufacturing method. The semiconductor device includes a channel region which is formed in a semiconductor substrate; a gate insulator which is formed on a surface of the channel region; a gate electrode which is formed on the gate insulator; and source/drain impurity layers which are formed on both sides of the channel region. In the semiconductor device, at least part of the source/drain impurity layer is formed in a semiconductor region containing Ge in the semiconductor substrate, and at least an element selected from a group including S, Se, and Te is contained in the semiconductor region which is deeper than a junction depth of the source/drain impurity layer.07-30-2009
20090189188SEMICONDUCTOR DEVICE AND FABRICATION METHOD OF THE SEMICONDUCTOR DEVICE - A semiconductor device and a fabrication method of the semiconductor device, the semiconductor device including: a substrate; a nitride based compound semiconductor layer placed on the substrate and doped with a first transition metal atom; an aluminum gallium nitride layer (Al07-30-2009
20090189187Active area shaping for Ill-nitride device and process for its manufacture - A III-nitride heterojunction power semiconductor device that includes a passivation body with a gate well having a top mouth that is wider than the bottom mouth thereof, and a method of fabrication for the same.07-30-2009
20090189186Group III Nitride Semiconductor Device and Epitaxial Substrate - Affords Group III nitride semiconductor devices in which the leakage current from the Schottky electrode can be reduced. In a high electron mobility transistor 07-30-2009
20080272397SEMICONDUCTOR DEVICE WITH MODULATED FIELD ELEMENT - The current invention introduces a modulated field element incorporated into the semiconductor device outside the controlling electrode and active areas. This element changes its conductivity and/or dielectric properties depending on the electrical potentials of the interface or interfaces between the modulated field element and the semiconductor device and/or incident electromagnetic radiation. The element is either connected to only one terminal of the semiconductor device, or not connected to any terminal of a semiconductor device nor to its active area(s). Such an element can be used as modulated field plate, or a part of a field plate, as a passivation layer or its part, as a guard ring or its part, as a smart field or charge control element or its part, as a feedback element or its part, as a sensor element or its part, as an additional electrode or its part, as an electromagnetic signal path or its part, and/or for any other functions optimizing or modernizing device performance.11-06-2008
20090121258FIELD EFFECT TRANSISTOR CONTAINING A WIDE BAND GAP SEMICONDUCTOR MATERIAL IN A DRAIN - A field effect transistor comprising a silicon containing body is provided. After formation of a gate dielectric, gate electrode, and a first gate spacer, a drain side trench is formed and filled with a wide band gap semiconductor material. Optionally, a source side trench may be formed and filled with a silicon germanium alloy to enhance an on-current of the field effect transistor. Halo implantation and source and drain ion implantation are performed to form various doped regions. Since the wide band gap semiconductor material as a wider band gap than that of silicon, impact ionization is reduced due to the use of the wide band gap semiconductor material in the drain, and consequently, a breakdown voltage of the field effect transistor is increased compared to transistors employing silicon in the drain region.05-14-2009
20090166677SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes: a semiconductor substrate; a diode having a cathode formed on a first surface side of the semiconductor substrate and an anode formed on a second surface side of the semiconductor substrate; and a transistor formed over the semiconductor substrate. The transistor includes a semiconductor layer laminate formed over the semiconductor substrate, a source electrode and a drain electrode that are formed spaced apart from each other over the semiconductor layer laminate, and a gate electrode formed between the source electrode and the drain electrode. The source electrode is electrically connected to the anode, and the drain electrode is electrically connected to the cathode.07-02-2009
20090146184SEMICONDUCTOR DEVICE WITH T-GATE ELECTRODE AND METHOD FOR FABRICATING THE SAME - Provided are a semiconductor device with a T-gate electrode capable of improving stability and a high frequency characteristic of the semiconductor device by reducing source resistance, parasitic capacitance, and gate resistance and a method of fabricating the same. In the semiconductor device, in order to form source and drain electrodes and the T-gate electrode on a substrate, first and second protective layers constructed with silicon oxide layers or silicon nitride layers are formed on sides of a supporting part under a head part of the T-gate electrode, and the second protective layer constructed with a silicon oxide layer or silicon nitride layer is formed on sides of the source and drain electrodes. Accordingly, it is possible to protect an activated region of the semiconductor device and reduce gate-drain parasitic capacitance and gate-source parasitic capacitance.06-11-2009
20090095984DIELECTRIC INTERFACE FOR GROUP III-V SEMICONDUCTOR DEVICE - A Group III-V Semiconductor device and method of fabrication is described. A high-k dielectric is interfaced to a confinement region by a chalcogenide region.04-16-2009
20090095983SEMICONDUCTOR DEVICE AND METHOD OF MAKING SAME - In one example embodiment, an integrated semiconductor circuit (04-16-2009
20110260215GALLIUM LATHANIDE OXIDE FILMS - Electronic apparatus and methods of forming the electronic apparatus include a gallium lanthanide oxide film for use in a variety of electronic systems. The gallium lanthanide oxide film may be structured as one or more monolayers. The gallium lanthanide oxide film may be formed using atomic layer deposition.10-27-2011
20080237638SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate common to a first field effect transistor and a second field effect transistor, a channel layer of a first conductivity type formed on the substrate and common to the first and second field effect transistors, a an upper compound semiconductor layer formed on the channel layer and common to the first and second field effect transistors, a compound semiconductor region of a second conductivity type formed in the same layer as the upper compound semiconductor layer, a gate electrode of the first field effect transistor in ohmic contact with the compound semiconductor region, and a gate electrode of the second field effect transistor in Schottky contact with the upper compound semiconductor layer.10-02-2008
20080296621III-nitride heterojunction device - A III-nitride heterojunction semiconductor device having a III-nitride heterojunction that includes a discontinuous two-dimensional electron gas under a gate thereof.12-04-2008
20110193134STEP DOPING IN EXTENSIONS OF III-V FAMILY SEMICONDUCTOR DEVICES - The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a buffer layer over a substrate, the buffer layer containing a first compound semiconductor that includes elements from one of: III-V families of a periodic table; and II-VI families of the periodic table. The method includes forming a channel layer over the buffer layer. The channel layer contains a second compound semiconductor that includes elements from the III-V families of the periodic table. The method includes forming a gate over the channel layer. The method includes depositing impurities on regions of the channel layer on either side of the gate. The method includes performing an annealing process to activate the impurities in the channel layer.08-11-2011
20090212326Hetero Field Effect Transistor and Manufacturing Method Thereof - A hetero field effect transistor includes: a first semiconductor layer; a second semiconductor layer formed on the first semiconductor layer to allow a generation of a two dimensional carrier gas layer of a first conductive type on a heterojunction interface between the first semiconductor layer and the second semiconductor layer; a third semiconductor layer formed on the second semiconductor layer and having an impurity introduced therein; a source electrode formed on the third semiconductor layer; a drain electrode formed on the third semiconductor layer and separated from the source electrode; a fourth semiconductor layer formed on or above the second semiconductor layer and has a second conductive type which is different from the first conductive type; and a gate electrode electrically connected on the fourth semiconductor layer. The fourth semiconductor layer is located adjacent to and surrounded by the third semiconductor layer.08-27-2009
20120228674SEMICONDUCTOR DEVICE, FIELD-EFFECT TRANSISTOR, AND ELECTRONIC DEVICE - Provided is a semiconductor device capable of suppressing an occurrence of a punch-through phenomenon.09-13-2012
20090267113SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device has a semiconductor base of a first conductivity type; a hetero semiconductor region in contact with the semiconductor base; a gate electrode adjacent to a portion of a junction between the hetero semiconductor region and the semiconductor base across a gate insulating film; a source electrode connected to the hetero semiconductor region; and a drain electrode connected to the semiconductor base. The hetero semiconductor region has a band gap different from that of the semi-conductor base. The hetero semiconductor region includes a first hetero semiconductor region and a second hetero semiconductor region. The first hetero semiconductor region is formed before the gate insulating film is formed. The second hetero semiconductor region is formed after the gate insulating film is formed.10-29-2009
20100084685SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes an SiGe film formed on part of a semiconductor substrate and including a channel region and at least part of source/drain extension regions between which the channel region is positioned, source/drain contact regions formed in a surface area of the semiconductor substrate and brought into contact with the pair of source/drain extension regions, a gate structure having a gate insulation film formed on the SiGe film and a gate electrode formed on the gate insulation film, first sidewall films formed on the SiGe film along side surfaces of the gate structure, second sidewall films formed on the SiGe film along the first sidewall films, third sidewall films formed on the source/drain contact regions along side surfaces of the SiGe film and the second sidewall films, and first silicide films formed on the source/drain contact regions.04-08-2010
20090230428DEVICES USING ABRUPT METAL-INSULATOR TRANSITION LAYER AND METHOD OF FABRICATING THE DEVICE - The abrupt metal-insulator transition device includes: an abrupt metal insulator transition material layer including an energy gap of less than or equal to 09-17-2009
20110062497SEMICONDUCTOR DEVICE STRUCTURE WITH STRAIN LAYER AND METHOD OF FABRICATING THE SEMICONDUCTOR DEVICE STRUCTURE - A semiconductor device with a strain layer and a method of fabricating the semiconductor device with a strain layer that can reduce a loading effect are provided. By arranging active dummies and gate dummies not to overlap each other, the area of active dummy on which a strain layer dummy will be formed can be secured, thereby reducing the loading effect.03-17-2011
20110062496Methods and Compositions for Preparing Ge/Si Semiconductor Substrates - The present disclosure describes methods for preparing semiconductor structures, comprising forming a Ge layer on a semiconductor substrate using an admixture of (a) (GeH03-17-2011
20110062495Field Effect Transistor with Access Region Recharge - The current invention provides the design of the field effect transistor with lateral channel suitable for high voltage switching. In such a transistor, the electrical charge stored in the high electric field region has to vary as the transistor switches from ON to OFF state and back. The invention provides the method of calculating the necessary recharging path parameters based on the material parameters of the FET and desired blocking voltage, ON state resistance and switching speed. The invention can be used in power electronics by providing circuits and parts, for example, for electrical power distribution between power plant customers, for automotive, craft and space applications and many other applications where high voltage in excess of 400-600 V is involved.03-17-2011
20110062494STRUCTURE WITH ISOTROPIC SILICON RECESS PROFILE IN NANOSCALE DIMENSIONS - A trench is formed by an anisotropic etch in a semiconductor material layer employing a masking layer, which can be gate spacers. In one embodiment, an adsorbed fluorine layer is provided at a cryogenic temperature only on vertical sidewalls of the semiconductor structure including the sidewalls of the trench. The adsorbed fluorine layer removes a controlled amount of the underlying semiconductor material once the temperature is raised above the cryogenic temperature. The trench can be filled with another semiconductor material to generate stress in the semiconductor material layer. In another embodiment, the semiconductor material is laterally etched by a plasma-based etch at a controlled rate while a horizontal portion of a contiguous oxide liner prevents etch of the semiconductor material from the bottom surface of the trench.03-17-2011
20110169053SEMICONDUCTOR DEVICE - A semiconductor device includes an undoped InGaAs layer; an Si-doped GaAs layer formed thereover and equipped with a first recess portion; a two-layered semiconductor layer formed between the undoped InGaAs layer and the Si-doped GaAs layer, equipped with a second recess portion provided in the first recess portion, and composed of an undoped ordered InGaP layer and an undoped GaAs layer formed thereover; a C-doped GaAs layer provided over the undoped InGaAs layer in the second recess portion; and a sidewall insulating film provided between the C-doped GaAs layer and the interface between the undoped GaAs layer and the undoped ordered InGaP layer, but not provided at a portion between the undoped ordered InGaP layer and the C-doped GaAs layer.07-14-2011
20110169051Structure for Use in Fabrication of PiN Heterojunction TFET - A method for fabricating a structure for use in fabrication of a PiN heterojunction tunnel field effect transistor (TFET) includes forming an alignment trench in a silicon wafer; forming a silicon germanium (SiGe) growth trench in the silicon wafer; growing a p-type SiGe region in the SiGe growth trench; forming a first oxide layer over the alignment trench and the p-type SiGe region; forming a hydrogen implantation region in the silicon wafer, the hydrogen implantation region dividing the silicon wafer into a upper silicon region and a lower silicon region; bonding the first oxide layer to a second oxide layer located on a handle wafer, forming a bonded oxide layer comprising the first oxide layer and the second oxide layer; and separating the lower silicon region from the upper silicon region at the hydrogen implantation region.07-14-2011
20110169052MEMFET RAM - A non-volatile field-effect device. The non-volatile field-effect device includes a source, a drain, a channel-formation portion and a memristive gate. The channel-formation portion is disposed between and coupled with the source and the drain. The memristive gate is disposed over the channel-formation portion and coupled with the channel-formation portion. The memristive gate includes a plurality of mobile ions and a confinement structure for the plurality of mobile ions. Moreover, the memristive gate is configured to switch the channel-formation portion from a first conductivity state to a second conductivity state in response to migration of the plurality of mobile ions within the confinement structure.07-14-2011
20090294802FIELD EFFECT TRANSISTOR WITH FREQUENCY DEPENDENT GATE-CHANNEL CAPACITANCE - A field effect transistor having a channel, a gate, and a means for decreasing a gate-to-channel capacitance of the transistor as an operating frequency of the transistor increases. The means can comprise, for example, a barrier layer disposed between the gate and the channel, which has a dielectric permittivity and/or a conductivity that varies with an operating frequency of the transistor. In an embodiment, the barrier layer comprises a conducting material, such as conducting polymer, conducting semiconductor, conducting semi-metal, amorphous silicon, polycrystalline silicon, and/or the like.12-03-2009
20090294800HYBRID FET INCORPORATING A FINFET AND A PLANAR FET - A stack of a vertical fin and a planar semiconductor portion are formed on a buried insulator layer of a semiconductor-on-insulator substrate. A hybrid field effect transistor (FET) is formed which incorporates a finFET located on the vertical fin and a planar FET located on the planar semiconductor portion. The planar FET enables a continuous spectrum of on-current. The surfaces of the vertical fin and the planar semiconductor portion may be set to coincide with crystallographic orientations. Further, different crystallographic orientations may be selected for the surfaces of the vertical fin and the surfaces of the planar semiconductor portion to tailor the characteristics of the hybrid FET.12-03-2009
20100283083Normally-off field effect transistor using III-nitride semiconductor and method for manufacturing such transistor - Provided is a normally-off field effect transistor using a III-nitride semiconductor. The transistor is provided with a III-nitride semiconductor layer grown on a substrate by including an acceptor and a donor; a gate insulating film which is formed on the III-nitride semiconductor layer to have a thickness to be at a prescribed threshold voltage based on the concentration of the acceptor and that of the donor; a gate electrode formed on the gate insulating film; a first source/drain electrode formed on the III-nitride semiconductor layer to one side of and separate from the gate electrode, directly or via a high dopant concentration region; and a second source/drain electrode formed away from the gate electrode and the first source/drain electrode, on or under the III-nitride semiconductor layer, directly or via a high dopant concentration region.11-11-2010
20090026497Method for Producing Semiconductor Device - A method for producing a semiconductor device (01-29-2009
20090261383OPTICAL DEVICE HAVING STRAINED BURIED CHANNEL - Provided is an optical device having a strained buried channel area. The optical device includes: a semiconductor substrate of a first conductive type; a gate insulating layer formed on the semiconductor substrate; a gate of a second conductive type opposite to the first conductive type, formed on the gate insulating layer; a high density dopant diffusion area formed in the semiconductor substrate under the gate and doped with a first conductive type dopant having a higher density than the semiconductor substrate; a strained buried channel area formed of a semiconductor material having a different lattice parameter from a material of which the semiconductor substrate is formed and extending between the gate insulating layer and the semiconductor substrate to contact the high density dopant diffusion area; and a semiconductor cap layer formed between the gate insulating layer and the strained buried channel area.10-22-2009
20100102357NITRIDE SEMICONDUCTOR DEVICE - A nitride semiconductor device includes: a main semiconductor region comprising a first nitride semiconductor layer having a first band gap, and a second nitride semiconductor layer having a second band gap larger than the first band gap, a heterojunction being formed between the first nitride semiconductor layer and the second nitride semiconductor layer such that a two-dimensional electron gas layer can be caused inside the first nitride semiconductor layer based on the heterojunction; a source electrode; a drain electrode; a third nitride semiconductor layer formed on the first nitride semiconductor layer and between the source electrode and the drain electrode; a fourth nitride semiconductor layer formed on the third nitride semiconductor layer and having p-type conductivity; and a gate electrode formed on the fourth nitride semiconductor layer. The third nitride semiconductor layer has a third band gap smaller than the first band gap.04-29-2010
20080277692SEMICONDUCTOR DEVICE - A semiconductor device includes: a first semiconductor layer made of an Al11-13-2008
20080290371SEMICONDUCTOR DEVICES INCLUDING IMPLANTED REGIONS AND PROTECTIVE LAYERS - A semiconductor structure includes a Group III-nitride semiconductor layer, a protective layer on the semiconductor layer, a distribution of implanted dopants within the semiconductor layer, and an ohmic contact extending through the protective layer to the semiconductor layer.11-27-2008
20080290370Semiconductor devices and methods of manufacturing thereof - Semiconductor devices and methods of manufacturing thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes providing a workpiece, and forming a recess in the workpiece. The recess has a depth having a first dimension. A first semiconductive material is formed in the recess to partially fill the recess in a central region to a height having a second dimension. The second dimension is about one-half or greater of the first dimension. A second semiconductive material is formed over the first semiconductive material in the recess to completely fill the recess, the second semiconductive material being different than the first semiconductive material.11-27-2008
20080303063Capacitorless DRAM and methods of manufacturing the same - Provided are a capacitorless DRAM and methods of manufacturing the same. The capacitorless DRAM may include a substrate including a source, a drain and a channel, a gate on the channel of the substrate, and a hole reserving unit below the channel.12-11-2008
20080308844Spin Transistor Using Perpendicular Magnetization - A spin transistor useful for device miniaturization and high-density integration is provided. The spin transistor includes: a semiconductor substrate including a channel layer; ferromagnetic source and drain disposed on the semiconductor substrate to be separated from each other and to be magnetized in a direction perpendicular to a surface of the channel layer; a gate formed on the semiconductor substrate between the source and the drain to adjust spins of electrons passing through the channel layer, wherein spin-polarized electrons are injected from the source to the channel layer, and the electrons injected into the channel layer pass though the channel layer and are injected into the drain, and wherein the spins of the electrons passing through the channel layer undergo precession due to a spin-orbit coupling induced magnetic field according to a voltage of the gate.12-18-2008
20120292664Integrated Circuit (IC) Chip Having Both Metal and Silicon Gate Field Effect Transistors (FETs) and Method of Manufacture - Field Effect Transistors (FETs), Integrated Circuit (IC) chips including the FETs, and a method of forming the FETs on ICs. FET locations are defined on a layered semiconductor wafer, preferably a Silicon On Insulator (SOI) wafer. One or more FET locations are defined as silicon gate locations and remaining as Replacement Metal Gate (RMG) FET locations with at least one of each on the IC. Polysilicon gates are formed in all FET locations. Gates in silicon gate locations are tailored, e.g., doped and silicided. Remaining polysilicon gates are replaced with metal in RMG FET locations. FETs are connected together into circuits with RMG FETs being connected to silicon gate FETs.11-22-2012
20110006346SEMICONDUCTOR DEVICE - The present invention provides a semiconductor device that has high electron mobility while reducing a gate leakage current, and superior uniformity and reproducibility of the threshold voltage, and is also applicable to the enhancement mode type. The semiconductor device according to the present invention is a semiconductor device having such a structure formed by sequentially laminating a lower barrier layer composed of lattice-relaxed Al01-13-2011
20090026498FIELD EFFECT TRANSISTOR AND METHOD FOR FABRICATING THE SAME - A field effect transistor includes: a nitride semiconductor layer having a channel layer; a gate electrode including a Schottky electrode that contacts the nitride semiconductor layer and includes a gallium doped zinc oxide (GZO) layer annealed in an inactive gas atmosphere; and ohmic electrodes connecting with the channel layer.01-29-2009
20090085063COMPOUND SEMICONDUCTOR DEVICE WITH T-SHAPED GATE ELECTRODE AND ITS MANUFACTURE - A method for manufacturing a compound semiconductor device forms an EB resist layer on first SiN film, performs EB exposure at high dose for recess forming opening and at low dose for eaves removing opening, develops the high dose EB resist pattern to etch the first SiN film, selectively etches the cap layer to form a recess wider than the opening of the first SiN film leaving eaves of SiN, develops the low dose EB resist pattern to form the eaves removing opening, etches the first SiN film to extinguish the eaves, forms second SiN film on the exposed surface, forms a resist pattern having a gate electrode opening on the second SiN film to etch the second SiN film, forms a metal layer to form a gate electrode by lift-off. The SiN film in eaves shape will not be left.04-02-2009
20090050937SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device of the present invention includes: a III-V nitride semiconductor layer including a channel region in which carriers travel; a concave portion provided in an upper portion of the channel region in the III-V nitride semiconductor layer; and a Schottky electrode consisting of a conductive material forming a Schottky junction with the semiconductor layer, and formed on a semiconductor layer, which spreads over the concave portion and peripheral portions of the concave portion, on the III-V nitride semiconductor layer. A dimension of the concave portion in a depth direction is set so that a portion of the Schottky electrode provided in the concave portion can adjust a quantity of the carriers traveling in the channel region.02-26-2009
20110140171APPARATUS AND METHODS FOR FORMING A MODULATION DOPED NON-PLANAR TRANSISTOR - Embodiments of an apparatus and methods for providing three-dimensional complementary metal oxide semiconductor devices comprising modulation doped transistors are generally described herein. Other embodiments may be described and claimed.06-16-2011
20110140170STRUCTURE AND METHOD FOR MAKING A STRAINED SILICON TRANSISTOR - A graded SiGe sacrificial layer is epitaxially grown overlying a silicon substrate. A single crystal silicon layer is then grown by an epitaxial process overlying the graded SiGe layer. A SiGe layer is next grown by an epitaxial process as a single crystal layer overlying the silicon layer. A subsequent silicon layer, which becomes the active silicon layer for the transistors, is epitaxially grown overlying the second silicon germanium layer. Together the epitaxially grown Si, SiGe and Si layers form a laminate semiconductor structure. A MOS transistor is then formed on the active area of the single crystal silicon. The graded SiGe sacrificial layer is removed by an etch process to electrically isolate the laminate semiconductor structure from the substrate.06-16-2011
20110140169Highly conductive source/drain contacts in III-nitride transistors - In one embodiment, a method for fabricating a III-Nitride transistor on a III-Nitride semiconductor body is disclosed. The method comprises etching dielectric trenches in a field dielectric overlying gate, source, and drain regions of the III-Nitride semiconductor body, and thereafter forming a gate dielectric over the gate, source and drain regions. The method further comprises forming a blanket diffusion barrier over the gate dielectric layer, and then removing respective portions of the blanket diffusion barrier from the source and drain regions. Thereafter, gate dielectric is removed from the source and drain regions to substantially expose the source and drain regions. Then, ohmic contacts are formed by depositing contact metal in the source and drain regions. The method results in highly conductive source/drain contacts that are particularly suitable for power transistors, for example, III-Nitride transistors, such as GaN transistors. In another embodiment, a structure for highly conductive source/drain contacts is disclosed.06-16-2011
20090200575SEMICONDUCTOR DEVICE - A semiconductor device is provided with a semiconductor region, a gate electrode, a source electrode and a drain electrode. The semiconductor region is formed on a semiconductor substrate surface and includes a first semiconductor portion of a first conducting type, a second semiconductor portion of a second conducting type, a band gap distinct from the substrate's band gap, more than two accumulated semiconductor layers, and junctions between the layers. The semiconductor layers each contain an impurity of the first conducting type. The gate electrode adjoins a heterojunction between the second semiconductor portion and the semiconductor substrate through a gate insulation film. The source electrode is coupled to the semiconductor region. The drain electrode is coupled to the semiconductor substrate.08-13-2009
20090230431SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The present invention has as an objective to provide: a semiconductor device to satisfy both of the trade-off characteristic advantages of the HBT; and the HFET and a manufacturing method thereof. The semiconductor device in the present invention is an HBT and HFET integrated circuit. The HBT includes a sub-collector layer, a GaAs collector layer, a GaAs base layer, and an InGaP emitter layer which are sequentially stacked. The sub-collector layer includes a GaAs external sub-collector region, and a GaAs internal sub-collector region disposed on the GaAs external sub-collector region. A mesa-shaped collector part and a collector electrode are separately formed on the GaAs external sub-collector region. The HFET includes a GaAs cap layer, a source electrode, and a drain electrode, the GaAs cap layer including portion of the GaAs external sub-collector region, and the source electrode and the drain electrode being formed on the GaAs cap layer.09-17-2009
20090230430Field effect transistor - A field effect transistor includes a layer structure made of compound semiconductor (09-17-2009
20090230429Field effect transistor - A field effect transistor (09-17-2009
20090242937Semiconductor device and manufacturing method - A semiconductor device has source and drain electrodes formed on a substrate, a gate insulation film formed on the substrate between the source and drain electrodes, and a gate electrode formed on the gate insulation film. These elements are all covered by a dielectric sub-insulation film. An opening is formed in the sub-insulation film, partially exposing the gate electrode. A field plate extends from the top of the gate electrode down one side of the gate electrode as far as the sub-insulation film covering the gate insulation film, filling the opening. The thickness of the sub-insulation film can be selected to optimize the separation between the field plate and the substrate for the purpose of reducing current collapse by reducing electric field concentration at the edge of the gate electrode.10-01-2009
20090250723Electronic Device and Heterojunction FET - In an electronic device of the present invention a gate Schottky electrode is formed on an active layer constructed of a GaN layer and an AlGaN layer, and a source ohmic electrode and a drain ohmic electrode are further formed on both sides of the gate Schottky electrode on the active layer. A dielectric layer (TiO10-08-2009
20120193680STRUCTURE WITH ISOTROPIC SILICON RECESS PROFILE IN NANOSCALE DIMENSIONS - A trench is formed by an anisotropic etch in a semiconductor material layer employing a masking layer, which can be gate spacers. In one embodiment, an adsorbed fluorine layer is provided at a cryogenic temperature only on vertical sidewalls of the semiconductor structure including the sidewalls of the trench. The adsorbed fluorine layer removes a controlled amount of the underlying semiconductor material once the temperature is raised above the cryogenic temperature. The trench can be filled with another semiconductor material to generate stress in the semiconductor material layer. In another embodiment, the semiconductor material is laterally etched by a plasma-based etch at a controlled rate while a horizontal portion of a contiguous oxide liner prevents etch of the semiconductor material from the bottom surface of the trench.08-02-2012
20120193678FABRICATION OF A VERTICAL HETEROJUNCTION TUNNEL-FET - Exemplary embodiments include a method for fabricating a heterojunction tunnel field-effect-transistor (FET), the method including forming a gate region on a silicon layer of a silicon-on-insulator (SOI) substrate, forming a drain region on the silicon layer adjacent the gate region and forming a vertical heterojunction source region adjacent the gate region, wherein the vertical heterojunction source region generates a tunnel path inline with a gate field associated with the gate region.08-02-2012
20090127584Transistor with a germanium-based channel encased by a gate electrode and method for producing one such transistor - Source and drain electrodes are each formed by an alternation of first and second layers made from a germanium and silicon compound. The first layers have a germanium concentration comprised between 0% and 10% and the second layers have a germanium concentration comprised between 10% and 50%. At least one channel connects two second layers respectively of the source electrode and drain electrode. The method comprises etching of source and drain zones, connected by a narrow zone, in a stack of layers. Then superficial thermal oxidation of said stack is performed so a to oxidize the silicon of the germanium and silicon compound having a germanium concentration comprised between 10% and 50% and to condense the germanium Ge. The oxidized silicon of the narrow zone is removed and a gate dielectric and a gate are deposited on the condensed germanium of the narrow zone.05-21-2009
20100155779Field Effect Transistor - In a field effect transistor, a Group III nitride semiconductor layer structure containing a hetero junction, a source electrode 06-24-2010
20100155780SEMICONDUCTOR DEVICE - An aspect of the present invention inheres in a semiconductor device includes a semiconductor region, a source electrode and a drain electrode, which are provided on a main surface of the semiconductor region, a gate electrode exhibiting normally-off characteristics, the gate electrode being provided above the main surface of the semiconductor region while interposing a p-type material film therebetween, and being arranged between the source electrode and the drain electrode, and a fourth electrode that is provided on the main surface of the semiconductor region, and is arranged between the gate electrode and the drain electrode.06-24-2010
20100187570Heterojunction Transistors Having Barrier Layer Bandgaps Greater Than Channel Layer Bandgaps and Related Methods - A heterojunction transistor may include a channel layer comprising a Group III nitride, a barrier layer comprising a Group III nitride on the channel layer, and an energy barrier comprising a layer of a Group III nitride including indium on the channel layer such that the channel layer is between the barrier layer and the energy barrier. The barrier layer may have a bandgap greater than a bandgap of the channel layer, and a concentration of indium (In) in the energy barrier may be greater than a concentration of indium (In) in the channel layer. Related methods are also discussed.07-29-2010
20100258844BUMPED, SELF-ISOLATED GaN TRANSISTOR CHIP WITH ELECTRICALLY ISOLATED BACK SURFACE - A semiconductor device comprising a silicon substrate, a compound semiconductor material, an insulating material between the silicon substrate and the compound semiconductor material, and a top surface comprising means of electrical connection, and passivation material, where the passivation material is silicon nitride, silicon dioxide, or a combination of both. The present invention eliminates the need for a thick electrical insulator between a heat sink and the back surface of a surface mounted device by the inclusion of an AlN seed layer to electrically isolate the silicon substrate of the device. The sidewalls of the device are also electrically isolated from the active area of the device.10-14-2010
20100258842ENHANCEMENT MODE GALLIUM NITRIDE TRANSISTOR WITH IMPROVED GATE CHARACTERISTICS - An enhancement mode GaN transistor having a gate pGaN structure having a thickness which avoids dielectric failure. In one embodiment, this thickness is in the range of 400 Å to 900 Å. In a preferred embodiment, the thickness is 600 Å.10-14-2010
20090078965INDIVIDUALLY CONTROLLED MULTIPLE III-NITRIDE HALF BRIDGES - A semiconductor device that includes a plurality of isolated half-bridges formed in a common semiconductor die.03-26-2009
20090078964ENHANCEMENT MODE III-NITRIDE SEMICONDUCTOR DEVICE WITH REDUCED ELECTRIC FIELD BETWEEN THE GATE AND THE DRAIN - An enhancement mode III-nitride heterojunction device that includes a region between the gate and the drain electrode thereof that is at the same potential as the source electrode thereof when the device is operating.03-26-2009
20130214329TRANSISTOR AND METHOD FOR FORMING THE SAME - A transistor and a method for forming the transistor are provided. The transistor can be formed over a substrate including a first region and second regions on opposite sides of the first region. On the substrate, a first SiGe layer can be formed, followed by forming a first silicon layer on the first SiGe layer and forming a second SiGe layer on the first silicon layer. The second SiGe layer and the first silicon layer within the second regions are removed. The first silicon layer within the first region is removed to form a cavity such that the second SiGe layer is floated. An isolating layer is formed in the cavity. Second silicon layers are formed in the second regions. A gate structure is formed on the second SiGe layer within the first region and the second silicon layers are doped to form a source and a drain.08-22-2013
20100193839III-V-Group compound semiconductor device - A III-V-group compound semiconductor device includes a substrate, a channel layer provided over the substrate, a barrier layer provided on the channel layer so as to form a hetero-interface, a plurality of electrodes provided on the barrier layer, an insulator layer provided to cover an entire upper surface of the barrier layer except for at least partial regions of the electrodes, and a hydrogen-absorbing layer stacked on the insulator layer or an integrated layer in which an hydrogen-absorbing layer is integrated with the insulator layer.08-05-2010
20100193840SUBSTRATE BAND GAP ENGINEERED MULTI-GATE PMOS DEVICES - A multi-gate transistor and a method of forming a multi-gate transistor, the multi-gate transistor including a fin having an upper portion and a lower portion. The upper portion having a first band gap and the lower portion having a second band gap with the first band gap and the second band gap designed to inhibit current flow from the upper portion to the lower portion. The multi-gate transistor further including a gate structure having sidewalls electrically coupled with said upper portion and said lower portion and a substrate positioned below the fin.08-05-2010
20100001318Field effect transistor, method of manufacturing the same, and semiconductor device - A J-FET includes a channel layer of a first conductivity type (a Si-doped n-type AlGaAs electron supply layers 01-07-2010
20100224910FIELD EFFECT TRANSISTOR - Disclosed is an HJFET 09-09-2010
20100276732SEMICONDUCTOR DEVICE - A semiconductor device includes a lower barrier layer 11-04-2010
20100001317CMOS TRANSISTOR AND THE METHOD FOR MANUFACTURING THE SAME - A CMOS transistor and a method for manufacturing the same are disclosed. A semiconductor substrate having at least a PMOS transistor and an NMOS transistor is provided. The source/drain of the PMOS transistor comprises SiGe epitaxial layer. A carbon implantation process is performed to form a carbon-doped layer in the top portion of the source/drain of the PMOS transistor. A silicide layer is formed on the source/drain. A CESL is formed on the PMOS transistor and the NMOS transistor. The formation of the carbon-doped layer is capable of preventing Ge out-diffusion.01-07-2010
20120139007SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - According to one embodiment, a fabrication method of a semiconductor device comprising forming a dummy gate with a gate length direction set to a [111] direction perpendicular to a [110] direction on a surface of a supporting substrate having Si06-07-2012
20110127580CAPACITOR-LESS MEMORY DEVICE - Provided is a capacitorless memory device. The device includes a semiconductor substrate, an insulating layer disposed on the semiconductor substrate, a storage region disposed on a partial region of the insulating layer, a channel region disposed on the storage region to provide a valence band energy offset between the channel region and the storage region, a gate insulating layer and a gate electrode sequentially disposed on the channel region, and source and drain regions connected to the channel region and disposed at both sides of the gate electrode. A storage region having different valence band energy from a channel region is disposed under the channel region unit so that charges trapped in the storage region unit cannot be easily drained. Thus, a charge retention time may be increased to improve data storage capability.06-02-2011
20110006345FIELD EFFECT TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - A field effect transistor according to the present invention includes A field effect transistor, comprising: a nitride-based semiconductor multilayer structure, at least including, a drift layer formed of n-type or i-type AlxGa01-13-2011
20100252863SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR THE SAME - A semiconductor device which reduces a source resistance and a manufacturing method for the same are provided. The semiconductor device has a nitride based compound semiconductor layer arranged on a substrate, an active region which has an aluminum gallium nitride layer arranged on the nitride based compound semiconductor layer, and a gate electrode, source electrode and drain electrode arranged on the active region. The semiconductor device has gate terminal electrodes, source terminal electrodes and drain terminal electrode connected to the gate electrode, source electrode and drain electrode respectively. The semiconductor device has end face electrodes which are arranged on a side face of the substrate by a side where the source terminal electrode is arranged, and which are connected to the source terminal electrode. The semiconductor device has a projection arranged on the end face electrode which prevents solder used in die bonding from reaching the source terminal electrodes.10-07-2010
20100252862Source/Drain Engineering of Devices with High-Mobility Channels - An integrated circuit structure includes a substrate, and a channel over the substrate. The channel includes a first III-V compound semiconductor material formed of group III and group V elements. A gate structure is over the channel. A source/drain region is adjacent the channel and includes a group-IV region formed of a doped group-IV semiconductor material selected from the group consisting essentially of silicon, germanium, and combinations thereof.10-07-2010
20100127307FIELD EFFECT TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - A semiconductor layer of a second conductive type is formed on a RESURF layer of a first conductive type that is formed on a buffer layer. A contact layer of the first conductive type is formed in or on the semiconductor layer. A source electrode is formed on the contact layer. A drain electrode is formed on the RESURF layer. A gate insulating film is formed on the semiconductor layer to overlap with an end of the semiconductor layer. A gate electrode is formed on the gate insulating film to overlap with the end of the semiconductor layer. A channel formed near the end of the semiconductor layer is electrically connected to the RESURF layer.05-27-2010
20090212324HETEROJUNCTION FIELD EFFECT TRANSISTOR - An aspect of the invention provides a heterojunction field effect transistor that comprises: a base; a first GaN channel layer formed on the base; an AlN electron supply layer formed on the first GaN layer, and a second GaN cap layer formed on the AlN layer.08-27-2009
20090166676SIGE DEVICE WITH SIGE-EMBEDDED DUMMY PATTERN FOR ALLEVIATING MICRO-LOADING EFFECT - A semiconductor device with dummy patterns for alleviating micro-loading effect includes a semiconductor substrate having thereon a middle annular region between an inner region and an outer region; a SiGe device on the semiconductor substrate within the inner region; and a plurality of dummy patterns provided on the semiconductor substrate within the middle annular region. At least one of the dummy patterns contains SiGe.07-02-2009
20090140293HETEROSTRUCTURE DEVICE AND ASSOCIATED METHOD - A heterostructure device or article includes a carrier transport layer, a back channel layer and a barrier layer. The carrier transport layer has a first surface and a second surface opposing to the first surface. The back channel layer is secured to the first surface of the carrier transport layer and the barrier layer is secured to the second surface of the carrier transport layer. Each of the carrier transport layer, the back channel layer and the barrier layer comprises an aluminum gallium nitride alloy. The article further includes a 2D electron gas at an interface of the second surface of the carrier transport layer and a surface of the barrier layer. The 2D electron gas is defined by a bandgap differential at an interface, which allows for electron mobility. A system includes a heterostructure field effect transistor that includes the article.06-04-2009
20090039392III-NITRIDE POWER SEMICONDUCTOR DEVICE - A III-nitride power semiconductor device that includes a two dimensional electron gas having a reduced charge region under the gate thereof.02-12-2009
20100219451FIELD EFFECT TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - A p-type nitride compound semiconductor layer is formed on a buffer formed on a substrate. An n-type contact region is formed by ion implantation under a source electrode and a drain electrode. An electric-field reducing layer made of an n-type nitride compound semiconductor is formed on the p-type nitride compound semiconductor layer. A career density of the electric-field reducing layer is lower than that of the n-type contact region. A first end portion of the electric-field reducing layer contacts with the n-type contact region, and a second end portion of the electric-field reducing layer overlaps with a gate electrode.09-02-2010
20090114950Semiconductor Device and Method of Manufacturing such a Device - The invention relates to a semiconductor device (05-07-2009
20100219450ASYMMETRIC SOURCE/DRAIN JUNCTIONS FOR LOW POWER SILICON ON INSULATOR DEVICES - A semiconductor device includes a buried insulator layer formed on a bulk substrate; a first type semiconductor material formed on the buried insulator layer, and corresponding to a body region of a field effect transistor (FET); a second type of semiconductor material formed over the buried insulator layer, adjacent opposing sides of the body region, and corresponding to source and drain regions of the FET; the second type of semiconductor material having a different bandgap than the first type of semiconductor material; wherein a source side p/n junction of the FET is located substantially within whichever of the first and the second type of semiconductor material having a lower bandgap, and a drain side p/n junction of the FET is located substantially entirely within whichever of the first and the second type of semiconductor material having a higher bandgap.09-02-2010
20100078682POWER MOSFET HAVING A STRAINED CHANNEL IN A SEMICONDUCTOR HETEROSTRUCTURE ON METAL SUBSTRATE - A field effect transistor device having a strained semiconductor channel region overlying a heterostructure-semiconductor on a metal substrate includes a first semiconductor layer overlying a first metal layer. The first semiconductor layer has a first semiconductor material and a second semiconductor material in a relaxed heterostructure and is heavily doped. A second semiconductor layer overlies the first semiconductor layer and has a first semiconductor material and a second semiconductor material in a relaxed heterostructure. The second semiconductor layer is more lightly doped than the first semiconductor layer. A trench extends into the second semiconductor layer and a channel region has a strained layer of the first semiconductor material adjacent a trench sidewall. The strained channel region provides enhanced carrier mobility and improves performance of the field effect transistor.04-01-2010
20110108885SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - The object of the present invention is to increase channel current density while a GaN-based field effect transistor operates in a normally-off mode. Provided is a semiconductor device comprising a group 3-5 compound semiconductor channel layer containing nitrogen, an electron supply layer that supplies electrons to the channel layer, a semiconductor layer that is formed on a side of the electron supply layer opposite the side facing the channel layer and that is an intrinsic or n-type group 3-5 compound semiconductor containing nitrogen, and a control electrode that is formed to contact the semiconductor layer or formed with an intermediate layer interposed between itself and the semiconductor layer.05-12-2011
20090108298SEMICONDUCTOR DEVICE - A semiconductor device includes: substrate region; a gate electrode, a source electrode, and a drain electrode which are placed on a first surface of the substrate regions; an active area between gate and source placed between the gate electrode and the source electrode; an active area between gate and drain placed between the gate electrode and the drain electrode; an active area placed on the substrate region of the underneath part of the gate electrode, the source electrode, and the drain electrode; and a non-active area placed adjoining the active area, the active area between gate and source, and the active area between gate and drain. Furthermore, width W04-30-2009
20090108296SEMICONDUCTOR DEVICES WITH DIFFERENT DIELECTRIC THICKNESSES - An integrated circuit with devices having dielectric layers with different thicknesses. The dielectric layers include a high-k dielectric and some of the dielectric layers include an oxide layer that is formed from an oxidation process. Each device includes a layer including germanium or carbon located underneath the electrode stack of the device. A silicon cap layers is located over the layer including germanium or carbon.04-30-2009
20100301394SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device includes a gate electrode formed on a silicon substrate via a gate insulation film in correspondence to a channel region, source and drain regions of a p-type diffusion region formed in the silicon substrate at respective outer sides of sidewall insulation films of the gate electrode, and a pair of SiGe mixed crystal regions formed in the silicon substrate at respective outer sides of the sidewall insulation films in epitaxial relationship to the silicon substrate, the SiGe mixed crystal regions being defined by respective sidewall surfaces facing with each other, wherein, in each of the SiGe mixed crystal regions, the sidewall surface is defined by a plurality of facets forming respective, mutually different angles with respect to a principal surface of the silicon substrate.12-02-2010
20100301392Source/Drain Re-Growth for Manufacturing III-V Based Transistors - A method of forming an integrated circuit structure includes providing a substrate, and epitaxially growing a first semiconductor layer over the substrate. The first semiconductor layer includes a first III-V compound semiconductor material formed of group III and group V elements. The method further includes forming a gate structure on the first semiconductor layer, and forming a gate spacer on at least one sidewall of the gate structure. After the step of forming the gate structure, a second semiconductor layer including a second III-V compound semiconductor material is epitaxially grown on the first semiconductor layer.12-02-2010
20100308374STRAINED CHANNEL TRANSISTOR STRUCTURE AND METHOD - A transistor device structure comprising: a substrate portion formed from a first material; and a source region, a drain region and a channel region formed in said substrate, the source and drain regions comprising a plurality of islands of a second material different from the first material, the islands being arranged to induce a strain in said channel region of the substrate.12-09-2010
20110241073STRUCTURE FOR SELF-ALIGNED SILICIDE CONTACTS TO AN UPSIDE-DOWN FET BY EPITAXIAL SOURCE AND DRAIN - A method for fabricating an upside-down p-FET includes: fully etching source and drain regions in a donor substrate by etching a silicon-on-insulator layer through buried oxide and partially etching the silicon substrate; refilling a bottom and sidewall surfaces of the etched source and drain regions with epitaxial silicide/germanide to form e-SiGe source and drain regions; capping the source and drain regions with self-aligning silicide/germanide; providing a silicide layer formed over the gate conductor line; providing a first stress liner over the gate and the e-SiGe source and drain regions; depositing a planarized dielectric over the self-aligning silicide/germanide; inverting the donor substrate; bonding the donor substrate to a host wafer; and selectively exposing the buried oxide and the e-SiGe source and drain regions by removing the donor wafer.10-06-2011
20090140294 HETERO-STRUCTURED, INVERTED-T FIELD EFFECT TRANSISTOR - The present invention provides a method of forming a transistor. The method includes forming a first layer of a first semiconductor material above an insulation layer. The first semiconductor material is selected to provide high mobility to a first carrier type. The method also includes forming a second layer of a second semiconductor material above the first layer of semiconductor material. The second semiconductor material is selected to provide high mobility to a second carrier type opposite the first carrier type. The method further includes forming a first masking layer adjacent the second layer and etching the second layer through the first masking layer to form at least one feature in the second layer. Each feature in the second layer forms an inverted-T shape with a portion of the second layer.06-04-2009
20110018032SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor device is provided which is capable of suppressing a reduction in electron mobility in a channel region formed in a strained silicon layer. A strained silicon layer is formed over a p type silicon-germanium layer formed over a semiconductor substrate. The strained layer has a thickness adjusted to be thicker than the critical film thickness at which no misfit dislocation occurs. Accordingly, misfit dislocations occur in the vicinity of the interface between the strained silicon layer and silicon-germanium layer.01-27-2011
20110031531PROCESS FOR FORMING LOW DEFECT DENSITY HETEROJUNCTIONS - A method for forming a low defect density heterojunction between a first and a second compound, the first and second compounds each includes a group III element combined with a group V element in the periodic table, the method includes the steps of introducing in the deposition chamber the flux of the group III element for the first compound at substantially the same time while introducing in the deposition chamber a flux of the group V element for the second compound, stopping the flux of the group III element for the first compound after a first predetermined time period, stopping the flux of the group V element for the first compound after a second predetermined time period, and introducing in the deposition chamber a flux of the group III element the group V element for the second compound.02-10-2011
20110031530FIELD EFFECT TRANSISTOR WITH A HETEROSTRUCTURE - A field effect transistor with a heterostructure includes a strained monocrystalline semiconductor layer formed on a carrier material, which has a relaxed monocrystalline semiconductor layer made of a first semiconductor material (Si) as the topmost layer. The strained monocrystalline semiconductor layer has a semiconductor alloy (GexSi1-x), where the proportion x of a second semiconductor material can be set freely. Furthermore, a gate insulation layer and a gate layer are formed on the strained semiconductor layer. To define an undoped channel region, drain/source regions are formed laterally with respect to the gate layer at least in the strained semiconductor layer. The possibility of freely setting the Ge proportion x enables a threshold voltage to be set as desired, whereby modern logic semiconductor components can be realized.02-10-2011
20110114996Inducement of Strain in a Semiconductor Layer - Strain is induced in a semiconductor layer. Embodiments include inducing strain by, for example, creation of free surfaces.05-19-2011
20090050936NITRIDE SEMICONDUCTOR DEVICE AND POWER CONVERTER INCLUDING THE SAME - A nitride semiconductor device includes a RESURF layer containing p-type In02-26-2009
20090065810III-NITRIDE BIDIRECTIONAL SWITCHES - Bidirectional switches are described. The bidirectional switches include first and a second III-N based high electron mobility transistor. In some embodiments, the source of the first transistor is in electrical contact with a source of the second transistor. In some embodiments, the drain of the first transistor is in electrical contact with a drain of the second transistor. In some embodiments, the two transistors share a drift region and the switch is free of a drain contact between the two transistors. Matrix converters can be formed from the bidirectional switches.03-12-2009
20090032845SOI FIELD EFFECT TRANSISTOR HAVING ASYMMETRIC JUNCTION LEAKAGE - A source trench and a drain trench are asymmetrically formed in a top semiconductor layer comprising a first semiconductor in a semiconductor substrate. A second semiconductor material having a narrower band gap than the first semiconductor material is deposited in the source trench and the drain trench to form a source side narrow band gap region and a drain side narrow band gap region, respectively. A gate spacer is formed and source and drain regions are formed in the top semiconductor layer. A portion of the boundary between an extended source region and an extended body region is formed in the source side narrow band gap region. Due to the narrower band gap of the second semiconductor material compared to the band gap of the first semiconductor material, charge formed in the extended body region is discharged through the source and floating body effects are reduced or eliminated.02-05-2009
20110133248VERTICAL PMOS FIELD EFFECT TRANSISTOR AND MANUFACTURING METHOD THEREOF - A PMOS field effect transistor includes a substrate, a first nitride layer, a mesa structure, two gate oxide films, a gate stack layer and a second nitride layer. The substrate has a oxide layer and a first doping area. The first nitride layer is located on the oxide layer. The mesa structure includes a first strained Si—Ge layer, an epitaxial Si layer and a second strained Si—Ge layer. The first strained Si—Ge layer is located on the oxide layer and the first nitride layer. The epitaxial Si layer is located on the first strained Si—Ge layer. The second strained Si—Ge layer is located on the epitaxial Si layer. In the surface layer of the second strained Si—Ge layer, there is a second doping area. The two gate oxide films are located at two sides of the mesa structure.06-09-2011
20110210375SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a semiconductor device including a tunnel FET, includes a gate electrode, which is formed on a first semiconductor layer formed of Si09-01-2011
20090315075SEMICONDUCTOR DEVICE - A semiconductor device is, constituted by: a nitride group semiconductor functional layer which includes a first nitride group semiconductor region, a second nitride group semiconductor region provided on the first nitride group semiconductor region by a hetero junction, and a two-dimensional carrier gas channel near the hetero junction of the first nitride group semiconductor region; a first main electrode and a second main electrode connected to the two-dimensional carrier gas channel by ohmic contact; and a gate electrode disposed between the first main electrode and the second main electrode. The nitride group semiconductor region has different thicknesses between the second main electrode and the gate electrode, and between the first main electrode and the gate electrode.12-24-2009
20090218598WARP-FREE SEMICONDUCTOR WAFER, AND DEVICES USING THE SAME - A semiconductor wafer to be diced into individual SBDs, HEMTs or MESFETs has a substrate with a main semiconductor region and counter semiconductor region formed on its opposite surfaces. The main semiconductor region is configured to provide the desired semiconductor devices. In order to counterbalance the warping effect of the main semiconductor region on the substrate, as well as to enhance the voltage strength of the devices made from the wafer, the counter semiconductor region is made similar in configuration to the main semiconductor region. The main semiconductor region and counter semiconductor region are arranged in bilateral symmetry as viewed in a cross-sectional plane at right angles with the substrate surfaces.09-03-2009
20090218597METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE HAVING AN EPITAXIAL CHANNEL AND TRANSISTOR HAVING SAME - A transistor having an epitaxial channel and a method for fabricating a semiconductor device having an epitaxial channel, the method including forming a hardmask on a substrate and forming an opening in the hardmask. The opening is geometrically characterized by a long dimension and a short dimension, and the opening is arranged in a predetermined manner relative to the channel region of a transistor. An epitaxial material is formed in the opening that induces strain in substrate regions proximate to the epitaxial material. The epitaxial material is confined to the opening, such that an epitaxial channel is formed. A transistor is fabricated in proximity to the epitaxial channel, such that the strain induced in the substrate provides enhanced transistor performance. By confining the epitaxial material to a predefined channel in the substrate, plastic strain relaxation of the epitaxial material is minimized and a maximum amount of strain is induced in the substrate.09-03-2009
20080258176Antimonide-based compound semiconductor with titanium tungsten stack - An apparatus in one example comprises an antimonide-based compound semiconductor (ABCS) stack, an upper barrier layer formed on the ABCS stack, and a gate stack formed on the upper barrier layer. The upper barrier layer comprises indium, aluminum, and arsenic. The gate stack comprises a base layer of titanium and tungsten formed on the upper barrier layer.10-23-2008
20110175142NITRIDE SEMICONDUCTOR DEVICE - A nitride semiconductor device includes a first nitride semiconductor layer; a second nitride semiconductor layer formed on the first nitride semiconductor layer, and having a wider bad gap than the first nitride semiconductor layer; a source electrode, a drain electrode, and a gate electrode, which are formed on the second nitride semiconductor layer; a high resistive layer formed lower than the first nitride semiconductor layer; a conductive layer formed under and in contact with the high resistive layer; a lower insulating layer formed under the conductive layer; and a bias terminal electrically connected to the conductive layer.07-21-2011
20120199878Drain Extended Field Effect Transistors and Methods of Formation Thereof - In an embodiment of the invention, a semiconductor device includes a first region having a first doping type, a channel region having the first doping type disposed in the first region, and a retrograde well having a second doping type. The second doping type is opposite to the first doping type. The retrograde well has a shallower layer with a first peak doping and a deeper layer with a second peak doping higher than the first peak doping. The device further includes a drain region having the second doping type over the retrograde well. An extended drain region is disposed in the retrograde well, and couples the channel region with the drain region. An isolation region is disposed between a gate overlap region of the extended drain region and the drain region. A length of the drain region is greater than a depth of the isolation region.08-09-2012
20100059791SEMICONDUCTOR DEVICE AND FABRICATION METHOD FOR THE SAME - A semiconductor device, which reduces the earth inductance, and a fabrication method for the same is provided.03-11-2010
20100065886SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - According to an aspect of the present invention, there is provided a semiconductor device including: a substrate that includes a semiconductor region including Ge as a primary component; a compound layer that is formed above the semiconductor region, that includes Ge and that has a non-metallic characteristic; an insulator film that is formed above the compound layer; an electrode that is formed above the insulator film; and source/drain regions that is formed in the substrate so as to sandwich the electrode therebetween.03-18-2010
20100065887FIELD EFFECT TRANSISTOR SOURCE OR DRAIN WITH A MULTI-FACET SURFACE - FET configurations in which two (or more) facets are exposed on a surface of a semiconductor channel, the facets being angled with respect to the direction of the channel, allow for conformal deposition of a convex or concave S/D. A convex tip of the S/D enhances electric fields at the interface, reducing the resistance between the S/D and the channel. In contrast, a S/D having a concave tip yields a dual-gate FET that emphasizes reduced short-channel effects rather than electric field enhancement. The use of self-limiting, selective wet etches to expose the facets facilitates process control, control of interface chemistry, and manufacturability.03-18-2010
20110079822COMPOUND SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD - A compound semiconductor device includes an electron transit layer; an electron supply layer formed over the electron transit layer; a first recessed portion and a second recessed portion formed in the electron supply layer; a chemical compound semiconductor layer including impurities that buries the first recessed portion and the second recessed portion and covers over the electron supply layer; a source electrode formed over the chemical compound semiconductor layer which buries the first recessed portion; a drain electrode formed over the chemical compound semiconductor layer which buries the second recessed portion; and a gate electrode formed over the electron supply layer between the source electrode and the drain electrode, wherein, in the chemical compound semiconductor layer, a concentration of impurities included below the source electrode and the drain electrode is higher than a concentration of impurities included near the gate electrode.04-07-2011
20090090936ELECTRIC FIELD READ/WRITE HEAD, METHOD OF MANUFACTURING THE SAME, AND INFORMATION STORAGE DEVICE COMPRISING ELECTRIC FIELD READ/WRITE HEAD - Provided is an electric field head including a resistance sensor to read information recorded on a recording medium. The resistance sensor includes a first semiconductor layer including a source and a drain, and a second semiconductor layer that is heterogeneously combined with the first semiconductor layer. Also, the electric field head further includes a channel between the source and the drain, in a junction region of the first and second semiconductor layers.04-09-2009
20110068368SEMICONDUCTOR DEVICE COMPRISING A HONEYCOMB HETEROEPITAXY - A semiconductor device comprising a honeycomb heteroepitaxy and method for making same are described. One embodiment is a method comprising defining a mask on a silicon substrate, the mask comprising a plurality of nano-size openings therethrough; subsequent to the defining, creating essentially defect-free non-silicon semiconductor nano-islands on portions of a surface of the silicon substrate exposed through the mask openings; subsequent to the creating, depositing high-k gate dielectric is deposited on the nano-islands; and subsequent to the deposition, constructing transistors on the nano-islands.03-24-2011
20110068369METAL GATE AND HIGH-K DIELECTRIC DEVICES WITH PFET CHANNEL SiGe - A method for fabricating a circuit structure is disclosed. The method includes depositing epitaxially a SiGe layer onto both NFET and PFET portions of a Si surface. Blanket disposing a first sequence of layers over the SiGe layer, including a high-k dielectric and a metal, and incorporating this first sequence of layers into the gatestacks and gate insulators of both NFET devices and PFET devices. This first sequence of layers is selected to yield desired device parameter values for the PFET devices. The method further includes removing the gatestack, the gate dielectric, and the SiGe layer, and re-forming the NFET devices by deploying a second sequence of layers that include a second high-k dielectric and a second metal. The second sequence of layers is selected to yield desired device parameter values for the NFET devices. A circuit structure is also disclosed. PFET devices have a gate dielectric with a high-k dielectric, a gatestack with a metal, and a silicide formed over the p-source/drain. NFET devices also include a gate dielectric with a high-k dielectric, a gatestack with a metal, and silicide formed over the n-source/drain. An epitaxial SiGe layer over the substrate surface is present everywhere in the device structures with the exception that it is absent underneath the NFET gate dielectric. The PFET and NFET device parameters are independently optimized through the composition of their gate dielectrics and gate stacks.03-24-2011
20100295096Integrated Devices on a Common Compound Semiconductor III-V Wafer - A method of fabricating an integrated circuit on a compound semiconductor III-V wafer including at least two different types of active devices by providing a substrate; growing a first epitaxial structure on the substrate; growing a second epitaxial structure on the first epitaxial structure; and processing the epitaxial structures to form different types of active devices, such as HBTs and FETs.11-25-2010
20090001422SEMICONDUCTOR APPARATUS AND MANUFACTURING METHOD THEREOF - There is provided a manufacturing method of a semiconductor apparatus, including forming an InGaP layer on a substrate, forming a gate electrode having a Ti layer and an Au layer by vapor deposition on an upper surface of the InGaP layer, further forming a GaAs layer on the upper surface of the InGaP layer in a region different from a region in which the gate electrode is formed, and further forming a source electrode and a drain electrode on an upper surface of the GaAs layer. When the gate electrode having the Ti and Au layers is formed on the upper surface of the InGaP layer, the Ti and Au layers are formed with a substrate temperature being set equal to or lower than 180° C.01-01-2009
20090001421NANOTUBE TRANSISTOR INTEGRATED CIRCUIT LAYOUT - An integrated circuit layout of a carbon nanotube transistor device includes a first and second conductive material. The first conductive material is connected to ends of single-walled carbon nanotubes below (or above) the first conductive material. The second conductive material is not electrically connected to the nanotubes below (or above) the second conductive material. The first conductive material may be metal, and the second conductive material may be polysilicon or metal. The nanotubes are perpendicular to the first conductive material. In one implementation, the first and second conductive materials form interdigitated fingers. In another implementation, the first conductive material forms a serpentine track.01-01-2009
20090212325Hetero Field Effect Transistor and Manufacturing Method Thereof - A hetero field effect transistor includes: a main semiconductor region including a first semiconductor layer and a second semiconductor layer formed thereon to allow a generation of a two-dimensional carrier gas layer of a first conductive type on a heterojunction interface therebetween; a source electrode formed on the main semiconductor region; a drain electrode formed on the main semiconductor region and separated from the source electrode; a third semiconductor layer of a second conductive type different from the first conductive type, the third semiconductor layer being formed on the second semiconductor layer and located between the source electrode and the drain electrode; and a gate electrode formed on the third semiconductor layer. A concave portion is formed in an upper surface of the second semiconductor layer at a region immediately below the gate electrode.08-27-2009
20110254053SUPERCONDUCTOR TRANSISTOR AND METHOD FOR MANUFACTURING SUCH TRANSISTOR - This field-effect superconductor transistor (10-20-2011
20120199879METHOD OF FORMING AN INVERTED T SHAPED CHANNEL STRUCTURE FOR AN INVERTED T CHANNEL FIELD EFFECT TRANSISTOR DEVICE - A method of forming an inverted T shaped channel structure having a vertical channel portion and a horizontal channel portion for an Inverted T channel Field Effect Transistor ITFET device comprises semiconductor substrate, a first layer of a first semiconductor material over the semiconductor substrate and a second layer of a second semiconductor material over the first layer. The first and the second semiconductor materials are selected such that the first semiconductor material has a rate of removal which is less than a rate of removal of the second semiconductor material.08-09-2012
20080246058GALLIUM NITRIDE MATERIAL TRANSISTORS AND METHODS ASSOCIATED WITH THE SAME - Gallium nitride material transistors and methods associated with the same are provided. The transistors may be used in power applications by amplifying an input signal to produce an output signal having increased power. The transistors may be designed to transmit the majority of the output signal within a specific transmission channel (defined in terms of frequency), while minimizing transmission in adjacent channels. This ability gives the transistors excellent linearity which results in high signal quality and limits errors in transmitted data. The transistors may be designed to achieve low ACPR values (a measure of excellent linearity), while still operating at high drain efficiencies and/or high output powers. Such properties enable the transistors to be used in RF power applications including third generation (3G) power applications based on W-CDMA modulation.10-09-2008
20120032230METHOD OF FORMING STRAINED SEMICONDUCTOR CHANNEL AND SEMICONDUCTOR DEVICE - The present invention provides a method of forming a strained semiconductor channel, comprising: forming a relaxed SiGe layer on a semiconductor substrate; forming a dielectric layer on the relaxed SiGe layer and forming a sacrificial gate on the dielectric layer, wherein the dielectric layer and the sacrificial gate form a sacrificial gate structure; depositing an interlayer dielectric layer, which is planarized to expose the sacrificial gate; etching to remove the sacrificial gate and the dielectric layer to form an opening; forming a semiconductor epitaxial layer by selective semiconductor epitaxial growth in the opening; depositing a high-K dielectric layer and a metal layer; and removing the high-K dielectric layer and metal layer covering the interlayer dielectric layer by planarizing the deposited metal layer and high-K dielectric layer to form a metal gate. The present invention also provides a semiconductor device manufactured by this process.02-09-2012
20120199880SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREOF - In order to solve a problem that, in an initial stage of film growth in a plasma CVD method, it is difficult to form a silicon layer which is excellent in crystallinity, provided is a semiconductor device, including: a substrate; a crystalline silicon layer; a titanium oxide layer containing titanium oxide as a main component; and a pair of electrodes electrically connected to the crystalline silicon layer, in which: the titanium oxide layer and the crystalline silicon layer are formed on the substrate in the mentioned order from the substrate side; and the titanium oxide layer and the crystalline silicon layer are formed in contact to each other.08-09-2012
20120168821SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device having a substrate including a major surface, a gate stack comprising a sidewall over the substrate and a spacer over the substrate adjoining the sidewall of the gate stack. The spacer having a bottom surface having an outer point that is the point on the bottom surface farthest from the gate stack. An isolation structure in the substrate on one side of the gate stack has an outer edge closest to the spacer. A strained material below the major surface of the substrate disposed between the spacer and the isolation structure having an upper portion and a lower portion separated by a transition plane at an acute angle to the major surface of the substrate.07-05-2012
20080203432SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A transistor including a gate insulation layer, a gate, and source/drain regions, the transistor comprising a semiconductor layer formed under the gate insulation layer for use as a channel region in a substrate, wherein the semiconductor layer is formed of a material having a lower bandgap than silicon.08-28-2008
20080203431GaN-BASED NITRIC OXIDE SENSORS AND METHODS OF MAKING AND USING THE SAME - GaN-based heterojunction field effect transistor (HFET) sensors are provided with engineered, functional surfaces that act as pseudo-gates, modifying the drain current upon analyte capture. In some embodiments, devices for sensing nitric oxide (NO) species in a NO-containing fluid are provided which comprise a semiconductor structure that includes a pair of separated GaN layers and an AlGaN layer interposed between and in contact with the GaN layers. Source and drain contact regions are formed on one of the GaN layers, and an exposed GaN gate region is formed between the source and drain contact regions for contact with the NO-containing fluid. The semiconductor structure most preferably is formed on a suitable substrate (e.g., SiC). An insulating layer may be provided so as to cover the semiconductor structure. The insulating layer will have a window formed therein so as to maintain exposure of the GaN gate region and thereby allow the gate region to contact the NO-containing fluid. Electrical contact pads are preferably provided in some embodiments so as to be in electrical contact with the source and drain contact regions, respectively. Electrical leads may thus be connected to the contact pads. According to other embodiments, the NO detection device will include a metalloporphyrin adsorbed on the GaN gate region.08-28-2008
20080203433HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD OF FORMING THE SAME - A high electron mobility transistor includes first, second and third compound semiconductor layers. The second compound semiconductor layer has a first interface with the first compound semiconductor layer. The third compound semiconductor layer is disposed over the first compound semiconductor layer. The third compound semiconductor layer has at least one of lower crystallinity and relaxed crystal structure as compared to the second compound semiconductor layer. The gate electrode is disposed over the third compound semiconductor layer. Source and drain electrodes are disposed over the second compound semiconductor layer. The two-dimensional carrier gas layer is generated in the first compound semiconductor layer. The two-dimensional carrier gas layer is adjacent to the first interface. The two-dimensional carrier gas layer either is absent under the third compound semiconductor layer or is reduced in at least one of thickens and carrier gas concentration under the third compound semiconductor layer.08-28-2008
20100320504SEMICONDUCTOR DEVICE COMPRISING GATE ELECTRODE SURROUNDING ENTIRE CIRCUMFERENCE OF CHANNEL REGION AND METHOD FOR MANUFACTURING THE SAME - Two first semiconductor layers are on a silicon substrate at a given distance from each other. Two second semiconductor layers are on the respective first semiconductor layers and includes a material different from a material of the first semiconductor layers. A first channel region is formed like a wire between the two second semiconductor layers. A first insulating layer is around the first channel region. A second insulating film is on each of opposite side surfaces of the two first semiconductor layers. A third insulating film is on each of opposite side surfaces of the two second semiconductor layers. A gate electrode is on the first, second, and third insulating films. Film thickness of the second insulating film is larger than film thickness of the first insulating film.12-23-2010
20100320505SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME, AND AMPLIFIER - A semiconductor device includes a nitride semiconductor layer having a (0001) face and a (000-1) face, formed above a common substrate; a (0001) face forming layer provided partially between the substrate and the nitride semiconductor layer; a source electrode, a drain electrode, and a gate electrode, provided on the nitride semiconductor layer having the (0001) face; and a hole extracting electrode provided on the nitride semiconductor layer having the (000-1) face.12-23-2010
20110254054SEMICONDUCTOR DEVICE - A semiconductor device has at least an n-type MIS transistor, which includes a first gate insulating film formed on a first semiconductor region in a semiconductor substrate, a first gate electrode formed on the first gate insulating film, first sidewalls formed on the side surfaces of the first gate electrode, and carbon-containing silicon regions formed laterally outside the first sidewalls. The top surfaces of the carbon-containing silicon regions are at a level higher than the top surface of a region in the first semiconductor region lying under the first gate insulating film.10-20-2011
20110133249HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD OF FORMING THE SAME - A high electron mobility transistor includes first, second and third compound semiconductor layers. The second compound semiconductor layer has a first interface with the first compound semiconductor layer. The third compound semiconductor layer is disposed over the first compound semiconductor layer. The third compound semiconductor layer has at least one of lower crystallinity and relaxed crystal structure as compared to the second compound semiconductor layer. The gate electrode is disposed over the third compound semiconductor layer. Source and drain electrodes are disposed over the second compound semiconductor layer. The two-dimensional carrier gas layer is generated in the first compound semiconductor layer. The two-dimensional carrier gas layer is adjacent to the first interface. The two-dimensional carrier gas layer either is absent under the third compound semiconductor layer or is reduced in at least one of thickens and carrier gas concentration under the third compound semiconductor layer.06-09-2011
20100301393FIELD EFFECT TRANSISTOR AND MANUFACTURING METHOD THEREFOR - There is provided a field effect transistor of a normally-OFF operation having a low contact resistance and capable of avoiding increases in on-resistance and maintaining high channel mobility. In this field effect transistor, a thin-layer portion 12-02-2010
20110084309METHOD FOR ENHANCING THE RELIABILITY OF A P-CHANNEL SEMICONDUCTOR DEVICE AND A P-CHANNEL SEMICONDUCTOR DEVICE MADE THEREOF - A method for forming a semiconductor device is disclosed. The device includes a control electrode on a semiconductor P-channel layer having at least a gate dielectric layer. The gate dielectric layer has an exponentially decreasing density of defect levels E04-14-2011
20110073909REPLACEMENT SPACER FOR TUNNEL FETS - A semiconductor fabrication method includes depositing a dummy gate layer onto a substrate, patterning the dummy gate layer, depositing a hardmask layer over the dummy gate layer, patterning the hardmask layer, etching a recess into the substrate, adjacent the dummy gate layer, depositing a semiconductor material into the recess, removing the hardmask layer, depositing replacement spacers onto the dummy gate layer, performing an oxide deposition over the dummy gate layer and replacement spacers, removing the dummy gate and replacement spacers, thereby forming a gate recess in the oxide and depositing a gate stack into the recess.03-31-2011
20110073910NITRIDE SEMICONDUCTOR MATERIAL, SEMICONDUCTOR ELEMENT, AND MANUFACTURING METHOD THEREOF - The nitride semiconductor material according to the present invention includes a group III nitride semiconductor and a group IV nitride formed on the group III nitride semiconductor, where an interface between the group III nitride semiconductor and the group IV nitride has a regular atomic arrangement. Moreover, an arrangement of nitrogen atoms of the group IV nitride in the interface and an arrangement of group III atoms of the group III nitride semiconductor in the interface may be substantially identical.03-31-2011
20110175141SEMICONDUCTOR DEVICES INCLUDING MOS TRANSISTORS HAVING AN OPTIMIZED CHANNEL REGION AND METHODS OF FABRICATING THE SAME - A semiconductor device, including a device isolation layer arranged on a predetermined region of a semiconductor substrate to define an active region, the active region including a central top surface of a (100) crystal plane and an inclined edge surface extending from the central top surface to the device isolation layer, a semiconductor pattern covering the central top surface and the inclined edge surface of the active region, the semiconductor pattern including a flat top surface of a (100) crystal plane that is parallel with the central top surface of the active region and a sidewall that is substantially perpendicular to the flat top surface, and a gate pattern overlapping the semiconductor pattern.07-21-2011
20100078684SELECTIVE HIGH-K DIELECTRIC FILM DEPOSITION FOR SEMICONDUCTOR DEVICE - Embodiments of the present invention describe a method of fabricating a III-V quantum well transistor with low current leakage and high on-to-off current ratio. A hydrophobic mask having an opening is formed on a semiconductor film. The opening exposes a portion on the semiconductor film where a dielectric layer is desired to be formed. A hydrophilic surface is formed on the exposed portion of the semiconductor film. A dielectric layer is then formed on the hydrophilic surface by using an atomic layer deposition process. A metal layer is deposited on the dielectric layer.04-01-2010
20110186912TRANSISTOR GATE ELECTRODE HAVING CONDUCTOR MATERIAL LAYER - Various embodiments of the invention relate to a PMOS device having a transistor channel of silicon germanium material on a substrate, a gate dielectric having a dielectric constant greater than that of silicon dioxide on the channel, a gate electrode conductor material having a work function in a range between a valence energy band edge and a conductor energy band edge for silicon on the gate dielectric, and a gate electrode semiconductor material on the gate electrode conductor material.08-04-2011
20110147795MATERIALS FOR INTERFACING HIGH-K DIELECTRIC LAYERS WITH III-V SEMICONDUCTORS - A group III chalcogenide layer for interfacing a high-k dielectric to a III-V semiconductor surface and methods of forming the same. A III-V QWFET includes a gate stack which comprises a high-K gate dielectric layer disposed on an interfacial layer comprising a group III chalcogenide. In an embodiment, a III-V semiconductor surface comprising a native oxide is sequentially exposed to TMA and H06-23-2011
20100025729PASSIVATED III-V FIELD EFFECT STRUCTURE AND METHOD - An improved insulated gate field effect device (02-04-2010
20120146093NITRIDE SEMICONDUCTOR DEVICE - A nitride semiconductor device includes a semiconductor multilayer formed on a substrate, a first ohmic electrode and a Schottky electrode spaced apart from each other on the semiconductor multilayer; and a passivation film covering a top of the semiconductor multilayer. The semiconductor multilayer 06-14-2012
20090173968Field Effect Transistor - A semiconductor device 07-09-2009
20120032231MOS TRANSISTOR STRUCTURE WITH IN-SITU DOPED SOURCE AND DRAIN AND METHOD FOR FORMING THE SAME - A MOS transistor structure with an in-situ doped source and/or drain and a method for forming the same are provided. The method comprises steps of: providing a substrate; forming a high Ge content layer on the substrate; forming a gate stack on the high Ge content layer and forming a side wall of one or more layers on both sides of the gate stack; etching the high Ge content layer to form a source region and/or a drain region; and forming a source and/or a drain in the source region and/or the drain region respectively by a low-temperature selective epitaxy, and introducing a doping gas during the low-temperature selective epitaxy to heavily dope the source and/or the drain and to in-situ activate a doping element.02-09-2012
20120305990METHODS AND APPARATUS TO REDUCE LAYOUT BASED STRAIN VARIATIONS IN NON-PLANAR TRANSISTOR STRUCTURES - The present disclosure relates to the field of fabricating microelectronic devices. In at least one embodiment, the present disclosure relates to forming isolation structures in strained semiconductor bodies of non-planar transistors while maintaining strain in the semiconductor bodies.12-06-2012
20120305988SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate; a plurality of convex structures formed on the substrate, in which every two adjacent convex structures are separated by a cavity; a plurality of floated films, in which each floated film is formed between the every two adjacent convex structures and connected with tops of the every two adjacent convex structures, the floated films are partitioned into a plurality of sets, a channel layer is formed on a convex structure between the floated films in each set, a source region and a drain region are formed on two sides of the channel layer respectively, and an isolation portion is set between two adjacent sets of floated films; and a gate stack formed on each channel layer.12-06-2012
20120305989METHOD TO PREVENT SURFACE DECOMPOSITION OF III-V COMPOUND SEMICONDUCTORS - A method of preventing surface decomposition of a III-V compound semiconductor is provided. The method includes forming a silicon film having a thickness from 10 Å to 400 Å on a surface of an III-V compound semiconductor. After forming the silicon film onto the surface of the III-V compound semiconductor, a high performance semiconductor device including, for example, a MOSFET, can be formed on the capped/passivated III-V compound semiconductor. During the MOSFET fabrication, a high k dielectric can be formed on the capped/passivated III-V compound semiconductor and thereafter, activated source and drain regions can be formed into the III-V compound semiconductor.12-06-2012
20080203430ENHANCEMENT MODE INSULATED GATE HETEROSTRUCTURE FIELD-EFFECT TRANSISTOR - Aspects of the present invention provide an enhancement mode (E-mode) insulated gate (IG) double heterostructure field-effect transistor (DHFET) having low power consumption at zero gate bias, low gate currents, and/or high reliability. An E-mode HFET in accordance with an embodiment of the invention includes: top and bottom barrier layers; and a channel layer sandwiched between the bottom and the top barrier layers, wherein the bottom and top barrier layers have a larger bandgap than the channel layer, and wherein polarization charges of the bottom barrier layer deplete the channel layer and polarization charges of the top barrier layer induce carriers in the channel layer; and wherein a total polarization charge in the bottom barrier layer is larger than a total polarization charge in the top barrier layer such that the channel layer is substantially depleted at zero gate bias.08-28-2008
20110316048SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - There is provided a semiconductor device and a method for fabricating the same whose withstanding characteristic may be enhanced and whose ON resistance may be reduced. A MIS-type HEMT includes a carrier traveling layer made of a group-III nitride semiconductor and formed on a supporting substrate, a carrier supplying layer made of a group-III nitride semiconductor and formed on the carrier traveling layer, source and drain electrodes formed on the carrier supplying layer, insulating films formed on the carrier supplying layer and a gate electrode formed on the insulating films. The insulating film is formed in a region interposed between the source and drain electrodes and has a trench whose cross-section is inverted trapezoidal and whose upper opening is wider than a bottom thereof. The gate electrode is formed at least from the bottom of the trench onto the insulating films on the side of the drain electrode.12-29-2011
20110316046Field Effect Transistor Device - A method for forming a field effect transistor device includes forming a gate stack portion on a substrate, forming a spacer portion on the gates stack portion and a portion of the substrate, removing an exposed portion of the substrate, epitaxially growing a first silicon material on the exposed portion of the substrate, removing a portion of the epitaxially grown first silicon material to expose a second portion of the substrate, and epitaxially growing a second silicon material on the exposed second portion of the substrate and the first silicon material.12-29-2011
20110316045LAYOUT DESIGN FOR A HIGH POWER, GaN-BASED FET - A FET includes a substrate, a buffer layer disposed on the substrate, a channel layer disposed over the buffer layer and a barrier layer disposed over the channel layer. Source, gate and drain electrodes are located over the barrier layer and extend in a longitudinal direction thereon. A portion of the channel and barrier layers define a mesa extending in the longitudinal direction and the source and drain electrodes extend beyond an edge of the mesa. The gate electrodes extend along an edge sidewall of the mesa. A conductive source interconnect is disposed over the buffer layer and have a first end electrically connected to the source electrode. A first dielectric layer is disposed over the buffer layer and over the source interconnect. A gate via is formed in the first dielectric layer. A conductive gate node extends along the buffer layer and electrically connects the portion of the gate electrode extending along the sidewall of the mesa. A gate pad is disposed on the first dielectric layer adjacent the mesa. A conductive gate connect strip is located over the gate node and is in contact therewith. The gate strip is in electrical contact with the gate pad. A source via is formed in the first dielectric layer and a source pad is formed in the source via. The conductive source interconnect has a second end in electrical contact with the source pad.12-29-2011
20110316047SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - The objective of the present invention is to provide a semiconductor device of a hetero-junction field effect transistor that is capable of obtaining a high output and a high breakdown voltage and a manufacturing method of the same. The present invention is a semiconductor device of a hetero junction field effect transistor provided with an Al12-29-2011
20120043585Field Effect Transistor Device with Shaped Conduction Channel - A field effect transistor device includes a substrate, a silicon germanium (SiGe) layer disposed on the substrate, gate dielectric layer lining a surface of a cavity defined by the substrate and the silicon germanium layer, a metallic gate material on the gate dielectric layer, the metallic gate material filling the cavity, a source region, and a drain region.02-23-2012
20120001229Semiconductor Device and Method for Forming the Same - A semiconductor device comprises a semiconductor substrate on an insulating layer; and a second gate, the second gate is located on the insulating layer and is embedded at least partially in the semiconductor substrate. A method for forming a semiconductor device comprises: forming a semiconductor substrate on an insulating layer; forming a void within the semiconductor substrate, with the insulating layer being exposed by the void; and forming a second gate, with the void being filled with at least one part of the second gate. It facilitates the reduction of the short channel effects, resistances of source and drain regions, and parasitic capacitances.01-05-2012
20110156099ENHANCED CONFINEMENT OF SENSITIVE MATERIALS OF A HIGH-K METAL GATE ELECTRODE STRUCTURE - When forming sophisticated high-k metal gate electrode structures, the removal of a dielectric cap material may be accomplished with superior process uniformity by using a silicon dioxide material. In other illustrative embodiments, an enhanced spacer regime may be applied, thereby also providing superior implantation conditions for forming drain and source extension regions and drain and source regions.06-30-2011
20110024795EPITAXIAL SUBSTRATE FOR SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE, AND PROCESS FOR PRODUCING EPITAXIAL SUBSTRATE FOR SEMICONDUCTOR DEVICE - Provided is an epitaxial substrate capable of manufacturing a HEMT device that has excellent two-dimensional electron gas characteristics and is capable of performing normally-off operation. A channel layer is formed of a first group III nitride represented by In02-03-2011
20120056246INSULATED GATE FIELD EFFECT TRANSISTORS - An improved insulated gate field effect device is obtained by providing a substrate desirably comprising a III-V semiconductor, having a further semiconductor layer on the substrate adapted to contain the channel of the device between spaced apart source-drain electrodes formed on the semiconductor layer. A dielectric layer is formed on the semiconductor layer. A sealing layer is formed on the dielectric layer and exposed to an oxygen plasma. A gate electrode is formed on the dielectric layer between the source-drain electrodes. The dielectric layer preferably comprises gallium-oxide and/or gadolinium-gallium oxide, and the oxygen plasma is preferably an inductively coupled plasma. A further sealing layer of, for example, silicon nitride is desirably provided above the sealing layer. Surface states and gate dielectric traps that otherwise adversely affect leakage and channel sheet resistance are much reduced.03-08-2012
20120056245SEMICONDUCTOR DEVICES INCLUDING SILICIDE REGIONS AND METHODS OF FABRICATING THE SAME - A semiconductor device includes a semiconductor substrate, a gate electrode structure including a gate electrode located on an active region of the semiconductor substrate, first and second epitaxial regions located in the active region at opposite sides of the gate electrode structure, and first and second silicide layers on upper surfaces of the first and second epitaxial regions, respectively. The first and second epitaxial regions include Si—X, where X is one of germanium and carbon, and at least a portion of each of the first and second silicide layers is devoid of X and includes Si—Y, where Y is a metal or metal alloy03-08-2012
20120007147SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - In a semiconductor film having a heterojunction structure, for example a semiconductor film including a SiGe layer and a Si layer formed on the SiGe layer, impurity concentration is controlled in such a manner that the concentration of impurity in the lower, SiGe layer becomes higher than that in the upper, Si layer by exploiting the fact that there is a difference between the SiGe layer and the Si layer in the diffusion coefficient of the impurity. The impurity contained in the semiconductor film 01-12-2012
20120007146METHOD FOR FORMING STRAINED LAYER WITH HIGH GE CONTENT ON SUBSTRATE AND SEMICONDUCTOR STRUCTURE - A semiconductor structure and a method for forming the same are provided. The semiconductor structure may comprise a substrate (01-12-2012
20120007145ASYMMETRIC CHANNEL MOSFET - A field effect transistor includes a partial SiGe channel, i.e., a channel including a SiGe channel portion, located underneath a gate electrode and a Si channel portion located underneath an edge of the gate electrode near the drain region. The SiGe channel portion can be located directly underneath a gate dielectric, or can be located underneath a Si channel layer located directly underneath a gate dielectric. The Si channel portion is located at the same depth as the SiGe channel portion, and contacts the drain region of the transistor. By providing a Si channel portion near the drain region, the GIDL current of the transistor is maintained at a level on par with the GIDL current of a transistor having a silicon channel only during an off state.01-12-2012
20120012893SEMICONDUCTOR TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - To provide a semiconductor transistor without variation in threshold voltage of an FET and a method of manufacturing the semiconductor transistor, the semiconductor transistor includes: a substrate; a first compound semiconductor layer formed above the substrate; a second compound semiconductor layer formed on the first compound semiconductor layer and having a bandgap larger than a bandgap of the first compound semiconductor layer; an oxygen-doped region formed by doping at least part of the second compound semiconductor layer with oxygen; a third compound semiconductor layer formed on the second compound semiconductor layer; a source electrode electrically connected to the first compound semiconductor layer; a drain electrode electrically connected to the first compound semiconductor layer; and a gate electrode formed on and in contact with the oxygen-doped region.01-19-2012
20110049571EPITAXIAL SUBSTRATE FOR SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING EPITAXIAL SUBSTRATE FOR SEMICONDUCTOR DEVICE - Provided is an epitaxial substrate capable of achieving a semiconductor device that has excellent schottky contact characteristics as well as satisfactory device characteristics. On a base substrate, a channel layer formed of a first group III nitride that contains at least Al and Ga and has a composition of In03-03-2011
20110049570EPITAXIAL SUBSTRATE FOR SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING EPITAXIAL SUBSTRATE FOR SEMICONDUCTOR DEVICE - Provided is an epitaxial substrate capable of achieving a semiconductor device that has excellent ohmic contact characteristics as well as satisfactory device characteristics. On a base substrate, a channel layer formed of a first group III nitride that contains at least Al and Ga and has a composition of In03-03-2011
20110049569Semiconductor structure including a field modulation body and method for fabricating same - According to one embodiment, a semiconductor structure including an equipotential field modulation body comprises a trench surrounding an active region of a group III-V power device fabricated in the semiconductor structure, and the equipotential field modulation body formed in the trench and extending over a portion of the active region. The equipotential field modulation body is electrically coupled to a terminal of the group III-V power device. In one embodiment, a method for fabricating a semiconductor structure including an equipotential field modulation body comprises fabricating a trench surrounding an active region of the semiconductor structure, forming the equipotential field modulation body in the trench, the equipotential field modulation body extending over a portion of the active region, and electrically coupling the equipotential field modulation body to a terminal of a group III-V power device fabricated in the active region.03-03-2011
20120061728SEMICONDUCTOR ON INSULATOR (XOI) FOR HIGH PERFORMANCE FIELD EFFECT TRANSISTORS - Semiconductor-on-insulator (XOI) structures and methods of fabricating XOI structures are provided. Single-crystalline semiconductor is grown on a source substrate, patterned, and transferred onto a target substrate, such as a Si/SiO03-15-2012
20120153355NITRIDE SEMICONDUCTOR DEVICE - A nitride semiconductor device includes a semiconductor substrate, and a nitride semiconductor layer formed on the semiconductor substrate. The semiconductor substrate includes a normal region and an interface current block region surrounding the normal region. The nitride semiconductor layer includes an element region and an isolation region surrounding the element region. The element region is formed over the normal region. The interface current block region contains impurities, and forms a potential barrier against carriers generated at an interface between the nitride semiconductor layer and the semiconductor substrate.06-21-2012
20120153353BURIED OXIDATION FOR ENHANCED MOBILITY - A method patterns at least one pair of openings through a protective layer and into a substrate. The openings are positioned on opposite sides of a channel region of the substrate. The method forms sidewall spacers along the sidewalls of the openings and removes additional substrate material from the bottom of the openings. The material removal process creates an extended bottom within the openings. The method forms a first strain producing material within the extended bottom of the openings. The method removes the sidewall spacers and forms a second material within the remainder of the openings between the first strain producing material and the top of the openings. The method removes the protective layer and forms a gate dielectric and a gate conductor on the horizontal surface on the substrate adjacent the channel region. The second material comprises source and drain regions.06-21-2012
20120153352HIGH INDIUM CONTENT TRANSISTOR CHANNELS - The present disclosure relates to the field of microelectronic transistor fabrication and, more particularly, to the formation of high mobility transistor channels from high indium content alloys, wherein the high indium content transistor channels are achieved with a barrier layer that can substantially lattice match with the high indium content transistor channel.06-21-2012
20120153354PERFORMANCE ENHANCEMENT IN TRANSISTORS COMPRISING HIGH-K METAL GATE STACKS AND AN EMBEDDED STRESSOR BY PERFORMING A SECOND EPITAXY STEP - When forming sophisticated transistors, for instance comprising high-k metal gate electrode structures, a significant material loss of an embedded strain-inducing semiconductor material may be compensated for, or at least significantly reduced, by performing a second epitaxial growth step after the incorporation of the drain and source extension dopant species. In this manner, superior strain conditions may be achieved, while also the required drain and source dopant profile may be implemented.06-21-2012
20120153351Stress modulated group III-V semiconductor device and related method - According to one embodiment, a group III-V semiconductor device comprises a compositionally graded body disposed over a substrate and below a buffer layer supporting an active area of the group III-V semiconductor device. The compositionally graded body includes a first region applying compressive stress to the substrate. The compositionally graded body further includes a stress modulating region over the first region, where the stress modulating region applies tensile stress to the substrate. In one embodiment, a method for fabricating a group III-V semiconductor device comprises providing a substrate for the group III-V semiconductor device and forming a first region of a compositionally graded body over the substrate to apply compressive stress to the substrate. The method further comprises forming a stress modulating region of the compositionally graded body over the first region, where the stress modulating region applies tensile stress to the substrate.06-21-2012
20100148217Graded high germanium compound films for strained semiconductor devices - Embodiments of an apparatus and methods for providing a graded high germanium compound region are generally described herein. Other embodiments may be described and claimed.06-17-2010
20120313143HIGHLY SCALED ETSOI FLOATING BODY MEMORY AND MEMORY CIRCUIT - A floating body memory cell, memory circuit, and method for fabricating floating body memory cells. The floating body memory cell includes a bi-layer heterojunction having a first semiconductor coupled to a second semiconductor. The first semiconductor and the second semiconductor have different energy band gaps. The floating body memory cell includes a buried insulator layer. The floating body memory cell includes a back transistor gate separated from the second semiconductor of the bi-layer heterojunction by at least the buried insulated layer. The floating body memory cell also includes a front transistor gate coupled to the first semiconductor of the bi-layer heterojunction.12-13-2012
20120161202JUNCTIONLESS ACCUMULATION-MODE DEVICES ON PROMINENT ARCHITECTURES, AND METHODS OF MAKING SAME - A junctionless accumulation-mode (JAM) semiconductive device is isolated from a semiconducive substrate by a reverse-bias band below a prominent feature of a JAM semiconductive body. Processes of making the JAM device include implantation and epitaxy.06-28-2012
20120126289METHOD OF FORMING A SEMICONDUCTOR STRUCTURE - A method of forming a semiconductor structure comprises forming a first layer of silicon and then forming a second, silicon germanium, layer adjacent the silicon layer. A thin third layer of silicon is then formed adjacent the second layer. A gate structure is then formed upon the third layer of silicon using convention Complementary Metal Oxide Semiconductor processes. Trenches are then formed into the second layer and the structure is then exposed to a thermal gaseous chemical etchant, for example heated hydrochloric acid. The etchant removes the silicon germanium, thereby forming a Silicon-On-Nothing structure. Thereafter, conventional CMOS processing techniques are applied to complete the structure as a Metal Oxide Semiconductor Field Effect Transistor, including the formation of spacer walls from silicon nitride, the silicon nitride also filling a cavity formed beneath the third layer of silicon by removal of the silicon germanium.05-24-2012
20100289062Carrier mobility in surface-channel transistors, apparatus made therewith, and systems containing same - A surface channel transistor is provided in a semiconductive device. The surface channel transistor is either a PMOS or an NMOS device. Epitaxial layers are disposed above the surface channel transistor to cause an increased bandgap phenomenon nearer the surface of the device. A process of forming the surface channel transistor includes grading the epitaxial layers.11-18-2010
20120126290NITRIDE SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A nitride semiconductor device includes: a first nitride semiconductor layer; a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a wider band gap than the first nitride semiconductor layer; and a third nitride semiconductor layer formed on the second nitride semiconductor layer. A region of the third nitride semiconductor layer located below the gate electrode is formed with a control region having a p-type conductivity, and a region of the third nitride semiconductor layer located between the gate electrode and each of the source electrode and the drain electrode is formed with a high resistive region having a higher resistance than the that of the control region.05-24-2012
20120126288Semiconductor device and method of manufacturing the same - A semiconductor device having first and second stacks formed successively over a common substrate, in which the first stack that remains after removing the second stack comprises a field effect transistor, the second stack that is stacked over the first stack comprises a device different from the field effect transistor, and the first stack comprising the field effect transistor has an etching stopper layer that defines a stopping position of a recess formed in the first stack and comprises InGaP, a lower compound semiconductor layer that is disposed below a gate electrode disposed in the recess and comprises AlGaAs, and a spacer layer that is interposed between the etching stopper layer and the lower compound semiconductor layer for preventing phosphorus contained in the etching stopper layer from thermally diffusing as far as the lower compound semiconductor layer and chemically bonding with constituents elements of the lower compound semiconductor layer.05-24-2012
20120126287COMPOUND SEMICONDUCTOR DEVICE HAVING INSULATION FILM WITH DIFFERENT FILM THICKNESSES BENEATH ELECTRODES - A compound semiconductor device includes a group-III nitride semiconductor layer; an insulation film located on the group-III nitride semiconductor layer; a drain electrode located in a position which is a first distance away from an upper surface of the group-III nitride semiconductor layer; a source electrode located in a position which is the first distance away from the upper surface of the group-III nitride semiconductor layer; a gate electrode located between the drain electrode and the source electrode; and a field plate electrode located between the drain electrode and the gate electrode at a position which is a second distance away from the upper surface of the group-III nitride semiconductor layer, the second distance is shorter than the first distance.05-24-2012
20120161204Transistor Comprising an Embedded Sigma Shaped Sequentially Formed Semiconductor Alloy - In sophisticated transistors, a specifically designed semiconductor material, such as a strain-inducing semiconductor material, may be sequentially provided in the drain region and the source region, thereby enabling a significant degree of lateral extension of the grown semiconductor materials without jeopardizing mechanical integrity of the transistor during the processing thereof. For example, semiconductor devices having different drain and source sides may be provided on the basis of sequentially provided embedded semiconductor materials.06-28-2012
20120161203Strain Enhancement in Transistors Comprising an Embedded Strain-Inducing Semiconductor Material by Alloy Species Condensation - In transistors requiring a high compressive strain, the germanium contents may be increased by applying a germanium condensation technique. In some illustrative embodiments, an oxidation process is performed in the presence of a silicon/germanium material obtained on the basis of selective epitaxial growth techniques, thereby increasingly oxidizing the silicon species, while driving the germanium into the lower lying areas of the active region, which finally results in an increased germanium concentration.06-28-2012
20100207164FIELD EFFECT TRANSISTOR - A field effect transistor includes a first nitride semiconductor layer 08-19-2010
20110180853CARRIER MOBILITY ENHANCED CHANNEL DEVICES AND METHOD OF MANUFACTURE - An integrated circuit with stress enhanced channels, a design structure and a method of manufacturing the integrated circuit is provided. The method includes forming a dummy gate structure on a substrate and forming a trench in the dummy gate structure. The method further includes filling a portion of the trench with a strain inducing material and filling a remaining portion of the trench with gate material.07-28-2011
20110180852ASYMMETRIC SOURCE/DRAIN JUNCTIONS FOR LOW POWER SILICON ON INSULATOR DEVICES - A semiconductor device includes a buried insulator layer formed on a bulk substrate; a first type semiconductor material formed on the buried insulator layer, and corresponding to a body region of a field effect transistor (FET); a second type of semiconductor material formed over the buried insulator layer, adjacent opposing sides of the body region, and corresponding to source and drain regions of the FET; the second type of semiconductor material having a different bandgap than the first type of semiconductor material; wherein a source side p/n junction of the FET is located substantially within whichever of the first and the second type of semiconductor material having a lower bandgap, and a drain side p/n junction of the FET is located substantially entirely within whichever of the first and the second type of semiconductor material having a higher bandgap.07-28-2011
20110180851CMOS DEVICES WITH A SINGLE WORK FUNCTION GATE ELECTRODE AND METHOD OF FABRICATION - Described herein are a device utilizing a gate electrode material with a single work function for both the pMOS and nMOS transistors where the magnitude of the transistor threshold voltages is modified by semiconductor band engineering and article made thereby. Further described herein are methods of fabricating a device formed of complementary (pMOS and nMOS) transistors having semiconductor channel regions which have been band gap engineered to achieve a low threshold voltage.07-28-2011
20120132957HIGH PERFORMANCE STRAINED SOURCE-DRAIN STRUCTURE AND METHOD OF FABRICATING THE SAME - A method for forming a high performance strained source-drain structure includes forming a gate structure on a substrate and forming a pocket implant region proximate to the gate structure. Spacers are formed adjacent to the gate structure. A dry etch forms a recess with a first contour; a wet etch enlarge the recess to a second contour; and a thermal etch enlarges the recess to a third contour. The source-drain structure is then formed in the recess having the third contour.05-31-2012
20120168819Semiconductor pillar power MOS - A novel semiconductor power transistor is presented. The semiconductor structure is simple and is based on a multi-gate vertical MOS configuration with multi semiconductor pillars, so that the control on the carrier transport is enhanced and the specific on-resistance per area is reduced. Furthermore, due to its particular geometry, the parasitic resistances due to the source/drain junctions, are also drastically reduced with respect to standard CMOS technologies. It offers the advantage of extremely lower on-resistance for the same silicon area while improving on its dynamic performances. The novel structure does not require Silicon On Insulator technologies and can be built using the standard Bulk CMOS process technology. This characteristic improves the thermal properties of the device which are extremely important in power applications.07-05-2012
20100052014SEMICONDUCTOR DEVICE AND FABRICATION METHOD FOR THE SAME - A semiconductor device includes a substrate; a nitride based compound semiconductor layer placed on the substrate; an active area which is placed on the nitride based compound semiconductor layer, and is composed of an aluminum gallium nitride layer (Al03-04-2010
20120248502III-V FIELD EFFECT TRANSISTOR (FET) AND III-V SEMICONDUCTOR ON INSULATOR (IIIVOI) FET, INTEGRATED CIRCUIT (IC) CHIP AND METHOD OF MANUFACTURE - Field Effect Transistors (FETs), Integrated Circuit (IC) chips including the FETs, and a method of forming the FETs and IC. FET locations define FET pedestals on a layered semiconductor wafer that may include a III-V semiconductor surface layer, e.g., Gallium Arsenide (GaAs), and a buried layer, e.g., Aluminum Arsenide (AlAs). A dielectric material, e.g., Aluminum Oxide (AlO), surrounds pedestals at least in FET source/drain regions. A conductive cap caps channel sidewalls at opposite channel ends. III-V on insulator (IIIVOI) devices form wherever the dielectric material layer is thicker than half the device length. Source/drain contacts are formed to the caps and terminate in/above the dielectric material in the buried layer.10-04-2012
20100006895III-NITRIDE SEMICONDUCTOR DEVICE - A III-nitride power switch that includes a III-nitride heterojunction, field dielectric bodies disposed over the heterojunction, and a gate electrode that does not overlap the top surface of the field dielectric bodies and is disposed over a well in the III-nitride heterojunction.01-14-2010
20100006894SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - The semiconductor device includes a P-type group III-V nitride semiconductor layer, an N-type group III-V nitride semiconductor layer, and an electrode in contact with both of the P-type group III-V nitride semiconductor layer and the N-type group III-V nitride semiconductor layer. The electrode includes a first electrode portion made of a first conductive material, and a second electrode portion, made of a second conductive material different from the first conductive material, bonded to the first electrode portion. The first electrode portion is in contact with the P-type group III-V nitride semiconductor layer, and the second electrode portion is in contact with the N-type group III-V nitride semiconductor layer.01-14-2010
20100244097FIELD EFFECT TRANSISTOR - Provided is a GaN based field effect transistor that is capable of normally-off operation, high breakdown voltage and large current. A body electrode 09-30-2010
20120313144RECESSED GATE FIELD EFFECT TRANSISTOR - A semiconductor device having a gate positioned in a recess between the source region and a drain region that are adjacent either side of the gate electrode. A channel region is below a majority of the source region as well as a majority of the drain region and the entire gate electrode.12-13-2012
20120187452SEMICONDUCTOR ELEMENT - According to one embodiment, the semiconductor element includes a first semiconductor layer. The first semiconductor layer contains Al07-26-2012
20120187451SEMICONDUCTOR ELEMENT - According to one embodiment, the semiconductor element includes a semi-insulating substrate which has a first first-conductivity-type layer. The semiconductor element includes a first semiconductor layer. The first semiconductor layer contains non-doped Al07-26-2012
20120187450STI SILICON NITRIDE CAP FOR FLAT FEOL TOPOLOGY - Transistor devices are formed with a nitride cap over STI regions during FEOL processing. Embodiments include forming a pad oxide layer on a substrate, forming an STI region in the substrate so that the top surface is level with the top surface of the pad oxide, forming a nitride cap on the STI region and on a portion of the pad oxide layer on each side of the STI region, implanting a dopant into the substrate, deglazing the nitride cap and pad oxide layer, removing the nitride cap, and removing the pad oxide layer. Embodiments include forming a silicon germanium channel (c-SiGe) in the substrate prior to deglazing the pad oxide layer. The nitride cap protects the STI regions and immediately adjacent area during processes that tend to degrade the STI oxide, thereby providing a substantially divot free substrate and an STI region with a zero step height for the subsequently deposited high-k dielectric and metal electrode.07-26-2012
20120223364TRANSISTORS AND METHODS OF MANUFACTURING THE SAME - In a method of manufacturing a transistor, a gate structure is formed on a substrate including silicon. An upper portion of the substrate adjacent to the gate structure is etched to form a first recess in the substrate. A preliminary first epitaxial layer including silicon-germanium is formed in the first recess. An upper portion of the preliminary first epitaxial layer is etched to form a second recess on the preliminary first epitaxial layer. In addition, a portion of the preliminary first epitaxial layer adjacent to the second recess is etched to thereby transform the preliminary first epitaxial layer into a first epitaxial layer. A second epitaxial layer including silicon-germanium is formed in the second recess located on the first epitaxial layer.09-06-2012
20120187453INSULATING LAYERS ON DIFFERENT SEMICONDUCTOR MATERIALS - A semiconductor structure is provided that includes a substrate having disposed thereon a silicon layer and a silicon germanium layer. An insulator is disposed between the silicon layer and the silicon germanium layer. An optional silicon nitride film is disposed conformally on the silicon layer and the silicon germanium layer, and a SiO07-26-2012
20120228673FIELD-EFFECT TRANSISTOR, SEMICONDUCTOR WAFER, METHOD FOR PRODUCING FIELD-EFFECT TRANSISTOR AND METHOD FOR PRODUCING SEMICONDUCTOR WAFER - Provided is a field-effect transistor including a gate insulating layer, a first semiconductor crystal layer in contact with the gate insulating layer, and a second semiconductor crystal layer lattice-matching or pseudo lattice-matching the first semiconductor crystal layer. Here, the gate insulating layer, the first semiconductor crystal layer, and the second semiconductor crystal layer are arranged in the order of the gate insulating layer, the first semiconductor crystal layer, and the second semiconductor crystal layer, the first semiconductor crystal layer is made of In09-13-2012
20120228672METHOD FOR FORMING A GE ON III/V-ON-INSULATOR STRUCTURE - The present invention concerns a method for forming a Semiconductor-On-Insulator structure that includes a semiconductor layer of III/V material by growing a relaxed germanium layer on a donor substrate; growing at least one layer of III/V material on the layer of germanium; forming a cleaving plane in the relaxed germanium layer; transferring a cleaved part of the donor substrate to a support substrate, with the cleaved part being a part of the donor substrate cleaved at the cleaving plane that includes the at least one layer of III/V material. The present invention also concerns a germanium on III/V-On-Insulator structure, a N Field-Effect Transistor (NFET), a method for manufacturing a NFET, a P Field-Effect Transistor (PFET), and a method for manufacturing a PFET.09-13-2012
20120228671STRAINED GE-ON-INSULATOR STRUCTURE AND METHOD FOR FORMING THE SAME - A strained Ge-on-insulator structure is provided, comprising: a silicon substrate, in which an oxide insulating layer is formed on a surface of the silicon substrate; a Ge layer formed on the oxide insulating layer, in which a first passivation layer is formed between the Ge layer and the oxide insulating layer; a gate stack formed on the Ge layer, a channel region formed below the gate stack, and a source and a drain formed on sides of the channel region; and a SiN stress cap layer covering the gate stack to produce a strain in the channel region. Further, a method for forming the strained Ge-on-insulator structure is also provided.09-13-2012
20100327321Tunnel Field-Effect Transistor with Narrow Band-Gap Channel and Strong Gate Coupling - A semiconductor device and the methods of forming the same are provided. The semiconductor device includes a low energy band-gap layer comprising a semiconductor material; a gate dielectric on the low energy band-gap layer; a gate electrode over the gate dielectric; a first source/drain region adjacent the gate dielectric, wherein the first source/drain region is of a first conductivity type; and a second source/drain region adjacent the gate dielectric. The second source/drain region is of a second conductivity type opposite the first conductivity type. The low energy band-gap layer is located between the first and the second source/drain regions.12-30-2010
20100327320NITRIDE SEMICONDUCTOR DEVICE - A nitride semiconductor device includes: a first semiconductor layer made of first nitride semiconductor; a second semiconductor layer formed on a principal surface of the first semiconductor layer and made of second nitride semiconductor having a bandgap wider than that of the first nitride semiconductor; a control layer selectively formed on, or above, an upper portion of the second semiconductor layer and made of third nitride semiconductor having a p-type conductivity; source and drain electrodes formed on the second semiconductor layer at respective sides of the control layer; a gate electrode formed on the control layer; and a fourth semiconductor layer formed on a surface of the first semiconductor layer opposite to the principal surface, having a potential barrier in a valence band with respect to the first nitride semiconductor and made of fourth nitride semiconductor containing aluminum.12-30-2010
20100327319CONTROL OF TUNNELING JUNCTION IN A HETERO TUNNEL FIELD EFFECT TRANSISTOR - Embodiments of the present disclosure provide a method to fabricate a hetero-junction in a Tunnel Field Effect Transistor (TFET) device configuration (e.g. in a segmented nanowire TFET). Since in prior art devices the highly doped source is in direct contact with the lowly doped or undoped channel, some amount of dopants will diffuse from the source to the channel which cannot be avoided due to the source deposition thermal budget. This out-diffusion reduces the steepness of the doping profile and hence deteriorates the device operation. Particular embodiments comprise the insertion of a thin transition layer in between the source region and channel region such that the out-diffusion is within a very limited region of a few nm, guaranteeing extremely good doping abruptness thanks to the lower diffusion of the dopants in the transition layer. The transition layer avoids the direct contact between the highly doped (e.g. Ge or SiGe) source region and the lowly doped or undoped (e.g. Si) channel and allows to contain the whole doping (e.g. B atoms) entirely within the source region and transition layer. The thickness of the transition layer can be engineered such that the transition layer coincides with the steep transition step from the highly doped source region to the intrinsic region (channel), and hence maximizing the tunneling current.12-30-2010
20100327318SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor device capable of suppressing the occurrence of a punch-through phenomenon is provided. A first n-type conductive layer (12-30-2010
20100327317Germanium on insulator using compound semiconductor barrier layers - Embodiments of an apparatus and methods for providing germanium on insulator using a large bandgap barrier layer are generally described herein. Other embodiments may be described and claimed.12-30-2010
20120319166TRANSISTOR WITH BURIED SILICON GERMANIUM FOR IMPROVED PROXIMITY CONTROL AND OPTIMIZED RECESS SHAPE - A method of forming a semiconductor device that includes providing a substrate including a semiconductor layer on a germanium-containing silicon layer and forming a gate structure on a surface of a channel portion of the semiconductor layer. Well trenches are etched into the semiconductor layer on opposing sides of the gate structure. The etch process for forming the well trenches forms an undercut region extending under the gate structure and is selective to the germanium-containing silicon layer. Stress inducing semiconductor material is epitaxially grown to fill at least a portion of the well trench to provide at least one of a stress inducing source region and a stress inducing drain region having a planar base.12-20-2012
20120319167Mask-less and Implant Free Formation of Complementary Tunnel Field Effect Transistors - A device includes a first source/drain region of a first conductivity type over a silicon substrate, wherein the first source/drain region is at a higher step of a two-step profile. The first source/drain region includes a germanium-containing region. A second source/drain region is of a second conductivity type opposite the first conductivity type, wherein the second source/drain region is at a lower step of the two-step profile. A gate dielectric includes a vertical portion in contact with a side edge the silicon substrate, and a horizontal portion in contact with a top surface of the silicon substrate at the lower step. The horizontal portion is connected to a lower end of the vertical portion. A gate electrode is directly over the horizontal portion, wherein a sidewall of the gate electrode is in contact with the vertical portion of the gate dielectric.12-20-2012
20120319168SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device and manufacturing method therefor includes a Σ-shaped embedded source or drain regions. A U-shaped recess is formed in a Si substrate using dry etching and a SiGe layer is grown epitaxially on the bottom of the U-shaped recess. Using an orientation selective etchant having a higher etching rate with respect to Si than SiGe, wet etching is performed on the Si substrate sidewalls of the U-shaped recess, to form a Σ-shaped recess.12-20-2012
20120261719HETEROJUNCTION BIPOLAR TRANSISTORS AND METHODS OF MANUFACTURE - Semiconductor structures and methods of manufacture semiconductors are provided which relate to heterojunction bipolar transistors. The structure includes two devices connected by metal wires on a same wiring level. The metal wire of a first of the two devices is formed by selectively forming a metal cap layer on copper wiring structures.10-18-2012
20120261718Method And Structure For Compound Semiconductor Contact - The present disclosure provides a buried channel semiconductor structure in which a crystallographic wet etch is used to tailor the profile of etched regions formed into a multilayered substrate which includes a compound semiconductor layer located atop a buried semiconductor channel material layer. The use of crystallographic wet etching on a compound semiconductor allows one to tailor the shape of a source recess region and a drain recess region formed into a multilayered substrate. This allows for the control of gate overlap/underlap. Also, the use of crystallographic wet etching on a compound semiconductor allows independent control of the length of an underlying buried semiconductor channel region.10-18-2012
20110037101SEMICONDUCTOR DEVICE - A semiconductor device includes an undoped GaN layer (02-17-2011
20080277691Production of a Transistor Gate on a Multibranch Channel Structure and Means for Isolating This Gate From the Source and Drain Regions - A method for fabricating a microelectronic device including a support, an etched stack of thin layers including at least one first block and at least one second block resting on the support, in which at least one drain region and at least one source region, respectively, are capable of being formed, plural semiconductor bars connecting a first zone of the first block and another zone of the second block, and able to form a multi-branch transistor channel, or plural transistor channels. A gate surrounds the bars and is located between the first block and the second block, the gate being in contact with a first and second insulating spacer in contact with at least one sidewall of the first block and with at least one sidewall of the second block, respectively, and at least partially separated from the first block and the second block, via the insulating spacers.11-13-2008
20120299062EMBEDDED SILICON GERMANIUM N-TYPE FILED EFFECT TRANSISTOR FOR REDUCED FLOATING BODY EFFECT - A method for fabricating a semiconductor device includes forming a gate stack on an active region of a silicon-on-insulator substrate. The active region is within a semiconductor layer and is doped with an p-type dopant. A gate spacer is formed surrounding the gate stack. A first trench is formed in a region reserved for a source region and a second trench is formed in a region reserved for a drain region. The first and second trenches are formed while maintaining exposed the region reserved for the source region and the region reserved for the drain region. Silicon germanium is epitaxially grown within the first trench and the second trench while maintaining exposed the regions reserved for the source and drain regions, respectively.11-29-2012
20120267683EARLY EMBEDDED SILICON GERMANIUM WITH INSITU BORON DOPING AND OXIDE/NITRIDE PROXIMITY SPACER - Devices are formed with an oxide liner and nitride layer before forming eSiGe spacers. Embodiments include forming first and second gate stacks on a substrate, forming an oxide liner over the first and second gate stacks, forming a nitride layer over the oxide liner, forming a resist over the first gate stack, forming nitride spacers from the nitride layer over the second gate stack, forming eSiGe source/drain regions for the second gate stack, subsequently forming halo/extension regions for the first gate stack, and independently forming halo/extension regions for the second gate stack. Embodiments include forming the eSiGe regions by wet etching the substrate with TMAH using the nitride spacers as a soft mask, forming sigma shaped cavities, and epitaxially growing in situ boron doped eSiGe in the cavities.10-25-2012
20120267685METAL GATE AND HIGH-K DIELECTRIC DEVICES WITH PFET CHANNEL SiGe - In a circuit structure, PFET devices have a gate dielectric including a high-k dielectric, a gatestack with a metal, a p-source/drain and silicide layer formed over the p-source/drain; NFET devices include a gate dielectric including a high-k dielectric, a gatestack with a metal, an n-source/drain and silicide layer formed over the n-source/drain. An epitaxial SiGe is present underneath and in direct contact with the PFET gate dielectric, while the epitaxial SiGe is absent underneath the NFET gate dielectric.10-25-2012
20120267684SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device includes a compound semiconductor substrate; a first conductivity type-channel field-effect transistor region formed on the compound semiconductor substrate, and that includes a first channel layer; a first conductivity type first barrier layer that forms a heterojunction with the first channel layer, and supplies a first conductivity type charge to the first channel layer; and a second conductivity type gate region that has a pn junction-type potential barrier against the first conductivity type first barrier layer; and a second conductivity type-channel field-effect transistor region formed on the compound semiconductor substrate, and that includes a second conductivity type second channel layer, and a first conductivity type gate region that has a pn junction-type potential barrier against the second conductivity type second channel layer.10-25-2012
20110215377Structure and Method for Forming Planar Gate Field Effect Transistor with Low Resistance Channel Region - A vertically-conducting planar-gate field effect transistor includes a silicon region of a first conductivity type, a silicon-germanium layer extending over the silicon region, a gate electrode laterally extending over but being insulated from the silicon-germanium layer, a body region of the second conductivity type extending in the silicon-germanium layer and the silicon region, and source region of the first conductivity type extending in the silicon-germanium layer. The gate electrode laterally overlaps both the source and body regions such that a portion of the silicon germanium layer extending directly under the gate electrode between the source region and an outer boundary of the body region forms a channel region.09-08-2011
20110227132FIELD-EFFECT TRANSISTOR - The present invention has as an object to provide a FET having low on-resistance. The FET according to the present invention includes: first nitride semiconductor layer; a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a higher band gap energy than the first nitride semiconductor layer; a third nitride semiconductor layer formed on the second nitride semiconductor layer; a fourth nitride semiconductor layer formed on the third nitride semiconductor layer and having a higher band gap energy than the third nitride semiconductor layer. A channel is formed in a heterojunction interface between the first nitride semiconductor layer and the second nitride semiconductor layer.09-22-2011
20120080723FABRICATING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE FABRICATED USING THE SAME METHOD - A fabricating method of a semiconductor device includes providing a substrate having a first region and a second region, forming a plurality of first gates in the first region of the substrate, such that the first gates are spaced apart from each other at a first pitch, forming a plurality of second gates in the second region of the substrate, such that the second gates are spaced apart from each other at a second pitch different from the first pitch, implanting an etch rate adjusting dopant into the second region to form implanted regions, while blocking the first region, forming a first trench by etching the first region between the plurality of first gates, and forming a second trench by etching the second region between the plurality of second gates.04-05-2012
20120080722METHOD FOR FORMING STRAINED SEMICONDUCTOR CHANNEL AND SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor substrate; a SiGe relaxed layer on the semiconductor substrate; an NMOS transistor on the SiGe relaxed layer; and a PMOS transistor on the SiGe relaxed layer, in which the NMOS transistor includes a tensile strained epitaxial layer located on the SiGe relaxed layer or embedded in the SiGe relaxed layer; and the PMOS transistor includes a compressive strained epitaxial layer located on the SiGe relaxed layer or embedded in the SiGe relaxed layer. The loss of the strained semiconductor material can be avoided and meanwhile the stress in the channel can be better maintained.04-05-2012
20120080721SEMICONDUCTOR STRUCTURE AND METHOD FOR MAKING THE SAME - A semiconductor structure includes a recess disposed in a substrate, a non-doped epitaxial layer and a doped epitaxial layer. The non-doped epitaxial layer is disposed on the inner surface of the recess and substantially consists of Si and an epitaxial layer. The non-doped epitaxial layer has a sidewall and a bottom which together cover the inner surface. The bottom thickness is not greater than 120% of the sidewall thickness. The non-doped epitaxial layer and the doped epitaxial layer together fill up the recess.04-05-2012
20100230721SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - In one aspect of the present invention, a semiconductor device may include a gate electrode formed on a gate insulation film on a main surface of a semiconductor substrate of a first conductivity type; source/drain regions formed to sandwich a channel region formed below the gate electrode, the source/drain regions having a structure in which a first semiconductor layer and a second semiconductor layer are stacked in this order, the first semiconductor layer containing a first element and an impurity of a second conductivity type that are forgiving strain to the channel region, and containing a second element that is for suppressing a diffusion of the impurity of the second conductivity type, the second semiconductor layer containing the first element and the impurity of the second conductivity type; and source/drain extension regions adjacent to the channel region, the extension regions extending respectively from the second semiconductor layers.09-16-2010
20120280279Field Effect Transistor Device with Shaped Conduction Channel - A field effect transistor device includes a substrate, a silicon germanium (SiGe) layer disposed on the substrate, gate dielectric layer lining a surface of a cavity defined by the substrate and the silicon germanium layer, a metallic gate material on the gate dielectric layer, the metallic gate material filling the cavity, a source region, and a drain region.11-08-2012
20110278646Balance Step-Height Selective Bi-Channel Structure on HKMG Devices - The present disclosure provides a method including forming STI features in a silicon substrate, defining a first and a second active regions for a PFET and an NFET, respectively; forming a hard mask having an opening to expose the silicon substrate within the first active region; etching the silicon substrate through the opening to form a recess within the first active region; growing a SiGe layer in the recess such that a top surface of the SiGe layer within the first active region and a top surface of the silicon substrate within the second active region are substantially coplanar; forming metal gate material layers; patterning the metal gate material layers to form a metal gate stack on the SiGe layer within the first active region; and forming an eSiGe S/D stressor distributed in both the SiGe layer and the silicon substrate within the first active region.11-17-2011
20120091507STRUCTURE OF HETEROJUNCTION FIELD EFFECT TRANSISTOR AND A FABRICATION METHOD THEREOF - An improved structure of heterojunction field effect transistor (HFET) and a fabrication method thereof are disclosed. The improved HFET structure comprises sequentially a substrate, a channel layer, a spacing layer, a carrier supply layer, a Schottky layer, a Schottky capping layer formed by a higher energy gap material, a tunneling layer formed by a lower energy gap material, a first etching stop layer, and a first n type doped layer. The fabrication method is a multiple selective etching process, which comprises steps of: etching the n type doped layer by using a first etching process to form a first indentation; etching first etching stop layer by using a second etching process to form a second indentation located under the first indentation; etching the tunneling layer by using a third etching process to form a third indentation located under the second indentation, wherein the said first, second and third indentations form a single gate groove, in which the gate electrode can form a Schottky contact with the Schottky capping layer that is made of a higher energy gap material.04-19-2012
20120091506Method and Structure for pFET Junction Profile With SiGe Channel - A semiconductor structure including a p-channel field effect transistor (pFET) device located on a surface of a silicon germanium (SiGe) channel is provided in which the junction profile of the source region and the drain region is abrupt. The abrupt source/drain junctions for pFET devices are provided in this disclosure by forming an N- or C-doped Si layer directly beneath a SiGe channel layer which is located above a Si substrate. A structure is thus provided in which the N- or C-doped Si layer (sandwiched between the SiGe channel layer and the Si substrate) has approximately the same diffusion rate for a p-type dopant as the overlying SiGe channel layer. Since the N- or C-doped Si layer and the overlying SiGe channel layer have substantially the same diffusivity for a p-type dopant and because the N- or C-doped Si layer retards diffusion of the p-type dopant into the underlying Si substrate, abrupt source/drain junctions can be formed.04-19-2012
20100258841BACK DIFFUSION SUPPRESSION STRUCTURES - An enhancement-mode GaN transistor, the transistor having a substrate, transition layers, a buffer layer comprised of a III Nitride material, a barrier layer comprised of a III Nitride material, drain and source contacts, a gate containing acceptor type dopant elements, and a diffusion barrier comprised of a III Nitride material between the gate and the buffer layer.10-14-2010
20130009210METAL OXIDE SEMICONDUCTOR HAVING EPITAXIAL SOURCE DRAIN REGIONS AND METHOD OF MANUFACTURING SAME USING DUMMY GATE PROCES - A method of manufacturing a transistor by which sufficient stress can be applied to a channel region within allowable ranges of concentrations of Ge and C in a mixed crystal layer. A semiconductor device is also provided.01-10-2013
20130009209SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - To provide a transistor including an oxide semiconductor layer and having electric characteristics required depending on an intended use and provide a semiconductor device including the transistor, in a transistor in which a semiconductor layer, source and drain electrode layers, a gate insulating film, and a gate electrode are stacked in this order over an oxide semiconductor insulating film, an oxide semiconductor stack layer which includes at least two oxide semiconductor layers with energy gaps different from each other and a mixed region therebetween is used as the semiconductor layer.01-10-2013
20130009211SILICON GERMANIUM FILM FORMATION METHOD AND STRUCTURE - Epitaxial deposition of silicon germanium in a semiconductor device is achieved without using masks. Nucleation delays induced by interactions with dopants present before deposition of the silicon germanium are used to determine a period over which an exposed substrate surface may be subjected to epitaxial deposition to form a layer of SiGe on desired parts with substantially no deposition on other parts. Dopant concentration may be changed to achieve desired thicknesses within preferred deposition times. Resulting deposited SiGe is substantially devoid of growth edge effects.01-10-2013
20130015500SEMICONDUCTOR DEVICEAANM IZUMIDA; TakashiAACI KanagawaAACO JPAAGP IZUMIDA; Takashi Kanagawa JPAANM MIYATA; ToshitakaAACI KanagawaAACO JPAAGP MIYATA; Toshitaka Kanagawa JP - According to one embodiment, a semiconductor device includes a semiconductor protrusion formed on a semiconductor substrate, a source/drain layer provided in a vertical direction of the semiconductor protrusion, a gate electrode provided on a side surface of the semiconductor protrusion through a gate insulating film, and a channel region provided on the side surface of the semiconductor protrusion. The potential height in the channel region is different between the drain layer side and the source layer side.01-17-2013
20130020613SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - This disclosure relates to a semiconductor device and a manufacturing method thereof. The semiconductor device comprises: a patterned stacked structure formed on a semiconductor substrate, the stacked structure comprising a silicon-containing semiconductor layer overlaying the semiconductor substrate, a gate dielectric layer overlaying the silicon-containing semiconductor layer and a gate layer overlaying the gate dielectric layer; and a doped epitaxial semiconductor layer on opposing sides of the silicon-containing semiconductor layer forming raised source/drain extension regions. Optionally, the silicon-containing semiconductor layer may be used as a channel region. According to this disclosure, the source/drain extension regions can be advantageously made to have a shallow junction depth (or a small thickness) and a high doping concentration.01-24-2013
20120241818TWO-DIMENSIONAL CONDENSATION FOR UNIAXIALLY STRAINED SEMICONDUCTOR FINS - Techniques are disclosed for enabling multi-sided condensation of semiconductor fins. The techniques can be employed, for instance, in fabricating fin-based transistors. In one example case, a strain layer is provided on a bulk substrate. The strain layer is associated with a critical thickness that is dependent on a component of the strain layer, and the strain layer has a thickness lower than or equal to the critical thickness. A fin is formed in the substrate and strain layer, such that the fin includes a substrate portion and a strain layer portion. The fin is oxidized to condense the strain layer portion of the fin, so that a concentration of the component in the strain layer changes from a pre-condensation concentration to a higher post-condensation concentration, thereby causing the critical thickness to be exceeded.09-27-2012
20120241817SEMICONDUCTOR DEVICE - According to an embodiment, a semiconductor device includes a first semiconductor layer, a second semiconductor layer, a control electrode, a third semiconductor layer, first and second main electrodes. The second semiconductor layer is provided on the first semiconductor layer, and has a higher impurity concentration than the first semiconductor layer. The control electrode is provided inside a first trench with an insulating film interposed, the first trench reaching the first semiconductor layer from a front surface of the second semiconductor layer. The third semiconductor layer is provided inside a second trench and including Si09-27-2012
20120241816Stabilization of Metal Silicides in PFET Transistors by Incorporation of Stabilizing Species in a Si/Ge Semiconductor Material - When forming sophisticated P-channel transistors, the metal silicide agglomeration in a germanium-containing strain-inducing semiconductor alloy may be avoided or at least significantly reduced by incorporating a carbon and/or nitrogen species in a highly controllable manner. In some illustrative embodiments, the carbon species or nitrogen species is incorporated during the epitaxial growth process so as to form a surface layer of the strain-inducing semiconductor alloy with a desired nitrogen and/or carbon concentration and with a desired thickness without unduly affecting any other device areas.09-27-2012
20100090250SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor layer; at least one electrode formed on a semiconductor layer to be in contact with the semiconductor layer; and a passivation film covering the semiconductor layer and at least part of the top surface of the electrode to protect the semiconductor layer and formed of a plurality of sub-films. The passivation film includes a first sub-film made of aluminum nitride.04-15-2010
20130168736METHOD FOR GROWING CONFORMAL EPI LAYERS AND STRUCTURE THEREOF - A method for forming a conformal buffer layer of uniform thickness and a resulting semiconductor structure are disclosed. The conformal buffer layer is used to protect highly-doped extension regions during formation of an epitaxial layer that is used for inducing mechanical stress on the channel region of transistors.07-04-2013
20130140605GaN high voltage HFET with passivation plus gate dielectric multilayer structure - A method of fabricating a multi-layer structure for a power transistor device includes performing, within a reaction chamber, a nitrogen plasma strike, resulting in the formation of a nitride layer directly on a nitride-based active semiconductor layer. A top surface of the nitride layer is then exposed to a second source. A subsequent nitrogen-oxygen plasma strike results in the formation of an oxy-nitride layer directly on the nitride layer. The nitride layer comprises a passivation layer and the oxy-nitride layer comprises a gate dielectric of the power transistor device.06-06-2013
20120248503SEMICONDUCTOR MEMORY CELL, DEVICE, AND METHOD FOR MANUFACTURING THE SAME - A semiconductor memory cell, a semiconductor memory device, and a method for manufacturing the same are disclosed. The semiconductor memory cell may comprise: a substrate; a channel region on the substrate; a gate region above the channel region; a source region and a drain region on the substrate and at opposite sides of the channel region; and a buried layer, which is disposed between the substrate and the channel region and comprises a material having a forbidden band narrower than that of a material for the channel region material. The buried layer material has a forbidden band narrower than that of the channel region material, so that a hole barrier is formed in the buried layer. Due to the barrier, it is difficult for holes stored in the buried layer to leak out, resulting in an improved information holding duration of the memory cell utilizing the floating-body effect.10-04-2012
20120248501SELF-ALIGNED III-V FIELD EFFECT TRANSISTOR (FET), INTEGRATED CIRCUIT (IC) CHIP WITH SELF-ALIGNED III-V FETS AND METHOD OF MANUFACTURE - Field Effect Transistors (FETs), Integrated Circuit (IC) chips including the FETs, and a method of forming the FETs and IC. FET locations are defined on a layered semiconductor wafer. The layered semiconductor wafer preferably includes a III-V semiconductor surface layer, e.g., Gallium Arsenide (GaAs), and a buried layer, e.g., Aluminum Arsenide (AlAs). Portions of the buried layer are converted to dielectric material, e.g., Aluminum Oxide (AlO), at least beneath FET source/drain regions. The converted dielectric material may extend completely under the FET. Source/drain contacts are formed to FETs above the dielectric material in the buried layer.10-04-2012
20130175578IO ESD Device and Methods for Forming the Same - A method includes forming an ESD diode including performing an epitaxy growth to form an epitaxy region comprising silicon and substantially free from germanium. The epitaxy region is doped with a p-type impurity to form a p-type region, wherein the p-type region forms an anode of the ESD diode.07-11-2013
20130175579TRANSISTOR WITH RECESSED CHANNEL AND RAISED SOURCE/DRAIN - A transistor includes a first semiconductor layer. A second semiconductor layer is located on the first semiconductor layer. A portion of the second semiconductor layer is removed to expose a first portion of the first semiconductor layer and to provide vertical sidewalls of the second semiconductor layer. A gate spacer is located on the second semiconductor layer. A gate dielectric includes a first portion located on the first portion of the first semiconductor layer and a second portion adjacent to the vertical sidewalls of the second semiconductor layer. A gate conductor is located on the first portion of the gate dielectric and abuts the gate dielectric second portion. A channel region is located in at least part of the first portion of the first semiconductor layer. Raised source/drain regions are located in the second semiconductor layer. At least part of the raised source/drain regions is located below the gate spacer.07-11-2013
20130113019SEMICONDUCTOR DEVICE WITH REDUCED THRESHOLD VARIABILITY HAVING A THRESHOLD ADJUSTING SEMICONDUCTOR ALLOY IN THE DEVICE ACTIVE REGION - Generally, the subject matter disclosed herein is directed to semiconductor devices with reduced threshold variability having a threshold adjusting semiconductor material in the device active region. One illustrative semiconductor device disclosed herein includes an active region in a semiconductor layer of a semiconductor device substrate, the active region having a region length and a region width that are laterally delineated by an isolation structure. The semiconductor device further includes a threshold adjusting semiconductor alloy material layer that is positioned on the active region substantially without overlapping the isolation structure, the threshold adjusting semiconductor alloy material layer having a layer length that is less than the region length. Additionally, the disclosed semiconductor device includes a gate electrode structure that is positioned above the threshold adjusting semiconductor alloy material layer, the gate electrode structure including a high-k dielectric material and a metal-containing electrode material formed above the high-k dielectric material.05-09-2013
20130126942SEMICONDUCTOR DEVICE - A low-loss GaN-based semiconductor device is provided.05-23-2013
20110272740FIELD EFFECT TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - A field-effect transistor includes a first semiconductor layer formed on a substrate, and a second semiconductor layer. The first semiconductor layer has a containing region provided as an isolation region which contains non-conductive impurities, and a non-containing region which contains no non-conductive impurities. A first region is defined by a vicinity of a portion of the interface between the containing region and the non-containing region, the portion of the interface being below a gate electrode, the vicinity including the portion of the interface and being included in the containing region. The second semiconductor layer includes a second region which is located directly above the first region. The concentration of the non-conductive impurities of the second region is lower than that of the first region.11-10-2011
20110272739METHOD FOR FABRICATING A STRAINED STRUCTURE - A structure for a field effect transistor on a substrate that includes a gate stack, an isolation structure and a source/drain (S/D) recess cavity below the top surface of the substrate disposed between the gate stack and the isolation structure. The recess cavity having a lower portion and an upper portion. The lower portion having a first strained layer and a first dielectric film. The first strained layer disposed between the isolation structure and the first dielectric film. A thickness of the first dielectric film less than a thickness of the first strained layer. The upper portion having a second strained layer overlying the first strained layer and first dielectric film.11-10-2011
20130134481Split-Channel Transistor and Methods for Forming the Same - A Fin Field-Effect Transistor (FinFET) includes a fin, which includes a channel splitter having a first bandgap, and a channel including a first portion and a second portion on opposite sidewalls of the channel splitter. The channel has a second bandgap smaller than the first bandgap. A gate electrode includes a first portion and a second portion on opposite sides of the fin. A gate insulator includes a first portion between the first portion of the gate electrode and the first portion of the channel, and a second portion between the second portion of the gate electrode and the second portion of the channel.05-30-2013
20110215376PRE-GATE, SOURCE/DRAIN STRAIN LAYER FORMATION - A method produces a transistor. The method forms a strain-producing layer on a base layer and then removes at least one portion of the strain-producing layer to create at least one opening in the strain-producing layer. This leaves first and second portions of the strain-producing layer on the substrate. The first and second portions of the strain-producing layer comprise source and drain stressor regions of the transistor. The method then grows a channel region in the opening of the strain-producing layer from the base layer, forms a gate insulator on the channel region, and forms a gate conductor on the gate insulator.09-08-2011
20130146943IN SITU GROWN GATE DIELECTRIC AND FIELD PLATE DIELECTRIC - Methods and apparatuses are disclosed for providing heterostructure field effect transistors (HFETs) with high-quality gate dielectric and field plate dielectric. The gate dielectric and field plate dielectric are in situ deposited on a semiconductor surface. The location of the gate electrode may be defined by etching a first pattern in the field plate dielectric and using the gate dielectric as an etch-stop. Alternatively, an additional etch-stop layer may be in situ deposited between the gate dielectric and the field plate dielectric. After etching the first pattern, a conductive material may be deposited and patterned to define the gate electrode. Source and drain electrodes that electrically contact the semiconductor surface are formed on opposite sides of the gate electrode.06-13-2013
20130146944SEMICONDUCTOR DEVICE INCLUDING STEPPED GATE ELECTRODE AND FABRICATION METHOD THEREOF - Disclosed are a semiconductor device including a stepped gate electrode and a method of fabricating the semiconductor device. The semiconductor device according to an exemplary embodiment of the present disclosure includes: a semiconductor substrate having a structure including a plurality of epitaxial layers and including an under-cut region formed in a part of a Schottky layer in an upper most part thereof; a cap layer, a first nitride layer and a second nitride layer sequentially formed on the semiconductor substrate to form a stepped gate insulating layer pattern; and a stepped gate electrode formed by depositing a heat-resistant metal through the gate insulating layer pattern, wherein the under-cut region includes an air-cavity formed between the gate electrode and the Schottky layer.06-13-2013
20130146945FIELD EFFECT TRANSISTOR WITH NARROW BANDGAP SOURCE AND DRAIN REGIONS AND METHOD OF FABRICATION - A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.06-13-2013
20130146946SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING SAME - A semiconductor device includes: a buffer layer provided on a substrate and made of a group III-V nitride semiconductor; a first semiconductor layer provided on the buffer layer and made of a group III-V nitride semiconductor; a second semiconductor layer provided on the first semiconductor layer and made of a group III-V nitride semiconductor; a back electrode provided on a back surface of the substrate and connected to a ground; a source electrode and a drain electrode provided on the second semiconductor layer so as to be apart from each other; a gate electrode provided on the second semiconductor layer; and a plug which passes through the second semiconductor layer, the first semiconductor layer, and the buffer layer, and reaches at least the substrate to electrically connect the source electrode and the back electrode.06-13-2013
20110210376INSULATED GATE FIELD EFFECT TRANSISTOR HAVING PASSIVATED SCHOTTKY BARRIERS TO THE CHANNEL - A transistor includes a semiconductor channel disposed nearby a gate and in an electrical path between a source and a drain, wherein the channel and at least one of the source or the drain are separated by an interface layer so as to form a channel-interface layer-source/drain junction in which a Fermi level of the semiconductor channel is depinned in a region near the junction and the junction has a specific contact resistance of less than approximately 1000 Ω-μm09-01-2011
20080197380Semiconductor component comprising a drift zone and a drift control zone - A semiconductor component is disclosed herein comprising a drift zone and a drift control zone. The drift control zone is arranged adjacent to the drift zone and is dielectrically insulated from the drift zone by a dielectric layer. The drift control zone includes at least one first semiconductor layer and one second semiconductor layer. The first semiconductor layer has a higher charge carrier mobility than the second semiconductor layer.08-21-2008
20100308373FIELD-EFFECT TRANSISTOR - A field-effect transistor provided with a substrate, a channel layer, a carrier supply layer, a source electrode, a drain electrode, a gate electrode, a first insulating layer that is laminated on the carrier supply layer between the source electrode and the drain electrode, and suppresses current collapse, an opening that is formed between an edge of the first insulating layer opposing the drain electrode and the drain electrode, and a second insulating layer that is laminated on the carrier supply layer exposed in the opening.12-09-2010
20110233611SEMICONDUCTOR DEVICE HAVING ANALOG TRANSISTOR WITH IMPROVED OPERATING AND FLICKER NOISE CHARACTERISTICS AND METHOD OF MAKING SAME - A semiconductor device with improved transistor operating and flicker noise characteristics includes a substrate, an analog NMOS transistor and a compressively-strained-channel analog PMOS transistor disposed on the substrate. The device also includes a first etch stop liner (ESL) and a second ESL which respectively cover the NMOS transistor and the PMOS transistor. The relative measurement of flicker noise power of the NMOS and PMOS transistors to flicker noise power of reference unstrained-channel analog NMOS and PMOS transistors at a frequency of 500 Hz is less than 1.09-29-2011
20110233610Nonvolatile Memory Devices Having Memory Cell Transistors Therein with Lower Bandgap Source/Drain Regions - Nonvolatile memory devices include a plurality of nonvolatile memory cell transistors having respective channel regions within a semiconductor layer formed of a first semiconductor material and respective source/drain regions formed of a second semiconductor material, which has a smaller bandgap relative to the first semiconductor material. The source/drain regions can form non-rectifying junctions with the channel regions. The source/drain regions may include germanium (e.g., Ge or SiGe regions), the semiconductor layer may be a P-type silicon layer and the source/drain regions of the plurality of nonvolatile memory cell transistors may be P-type germanium or P-type silicon germanium.09-29-2011
20100314663SEMICONDUCTOR DEVICE - One embodiment of a semiconductor device according to the present invention includes a substrate, a base compound semiconductor layer layered on the substrate to form a base, a channel defining compound semiconductor layer layered on the base compound semiconductor layer to define a channel, and an impact ionization control layer that is layered within a layering range of the base compound semiconductor layer and controls the location of impact ionization, wherein the base compound semiconductor layer is formed of a first compound semiconductor, the channel defining compound semiconductor layer is formed of a second compound semiconductor, and the impact ionization control layer is formed of a third compound semiconductor that has a smaller band gap than the first compound semiconductor.12-16-2010
20130153966SEMICONDUCTOR DEVICE - A semiconductor device includes: a first semiconductor layer made of an Al06-20-2013
20130153964FETs with Hybrid Channel Materials - Techniques for employing different channel materials within the same CMOS circuit are provided. In one aspect, a method of fabricating a CMOS circuit includes the following steps. A wafer is provided having a first semiconductor layer on an insulator. STI is used to divide the first semiconductor layer into a first active region and a second active region. The first semiconductor layer is recessed in the first active region. A second semiconductor layer is epitaxially grown on the first semiconductor layer, wherein the second semiconductor layer comprises a material having at least one group III element and at least one group V element. An n-FET is formed in the first active region using the second semiconductor layer as a channel material for the n-FET. A p-FET is formed in the second active region using the first semiconductor layer as a channel material for the p-FET.06-20-2013
20130153965STRAINED TRANSISTOR INTEGRATION FOR CMOS - Various embodiments of the invention relate to a CMOS device having (1) an NMOS channel of silicon material selectively deposited on a first area of a graded silicon germanium substrate such that the selectively deposited silicon material experiences a tensile strain caused by the lattice spacing of the silicon material being smaller than the lattice spacing of the graded silicon germanium substrate material at the first area, and (2) a PMOS channel of silicon germanium material selectively deposited on a second area of the substrate such that the selectively deposited silicon germanium material experiences a compressive strain caused by the lattice spacing of the selectively deposited silicon germanium material being larger than the lattice spacing of the graded silicon germanium substrate material at the second area.06-20-2013
20110303951SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - The present application discloses a semiconductor device and a method for manufacturing the same. The semiconductor device comprises a semiconductor substrate; a first semiconductor layer on the semiconductor substrate; a second semiconductor layer surrounding the first semiconductor layer; a high k dielectric layer and a gate conductor formed on the first semiconductor layer; source/drain regions formed in the second semiconductor layer, wherein the second semiconductor layer has a slant sidewall in contact with the first semiconductor layer. The semiconductor device has an increased output current, an increased operating speed, and a reduced power consumption due to the channel region of high mobility.12-15-2011
20110303950FABRICATION OF A VERTICAL HETEROJUNCTION TUNNEL-FET - Exemplary embodiments include a method for fabricating a heterojunction tunnel field-effect-transistor (FET), the method including forming a gate region on a silicon layer of a silicon-on-insulator (SOI) substrate, forming a drain region on the silicon layer adjacent the gate region and forming a vertical heterojunction source region adjacent the gate region, wherein the vertical heterojunction source region generates a tunnel path inline with a gate field associated with the gate region.12-15-2011
20110309411FIELD EFFECT TRANSISTOR - An insulating film is provided over one surface of a first semiconductor layer including a first oxide semiconductor including indium as a main component, and a second semiconductor layer including an i-type second oxide semiconductor is provided in contact with the other surface. The energy difference between a vacuum level and a Fermi level in the second oxide semiconductor is larger than that in the first oxide semiconductor. In the first semiconductor layer, a region in the vicinity of the junction surface with the second oxide semiconductor which satisfies the above condition is a region having an extremely low carrier concentration (a quasi-i-type region). By using the region as a channel, the off-state current can be reduced. Further, a drain current of the FET flows through the first oxide semiconductor having a high mobility; accordingly, a large amount of current can be extracted.12-22-2011
20120018781MODULATION-DOPED MULTI-GATE DEVICES - Modulation-doped multi-gate devices are generally described. In one example, an apparatus includes a semiconductor substrate having a surface, one or more buffer films coupled to the surface of the semiconductor substrate, a first barrier film coupled to the one or more buffer films, a multi-gate fin coupled to the first barrier film, the multi-gate fin comprising a source region, a drain region, and a channel region of a multi-gate device wherein the channel region is disposed between the source region and the drain region, a spacer film coupled to the multi-gate fin, and a doped film coupled to the spacer film.01-26-2012
20120018780SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a method is disclosed for manufacturing a semiconductor device. A side face parallel to a channel direction of a plurality of gate electrodes provided via a gate insulating film above a semiconductor substrate is included as a part of an inner wall of an isolation groove provided between the adjacent gate electrodes. The method can include forming a protection film covering the side face of the gate electrode. The method can include etching the semiconductor substrate using the gate electrode as a mask to form the isolation groove. The side face of the gate electrode is covered with the protection film. The method can include forming a first insulating film by oxidizing a surface of the isolation groove to fill a bottom portion of the isolation groove. In addition, the method can include forming a second insulating film on the first insulating film to fill an upper portion of the isolation groove including the side face of the gate electrode.01-26-2012
20130193481FIELD EFFECT TRANSISTOR AND A METHOD OF FORMING THE TRANSISTOR - Disclosed are embodiments of a metal oxide semiconductor field effect transistor (MOSFET) structure and a method of forming the structure. The structure incorporates source/drain regions and a channel region between the source/drain regions. The source/drain regions can comprise silicon, which has high diffusivity to the source/drain dopant. The channel region can comprise a silicon alloy selected for optimal charge carrier mobility and band energy and for its low source/drain dopant diffusivity. During processing, the source/drain dopant can diffuse into the edge portions of the channel region. However, due to the low diffusivity of the silicon alloy to the source/drain dopant, the dopant does not diffuse deep into channel region. Thus, the edge portions of the silicon alloy channel region can have essentially the same dopant profile as the source/drain regions, but a different dopant profile than the center portion of the silicon alloy channel region.08-01-2013
20130193482Fin Structures with Damage-Free Sidewalls for Multi-Gate Mosfets - Improved Fin Field Effect Transistors (FinFET) are provided, as well as improved techniques for forming fins for a FinFET. A fin for a FinFET is formed by forming a semi-insulating layer on an insulator that gives a sufficiently large conduction band offset (ΔE08-01-2013
20130193483Mosfet Structures Having Compressively Strained Silicon Channel - MOSFET structures are provided having a compressively strained silicon channel. A semiconductor device is provided that comprises a field effect transistor (FET) structure having a gate stack on a silicon substrate, wherein the field effect transistor structure comprises a channel formed below the gate stack; and a compressively strained silicon layer on at least a portion of the silicon substrate to compressively strain the channel.08-01-2013
20130193484FIELD-EFFECT TRANSISTOR ON A SELF-ASSEMBLED SEMICONDUCTOR WELL - A device including at least one transistor on a substrate in a first semiconductor material, each transistor including a gate electrode as a gate, two conductor electrodes, an island in a second semiconductor material inlaid in the substrate, defining a region capable of forming a channel as a channel region, and an insulating layer separating the gate from the two electrodes and the channel region. The channel region is inside the island and is in direct electrical contact with at least one of the two conductor electrodes.08-01-2013
20130200434USE OF CONTACTS TO CREATE DIFFERENTIAL STRESSES ON DEVICES - Disclosed herein are various methods and structures using contacts to create differential stresses on devices in an integrated circuit (IC) chip. An IC chip is disclosed having a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET), a PFET contact to a source/drain region of the PFET and an NFET contact to a source/drain region of the NFET. In a first embodiment, a silicon germanium (SiGe) layer is included only under the PFET contact, between the PFET contact and the source/drain region of the PFET. In a second embodiment, either the PFET contact extends into the source/drain region of the PFET or the NFET contact extends into the source/drain region of the NFET.08-08-2013
20120086048SEMICONDUCTOR DEVICES AND METHODS FOR MANUFACTURING THE SAME - Semiconductor devices and methods of manufacturing semiconductor devices. A semiconductor device includes a metal gate electrode stacked on a semiconductor substrate with a gate insulation layer disposed therebetween, spacer structures disposed on the semiconductor substrate at both sides of the metal gate electrode, source/drain regions formed in the semiconductor substrate at the both sides of the metal gate electrode, and an etch stop pattern including a bottom portion covering the source/drain regions and a sidewall portion extended from the bottom portion to cover a portion of sidewalls of the spacer structures, in which an upper surface of the sidewall portion of the etch stop pattern is positioned under an upper surface of the metal gate electrode.04-12-2012
20130207162HIGH PERFORMANCE MULTI-FINGER STRAINED SILICON GERMANIUM CHANNEL PFET AND METHOD OF FABRICATION - A field effect transistor and method of fabrication are provided. The field effect transistor comprises a plurality of elongated uniaxially-strained SiGe regions disposed on a silicon substrate, oriented such that they are in parallel to the direction of flow of electrical carriers in the channel. The elongated uniaxially-strained SiGe regions are oriented perpendicular to, and traverse through the transistor gate.08-15-2013

Patent applications in class Field effect transistor

Patent applications in all subclasses Field effect transistor