| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 257133000 |
Combined with field effect transistor
| 387 |
| 257173000 |
Device protection (e.g., from overvoltage)
| 73 |
| 257119000 |
Bidirectional rectifier with control electrode (gate) (e.g., Triac)
| 35 |
| 257109000 |
Having only two terminals and no control electrode (gate), e.g., Shockley diode
| 26 |
| 257146000 |
Combined with other solid-state active device in integrated structure
| 7 |
| 257147000 |
With extended latchup current level (e.g., gate turn off "GTO" device)
| 6 |
| 257168000 |
With means to increase breakdown voltage | 5 |
| 20130099280 | OVERVOLTAGE AND/OR ELECTROSTATIC DISCHARGE PROTECTION DEVICE - An overvoltage protection devices operable to provide protection against overvoltage events of positive and negative polarity, comprising: an N P N semiconductor structure defining: a first N-type region; a first P-type region; and a second N-type region; wherein one of the first or second N-type regions is connected to a terminal, conductor or node that is to be protected against an overvoltage event, and the other one of the first or second N-type regions is connected to a reference, and wherein a field plate is in electrical contact with the first P-type region, and the field plate overlaps with but is isolated from portions of the first and second N type regions. | 04-25-2013 |
| 20100078677 | SEMICONDUCTOR DEVICE - A semiconductor device comprises a semiconductor substrate having a first semiconductor region of a first semiconductor type, a second semiconductor region of a second conductivity type extended in the first semiconductor region, and a mesa area forming a slope along an outer circumference of the semiconductor substrate; a first electrode provided on a first principal surface of the semiconductor substrate; and a second electrode provided on a second principal surface of the semiconductor substrate that is opposed to the first principal surface; wherein the second semiconductor region comprises a main region provided in the semiconductor substrate while being brought into contact with the first electrode, the main region including an annular portion and diffused portions arranged in a spread manner in an area surrounded by the annular portion; and wherein a portion of the first semiconductor region is interposed between the diffused portions and between the diffused portions and the annular portion; and the diffused portions are composed of a small pitch region and a large pitch region having a larger pitch than that of the small pitch region. | 04-01-2010 |
| 20120286327 | OVERVOLTAGE AND/OR ELECTROSTATIC DISCHARGE PROTECTION DEVICE - An overvoltage protection device in combination with a filter, the overvoltage protection device having a first node for connection to a node to be protected, a second node for connection to a discharge node; and a control node; and wherein the filter comprises at least one of: (a) a capacitor connected between the first node and the discharge node; (b) a capacitor connected between the control node and the discharge node; or (c) an inductor in series connection with the first node. | 11-15-2012 |
| 20120098031 | DUAL-DIRECTIONAL SILICON CONTROLLED RECTIFIER - A Dual-directional Silicon Controlled Rectifier (DSCR) includes a substrate of a first conductivity type, a buried layer formed on the substrate and of a second conductivity type, a first well and a second well formed on the buried layer and of the first conductivity type, a third well formed between the first well and the second well and of the second conductivity type, and a doped region formed between a first semiconductor region and a third semiconductor region and of the second conductivity type. The doped region includes a part of the third well. The DSCR may regulate a breakdown voltage of a junction thereof. Therefore, when an I/O voltage of an Integrated Circuit (IC) is much higher than a working voltage, a false action may not occur. | 04-26-2012 |
| 20100038676 | Semiconductor Devices with a Field Shaping Region - A semiconductor device includes a semiconductor region having a pn junction and a field shaping region located adjacent the pn junction to increase the reverse breakdown voltage of the device. The field shaping region is coupled via capacitive voltage coupling regions to substantially the same voltages as are applied to the pn junction. When a reverse voltage is applied across the pn junction and the device is non-conducting, a capacitive electric field is present in a part of the field shaping region which extends beyond a limit of the pn junction depletion region which would exist in the absence of the field shaping region. The electric field in the field shaping region inducing a stretched electric field limited to a correspondingly stretched pn junction depletion region in the semiconductor region. | 02-18-2010 |
| 257162000 |
Lateral structure | 4 |
| 20080237632 | III-nitride power semiconductor device - A III-nitride power semiconductor device that includes a first III-nitride power semiconductor device and a second III-nitride power semiconductor device formed in a common semiconductor die and operatively integrated to form a half-bridge. | 10-02-2008 |
| 20090140290 | SEMICONDUCTOR COMPONENT INCLUDING A SHORT-CIRCUIT STRUCTURE - A semiconductor component including a short-circuit structure. One embodiment provides a semiconductor component having a semiconductor body composed of doped semiconductor material. The semiconductor body includes a first zone of a first conduction type and a second zone of a second conduction type, complementary to the first conduction type, the second zone adjoining the first zone. The first zone and the second zone are coupled to an electrically highly conductive layer. A connection zone of the second conduction type is arranged between the second zone and the electrically highly conductive layer. | 06-04-2009 |
| 20100163924 | LATERAL SILICON CONTROLLED RECTIFIER STRUCTURE - A lateral silicon controlled rectifier structure includes a P-type substrate; an N-well region in the P-type substrate; a first P | 07-01-2010 |
| 20110147794 | STRUCTURE AND METHOD FOR A SILICON CONTROLLED RECTIFIER (SCR) STRUCTURE FOR SOI TECHNOLOGY - A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a P+-N body diode and an N+-P body diode. The P+-N body diode and the N+-P body diode are laterally integrated. | 06-23-2011 |
| 257132000 |
Five or more layer unidirectional structure | 3 |
| 20110220961 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the second conductivity type, a fourth semiconductor region of the first conductivity type, a first control electrode, a first main electrode, a fifth semiconductor region of the first conductivity type, a sixth semiconductor region of the second conductivity type, a second main electrode and a semiconductor element. The semiconductor element is connected between the first main electrode and the third semiconductor region. In addition, the semiconductor element includes a channel using part of the first semiconductor region and a second control electrode configured to control the channel on the one major surface of the first semiconductor region. | 09-15-2011 |
| 20120193675 | ESD Protection Device - Electrostatic discharge (ESD) protection is provided for discharging current between input and output nodes. In accordance with various embodiments, an ESD protection device includes an open-base transistor having an emitter connected to the input node and a collector connected to pass current to the output node via a resistor in response to a voltage at the input node exceeding a threshold that causes the transistor to break down. The resistor is coupled across emitter and collector regions of a second open-base transistor that is configured to turn on for passing current in response to the current across the resistor exceeding a threshold that applies a threshold breakdown voltage across the second transistor. In some implementations, an emitter and/or base of the second transistor are connected to, or are respectively the same region as, a base and a collector of the first transistor. | 08-02-2012 |
| 20110186907 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A sinker layer is in contact with a first conductivity-type well and a second conductivity-type drift layer, respectively, and is separated from a first conductivity-type collector layer. A second conductivity-type diffusion layer (second second-conductivity-type high-concentration diffusion layer) is formed in the surface layer of the sinker layer. The second conductivity-type diffusion layer has a higher impurity concentration than that of the sinker layer. The second conductivity-type diffusion layer and the first conductivity-type collector layer are isolated from each other with an element isolation insulating film interposed therebetween. | 08-04-2011 |
| 257175000 |
With means to control triggering (e.g., gate electrode configuration, Zener diode firing, dV/Dt control, transient control by ferrite bead, etc.) | 2 |
| 20120012892 | HIGH DENSITY THYRISTOR RANDOM ACCESS MEMORY DEVICE AND METHOD - Memory devices and methods of making memory devices are shown. Methods and configurations as shown provide folded and vertical memory devices for increased memory density. Methods provided allow trace wiring in a memory array to be formed on or near a surface of a memory device. | 01-19-2012 |
| 20130009208 | HIGH DENSITY THYRISTOR RANDOM ACCESS MEMORY DEVICE AND METHOD - Memory devices and methods of making memory devices are shown. Methods and configurations as shown provide folded and vertical memory devices for increased memory density. Methods provided allow trace wiring in a memory array to be formed on or near a surface of a memory device. | 01-10-2013 |
| 257113000 |
With light activation | 2 |
| 20110284920 | LASER PUMPING OF THYRISTORS FOR FAST HIGH CURRENT RISE-TIMES - An optically triggered semiconductor switch includes an anode metallization layer; a cathode metallization layer; a semiconductor between the anode metallization layer and the cathode metallization layer and a photon source. The semiconductor includes at least four layers of alternating doping in the form P-N-P-N, in which an outer layer adjacent to the anode metallization layer forms an anode and an outer layer adjacent the cathode metallization layer forms a cathode and in which the anode metallization layer has a window pattern of optically transparent material exposing the anode layer to light. The photon source emits light having a wavelength, with the light from the photon source being configured to match the window pattern of the anode metallization layer. | 11-24-2011 |
| 20120098029 | PHOTONICALLY-ACTIVATED SINGLE-BIASFAST-SWITCHING INTEGRATED THYRISTOR - Preferred embodiments of the invention include a thyristor core that is single biased by a source, such as a power source (or a portion thereof) that is being switched through the thyristors. An optically activated transistor that is preferably a minority carrier device is in series with the thyristor core. The thyristor core has an optically activated gate. The turn-off of the thyristor can be accelerated by the turn-on (conduction state) of a gate switch, which ensures a unity gain turn-off of the core thyristor. | 04-26-2012 |
| 257157000 |
With integrated trigger signal amplification means (e.g., amplified gate, "pilot thyristor", etc.) | 2 |
| 20120043583 | LOW LEAKAGE, LOW CAPACITANCE ELECTROSTATIC DISCHARGE (ESD) SILICON CONTROLLED RECITIFER (SCR), METHODS OF MANUFACTURE AND DESIGN STRUCTURE - A low leakage, low capacitance diode based triggered electrostatic discharge (ESD) silicon controlled rectifiers (SCR), methods of manufacture and design structure are provided. The method includes providing a silicon film on an insulator layer. The method further includes forming isolation regions which extend from an upper side of the silicon layer to the insulator layer. The method further includes forming one or more diodes in the silicon layer, including a p+ region and an n+ region formed in a well bordered by the isolation regions. The isolation regions isolate the one or more diodes in a vertical direction and the insulator layer isolates the one or more diodes from an underlying P or N type substrate, in a horizontal direction. | 02-23-2012 |
| 20090057714 | THYRISTOR AND METHODS FOR PRODUCING A THYRISTOR - A thyristor having a semiconductor body in which a p-doped emitter, an n-doped base, a p-doped base and an n-doped main emitter are arranged successively in a vertical direction starting from a rear face toward a front face. For buffering of the transient heating, a metallization is applied to the front face and/or to the rear face and includes at least one first section which has an area-specific heat capacity of more than 50 J·K | 03-05-2009 |
| 257155000 |
With switching speed enhancement means (e.g., Schottky contact) | 2 |
| 20110147793 | SiGe HETEROJUNCTION BIPOLAR TRANSISTOR MULTI-FINGER STRUCTURE - The present invention provides a multi-finger structure of a SiGe heterojunction bipolar transistor (HBT). It is consisted of plural SiGe HBT single cells. The multi-finger structure is in a form of C/BEBC/BEBC/.../C, wherein, C, B, E respectively stands for collector, base and emitter; CBEBC stands for a SiGe HBT single cell. The collector region is consisted of an n type ion implanted layer inside the active region. The bottom of the implanted layer is connected to two n type pseudo buried layers. The two pseudo buried layers are formed through implantation to the bottom of the shallow trenches that surround the collector active region. Two collectors are picked up by deep trench contact through the field oxide above the two pseudo buried layers. The present invention can reduce junction capacitance, decrease collector electrode output resistance, and improve device frequency characteristics. | 06-23-2011 |
| 20130082302 | SEMICONDUCTOR DEVICE - A semiconductor device comprises: a substrate having a first and second surface; trenches provided on the second surface; a gate electrode provided in each trench; a first-conductive-type emitter layer provided on the second surface and contacting with the trenches; and an emitter electrode provided on the second surface to extend in a longitudinal direction of the trenches, the emitter electrode having a non-contact portion partially provided in the first-conductive-type emitter layer. | 04-04-2013 |
| 257163000 |
Emitter region feature | 2 |
| 20110127576 | Bipolar Power Semiconductor Component Comprising a P-type Emitter and More Highly Doped Zones in the P-type Emitter, and Production Method - A bipolar power semiconductor component configured as an IGBT includes a semiconductor body, in which a p-doped emitter, an n-doped base, a p-doped base and an n-doped main emitter are arranged successively in a vertical direction. The p-doped emitter has a number of heavily p-doped zones having a locally increased p-type doping. | 06-02-2011 |
| 20100052012 | SEMICONDUCTOR DEVICE - The first base electrodes and the first emitter electrodes are all formed like strips, and are alternately arranged in parallel, and the area of the second emitter electrode is expanded to be larger than that of the second base electrode. With this, the number of current paths increases in each of which a current is pulled up almost straight from the emitter region to the second emitter electrode through the first emitter electrodes, thereby preventing the current densities of the entire chip from becoming uneven. | 03-04-2010 |
| 257172000 |
With means to lower "ON" voltage drop | 1 |
| 20080230801 | TRENCH TYPE POWER SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A method for manufacturing a trench type power semiconductor device is provided. The method includes: forming a first silicon oxide film on a silicon substrate; forming a thermal oxidation-resistant film on the first silicon oxide film; forming an opening in the first silicon oxide film and the thermal oxidation-resistant film; forming a sidewall on an inner side surface of the opening; forming a trench in the silicon substrate by etching the silicon substrate using the first silicon oxide film, the thermal oxidation-resistant film, and the sidewall as a mask; removing the sidewall; forming a second silicon oxide film thicker than the first silicon oxide film on an inner surface of the trench by applying thermal oxidation to the silicon substrate; burying a trench gate electrode in the trench; removing the thermal oxidation-resistant film; and introducing impurities into at least part of a region of the silicon substrate between the trenches. | 09-25-2008 |
| 257177000 |
With housing or external electrode | 1 |
| 20090095979 | Power Module - A power module includes a substrate having first and second main substrate surfaces; a semiconductor device disposed on the first main substrate surface, and having a first main surface on which a first main electrode is formed, and a second main surface on which a second main electrode in contact with the first main substrate surface is formed; a heat conduction portion disposed on the first main substrate surface in a residual region of a region on which the semiconductor device is disposed; and an upper cooling portion disposed on the heat conduction portion. | 04-16-2009 |
| 257154000 |
With resistive region connecting separate sections of device | 1 |
| 20110204415 | HIGH HOLDING VOLTAGE DEVICE - A high holding voltage (HV) electrostatic discharge (ESD) protection circuit comprises a silicon controlled rectifier (SCR) device and compensation regions located within the length between the anode and cathode (LAC) of the SCR device which increase the holding voltage of the SCR device. The compensation regions may introduce negative feedback mechanisms into the SCR device which may influence the loop gain of the SCR and cause it to reach regenerative feedback at a higher holding voltage. | 08-25-2011 |
| 257108000 |
Controlled by nonelectrical, nonoptical external signal (e.g., magnetic field, pressure, thermal) | 1 |
| 20090114945 | SPINTRONICS COMPONENTS WITHOUT NON-MAGNETIC INTERPLAYERS - A spintronics element comprises two ferromagnetic layers without a non-magnetic interlayer between them. The two ferromagnetic layers may be independently switched by various means such as but not limited to applying one or more external magnetic fields, and/or employing current induced switching, and/or applying optical spin-pumping. | 05-07-2009 |
