Class / Patent application number | Description | Number of patent applications / Date published |
257104000 | TUNNELING PN JUNCTION (E.G., ESAKI DIODE) DEVICE | 46 |
20090039384 | POWER RECTIFIERS AND METHOD OF MAKING SAME - In one embodiment the present invention includes a semiconductor rectifier device comprising a first, second, and third semiconductor regions and a gate. The first semiconductor region is of a first conductivity type. The second semiconductor region is adjacent to the first semiconductor region which has a second conductivity type. The third semiconductor region is adjacent to the second semiconductor region which has the second conductivity type. The gate is proximate to but insulated from the second semiconductor region and electrically coupled to the third semiconductor region. When the first semiconductor region is biased in a first direction, an inversion region forms in the second semiconductor region. The inversion region forms a forward-biased tunnel diode junction with the third semiconductor region. When the first semiconductor region is biased a second direction, the semiconductor rectifier device functions as a reverse-biased PIN diode. | 02-12-2009 |
20090065801 | Surface plasmon polariton actuated transistors - A surface plasmon polaritron activated semiconductor device uses a surface plasmon wire that functions as an optical waveguide for fast communication of a signal and functions as a energy translator using a wire tip for translating the optical signal passing through the waveguide into plasmon-polaritron energy at a connection of the semiconductor device, such as a transistor, to activate the transistor for improved speed of communications and switching for preferred use in digital systems. | 03-12-2009 |
20090085058 | ELECTRONIC DEVICE INCLUDING A MAGNETO-RESISTIVE MEMORY DEVICE AND A PROCESS FOR FORMING THE ELECTRONIC DEVICE - A process of forming an electronic device can include forming a stack including a tunnel barrier layer. The tunnel barrier layer can have a ratio of the metal atoms to oxygen atoms of greater than a stoichiometric ratio, wherein the ratio has a particular value. The process can also include forming a gettering layer having a composition capable of gettering oxygen, and depositing an insulating layer over the gettering layer. The process can further include exposing the insulating layer to a temperature of at least approximately 60° C. In one embodiment, after such exposure, a portion of the gettering layer is converted to an insulating material. In another embodiment, an electronic device can include a magnetic tunnel junction and an adjacent insulating layer lying within an opening in another insulating layer. | 04-02-2009 |
20090200574 | POWER SEMICONDUCTOR DEVICE - A power semiconductor device includes a first layer of a first conductivity type, which has a first main side and a second main side opposite the first main side. A second layer of a second conductivity type is arranged in a central region of the first main side and a fourth electrically conductive layer is arranged on the second layer. On the second main side a third layer with a first zone of the first conductivity type with a higher doping than the first layer is arranged followed by a fifth electrically conductive layer. The area between the second layer and the first zone defines an active area. The third layer includes at least one second zone of the second conductivity type, which is arranged in the same plane as the first zone. A sixth layer of the first conductivity type with a doping, which is lower than that of the first zone and higher that that of the first layer, is arranged between the at least one second zone and the first layer. | 08-13-2009 |
20100200892 | TUNNEL DEVICE - This invention relates to a tunnel device which can generate tunneling effect with multi-band waveforms. The tunnel device can also be interacted with the field which includes thermal field, optical field, electric field, magnetic field, pressure field, acoustic field, or any combination of them. This tunnel device can be a power conversion device for driving high speed loading such as p-n junction device. | 08-12-2010 |
20110220959 | High-Frequency Bridge Suspended Diode - A high-frequency metal-insulator-metal (MIM) type diode is constructed as a bridge suspended above a substrate to significantly reduce parasitic capacitances affecting the operation frequency of the diode thereby permitting improved high-frequency rectification, demodulation, or the like. | 09-15-2011 |
20110298007 | SELECT DEVICES INCLUDING AN OPEN VOLUME, MEMORY DEVICES AND SYSTEMS INCLUDING SAME, AND METHODS FOR FORMING SAME - Select devices including an open volume that functions as a high bandgap material having a low dielectric constant are disclosed. The open volume may provide a more nonlinear, asymmetric I-V curve and enhanced rectifying behavior in the select devices. The select devices may comprise, for example, a metal-insulator-insulator-metal (MIIM) diode. Various methods may be used to form select devices and memory systems including such select devices. Memory devices and electronic systems include such select devices. | 12-08-2011 |
20130146940 | DESIGN STRUCTURE INCLUDING VOLTAGE CONTROLLED NEGATIVE RESISTANCE - Aspects of the invention provide a semiconductor tunneling device including voltage controlled negative resistance. In one embodiment, the semiconductor tunneling device includes: at least one pair of spaced apart terminals; an inter-level dielectric (ILD) layer between the at least one pair of spaced apart terminals; and a dielectric capping layer extending continuously over the at least one pair of spaced apart terminals and the ILD layer. | 06-13-2013 |
20130285110 | SELECT DEVICES INCLUDING AN OPEN VOLUME, AND RELATED METHODS, MEMORY DEVICES, AND ELECTRONIC SYSTEMS - Select devices including an open volume that functions as a high bandgap material having a low dielectric constant are disclosed. The open volume may provide a more nonlinear, asymmetric I-V curve and enhanced rectifying behavior in the select devices. The select devices may comprise, for example, a metal-insulator-insulator-metal (MIIM) diode. Various methods may be used to form select devices and memory systems including such select devices. Memory devices and electronic systems include such select devices. | 10-31-2013 |
20140167098 | Quantum Tunneling Devices and Circuits with Lattice-Mismatched Semiconductor Structures - Structures include a tunneling device disposed over first and second lattice-mismatched semiconductor materials. Process embodiments include forming tunneling devices over lattice-mismatched materials. | 06-19-2014 |
20140346558 | RECTIFYING DEVICE AND METHOD FOR MANUFACTURING THE SAME - Disclosed herein are a rectifying device and a method of fabricating the same. The rectifying device includes a first electrode formed in a flat shape, an insulating layer deposited on the first electrode and a second electrode formed on a preset region of the insulating layer in a nanaopillar shape in a longitudinal direction to be asymmetrical to the first electrode, thereby increasing current flow. | 11-27-2014 |
20160172352 | Power Semiconductor Device with Improved Stability and Method for Producing the Same | 06-16-2016 |
257105000 | In three or more terminal device | 22 |
20090026491 | TUNNELING EFFECT TRANSISTOR WITH SELF-ALIGNED GATE - In one embodiment, a mandrel and an outer dummy spacer may be employed to form a first conductivity type region. The mandrel is removed to form a recessed region wherein a second conductivity type region is formed. In another embodiment, a mandrel is removed from within shallow trench isolation to form a recessed region, in which an inner dummy spacer is formed. A first conductivity type region and a second conductivity region are formed within the remainder of the recessed region. An anneal is performed so that the first conductivity type region and the second conductivity type region abut each other by diffusion. A gate electrode is formed in self-alignment to the p-n junction between the first and second conductivity regions. The p-n junction controlled by the gate electrode, which may be sublithographic, constitutes an inventive tunneling effect transistor. | 01-29-2009 |
20100148213 | TUNNEL DEVICE - The present invention has provided a new diode and transistor by employing the characteristic of the tunnel diode. The new diode and transistor are field interacted and can be a solarcell, light sensor, thermal device, Hall device, pressure device or acoustic device which outputs self-excited multi-band waveforms with broad bandwidth. The present invention has also revealed a precisional switch which can works at high speeds and a capacitor whose capacitance can be actively controlled. | 06-17-2010 |
20110127572 | GATED RESONANT TUNNELING DIODE - A gated resonant tunneling diode (GRTD) that operates without cryogenic cooling is provided. This GRTD employs conventional CMOS process technology, preferably at the 65 nm node and smaller, which is different from other conventional quantum transistors that require other, completely different process technologies and operating conditions. To accomplish this, the GRTD uses a body of a first conduction type with a first electrode region and a second electrode region (each of a second conduction type) formed in the body. A channel is located between the first and second electrode regions in the body. A barrier region of the first conduction type is formed in the channel (with the doping level of the barrier region being greater than the doping level of the body), and a quantum well region of the second conduction type formed in the channel. Additionally, the barrier region is located between each of the first and second electrode regions and the quantum well region. An insulating layer is formed on the body with the insulating layer extending over the quantum well region and at least a portion of the barrier region, and a control electrode region is formed on the insulating layer. | 06-02-2011 |
20120032227 | LOW VOLTAGE TUNNEL FIELD-EFFECT TRANSISTOR (TFET) AND METHOD OF MAKING SAME - A low voltage tunnel field effect transistor includes a p-n tunnel junction, a gate-dielectric, a gate, a source-contact, and a drain-contact. The p-n tunnel junction includes a depletion region interfacing together a source-layer and a drain-layer. The depletion region includes a source-tunneling-region of the source-layer and a drain-tunneling-region of the drain-layer. When no external electric field is imposed, the depletion region of the p-n tunnel junction has an internal electric field that substantially points towards the source-tunneling-region and the drain-tunneling-region. The gate-dielectric is interfaced directly onto the drain-tunneling-region such that the drain-tunneling-region is between the source-tunneling-region and the gate-dielectric. The gate is interfaced onto the gate-dielectric such that the gate is configured to impose an external electric field which is oriented substantially in parallel to the internal electric field of the depletion region. | 02-09-2012 |
20120223361 | LOW-POWER CONSUMPTION TUNNELING FIELD-EFFECT TRANSISTOR WITH FINGER-SHAPED GATE STRUCTURE - The present invention discloses a low-power consumption tunnelling field-effect transistor (TFET). The TFET according to the invention includes a source, a drain and a control gate, wherein the control gate extends towards the source to form a finger-type control gate, which includes an extended gate region and an original control gate region, and an active region covered by the extended gate region is also an channel region and is made of the substrate material. The invention employs a finger-shaped gate structure, and the source region of the TFET surrounds the channel so that the on-state current of the device is improved. In comparison with the conventional planar TFET, a higher on-state current and a steeper subthreshold slope may be obtained under the same process conditions and with the same active region size. | 09-06-2012 |
20140124827 | Integrated Circuit Arrangement Comprising a Field Effect Transistor, Especially a Tunnel Field Effect Transistor - Integrated circuit arrangement comprising a field effect transistor, especially a tunnel field effect transistor. An explanation is given of, inter alia, tunnel field effect transistors having a thicker gate dielectric in comparison with other transistors on the same integrated circuit arrangement. As an alternative or in addition, said tunnel field effect transistors have gate regions at mutually remote sides of a channel forming region or an interface between the connection regions of the tunnel field effect transistor. | 05-08-2014 |
20140203324 | A STRIP-SHAPED GATE-MODULATED TUNNELING FIELD EFFECT TRANSISTOR AND A PREPARATION METHOD THEREOF - The present invention discloses a strip-shaped gate-modulated tunneling field effect transistor and a preparation method thereof, belonging to a field of field effect transistor logic device and the circuit in CMOS ultra large scale integrated circuit (ULSI). The tunneling field effect transistor includes a control gate, a gate dielectric layer, a semiconductor substrate, a highly-doped source region and a highly-doped drain region, where the highly-doped source region and the highly-doped drain region lie on both sides of the control gate, respectively, the control gate has a strip-shaped structure with a gate length greater than a gate width, and at one side thereof is connected to the highly-doped drain region and at the other side thereof extends laterally into the highly-doped source region; a region located below the control gate is a channel region; and the gate width of the control gate is less than twice width of a source depletion layer. The device modulates the source-side tunneling junction by using the strip-shaped gate structure, achieves the effect equivalent to that the source junction has a steep doping concentration gradient, and improves the TFET device performance; and the preparation method thereof is simple. | 07-24-2014 |
20140252407 | TUNNEL EFFECT TRANSISTOR - A tunnel effect transistor includes a channel made of an intrinsic semiconductor material; source and drain extension regions on either side of the channel, the source extension region being made of a semiconductor material doped according to a first type of doping P or N and the drain extension region being made of a semiconductor material doped according to a second type of doping opposite to said first type of doping; source and drain conductive regions respectively in contact with the source and drain extension regions; a gate structure including a gate dielectric layer in contact with the channel and a gate area arranged such that the gate dielectric layer is arranged between the gate area and the channel; and an area doped according to the first type of doping inserted between the channel and the drain extension region. | 09-11-2014 |
20150021654 | TUNNELING TRANSISTOR WITH ASYMMETRIC GATE - An asymmetric gate tunneling transistor includes a substrate, a first-polarity portion, a second-polarity portion, a channel portion, a gate structure and an insulation body. The first-polarity portion and the second-polarity portion are disposed on the substrate. The channel portion is connected with the first-polarity portion and the second-polarity portion, and includes a first section and a second section. The gate structure includes an enveloping portion surrounding the first section, and a flat portion covering one side of the second section away from the substrate. The insulation body includes a first insulation portion disposed between the first section and the enveloping portion, and a second insulation portion disposed between the second section and the flat portion. Through the asymmetric design of the gate structure, the tunneling transistor is offered with features of a high ON current and a low OFF current. | 01-22-2015 |
20150041847 | TUNNELING FIELD EFFECT TRANSISTORS (TFETS) FOR CMOS ARCHITECTURES AND APPROACHES TO FABRICATING N-TYPE AND P-TYPE TFETS - Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and P-type TFETs are described. For example, a tunneling field effect transistor (TFET) includes a homojunction active region disposed above a substrate. The homojunction active region includes a relaxed Ge or GeSn body having an undoped channel region therein. The homojunction active region also includes doped source and drain regions disposed in the relaxed Ge or GeSn body, on either side of the channel region. The TFET also includes a gate stack disposed on the channel region, between the source and drain regions. The gate stack includes a gate dielectric portion and gate electrode portion. | 02-12-2015 |
20150069458 | VERTICAL TUNNEL FIELD EFFECT TRANSISTOR - A tunnel field transistor (TFET) device includes a fin structure that protrudes from a substrate surface. The fin structure includes a base portion proximate to the substrate surface, a top portion, and a first pair of sidewalls extending from the base portion to the top portion. The first pair of sidewalls has a length corresponding to a length of the fin structure. The fin structure also includes a first doped region having a first dopant concentration at the base portion of the fin structure. The fin structure also includes a second doped region having a second dopant concentration at the top portion of the fin structure. The TFET device further includes a gate including a first conductive structure neighboring a first sidewall of the first pair of sidewalls. A dielectric layer electrically isolates the first conductive structure from the first sidewall. | 03-12-2015 |
20150076553 | SEMICONDUCTOR DEVICE - A semiconductor device according to the present embodiment includes a semiconductor layer. A gate dielectric film is provided on a surface of the semiconductor layer. A gate electrode is provided on the semiconductor layer via the gate dielectric film. A drain layer of a first conductivity type is provided in a part of the semiconductor layer on a side of a first end of the gate electrode. A source layer of a second conductivity type is provided in a part of the semiconductor layer on a side of a second end of the gate electrode and below the gate electrode. The source layer has a substantially uniform impurity concentration at the part of the semiconductor layer below the gate electrode. Voltages of a same polarity are applied to the gate electrode and the drain layer. | 03-19-2015 |
20150084091 | TUNNEL FIELD-EFFECT TRANSISTORS WITH A GATE-SWING BROKEN-GAP HETEROSTRUCTURE - Device structures, fabrication methods, and design structures for tunnel field-effect transistors. A drain comprised of a first semiconductor material having a first band gap and a source comprised of a second semiconductor material having a second band gap are formed. A tunnel barrier is formed between the source and the drain. The second semiconductor material exhibits a broken-gap energy band alignment with the first semiconductor material. The tunnel barrier is comprised of a third semiconductor material with a third band gap larger than the first band gap and larger than the second band gap. The third band gap is configured to bend under an external bias to assist in aligning a first energy band of the first semiconductor material with a second energy band of the second semiconductor material | 03-26-2015 |
20150129925 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor layer opposing to a bottom surface and a side surface of a gate electrode. An insulation film is provided between the bottom surface of the gate electrode and the semiconductor layer and between the side surface of the gate electrode and the semiconductor layer. A first conduction-type drain layer is provided in the semiconductor layer on a side of an end part of one of the bottom surface and the side surface of the gate electrode. A second conduction-type source layer is provided in the semiconductor layer opposing to the other one of the bottom surface and the side surface of the gate electrode. A second conduction-type extension layer is provided in the semiconductor layer opposing to a corner part between the side surface and the bottom surface of the gate electrode and has a lower impurity concentration than that of the source layer. | 05-14-2015 |
20150129926 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A field effect transistor is provided. The field effect transistor includes a semiconductor region formed on a substrate, wherein the semiconductor region comprises an undoped channel region, a source region including a first dopant type, and a drain region including a second dopant type, and wherein the channel region is formed of a group III-V compound semiconductor material. The field effect transistor further includes a high-K gate formed on the channel region, wherein the high-K gate is configured to generate electron tunneling between the source region and the drain region when a gate voltage is applied, and wherein a first contact surface between the source region and the channel region and a second contact surface between the drain region and the channel region are inclined. | 05-14-2015 |
20150340489 | FIN TUNNELING FIELD EFFECT TRANSISTOR AND MANUFACTURING METHOD THEREOF - A fin tunneling field effect transistor (TFET) is disclosed. The fin TFET includes a semiconductor body extending in a first direction on a substrate, wherein the semiconductor body constitutes a channel of the fin TFET. The fin TFET also includes a source and a drain disposed at opposite ends of the semiconductor body, wherein the source is doped with a first dopant type and the drain is doped with a second dopant type, and the first dopant type is different from the second dopant type. The fin TFET further includes a gate disposed on at least two sides of the channel, wherein a portion of the source is disposed in contact with a portion of the channel. | 11-26-2015 |
20160020306 | Short-Gate Tunneling Field Effect Transistor Having Non-Uniformly Doped Vertical Channel and Fabrication Method Thereof - The present invention discloses a short-gate tunneling field effect transistor having a non-uniformly doped vertical channel and a fabrication method thereof. The short-gate tunneling field effect transistor has a vertical channel and the channel region is doped in such a slowly-varied and non-uniform manner that a doping concentration in the channel region appears a Gaussian distribution along a vertical direction and the doping concentration in the channel near the drain region is higher while the doping concentration in the channel near the source region is lower; and double control gates are formed at both sides of the vertical channel and the control gates form an L-shaped short-gate structure, so that a gate underlapped region is formed in the channel near the drain region, and a gate overlapped region is formed at the source region. As compared with a conventional TFET, the short-gate tunneling field effect transistor according to the present invention can effectively suppress the impact of the electrical field at the drain region on the tunneling width of the tunneling junction at the source region; the super exponential relationship between the output tunneling current and the drain voltage is weakened; and the output characteristic of the transistor is significantly improved. Meanwhile, the tunneling field effect transistor is beneficial to increase the on-current of the transistor and to gain a steeper sub-threshold slope. | 01-21-2016 |
20160043175 | TUNNEL TRANSISTORS WITH ABRUPT JUNCTIONS - A tunnel field effect transistor (TFET) including a first doped source region for a first type TFET or a second doped source region for a second type TFET; a second doped drain region for the first type TFET or a first doped drain region for the second type TFET; a body region that is either intrinsic or doped, with a doping concentration less than that of the first or second source region, separating the first or second source from the first or second drain regions; a self-aligned etch cavity separating the first or second doped source and drain regions; a thin epitaxial channel region that is grown within the self-aligned etch cavity, covering at least the first or the second source region; a replacement gate stack comprising a high-k gate dielectric and one or a combination of metals and polysilicon; and sidewall spacers adjacent to the replacement gate stack. | 02-11-2016 |
20160071882 | Semiconductor Device, Method for Manufacturing Same, and Nonvolatile Semiconductor Memory Device - Provided is a semiconductor element having, while maintaining the same integratability as a conventional MOSFET, excellent switch characteristics compared with the MOSFET, that is, having the S-value less than 60 mV/order at room temperature. Combining the MOSFET and a tunnel bipolar transistor having a tunnel junction configures a semiconductor element that shows an abrupt change in the drain current with respect to a change in the gate voltage (an S-value of less than 60 mV/order) even at a low voltage. | 03-10-2016 |
20160079400 | A JUNCTION-MODULATED TUNNELING FIELD EFFECT TRANSISTOR AND A FABRICATION METHOD THEREOF - The present invention discloses a junction-modulated tunneling field effect transistor and a fabrication method thereof, belonging to a field of field effect transistor logic device and the circuit in connection with CMOS ultra large scale integrated circuit (ULSI). The PN junction provided by a highly-doped source region surrounding three sides of the vertical channel region of the tunneling field effect transistor can deplete effectively the channel region, so that the energy band of the surface channel under the gate is lifted, therefore the device may obtain a steeper energy band and a narrower tunneling barrier width than the conventional TFET when the band-to-band tunneling occurs, equivalently achieving the effect of a steep doping concentration gradient at the source tunneling junction, and thereby the sub-threshold characteristics are significantly improved while the turn-on current of the device is improved relative to the conventional TFET. Under the conditions that the device of the present invention is compatible with the existing CMOS process, on the one hand an ambipolar effect of the device can be inhibited effectively, while a parasitic tunneling current at a source junction corner in the small size device can be inhibited and thus can equivalently achieve an effect of a steep doping concentration gradient at the source junction. | 03-17-2016 |
20160141398 | TUNNEL FIELD-EFFECT TRANSISTOR (TFET) WITH SUPERSTEEP SUB-THRESHOLD SWING - Technologies are generally described herein generally relate to tunnel field-effect transistor (TFETs) structures with a gate-on-germanium source (GoGeS) on bulk silicon substrate for sub 0.5V (V | 05-19-2016 |
20160163840 | TUNNEL FIELD EFFECT TRANSISTOR (TFET) WITH LATERAL OXIDATION - A vertical-mode tunnel field-effect transistor (TFET) is provided with an oxide region that may be laterally positioned relative to a source region. The oxide region operates to reduce a tunneling effect in a tunnel region underlying a drain region, during an OFF-state of the TFET. The reduction in tunneling effect results in a reduction or elimination of a flow of OFF-state leakage current between the source region and the drain region. The TFET may have components made from group III-V compound materials. | 06-09-2016 |
257106000 | Reverse bias tunneling structure (e.g., "backward" diode, true Zener diode) | 12 |
20090250720 | TRANSIENT VOLTAGE SUPPRESSOR AND METHODS - Transient voltage suppressor and method for manufacturing the transient voltage suppressor having a dopant or carrier concentration in a portion of a gate region near a Zener region that is different from a dopant concentration in a portion of a gate region that is away from the Zener region. | 10-08-2009 |
20100006889 | LOW CLAMP VOLTAGE ESD DEVICE AND METHOD THEREFOR - In one embodiment, an ESD device is configured to include a zener diode and a P-N diode and to have a conductor that provides a current path between the zener diode and the P-N diode. | 01-14-2010 |
20100019274 | Semiconductor device - A semiconductor device includes an insulating film formed over a semiconductor substrate, a Zener diode formed above the insulating film, an interlayer film formed above the Zener diode, and a gate aluminum and a source aluminum formed above the interlayer film. The Zener diode is connected between the gate aluminum and the source aluminum. The Zener diode is formed by alternately joining an N type region and a P type region concentrically. The gate electrode includes a gate pad section. A planar shape of the Zener diode is substantially similar to a planer shape of the gate pad section. The gate pad section extends for a predetermined distance from an outermost edge of the P type region of the Zener diode to outside. | 01-28-2010 |
20100244088 | ZENER TRIGGERED ESD PROTECTION - Electrostatic discharge (ESD) protection clamps ( | 09-30-2010 |
20110186906 | METHODS AND APPARATUS FOR ANTIMONIDE-BASED BACKWARD DIODE MILLIMETER-WAVE DETECTORS - Example methods and apparatus for Antimonide-based backward diode millimeter-wave detectors are disclosed. A disclosed example backward diode includes a cathode layer adjacent to a first side of a non-uniform doping profile, and an Antimonide tunnel barrier layer adjacent to a second side of the spacer layer. | 08-04-2011 |
20110266591 | BI-DIRECTIONAL DIODE STRUCTURE - In one embodiment, a bi-directional diode structure is formed to have a substantially symmetrical current-voltage characteristic. | 11-03-2011 |
20120326206 | DEVICES WITH ZENER TRIGGERED ESD PROTECTION - Electrostatic discharge (ESD) protection clamps for I/O terminals of integrated circuit (IC) cores comprise a bipolar transistor with an integrated Zener diode coupled between the base and collector of the transistor. Variations in clamp voltage in different parts of the same IC chip or wafer caused by conventional deep implant geometric mask shadowing are avoided by using shallow implants and forming the base coupled anode and collector coupled cathode of the Zener using opposed edges of a single relatively thin mask. The anode and cathode are self-aligned, and the width of the Zener space charge region between them is defined by the opposed edges substantially independent of location and orientation of the ESD clamps on the die or wafer. Because the mask is relatively thin and the anode and cathode implants relatively shallow, mask shadowing is negligible and prior art clamp voltage variations are avoided. | 12-27-2012 |
20130134476 | SOLID-STATE DIODE - The solid-state diode comprises a semiconductor substrate having a top side and having two masking regions formed on the top side of the semiconductor substrate and made of a first masking material impermeable to ion implantation, the masking regions comprising two mutually opposite limiting edge portions. The solid-state diode comprises an n-doped cathode region formed in the semiconductor substrate and extending up into the intermediate region between the mutually opposite limiting edge portions of the masking regions, the n-doped cathode region comprising a cathode connection field. The diode comprises a p-doped anode region formed in the semiconductor substrate, extending up into the intermediate region between the mutually opposite limiting edge portions of the masking regions and bordering/overlapping on the cathode region, the p-doped anode region comprising an anode connection field. The masking regions and either the cathode or the anode connection field are substantially on the same electric potential. | 05-30-2013 |
20130234198 | Electrical Circuit Protection Design with Dielectrically-Isolated Diode Configuration and Architecture - A novel electrical circuit protection design with dielectrically-isolated diode configuration and architecture is disclosed. In one embodiment of the invention, a plurality of diodes connected in series is monolithically integrated in a single piece of semiconductor substrates by utilizing dielectrically-isolated trenching and silicon-on-insulator substrates, which enable formation of “silicon islands” to insulate a diode structure electrically from adjacent structures. In one embodiment of the invention, the plurality of diodes connected in series includes at least one Zener diode, which provides a clamping voltage approximately equal to its breakdown voltage value in case of a voltage spike or a power surge event. In another embodiment of the invention, the plurality of diodes connected in series includes a scalable number of monolithically-integrated forward-bias PN diodes, wherein the summation of the forward-bias voltage of each PN diode is equivalent to a net clamping voltage value for an electrical circuit protection design. | 09-12-2013 |
20140061715 | ZENER DIODE DEVICE AND FABRICATION - A disclosed Zener diode includes, in one embodiment, an anode region and a cathode region that form a shallow sub-surface latitudinal Zener junction. The Zener diode may further include an anode contact region interconnecting the anode region with a contact located away from the Zener junction region and a silicide blocking structure overlying the anode region. The Zener diode may also include one or more shallow, sub-surface longitudinal p-n junctions at the junctions between lateral edges of the cathode region and the adjacent region. The adjacent region may be a heavily doped region such as the anode contact region. In other embodiments, the Zener diode may include a breakdown voltage boost region comprising a more lightly doped region located between the cathode region and the anode contact region. | 03-06-2014 |
20150364460 | TRANSIENT VOLTAGE SUPPRESSION DEVICE AND MANUFACTURING METHOD THEREOF - The present invention discloses a transient voltage suppression (TVS) device and a manufacturing method thereof. The TVS device limits a voltage drop between two terminals thereof not to exceed a clamp voltage. The TVS device is formed in a stack substrate including a semiconductor substrate, a P-type first epitaxial layer, and a second epitaxial layer stacked in sequence. In the TVS device, a first PN diode is connected to a Zener diode in series, wherein the series circuit is surrounded by a first shallow trench isolation (STI) region; and a second PN diode is connected in parallel to the series circuit, wherein the second PN diode is surrounded by a second STI region. The first STI region and the second STI region both extend from an upper surface to the second epitaxial layer, but not to the first epitaxial layer. | 12-17-2015 |
20160141429 | ELECTROSTATIC DISCHARGE DEVICE AND METHOD OF FABRICATING THE SAME - Provided are an electrostatic discharge (ESD) device and method of fabricating the same where the ESD device is configured to prevent electrostatic discharge which can be a cause to product failure. More particularly, the ESD device provided includes a Zener diode and a plurality of PN diodes by improving the architecture of an area wherein a Zener diode is configured compared to alternatives, to provide improved functionality when protecting against ESD events. | 05-19-2016 |