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Diamond or silicon carbide

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257 - Active solid-state devices (e.g., transistors, solid-state diodes)

257076000 - SPECIFIED WIDE BAND GAP (1.5EV) SEMICONDUCTOR MATERIAL OTHER THAN GAASP OR GAALAS

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DocumentTitleDate
20110175107SILICON CARBIDE SUBSTRATE - A base portion is made of silicon carbide and has a main surface. At least one silicon carbide layer is provided on the main surface of the base portion in a manner exposing a region of the main surface along an outer edge of the main surface. At least one protection layer is provided on this region of the main surface of the base portion along the outer edge of the main surface. Thus, a silicon carbide substrate can be polished with high in-plane uniformity.07-21-2011
20110198614METHOD AND APPARATUS FOR MANUFACTURING A SiC SINGLE CRYSTAL FILM - A manufacturing method for a SiC single crystal film which allows stable growth of a SiC epitaxial film with a low doping concentration on a substrate with a diameter of at least 2 inches by the LPE method using a SiC solution in solvent of a melt includes an evacuation step in which the interior of a crystal growth furnace is evacuated with heating until the vacuum pressure at the crystal growth temperature is 5×1008-18-2011
20110198612SIC SEMICONDUCTOR DEVICE HAVING CJFET AND METHOD FOR MANUFACTURING THE SAME - A SiC semiconductor device includes: a SiC substrate made of intrinsic SiC having semi-insulating property; first and second conductive type SiC layers disposed in the substrate; an insulation separation layer made of intrinsic SiC for isolating the first conductive type SiC layer from the second conductive type SiC layer; first and second conductive type channel JFETs disposed in the first and second conductive type SiC layers, respectively. The first and second conductive type channel JFETs provide a complementary junction field effect transistor. Since an electric element is formed on a flat surface, a manufacturing method is simplified. Further, noise propagation at high frequency and current leakage at high temperature are restricted.08-18-2011
20120199848SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A buffer layer is provided on a substrate, is made of silicon carbide containing an impurity, and has a thickness larger than 1 μm and smaller than 7 μm. A drift layer is provided on the buffer layer and is made of silicon carbide having an impurity concentration smaller than that of the buffer layer. In this way, there can be provided a silicon carbide semiconductor device having the drift layer having a desired impurity concentration and a high crystallinity.08-09-2012
20130043490SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE DEVICE - The semiconductor device 02-21-2013
20130043491Schottky Diodes Including Polysilicon Having Low Barrier Heights - Hybrid semiconductor devices including a PIN diode portion and a Schottky diode portion are provided. The PIN diode portion is provided on a semiconductor substrate and has an anode contact on a first surface of the semiconductor substrate. The Schottky diode portion is also provided on the semiconductor substrate and includes a polysilicon layer on the semiconductor substrate and a ohmic contact on the polysilicon layer. Related Schottky diodes are also provided herein.02-21-2013
20130043489COMPOUND SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A compound semiconductor device includes: a substrate; a GaN compound semiconductor multilayer structure disposed over the substrate; and a stress relief layer which is AlN-based and which is disposed between the substrate and the GaN compound semiconductor multilayer structure, wherein a surface of the stress relief layer that is in contact with the GaN compound semiconductor multilayer structure includes recesses that have a depth of 5 nm or more and that are formed at a number density of 2×1002-21-2013
20130043492NITRIDE SEMICONDUCTOR TRANSISTOR - A nitride semiconductor transistor includes a heterojunction layer including a plurality of nitride semiconductor layers having different polarizations, and a gate electrode disposed on the heterojunction layer. An electron current reduction layer having a p-type conductivity is disposed between the heterojunction layer and the gate electrode to pass hole current therethrough and reduce electron current.02-21-2013
20120161154SILICON CARBIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - An SiC semiconductor device includes a substrate, a drift layer, a base region, a source region, a trench, a gate oxide film, a gate electrode, a source electrode and a drain electrode. The substrate has a Si-face as a main surface. The source region has the Si-face. The trench is provided from a surface of the source region to a portion deeper than the base region and extends longitudinally in one direction and has a Si-face bottom. The trench has an inverse tapered shape, which has a smaller width at an entrance portion than at a bottom, at least at a portion that is in contact with the base region.06-28-2012
20090194773GALLIUM NITRIDE MATERIAL DEVICES INCLUDING DIAMOND REGIONS AND METHODS ASSOCIATED WITH THE SAME - Gallium nitride material structures are provided, as well as devices and methods associated with such structures. The structures include a diamond region which may facilitate conduction and removal of heat generated within the gallium nitride material during device operation. The structures described herein may form the basis of a number of semiconductor devices and, in particular, transistors (e.g., FETs).08-06-2009
20090194772Method For Fabricating Silicon Carbide Vertical MOSFET Devices - A method of forming a vertical MOSFET device includes forming a first trench within a semiconductor layer of a first polarity, the first trench generally defining a well region of a second polarity opposite the first polarity; growing a first epitaxial well layer of the second polarity over the original semiconductor layer; growing a second epitaxial source contact layer of the first polarity over the well layer; forming a second trench through the source contact layer and at least a portion of the well layer; growing a third epitaxial layer of the second polarity over the source contact layer; and planarizing at least the first and second epitaxial layers so as to expose an upper surface of the original semiconductor layer, wherein a top surface of the third epitaxial layer is substantially coplanar with a top surface of the source contact layer prior to ohmic contact formation.08-06-2009
20110284873SILICON CARBIDE SUBSTRATE - A silicon carbide substrate has a substrate region and a support portion. The substrate region has a first single crystal substrate. The support portion is joined to a first backside surface of the first single crystal. The dislocation density of the first single crystal substrate is lower than the dislocation density of the support portion. At least one of the substrate region and the support portion has voids.11-24-2011
20130134443NITRIDE SEMICONDUCTOR DIODE - Disclosed is a high performance nitride semiconductor having a reverse leak current characteristic with two-dimensional electron gas as a conductive layer. A desired impurity is diffused into or a nitride semiconductor to which a desired impurity is added is re-grown on the bottom surface and the side face portion of a recessed portion formed by dry etching using chlorine gas on the upper surface of a nitride semiconductor stacked film to increase resistance of the side face portion of the nitride semiconductor stacked film contacting an anode electrode, reducing the reverse leak current.05-30-2013
20080258152SiC semiconductor device having outer periphery structure - A SiC semiconductor device includes: a SiC substrate; a SiC drift layer on the substrate having an impurity concentration lower than the substrate; a semiconductor element in a cell region of the drift layer; an outer periphery structure including a RESURF layer in a surface portion of the drift layer and surrounding the cell region; and an electric field relaxation layer in another surface portion of the drift layer so that the electric field relaxation layer is separated from the RESURF layer. The electric field relaxation layer is disposed on an inside of the RESURF layer so that the electric field relaxation layer is disposed in the cell region. The electric field relaxation layer has a ring shape.10-23-2008
20110193101SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a SiC layer of a first conductivity type, a SiC region of a second conductivity type, and a conductive layer of the second conductivity type. The SiC layer of the first conductivity type has a hexagonal crystal structure. The SiC region of the second conductivity type is formed in a surface of the SiC layer. The conductive layer of the second conductivity type is provided on the SiC region and is in contact with a portion of the SiC region including SiC of a cubic crystal structure.08-11-2011
20110193100SIC SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing an SiC semiconductor device according to the present invention includes the steps of (a) by using a single mask, etching regions of an SiC semiconductor layer which serve as an impurities implantation region and a mark region, to form recesses, (b) by using the same mask as in the step (a), performing ion-implantation in the recesses of the regions which serve as the impurities implantation region and the mark region, at least from an oblique direction relative to a surface of the SiC semiconductor layer and (c) positioning another mask based on the recess of the region which serves as the impurities implantation region or the mark region, and performing well implantation in a region containing the impurities implantation region.08-11-2011
20110193099SEMICONDUCTOR DEVICE - A semiconductor device according to the present invention includes: a low dielectric constant oxide film as an inorganic oxide film formed selectively on an n-type semiconductor substrate as a semiconductor substrate of a fist conductivity type; and anode electrodes as electrode layers formed on the n-type semiconductor substrate so as to sandwich the low dielectric constant oxide film therebetween, wherein the low dielectric constant oxide film is doped with an element for reducing a dielectric constant.08-11-2011
20110193098High voltage high package pressure semiconductor package - A hermetically sealed integrated circuit package that includes a cavity housing a semiconductor die, whereby the cavity is pressurized during assembly and when formed. The invention prevents the stress on a package created when the package is subject to high temperatures at atmospheric pressure and then cooled from reducing the performance of the die at high voltages. By packaging a die at a high pressure, such as up to 50 PSIG, in an atmosphere with an inert gas, and providing a large pressure in the completed package, the dies are significantly less likely to arc at higher voltages, allowing the realization of single die packages operable up to at least 1200 volts. Moreover, the present invention is configured to employ brazed elements compatible with Silicon Carbide dies which can be processed at higher temperatures.08-11-2011
20110193097Silicon carbide semiconductor - A hermetically sealed integrated circuit package that includes a cavity housing a semiconductor die, whereby the cavity is pressurized during assembly and when formed. The invention prevents the stress on a package created when the package is subject to high temperatures at atmospheric pressure and then cooled from reducing the performance of the die at high voltages. By packaging a die at a high pressure, such as up to 50 PSIG, in an atmosphere with an inert gas, and providing a large pressure in the completed package, the dies are significantly less likely to arc at higher voltages, allowing the realization of single die packages operable up to at least 1200 volts. Moreover, the present invention is configured to employ brazed elements compatible with Silicon Carbide dies which can be processed at higher temperatures.08-11-2011
20130082284ELECTRONIC CIRCUIT - An electronic circuit includes a bipolar device, a unipolar device connected in parallel to the bipolar device, and an output line connected to the bipolar device and to the unipolar device. An inductance between the unipolar device and the output line is smaller than an inductance between the bipolar device and the output line.04-04-2013
20130037824POWER SEMICONDUCTOR DEVICE - Cell electrodes are provided respectively for cell structures on a semiconductor substrate. The cell electrodes are divided into groups each including two or more cell electrodes. Conductive members are respectively electrically connected to the groups. The conductive members have a used portion and an unused portion. The used portion has two or more conductive members electrically connected to each other. The unused portion has at least one of the conductive members and is electrically insulated from the used portion.02-14-2013
20130037822Semiconductor Device and Manufacturing Method Thereof - A semiconductor device and its manufacturing method are provided. The semiconductor device comprises: a semiconductor substrate of a first semiconductor material, a gate structure on the semiconductor substrate, a crystal lattice dislocation line in a channel under the gate structure for generating channel stress, wherein the crystal lattice dislocation line being at an angle to the channel.02-14-2013
20130037821Semiconductor Device and Manufacturing Method thereof - The present invention provides a semiconductor device, comprising: a substrate; shallow trench isolations embedded into the substrate and forming at least one opening area; a channel region located in the opening area; a gate stack comprising a gate dielectric layer and a gate electrode layer and located above the channel region; source/drain regions located at both sides of the channel region and comprising a stress layer that provides a strain to the channel region; wherein, there is a liner layer between the shallow trench isolation and the stress layer, which serves as the seed layer of the stress layer. A liner layer that is of the same or similar material as the stress layer in the source/drain region is inserted between the STI and the stress layer of the source/drain region as a seed layer or nucleation layer for the epitaxial growth, thereby eliminating the STI edge effect during the source/drain strain engineering, i.e. eliminating the gap between the STI and the stress layer of the source/drain region, as a result, the reduction of the channel stress produced by the source/drain strain is prevented, the carrier mobility of the MOS device is increased and the driving capability of the device is enhanced.02-14-2013
20130037823SEMICONDUCTOR DEVICE - In one embodiment, a semiconductor device includes a semiconductor substrate, a gate electrode provided on the semiconductor substrate via an insulating layer, and a gate insulator provided on a side surface of the gate electrode. The device includes a stacked layer including a lower main terminal layer of a first conductivity type, an intermediate layer, and an upper main terminal layer of a second conductivity type which are successively stacked on the semiconductor substrate, the stacked layer being provided on the side surface of the gate electrode via the gate insulator. The upper or lower main terminal layer is provided on the side surface of the gate electrode via the gate insulator and the semiconductor layer.02-14-2013
20120175639TANTALUM CARBIDE, METHOD FOR PRODUCING TANTALUM CARBIDE, TANTALUM CARBIDE WIRING AND TANTALUM CARBIDE ELECTRODE - It is an object of the present invention to provide a method for manufacturing tantalum carbide which can form tantalum carbide having a prescribed shape using a simple method, can form the tantalum carbide having a uniform thickness even when the tantalum carbide is coated on the surface of an article and is not peeled off by a thermal history, tantalum carbide obtained by the manufacturing method, wiring of tantalum carbide, and electrodes of tantalum carbide.07-12-2012
20100117097SILICON CARBIDE SEMICONDUCTOR DEVICE - The present invention relates to a semiconductor device (05-13-2010
20100117098SCHOTTKY ELECTRODE FOR DIAMOND SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - To provide a Schottky electrode in a diamond semiconductor, which has a good adhesion properties to diamonds, has a contacting surface which does not become peeled due to an irregularity in an external mechanical pressure, does not cause a reduction in yield in a diode forming process and does not cause deterioration in current-voltage characteristics, and a method of manufacturing the Schottky electrode.05-13-2010
20100072485SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MANUFACTURING METHOD - One atomic layer of Si atoms 3 is grown on an Si-terminated SiC surface 103-25-2010
20100072484HETEROEPITAXIAL GALLIUM NITRIDE-BASED DEVICE FORMED ON AN OFF-CUT SUBSTRATE - Embodiments include but are not limited to apparatuses and systems including a heteroepitaxial gallium nitride-based device formed on an off-cut substrate, and methods for making the same. Other embodiments may be described and claimed.03-25-2010
20130032824SILICON CARBIDE SEMICONDUCTOR DEVICE - First, second, fourth, and fifth impurity regions have a first conductivity type, and a third impurity region has a second conductivity type. The first to third impurity regions reach a first layer having the first conductivity type. The fourth and fifth impurity regions are provided on a second layer. First to fifth electrodes are provided on the first to fifth impurity regions, respectively. Electrical connection is established between the first and fifth electrodes, and between the third and fourth electrodes. A sixth electrode is provided on a gate insulating film covering a portion between the fourth and fifth impurity regions.02-07-2013
20130032823SILICON CARBIDE SEMICONDUCTOR DEVICE - A first layer has a first conductivity type. A second layer is provided on the first layer such that a part of the first layer is exposed, and it has a second conductivity type. First to third impurity regions penetrate the second layer and reach the first layer. Each of the first and second impurity regions has the first conductivity type.02-07-2013
20130032822SUBSTRATE, SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING THE SAME - A substrate capable of achieving a lowered probability of defects produced in a step of forming an epitaxial film or a semiconductor element, a semiconductor device including the substrate, and a method of manufacturing a semiconductor device are provided. A substrate is a substrate having a front surface and a back surface, in which at least a part of the front surface is composed of single crystal silicon carbide, the substrate having an average value of surface roughness Ra at the front surface not greater than 0.5 nm, a standard deviation σ of that surface roughness Ra not greater than 0.2 nm, an average value of surface roughness Ra at the back surface not smaller than 0.3 nm and not greater than 10 nm, standard deviation σ of that surface roughness Ra not greater than 3 nm, and a diameter D of the front surface not smaller than 110 mm.02-07-2013
20130032821SCHOTTKY BARRIER DIODE AND METHOD FOR MANUFACTURING THE SAME - A Schottky barrier diode (SBD) is provided, which improves electrical characteristics and optical characteristics by securing high crystallinity by including an n-gallium nitride (GaN) layer and a GaN layer which are doped with aluminum (Al). In addition, by providing a p-GaN layer on the Al-doped GaN layer, a depletion layer may be formed when a reverse current is applied, thereby reducing a leakage current. The SBD may be manufactured by etching a part of the Al-doped GaN layer and growing a p-GaN layer from the etched part of the Al-doped GaN layer. Therefore, a thin film crystal is not damaged, thereby increasing reliability. Also, since dedicated processes for ion implantation and thermal processing are not necessary, simplified process and reduced cost may be achieved.02-07-2013
20130075759SILICON CARBIDE SEMICONDUCTOR DEVICE - A first layer has n type conductivity. A second layer is epitaxially formed on the first layer and having p type conductivity. A third layer is on the second layer and having n type conductivity. ND is defined to represent a concentration of a donor type impurity. NA is defined to represent a concentration of an acceptor type impurity. D03-28-2013
20130075757SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device according to the present embodiment includes a diamond substrate having a surface plane inclined from a (100) plane in a range of 10 degrees to 40 degrees in a direction of <011> ±10 degrees, and an n-type diamond semiconductor layer containing phosphorus (P) and formed above the surface plane described above.03-28-2013
20130075760SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - The present application relates to technology for improving a withstand voltage of a semiconductor device. The semiconductor device includes a termination area that surrounds a cell area. The cell area is provided with a plurality of main trenches. The termination area is provided with one or more termination trenches surrounding the cell area. A termination trench is disposed at an innermost circumference of one or more termination trenches. A body region is disposed on a surface of a drift region. Each main trench reaches the drift region. A gate electrode is provided within each main trench. The termination trench reaches the drift region. Sidewalls and a bottom surface of the termination trench are covered with a insulating layer. A surface of the insulating layer covering the bottom surface of the termination trench is covered with a buried electrode. A gate potential is applied to the buried electrode.03-28-2013
20130075758SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A MOSFET includes a semiconductor substrate having a trench formed in a main surface, a gate oxide film, a gate electrode, and a source interconnection. A semiconductor substrate includes an n-type drift layer and a p-type body layer. The trench is formed to penetrate the body layer and to reach the drift layer. The trench includes an outer peripheral trench arranged to surround an active region when viewed two-dimensionally. On the main surface opposite to the active region when viewed from the outer peripheral trench, a potential fixing region where the body layer is exposed is formed. The source interconnection is arranged to lie over the active region when viewed two-dimensionally. The potential fixing region is electrically connected to the source interconnection.03-28-2013
20130082285SEMICONDUCTOR DEVICE AND PROCESS FOR PRODUCTION THEREOF - A semiconductor device according to the present invention includes a contact region 04-04-2013
20130082280LIGHT EMITTING DEVICES HAVING LIGHT COUPLING LAYERS - A light emitting device comprises a first layer of an n-type semiconductor material, a second layer of a p-type semiconductor material, and an active layer between the first layer and the second layer. A light coupling layer is disposed adjacent to one of the first layer and the second layer. In some cases, the light coupling layer is formed by roughening a buffer layer of the light emitting device. The light emitting device includes an electrode in electrical communication with one of the first layer and the second layer through a portion of the light coupling layer.04-04-2013
20090121235METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE - A transistor of a semiconductor device includes a substrate, a gate over the substrate, a source/drain region formed in the substrate to have a channel region therebetween, and an epitaxial layer formed below the channel region to have a different lattice constant from the substrate. The epitaxial layer having a different lattice constant with a substrate material is formed below the channel region to apply a stress to the channel region. Thus, the mobility of carriers of the transistor increases.05-14-2009
20090072244METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE, AND SILICON CARBIDE SEMICONDUCTOR DEVICE - The object is to provide a method for the fabrication of a semiconductor device having undergone an anneal treatment for the purpose of forming such ohmic contact as enables decrease of ohmic contact resistance and being provided on the (000-1) plane of silicon carbide with an insulating film and provide the semiconductor device. The method for the fabrication of a silicon carbide semiconductor device includes the steps of performing thermal oxidation on the (000-1) plane of a silicon carbide semiconductor in a gas containing at least oxygen and moisture, thereby forming an insulating film in such a manner as to contact the (000-1) plane of the silicon carbide semiconductor, removing part of the insulating film, thereby forming an opening part therein, depositing contact metal on at least part of the opening part, and performing a heat treatment, thereby forming a reaction layer of the contact metal and silicon carbide, wherein the heat treatment is implemented in a mixed gas of an inert gas and hydrogen.03-19-2009
20100044721METHOD OF PRODUCING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - The invention offers a method of producing a semiconductor device that can suppress the worsening of the property due to surface roughening of a wafer by sufficiently suppressing the surface roughening of the wafer in the heat treatment step and a semiconductor device in which the worsening of the property caused by the surface roughening is suppressed. The method of producing a MOSFET as a semiconductor device is provided with a step of preparing a wafer 02-25-2010
20100044720SEMICONDUCTOR DEVICE WITH A REDUCED BAND GAP AND PROCESS - The application relates to a semiconductor device made of silicon with regionally reduced band gap and a process for the production of same. One embodiment provides a semiconductor device including a body zone, a drain zone and a source zone. A gate extends between the source zone and the drain zone. A reduced band gap region is provided in a region of the body zone, made of at least ternary compound semiconductor material.02-25-2010
20130075756SEMICONDUCTOR DEVICE AND METHOD FOR REDUCED BIAS THRESHOLD INSTABILITY - According to one embodiment, a semiconductor device, having a semiconductor substrate comprising silicon carbide with a gate electrode disposed on a portion of the substrate on a first surface with, a drain electrode disposed on a second surface of the substrate. There is a dielectric layer disposed on the gate electrode and a remedial layer disposed about the dielectric layer, wherein the remedial layer is configured to mitigate negative bias temperature instability maintaining a change in threshold voltage of less than about 1 volt. A source electrode is disposed on the remedial layer, wherein the source electrode is electrically coupled to a contact region of the semiconductor substrate.03-28-2013
20120205669POWER SEMICONDUCTOR DEVICE - In a semiconductor device according to the present invention, a p-type well region disposed in an outer peripheral portion of the power semiconductor device is divided into two parts, that is, an inside and an outside, and a field oxide film having a greater film thickness than the gate insulating film is provided on a well region at the outside to an inside of an inner periphery of the well region. Therefore, it is possible to prevent, in the gate insulating film, a dielectric breakdown due to the voltage generated by the flow of the displacement current in switching.08-16-2012
20100102332METHOD OF FORMING AN OHMIC CONTACT ON A P-TYPE 4H-SIC SUBSTRATE - A method of forming an Ohmic contact on a P-type 4H—SiC and an Ohmic contact formed by the same are provided. A method of forming an Ohmic contact on a P-type 4H—SiC substrate including a deposition step of successively depositing a 1 to 60 nm thick first Al layer, Ti layer, and second Al layer on a P-type 4H—SiC substrate and an alloying step of forming an alloy layer between the SiC substrate and the Ti layer through the first Al layer by heat treatment in a nonoxidizing atmosphere. An Ohmic contact on a P-type 4H—SiC substrate formed by this method is also provided.04-29-2010
20090159898SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF - A semiconductor device is provided in which the contact resistance of the interface between an electrode and the semiconductor substrate is reduced. The semiconductor device includes a 4H polytype SiC substrate, and an electrode formed on a surface of the substrate. A 3C polytype layer, which extends obliquely relative to the surface of the substrate and whose end portion at the substrate surface is in contact with the electrode, is formed at the surface of the substrate. The 3C polytype layer has a lower bandgap than 4H polytype. Hence, electrons present in the 4H polytype region pass through the 3C polytype layer and reach the electrode. More precisely, the width of the passageway of the electrons is determined by the thickness of the 3C polytype layer. Consequently, with this semiconductor device, in which the passageway of the electrons is narrow, the electrons are able to reach the electrode at a speed close to the theoretical value, by the quantum wire effect. In this way, the contact resistance can be reduced in the semiconductor device.06-25-2009
20090159897METHOD FOR TREATING SEMICONDUCTOR PROCESSING COMPONENTS AND COMPONENTS FORMED THEREBY - A semiconductor processing component has an outer surface portion comprised of silicon carbide, the outer surface portion having a skin impurity level and a bulk impurity level. The skin impurity level is average impurity level from 0 nm to 100 nm of depth into the outer surface portion, the bulk impurity level is measured at a depth of at least 3 microns into the outer surface portion, and the skin impurity level is not greater than 80% of the bulk impurity level06-25-2009
20090159896SILICON CARBIDE MOSFET DEVICES AND METHODS OF MAKING - A method of making a silicon carbide MOSFET is disclosed. The method includes providing a semiconductor device structure, wherein the device structure comprises a silicon carbide semiconductor device layer, an ion implanted well region of a first conductivity type formed in the semiconductor device layer, an ion implanted source region of a second conductivity type formed into the ion implanted well region; providing a mask layer over the semiconductor device layer, the mask layer exposing a portion of the ion implanted source region, then etching through the portion of the ion implanted source region to form a dimple; then implanting ions through the dimple to form a high dopant concentration first conductivity type ion implanted contact region, wherein the ion implanted contact region is deeper than the ion implanted well region; then removing the contact region mask layer and annealing implanted ions.06-25-2009
20130026497SILICON CARBIDE SUBSTRATE MANUFACTURING METHOD AND SILICON CARBIDE SUBSTRATE - Silicon carbide single crystal is prepared. Using the silicon carbide single crystal as a material, a silicon carbide substrate having a first face and a second face located at a side opposite to the first face is formed. In the formation of the silicon carbide substrate, a first processed damage layer and a second processed damage layer are formed at the first face and second face, respectively. The first face is polished such that at least a portion of the first processed damage layer is removed and the surface roughness of the first face becomes less than or equal to 5 nm. At least a portion of the second processed damage layer is removed while maintaining the surface roughness of the second plane greater than or equal to 10 nm.01-31-2013
20130026496Semiconductor Device and Manufacturing Method Thereof - A method for manufacturing a semiconductor device, comprising forming a tunneling dielectric layer, a storage dielectric layer, a gate dielectric layer and a gate layer sequentially on a semiconductor substrate of a first semiconductor material; patterning the tunneling dielectric layer, the storage dielectric layer, the gate dielectric layer and the gate layer to form a gate stack; forming a groove in the semiconductor substrate on the sides of the gate stack; filling the groove with a second semiconductor material different from the first semiconductor material, meanwhile, the entire device is covered by the dielectric layer. The surface energy level in the channel is made to change by the stress generated by the second semiconductor material and the covering dielectric layer, thereby increasing tunneling current and improving the storage efficiency of the device.01-31-2013
20130026495III-Nitride Metal Insulator Semiconductor Field effect Transistor - A field effect transistor (FET) includes a III-Nitride channel layer, a III-Nitride barrier layer on the channel layer, wherein the barrier layer has an energy bandgap greater than the channel layer, a source electrode electrically coupled to one of the III-Nitride layers, a drain electrode electrically coupled to one of the III-Nitride layers, a gate insulator layer stack for electrically insulating a gate electrode from the barrier layer and the channel layer, the gate insulator layer stack including an insulator layer, such as SiN, and an AlN layer, the gate electrode in a region between the source electrode and the drain electrode and in contact with the insulator layer, and wherein the AlN layer is in contact with one of the III-Nitride layers.01-31-2013
20130026494SILICON CARBIDE SEMICONDUCTOR DEVICE - An SiC semiconductor device includes a semiconductor element formed in an SiC substrate, a source electrode and a gate pad formed by using an interconnect layer having barrier metal provided at the bottom surface thereof, and a temperature measuring resistive element formed by using part of the barrier metal in the interconnect line.01-31-2013
20130026493SIC DEVICES WITH HIGH BLOCKING VOLTAGE TERMINATED BY A NEGATIVE BEVEL - The present disclosure relates to a Silicon Carbide (SiC) semiconductor device having both a high blocking voltage and low on-resistance. In one embodiment, the semiconductor device has a blocking voltage of at least 10 kilovolts (kV) and an on-resistance of less than 10 milli-ohms centimeter squared (mΩ·cm01-31-2013
20130026492Diamond Semiconductor System and Method - Disclosed herein is a new and improved system and method for fabricating diamond semiconductors. The system may include a diamond material having n-type donor atoms and a diamond lattice, wherein 0.16% of the donor atoms contribute conduction electrons with mobility greater than 770 cm2/Vs to the diamond lattice at 100 kPa and 300K. The method of fabricating diamond semiconductors may include the steps of selecting a diamond material having a diamond lattice; introducing a minimal amount of acceptor dopant atoms to the diamond lattice to create ion tracks; introducing substitutional dopant atoms to the diamond lattice through the ion tracks; and annealing the diamond lattice.01-31-2013
20130026491LED STRUCTURE AND METHOD FOR MANUFACTURING THEREOF - The present invention discloses a LED structure and a method for manufacturing the LED structure. The LED structure includes a substrate, a reflection layer, a first conducting layer, a light emitting layer, and a second conducting layer. The substrate has a plurality of grooves, and the reflection layer is disposed inside the plurality of grooves. The reflection layer is formed as a reflection block inside each of the grooves. The first conducting layer is disposed on the substrate, that is, the reflection layer is disposed between the first conducting layer and the substrate. The light emitting layer and the second conducting layer are sequentially disposed on the first conducting layer. The light emitting layer generates light when a current pass through the light emitting layer. Accordingly, the light generated by the light emitting layer can be emitted to the same side of the LED structure.01-31-2013
20130026490GLASS/CERAMICS REPLACEMENT OF EPOXY FOR HIGH TEMPERATURE HERMETICALLY SEALED NON-AXIAL ELECTRONIC PACKAGES - A high temperature, non-cavity package for non-axial electronics is designed using a glass ceramic compound with that is capable of being assembled and operating continuously at temperatures greater that 300-400° C. Metal brazes, such as silver, silver colloid or copper, are used to connect the semiconductor die, lead frame and connectors. The components are also thermally matched such that the packages can be assembled and operating continuously at high temperatures and withstand extreme temperature variations without the bonds failing or the package cracking due to a thermal mismatch.01-31-2013
20130026489AlN BUFFER N-POLAR GaN HEMT PROFILE - An N-face GaN HEMT device including a semiconductor substrate, a buffer layer including AlN or AlGaN deposited on the substrate, a barrier layer including AlGaN or AlN deposited on the buffer layer and a GaN channel layer deposited on the barrier layer. The channel layer, the barrier layer and the buffer layer create a two-dimensional electron gas (2-DEG) layer at a transition between the channel layer and the barrier layer.01-31-2013
20130082283SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE THEREOF - A semiconductor device includes an insulating substrate, a wiring pattern formed on the insulating substrate, a semiconductor chip secured to the wiring pattern, a junction terminal formed of the same material as the wiring pattern and electrically connected to the semiconductor chip, one end of the junction terminal being secured to the insulating substrate, the other end of the junction terminal extending upward away from the insulating substrate, and a control circuit for transmitting a control signal for the semiconductor chip, the control circuit being electrically connected to the junction terminal.04-04-2013
20130082281METHOD AND STRUCTURE HAVING MONOLITHIC HETEROGENEOUS INTEGRATION OF COMPOUND SEMICONDUCTORS WITH ELEMENTAL SEMICONDUCTOR - A semiconductor structure having compound semiconductor (CS) device formed in a compound semiconductor of the structure and an elemental semiconductor device formed in an elemental semiconductor layer of the structure. The structure includes a layer having an elemental semiconductor device is disposed over a buried oxide (BOX) layer. A selective etch layer is disposed between the BOX layer and a layer for a compound semiconductor device. The selective etch layer enables selective etching of the BOX layer to thereby maximize vertical and lateral window etch process control for the compound semiconductor device grown in etched window. The selective etch layer has a lower etch rate than the etch rate of the BOX layer.04-04-2013
20130082282SILICON CARBIDE SEMICONDUCTOR DEVICE - Disclosed is a semiconductor device which includes a silicon carbide layer, a trench formed in the silicon carbide layer, and a channel formed on at least one of a bottom of the trench, a side-wall surface, or the silicon carbide layer, in which an electrical conduction direction of the channel is parallel to a surface of the silicon carbide layer.04-04-2013
20130087810FIN FIELD-EFFECT TRANSISTOR STRUCTURE - A fin field-effect transistor structure comprises a substrate, a fin channel, a source/drain region, a high-k metal gate and a plurality of slot contact structures. The fin channel is formed on the substrate. The source/drain region is formed in the fin channel. The high-k metal gate formed on the substrate and the fin channel comprises a high-k dielectric layer and a metal gate layer, wherein the high-k dielectric layer is arranged between the metal gate layer and the fin channel. The slot contact structures are disposed at both sides of the metal gate.04-11-2013
20130087809METHOD OF MANUFACTURING A SiC BIPOLAR JUNCTION TRANSISTOR AND SiC BIPOLAR JUNCTION TRANSISTOR THEREOF - A method of manufacturing a silicon carbide (SiC) bipolar junction transistor (BJT) and a SiC BJT are provided. The SiC BJT comprises an emitter region, a base region and a collector region. The collector region is arranged on a substrate having an off-axis orientation of about 4 degrees or lower. Further, a defect termination layer (DTL) is arranged between the substrate and the collector region. A thickness and a doping level of the DTL are configured to terminate basal plane dislocations in the DTL and reduce the growth of defects from the DTL to the collector region. At least some of the embodiments are advantageous in that SiC BJTs with improved stability are provided. Further, a method of evaluating the degradation performance of a SiC BJT is provided.04-11-2013
20120181551SILICON CARBIDE SEMICONDUCTOR DEVICE - A silicon carbide semiconductor device includes a silicon carbide semiconductor substrate and a trench. The silicon carbide semiconductor substrate has an offset angle with respect to a (07-19-2012
20120181549STRESSED CHANNEL FET WITH SOURCE/DRAIN BUFFERS - A method for forming a stressed channel field effect transistor (FET) with source/drain buffers includes etching cavities in a substrate on either side of a gate stack located on the substrate; depositing source/drain buffer material in the cavities; etching the source/drain buffer material to form vertical source/drain buffers adjacent to a channel region of the FET; and depositing source/drain stressor material in the cavities adjacent to and over the vertical source/drain buffers.07-19-2012
20090045414SILICON CARBIDE SEMICONDUCTOR ELEMENT, METHOD OF MANUFACTURING THE SAME, AND SILICON CARBIDE DEVICE - A silicon carbide semiconductor element and a manufacturing method thereof are disclosed in which a low contact resistance is attained between an electrode film and a wiring conductor element, and the wiring conductor element is hardly detached from the electrode film. In the method, a nickel film and a nickel oxide film are laminated in this order on a surface of an n-type silicon carbide substrate or an n-type silicon carbide region of a silicon carbide substrate, followed by a heat treatment under a non-oxidizing condition. The heat treatment transforms a portion of the nickel film into a nickel silicide film. Then, the nickel oxide film is removed with hydrochloric acid solution, and subsequently, a nickel aluminum film and an aluminum film are laminated in this order on a surface of the nickel silicide film.02-19-2009
20130087808SIC BIPOLAR JUNCTION TRANSISTOR WITH OVERGROWN EMITTER - New designs for silicon carbide (SiC) bipolar junction transistors (BJTs) and new methods of manufacturing such SiC BJTs are provided. The SiC BJT can include a collector region, a base region, and an emitter region where the collector region, the base region, and the emitter region are arranged as a stack. The emitter region can form an elevated structure defined by outer sidewalls disposed on the stack. The base region can have a portion interfacing the emitter region and defining an intrinsic base region. The intrinsic base region can include a first portion laterally spaced away from the outer sidewalls of the emitter region by a second portion of the base region that has a dopant dose higher than a dopant dose of the first portion.04-11-2013
20100001292High Efficiency Indirect Transition Semiconductor Ultraviolet Light Emitting Device - Provided is a light emitting device formed of an indirect transition semiconductor configured from a semiconductor material having high exciton binding energy, wherein an active layer of the indirect transition semiconductor or an active region by a pn junction is formed, the light emitting device has an electrode for injecting current into the active layer or the active region, and the internal quantum efficiency is 10% or more.01-07-2010
20100133549Semiconductor Devices with Current Shifting Regions and Related Methods - A semiconductor device may include a semiconductor buffer layer having a first conductivity type and a semiconductor mesa having the first conductivity type on a surface of the buffer layer. In addition, a current shifting region having a second conductivity type may be provided adjacent a corner between the semiconductor mesa and the semiconductor buffer layer, and the first and second conductivity types may be different conductivity types. Related methods are also discussed.06-03-2010
20090315040WIDE BANDGAP DEVICE IN PARALLEL WITH A DEVICE THAT HAS A LOWER AVALANCHE BREAKDOWN VOLTAGE AND A HIGHER FORWARD VOLTAGE DROP THAN THE WIDE BANDGAP DEVICE - A method and device for protecting wide bandgap devices from failing during suppression of voltage transients. An improvement in avalanche capability is achieved by placing one or more diodes, or a PNP transistor, across the blocking junction of the wide bandgap device.12-24-2009
20090108266Friction Control in Apparatus Having Wide Bandgap Semiconductors - Apparatus comprising, in use, a wide bandgap semiconductor, a conductor which is moveable relative to the semiconductor and means for applying a potential across the junction between a conductor and semiconductor to control the friction generated by the relative movement between the semiconductor and the conductor. A method of controlling friction between a wide bandgap semiconductor and conductor which are moveable relative to each other comprising applying a potential across the junction between the semiconductor and the conductor.04-30-2009
20090302328Silicon carbide semiconductor substrate and method of manufacturing the same - A buffer layer configured of the same conductive semiconductor layers of two or more layers as a drift layer is installed by epitaxial growth between a first semiconductor layer configuring the drift layer that is a layer in which components of the semiconductor device are made and a base substrate including a silicon carbide single crystal wafer. A step of donor concentration is provided at an interface between the drift layer and the buffer layer, an interface between the semiconductor layers configuring the buffer layer, and an interface between the buffer layer and the base substrate and the donor concentration of the drift layer side is lower than that of the base substrate side, thereby making it possible to convert most basal plane dislocations into threading edge dislocations as compared to the drift layer having one layer or the buffer layer configured of one layer.12-10-2009
20120217513SILICON CARBIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A SiC MOSFET has a subject that resistance in the source region is increased when annealing for metal silicidation is performed to a source region before forming the gate insulating film, the metal silicide layer of the source region is oxidized by an oxidizing treatment (including oxynitriding treatment) when the gate insulating film is formed. When a metal silicide layer to be formed on the surface of a SiC epitaxial substrate is formed before forming a gate insulating film interface layer (oxide film), and an anti-oxidation film for the metal silicide is formed on the metal silicide layer, it is possible to suppress oxidation of the metal silicide layer by the oxidizing treatment upon forming the gate insulating film interface layer and the resistance of the source region can be decreased without lowering the channel mobility.08-30-2012
20130056755POWER SEMICONDUCTOR MODULE - A transistor chip formed from a wide band gap semiconductor, on which transistor elements for an upper arm are formed is mounted on a front surface of an insulating substrate. A transistor chip formed from a wide band gap semiconductor, on which transistor elements for a lower arm are formed is mounted on a rear surface of the insulating substrate.03-07-2013
20130056752SILICON CARBIDE SUBSTRATE, SILICON CARBIDE SUBSTRATE MANUFACTURING METHOD, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - An edge region has a width of 5 mm. A valid region is surrounded by the edge region, and has an area greater than or equal to 100 cm03-07-2013
20120112209SILICON CARBIDE SUBSTRATE FABRICATION METHOD, SEMICONDUCTOR DEVICE FABRICATION METHOD, SILICON CARBIDE SUBSTRATE, AND SEMICONDUCTOR DEVICE - A method of fabricating a silicon carbide substrate that can reduce the fabrication cost of a semiconductor device employing the silicon carbide substrate includes the steps of: preparing a SiC substrate made of single crystal silicon carbide; arranging a base substrate in a vessel so as to face one main face of the SiC substrate; forming a base layer made of silicon carbide so as to contact one main face of the SiC substrate by heating a base substrate to a temperature range greater than or equal to a sublimation temperature of silicon carbide constituting the base substrate. In the step of forming a base layer, a silicon generation source made of a substance including silicon is arranged in the vessel, in addition to the SiC substrate and the base substrate.05-10-2012
20120112208STRESSED TRANSISTOR WITH IMPROVED METASTABILITY - An embedded, strained epitaxial semiconductor material, i.e., an embedded stressor element, is formed at the footprint of at least one pre-fabricated field effect transistor that includes at least a patterned gate stack, a source region and a drain region. As a result, the metastability of the embedded, strained epitaxial semiconductor material is preserved and implant and anneal based relaxation mechanisms are avoided since the implants and anneals are performed prior to forming the embedded, strained epitaxial semiconductor material.05-10-2012
20120112206ASYMMETRIC HETERO-STRUCTURE FET AND METHOD OF MANUFACTURE - An asymmetric hetero-structure FET and method of manufacture is provided. The structure includes a semiconductor substrate and an epitaxially grown semiconductor layer on the semiconductor substrate. The epitaxially grown semiconductor layer includes an alloy having a band structure and thickness that confines inversion carriers in a channel region, and a thicker portion extending deeper into the semiconductor structure at a doped edge to avoid confinement of the inversion carriers at the doped edge.05-10-2012
20120305940Defect Free Si:C Epitaxial Growth - A method and structure are disclosed for a defect free Si:C source/drain in an NFET device. A wafer is accepted with a primary surface of {100} crystallographic orientation. A recess is formed in the wafer in such manner that the bottom surface and the four sidewall surfaces of the recess are all having {100} crystallographic orientations. A Si:C material is eptaxially grown in the recess, and due to the crystallographic orientations the defect density next to each of the four sidewall surfaces is essentially the same as next to the bottom surface. The epitaxially filled recess is used in the source/drain fabrication of an NFET device. The NFET device is oriented along the <100> crystallographic direction, and has the device channel under a tensile strain due to the defect free Si:C in the source/drain.12-06-2012
20130056753Semiconductor Device with Low-Conducting Field-controlling Element - A semiconductor device including a low conducting field-controlling element is provided. The device can include a semiconductor including an active region (e.g., a channel), and a set of contacts to the active region. The field-controlling element can be coupled to one or more of the contacts in the set of contacts. The field-controlling element can be formed of a low conducting layer of material and have a lateral resistance that is both larger than an inverse of a minimal operating frequency of the device and smaller than an inverse of a maximum control frequency of the device.03-07-2013
20130056754ELECTRONIC CIRCUIT DEVICE - A normally-off type silicon carbide junction FET has a problem that the gate thereof is not easy to use due to inferiority in the characteristics of it. This problem occurs because in order to achieve normally-off, the gate voltage should be off at 0V and at the same time, the ON-state gate voltage should be suppressed to about 2.5V to prevent the passage of an electric current through a pn junction between gate and source. Accordingly, a range from the threshold voltage to the ON-state gate voltage is only from about 1 V to 2V and it is difficult to control the gate voltage. Provided in the present invention is an electronic circuit device obtained by coupling, to a gate of a normally-off type silicon carbide junction FET, an element having a capacitance equal to or a little smaller than the gate capacitance of the junction FET.03-07-2013
20130161647INGOT, SUBSTRATE, AND SUBSTRATE GROUP - An ingot, a substrate, and a substrate group are obtained each of which is made of silicon carbide and is capable of suppressing variation of characteristics of semiconductor devices. The ingot is made of single-crystal silicon carbide, and has p type impurity. The ingot has a thickness of 10 mm or greater in a growth direction thereof. Further, the ingot has an average carrier density of 1×1006-27-2013
20130161645SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate having a principal surface, and an insulating film formed on the principal surface and continuously covering a top surface of a first boundary region and a top surface of a second boundary region, the first boundary region including a boundary between a well layer and a RESURF layer, the second boundary region including a boundary between the RESURF layer and a first impurity region. The semiconductor device further includes a plurality of lower field plates formed in the insulating film in such a manner that the plurality of lower field plates do not lie directly above the first and second boundary regions, and a plurality of upper field plates formed on the insulating film in such a manner that the plurality of upper field plates do not lie directly above the first and second boundary regions.06-27-2013
20130161642SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - The present application discloses a semiconductor device and a method for manufacturing the same. The semiconductor device comprises an SOI substrate; a semiconductor fin formed on the SOI substrate, the semiconductor fin having a first side and a second side which are opposite to each other and stand upward on a surface of the SOI substrate, and a trench which is opened at a central portion of the second side and opposite to the first side; a channel region formed in the fin and being between the first side and the trench at the second side; source and drain regions formed in the fin and sandwiching the channel region; and a gate stack formed on the SOI substrate and being adjacent to the first side of the fin, wherein the gate stack comprises a first gate dielectric extending away from the first side and being adjacent to the channel region, a first conductor layer extending away from the first side and being adjacent to the first gate dielectric, a second gate dielectric extending away from the first side and being adjacent laterally to one side of the first conductor layer, and a second conductor layer extending away from the first side and being adjacent laterally to one side of the second gate dielectric. The embodiments of the invention can be applied in manufacturing an FinFET.06-27-2013
20130161643Method for Fabricating Three-Dimensional Gallium Nitride Structures with Planar Surfaces - A method is provided for fabricating three-dimensional gallium nitride (GaN) pillar structures with planar surfaces. After providing a substrate, the method grows a GaN film overlying a top surface of the substrate and forms cavities in a top surface of the GaN film. The cavities are formed using a laser ablation, ion implantation, sand blasting, or dry etching process. The cavities in the GaN film top surface are then wet etched, forming planar sidewalls extending into the GaN film. More explicitly, the cavities are formed into a c-plane GaN film top surface, and the planar sidewalls are formed perpendicular to a c-plane, in the m-plane or a-plane family.06-27-2013
20130062629SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A substrate is provided with a main surface having an off angle of 5° or smaller relative to a reference plane. The reference plane is a {000-1} plane in the case of hexagonal system and is a {111} plane in the case of cubic system. A silicon carbide layer is epitaxially formed on the main surface of the substrate. The silicon carbide layer is provided with a trench having first and second side walls opposite to each other. Each of the first and second side walls includes a channel region. Further, each of the first and second side walls substantially includes one of a {0-33-8} plane and a {01-1-4} plane in the case of the hexagonal system and substantially includes a {100} plane in the case of the cubic system.03-14-2013
20130062627STRESS REGULATED SEMICONDUCTOR DEVICES AND ASSOCIATED METHODS - Stress regulated semiconductor devices and associated methods are provided. In one aspect, for example, a stress regulated semiconductor device can include a semiconductor layer, a stress regulating interface layer including a carbon layer formed on the semiconductor layer, and a heat spreader coupled to the carbon layer opposite the semiconductor layer. The stress regulating interface layer is operable to reduce the coefficient of thermal expansion difference between the semiconductor layer and the heat spreader to less than or equal to about 10 ppm/° C.03-14-2013
20130062624SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device according to an embodiment includes a silicon carbide, a metal silicide formed on the silicon carbide and including a first layer and a second layer having a carbon ratio lower than that of the first layer, and a metallic electrode formed on the metal silicide, wherein the second layer is formed on the first layer, and the second layer is in contact with the metallic electrode, and an average grain diameter of a metal silicide in the second layer is larger than an average grain diameter of a metal silicide in the first layer.03-14-2013
20130062626POWER SEMICONDUCTOR MODULE - Disclosed is a power semiconductor module which includes a unipolar type switching device using a wide bandgap semiconductor (wide bandgap semiconductor switching device) and an insulated gate bipolar transistor using a silicon semiconductor (Si-IGBT) connected in parallel, in which a chip area of the wide bandgap semiconductor switching device is smaller than that of the Si-IGBT.03-14-2013
20130062628METHODS FOR THE EPITAXIAL GROWTH OF SILICON CARBIDE - A method for the epitaxial growth of SiC is described which includes contacting a surface of a substrate with hydrogen and HCl, subsequently increasing the temperature of the substrate to at least 1550° C. and epitaxially growing SiC on the surface of the substrate. A method for the epitaxial growth of SiC is also described which includes heating a substrate to a temperature of at least 1550° C., contacting a surface of the substrate with a C containing gas and a Si containing gas at a C/Si ratio of 0.5-0.8 to form a SiC buffer layer and subsequently contacting the surface with a C containing gas and a Si containing gas at a C/Si ratio >0.8 to form a SiC epitaxial layer on the SiC buffer layer. The method results in silicon carbide epitaxial layers with improved surface morphology.03-14-2013
20130062625SEMICONDUCTOR DEVICE - Disclosed is a semiconductor device including: a semiconductor substrate; a field effect transistor formed on the semiconductor substrate; and a diode forming area adjacent to a forming area of the field effect transistor, wherein the diode forming area is insulated from the forming area of the field effect transistor on the semiconductor substrate, the diode forming area includes an anode electrode and a cathode electrode arranged side by side in a multi-finger shape, and the anode electrode and the cathode electrode are formed in a direction different from directions of a gate electrode, a source electrode, and a drain electrode of the field effect transistor arranged side by side in a multi-finger shape.03-14-2013
20130062623SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Disclosed is a semiconductor device including: a first electrode formed of a conductive material; a p-type first silicon carbide (SiC) semiconductor section and an n-type second SiC semiconductor section 03-14-2013
20130062620SCHOTTKY DIODE EMPLOYING RECESSES FOR ELEMENTS OF JUNCTION BARRIER ARRAY - The present disclosure generally relates to a Schottky diode that has a substrate, a drift layer provided over the substrate, and a Schottky layer provided over an active region of the substrate. A junction barrier array is provided in the drift layer just below the Schottky layer. The elements of the junction barrier array are generally doped regions in the drift layer. To increase the depth of these doped regions, individual recesses may be formed in the surface of the drift layer where the elements of the junction barrier array are to be formed. Once the recesses are formed in the drift layer, areas about and at the bottom of the recesses are doped to form the respective elements of the junction barrier array.03-14-2013
20130062622SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device according to the present embodiment includes a semiconductor substrate having a first n-type silicon carbide layer and a second n-type silicon carbide layer, a first p-type impurity region formed in the n-type silicon carbide layer, a first n-type impurity region of 4H—SiC structure formed in the n-type silicon carbide layer, a second n-type impurity region of 3C—SiC structure formed in the n-type silicon carbide layer having a depth shallower than the first n-type impurity region, a gate insulating film, a gate electrode formed on the gate insulating film, and a metallic silicide layer formed above the first n-type impurity region and having a bottom portion and a side surface portion such that the second n-type impurity region is sandwiched between the first n-type impurity region and at least the side surface portion.03-14-2013
20130062619EDGE TERMINATION STRUCTURE EMPLOYING RECESSES FOR EDGE TERMINATION ELEMENTS - Elements of an edge termination structure, such as multiple concentric guard rings, are effectively doped regions in a drift layer. To increase the depth of these doped regions, individual recesses may be formed in a surface of the drift layer where the elements of the edge termination structure are to be formed. Once the recesses are formed in the drift layer, these areas about and at the bottom of the recesses are doped to form the respective edge termination elements.03-14-2013
20130062621III-N DEVICE STRUCTURES HAVING A NON-INSULATING SUBSTRATE - Embodiments of the present disclosure includes a III-N device having a substrate layer, a first III-N material layer on one side of the substrate layer, a second III-N material layer on the first III-N material layer, and a barrier layer disposed on another side of the substrate layer, the barrier layer being less electrically conductive than the substrate layer.03-14-2013
20120223330SEMICONDUCTOR DEVICE HAVING HIGH PERFORMANCE CHANNEL - Semiconductor devices having a high performance channel and method of fabrication thereof are disclosed. Preferably, the semiconductor devices are Metal-Oxide-Semiconductor (MOS) devices, and even more preferably the semiconductor devices are Silicon Carbide (SiC) MOS devices. In one embodiment, a semiconductor device includes a SiC substrate of a first conductivity type, a first well of a second conductivity type, a second well of the second conductivity type, and a surface diffused channel of the second conductivity type formed at the surface of semiconductor device between the first and second wells. A depth and doping concentration of the surface diffused channel are controlled to provide increased carrier mobility for the semiconductor device as compared to the same semiconductor device without the surface diffused channel region when in the on-state while retaining a turn-on, or threshold, voltage that provides normally-off behavior.09-06-2012
20110012133SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A silicon carbide MOSFET that exhibits a high source-to-drain withstand voltage and that involves a smaller difference between gate-to-drain capacitance achieved in an activated state and gate-to-drain capacitance achieved in a deactivated state. A silicon carbide drift layer of a first conductivity type is provided on a silicon carbide substrate of a first conductivity type; a pair of base regions are provided in a surface layer portion of the silicon carbide drift layer and exhibit a second conductivity type; a pair of source regions are provided in interiors of surface layer portions of the pair of base regions and exhibit a first conductivity type; and semi-insulating regions are provided between the silicon carbide substrate and the pair of base regions.01-20-2011
20110012132Semiconductor Device - Provided is a semiconductor device which has improved withstand voltage and can be manufactured by simpler manufacturing process. The semiconductor device according to the present invention includes: a SiC-containing n-type epitaxial layer 01-20-2011
20110012131METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE, AND SEMICONDUCTOR DEVICE - An object is to provide a novel manufacturing method of a semiconductor substrate containing silicon carbide, and another object is to provide a semiconductor device using silicon carbide. A semiconductor substrate is manufactured through the steps of: adding ions to a silicon carbide substrate to form an embrittlement region in the silicon carbide substrate; bonding the silicon carbide substrate to a base substrate with insulating layers interposed therebetween; heating the silicon carbide substrate and separating the silicon carbide substrate at the embrittlement region to form a silicon carbide layer over the base substrate with the insulating layers interposed between therebetween; and performing heat treatment on the silicon carbide layer at a temperature of 1000° C. to 1300° C. to reduce defects of the silicon carbide layer. A semiconductor device is manufactured using the semiconductor substrate formed as described above.01-20-2011
20110012130High Breakdown Voltage Wide Band-Gap MOS-Gated Bipolar Junction Transistors with Avalanche Capability - High power wide band-gap MOSFET-gated bipolar junction transistors (“MGT”) are provided that include a first wide band-gap bipolar junction transistor (“BJT”) having a first collector, a first emitter and a first base, a wide band-gap MOSFET having a source region that is configured to provide a current to the base of the first wide band-gap BJT and a second wide band-gap BJT having a second collector that is electrically connected to the first collector, a second emitter that is electrically connected to the first emitter, and a second base that is electrically connected to the first base.01-20-2011
20110012129High-Gain Wide Bandgap Darlington Transistors and Related Methods of Fabrication - A packaged power electronic device includes a wide bandgap bipolar driver transistor having a base, a collector, and an emitter terminal, and a wide bandgap bipolar output transistor having a base, a collector, and an emitter terminal. The collector terminal of the output transistor is coupled to the collector terminal of the driver transistor, and the base terminal of the output transistor is coupled to the emitter terminal of the driver transistor to provide a Darlington pair. An area of the output transistor is at least 3 times greater than an area of the driver transistor in plan view. For example, an area ratio of the output transistor to the driver transistor may be between about 3:1 to about 5:1. Related devices and methods of fabrication are also discussed.01-20-2011
20090261351Silicon Carbide Devices Having Smooth Channels - Power devices are provided including a p-type conductivity well region and a buried p10-22-2009
20100123140SiC SUBSTRATES, SEMICONDUCTOR DEVICES BASED UPON THE SAME AND METHODS FOR THEIR MANUFACTURE - The present invention generally relates to a method for improving inversion layer mobility and providing low defect density in a semiconductor device based upon a silicon carbide (SiC) substrate. More specifically, the present invention provides a method for the manufacture of a semiconductor device based upon a silicon carbide substrate and comprising an oxide layer comprising incorporating at least one additive into the atomic structure of the oxide layer. Semiconductor devices, such as MOSFETS, based upon a substrate treated according to the present method are expected to have inversion layer mobilities of at least about 60 cm05-20-2010
20090236612SILICON CARBIDE MOS SEMICONDUCTOR DEVICE - A silicon carbide MOS semiconductor device is disclosed which suppresses degradation of efficiency percentage yield with respect to a breakdown voltage even when a surface region with a high impurity concentration is formed by ion implantation with such a high dose as required for attaining a good ohmic contact. The device has a silicon carbide semiconductor substrate, a voltage blocking layer of a first conductivity type formed on the substrate, a body region of a second conductivity type formed on the voltage blocking layer, a body contact region of the second conductivity type formed in a surface region of the body region by selective ion implantation, a surface of the body contact region having such a high impurity concentration as to impart an ohmic contact, a source contact region of the first conductivity type formed in a surface region of the body region by selective ion implantation, a surface of the source contact region having such a high impurity concentration as to impart an ohmic contact, and a source extension region with an impurity concentration lower than that in the source contact region under the source contact region at a region deeper than a tail part of a bottom region of the source contact region by selective ion implantation, the source extension region having an impurity concentration less than 3×1009-24-2009
20090236611SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MAKING THE SAME - A silicon carbide semiconductor device provided as a semiconductor chip includes a substrate, a drift layer on the substrate, an insulation film on the drift layer, a semiconductor element formed in a cell region of the drift layer, a surface electrode formed on the drift layer and electrically coupled to the semiconductor element through an opening of the insulation film, and a passivation film formed above the drift layer around the periphery of the cell region to cover an outer edge of the surface electrode. The passivation film has an opening through which the surface electrode is exposed outside. A surface of the passivation film is made uneven to increase a length from an inner edge of the opening of the passivation film to a chip edge measured along the surface of the passivation film.09-24-2009
20090236610Method for Manufacturing a Semiconductor Structure, and a Corresponding Semiconductor Structure - A method for manufacturing a semiconductor structure is provided which includes the following operations: supplying a crystalline semiconductor substrate, providing a porous region adjacent to a surface of the semiconductor substrate, introducing a dopant into the porous region from the surface, and thermally recrystallizing the porous region into a crystalline doping region of the semiconductor substrate whose doping type and/or doping concentration and/or doping distribution are/is different from those or that of the semiconductor substrate. A corresponding semiconductor structure is likewise provided.09-24-2009
20090236609Method and Apparatus for Producing Graphene Oxide Layers on an Insulating Substrate - In a method of making a functionalized graphitic structure, a portion of a multi-layered graphene surface extending from a silicon carbide substrate is exposed to an acidic environment so as to separate graphene layers in a portion of the multi-layered graphene surface. The portion of the multi-layered graphene surface is exposed to a functionalizing material that binds to carbon atoms in the graphene sheets so that the functionalizing material remains between the graphene sheets, thereby generating a functionalized graphitic structure. The functionalized graphitic structure is dried in an inert environment.09-24-2009
20090236608Method for Producing Graphitic Patterns on Silicon Carbide - In a method of making a vertical graphitic path on a silicon carbide crystal having a horizontal surface, a portion of the silicon carbide crystal is removed from the horizontal surface so as to define a vertical surface that is transverse to the horizontal surface of the silicon carbide crystal. The vertical surface is annealed so as to generate a thin-film graphitic layer on the vertical surface. In another method of making graphitic layers, a material that inhibits formation of a graphitic layer when the silicon carbide crystal is annealed is applied to a surface of a silicon carbide crystal so as to define at least one opening that exposes a portion of the surface of the silicon carbide crystal. The portion of the silicon carbide crystal is annealed so as to generate a thin-film graphitic layer in the portion of the silicon carbide crystal.09-24-2009
20090050899High-output diamond semiconductor element - The present invention relates to a high-output diamond semiconductor element, including a Schottky electrode as a cathode, a diamond P02-26-2009
20130069082SEMICONDUCTOR DEVICE AND SOLID STATE RELAY USING SAME - A semiconductor device includes one or more unipolar compound semiconductor element; and bypass semiconductor elements externally connected to the respective compound semiconductor elements in parallel. A turn-on voltage of the bypass semiconductor elements is smaller than a turn-on voltage of the compound semiconductor elements in the direction from the source to the drain.03-21-2013
20130069081Layout Method To Minimize Context Effects and Die Area - An integrated circuit with an active geometry with a wide active region and with a narrow active region with at least one jog where said wide active region transitions to said narrow active region and where a gate overlies said jog. A method of making an integrated circuit with an active geometry with a wide active region and with a narrow active region with at least one jog where said wide active region transitions to said narrow active region, where a gate overlies said jog and where a gate overlies the wide active region forming a wide transistor.03-21-2013
20130069080SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor device includes a silicon carbide substrate having a first surface and a second surface on a side opposite to the first surface, a semiconductor layer having an element region and a peripheral region provided on the second surface of the silicon carbide substrate, an insulating film provided on a surface of the peripheral region of the semiconductor layer, a reinforcing substrate provided on the insulating film in the peripheral region, a first electrode provided in contact with the first surface of the silicon carbide substrate, and a second electrode provided in contact with a surface of the element region. The peripheral region is further on an edge portion side than is the element region.03-21-2013
20090020764GRAPHENE-BASED TRANSISTOR - A graphene layer is formed on a surface of a silicon carbide substrate. A dummy gate structure is formed over the fin, in the trench, or on a portion of the planar graphene layer to implant dopants into source and drain regions. The dummy gate structure is thereafter removed to provide an opening over the channel of the transistor. Threshold voltage adjustment implantation may be performed to form a threshold voltage implant region directly beneath the channel, which comprises the graphene layer. A gate dielectric is deposited over a channel portion of the graphene layer. After an optional spacer formation, a gate conductor is formed by deposition and planarization. The resulting graphene-based field effect transistor has a high carrier mobility due to the graphene layer in the channel, low contact resistance to the source and drain region, and optimized threshold voltage and leakage due to the threshold voltage implant region.01-22-2009
20090008651Silicon carbide semiconductor device having junction barrier schottky diode - A silicon carbide semiconductor device includes a drift layer having first conductive type on a substrate, a cell region in the drift layer, a schottky electrode on the drift layer and multiple second conductive type layers in the cell region. The second conductive type layers are separated from each other and contact the schottky electrode. A size and an impurity concentration of the second conductive type layers and a size and an impurity concentration of a portion of the drift layer sandwiched between the second conductive type layers are determined so that a charge quantity of the second conductive type layers is equal to a charge quantity of the portion. Hereby, the pressure-proof JBS and low resistivity second conductive type layers arranged on a surface of the drift layer to provide a PN diode, can be obtained.01-08-2009
20090008649Silicon carbide semiconductor device and method of manufacturing the same - A silicon carbide semiconductor device includes a substrate having one of a first conductivity type and a second conductivity type, a drift layer having the first conductivity type, a plurality of base regions having the second conductivity type, a plurality of source regions having the first conductivity type, a surface channel layer having the first conductivity type, a plurality of body layers having the second conductivity type, a gate insulation layer, a gate electrode, a first electrode, a second electrode, and a plurality of second conductivity-type regions. The first electrode is electrically coupled with the source regions and the body layers. The second conductivity-type regions are disposed at portions of the drift layer located under the body layers so as to be connected with the base regions respectively.01-08-2009
20130134444STRESSED TRANSISTOR WITH IMPROVED METASTABILITY - An embedded, strained epitaxial semiconductor material, i.e., an embedded stressor element, is formed at the footprint of at least one pre-fabricated field effect transistor that includes at least a patterned gate stack, a source region and a drain region. As a result, the metastability of the embedded, strained epitaxial semiconductor material is preserved and implant and anneal based relaxation mechanisms are avoided since the implants and anneals are performed prior to forming the embedded, strained epitaxial semiconductor material.05-30-2013
20120235165SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device includes: a substrate made of silicon carbide and having a main surface having an off angle of not less than −° and not more than +5° relative to a (0-33-8) plane in a <01-10> direction; a p type layer made of silicon carbide and formed on the main surface of the substrate by means of epitaxial growth; and an oxide film formed in contact with a surface of the p type layer. A maximum value of nitrogen atom concentration is 1×1009-20-2012
20120235164TRANSISTOR WITH A-FACE CONDUCTIVE CHANNEL AND TRENCH PROTECTING WELL REGION - A transistor structure optimizes current along the A-face of a silicon carbide body to form an AMOSFET that minimizes the JFET effect in the drift region during forward conduction in the on-state. The AMOSFET further shows high voltage blocking ability due to the addition of a highly doped well region that protects the gate corner region in a trench-gated device. The AMOSFET uses the A-face conduction along a trench sidewall in addition to a buried channel layer extending across portions of the semiconductor mesas defining the trench. A doped well extends from at least one of the mesas to a depth within the current spreading layer that is greater than the depth of the trench. A current spreading layer extends between the semiconductor mesas beneath the bottom of the trench to reduce junction resistance in the on-state. A buffer layer between the trench and the deep well further provides protection from field crowding at the trench corner.09-20-2012
20120235163SEMICONDUCTOR SUBSTRATE AND METHOD FOR PRODUCING SEMICONDUCTOR SUBSTRATE - A semiconductor substrate includes: single crystal silicon; a mask material formed on a surface of the single crystal silicon and having an opening; a silicon carbide film formed on a portion exposed in the opening of the single crystal silicon; and a single crystal silicon carbide film formed so as to cover the silicon carbide film and the mask material. The mask material has a viscosity of 1009-20-2012
20120235162POWER CONVERTER - This power converter includes a power-conversion semiconductor element, an electrode conductor having a substantially flat upper end surface, and a sealant. The sealant allows the substantially flat upper end surface of the electrode conductor to be exposed at an upper surface of the sealant, and provides electrical connection with an external device at the upper end surface of the exposed electrode conductor.09-20-2012
20130161648Diamond Semiconductor System and Method - Disclosed herein is a new and improved system and method for fabricating diamond semiconductors. The method may include the steps of selecting a diamond semiconductor material having a surface, exposing the surface to a source gas in an etching chamber, forming a carbide interface contact layer on the surface; and forming a metal layer on the interface layer.06-27-2013
20130161649STRUCTURE AND METHOD FOR INCREASING STRAIN IN A DEVICE - A method and structure are disclosed for increasing strain in a device, specifically an n-type field effect transistor (NFET) complementary metal-oxide-semiconductor (CMOS) device. Embodiments of this invention include an n-type field effect transistor (NFET) complementary metal-oxide-semiconductor (CMOS) device having a source region and a drain region, the NFET CMOS including: an n-type doped layer in at least one of the source region and the drain region, wherein the n-type doped layer includes substitutional carbon and has a memorized tensile stress induced by a stress memorization technique (SMT).06-27-2013
20130161650DEVICE WITH SELF ALIGNED STRESSOR AND METHOD OF MAKING SAME - A method includes providing a substrate comprising a substrate material, a gate dielectric film above the substrate, and a first spacer adjacent the gate dielectric film. The spacer has a first portion in contact with a surface of the substrate and a second portion in contact with a side of the gate dielectric film. A recess is formed in a region of the substrate adjacent to the spacer. The recess is defined by a first sidewall of the substrate material. At least a portion of the first sidewall underlies at least a portion of the spacer. The substrate material beneath the first portion of the spacer is reflowed, so that a top portion of the first sidewall of the substrate material defining the recess is substantially aligned with a boundary between the gate dielectric film and the spacer. The recess is filled with a stressor material.06-27-2013
20130161651LOW 1C SCREW DISLOCATION 3 INCH SILICON CARBIDE WAFER - A high quality single crystal wafer of SiC is disclosed having a diameter of at least about 3 inches and a 1 c screw dislocation density from about 500 cm06-27-2013
20110042685SUBSTRATES AND METHODS OF FABRICATING EPITAXIAL SILICON CARBIDE STRUCTURES WITH SEQUENTIAL EMPHASIS - Embodiments of the invention relate generally to semiconductors and semiconductor fabrication techniques, and more particularly, to devices, integrated circuits, substrates, and methods to form silicon carbide structures, including epitaxial layers, by supplying sources of silicon and carbon with sequential emphasis. In at least some embodiments, a method of forming an epitaxial layer of silicon carbide can include depositing a layer on a substrate in the presence of a silicon source, and purging gaseous materials subsequent to depositing the layer. Further, the method can include converting the layer into a sub-layer of silicon carbide in the presence of a carbon source, and purging other gaseous materials subsequent to converting the layer. The presence of the silicon source can be independent of the presence of the carbon source. In some embodiments, dopants, such as n-type dopants, can be introduced during the formation of the epitaxial layer of silicon carbide.02-24-2011
20120193642DIAMOND SEMICONDUCTOR DEVICES AND ASSOCIATED METHODS - Semiconductor devices and methods for making such devices are provided. One such method may include forming a transparent diamond layer having a SiC layer coupled thereto, where the SiC layer has a crystal structure that is substantially epitaxially matched to the transparent diamond layer, forming epitaxially a plurality of semiconductor layers on the SiC layer, and coupling a diamond substrate to at least one of the plurality of semiconductor layers such that the diamond support is oriented parallel to the transparent diamond layer. In one aspect such a method may further include electrically coupling at least one of a p-type electrode or an n-type electrode to at least one of the plurality of semiconductor layers.08-02-2012
20090302327RUGGED SEMICONDUCTOR DEVICE ARCHITECTURE - A wide bandgap silicon carbide device has an avalanche control structure formed in an epitaxial layer of a first conductivity type above a substrate that is connected to a first electrode of the device. A first region of a second conductivity type is in the upper surface of the epitaxial layer with a connection to a second electrode of the device. A second region of the first conductivity type lies below the first region and has a dopant concentration greater than the dopant concentration in the epitaxial layer.12-10-2009
20110278599SILICON CARBIDE SEMICONDUCTOR DEVICE - A SiC semiconductor device capable of increasing a switching speed without destroying a gate insulating film. In addition, in a SiC-MOSFET including an n-type semiconductor substrate formed of SiC, a p-type semiconductor layer is entirely or partially provided on an upper surface of a p-type well layer that has a largest area of the transverse plane among a plurality of p-type well layers provided in an n-type drift layer and is arranged on an outermost periphery immediately below a gate electrode pad. It is preferable that a concentration of an impurity contained in the p-type semiconductor layer be larger than that of the p-type well layer.11-17-2011
20110278595METHOD FOR MANUFACTURING SILICON CARBIDE SUBSTRATE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, SILICON CARBIDE SUBSTRATE, AND SEMICONDUCTOR DEVICE - A method for manufacturing a silicon carbide substrate includes the steps of: preparing a base substrate made of silicon carbide and a SiC substrate made of single-crystal silicon carbide; fabricating a stacked substrate by placing said SiC substrate on and in contact with a main surface of said base substrate; and connecting said base substrate and said SiC substrate to each other by heating said stacked substrate in a container to fall within a range of temperature equal to or greater than a sublimation temperature of silicon carbide constituting said base substrate. In the step of connecting said base substrate and said SiC substrate, a silicon carbide body made of silicon carbide and different from said base substrate and said SiC substrate is disposed in said container.11-17-2011
20110278598SEMICONDUCTOR STRUCTURE, AN INTEGRATED CIRCUIT INCLUDING A SEMICONDUCTOR STRUCTURE AND A METHOD FOR MANUFACTURING A SEMICONDUCTOR STRUCTURE - A monolithic semiconductor structure includes a stack of layers. The stack includes a substrate; a first layer made from a first semiconductor material; and a second layer made from a second semiconductor material. The first layer is situated between the substrate and the second layer and at least one of the first semiconductor material and the second semiconductor material contains a III-nitride material. The structure includes a power transistor, including a body formed in the stack of layers; a first power terminal at a side of the first layer facing the second layer; a second power terminal at least partly formed in the substrate; and a gate structure for controlling the propagation through the body of electric signals between the first power terminal and the second power terminal. The structure further includes a vertical Schottky diode, including: an anode; a cathode including the substrate, and a Schottky barrier between the cathode and the anode, the Schottky barrier being situated between the substrate and a anode layer in the stack of layers.11-17-2011
20110278597METHOD OF PRODUCING A LAYER OF CAVITIES - A method of producing a layer of cavities in a structure comprises at least one substrate formed from a material that can be oxidized or nitrided, the method comprising the following steps: implanting ions into the substrate in order to form an implanted ion concentration zone at a predetermined mean depth; heat treating the implanted substrate to form a layer of cavities at the implanted ion concentration zone; and forming an insulating layer in the substrate by thermochemical treatment from one surface of the substrate, the insulating layer that is formed extending at least partially into the layer of cavities.11-17-2011
20110278596Epitaxial silicon carbide monocrystalline substrate and method of production of same - The present invention provides an epitaxial SiC monocrystalline substrate having a high quality epitaxial film suppressed in occurrence of step bunching in epitaxial growth using a substrate with an off angle of 6° or less and a method of production of the same, that is, an epitaxial silicon carbide monocrystalline substrate comprised of a silicon carbide monocrystalline substrate with an off angle of 6° or less on which a silicon carbide monocrystalline thin film is formed, the epitaxial silicon carbide monocrystalline substrate characterized in that the silicon carbide monocrystalline thin film has a surface with a surface roughness (Ra value) of 0.5 nm or less and a method of production of the same.11-17-2011
20110278594METHOD FOR MANUFACTURING SILICON CARBIDE SUBSTRATE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, SILICON CARBIDE SUBSTRATE, AND SEMICONDUCTOR DEVICE - A method for manufacturing a silicon carbide substrate includes the steps of: preparing a SiC substrate made of single-crystal silicon carbide; disposing a base substrate in a crucible so as to face a main surface of the SiC substrate; and forming a base layer made of silicon carbide in contact with the main surface of the SiC substrate by heating the base substrate in the crucible to fall within a range of temperature equal to or higher than a sublimation temperature of silicon carbide constituting the base substrate. The crucible has an inner wall at least a portion of which is provided with a coating layer made of silicon carbide.11-17-2011
20110278592SEMICONDUCTOR DEVICE - A semiconductor device which is designed based on RDR, suppresses the occurrence of a trouble at the boundary between an active region and a power wire and therearound and is small in size and highly integrated. The semiconductor device includes a first conductive impurity region for functional elements which is formed over the main surface of a semiconductor substrate and a second conductive impurity region for power potential to which power potential is applied in at least one standard cell. It also includes insulating layers which are formed over the main surface of the semiconductor substrate and have throughholes reaching the main surface of the semiconductor substrate, and a conductive layer for contact formed in the throughholes of the insulating layers. The impurity region for functional elements and the impurity region for power potential are electrically coupled to each other through the conductive layer for contact which is formed astride the impurity region for functional elements and the impurity region for power potential.11-17-2011
20110278590Semiconductor Devices Having Gates Including Oxidized Nickel and Related Methods of Fabricating the Same - Schottky barrier semiconductor devices are provided including a wide bandgap semiconductor layer and a gate on the wide bandgap semiconductor layer. The gate includes a metal layer on the wide bandgap semiconductor layer including a nickel oxide (NiO) layer. Related methods of fabricating devices are also provided herein.11-17-2011
20120181550COMPOUND SEMICONDUCTOR SUBSTRATE AND MANUFACTURING METHOD OF THE SAME - A compound semiconductor substrate includes a first substrate and a second substrate made of single crystal silicon carbide. In each of the first substrate and the second substrate, one surface is a (000-1) C-face and an opposite surface is a (0001) Si-face. The first substrate and the second substrate are bonded to each other in a state where the (0001) Si-face of the first substrate and the (0001) Si-face of the second substrate face each other, and the (000-1) C-face of the first substrate and the (000-1) C-face of the second substrate are exposed.07-19-2012
20130020585SILICON CARBIDE SUBSTRATE, SEMICONDUCTOR DEVICE, AND METHODS FOR MANUFACTURING THEM - A silicon carbide substrate capable of reducing on-resistance and improving yield of semiconductor devices is made of single-crystal silicon carbide, and sulfur atoms are present in one main surface at a ratio of not less than 60×1001-24-2013
20120138956COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A compound semiconductor device includes: a substrate; an electron transit layer formed over the substrate; an electron supply layer formed over the electron transit layer; and a buffer layer formed between the substrate and the electron transit layer and including Al06-07-2012
20110284874SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - In a cell region of a first major surface of a semiconductor substrate of a first conductivity type, a first well of a second conductivity type is in an upper surface. A diffusion region of a first conductivity type is in the upper surface in the first well. A first gate insulating film is on the first well, and a first gate electrode on the first gate insulating film. A second well of a second conductivity type is in the upper surface of the first major surface on a peripheral portion of the cell region. A second gate insulating film is on the second well, and a thick field oxide film is on the peripheral side than the second gate insulating film. A second gate electrode is sequentially on the second gate insulating film and the field oxide film and electrically connected to the first gate electrode. A first electrode is connected to the first, second well and the diffusion region. A second electrode is connected on a second major surface of the semiconductor substrate. A gate wiring is on the field oxide film, going around a periphery of the cell region, and electrically connected to the second gate electrode. The gate wiring is a silicide of a constituting substance of the second gate electrode.11-24-2011
20110284872METHOD FOR MANUFACTURING SILICON CARBIDE SUBSTRATE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, SILICON CARBIDE SUBSTRATE, AND SEMICONDUCTOR DEVICE - A method for manufacturing a silicon carbide substrate includes the steps of: preparing a base substrate made of silicon carbide, and a SiC substrate made of single-crystal silicon carbide; fabricating a stacked substrate by placing the SiC substrate on and in contact with a main surface of the base substrate; connecting the base substrate and the SiC substrate by heating the stacked substrate to allow the base substrate to have a temperature higher than that of the SiC substrate; and forming an epitaxial growth layer on an opposite main surface, to the SiC substrate, of the base substrate connected to the SiC substrate.11-24-2011
20110284875HIGH EFFICIENCY GROUP III NITRIDE LED WITH LENTICULAR SURFACE - A high efficiency Group III nitride light emitting diode is disclosed. The diode includes a substrate selected from the group consisting of semiconducting and conducting materials, a Group III nitride-based light emitting region on or above the substrate, and, a lenticular surface containing silicon carbide on or above the light emitting region, and extending to said light emitting region.11-24-2011
20110284876SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device provided with a silicon carbide semiconductor substrate, and an ohmic metal layer joined to one surface of the silicon carbide semiconductor substrate in an ohmic contact and composed of a metal material whose silicide formation free energy and carbide formation free energy respectively take negative values. The ohmic metal layer is composed of, for example, a metal material such as molybdenum, titanium, chromium, manganese, zirconium, tantalum, or tungsten.11-24-2011
20110284870METHOD FOR MAKING A SEMICONDUCTOR STRUCTURE WITH A BURIED GROUND PLANE - A method for making a semiconducting structure, including: a) forming, on a surface of a final semiconductor substrate, a semiconducting layer, doped with elements from columns III and V of the Periodic Table so as to form a ground plane, b) forming a dielectric layer, c) then assembling, by direct adhesion of the source substrate, on the final substrate, the layer forming the ground plane between the final substrate and the source substrate, the dielectric layer being between the source substrate and the ground plane, d) then thinning the source substrate, leaving, on the surface of the semiconductor structure, a film made from a semiconducting material.11-24-2011
20110284871SILICON CARBIDE SUBSTRATE, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SILICON CARBIDE SUBSTRATE - A silicon carbide substrate includes a base layer made of silicon carbide, an SiC layer made of single crystal silicon carbide, arranged on the base layer, and having a concentration of inevitable impurities lower than the concentration of inevitable impurities in the base layer, and a cover layer made of silicon carbide, formed on a main surface of the base layer at a side opposite to the SiC layer, and having a concentration of inevitable impurities lower than the concentration of inevitable impurities in the base layer.11-24-2011
20110127543SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate, a semiconductor element disposed on the main surface of the substrate and generating a heat of 200° C. or more, an enclosure surrounding the semiconductor element, and a liquid sealant containing a heat-resistant oil. The enclosure controls the flow of the sealant and seals the semiconductor element.06-02-2011
20120007103SILICON CARBIDE BIPOLAR JUNCTION TRANSISTOR - The present disclosure relates to a silicon carbide (SiC) bipolar junction transistor (BJT), where the surface region between the emitter and base contacts (01-12-2012
20100006860METHOD FOR IMPROVING INVERSION LAYER MOBILITY IN A SILICON CARBIDE MOSFET - A method of manufacturing a semiconductor device based on a SiC substrate (01-14-2010
20100006858Semiconductor-on-diamond devices and associated methods - Semiconductor devices and methods for making such devices are provided. One such method may include forming an epitaxial layer of single crystal SiC on a single crystal Si growth substrate, forming an epitaxial diamond layer on the layer of SiC, forming a Si layer on the diamond layer, bonding a SiO01-14-2010
20110127544GROUP III NITRIDE TEMPLATES AND RELATED HETEROSTRUCTURES, DEVICES, AND METHODS FOR MAKING THEM - A templated substate includes a base layer, and a template layer disposed on the base layer and having a composition including a single-crystal Group Ill nitride. The template layer includes a continuous sublayer on the base layer and a nanocolumnar sublayer on the first sublayer, wherein the nanocolumnar sublayer includes a plurality of nano-scale columns.06-02-2011
20110018005SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device of the present invention includes a semiconductor layer composed of SiC, a metal layer directly bonded to one face of the semiconductor layer, and a high carbon concentration layer formed on a surface layer portion at one side of the semiconductor layer and containing more highly concentrated carbon than a surface layer portion of the other side. Further, a manufacturing method of a semiconductor device of the present invention includes the steps of forming, on a surface layer portion at one face side of a semiconductor layer composed of SiC, a high carbon concentration layer containing more highly concentrated carbon than a surface layer portion at the other face side by heat treatment and directly bonding metal to the high carbon concentration layer.01-27-2011
20110297962SCHOTTKY DIODE WITH DIAMOND ROD AND METHOD FOR MANUFACTURING THE SAME - The present invention relates to a Schottky diode with a diamond rod, which comprises: a substrate with a gate layer formed thereon; a patterned insulating layer disposed on the gate layer, wherein the patterned insulating layer comprises a first contact region and a second contact region; a diamond rod disposed on the patterned insulating layer, wherein a first end of the diamond rod connects to the first contact region, and a second end of the diamond rod connects to the second contact region; a first electrode corresponding to the first contact region of the patterned insulating layer, and covering the first end of the diamond rod; and a second electrode corresponding to the second contact region of the patterned insulating layer, and covering the second end of the diamond rod, and a method for manufacturing the same.12-08-2011
20100264427Bipolar Junction Transistor Guard Ring Structures and Method of Fabricating Thereof - Semiconductor devices with multiple floating guard ring edge termination structures and methods of fabricating same are disclosed. A method for fabricating guard rings in a semiconductor device that includes forming a mesa structure on a semiconductor layer stack, the semiconductor stack including two or more layers of semiconductor materials including a first layer and a second layer, said second layer being on top of said first layer, forming trenches for guard rings in the first layer outside a periphery of said mesa, and forming guard rings in the trenches. The top surfaces of said guard rings have a lower elevation than a top surface of said first layer.10-21-2010
20110169015BIPOLAR SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - Disclosed is a bipolar semiconductor device which is capable of reducing the surface state density of a bipolar transistor and increasing the current gain of the transistor, thereby improving the transistor performance. A bipolar semiconductor device (07-14-2011
20110068350Diamond semiconductor devices and associated methods - Semiconductor devices and methods for making such devices are provided. One such method may include forming a transparent diamond layer having a SiC layer coupled thereto, where the SiC layer has a crystal structure that is substantially epitaxially matched to the transparent diamond layer, forming epitaxially a plurality of semiconductor layers on the SiC layer, and coupling a diamond substrate to at least one of the plurality of semiconductor layers such that the diamond support is oriented parallel to the transparent diamond layer. In one aspect such a method may further include electrically coupling at least one of a p-type electrode or an n-type electrode to at least one of the plurality of semiconductor layers.03-24-2011
20100090228BORON ALUMINUM NITRIDE DIAMOND HETEROSTRUCTURE - A heterostructure having a heterojunction comprising: a diamond layer; and a boron aluminum nitride (B04-15-2010
20120286290SEMICONDUCTOR ELEMENT AND SEMICONDUCTOR DEVICE - A semiconductor element according to the present invention includes: a semiconductor substrate of a first conductivity type; a first silicon carbide semiconductor layer of the first conductivity type on the semiconductor substrate; a body region of a second conductivity type defined in the first silicon carbide semiconductor layer; an impurity region of the first conductivity type defined in the body region; a second silicon carbide semiconductor layer of the first conductivity type on the first silicon carbide semiconductor layer; a gate insulating film on the second silicon carbide semiconductor layer; a gate electrode on the gate insulating film; a first ohmic electrode connected to the impurity region; and a second ohmic electrode on the back surface of the semiconductor substrate. The body region includes first and second body regions. The average impurity concentration of the first body region is twice or more as high as that of the second body region. And the bottom of the impurity region is deeper than that of the first body region.11-15-2012
20110291110SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The silicon carbide semiconductor device includes a substrate, a drift layer, a base region, a source region, a trench, a gate insulating layer, a gate electrode, a source electrode, a drain electrode, and a deep layer. The deep layer is disposed under the base region and is located to a depth deeper than the trench. The deep layer is divided into a plurality of portions in a direction that crosses a longitudinal direction of the trench. The portions include a group of portions disposed at positions corresponding to the trench and arranged at equal intervals in the longitudinal direction of the trench. The group of portions surrounds corners of a bottom of the trench.12-01-2011
20110291112NORMALLY-OFF INTEGRATED JFET POWER SWITCHES IN WIDE BANDGAP SEMICONDUCTORS AND METHODS OF MAKING - Wide bandgap semiconductor devices including normally-off VJFET integrated power switches are described. The power switches can be implemented monolithically or hybridly, and may be integrated with a control circuit built in a single- or multi-chip wide bandgap power semiconductor module. The devices can be used in high-power, temperature-tolerant and radiation-resistant electronics components. Methods of making the devices are also described.12-01-2011
20110291111SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A chip size package includes: a radio frequency substrate having a radio frequency semiconductor circuit formed on a principal surface; a semiconductor cover substrate arranged at a position facing the principal surface of the radio frequency substrate; and a joining frame arranged in a manner such as to surround the radio frequency semiconductor circuit between the radio frequency substrate and the semiconductor cover substrate, the joining frame joining the radio frequency substrate and the semiconductor cover substrate, wherein: the radio frequency substrate further has a wire formed on a surface opposite to the principal surface; and the radio frequency semiconductor circuit and the wire are electrically connected to each other through a via hole penetrating through the radio frequency substrate in a thickness direction thereof.12-01-2011
20110291106POWER SEMICONDUCTOR DEVICE - Provided is a power semiconductor device including: a power semiconductor element; a metal block as a first metal block that is connected to the power semiconductor element through an upper surface electrode pattern as a first upper surface electrode pattern selectively formed on an upper surface of the power semiconductor element; and a mold resin filled so as to cover the power semiconductor element and the metal block, wherein an upper surface of the metal block is exposed from a surface of the mold resin.12-01-2011
20110291109POLARIZATION ENHANCED AVALANCHE PHOTODETECTOR AND METHOD THEREOF - An avalanche photodetector comprising a multiplication layer formed of a first material having a first polarization; the multiplication layer having a first electric field upon application of a bias voltage; an absorption layer formed of a second material having a second polarization forming an interface with the multiplication layer; the absorption layer having a second electric field upon application of the bias voltage, the second electric field being less than the first electric field or substantially zero, carriers created by light absorbed in the absorption layer being multiplied in the multiplication layer due to the first electric field; the absorption layer having a second polarization which is greater or less than the first polarization to thereby create an interface charge; the interface charge being positive when the first material predominately multiplies holes, the interface charge being negative when the first material predominately multiplies electrons, the change in electric field at the interface occurring abruptly at the atomic level; the interface charge creating electric field discontinuity causing first electric field to attain the breakdown field in the multiplication region and the second electric field to be low or zero in the absorption layer to thereby eliminate the need for a doped charge layer and the associated thickness of the doped charge layer required to transition from the low field to the high field. Also claimed is a method of making.12-01-2011
20110291107SELF-ALIGNED SEMICONDUCTOR DEVICES WITH REDUCED GATE-SOURCE LEAKAGE UNDER REVERSE BIAS AND METHODS OF MAKING - A vertical junction field effect transistor (VJFET) having a self-aligned pin, a p+/n/n+ or a p+/p/n+ gate-source junction is described. The device gate can be self-aligned to within 0.5 μm to the source in order to maintain good high voltage performance (i.e. low DIBL) while reducing gate-source junction leakage under reverse bias. The device can be a wide-bandgap semiconductor device such as a SiC vertical channel junction field effect. Methods of making the device are also described.12-01-2011
20110291105SEMICONDUCTOR MODULE AND METHOD OF MANUFACTURING THE SAME - A semiconductor module according to the present invention includes: an insulating substrate (12-01-2011
20110291104SMOOTHING METHOD FOR SEMICONDUCTOR MATERIAL AND WAFERS PRODUCED BY SAME - A smoothing method for semiconductor material and semiconductor wafers produced by the method are disclosed. Semiconductor wafers with reduced atomic steps, as well with reduced scratches and subsurface defects can be produced. Such wafers feature an improved growth surface that can provide for the growth of an epilayer with reduced macroscopic defects and defect densities. A method of smoothing the surface of a wafer according to example embodiments of the invention includes planarizing the surface of a semiconductor wafer, and then oxidizing the wafer to achieve a specified thickness of oxide on the surface of the wafer. The oxide can then be stripped from the surface of the semiconductor wafer.12-01-2011
20090289264Silicon carbide semiconductor device and method of manufacturing the same - An SiC semiconductor device includes a substrate, a drift layer disposed on a first surface of the substrate, a base region disposed above the drift layer, a source region disposed above the base region, a trench penetrating the source region and the base region to the drift layer, a gate insulating layer disposed on a surface of the trench, a gate electrode disposed on a surface of the gate insulating layer, a first electrode electrically coupled with the source region and the base region, a second electrode disposed on the second surface of the substrate, and a second conductivity-type layer disposed at a portion of the base region located under the source region. The second conductivity-type layer has the second conductivity type and has an impurity concentration higher than the base region.11-26-2009
20110169014COMPOUND SEMICONDUCTOR DEVICE - A compound semiconductor device includes: an electron transit layer made of GaN; a channel layer made of AlGaN; a source electrode, a gate electrode and a drain electrode that are provided on the channel layer; a cap layer that is provided at least between the source electrode and the gate electrode and between the gate electrode and the drain electrode and is made of GaN; a recess portion that is provided in the cap layer between the gate electrode and the drain electrode; and a thick portion that is provided in the cap layer between the recess portion and the drain electrode and has a thickness larger than the recess portion.07-14-2011
20110169013GROWING POLYGONAL CARBON FROM PHOTORESIST - A method of growing polygonal carbon from photoresist and resulting structures are disclosed. Embodiments of the invention provide a way to produce polygonal carbon, such as graphene, by energizing semiconductor photoresist. The polygonal carbon can then be used for conductive paths in a finished semiconductor device, to replace the channel layers in MOSFET devices on a silicon carbide base, or any other purpose for which graphene or graphene-like carbon material formed on a substrate is suited. In some embodiments, the photoresist layer forms both the polygonal carbon layer and an amorphous carbon layer over the polygonal carbon layer, and the amorphous carbon layer is removed to leave the polygonal carbon on the substrate.07-14-2011
20120097979STRUCTURALLY ROBUST POWER SWITCHING ASSEMBLY - A structurally robust power switching assembly, that has a first rigid structural unit, defining a first unit major surface that is patterned to define a plurality of mutually electrically isolated, electrically conductive paths. Also, a similar, second rigid structural unit is spaced apart from the first unit major surface. Finally, a transistor is interposed between and electrically connected to the first unit major surface and the second unit major surface.04-26-2012
20120097978PHOTO-SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A photo-semiconductor device comprises a photoconductive semiconductor film provided with electrodes and formed on a second substrate, the semiconductor film being formed by epitaxial growth on a first semiconductor substrate different from the second substrate, the second substrate being also provided with electrodes, the electrodes of the second substrate and the electrodes of the photoconductive semiconductor film being held in contact with each other.04-26-2012
20120097977SEMICONDUCTOR DEVICE AND A METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor device of the present invention has a (110)-plane-orientation silicon substrate and a p channel type field effect transistor formed in a pMIS region. The p channel type field effect transistor includes a gate electrode disposed via a gate insulation film, and source/drain regions disposed inside a trench disposed in the silicon substrate on the opposite sides of the gate electrode, and including SiGe larger in lattice constant than Si. The trench has a (100)-plane-orientation first inclined surface, and a (100)-plane-orientation second inclined surface crossing the first inclined surface at a sidewall part situated on the gate electrode side. With the configuration, the angle formed between the surface (110) plane and the (100) plane of the substrate is 45°, so that the first inclined surface is formed at a relatively acute angle. This can effectively apply a compressive strain to a channel region of the p channel type MISFET.04-26-2012
20120097976LIGHT EMITTING DIODE CHIP AND METHOD FOR MANUFACTURING THE SAME - A light emitting diode chip includes an electrically conductive substrate, a reflecting layer disposed on the substrate, a semiconductor structure formed on the reflecting layer, an electrode disposed on the semiconductor structure, and a plurality of slots extending through the semiconductor structure. The semiconductor structure includes a P-type semiconductor layer formed on the reflecting layer, a light-emitting layer formed on the P-type semiconductor layer, and an N-type semiconductor layer formed on the light-emitting layer. A current diffusing region is defined in the semiconductor structure and around the electrode. The slots are located outside the current diffusing region.04-26-2012
20120097975Nitride-Based Semiconductor Substrates Having Hollow Member Pattern And Methods Of Fabricating The Same - A nitride-based semiconductor substrate may includes a plurality of hollow member patterns arranged on a substrate, a nitride-based seed layer formed on the substrate between the plurality of hollow member patterns, and a nitride-based buffer layer on the nitride-based seed layer so as to cover the plurality of hollow member patterns, wherein the plurality of hollow member patterns contact the substrate in a first direction and both ends of each of the plurality of hollow member patterns are open in the first direction.04-26-2012
20120097974POWER SEMICONDUCTOR DEVICE - A method and apparatus for achieving high current gain, and low on-resistance, from a Bipolar Junction Transistor (BJT) in high temperature and high power applications are disclosed. In some embodiments, a thin doped delta layer is inserted at the base emitter junction but inside the base layer. In addition, in some embodiments, a surface recombination layer is inserted between the emitter-base regions of the device. In some embodiments, use of an ion implantation step is avoided to achieve simplicity and low cost of manufacture.04-26-2012
20100078654SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device according to one embodiment includes: a first transistor comprising a first gate electrode formed on a semiconductor substrate via a first gate insulating film, a first channel region formed in the semiconductor substrate under the first gate insulating film, and first epitaxial crystal layers formed on both sides of the first channel region in the semiconductor substrate, the first epitaxial crystal layers comprising a first crystal; and a second transistor comprising a second gate electrode formed on the semiconductor substrate via a second gate insulating film, a second channel region formed in the semiconductor substrate under the second gate insulating film, second epitaxial crystal layers formed on both sides of the second channel region in the semiconductor substrate, and third epitaxial crystal layers formed on the second epitaxial crystal layers, the second epitaxial crystal layers comprising a second crystal, the third epitaxial crystal layers comprising the first crystal, the second transistor having a conductivity type different from that of the first transistor.04-01-2010
20090212301Double Guard Ring Edge Termination for Silicon Carbide Devices and Methods of Fabricating Silicon Carbide Devices Incorporating Same - Edge termination structures for semiconductor devices are provided including a plurality of spaced apart concentric floating guard rings in a semiconductor layer that at least partially surround a semiconductor junction. The spaced apart concentric floating guard rings have a highly doped portion and a lightly doped portion. Related methods of fabricating devices are also provided herein.08-27-2009
20090184328ELECTRICAL SWITCHING DEVICE AND METHOD OF EMBEDDING CATALYTIC MATERIAL IN A DIAMOND SUBSTRATE - An electrical switching device (07-23-2009
20120025208METHOD FOR MANUFACTURING SILICON CARBIDE SUBSTRATE AND SILICON CARBIDE SUBSTRATE - A method for manufacturing a silicon carbide substrate includes the steps of: preparing a base substrate made of silicon carbide and a SiC substrate made of single-crystal silicon carbide; forming a Si film made of silicon on a main surface of the base substrate; fabricating a stacked substrate by placing the SiC substrate on and in contact with the Si film; and connecting the base substrate and the SiC substrate to each other by heating the stacked substrate to convert, into silicon carbide, at least a region making contact with the base substrate and a region making contact with the SiC substrate in the Si film.02-02-2012
20120025207PROCESS FOR DIVIDING WAFER INTO INDIVIDUAL CHIPS AND SEMICONDUCTOR CHIPS - A process to divide a wafer into individual chips is disclosed. The process (1) etches semiconductor layers for an active device to form two grooves putting the virtual cut line therebetween, where the semiconductor wafer is to be divided along the virtual cut line; (2) etches the substrate in a region including the virtual cut line but offset from the groove from the back surface thereof so as to expose the semiconductor layers in the primary surface; and (3) etches the semiconductor layer exposed in step (2).02-02-2012
20120025205SEMICONDUCTOR DEVICE - A semiconductor device includes an AlGaN layer that is provided on a SiC substrate and has an acceptor concentration equal to or higher than a donor concentration, a GaN layer provided on the AlGaN layer, and an electron supply layer that is provided on the GaN layer and has a band gap greater than that of GaN.02-02-2012
20120025204SEMICONDUCTOR DEVICE HAVING Si-SUBSTRATE AND PROCESS TO FORM THE SAME - A semiconductor device and a process to form the semiconductor device are disclosed. The semiconductor device includes a Si substrate, active devices primarily made of nitride based compound semiconductor material, and passive devices. The Si substrate includes a via hole piercing from the back surface to the primary surface of the Si substrate. The active device is mounted on the primary surface so as to cover at least a portion of the via hole. The metal layer cover the whole back surface, inner surfaces of the via hole, and the back surface of the active device exposed in the via hole.02-02-2012
20090315039Trench MOS type silicon carbide semiconductor device - A trench MOS type SiC semiconductor device includes a first conductivity semiconductor substrate, a first conductivity drift layer on the substrate, a second conductivity base layer on the drift layer, a first conductivity source layer on the base layer, a stripe shaped trench reaching from the surface of the source layer to the drift layer and having a gate electrode via a gate oxide film, a second conductivity layer on the bottom of the trench, and a second conductivity type region thereon on across-the-width side walls of at least one end of the trench, electrically coupling the second conductivity layer with the base layer. The device allows a low on-resistance without newly forming an electrode connected to the second conductivity layer even in the case of a device in which the second conductivity layer has to be grounded.12-24-2009
20090146154Transistor with A-Face Conductive Channel and Trench Protecting Well Region - A transistor structure optimizes current along the A-face of a silicon carbide body to form an AMOSFET that minimizes the JFET effect in the drift region during forward conduction in the on-state. The AMOSFET further shows high voltage blocking ability due to the addition of a highly doped well region that protects the gate corner region in a trench-gated device. The AMOSFET uses the A-face conduction along a trench sidewall in addition to a buried channel layer extending across portions of the semiconductor mesas defining the trench. A doped well extends from at least one of the mesas to a depth within the current spreading layer that is greater than the depth of the trench. A current spreading layer extends between the semiconductor mesas beneath the bottom of the trench to reduce junction resistance in the on-state. A buffer layer between the trench and the deep well further provides protection from field crowding at the trench corner.06-11-2009
20120228631SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device of an embodiment includes: a silicon carbide substrate including first and second principal surfaces; a first conductive-type first silicon carbide layer provided on the first principal surface of the silicon carbide substrate; a second conductive-type first silicon carbide region formed on a surface of the first silicon carbide layer; a first conductive-type second silicon carbide region formed on a surface of the first silicon carbide region; a second conductive-type third silicon carbide region formed on the surface of the first silicon carbide region; a gate insulating film continuously formed on the surfaces of the first silicon carbide layer, the first silicon carbide region, and the second silicon carbide region; a first electrode formed of silicon carbide formed on the gate insulating film; a second electrode formed on the first electrode; an interlayer insulating film for covering the first and second electrodes; a third electrode electrically connected to the second silicon carbide region and the third silicon carbide region; and a fourth electrode formed on the second principal surface of the silicon carbide substrate.09-13-2012
20110260174GaN BASED POWER DEVICES WITH INTEGRATED PROTECTION DEVICES: STRUCTURES AND METHODS - Exemplary embodiments provide structures and methods for power devices with integrated clamp structures. The integration of clamp structures can protect the power device, e.g., from electrical overstress (EOS). In one embodiment, active devices can be formed over a substrate, while a clamp structure can be integrated outside the active regions of the power device, for example, under the active regions and/or inside the substrate. Integrating clamp structure outside active regions of power devices can maximize the active area for a given die size and improve robustness of the clamped device since the current will spread in the substrate by this integration.10-27-2011
20080265261PROCESS FOR TRANSFERRING A LAYER OF STRAINED SEMICONDUCTOR MATERIAL - Semiconductor wafers having a thin layer of strained semiconductor material. These structures include a substrate; an oxide layer upon the substrate; a silicon carbide (SiC) layer upon the oxide layer, and a strained layer of a semiconductor material in a strained state upon the silicon carbide layer, or a matching layer upon the donor substrate that is made from a material that induces strain in subsequent epitaxially grown layers thereon; a strained layer of a semiconductor material of defined thickness in a strained state; and an insulating or semi-insulating layer upon the strained layer in a thickness that retains the strained state of the strained layer. The insulating or semi-insulating layers are made of silicon carbide or oxides and act to retain strain in the strained layer.10-30-2008
20120292640Solid State Device - A solid state energy conversion device and method of making is disclosed for converting energy between electromagnetic and electrical energy. The solid state energy conversion device comprises a wide bandgap semiconductor material having a first doped region. A thermal energy beam is directed onto the first doped region of the wide bandgap semiconductor material in the presence of a doping gas for converting a portion of the first doped region into a second doped region in the wide bandgap semiconductor material. In one embodiment, the solid state energy conversion device operates as a light emitting device. In another embodiment, the solid state energy conversion device operates as a photovoltaic device.11-22-2012
20100320477PROCESS FOR PRODUCING SILICON CARBIDE CRYSTALS HAVING INCREASED MINORITY CARRIER LIFETIMES - A process is described for producing silicon carbide crystals having increased minority carrier lifetimes. The process includes the steps of heating and slowly cooling a silicon carbide crystal having a first concentration of minority carrier recombination centers such that the resultant concentration of minority carrier recombination centers is lower than the first concentration.12-23-2010
20100078652DIAMOND ELECTRONIC DEVICES INCLUDING A SURFACE AND METHODS FOR THEIR MANUFACTURE - The present invention relates to a diamond electronic device comprising a functional surface formed by a planar surface of a single crystal diamond, the planar surface of the single crystal diamond having an Rq of less than 10 nm and at least one of the following characteristics: (a) the surface has not been mechanically processed since formation by synthesis; (b) the surface is an etched surface; (c) a density of dislocations in the diamond breaking the surface is less than 400 cm″2 measured over an area greater than 0.014 cm2; (d) the surface has an Rq less than 1 nm; (e) the surface has regions with a layer of charge carriers immediately below it, such that the regions of the surface are normally termed conductive, such as a hydrogen terminated {100} diamond surface region; (f) the surface has regions with no layer of charge carriers immediately below it, such that these regions of the surface are normally termed insulating, such as an oxygen terminated {100} diamond surface; and (g) the surface has one or more regions of metallization providing electrical contact to the diamond surface beneath these regions.04-01-2010
20100084663Silicon Carbide Zener Diode - A silicon carbide Zener diode is a bipolar semiconductor device that has a mesa structure and includes a silicon carbide single crystal substrate of a first conductivity type, formed thereon, a silicon carbide conductive layer of a first conductivity type, and a silicon carbide conductive layer of a second conductivity type formed on the silicon carbide conductive layer of a first conductivity type, wherein a depletion layer that is formed under reverse bias at a junction between the silicon carbide conductive layer of a first conductivity type and the silicon carbide conductive layer of a second conductivity type does not reach a mesa corner formed in the silicon carbide conductive layer of a first conductivity type.04-08-2010
20110140126HEAT CONDUCTION FOR CHIP STACKS AND 3-D CIRCUITS - A semiconductor device assembly and method can include a single semiconductor layer or stacked semiconductor layers, for example semiconductor wafers or wafer sections (semiconductor dice). On each semiconductor layer, a diamond layer formed therethrough can aid in the routing and dissipation of heat. The diamond layer can include a first portion on the back of the semiconductor layer, and one or more second portions which extend vertically into the semiconductor layer, for example completely through the semiconductor layer. Thermal contact can then be made to the diamond layer to conduct heat away from the one or more semiconductor layers. A conductive via can be formed through the diamond layers to provide signal routing and heat dissipation capabilities.06-16-2011
20090267082Semiconductor device and manufacturing method of the same - A semiconductor device includes: a semiconductor element having a first surface and a second surface; a first electrode disposed on the first surface of the element; a second electrode disposed on the second surface of the element; and an insulation film covers a part of the first electrode, the first surface of the element and a part of a sidewall of the element. The above semiconductor device has small dimensions and a high breakdown voltage.10-29-2009
20090267081SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATION THEREOF - A semiconductor device includes a substrate formed of a single crystal. a silicon carbide layer disposed on a surface of the single crystal substrate and an intermediate layer disposed on a surface of the silicon carbide layer and formed of a Group III nitride semiconductor, wherein the silicon carbide layer is formed of a cubic crystal stoichiometrically containing silicon copiously and the surface thereof has a (3×3) reconstruction structure. The semiconductor device is fabricated by a method including a first step of blowing a hydrocarbon gas on the surface of the substrate, thereby inducing adsorption of hydrocarbon thereon, a second step of heating the substrate having adsorbed the hydrocarbon to a temperature exceeding a temperature used for the adsorption of the hydrocarbon while irradiating the surface of the substrate with electrons and consequently giving rise to a silicon carbide layer formed of a cubic crystal stoichiometrically containing silicon copiously and provided with a surface having a (3×3) reconstruction structure and a third step of supplying a gaseous raw material containing nitrogen and a gaseous raw material containing a Group III element to the surface of the silicon carbide layer and consequently giving rise to the intermediate layer formed of the Group III nitride semiconductor.10-29-2009
20100090227METHOD FOR THE FORMATION OF A GATE OXIDE ON A SIC SUBSTRATE AND SIC SUBSTRATES AND DEVICES PREPARED THEREBY - Methods are provided for improving inversion layer mobility and providing low defect density in a semiconductor device based upon a silicon carbide (SiC) substrate. More specifically, embodiments of the present method provide for the formation of a gate oxide on a silicon carbide substrate comprising oxidizing the substrate with a gaseous mixture comprising oxygen at a temperature of at least about 1300° C. Semiconductor devices, such as MOSFETS, based upon a substrate treated according to the present method are expected to have inversion layer mobilities of at least about 12 cm04-15-2010
20110147767SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - There is provided a semiconductor device including an ohmic junction layer which is excellent in surface flatness and uniformity of composition in an interface with a semiconductor substrate and thus can give a sufficiently high adhesiveness with a Schottky junction layer. Such a semiconductor device includes an n type SiC semiconductor substrate (06-23-2011
20100078650SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate made of silicon carbide and having a surface, a normal vector for the surface having an off angle with respect to a <0001> direction or a <000-1> direction, a semiconductor layer of a first conductivity type formed on the semiconductor substrate, a first semiconductor region of a second conductivity type formed in a surface region of the semiconductor layer, a source region of a first conductivity type formed in a surface region of the first semiconductor region, a second semiconductor region of a second conductivity type formed in the surface region of the semiconductor layer, contacting the first semiconductor region, and having a bottom surface lower than a bottom surface of the first semiconductor region, wherein at least one end of the bottom surface of the second semiconductor region is perpendicular to an off angle direction.04-01-2010
20090173949SILICON CARBIDE MOS FIELD EFFECT TRANSISTOR WITH BUILT-IN SCHOTTKY DIODE AND METHOD FOR MANUFACTURING SUCH TRANSISTOR - This invention has a cell incorporating a built-in Schottky diode region disposed in at least part of an elementary cell that constitutes an SiC vertical MOSFET provided in a low-density p-type deposit film with a channel region and a base region inverted to an n-type by ion implantation. This built-in Schottky diode region has built therein a Schottky diode of low on-resistance that is formed of a second deficient pan disposed in a high-density gate layer, a second n-type base layer penetrating a low-density p-type deposit layer formed thereon, reaching an n-type drift layer of the second deficient part and attaining its own formation in consequence of inversion of the p-type deposit layer into an n-type by the ion implantation of an n-type impurity from the surface, and a source electrode connected in the manner of forming a Schottky barrier to the surface-exposed part of the second n-type base layer.07-09-2009
20110062450Silicon carbide semiconductor device - A silicon carbide semiconductor device comprising a region of germanium and a region of crystalline or polycrystalline silicon carbide. The germanium region and the silicon carbide region are configured to form a germanium/silicon carbide heterojunction.03-17-2011
20090206347Semiconductor Device - A unipolar semiconductor device having a drift layer (08-20-2009
20110198613SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - The leakage current generated in a pn junction region between a gate and a source is reduced in a junction FET using a silicon carbide substrate. In a trench junction FET using a silicon carbide substrate, nitrogen is introduced into a sidewall and a bottom surface of a trench, thereby forming an n type layer and an n08-18-2011
20110198617ELECTRODE, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE - Disclosed is a semiconductor device comprising a p-type SiC semiconductor and an ohmic electrode having an Ni/Al laminated structure provided on the p-type SiC semiconductor. The semiconductor device simultaneously has improved contact resistance and surface roughness in the ohmic electrode. The semiconductor device comprises an ohmic electrode (08-18-2011
20110198616SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - Each unit cell includes: a drift layer 08-18-2011
20090278137SEMICONDUCTOR DEVICES WITH NON-PUNCH-THROUGH SEMICONDUCTOR CHANNELS HAVING ENHANCED CONDUCTION AND METHODS OF MAKING - Semiconductor devices are described wherein current flow in the device is confined between the rectifying junctions (e.g., p-n junctions or metal-semiconductor junctions). The device provides non-punch-through behavior and enhanced current conduction capability. The devices can be power semiconductor devices as such as Junction Field-Effect Transistors (VJFETs), Static Induction Transistors (SITs), Junction Field Effect Thyristors, or JFET current limiters. The devices can be made in wide bandgap semiconductors such as silicon carbide (SiC). According to some embodiments, the device can be a normally-off SiC vertical junction field effect transistor. Methods of making the devices and circuits comprising the devices are also described.11-12-2009
20090045413Silicon Carbide Bipolar Semiconductor Device - In a SiC bipolar semiconductor device with a mesa structure having a SiC drift layer of a first conductive type and a SiC carrier injection layer of a second conductive type that are SiC epitaxial layers grown from a surface of a SiC single crystal substrate, the formation of stacking faults and the expansion of the area thereof are prevented and thereby the increase in forward voltage is prevented. Further, a characteristic of withstand voltage in a reverse biasing is improved. An forward-operation degradation preventing layer is formed on a mesa wall or on a mesa wall and a mesa periphery to separate spatially the surface of the mesa wall from a pn-junction interface. In one embodiment, the forward-operation degradation preventing layer is composed of a silicon carbide low resistance layer of a second conductive type that is equipotential during the application of a reverse voltage. In another embodiment, the forward-operation degradation preventing layer is composed of a silicon carbide conductive layer of a second conductive type, and a metal layer that is equipotential during the application of a reverse voltage is formed on a surface of the silicon carbide conductive layer. In still another embodiment, the forward-operation degradation preventing layer is composed of a high resistance amorphous layer.02-19-2009
20090045412Method for production of silicon carbide layer, gallium nitride semiconductor device and silicon substrate - A method for producing a silicon carbide layer on a surface of a silicon substrate includes the step of irradiating the surface of the silicon substrate heated in a high vacuum at a temperature in a range of from 500° C. to 1050° C. with a hydrocarbon-based gas as well as an electron beam to form a cubic silicon carbide layer on the silicon substrate surface.02-19-2009
20090090920Silicon carbide semiconductor device - A silicon carbide semiconductor device is disclosed. The silicon carbide semiconductor device includes a substrate; a drift layer having a first conductivity type and located on a first surface of the substrate; and a vertical type semiconductor element. The vertical type semiconductor element includes: an impurity layer having a second conductivity type, and located in a surface portion of the drift layer; and a first conductivity type region located in the drift layer, spaced away from the impurity layer, located closer to the substrate than the impurity layer, and having an impurity concentration higher than the drift layer.04-09-2009
20090090919Semiconductor device and method of producing the same - A semiconductor device includes a silicon carbide substrate having a channel region formed on a surface thereof; a silicon layer formed on the channel region; a gate insulation film formed on the silicon layer; and a gate electrode formed on the gate insulation film. A method of producing a semiconductor device includes the steps of: forming a silicon layer on a surface of a silicon carbide substrate; forming a gate insulation film on the silicon layer to form a laminated structure of the silicon layer and the gate insulation film; and forming a gate electrode on the gate insulation film.04-09-2009
20110169016MOSFET AND METHOD FOR MANUFACTURING MOSFET - A MOSFET includes: a silicon carbide (SiC) substrate having a main surface having an off angle of not less than 50° and not more than 65° relative to a {0001} plane; a semiconductor layer formed on the main surface of the SiC substrate; and an insulating film formed in contact with a surface of the semiconductor layer. The MOSFET has a sub-threshold slope of not more than 0.4 V/Decade.07-14-2011
20080210950Diamond-like carbon electronic devices and methods of manufacture - Materials, devices, and methods for enhancing performance of electronic devices such as solar cells, fuels cells, LEDs, thermoelectric conversion devices, and other electronic devices are disclosed and described. A diamond-like carbon electronic device can include a conductive diamond-like carbon cathode having specified carbon, hydrogen and sp09-04-2008
20090272984Silicon Carbide on Diamond Substrates and Related Devices and Methods - A high power, wide-bandgap device is disclosed that exhibits reduced junction temperature and higher power density during operation and improved reliability at a rated power density. The device includes a diamond substrate for providing a heat sink with a thermal conductivity greater than silicon carbide, a single crystal silicon carbide layer on the diamond substrate for providing a supporting crystal lattice match for wide-bandgap material structures that is better than the crystal lattice match of diamond, and a Group III nitride heterostructure on the single crystal silicon carbide layer for providing device characteristics.11-05-2009
20090272983Silicon carbide semiconductor device and method for manufacturing the same - A silicon carbide semiconductor device includes: a semiconductor substrate having a silicon carbide substrate, a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer; a trench penetrating the second and the third semiconductor layers to reach the first semiconductor layer; a channel layer on a sidewall and a bottom of the trench; an oxide film on the channel layer; a gate electrode on the oxide film; a first electrode connecting to the third semiconductor layer; and a second electrode connecting to the silicon carbide substrate. A position of a boundary between the first semiconductor layer and the second semiconductor layer is disposed lower than an utmost lowest position of the oxide film.11-05-2009
20090272982TRENCH GATE TYPE SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING THE SAME - A method of producing a trench gate type MOSFET is provided in which each intersection trench is formed as a two-stage trench structure. A gate trench is backfilled with a mask material and the mask material is then patterned to form a mask used for forming each intersection trench. The intersection trench intersecting the gate trench is provided so as to be deeper than the gate trench. A Schottky electrode is provided in the bottom of each intersection trench 11-05-2009
20110198615High-Sensitivity, High-Resolution Detector Devices and Arrays - Avalanche amplification structures including electrodes, an avalanche region, a quantifier, an integrator, a governor, and a substrate arranged to detect a weak signal composed of as few as several electrons are presented. Quantifier regulates the avalanche process. Integrator accumulates a signal charge. Governor drains the integrator and controls the quantifier. Avalanche amplifying structures include: normal quantifier, reverse bias designs; normal quantifier, normal bias designs; lateral quantifier, normal bias designs; changeable quantifier, normal bias, adjusting electrode designs; normal quantifier, normal bias, adjusting electrode designs; and lateral quantifier, normal bias, annular integrator designs. Avalanche amplification structures are likewise arranged to provide arrays of multi-channel devices. The described invention is expected to be used within photodetectors, electron amplifiers, chemical and biological sensors, and chemical and biological chips with lab-on-a-chip applications. Structures have immediately applicability to devices critical to homeland defense.08-18-2011
20090289262JUNCTION BARRIER SCHOTTKY DIODES WITH CURRENT SURGE CAPABILITY - An electronic device includes a silicon carbide drift region having a first conductivity type, a Schottky contact on the drift region, and a plurality of junction barrier Schottky (JBS) regions at a surface of the drift region adjacent the Schottky contact. The JBS regions have a second conductivity type opposite the first conductivity type and have a first spacing between adjacent ones of the JBS regions. The device further includes a plurality of surge protection subregions having the second conductivity type. Each of the surge protection subregions has a second spacing between adjacent ones of the surge protection subregions that is less than the first spacing.11-26-2009
20090289263System and Method for Emitter Layer Shaping - Embodiments of an LED disclosed has an emitter layer shaped to a controlled depth or height relative to a substrate of the LED to maximize the light output of the LED and to achieve a desired intensity distribution. In some embodiments, the exit face of the LED may be selected to conserve radiance. In some embodiments, shaping the entire LED, including the substrate and sidewalls, or shaping the substrate alone can extract 100% or approximately 100% of the light generated at the emitter layers from the emitter layers. In some embodiments, the total efficiency is at least 90% or above. In some embodiments, the emitter layer can be shaped by etching, mechanical shaping, or a combination of various shaping methods. In some embodiments, only a portion of the emitter layer is shaped to form the tiny emitters. The unshaped portion forms a continuous electrical connection for the LED.11-26-2009
20090294777METHOD FOR FORMING A GROUP III NITRIDE MATERIAL ON A SILICON SUBSTRATE - Semiconductor process technology and devices are provided, including a method for forming a high quality group III nitride layer on a silicon substrate and to a device obtainable therefrom. According to the method, a pre-dosing step is applied to a silicon substrate, wherein the substrate is exposed to at least 0.01 μmol/cm12-03-2009
20090294776Highly Oxygen-Sensitive Silicon Layer and Method for Obtaining Same - Silicon layer highly sensitive to oxygen and method for obtaining said layer.12-03-2009
20110204383SIC SEMICONDUCTOR DEVICE HAVING SCHOTTKY BARRIER DIODE AND METHOD FOR MANUFACTURING THE SAME - A SiC semiconductor device having a Schottky barrier diode includes: a substrate made of SiC and having a first conductive type, wherein the substrate includes a main surface and a rear surface; a drift layer made of SiC and having the first conductive type, wherein the drift layer is disposed on the main surface of the substrate and has an impurity concentration lower than the substrate; a Schottky electrode disposed on the drift layer and has a Schottky contact with a surface of the drift layer; and an ohmic electrode disposed on the rear surface of the substrate. The Schottky electrode directly contacts the drift layer in such a manner that a lattice of the Schottky electrode is matched with a lattice of the drift layer.08-25-2011
20090008650FIELD-EFFECT TRANSISTOR AND THYRISTOR - A decrease in breakdown voltage can be prevented as much as possible. A field-effect transistor includes: a drain region made of SiC; a drift layer which is formed on the drain region and is made of n-type SiC; a source region which is formed on the surface of the drift layer and is made of n-type SiC; a channel region which is formed on the surface of the drift layer located on a side of the source region and is made of SiC; an insulating gate which is formed on the channel region; and a p-type base region interposed between the bottom portion of the source region and the drift region, and containing two kinds of p-type impurities.01-08-2009
20090261350Silicon carbide semiconductor device including deep layer - A silicon carbide semiconductor device includes a substrate, a drift layer located on a first surface of the substrate, a base region located on the drift layer, a source region located on the base region, a trench sandwiched by each of the base region to the drift layer, a channel layer located in the trench, a gate insulating layer located on the channel layer, a gate electrode located on the gate insulating layer, a source electrode electrically coupled with the source region and the base region, a drain electrode located on a second surface of the substrate, and a deep layer located under the base region and extending to a depth deeper than the trench. The deep layer is formed into a lattice pattern.10-22-2009
20090261349SEMICONDUCTOR DEVICE WITH STRAINED CHANNEL AND METHOD OF FABRICATING THE SAME - A semiconductor device includes: a gate pattern over a substrate; recess patterns provided in the substrate at both sides of the gate pattern, each having a side surface extending below the gate pattern; and a source and a drain filling the recess patterns, and forming a strained channel under the gate pattern.10-22-2009
20090261347DIAMOND SEMICONDUCTOR ELEMENT AND PROCESS FOR PRODUCING THE SAME - In a conventional diamond semiconductor element, because of high density of crystal defects, it is impossible to reflect the natural physical properties peculiar to a diamond, such as high thermal conductivity, high breakdown field strength, high-frequency characteristics and the like, in the transistor characteristics. By slightly shifting surface orientation of a diamond substrate in a [001] direction, a significant reduction in crystal defects peculiar to a diamond is possible. The equivalent effects are also provided by shifting surface orientation of a single-crystal diamond thin-film or channel slightly from a [001] direction. It is possible to obtain a significantly high transconductance gm as compared with that in a transistor produced using conventional surface orientation.10-22-2009
20120292638PROCESS FOR MANUFACTURING STRESS-PROVIDING STRUCTURE AND SEMICONDUCTOR DEVICE WITH SUCH STRESS-PROVIDING STRUCTURE - A process for manufacturing a stress-providing structure is applied to the fabrication of a semiconductor device. Firstly, a substrate with a channel structure is provided. A silicon nitride layer is formed over the substrate by chemical vapor deposition in a halogen-containing environment. An etching process is performed to partially remove the silicon nitride layer to expose a portion of a surface of the substrate beside the channel structure. The exposed surface of the substrate is etched to form a recess in the substrate. Then, the substrate is thermally treated at a temperature between 750° C. and 820° C. After the substrate is thermally treated, a stress-providing material is filled in the recess to form a stress-providing structure within the recess. The semiconductor device includes a substrate, a recess and a stress-providing structure. The recess has a round inner surface. The stress-providing structure has a round outer surface.11-22-2012
20120292637Dual Cavity Etch for Embedded Stressor Regions - Generally, the present disclosure is directed to methods for forming embedded stressor regions in semiconductor devices such as transistor elements and the like. One illustrative method disclosed herein includes forming a first material in first cavities formed in a first active area adjacent to a first channel region of a semiconductor device, wherein the first material induces a first stress in the first channel region. The method also includes, among other things, forming a second material in second cavities formed in a second active area adjacent to a second channel region of the semiconductor device, wherein the second material induces a second stress in the second channel region that is of an opposite type of the first stress in the first channel region, and wherein the first and second cavities are formed during a common etch process.11-22-2012
20120292636SIC DEVICES WITH HIGH BLOCKING VOLTAGE TERMINATED BY A NEGATIVE BEVEL - A negative bevel edge termination for a Silicon Carbide (SiC) semiconductor device is disclosed. In one embodiment, the negative bevel edge termination includes multiple steps that approximate a smooth negative bevel edge termination at a desired slope. More specifically, in one embodiment, the negative bevel edge termination includes at least five steps, at least ten steps, or at least 15 steps. The desired slope is, in one embodiment, less than or equal to fifteen degrees. In one embodiment, the negative bevel edge termination results in a blocking voltage for the semiconductor device of at least 10 kilovolts (kV) or at least 12 kV. The semiconductor device is preferably, but not necessarily, a thyristor such as a power thyristor, a Bipolar Junction Transistor (BJT), an Insulated Gate Bipolar Transistor (IGBT), a U-channel Metal-Oxide-Semiconductor Field Effect Transistor (UMOSFET), or a PIN diode.11-22-2012
20120292641SEMICONDUCTOR DEVICE HAVING AT LEAST ONE CONTACT, AND MANUFACTURING METHOD FOR A SEMICONDUCTOR DEVICE HAVING AT LEAST ONE CONTACT - A semiconductor device having a substrate, and at least one contact, situated on and/or above a surface of the substrate, having at least one layer made of a conductive material, the conductive material including at least one metal. The layer made of the conductive material is sputtered on, and has tear-off marks on at least one outer side area between an outer base area facing the surface and an outer contact area facing away from the surface. A manufacturing method for a semiconductor device having at least one contact is also described.11-22-2012
20120292639STRESSED SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING - A semiconductor device and method of manufacturing a semiconductor device is disclosed. The exemplary semiconductor device and method for fabricating the semiconductor device enhance carrier mobility. The method includes providing a substrate and forming a dielectric layer over the substrate. The method further includes forming a first trench within the dielectric layer, wherein the first trench extends through the dielectric layer and epitaxially (epi) growing a first active layer within the first trench and selectively curing with a radiation energy the dielectric layer adjacent to the first active layer.11-22-2012
20120292642FUNCTIONAL ELEMENT AND MANUFACTURING METHOD OF SAME - Provided is a functional element which is obtained by forming a lamination film on a substrate and then dividing the substrate and the lamination film into a desired shape. The functional element has a hexagonal substrate, a lamination film formed on a C surface of the substrate, and a plurality of divided surfaces which are exposed by dividing the substrate into quadrilaterals. At least one line of division lines in the case of dividing the substrate into quadrilaterals is perpendicular to any one of equivalent directions of [11-22-2012
20110266557Semiconductor Devices Having Improved Adhesion and Methods of Fabricating the Same - Wide bandgap semiconductor devices are fabricated by providing a wide bandgap semiconductor layer, providing a plurality of recesses in the wide bandgap semiconductor layer, and providing a metal gate contact in the plurality of recesses. A protective layer may be provided on the wide bandgap semiconductor layer, the protective layer having a first opening extending therethrough, a dielectric layer may be provided on the protective layer, the dielectric layer having a second opening extending therethrough that is narrower than the first opening, and a gate contact may be provided in the first and second openings. The metal gate contact may be provided to include a barrier metal layer in the plurality of recesses, and a current spreading layer on the barrier metal layer remote from the wide bandgap semiconductor layer. Related devices and fabrication methods are also discussed.11-03-2011
20110266556METHOD FOR CONTROLLED GROWTH OF SILICON CARBIDE AND STRUCTURES PRODUCED BY SAME - A method for controlled growth of silicon carbide and structures produced by the method are disclosed. A crystal of silicon carbide (SiC) can be grown by placing a sacrificial substrate in a growth zone with a source material. The source material may include a low-solubility impurity. SiC is then grown on the sacrificial substrate to condition the source material. The sacrificial substrate is then replaced with the final substrate, and SiC is grown on the final substrate. A single crystal of silicon carbide is produced, wherein the crystal of silicon carbide has substantially few micropipe defects. Such a crystal may also include a substantially uniform concentration of the low-solubility impurity, and may be used to make wafers and/or SiC die.11-03-2011
20100102331OHMIC ELECTRODE FOR SIC SEMICONDUCTOR, METHOD OF MANUFACTURING OHMIC ELECTRODE FOR SIC SEMICONDUCTOR, SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - An ohmic electrode for SiC semiconductor that contains Si and Ni or an ohmic electrode for SiC semiconductor that further contains Au or Pt in addition to Si and Ni is provided. In addition, a method of manufacturing the ohmic electrode for SiC semiconductor, a semiconductor device including the ohmic electrode for SiC semiconductor, and a method of manufacturing the semiconductor device are provided.04-29-2010
20110204384METHOD OF FORMING A PLANAR FIELD EFFECT TRANSISTOR WITH EMBEDDED AND FACETED SOURCE/DRAIN STRESSORS ON A SILICON-ON-INSULATOR (SOI) WAFER, A PLANAR FIELD EFFECT TRANSISTOR STRUCTURE AND A DESIGN STRUCTURE FOR THE PLANAR FIELD EFFECT TRANSISTOR - Disclosed are embodiments of a method of forming, on an SOI wafer, a planar FET with embedded and faceted source/drain stressors. The method incorporates a directional ion implant process to create amorphous regions at the bottom surfaces of source/drain recesses in a single crystalline semiconductor layer of an SOI wafer. Then, an etch process selective to different crystalline planes over others and further selective to single crystalline semiconductor material over amorphous semiconductor material can be performed in order to selectively adjust the shape (i.e., the profile) of the recess sidewalls without increasing the depth of the recesses. Subsequently, an anneal process can be performed to re-crystallize the amorphous regions and an epitaxial deposition process can be used to fill the recesses with source/drain stressor material. Also disclosed are embodiments of a planar FET structure and a design structure for the planar FET.08-25-2011
20110204382LAYERED STRUCTURES COMPRISING SILICON CARBIDE LAYERS, A PROCESS FOR THEIR MANUFACTURE AND THEIR USE - A layered structure comprising in this order: (A) a silicon carbide layer, (B) at least one stratum (b1) located at least one major surface of the silicon carbide layer (A), (b2) chemically bonded to the bulk of the silicon carbide layer (A) by silicon-oxygen and/or silicon-carbon bonds, (b3) covering the at least one major surface of the silicon carbide layer (A) partially or completely, and (b4) having a higher polarity than a pure silicon carbide surface as exemplified by a contact angle with water which is lower than the contact angle of water with a pure silicon carbide surface; and (C) at least one dielectric layer, which covers the stratum or the strata (B) partially or completely and is selected from inorganic and inorganic-organic hybrid dielectric layers; a process for its manufacture and its use.08-25-2011
20080251793JUNCTION BARRIER SCHOTTKY RECTIFIERS HAVING EPITAXIALLY GROWN P+-N JUNCTIONS AND METHODS OF MAKING - A junction barrier Schottky (JBS) rectifier device and a method of making the device are described. The device comprises an epitaxially grown first n-type drift layer and p-type regions forming p10-16-2008
20080277669SiC semiconductor having junction barrier Schottky device - A semiconductor device having a JBS diode includes: a SiC substrate; a drift layer on the substrate; an insulation film on the drift layer having an opening in a cell region; a Schottky barrier diode having a Schottky electrode contacting the drift layer through the opening and an ohmic electrode on the substrate; a terminal structure having a RESURF layer in the drift layer surrounding the cell region; and multiple second conductive type layers in the drift layer on an inner side of the RESURF layer contacting the Schottky electrode. The second conductive type layers are separated from each other. The second conductive type layers and the drift layer provide a PN diode. Each second conductive type layer has a depth larger than the RESURF layer.11-13-2008
20080277668SIS semiconductor having junction barrier schottky device - A semiconductor device having a junction barrier Schottky diode includes: a SiC substrate; a drift layer on the substrate; an insulation film on the drift layer having an opening in a cell region; a Schottky barrier diode having a Schottky electrode contacting the drift layer through the opening of the insulation film and an ohmic electrode on the substrate; a terminal structure having a RESURF layer surrounding the cell region; and multiple second conductive type layers on an inner side of the RESURF layer. The second conductive type layers and the drift layer provide a PN diode. The Schottky electrode includes a first Schottky electrode contacting the second conductive type layers with ohmic contact and a second Schottky electrode contacting the drift layer with Schottky contact.11-13-2008
20100012949SUBSTRATE, IN PARTICULAR MADE OF SILICON CARBIDE, COATED WITH A THIN STOICHIOMETRIC FILM OF SILICON NITRIDE, FOR MAKING ELECTRONIC COMPONENTS, AND METHOD FOR OBTAINING SUCH A FILM - Substrate, in particular in silicon carbide, covered by a thin film of stoichiometric silicon nitride, for the manufacture of electronic components and method for obtaining said film.01-21-2010
20080303036METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURED THEREOF - Methods of manufacturing a semiconductor device including a semiconductor substrate and a hetero semiconductor region including a semiconductor material having a band gap different from that of the semiconductor substrate and contacting a portion of a first surface of the semiconductor substrate are taught herein, as are the resulting devices. The method comprises depositing a first insulating film on exposed portions of the first surface of the semiconductor substrate and on exposed surfaces of the hetero semiconductor material and forming a second insulating film between the first insulating film and facing surfaces of the semiconductor substrate and the hetero semiconductor region by performing a thermal treatment in an oxidizing atmosphere.12-11-2008
20080265260Power Device - A power device having a transistor structure is formed by using a wide band gap semiconductor. A current path 10-30-2008
20080290348Semiconductor device - In the present invention, a vertical MOSFET is formed by growing epitaxial Si on a SiC substrate and forming a Si oxide layer on the Si. In particular, a semiconductor device according to the present invention includes a SiC substrate, and an epitaxial Si layer formed on a surface of the SiC substrate, and a Si oxide layer formed on the epitaxial Si layer, and a gate electrode formed on the Si oxide layer, and a source region formed in the epitaxial Si layer, and a drain electrode connected to the SiC substrate.11-27-2008
20080217627SiC-PN Power Diode - An integrated vertical SiC—PN power diode has a highly doped SiC semiconductor body of a first conductivity type, a low-doped drift zone of the first conductivity type, arranged above the semiconductor body on the emitter side, an emitter zone of a second conductivity type, applied to the drift zone, and at least one thin intermediate layer of the first conductivity type. The intermediate layer is arranged inside the drift zone, has a higher doping concentration than the drift zone, and divides the drift zone into at least one first anode-side drift zone layer and at least one second cathode-side drift zone layer. There is also disclosed a circuit configuration with such SiC—PN power diodes.09-11-2008
20130181228POWER SEMICONDUCTOR MODULE AND METHOD OF MANUFACTURING THE SAME - First chip main surfaces of first semiconductor chips are bonded to a heat spreader, and second chip main surfaces of the first semiconductor chips are bonded to a first electrode. First chip main surfaces of second semiconductor chips are bonded to a heat spreader, and second chip main surfaces of the second semiconductor chips are bonded to a first electrode. A plurality of electrodes are provided by a lead frame. An insulating member is provided on a side opposite to the chips when viewed from the heat spreader. An insulating substrate is provided on a side opposite to the chips when viewed from the first electrodes.07-18-2013
20080277670SiC crystal and semiconductor device - The present invention discloses a SiC crystal, comprising: acceptor impurities that are in a concentration greater than 5×1011-13-2008
20100289031DIAMOND SEMICONDUCTOR DEVICE - The diamond semiconductor device is a diamond semiconductor device where a pair of electrodes are fixed on a diamond substrate, and wherein at least one interface to the electrode on the surface of the diamond substrate has a hydrogen termination and at least the surface of the substrate between the pair of two electrodes is controlled to have a larger electric resistivity value than inside the substrate. Accordingly, a diamond semiconductor device can be realized, capable of attaining the device work stability, especially the device work stability in severe environments such as high temperature with exhibiting the function of the hydrogen termination thereof to the utmost extent.11-18-2010
20130119405SEMICONDUCTOR DEVICE WITH ENHANCED STRAIN - The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate. The semiconductor device includes a gate that is disposed over the substrate. The substrate has a recess. The semiconductor device includes a trench liner that is coated along the recess. The trench liner contains a semiconductor crystal material. The trench liner directly abuts the source/drain stressor device. The semiconductor device also includes a dielectric trench component that is disposed on the trench liner and filling the recess. The semiconductor device includes a source/drain stressor device that is disposed in the substrate. The source/drain stressor device is disposed between the gate and the trench liner.05-16-2013
20130119406SILICON CARBIDE SUBSTRATE, SEMICONDUCTOR DEVICE, AND METHODS FOR MANUFACTURING THEM - A silicon carbide substrate includes a base layer made of silicon carbide, silicon carbide layers made of single-crystal silicon carbide and arranged side by side on the base layer when viewed in plan view, and a filling portion made of silicon carbide and filling a gap formed between the adjacent silicon carbide layers. The filling portion has a surface roughness of not more than 50 μm in RMS value.05-16-2013
20130119407METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes the steps of: preparing a substrate made of silicon carbide; forming, in the substrate, a trench opened on one main surface side of the substrate; and forming an oxide film in a region including a surface of the trench. In the step of forming the oxide film, the substrate is heated at a temperature of not less than 1250° C. in an atmosphere containing oxygen.05-16-2013
20100270562Semiconductor wafer, semiconductor thin film, and method for manufacturing semiconductor thin film devices - A method for manufacturing a semiconductor thin film device includes: forming a buffer layer on an Si (111) substrate and a single crystal semiconductor layer on the buffer layer; forming an island including the semiconductor layer, buffer layer, and a portion of the substrate; forming a coating layer on the island; etching the substrate along its Si (111) plane to release the island from the substrate, the coating layer serving as a mask; and bonding the released island to another substrate, a released surface of the released island contacting the another substrate. A semiconductor device includes a single crystal semiconductor layer other than Si, which has a semiconductor device formed on a front surface of an Si (111) layer lying in a (111) plane. The layer is bonded to another substrate with a back surface contacting the another substrate or a bonding layer formed on the another substrate.10-28-2010
20110006309EPITAXIAL SiC SINGLE CRYSTAL SUBSTRATE AND METHOD OF MANUFACTURE OF EXPITAXIAL SiC SINGLE CRYSTAL SUBSTRATE - An epitaxial SiC single crystal substrate including a SiC single crystal wafer whose main surface is a c-plane or a surface that inclines a c-plane with an angle of inclination that is more than 0 degree but less than 10 degrees, and SiC epitaxial film that is formed on the main surface of the SiC single crystal wafer, wherein the dislocation array density of threading edge dislocation arrays that are formed in the SiC epitaxial film is 10 arrays/cm01-13-2011
20110006310SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device comprises a semiconductor substrate made of silicon carbide, a gate insulating film formed on the semiconductor substrate, and a gate electrode formed on the gate insulating film. The junction surface of the semiconductor surface joined with the gate insulating film is macroscopically parallel to a nonpolar face and microscopically comprised of the nonpolar face and a polar face. In the polar face, either a Si face or a C face is dominant. A semiconductor device comprises a semiconductor substrate comprised of silicon carbide and a gate electrode formed on the semiconductor substrate. The junction surface of the semiconductor surface joined with the electrode is macroscopically parallel to a nonpolar face and microscopically comprised of the nonpolar face and a polar face. In the polar face, either a Si face or a C face is dominant. The present invention is a semiconductor device having a silicon carbide substrate, and the electrical characteristics and the stability of the interface between the electrode and the silicon carbide or between the oxide film (insulating film) and the silicon carbide in the nonpolar face of a silicon carbide epitaxial layer can be improved.01-13-2011
20090090918TRANSPARENT NANOCRYSTALLINE DIAMOND CONTACTS TO WIDE BANDGAP SEMICONDUCTOR DEVICES - A heterojunction between thin films of NCD and 4H—SiC was developed. Undoped and B-doped NCDs were deposited on both n− and p− SiC epilayers. I-V measurements on p+ NCD/n− SiC indicated Schottky rectifying behavior with a turn-on voltage of around 0.2 V. The current increased over eight orders of magnitude with an ideality factor of 1.17 at 30° C. Ideal energy-band diagrams suggested a possible conduction mechanism for electron transport from the SiC conduction band to either the valence band or acceptor level of the NCD film.04-09-2009
20080258153Silcon carbide semiconductor device having schottky barrier diode and method for manufacturing the same - An SiC semiconductor device is provided, which comprises: a substrate made of silicon carbide and having a principal surface; a drift layer made of silicon carbide and disposed on the principal surface; an insulating layer disposed on the drift layer and including an opening; a Schottky electrode contacting with the drift layer through the opening; a termination structure disposed around an outer periphery of the opening; and second conductivity type layers disposed in a surface part of the drift layer, contacting the Schottky electrode, surrounded by the termination structure, and separated from one another. The second conductivity type layers include a center member and ring members. Each ring member surrounds the center member and is arranged substantially in a point symmetric manner with respect to the center member.10-23-2008
20090001382Schottky barrier diode and method for making the same - A schottky diode includes a SiC substrate which has a first surface and a second surface facing away from the first surface, a semiconductor layer which is formed on the first surface of the SiC substrate, a schottky electrode which is in contact with the semiconductor layer, and an ohmic electrode which is in contact with the second surface of the SiC substrate. The first surface of the SiC substrate is a (000-1) C surface, upon which the semiconductor layer is formed.01-01-2009
20090152566Junction field-effect transistor - A junction field-effect transistor comprises an n-type semiconductor layer having a channel region, a buffer layer formed on the channel region and a p06-18-2009
20120061683GROUP III NITRIDE SEMICONDUCTOR GROWTH SUBSTRATE, GROUP III NITRIDE SEMICONDUCTOR EPITAXIAL SUBSTRATE, GROUP III NITRIDE SEMICONDUCTOR ELEMENT AND GROUP III NITRIDE SEMICONDUCTOR FREE-STANDING SUBSTRATE, AND METHOD OF PRODUCING THE SAME - An object of the present invention is to provide a Group III nitride semiconductor epitaxial substrate, a Group III nitride semiconductor element, and a Group III nitride semiconductor free-standing substrate, which have good crystallinity, with not only AlGaN, GaN, and GaInN the growth temperature of which is 1050° C. or less, but also with Al03-15-2012
20120061681MECHANISM OF FORMING SIC CRYSTALLINE ON SI SUBSTRATES TO ALLOW INTEGRATION OF GAN AND SI ELECTRONICS - The mechanisms of forming SiC crystalline regions on Si substrate described above enable formation and integration of GaN-based devices and Si-based devices on a same substrate. The SiC crystalline regions are formed by implanting carbon into regions of Si substrate and then annealing the substrate. An implant-stop layer is used to cover the Si device regions during formation of the SiC crystalline regions.03-15-2012
20110266558SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING SILICON CARBIDE SEMICONDUCTOR DEVICE - There is provided a silicon carbide semiconductor device equipped with an ohmic electrode that exhibits both low contact resistance and favorable surface conditions, 11-03-2011
20090127565P-n junctions on mosaic diamond substrates - The present invention provides methods of making and using semiconductive single crystal diamond bodies, including semiconductive diamond bodies made by such methods. In one aspect, a method of making a semiconductive single crystal diamond layer may include placing a plurality of diamond segments in close proximity under high pressure in association with a molten catalyst and a carbon source, where the diamond segments are arranged in a single crystal orientation. The plurality of diamond segments are then maintained under high pressure in the molten catalyst until the plurality of diamond segments have joined together with diamond to diamond bonds to form a substantially single crystal diamond body. Following creation of the single crystal diamond body, a homoepitaxial single crystal diamond layer may be deposited on the single crystal diamond body. A dopant may be introduced into the homoepitaxial single crystal diamond layer to form a semiconductive single crystal diamond layer.05-21-2009
20110220918SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A high-performance semiconductor device capable of suppressing a leak current with little electric field concentration, reducing an invalid region in a PN junction region, securing a sufficient area for a Schottky junction region, and achieving efficient and easy manufacturing, in which, in one surface of a semiconductor substrate (09-15-2011
20100193801SOLDER MATERIAL, METHOD FOR MANUFACTURING THE SAME, JOINED BODY, METHOD FOR MANUFACTURING THE SAME, POWER SEMICONDUCTOR MODULE, AND METHOD FOR MANUFACTURING THE SAME - A zinc based solder material 08-05-2010
20100200866SiC single crystal substrate, SiC single crystal epitaxial wafer, and SiC semiconductor device - A direction of a dislocation line of a threading dislocation is aligned, and an angle between the direction of the dislocation line of the threading dislocation and a [0001]-orientation c-axis is equal to or smaller than 22.5 degrees. The threading dislocation having the dislocation line along with the [0001]-orientation c-axis is perpendicular to a direction of a dislocation line of a basal plane dislocation. Accordingly, the dislocation does not provide an extended dislocation on the c-face, so that a stacking fault is not generated. Thus, when an electric device is formed in a SiC single crystal substrate having the direction of the dislocation line of the threading dislocation, which is the [0001]-orientation c-axis, a SiC semiconductor device is obtained such that device characteristics are excellent without deterioration, and a manufacturing yield ration is improved.08-12-2010
20090261348SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - In a semiconductor device using a SiC substrate, a Junction Termination Edge (JTE) layer is hardly affected by fixed charge so that a stable dielectric strength is obtained. A semiconductor device according to a first aspect of the present invention includes a SiC epi-layer having n type conductivity, an impurity region in a surface of the SiC epi-layer and having p type conductivity, and JTE layers adjacent to the impurity region, having p type conductivity, and having a lower impurity concentration than the impurity region. The JTE layers are spaced by a distance from an upper surface of the SiC epi-layer, and SiC regions having n type conductivity are present on the JTE layers.10-22-2009
20120138955COMPOUND SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A compound semiconductor device includes a substrate; an initial layer formed over the substrate; and a core layer which is formed over the initial layer and contains a Group III-V compound semiconductor. The initial layer is a layer of Group III atoms of the Group III-V compound semiconductor contained in the core layer.06-07-2012
20090140264SEMICONDUCTOR DEVICE - A hetero semiconductor corner region, which is a current-concentration relief region that keeps a reverse bias current from concentrating on the convex corner, is arranged in a hetero semiconductor region. Thereby, a current concentration on the convex corner can be prevented. As a result, an interrupting performance can be improved at the time of interruption, and at the same time, the generation of the hot spot where in a specific portion is prevented at the time of conduction to suppress deterioration in a specific portion, thereby ensuring a long-term reliability. Further, when the semiconductor chip is used in an L load circuit or the like, for example, at the time of conduction or during a transient response time to the interrupted state, in an index such as a short resistant load amount and an avalanche resistant amount, which are indexes of a breakdown tolerance when overcurrent or overvoltage occurs, the current concentration on a specific portion can be prevented, and thus, these breakdown tolerances can also be improved.06-04-2009
20090140263METHOD FOR DIAMOND SURFACE TREATMENT AND DEVICE USING DIAMOND THIN FILM - A method for surface treatment of diamond comprising exposing the surface of diamond to UV light containing wavelengths of 172 nm to 184.9 nm and 253.7 nm at an integrated exposure of 10 to 5,000 J/cm06-04-2009
20110220916ELECTRONIC CIRCUIT DEVICE - A normally-off type silicon carbide junction FET has a problem that the gate thereof is not easy to use due to inferiority in the characteristics of it. This problem occurs because in order to achieve normally-off, the gate voltage should be off at 0V and at the same time, the ON-state gate voltage should be suppressed to about 2.5V to prevent the passage of an electric current through a pn junction between gate and source. Accordingly, a range from the threshold voltage to the ON-state gate voltage is only from about 1 V to 2V and it is difficult to control the gate voltage. Provided in the present invention is an electronic circuit device obtained by coupling, to a gate of a normally-off type silicon carbide junction FET, an element having a capacitance equal to or a little smaller than the gate capacitance of the junction FET.09-15-2011
20120068195METHOD FOR MANUFACTURING SILICON CARBIDE SUBSTRATE AND SILICON CARBIDE SUBSTRATE - A method for manufacturing a silicon carbide substrate includes the steps of: preparing a plurality of SiC substrates each made of single-crystal silicon carbide; forming a base layer made of silicon carbide and holding the plurality of SiC substrates, which are arranged side by side when viewed in a planar view; and forming a filling portion filling a gap between the plurality of SiC substrates.03-22-2012
20120068194SILICON CARBIDE SEMICONDUCTOR DEVICES - A method of manufacturing a semiconductor device, wherein the method comprises applying a first layer comprising silicon to a second layer comprising silicon carbide, wherein an interface is defined between the first and second layers; and oxidising sonic or all of the first layer.03-22-2012
20120068193STRUCTURE AND METHOD FOR INCREASING STRAIN IN A DEVICE - A method and structure are disclosed for increasing strain in a device, specifically an n-type field effect transistor (NFET) complementary metal-oxide-semiconductor (CMOS) device. Embodiments of this invention include growing an epitaxial layer, performing a cold carbon or cluster carbon pre-amorphization implantation to implant substitutional carbon into the epitaxial layer, forming a tensile cap over the epitaxial layer, and then annealing to recrystallize the amorphous layer to create a stress memorization technique (SMT) effect. The epitaxial layer will therefore include substitutional carbon and have a memorized tensile stress induced by the SMT. Embodiments of this invention can also include a lower epitaxial layer under the epitaxial layer, the lower epitaxial layer comprising for example, a silicon carbon phosphorous (SiCP) layer.03-22-2012
20090050901GLASS-CERAMIC-BASED SEMICONDUCTOR-ON-INSULATOR STRUCTURES AND METHOD FOR MAKING THE SAME - The present invention relates to a semiconductor-on-insulator structure including a semiconductor component comprised of substantially single-crystal semiconductor material layer and a single-crystal semiconductor material with an enhanced oxygen content layer; an oxide glass material layer; and a glass-ceramic layer.02-26-2009
20090050900FIELD-EFFECT TRANSISTOR - At least two drain ohmic contacts are arranged to intersect with an active area. A source ohmic contact is arranged between the drain ohmic contacts. A drain coupling portion on an element separating area couples ends of the drain ohmic contacts on the same side thereof. A gate power supply wiring on the element separating area couples gate fingers at the end thereof on the opposite side of the arrangement side of the drain coupling portion. A gate edge coupling portion couples two gate fingers adjacent to each other, sandwiching the source ohmic contact at the end thereof on the arrangement side of the drain coupling portion. The gate edge coupling portion does not intersect with the drain ohmic contact and the drain coupling portion.02-26-2009
20090050898Silicon carbide semiconductor device and method for producing the same - A silicon carbide semiconductor device (02-26-2009
20090050897Substrate, method of polishing the same, and polishing apparatus - A polishing method and a polishing apparatus capable of polishing a surface of a substrate made of SiC or diamond extremely smoothly and efficiently without causing subsurface damage are provided. A polishing platen 02-26-2009
20090065788Semiconductor substrate with islands of diamond and resulting devices - Disclosed is a method of forming a substrate having islands of diamond (or other material, such as diamond-like carbon), as well as integrated circuit devices formed from such a substrate. A diamond island can form part of the thermal solution for an integrated circuit formed on the substrate, and the diamond island can also provide part of a stress engineering solution to improve performance of the integrated circuit. Other embodiments are described and claimed.03-12-2009
20110220915Off-Axis Silicon Carbide Substrates - A method of epitaxial growth of a material on a crystalline substrate includes selecting a substrate having a crystal plane that includes a plurality of terraces with step risers that join adjacent terraces. Each terrace of the plurality or terraces presents a lattice constant that substantially matches a lattice constant of the material, and each step riser presents a step height and offset that is consistent with portions of the material nucleating on adjacent terraces being in substantial crystalline match at the step riser. The method also includes preparing a substrate by exposing the crystal plane; and epitaxially growing the material on the substrate such that the portions of the material nucleating on adjacent terraces merge into a single crystal lattice without defects at the step risers.09-15-2011
20110220913SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device provided with a structure, which prevents withstand voltage deterioration and may be manufactured at a low cost, is provided. The semiconductor device is provided with a semiconductor substrate, a first conductive type semiconductor layer formed of silicon carbide formed on the substrate, an active region formed on a surface of the semiconductor layer, a second conductive type first semiconductor region formed on the surface of the semiconductor layer so as to surround the active region, a second semiconductor region provided on the surface of the semiconductor layer so as to contact the outside of the first semiconductor region to surround the first semiconductor region in which a second conductive type impurity region having impurity concentration and a depth identical to those of the first semiconductor region is formed into a mesh shape, a first electrode provided on the active region, and a second electrode provided on a backside of the semiconductor substrate.09-15-2011
20110220914POWER SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a power semiconductor device according to the present invention includes the steps of: (a) forming a silicon nitride film on a semiconductor substrate; (b) after the step (a), forming a ring-shaped trench along a peripheral portion of the semiconductor substrate 09-15-2011
20110140127SEMI-CONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING THEREOF - A semiconductor light-emitting device and a method for manufacturing the same is disclosed, which improves light extraction efficiency by forming a plurality of protrusions on a surface of a substrate for growing a nitride semiconductor material thereon, the semiconductor light-emitting device comprising a substrate; one or more first protrusions on the substrate, each first protrusion having a recess through which a surface of the substrate is exposed planarly; a first semiconductor layer on the substrate including the first protrusions; an active layer on the first semiconductor layer; a second semiconductor layer on the active layer; a first electrode on a predetermined portion of the first semiconductor layer, wherein the active layer and second semiconductor layer are not formed on the predetermined portion of the first semiconductor layer; and a second electrode on the second semiconductor layer.06-16-2011
20090101918SEMICONDUCTOR ELEMENT AND METHOD FOR MANUFACTURING SAME - A semiconductor device includes: a semiconductor layer 04-23-2009
20090014730SILICON CARBIDE TRANSISTORS AND METHODS FOR FABRICATING THE SAME - An exemplary method for forming an insulator layer over a silicon carbide substrate includes providing a silicon carbide substrate and anodizing the silicon carbide substrate in a liquid ambient at a temperature of not more than 200° C. to form a silicon dioxide layer thereon. Also provided are silicon carbide transistors and methods for fabricating the same.01-15-2009
20120193644BORON-DOPED DIAMOND SEMICONDUCTOR - First and second synthetic diamond regions are doped with boron. The second synthetic diamond region is doped with boron to a greater degree than the first synthetic diamond region, and in physical contact with the first synthetic diamond region. In a further example embodiment, the first and second synthetic diamond regions form a diamond semiconductor, such as a Schottky diode when attached to at least one metallic lead.08-02-2012
20120104417SILICON CARBIDE SEMICONDUCTOR ELEMENT, METHOD OF MANUFACTURING THE SAME, AND SILICON CARBIDE DEVICE - A silicon carbide semiconductor element and a manufacturing method thereof are disclosed in which a low contact resistance is attained between an electrode film and a wiring conductor element, and the wiring conductor element is hardly detached from the electrode film. In the method, a nickel film and a nickel oxide film are laminated in this order on a surface of an n-type silicon carbide substrate or an n-type silicon carbide region of a silicon carbide substrate, followed by a heat treatment under a non-oxidizing condition. The heat treatment transforms a portion of the nickel film into a nickel silicide film. Then, the nickel oxide film is removed with hydrochloric acid solution, and subsequently, a nickel aluminum film and an aluminum film are laminated in this order on a surface of the nickel silicide film.05-03-2012
20120104416BIPOLAR JUNCTION TRANSISTOR GUARD RING STRUCTURES AND METHOD OF FABRICATING THEREOF - Semiconductor devices with multiple floating guard ring edge termination structures and methods of fabricating same are disclosed. A method for fabricating guard rings in a semiconductor device that includes forming a mesa structure on a semiconductor layer stack, the semiconductor stack including two or more layers of semiconductor materials including a first layer and a second layer, said second layer being on top of said first layer, forming trenches for guard rings in the first layer outside a periphery of said mesa, and forming guard rings in the trenches. The top surfaces of said guard rings have a lower elevation than a top surface of said first layer.05-03-2012
20120104415SEMICONDUCTOR DEVICE - A semiconductor device includes: an emitter electrode formed of a silicide film, and provided on a semiconductor layer; an insulating film provided on the emitter electrode; and an electrode pad made of Al, and provided on the insulating film.05-03-2012
20120104414MINIATURE PACKAGING FOR DISCRETE CIRCUIT COMPONENTS - A miniature packaging for a discrete circuit component that comprises a core dice for the circuit component fabricated on a semiconductor substrate. The core dice has at least a pair of metallization electrodes formed on the same or different surfaces of the semiconductor substrate. An end electrode covers a corresponding side surface of the core dice and electrically connects to a corresponding one of the pair of metallization electrodes. The end electrode extends toward the center of the core dice on both the top and bottom surface of the core dice.05-03-2012
20090200559Silicon carbide semiconductor device including deep layer - A silicon carbide semiconductor device includes a substrate, a drift layer located on a first surface of the substrate, a base region located on the drift layer, a source region located on the base region, a trench penetrating the source region and the base region to the drift layer, a channel layer located in the trench, a gate insulating layer located on the channel layer, a gate electrode located on the gate insulating layer, a source electrode electrically coupled with the source region and the base region, a drain electrode located on a second surface of the substrate, and a deep layer. The deep layer is located under the base region, extends to a depth deeper than the trench and is formed along an approximately normal direction to a sidewall of the trench.08-13-2009
20130214291SEMICONDUCTOR ELEMENT AND MANUFACTURING METHOD THEREFOR - As viewed along a normal to the principal surface of a substrate 08-22-2013
20090230406HOMOEPITAXIAL GROWTH OF SIC ON LOW OFF-AXIS SIC WAFERS - A wafer including a SiC substrate having a surface that is inclined relative to a (0001) basal plane at an angle higher than 0.1 degree but less than 1 degree, a SiC homoepitaxial device layer, and a SiC homoepitaxial boundary layer having a thickness up to 1 μm arranged between the substrate and the device layer. The boundary layer has been grown on the substrate under an atmosphere of lower supersaturation than when forming the device layer and at a C/Si ratio above 1.09-17-2009
20090230405Diode having Schottky junction and PN junction and method for manufacturing the same - A manufacturing method of a diode includes: forming a P type semiconductor film on a N type semiconductor layer with a crystal growth method; forming a first metallic film on the P type semiconductor film so that the first metallic film contacts the P type semiconductor film with an ohmic contact; forming a mask having an opening on the first metallic film; etching a part of the first metallic film and a part of the P type semiconductor film via the opening so that a part of the N type semiconductor layer is exposed; and forming a second metallic film on the part of the N type semiconductor layer so that the second metallic film contacts the N type semiconductor layer with a Schottky contact.09-17-2009
20090230404SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR09-17-2009
20090242899Epitaxial Growth on Low Degree Off-Axis SiC Substrates and Semiconductor Devices Made Thereby - A method of epitaxially growing a SiC layer on a single crystal SiC substrate is described. The method includes heating a single-crystal SiC substrate to a first temperature of at least 1400° C. in a chamber, introducing a carrier gas, a silicon containing gas and carbon containing gas into the chamber; and epitaxially growing a layer of SiC on a surface of the SiC substrate. The SiC substrate is heated to the first temperature at a rate of at least 10-01-2009
20090250705SILICON CARBIDE SEMICONDUCTOR DEVICE COMPRISING SILICON CARBIDE LAYER AND METHOD OF MANUFACTURING THE SAME - A p base ohmic contact of a silicon carbide semiconductor device consists of a p++ layer formed by high-concentration ion implantation and a metal electrode. Since the high-concentration ion implantation performed at the room temperature significantly degrades the crystal of the p++ layer to cause a process failure, a method for implantation at high temperatures is used. In terms of switching loss and the like of devices, it is desirable that the resistivity of the p base ohmic contact should be lower. In well-known techniques, nothing is mentioned on a detailed relation among the ion implantation temperature, the ohmic contact resistivity and the process failure. Then, in the ion implantation step, the temperature of a silicon carbide wafer is maintained in a range from 175° C. to 300° C., more preferably in a range from 175° C. to 200° C. The resistivity of the p base ohmic contact using a p++ region formed by ion implantation at a temperature in a range from 175° C. to 300° C. becomes lower than that in a case where the p++ region is formed by ion implantation at a temperature over 300° C. Further, this can avoid any process failure.10-08-2009
20090256162Method for Producing Semi-Insulating Resistivity in High Purity Silicon Carbide Crystals - A method is disclosed for producing high quality semi-insulating silicon carbide crystals in the absence of relevant amounts of deep level trapping elements. The invention includes the steps of heating a silicon carbide crystal having a first concentration of point defects to a temperature that thermodynamically increases the number of point defects and resulting states in the crystal, and then cooling the heated crystal at a sufficiently rapid rate to maintain an increased concentration of point defects in the cooled crystal.10-15-2009
20090242900MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - The invention discloses a memory device and method thereof. The memory device comprises a substrate, an insulator layer, a first conducting layer, a CaCu10-01-2009
20100148186VERTICAL JUNCTION FIELD EFFECT TRANSISTORS HAVING SLOPED SIDEWALLS AND METHODS OF MAKING - Semiconductor devices and methods of making the devices are described. The devices can be junction field-effect transistors (JFETs). The devices have raised regions with sloped sidewalls which taper inward. The sidewalls can form an angle of 5° or more from vertical to the substrate surface. The devices can have dual-sloped sidewalls in which a lower portion of the sidewalls forms an angle of 5° or more from vertical and an upper portion of the sidewalls forms an angle of <5° from vertical. The devices can be made using normal (i.e., 0°) or near normal incident ion implantation. The devices have relatively uniform sidewall doping and can be made without angled implantation.06-17-2010
20090256160SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a semiconductor device is provided. A gate structure is formed on a substrate. A first dopant implantation and a first strain atom implantation are performed. Thereafter, spacers are formed on sidewalls of the gate structure. A second dopant implantation and a second strain atom implantation are performed. A solid-phase epitaxy annealing process is performed to form source and drain regions made of a semiconductor compound solid-phase epitaxial layer beside the gate structure.10-15-2009
20120193641NORMALLY-OFF POWER JFET AND MANUFACTURING METHOD THEREOF - In general, in a semiconductor active element such as a normally-off JFET based on SiC in which an impurity diffusion speed is significantly lower than in silicon, gate regions are formed through ion implantation into the side walls of trenches formed in source regions. However, to ensure the performance of the JFET, it is necessary to control the area between the gate regions thereof with high precision. Besides, there is such a problem that, since a heavily doped PN junction is formed by forming the gate regions in the source regions, an increase in junction current cannot be avoided. The present invention provides a normally-off power JFET and a manufacturing method thereof and forms the gate regions according to a multi-epitaxial method which repeats a process including epitaxial growth, ion implantation, and activation annealing a plurality of times.08-02-2012
20120193640CRYSTALLINE ALUMINUM CARBIDE THIN FILM, SEMICONDUCTOR SUBSTRATE HAVING THE ALUMINUM CARBIDE THIN FILM FORMED THEREON AND METHOD OF FABRICATING THE SAME - Embodiments of the invention provide a crystalline aluminum carbide thin film, a semiconductor substrate having the crystalline aluminum carbide thin film formed thereon, and a method of fabricating the same. Further, the method of fabricating the AlC thin film includes supplying a carbon containing gas and an aluminum containing gas to a furnace, to growing AlC crystals on a substrate.08-02-2012
20090256161POWER CONVERSION APPARATUS - In the case where a chip is made of wide band gap semiconductor, a power conversion apparatus is obtained in which a component having a low heat resistant temperature is prevented from receiving thermal damage by heat generated at the chip. In a configuration including: a chip portion (10-15-2009
20120193643SEMICONDUCTOR DEVICE - A MOSFET includes a silicon carbide substrate, an active layer, a gate oxide film, and a gate electrode. The active layer includes a p type body region in which an inversion layer is formed when the gate electrode is fed with a voltage. The inversion layer has an electron mobility μ dependent more strongly on an acceptor concentration N08-02-2012
20100155743SiC SEMICONDUCTOR DEVICE WITH SELF-ALIGNED CONTACTS, INTEGRATED CIRCUIT AND MANUFACTURING METHOD - One aspect includes a semiconductor device with self-aligned contacts, integrated circuit and manufacturing method. One embodiment provides gate control structures. Each of the gate control structures is configured to control the conductivity of a channel region within a silicon carbide substrate by field effect. A contact hole is self-aligned to opposing sidewalls of adjacent gate control structures by intermediate spacers.06-24-2010
20100187543METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE AND THE SILICON CARBIDE SEMICONDUCTOR DEVICE - Silicon carbide semiconductor device includes trench, in which connecting trench section is connected to straight trench section. Straight trench section includes first straight trench and second straight trench extending in parallel to each other. Connecting trench section includes first connecting trench perpendicular to straight trench section, second connecting trench that connects first straight trench and first connecting trench to each other, and third connecting trench that connects second straight trench and first connecting trench to each other. Second connecting trench extends at 30 degrees of angle with the extension of first straight trench. Third connecting trench extends at 30 degrees of angle with the extension of second straight trench. A manufacturing method according to the invention for manufacturing a silicon carbide semiconductor device facilitates preventing defects from being causes in a silicon carbide semiconductor device during the manufacture thereof.07-29-2010
20100193800SEMICONDUCTOR DEVICE - A semiconductor device is fabricated on an off-cut semiconductor substrate 08-05-2010
20120032190PACKAGE AND FABRICATION METHOD OF THE SAME - According to one embodiment, provided are a package utilized for a high frequency semiconductor device and a fabrication method for such the package, the package including: a conductive base plate including a CTE control layer composed of compound material, and a heat conduction layer disposed on the CTE control layer and composed of Cu.02-09-2012
20100176403SILICON CARBIDE SUBSTRATE, EPITAXIAL WAFER AND MANUFACTURING METHOD OF SILICON CARBIDE SUBSTRATE - An SiC substrate includes the steps of preparing a base substrate having a main surface and made of SiC, washing the main surface using a first alkaline solution, and washing the main surface using a second alkaline solution after the step of washing with the first alkaline solution. The SiC substrate has the main surface, and an average of residues on the main surface are equal to or larger than 0.2 and smaller than 200 in number.07-15-2010
20130214289Short-Resistant Metal-Gate MOS Transistor and Method of Forming the Transistor - A protective cap is formed on the metal gate of a MOS transistor to protect the metal gate during an etch that forms a source contact opening and a drain contact opening. The protective cap also electrically isolates the source metal contact and the drain metal contact from the metal gate.08-22-2013
20130214290METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE AND SILICON CARBIDE SEMICONDUCTOR DEVICE - A silicon carbide layer having a first surface and a second surface includes a first region constituting the first surface and of a first conductivity type, a second region provided on the first region and of said second conductivity type, and a third region provided on the second region and of the first conductivity type. At the second surface is formed a gate electrode having a bottom and sidewall, passing through the third region and the second region up to the first region. An additional trench is formed, extending from the bottom of the gate trench in the thickness direction. A fourth region of the second conductivity type is formed to fill the additional trench.08-22-2013
20090078942SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes an SiC substrate, a first SiC layer of first conductivity provided on the substrate, a second SiC layer of second conductivity provided on the first SiC layer, first and second SiC regions provided in the second SiC layer, facing each other and having the same depth, a third SiC region extending through the first SiC region and reaching the first SiC layer, a gate insulator formed on the first and second SiC regions and the second SiC layer interposed therebetween, a gate electrode formed on the gate insulator, a first contact of first conductivity formed on the second SiC region, a second contact of second conductivity formed on the second SiC region, reaching the second SiC layer through the second SiC region, and a top electrode formed on the first and second contacts, and a bottom electrode formed on a back surface of the substrate.03-26-2009
20100187544FABRICATING A GALLIUM NITRIDE LAYER WITH DIAMOND LAYERS - In one aspect, a method includes fabricating a gallium nitride (GaN) layer with a first diamond layer having a first thermal conductivity and a second diamond layer having a second thermal conductivity greater than the first thermal conductivity. The fabricating includes using a microwave plasma chemical vapor deposition (CVD) process to deposit the second diamond layer onto the first diamond layer.07-29-2010
20120228639SELF ALIGNED DEVICE WITH ENHANCED STRESS AND METHODS OF MANUFACTURE - A method includes forming a stressed Si layer in a trench formed in a stress layer deposited on a substrate. The stressed Si layer forms an active channel region of a device. The method further includes forming a gate structure in the active channel region formed from the stressed Si layer.09-13-2012
20100258816Silicon carbide semiconductor device and manufacturing method therefor - With a view to preventing increases in forward voltage due to a change with the lapse of time of a bipolar semiconductor device using a silicon carbide semiconductor, a buffer layer, a drift layer and other p-type and n-type semiconductor layers are formed on a growth surface, which is given by a surface of a crystal of a silicon carbide semiconductor having an off-angle θ of 8 degrees from a (000-1) carbon surface of the crystal, at a film growth rate having a film-thickness increasing rate per hour h of 10 μm/h, which is three times or more higher than conventional counterparts. The flow rate of silane and propane material gases and dopant gases is largely increased to enhance the film growth rate.10-14-2010
20100258817Silicon carbide semiconductor device and manufacturing method therefor - With a view to preventing increases in forward voltage due to a change with the lapse of time of a bipolar semiconductor device using a silicon carbide semiconductor, a buffer layer, a drift layer and other p-type and n-type semiconductor layers are formed on a growth surface, which is given by a surface of a crystal of a silicon carbide semiconductor having an off-angle θ of 8 degrees from a (000-1) carbon surface of the crystal, at a film growth rate having a film-thickness increasing rate per hour h of 10 μm/h, which is three times or more higher than conventional counterparts. The flow rate of silane and propane material gases and dopant gases is largely increased to enhance the film growth rate.10-14-2010
20120228632SEMICONDUCTOR DEVICE - A semiconductor device of an embodiment includes: a semiconductor substrate; a field-effect transistor formed on the semiconductor substrate; and a diode forming area which is adjacent to a forming area of the field-effect transistor, wherein the diode forming area is insulated from the forming area of the transistor on the semiconductor substrate, and includes a first diode electrode in which a gate electrode of the field-effect transistor is placed in Schottky barrier junction and/or ohmic contact with the semiconductor substrate through a bus wiring or a pad; and a second diode electrode in which a source electrode of the field-effect transistor is placed in ohmic contact and/or Schottky barrier junction with the semiconductor substrate through a bus interconnection or a pad to form a diode between the gate electrode and the source electrode.09-13-2012
20120241762SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a semiconductor layer of a first conductivity type, a first region of a second conductivity type selectively provided in a first major surface of the semiconductor layer, a second region of the second conductivity type selectively provided in the first major surface and connected to the first region, a first electrode provided in contact with the semiconductor layer and the first region, a second electrode provided in contact with the second region, and a third electrode electrically connected to a second major surface of the semiconductor layer opposite to the first major surface.09-27-2012
20100193799Semiconductor device and method of manufacturing semiconductor device - The semiconductor device according to the present invention includes: a semiconductor layer of a first conductivity type made of SiC having an Si surface; a gate trench dug down from the surface of the semiconductor layer; a gate insulating film formed on a bottom surface and a side surface of the gate trench so that the ratio of the thickness of a portion located on the bottom surface to the thickness of a portion located on the side surface is 0.3 to 1.0; and a gate electrode embedded in the gate trench through the gate insulating film.08-05-2010
20100155742LIGHT-EMITTING DIODE AND LIGHT-EMITTING DIODE LAMP - The present invention provides a light-emitting diode (06-24-2010
20100224885SEMICONDUCTOR DEVICE - A semiconductor device having a junction FET having improved characteristics is provided. The semiconductor device has a junction FET as a main transistor and has a MISFET as a transistor for control. The junction FET has a first gate electrode, a first source electrode, and a first drain electrode. The MISFET has a second gate electrode, a second source electrode, and a second drain electrode. The MISFET is an n-channel type MISFET and has electric characteristics of an enhancement mode MISFET. The second gate electrode and the second drain electrode of the MISFET are connected to each other by short-circuiting. The first gate electrode of the junction FET and the second source electrode of the MISFET are connected to each other by short-circuiting.09-09-2010
20100276702Doped Diamond LED Devices and Associated Methods - LED devices and methods for making such devices are provided. One such method may include forming epitaxially a substantially single crystal SiC layer on a substantially single crystal Si wafer, forming epitaxially a substantially single crystal diamond layer on the SiC layer, doping the diamond layer to form a conductive diamond layer, removing the Si wafer to expose the SiC layer opposite to the conductive diamond layer, forming epitaxially a plurality of semiconductor layers on the SiC layer such that at least one of the semiconductive layers contacts the SiC layer, and coupling an n-type electrode to at least one of the semiconductor layers such that the plurality of semiconductor layers is functionally located between the conductive diamond layer and the n-type electrode.11-04-2010
20100276701LOW THERMAL RESISTANCE AND ROBUST CHIP-SCALE-PACKAGE (CSP), STRUCTURE AND METHOD - A chip scale package (CSP) semiconductor device can include a semiconductor layer, circuitry on an active surface of the semiconductor layer, and a diamond layer on a back side of the semiconductor layer. The diamond layer can provide an efficient heat sink for the semiconductor layer, with a thermal conductivity which can be more than three times greater than the thermal conductivity of copper. Further, a hardness of the diamond layer (up to about 10 times stronger than silicon) can provide effective protection against damage to the exposed semiconductor layer, for example during manufacturing, handling, and use of the CSP device. Thus a thin protective diamond layer can be used, which can result in a very thin CSP package design.11-04-2010
20100213469ILLUMINATION DEVICE - An illumination device having a plurality of light emitting diodes is provided. The light emitting diode may include a plurality of semiconductor layers at least one of which has a light emitting surface which may include a rough surface pattern having a pre-determined pattern. The pre-determined pattern may include one or more impurity regions with each region having a recess for guiding current across the light emitting surface and maximizing the emission of light (i.e. light intensity) of the illumination device. Each recess may include a lower internal portion having a bottom contact point located on a bottom surface and an upper internal portion integrally connected to the lower internal portion by a plurality of center contact points. The gaps created between the center and bottom contact points in adjacent recesses may act as spark gaps allowing for the current to flow through the entire light emitting surface.08-26-2010
20100213470SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - At least part of a semiconductor layer or a semiconductor substrate includes a semiconductor region having a large energy gap. The semiconductor region having a large energy gap is preferably formed from silicon carbide and is provided in a position at least overlapping with a gate electrode provided with an insulating layer between the semiconductor region and the gate electrode. By making a structure in which the semiconductor region is included in a channel formation region, a dielectric breakdown voltage is improved.08-26-2010
20100224884SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A channel layer (09-09-2010
20090045411Forming Embedded Dielectric Layers Adjacent to Sidewalls of Shallow Trench Isolation Regions - A semiconductor structure is provided. The semiconductor structure includes a semiconductor substrate; an insulating region extending from substantially a top surface of the semiconductor substrate into the semiconductor substrate; an embedded dielectric spacer adjacent the insulating region, wherein a bottom of the embedded dielectric spacer adjoins the semiconductor substrate; and a semiconductor material adjoining a top edge and extending on a sidewall of the embedded dielectric spacer.02-19-2009
20100237356BIDIRECTIONAL SILICON CARBIDE TRANSIENT VOLTAGE SUPPRESSION DEVICES - An electronic device includes a silicon carbide layer having a first conductivity type and having a first surface and a second surface opposite the first surface, and first and second silicon carbide Zener diodes on the silicon carbide layer. Each of the first and second silicon carbide Zener diodes may include a first heavily doped silicon carbide region having a second conductivity type opposite the first conductivity type on the silicon carbide layer, and an ohmic contact on the first heavily doped silicon carbide region.09-23-2010
20100001293SEMICONDUCTOR DEVICES HAVING GALLIUM NITRIDE EPILAYERS ON DIAMOND SUBSTRATES - Methods for integrating wide-gap semiconductors with synthetic diamond substrates are disclosed. Diamond substrates are created by depositing synthetic diamond onto a nucleating layer deposited or formed on a layered structure including at least one layer of gallium nitride, aluminum nitride, silicon carbide, or zinc oxide. The resulting structure is a low stress process compatible with wide-gap semiconductor films, and may be processed into optical or high-power electronic devices. The diamond substrates serve as heat sinks or mechanical substrates.01-07-2010
20100001291ELECTRONIC DEVICE AND MANUFACTURING THEREOF - An electronic device and manufacturing thereof. One embodiment provides a carrier and multiple contact elements. The carrier defines a first plane. A power semiconductor chip is attached to the carrier. A body is formed of an electrically insulating material covering the power semiconductor chip. The body defines a second plane parallel to the first plane and side faces extends from the first plane to the second plane. At least one of the multiple contact elements has a cross section in a direction orthogonal to the first plane that is longer than 60% of the distance between the first plane and the second plane.01-07-2010
20100001290BIPOLAR SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor crystal includes a recombination-inhibiting semiconductor layer (01-07-2010
20100252837METHOD FOR PRODUCING SINGLE CRYSTAL SiC SUBSTRATE AND SINGLE CRYSTAL SiC SUBSTRATE PRODUCED BY THE SAME - A single crystal SiC substrate is produced with low cost in which a polycrystalline SiC substrate with relatively low cost is used as a base material substrate where the single crystal SiC substrate has less strain, good crystallinity and large size. The method including a P-type ion introduction step for implanting P-type ions from a side of a surface Si layer 10-07-2010
20100224886P-CHANNEL SILICON CARBIDE MOSFET - A second trench in each source electrode portion (Schottky diode portion) is formed to have a depth equal to or larger than the depth of a first trench in each gate electrode portion. The distance between the first and second trenches is set to be not longer than 10 μm. A source electrode is formed in the second trench and a Schottky junction is formed in the bottom portion of the second trench. In this manner, it is possible to provide a wide band gap semiconductor device which is small-sized, which has low on-resistance and low loss characteristic, in which electric field concentration into a gate insulating film is relaxed to suppress reduction of a withstand voltage, and which has high avalanche breakdown tolerance at turn-off time.09-09-2010
20100140628Insulated gate bipolar transistors including current suppressing layers - An insulated gate bipolar transistor (IGBT) includes a first conductivity type substrate and a second conductivity type drift layer on the substrate. The second conductivity type is opposite the first conductivity type. The IGBT further includes a current suppressing layer on the drift layer. The current suppressing layer has the second conductivity type and has a doping concentration that is larger than a doping concentration of the drift layer. A first conductivity type well region is in the current suppressing layer. The well region has a junction depth that is less than a thickness of the current suppressing layer, and the current suppressing layer extends laterally beneath the well region. A second conductivity type emitter region is in the well region.06-10-2010
20130126903DIAMOND GaN DEVICES AND ASSOCIATED METHODS - Semiconductor devices and methods of making thereof are provided. In one aspect, for example, a method for making a semiconductor device can include polishing a working surface of a diamond layer to a substantially flat surface, depositing a buffer layer on the working surface of the diamond layer, and depositing a semiconductor layer on the buffer layer. In one specific aspect, the c-axis of the buffer layer is oriented perpendicular to the working surface of the diamond layer.05-23-2013
20130126905SEMICONDUCTOR DEVICE WITH LOW-CONDUCTING BURIED AND/OR SURFACE LAYERS - A device including one or more low-conducting layers is provided. A low-conducting layer can be located below the channel and one or more attributes of the low-conducting layer can be configured based on a minimum target operating frequency of the device and a charge-discharge time of a trapped charge targeted for removal by the low-conducting layer or a maximum interfering frequency targeted for suppression using the low-conducting layer. For example, a product of the lateral resistance and a capacitance between the low-conducting layer and the channel can be configured to be larger than an inverse of the minimum target operating frequency and the product can be smaller than at least one of: the charge-discharge time or an inverse of the maximum interfering frequency.05-23-2013
20120241766EPITAXIAL WAFER AND SEMICONDUCTOR ELEMENT - A silicon carbide semiconductor element, including: i) an n-type silicon carbide substrate doped with a dopant, such as nitrogen, at a concentration C, wherein the substrate has a lattice constant that decreases with doping; ii) an n-type silicon carbide epitaxially-grown layer doped with the dopant, but at a smaller concentration than the substrate; and iii) an n-type buffer layer doped with the dopant, and arranged between the substrate and the epitaxially-grown layer, wherein the buffer layer has a multilayer structure in which two or more layers having the same thickness are laminated, and is configured such that, based on a number of layers (N) in the multilayer structure, a doping concentration of a K-th layer from a silicon carbide epitaxially-grown layer side is C·K/(N+1).09-27-2012
20120241764SEMICONDUCTOR DEVICE BASED ON THE CUBIC SILICON CARBIDE SINGLE CRYSTAL THIN FILM - A semiconductor apparatus includes a cubic silicon carbide single crystal thin film of a multilayer structure including an Al09-27-2012
20130126909ELECTRONIC FIELD EFFECT DEVICES AND METHODS FOR THEIR MANUFACTURE - Electronic field effect devices, and methods of manufacture of these electronic field effect devices are disclosed. In particular, there is disclosed an electronic field effect device which has improved electrical properties due to the formation of a highly mobile two-dimensional charge-carrier gas in a simple structure formed from diamond in combination with polar materials.05-23-2013
20130126911STRESS ENHANCED JUNCTION ENGINEERING FOR LATCHUP SCR - A latchup silicon controlled rectifier (SCR) includes a p+ region and an n+ region located in a p-well of the latchup SCR; and a p+ region and an n+ region located in a n-well of the latchup SCR, wherein the latchup SCR further comprises one of embedded silicon germanium (eSiGe) in the p+ region in the n-well of the latchup SCR and silicon carbide (SiC) in the n+ region in the p-well of the latchup SCR.05-23-2013
20120138954SEMICONDUCTOR DEVICE - According to one embodiment, provided is a semiconductor device includes: a high frequency semiconductor chip; an input matching circuit disposed at the input side of the high frequency semiconductor chip; an output matching circuit disposed at the output side of the high frequency semiconductor chip; a high frequency input terminal connected to the input matching circuit; a high frequency output terminal connected to the output matching circuit, and a smoothing capacitor terminal connected to the high frequency semiconductor chip. The high frequency semiconductor chip, the input matching circuit and the output matching circuit are housed by one package.06-07-2012
20110057202SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - According to the embodiments, a semiconductor device using SiC and having a high breakdown voltage, a low on-resistance, and excellent reliability is provided. The semiconductor device includes a silicon carbide substrate having first and second main surfaces; a first silicon carbide layer of a first conductive type provided on the first main surface of the silicon carbide substrate; first silicon carbide regions of a second conductive type formed on a surface of the first silicon carbide layer; second silicon carbide regions of the first conductive type formed on respective surfaces of the first silicon carbide regions; third silicon carbide regions of the second conductive type formed on the respective surfaces of the first silicon carbide regions; a fourth silicon carbide region of the second conductive type formed between the facing first silicon carbide regions with the first silicon carbide layer therebetween; a gate insulating film formed continuously on surfaces of the first silicon carbide regions, the first silicon carbide layer, and the fourth silicon carbide region; a gate electrode formed on the gate insulating film; an interlayer insulating film which covers the gate electrode; a first electrode which is electrically connected to the second silicon carbide regions and the third silicon carbide regions; and a second electrode formed on the second main surface of the silicon carbide substrate.03-10-2011
20100127277SEMICONDUCTOR MODULE - A semiconductor module having one or more silicon carbide diode elements mounted on a switching element is provided in which the temperature rise is reduced by properly disposing each of the diode elements on the switching element, to thereby provide a thermal dissipation path for the respective diode elements. The respective diode elements are arranged on a non-central portion of the switching element, to facilitate dissipation of the heat produced by each of the diode elements, whereby the temperature rise in the semiconductor module is reduced.05-27-2010
20100127278SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes the steps of forming a SiC film, forming trenches at a surface of the SiC film, heat-treating the SiC film with silicon supplied to the surface of the SiC film, and obtaining a plurality of macrosteps to constitute channels, at the surface of the SiC film by the step of heat-treating. Taking the length of one cycle of the trenches as L and the height of the trenches as h, a relation L=h(cot α+cot β) (where α and β are variables that satisfy the relations 0.5≦α,β,≦45) holds between the length L and the height h. Consequently, the semiconductor device can be improved in property.05-27-2010
20100090226DIAMOND UV-RAY SENSOR - Au base electrode materials have fatal disadvantages, such as inferior adhesion to diamond, low mechanical strength, and low thermal stability.04-15-2010
20100078651ELECTRONIC FIELD EFFECT DEVICES AND METHODS FOR THEIR MANUFACTURE - Electronic field effect devices, and methods of manufacture of these electronic field effect devices are disclosed. In particular, there is disclosed an electronic field effect device which has improved electrical properties due to the formation of a highly mobile two-dimensional charge-carrier gas in a simple structure formed from diamond in combination with polar materials.04-01-2010
20090184327METHOD FOR PRODUCING SILICON CARBIDE SINGLE CRYSTAL - A method for the production of an SiC single crystal includes the steps of growing a first SiC single crystal in a first direction of growth on a first seed crystal formed of an SiC single crystal, disposing the first SiC single crystal grown on the first seed crystal in a direction parallel or oblique to the first direction of growth and cutting the disposed first SiC single crystal in a direction of a major axis in a cross section perpendicular to the first direction of growth to obtain a second seed crystal, using the second seed crystal to grow thereon in a second direction of growth a second SiC single crystal to a thickness greater than a length of the major axis in the cross section, disposing the second SiC single crystal grown on the second seed crystal in a direction parallel or oblique to the second direction of growth and cutting the disposed second SiC single crystal in a direction of a major axis in a cross section perpendicular to the second direction of growth to obtain a third seed crystal, using the third seed crystal to grow thereon a third SiC single crystal, and cutting the third SiC single crystal grown on the third seed crystal in such a manner as to expose a {0001} crystal face, thereby obtaining an SiC single crystal. The method enables the crystal to be enlarged efficiently without impairing crystallinity.07-23-2009
20090114924LIGHTLY DOPED SILICON CARBIDE WAFER AND USE THEREOF IN HIGH POWER DEVICES - A method for manufacturing a silicon carbide single crystal. A silicon carbide single crystal is grown. The crystal has a boron concentration less than 5×1005-07-2009
20090114923SEMICONDUCTOR DEVICE - A semiconductor device includes a peripheral voltage withstanding structure, which includes an n05-07-2009
20090072242Insulated Gate Bipolar Conduction Transistors (IBCTS) and Related Methods of Fabrication - Insulated gate bipolar conduction transistors (IBCTs) are provided. The IBCT includes a drift layer having a first conductivity type. An emitter well region is provided in the drift layer and has a second conductivity type opposite the first conductivity type. A well region is provided in the drift layer and has the second conductivity type. The well region is spaced apart from the emitter well region. A space between the emitter well region and the well region defines a JFET region of the IBCT. An emitter region is provided in the well region and has the first conductivity type and a buried channel layer is provided on the emitter well region, the well region and the JFET region and has the first conductivity type. Related methods of fabrication are also provided.03-19-2009
20100295061RECRYSTALLIZATION OF SEMICONDUCTOR WATERS IN A THIN FILM CAPSULE AND RELATED PROCESSES - An original wafer, typically silicon, has the form of a desired end PV wafer. The original may be made by rapid solidification or CVD. It has small grains. It is encapsulated in a clean thin film, which contains and protects the silicon when recrystallized to create a larger grain structure. The capsule can be made by heating a wafer in the presence of oxygen, or steam, resulting in silicon dioxide on the outer surface, typically 1-2 microns. Further heating creates a molten zone in space, through which the wafer travels, resulting in recrystallization with a larger grain size. The capsule contains the molten material during recrystallization, and protects against impurities. Recrystallization may be in air. Thermal transfer through backing plates minimizes stresses and defects. After recrystallization, the capsule is removed.11-25-2010
20100295060SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device 11-25-2010
20100295058TUNNELING FIELD EFFECT TRANSISTOR SWITCH DEVICE - A tunneling field effect transistor (TFET) device includes a semiconductor substrate having a layer of relatively intermediate bandgap semiconductor material, a layer of relatively low bandgap semiconductor material overlying the layer of relatively intermediate bandgap semiconductor material, and a layer of relatively high bandgap semiconductor material overlying the layer of relatively low bandgap semiconductor material. The TFET device includes a source region, a drain region, and a channel region defined in the semiconductor substrate. The TFET device also has a gate structure overlying at least a portion of the channel region. The source region is highly doped with an impurity dopant having a first conductivity type, and the drain region is highly doped with an impurity dopant having a second conductivity type. The layer of relatively low bandgap semiconductor material promotes tunneling at a first junction between the source region and the channel region, and the layer of relatively high bandgap semiconductor material inhibits tunneling at a second junction between the source region and the channel region.11-25-2010
20100308340SEMICONDUCTOR DEVICE HAVING A BURIED CHANNEL - Provided is a device that includes a semiconductor body having a surface. Source and drain regions with effective dopant populations of a first polarity can be disposed adjacent to the surface and spaced apart from one another. A channel region with an effective dopant population of the first polarity can extend between the source and drain regions while being spaced apart from the surface. A gate region with an effective dopant population of a second polarity and first effective dopant density can extend between the source and drain regions and be disposed between the channel region and the surface. A gate contact region can be disposed between the source and drain regions and adjacent to the surface. The gate contact region can have an effective dopant population of the second polarity and a second effective dopant density greater than the first effective dopant density.12-09-2010
20110127542SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - According to one embodiment, a semiconductor device contains a gate electrode, SiGe layers, Si layers, source/drain regions, and silicide layers. The gate electrode is formed on a semiconductor substrate via a gate insulating film. The SiGe layers are formed on both sides of the gate electrode on the semiconductor substrate. Over half of a region of the SiGe layers is higher than an interface between the semiconductor substrate and the gate insulating film. The Si layers are formed on the SiGe layers. The source/drain regions are formed on both sides of the gate electrode in the Si layers, the SiGe layers and the semiconductor substrate. The silicide layers are formed on the Si layers.06-02-2011
20100308344METHOD FOR GROWING P-TYPE SIC SEMICONDUCTOR SINGLE CRYSTAL AND P-TYPE SIC SEMICONDUCTOR SINGLE CRYSTAL - In a method for growing a p-type SiC semiconductor single crystal on a SiC single crystal substrate, using a first solution in which C is dissolved in a melt of Si, a second solution is prepared by adding Al and N to the first solution such that an amount of Al added is larger than that of N added, and the p-type SiC semiconductor single crystal is grown on the SiC single crystal substrate from the second solution. A p-type SiC semiconductor single crystal is provided which is grown by the method as described above, and which contains 1×1012-09-2010
20100308342ELECTRICAL SWITCHING DEVICE AND METHOD OF EMBEDDING CATALYTIC MATERIAL IN A DIAMOND SUBSTRATE - An electrical device according to one embodiment includes a substrate including at least one diamond layer; at least one first electrode in contact with said substrate, wherein at least one said first electrode includes at least one electrically conductive protrusion extending into said substrate; and at least one second electrode in contact with said substrate and spaced from the or each said first electrode.12-09-2010
20100301350SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Recesses are formed in a pMOS region 12-02-2010
20100301351HIGH VOLTAGE SWITCHING DEVICES AND PROCESS FOR FORMING SAME - The present invention relates to various switching device structures including Schottky diode, P—N diode, and P—I—N diode, which are characterized by low defect density, low crack density, low pit density and sufficient thickness (>2.5 um) GaN layers of low dopant concentration (<1E16 cm12-02-2010
20130193446FINFET AND METHOD OF FABRICATING THE SAME - The disclosure relates to a fin field effect transistor (FinFET). An exemplary structure for a FinFET comprises a substrate comprising a major surface; a first fin and a second fin extending upward from the substrate major surface to a first height; an insulation layer comprising a top surface extending upward from the substrate major surface to a second height less than the first height, whereby portions of the fins extend beyond the top surface of the insulation layer; each fin covered by a bulbous epitaxial layer defining an hourglass shaped cavity between adjacent fins, the cavity comprising upper and lower portions, wherein the epitaxial layer bordering the lower portion of the cavity is converted to silicide.08-01-2013
20110001143Composition Comprising Silicon Carbide - A method of depositing a ceramic film, particularly a silicon carbide film, on a substrate is disclosed in which the residual stress, residual stress gradient, and resistivity are controlled. Also disclosed are substrates having a deposited film with these controlled properties and devices, particularly MEMS and NEMS devices, having substrates with films having these properties.01-06-2011
20110001144SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A JFET is a semiconductor device allowing more reliable implementation of the characteristics essentially achievable by employing SiC as a material and includes a wafer having at least an upper surface made of silicon carbide, and a gate contact electrode formed on the upper surface. The wafer includes a first p-type region serving as an ion implantation region formed so as to include the upper surface. The first p-type region includes a base region disposed so as to include the upper surface, and a protruding region. The base region has a width (w01-06-2011
20110108855METHOD OF FORMING VIAS IN SILICON CARBIDE AND RESULTING DEVICES AND CIRCUITS - A method of fabricating an integrated circuit on a silicon carbide substrate is disclosed that eliminates wire bonding that can otherwise cause undesired inductance. The method includes fabricating a semiconductor device including a Group III-V semiconductor layer on a surface on a silicon carbide substrate, wherein the semiconductor device defines at least one via through the silicon carbide substrate and the epitaxial layer.05-12-2011
20110241021SILICON CARBIDE BARRIER DIODE - Improved semiconductor devices are fabricated utilizing nickel gallide and refractory borides deposited onto a silicon carbide semiconductor substrate. Varying the deposition and annealing parameters of fabrication can provide a more thermally stable device that has greater barrier height and a low ideality. This improvement in the electrical properties allows use of Schottky barrier diodes in high power and high temperature applications. In one embodiment, a refractory metal boride layer is joined to a surface of a silicon carbide semiconductor substrate. The refractory metal boride layer is deposited on the silicon carbon semiconductor substrate at a temperature greater than 200° C. In another embodiment, a Schottky barrier diode is fabricated via deposition of nickel gallide on a SiC substrate.10-06-2011
20110241020HIGH ELECTRON MOBILITY TRANSISTOR WITH RECESSED BARRIER LAYER - Embodiments of a high electron mobility transistor with recessed barrier layer, and methods of forming the same, are disclosed. Other embodiments are also be described and claimed.10-06-2011
20110018004SEMICONDUCTOR DEVICE WITH LARGE BLOCKING VOLTAGE AND MANUFACTURING METHOD THEREOF - There is no effective method for fabricating a semiconductor power device containing UMOSFET possessing large channel mobility and whose threshold voltage can be lowered with no loss in blocking voltage. A semiconductor device with large blocking voltage is provided utilizing silicon carbide trench MOSFET possessing both narrow regions where the p body concentration is low, and wide regions where the p body concentration is high.01-27-2011
20110108853COMPOUND SEMICONDUCTOR DEVICE - A compound semiconductor device having reduced contact resistance to an electrode is provided. The compound semiconductor device includes an n-substrate 05-12-2011
20110127545COMPOUND SEMICONDUCTOR DEVICE WITH T-SHAPED GATE ELECTRODE - A compound semiconductor device includes a compound semiconductor substrate; epitaxially grown layers formed over the compound semiconductor substrate and including a channel layer and a resistance lowering cap layer above the channel layer; source and drain electrodes in ohmic contact with the channel layer; recess formed by removing the cap layer between the source and drain electrodes; a first insulating film formed on an upper surface of the cap layer and having side edges at positions retracted from edges, or at same positions as the edges of the cap layer in a direction of departing from the recess; a second insulating film having gate electrode opening and formed covering a semiconductor surface in the recess and the first insulating film; and a gate electrode formed on the recess via the gate electrode opening.06-02-2011
20110024766ONE HUNDRED MILLIMETER SINGLE CRYSTAL SILICON CARBIDE WAFER - A method is disclosed for producing a high quality bulk single crystal of silicon carbide in a seeded growth system by reducing the separation between a silicon carbide seed crystal and a seed holder until the conductive heat transfer between the seed crystal and the seed holder dominates the radiative heat transfer between the seed crystal and the seed holder over substantially the entire seed crystal surface that is adjacent the seed holder.02-03-2011
20110024769SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes the steps of forming a SiC film, forming trenches at a surface of the SiC film, heat-treating the SiC film with silicon supplied to the surface of the SiC film, and obtaining a plurality of macrosteps to constitute channels, at the surface of the SiC film by the step of heat-treating. Taking the length of one cycle of the trenches as L and the height of the trenches as h, a relation L=h(cot α+cot β) (where α and β are variables that satisfy the relations 0.5≦α, β≦45) holds between the length L and the height h. Consequently, the semiconductor device can be improved in property.02-03-2011
20110024767Semiconductor Substrates, Devices and Associated Methods - Semiconductor substrates and devices having improved performance and cooling, as well as associated methods, are provided. In one aspect, for example, a semiconductor device can include a matrix layer and a plurality of single crystal semiconductor tiles disposed in the matrix layer. The plurality of semiconductor tiles are positioned such that an exposed surface of each of substantially all of the plurality of diamond tiles aligns along a common plane to form a substrate surface. In one aspect, a semiconductor layer is disposed on the substrate surface. In another aspect, the semiconductor layer is a doped diamond layer. In yet another aspect, the semiconductor tiles are doped. In a further aspect, the exposed surface of each of the plurality of semiconductor tiles has a common crystallographic orientation.02-03-2011
20110024765SILICON CARBIDE SEMICONDUCTOR STRUCTURES, DEVICES AND METHODS FOR MAKING THE SAME - There are provided semiconductor structures and devices comprising silicon carbide (SiC) and methods for making the same. The structures and devices comprise a base or shielding layer, channel and surface layer, all desirably formed via ion implantation. As a result, the structures and devices provided herein are hard, “normally off” devices, i.e., exhibiting threshold voltages of greater than about 3 volts.02-03-2011
20120032189ORGANOPOLYSILOXANE COMPOSITION AND SEMICONDUCTOR APPARATUS - Provided is an organopolysiloxane composition that provides a cured product which has excellent heat resistance and does not peel or crack even under high temperatures. The organopolysiloxane composition comprises (A) an organopolysiloxane having difunctional siloxane units (D units) and trifunctional siloxane units (T units), and a weight-average molecular weight of 37,000 to 140,000 in which the molar ratio (T/D) of the T units to the D units is 0.3 to 0.8; and (B) an organopolysiloxane having the difunctional siloxane units (D units) and the trifunctional siloxane units (T units), and a weight-average molecular weight of 1,000 to 60,000 in which the molar ratio (T/D) of the T units to the D units is 0.15 or less, the organopolysiloxane composition being characterized by having a molar ratio (B/A) of the organopolysiloxane (B) to the organopolysiloxane (A) of 1.5 to 6.5.02-09-2012
20110031503DEVICE WITH STRESSED CHANNEL - An FET device is disclosed which contains a source and a drain that are each provided with an extension. The source and the drain, and their extensions, are composed of epitaxial materials containing Ge or C. The epitaxial materials and the Si substrate have differing lattice constants, consequently the source and the drain and their extensions are imparting a state of stress onto the channel. For a PFET device the epitaxial material may be SiGe, or Ge, and the channel may be in a compressive state of stress. For an NFET device the epitaxial material may be SiC and the channel may be in a tensile state of stress. A method for fabricating an FET device is also disclosed. One may form a first recession in the Si substrate to a first depth on opposing sides of the gate. The first recession is filled epitaxially with a first epitaxial material. Then, a second recession may be formed in the Si substrate to a second depth, which is greater than the first depth. Next, one may fill the second recession with a second epitaxial material, which is the same kind of material as the first epitaxial material. The epitaxial materials are selected to have a different lattice constant than the Si substrate, and consequently a state of stress is being imparted onto the channel.02-10-2011
20110031505SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A silicon carbide semiconductor device having an active layer with reduced defect density which is formed on a substrate made of silicon carbide, and a method of manufacturing the same are provided. A semiconductor device includes a substrate made of silicon carbide and having an off angle of not less than 50° and not more than 65° with respect to a plane orientation; a buffer layer, and an epitaxial layer, a p-type layer and an n02-10-2011
20110031504Apparatus and method for increasing thermal conductivity of a substrate - An apparatus and method is disclosed for increasing the thermal conductivity in a substrate of a non-wide bandgap material comprising the steps of directing a thermal energy beam onto the substrate in the presence of a first doping gas for converting a region of the substrate into a wide bandgap material to enhance the thermal conductivity of the substrate for cooling the non-wide bandgap material. In one example, the invention is incorporated into a carbon rich layer formed within the wide bandgap material. In another example, the invention is incorporated into a carbon rich layer formed within the wide bandgap material having basal planes disposed to extend generally outwardly relative to an external surface of the substrate to enhance the cooling of the substrate.02-10-2011
20110031507SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A MOSFET representing a semiconductor device capable of achieving decrease in the number of steps in a manufacturing process and improvement in integration by including an electrode that can be in contact with any of a p-type SiC region and an n-type SiC region with contact resistance being sufficiently suppressed includes an n02-10-2011
20110031502LIGHT EMITTING DIODES INCLUDING INTEGRATED BACKSIDE REFLECTOR AND DIE ATTACH - Light emitting diodes include a silicon carbide substrate having first and second opposing faces, a diode region on the first face, anode and cathode contacts on the diode region opposite the silicon carbide substrate and a hybrid reflector on the silicon carbide substrate opposite the diode region. The hybrid reflector includes a transparent layer having an index of refraction that is lower than the silicon carbide substrate, and a reflective layer on the transparent layer, opposite the substrate. A die attach layer may be provided on the hybrid reflector, opposite the silicon carbide substrate. A barrier layer may be provided between the hybrid reflector and the die attach layer.02-10-2011
20110108854SUBSTANTIALLY LATTICE MATCHED SEMICONDUCTOR MATERIALS AND ASSOCIATED METHODS - Semiconductor devices having atomic lattice matching template interlayers are provided. In one aspect, a semiconductor device can include a first semiconductor material, a second semiconductor material disposed on the first semiconductor material, and an atomic template interlayer disposed between the first semiconductor material and the second semiconductor material, the atomic template interlayer bonding together and facilitating a substantial lattice matching between the first semiconductor material and the second semiconductor material.05-12-2011
20130153924PIEZOELECTRIC DEVICES AND METHODS FOR THEIR PREPARATION AND USE - Methods for fabricating a piezoelectric device are provided. The methods can include providing a substrate and forming a nanocrystalline diamond layer on a first surface of the substrate. The methods can also include depositing a piezoelectric layer on a first surface of the nanocrystalline diamond layer.06-20-2013
20130153927SEMICONDUCTOR DEVICES HAVING STRESSOR REGIONS AND RELATED FABRICATION METHODS - Apparatus for semiconductor device structures and related fabrication methods are provided. One method for fabricating a semiconductor device structure involves forming a gate structure overlying a region of semiconductor material, wherein the width of the gate structure is aligned with a <100> crystal direction of the semiconductor material. The method continues by forming recesses about the gate structure and forming a stress-inducing semiconductor material in the recesses.06-20-2013
20130153930PHENYL GROUP-CONTAINING ORGANIC/INORGANIC HYBRID PREPOLYMER, HEAT RESISTANT ORGANIC/INORGANIC HYBRID MATERIAL, AND ELEMENT ENCAPSULATION STRUCTURE - The object of the present invention is to provide an organic-inorganic hybrid material having heat resistance, and said object of the present invention can be attained by providing an organic-inorganic hybrid prepolymer containing a phenyl group which is prepared by the polycondensation reaction accompanying dehydration between a polydimethylsiloxane and a metal and/or semimetal alkoxide, wherein (a) phenyl group(s) is (are) partially or wholly introduced into said polydimethylsiloxane and/or said metal and/or semimetal alkoxide.06-20-2013
20130153931N-DOPED SINGLE CRYSTAL DIAMOND SUBSTRATES AND METHODS THEREFOR - The disclosure relates to the formation of n-doped single crystal diamond (SCD). In general, a SCD substrate is preferentially anisotropically etched to provide one or more recesses in the SCD substrate, where the recesses are defined by (06-20-2013
20110114968Integrated Nitride and Silicon Carbide-Based Devices - A monolithic electronic device includes a first nitride epitaxial structure including a plurality of nitride epitaxial layers. The plurality of nitride epitaxial layers include at least one common nitride epitaxial layer. A second nitride epitaxial structure is on the common nitride epitaxial layer of the first nitride epitaxial structure. A first plurality of electrical contacts is on the first epitaxial nitride structure and defines a first electronic device in the first nitride epitaxial structure. A second plurality of electrical contacts is on the first epitaxial nitride structure and defines a second electronic device in the second nitride epitaxial structure. A monolithic electronic device includes a bulk semi-insulating silicon carbide substrate having implanted source and drain regions and an implanted channel region between the source and drain regions, and a nitride epitaxial structure on the surface of the silicon carbide substrate. Corresponding methods are also disclosed.05-19-2011
20110084284Transistors with Semiconductor Interconnection Layers and Semiconductor Channel Layers of Different Semiconductor Materials - A transistor may include a semiconductor drift layer of a first semiconductor material and a semiconductor channel layer on the semiconductor drift layer. The semiconductor channel layer may include a second semiconductor material different than the first semiconductor material. A semiconductor interconnection layer may be electrically coupled between the semiconductor drift layer and the semiconductor channel layer, and the semiconductor interconnection layer may include a third semiconductor material different than the first and second semiconductor materials. In addition, a control electrode may be provided on the semiconductor channel layer.04-14-2011
20110210341P-TYPE SiC SEMICONDUCTOR - A p-type SiC semiconductor includes a SiC crystal that contains Al and Ti as impurities, wherein the atom number concentration of Ti is equal to or less than the atom number concentration of Al. It is preferable that the concentration of Al and the concentration of Ti satisfy the following relations: (Concentration of Al)≧5×1009-01-2011
20090072243Compound semiconductor device and method for fabricating compound semiconductor - In the present invention, a technology for causing arbitrary polarity, crystal face and crystal orientation to exist mixedly in a plane on the surface of a SiC substrate, and for forming a SiC layer or a group III-nitride or group II-oxide layer on the surface, is provided. A first SiC substrate 03-19-2009
20090032821SEMICONDUCTOR DEVICE AND ELECTRICAL CIRCUIT DEVICE USING THEREOF - A UMOSFET is capable of reducing a threshold voltage and producing a large saturation current. A typical UMOSFET according to the present invention includes: an N02-05-2009
20100032685MESA TERMINATION STRUCTURES FOR POWER SEMICONDUCTOR DEVICES AND METHODS OF FORMING POWER SEMICONDUCTOR DEVICES WITH MESA TERMINATION STRUCTURES - An electronic device includes a drift layer having a first conductivity type, a buffer layer having a second conductivity type, opposite the first conductivity type, on the drift layer and forming a P—N junction with the drift layer, and a junction termination extension region having the second conductivity type in the drift layer adjacent the P—N junction. The buffer layer includes a step portion that extends over a buried portion of the junction termination extension. Related methods are also disclosed.02-11-2010
20100032686Bipolar Semiconductor Device, Method for Producing the Same, and Method for Controlling Zener Voltage - Bipolar semiconductor devices have a Zener voltage controlled very precisely in a wide range of Zener voltages (for example, from 10 to 500 V). A bipolar semiconductor device has a mesa structure and includes a silicon carbide single crystal substrate of a first conductivity type, a silicon carbide conductive layer of a first conductivity type, a highly doped layer of a second conductivity type and a silicon carbide conductive layer of a second conductivity type which substrate and conductive layers are laminated in the order named.02-11-2010
20110079791BETAVOLTAIC CELL - High aspect ratio micromachined structures in semiconductors are used to improve power density in Betavoltaic cells by providing large surface areas in a small volume. A radioactive beta-emitting material may be placed within gaps between the structures to provide fuel for a cell. The pillars may be formed of SiC. In one embodiment, SiC pillars are formed of n-type SiC. P type dopant, such as boron is obtained by annealing a borosilicate glass boron source formed on the SiC. The glass is then removed. In further embodiments, a dopant may be implanted, coated by glass, and then annealed. The doping results in shallow planar junctions in SiC.04-07-2011
20090078943NITRIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A nitride semiconductor device mainly made of a nitride semiconductor material having excellent heat dissipation characteristics and great crystallinity and a method for manufacturing thereof are provided. The method for manufacturing the nitride semiconductor includes vapor-depositing a diamond layer on a silicon substrate, bonding an SOI substrate on a surface of the diamond layer, thinning the SOI substrate, epitaxially growing an GaN layer on the thinned SOI substrate, removing the silicon substrate, and bonding, on a rear-surface of the diamond layer, a material having a thermal conductivity greater than a thermal conductivity of the silicon substrate. The SOI substrate has an outermost surface layer and a silicon oxide layer. In the thinning, the SOI substrate is thinned by selectively removed through the silicon oxide layer, so that only the outermost surface layer is left.03-26-2009
20100219418DIAMOND LED DEVICES AND ASSOCIATED METHODS - LED devices incorporating diamond materials and methods for making such devices are provided. One such method may include forming epitaxially a substantially single crystal SiC layer on a substantially single crystal Si wafer, forming epitaxially a substantially single crystal diamond layer on the SiC layer, doping the diamond layer to form a conductive diamond layer, removing the Si wafer to expose the SiC layer opposite to the conductive diamond layer, forming epitaxially a plurality of semiconductor layers on the SiC layer such that at least one of the semiconductive layers contacts the SiC layer, and coupling an n-type electrode to at least one of the semiconductor layers such that the plurality of semiconductor layers is functionally located between the conductive diamond layer and the n-type electrode.09-02-2010
20100219417SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device and a method of manufacturing the same, to appropriately determine an impurity concentration distribution of a field relieving region and reduce an ON-resistance. The semiconductor device includes a substrate, a first drift layer, a second drift layer, a first well region, a second well region, a current control region, and a field relieving region. The first well region is disposed continuously from an end portion adjacent to the vicinity of outer peripheral portion of the second drift layer to a portion of the first drift layer below the vicinity of outer peripheral portion. The field relieving region is so disposed in the first drift layer as to be adjacent to the first well region.09-02-2010
20110079792SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SEMICONDUCTOR DEVICE - Provided are a semiconductor device and a method of fabricating the semiconductor device, the semiconductor device including: a source trace, a drain trace, and a gate trace placed on a substrate; a transistor which is placed on the drain trace and includes a source pad and a gate pad; insulating films placed between the drain and source traces and between the drain and gate traces on the substrate so as to cover sidewall surfaces of the transistor; a source spray electrode which is placed on the insulating film between the source and drain traces and connects the source pad of the transistor and the source trace; and a gate spray electrode placed on the insulating film between the gate and drain traces and connects the gate pad of the transistor and the gate trace.04-07-2011
20110210342SILICON CARBIDE SUBSTRATE AND METHOD OF MANUFACTURING SILICON CARBIDE SUBSTRATE - A SiC substrate includes a first orientation flat parallel to the <11-20> direction, and a second orientation flat being in a direction intersecting the first orientation flat and being different from the first orientation flat in length. An alternative SiC substrate has a rectangular plane shape, and a main surface of the substrate includes a first side parallel to the <11-20> direction, a second side in a direction perpendicular to the first side, and a third side connecting the first side to the second side. A length of the third side projected in a direction in which the first side extends is different from a length of the third side projected in a direction in which the second side extends.09-01-2011
20110210340HIGH TEMPERATURE GATE DRIVERS FOR WIDE BANDGAP SEMICONDUCTOR POWER JFETS AND INTEGRATED CIRCUITS INCLUDING THE SAME - Gate drivers for wide bandgap (e.g., >2 eV) semiconductor junction field effect transistors (JFETs) capable of operating in high ambient temperature environments are described. The wide bandgap (WBG) semiconductor devices include silicon carbide (SiC) and gallium nitride (GaN) devices. The driver can be a non-inverting gate driver which has an input, an output, a first reference line for receiving a first supply voltage, a second reference line for receiving a second supply voltage, a ground terminal, and six Junction Field-Effect Transistors (JFETs) wherein the first JFET and the second JFET form a first inverting buffer, the third JFET and the fourth JFET form a second inverting buffer, and the fifth JFET and the sixth JFET form a totem pole which can be used to drive a high temperature power SiC JFET. An inverting gate driver is also described.09-01-2011
20110210339SEMICONDUCTOR DEVICE - A semiconductor device including a non-volatile memory cell including a writing transistor which includes an oxide semiconductor, a reading transistor which includes a semiconductor material different from that of the writing transistor, and a capacitor is provided. Data is written or rewritten to the memory cell by turning on the writing transistor and supplying a potential to a node where a source electrode (or a drain electrode) of the writing transistor, one electrode of the capacitor, and a gate electrode of the reading transistor are electrically connected to each other, and then turning off the writing transistor so that the predetermined amount of charge is held in the node. Further, when a transistor whose threshold voltage is controlled and set to a positive voltage is used as the reading transistor, a reading potential is a positive potential.09-01-2011
20100012952Nitride-Based Transistors Having Laterally Grown Active Region and Methods of Fabricating Same - High electron mobility transistors and/or methods of fabricating high electron mobility transistors that include a first Group III-nitride layer having vertically grown regions, laterally grown regions and a coalescence region are provided. A Group III-nitride channel layer is provided on the first Group III-nitride layer and a Group III-nitride barrier layer is provided on the Group III-nitride channel layer. A drain contact, a source contact and a gate contact are provided on the barrier layer. The gate contact is disposed on a portion of the barrier layer on a laterally grown region of the first Group III-nitride layer and at least a portion of one of the source contact and/or the drain contact is disposed on a portion of the barrier layer on a vertically grown region of the first Group III-nitride layer.01-21-2010
20090321747MULTILAYERED SEMICONDUCTOR WAFER AND PROCESS FOR MANUFACTURING THE SAME - The invention relates to a process for manufacturing a multilayered semiconductor wafer comprising a handle wafer (12-31-2009
20090218579SUBSTRATE HEATING APPARATUS, SEMICONDUCTOR DEVICE MANUFACTURING METHOD, AND SEMICONDUCTOR DEVICE - In a substrate heating apparatus, thermoelectrons generated by a filament (09-03-2009
20090039357STACKED NON-VOLATILE MEMORY WITH SILICON CARBIDE-BASED AMORPHOUS SILICON THIN FILM TRANSISTORS - A stacked non-volatile memory device uses amorphous silicon based thin film transistors stacked vertically. Each layer of transistors or cells is formed from a deposited a-Si channel region layer having a predetermined concentration of carbon to form a carbon rich silicon film or silicon carbide film, depending on the carbon content. The dielectric stack is formed over the channel region layer. In one embodiment, the dielectric stack is an ONO structure. The control gate is formed over the dielectric stack. This structure is repeated vertically to form the stacked structure. In one embodiment, the carbon content of the channel region layer is reduced for each subsequently formed layer.02-12-2009
20120146051NITRIDE BASED SEMICONDUCTOR DEVICE - Disclosed herein is a nitride based semiconductor device. There is provided a nitride based semiconductor device including a base substrate; a semiconductor layer disposed on the base substrate; and an electrode structure disposed on the semiconductor layer, wherein the electrode structure includes: a first ohmic electrode ohmic-contacting the semiconductor layer; a second ohmic electrode ohmic-contacting the semiconductor layer and spaced apart from the first ohmic electrode; and a schottky electrode unit schottky-contacting the semiconductor layer and covering the second ohmic electrode.06-14-2012
20100012951Silicon carbide semiconductor device and method for producing the same - In an SiC vertical MOSFET comprising a channel region and an n-type inverted electron guide path formed through ion implantation in a low-concentration p-type deposition film, the width of the channel region may be partly narrowed owing to implantation mask positioning failure, and the withstand voltage of the device may lower, and therefore, the device could hardly satisfy both low on-resistance and high withstand voltage. In the invention, second inverted layers (01-21-2010
20100012950CRACKSTOP STRUCTURES AND METHODS OF MAKING SAME - An integrated circuit chip and a method of fabricating an integrated circuit chip. The integrated circuit chip includes: a set of wiring levels stacked from a first wiring level to a last wiring level; and a respective void in each wiring level of two or more wiring levels of the set wiring levels, each respective void extending in a continuous ring parallel and proximate to a perimeter of the integrated circuit chip, a void of a higher wiring level stacked directly over but not contacting a void of a lower wiring level, the respective voids forming a crack stop.01-21-2010
20100038653DIAMOND ELECTRONIC DEVICES AND METHODS FOR THEIR MANUFACTURE - The present invention relates to a diamond electronic device comprising a functional interface between two solid materials, wherein the interface is formed by a planar first surface of a first layer of single crystal diamond and a second layer formed on the first surface of the first diamond layer, the second layer being solid, non-metallic and selected from diamond, a polar material and a dielectric material, and wherein the planar first surface of the first layer of single crystal diamond has an Rq of less than 10 nm and has at least one of the following characteristics: (a) the first surface is an etched surface; (b) a density of dislocations in the first diamond layer breaking the first surface is less than 400 cm02-18-2010
20110175111SILICON CARBIDE SEMICONDUCTOR DEVICE - Provided is a silicon carbide semiconductor device capable of lowering the contact resistance of an ohmic electrode and achieving high reverse breakdown voltage characteristics. A semiconductor device includes a substrate and a p07-21-2011
20110175108LIGHT-EMITTING DEVICE - A silicon carbide substrate has a first layer facing a semiconductor layer and a second layer stacked on the first layer. Dislocation density of the second layer is higher than dislocation density of the first layer. Thus, quantum efficiency and power efficiency of a light-emitting device can both be high.07-21-2011
20100059763LUMINOUS ELEMENT HAVING A PLURALITY OF CELLS - Disclosed is a light emitting element comprising a first array having a plurality of vertical light emitting cells connected in series on a single substrate; and a second array that has another plurality of vertical light emitting cells connected in series on the single substrate and is connected to the first array in reverse parallel. In the light emitting element, each of the vertical light emitting cells in the first and second arrays has a first electrode pad on a bottom surface thereof and a second electrode pad on a top surface thereof, and a connection portion is provided to electrically connect the first electrode pad of the vertical light emitting cell in the first array to the first electrode pad of the vertical light emitting cell in the second array.03-11-2010
20100059764STRUCTURE AND METHOD TO FORM MULTILAYER EMBEDDED STRESSORS - A multilayer embedded stressor having a graded dopant profile for use in a semiconductor structure for inducing strain on a device channel region is provided. The inventive multilayer stressor is formed within areas of a semiconductor structure in which source/drain regions are typically located. The inventive multilayer stressor includes a first conformal epi semiconductor layer that is undoped or lightly doped and a second epi semiconductor layer that is highly dopant relative to the first epi semiconductor layer. The first and second epi semiconductor layers each have the same lattice constant, which is different from that of the substrate they are embedded in. The structure including the inventive multilayer embedded stressor achieves a good balance between stress proximity and short channel effects, and even eliminates or substantially reduces any possible defects that are typically generated during formation of the deep source/drain regions.03-11-2010
20110101378SEMICONDUCTOR DEVICES HAVING TENSILE AND/OR COMPRESSIVE STRAIN AND METHODS OF MANUFACTURING AND DESIGN STRUCTURE - A semiconductor device having a tensile and/or compressive strain applied thereto and methods of manufacturing the semiconductor devices and design structure to enhance channel strain. The method includes forming a gate structure for an NFET and a PFET and forming sidewalls on the gate structure for the NFET and the PFET using a same deposition and etching process. The method also includes providing stress materials in the source and drain regions of the NFET and the PFET.05-05-2011
20100065857SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A silicon carbide semiconductor device having excellent performance characteristics and a method of manufacturing the same are obtained. A coating film made of Si is formed on an initial growth layer on a 4H—SiC substrate, and an extended terrace surface is formed in a region covered with the coating film. Next, the coating film is removed, and a new growth layer is epitaxially grown on the initial growth layer. A 3C—SiC portion made of 3C—SiC crystals having a polytype stable at a low temperature is grown on the extended terrace surface of the initial growth layer. A channel region of a MOSFET or the like is provided in the 3C—SiC portion having a narrow band gap. As a result, the channel mobility is improved because of a reduction in an interface state, and a silicon carbide semiconductor device having excellent performance characteristics is obtained.03-18-2010
20110175110MOSFET AND METHOD FOR MANUFACTURING MOSFET - A MOSFET includes a silicon carbide (SiC) substrate having a main surface having an off angle of not less than 50° and not more than 65° relative to a {0001} plane; a semiconductor layer formed on the main surface of the SiC substrate; and an insulating film formed in contact with a surface of the semiconductor layer. When the insulating film has a thickness of not less than 30 nm and not more than 46 nm, the threshold voltage thereof is not more than 2.3V. When the insulating film has a thickness of more than 46 nm and not more than 100 nm, the threshold voltage thereof is more than 2.3 V and not more than 4.9 V.07-21-2011
20110101375Power Semiconductor Devices Having Selectively Doped JFET Regions and Related Methods of Forming Such Devices - Semiconductor switching devices include a wide band-gap drift layer having a first conductivity type (e.g., n-type), and first and second wide band-gap well regions having a second conductivity type (e.g., p-type) on the wide band-gap drift layer. First and second wide band-gap source/drain regions of the first conductivity type are on the first and second wide band-gap well regions, respectively. A wide band-gap JFET region having the first conductivity type is provided between the first and second well regions. This JFET region includes a first local JFET region that is adjacent a side surface of the first well region and a second local JFET region that is adjacent a side surface of the second well region. The local JFET regions have doping concentrations that exceed a doping concentration of a central portion of the JFET region that is between the first and second local JFET regions of the JFET region.05-05-2011
20110068351Method of Forming Three Dimensional Features on Light Emitting Diodes for Improved Light Extraction - A method is disclosed for obtaining a high-resolution lenticular pattern on the surface of a light emitting diode. The method comprises imprinting a patterned sacrificial layer of etchable material that is positioned on a semiconductor surface that is in turn adjacent a light emitting active region, and thereafter etching the imprinted sacrificial layer and the underlying semiconductor to transfer an imprinted pattern into the semiconductor layer adjacent the light emitting active region.03-24-2011
20110101376Optically-Initiated Silicon Carbide High Voltage Switch - An improved photoconductive switch having a SIC or other wide band gap substrate material, such as GaAs and field-grading liners composed of preferably SiN formed on the substrate adjacent the electrode perimeters or adjacent the substrate perimeters for grading the electric fields.05-05-2011
20110101377HIGH TEMPERATURE ION IMPLANTATION OF NITRIDE BASED HEMTS - A method is disclosed for forming a high electron mobility transistor. The method includes the steps of implanting a Group III nitride layer at a defined position with ions that when implanted produce an improved ohmic contact between the layer and contact metals, with the implantation being carried out at a temperature higher than room temperature and hot enough to reduce the amount of damage done to the Group III nitride layer, but below a temperature at which surface problems causing leakage at the gate or epitaxial layer dissociation would occur. An ohmic contact selected from the group consisting of titanium, aluminum, nickel and alloys thereof is added to the implanted defined position on the Group III nitride layer.05-05-2011
20110068353SEMICONDUCTOR DEVICE - A semiconductor device (A03-24-2011
20110068352DIAMOND SEMICONDUCTOR ELEMENT AND PROCESS FOR PRODUCING THE SAME - An integrated optical waveguide has a first optical waveguide, a second optical waveguide, and a groove. The second optical waveguide is coupled to the first optical waveguide and has a refractive index that is different from the first optical waveguide. The groove is disposed so as to traverse an optical path of the first optical waveguide and is separated from an interface between the first optical waveguide and the second optical waveguide by a predetermined spacing. The spacing from the interface and the width of the groove are determined such that reflection at a boundary between the first optical waveguide and the second optical waveguide is weakened. A semiconductor board may be disposed at a boundary between the first optical waveguide and the second optical waveguide. In this case, the width of the groove and the thickness of the semiconductor board are determined such that light reflected off an interface between the first optical waveguide and the groove is weakened by light reflected from an interface between the groove and the semiconductor board, and by light reflected from an interface between the semiconductor board and the second optical waveguide.03-24-2011
20090026466QUASI SINGLE CRYSTAL NITRIDE SEMICONDUCTOR LAYER GROWN OVER POLYCRYSTALLINE SiC SUBSTRATE - A compound semiconductor device is manufactured by using a polycrystalline SiC substrate, the compound semiconductor device having a buffer layer being formed on the substrate and having a high thermal conductivity of SiC and aligned orientations of crystal axes. The method for manufacturing the compound semiconductor device includes: forming a mask pattern on a polycrystalline SiC substrate, the mask pattern having an opening of a stripe shape defined by opposing parallel sides or a hexagonal shape having an apex angle of 120 degrees and exposing the surface of the polycrystalline SiC substrate in the opening; growing a nitride semiconductor buffer layer, starting growing on the polycrystalline SiC substrate exposed in the opening of the mask pattern, burying the mask pattern, and having a flat surface; and growing a GaN series compound semiconductor layer on the nitride semiconductor buffer layer.01-29-2009
20110031506SEMICONDUCTOR DEVICE - A MOSFET capable of achieving decrease in the number of steps in a manufacturing process and improvement in integration includes an SiC wafer composed of silicon carbide and a source contact electrode arranged in contact with the SiC wafer and containing titanium, aluminum, silicon, and carbon as well as a remaining inevitable impurity. The SiC wafer includes an n02-10-2011
20100295059SIC SINGLE-CRYSTAL SUBSTRATE AND METHOD OF PRODUCING SIC SINGLE-CRYSTAL SUBSTRATE - The invention provides a high-quality SiC single-crystal substrate, a seed crystal for producing the high-quality SiC single-crystal substrate, and a method of producing the high-quality SiC single-crystal substrate, which enable improvement of device yield and stability. Provided is an SiC single-crystal substrate wherein, when the SiC single-crystal substrate is divided into 5-mm square regions, such regions in which dislocation pairs or dislocation rows having intervals between their dislocation end positions of 5 μm or less are present among the dislocations that have ends at the substrate surface account for 50% or less of all such regions within the substrate surface and the dislocation density in the substrate of dislocations other than the dislocation pairs or dislocation is 8,000/cm11-25-2010
20130161646SEMICONDUCTOR SUBSTRATE - A semiconductor substrate has a main surface and formed of single crystal silicon carbide. The main surface includes a central area, which is an area other than the area within 5 mm from the outer circumference. When the central area is divided into square areas of 1 mm×1 mm, in any square area, density of dislocations of which Burgers vector is parallel to <0001> direction is at most 1×1006-27-2013
20130161644SEMICONDUCTOR MODULE - Provided is a semiconductor module having high inrush-current tolerance. A semiconductor module includes a switching element formed of a wide bandgap semiconductor, and a free wheel diode connected in antiparallel with the switching element, wherein the free wheel diode is made of silicon and has negative temperature characteristics.06-27-2013
20110248286SEMICONDUCTOR DEVICE - For suggesting a structure capable of achieving both a low start-up voltage and high breakdown voltage, a SiC vertical diode includes a cathode electrode, an n10-13-2011
20110248285SEMICONDUCTOR DEVICES INCLUDING SCHOTTKY DIODES HAVING OVERLAPPING DOPED REGIONS AND METHODS OF FABRICATING SAME - A semiconductor device includes a semiconductor layer having a first conductivity type and having a surface in which an active region of the semiconductor device is defined, and a plurality of spaced apart doped regions within the active region. The plurality of doped regions have a second conductivity type that is opposite the first conductivity type and define a plurality of exposed portions of the semiconductor layer within the active region. The plurality of doped regions include a plurality of rows extending in a longitudinal direction. Each of the rows includes a plurality of longitudinally extending segments, and the longitudinally extending segments in a first row at least partially overlap the longitudinally extending segments in an adjacent row in a lateral direction that is perpendicular to the longitudinal direction.10-13-2011
20110248284SCHOTTKY DIODE WITH IMPROVED SURGE CAPABILITY - An SiC Schottky diode die or a Si Schottky diode die is mounted with its epitaxial anode surface connected to the best heat sink surface in the device package. This produces a substantial increase in the surge current capability of the device.10-13-2011
20100295062SEMICONDUCTOR ELEMENT AND MANUFACTURING METHOD THEREFOR - A semiconductor device includes: a semiconductor layer including silicon carbide, which has been formed on a substrate; a semiconductor region 11-25-2010
20100244047Methods of Forming Semiconductor Devices Including Epitaxial Layers and Related Structures - A method of forming a semiconductor device may include forming a terminal region of a first conductivity type within a semiconductor layer of the first conductivity type. A well region of a second conductivity type may be formed within the semiconductor layer wherein the well region is adjacent at least portions of the terminal region within the semiconductor layer, a depth of the well region into the semiconductor layer may be greater than a depth of the terminal region into the semiconductor layer, and the first and second conductivity types may be different. An epitaxial semiconductor layer may be formed on the semiconductor layer, and a terminal contact region of the first conductivity type may be formed in the epitaxial semiconductor layer with the terminal contact region providing electrical contact with the terminal region. In addition, an ohmic contact may be formed on the terminal contact region. Related structures are also discussed.09-30-2010
20100244049Silicon carbide semiconductor device with schottky barrier diode and method of manufacturing the same - A silicon carbide semiconductor device with a Schottky barrier diode includes a first conductivity type silicon carbide substrate, a first conductivity type silicon carbide drift layer on a first surface of the substrate, a Schottky electrode forming a Schottky contact with the drift layer, and an ohmic electrode on a second surface of the substrate. The Schottky electrode includes an oxide layer in direct contact with the drift layer. The oxide layer is made of an oxide of molybdenum, titanium, nickel, or an alloy of at least two of these elements.09-30-2010
20100264426DIAMOND CAPACITOR BATTERY - In one embodiment, a charge storage device can include: a first node having a plurality of n-type diamond layers connected together; and a second node having a plurality of p-type diamond layers connected together, the plurality of p-type diamond layers being interleaved with the plurality of n-type diamond layers, where each of the plurality of diamond layers is formed using chemical vapor deposition (CVD).10-21-2010
20100252838Semiconductor device and method of manufacturing the same - A semiconductor device provided with a silicon carbide semiconductor substrate, and an ohmic metal layer joined to one surface of the silicon carbide semiconductor substrate in an ohmic contact and composed of a metal material whose silicide formation free energy and carbide formation free energy respectively take negative values. The ohmic metal layer is composed of, for example, a metal material such as molybdenum, titanium, chromium, manganese, zirconium, tantalum, or tungsten.10-07-2010
20100244052HIGH OUTPUT GROUP III NITRIDE LIGHT EMITTING DIODES - A light emitting diode is disclosed that includes a silicon carbide substrate and a light emitting structure formed from the Group III nitride material system on the substrate. The diode has an area greater than 100,000 square microns and has a radiant flux at 20 milliamps current of at least 29 milliwatts at its dominant wavelength between 390 and 540 nanometers.09-30-2010
20100244051Semiconductor Device and Manufacturing Method Thereof - An object is to realize an integrated circuit included in a semiconductor device which has multiple functions, or to increase the size of an integrated circuit even when the integrated circuit is formed using a silicon carbide substrate. The integrated circuit includes a first transistor including an island-shaped silicon carbide layer provided over a substrate with a first insulating layer interposed therebetween, a first gate insulating layer provided over the silicon carbide layer, and a first conductive layer provided over the first gate insulating layer and overlapped with the silicon carbide layer; and a second transistor including an island-shaped single crystal silicon layer provided over the substrate with a second insulating layer interposed therebetween, a second gate insulating layer provided over the single crystal silicon layer, and a second conductive layer provided over the second gate insulating layer and overlapped with the single crystal silicon layer.09-30-2010
20100244050SEMICONDUCTOR DEVICE - A semiconductor device which is capable of operating at an operation frequency “f”, includes a substrate, a first element unit and a second element unit. The substrate has a thermal diffusion coefficient “D”. The first element unit is formed on the substrate. The first element includes a first active element. The second element unit is adjacent to the first element unit on the substrate. The second element includes a second active element. The second active element acts on a different timing from the first active element. Moreover, a distance of between a first gravity center of the first element unit and a second gravity center of the second element unit is equal to or less than twice of a thermal diffusion length (D/πf)09-30-2010
20100244048SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device according to the present invention comprises a silicon carbide semiconductor substrate (09-30-2010
20090001384Group III Nitride semiconductor HFET and method for producing the same - Provided is an HFET exhibiting reduced buffer leakage current. The HFET of the present invention includes an SiC substrate, an AlN layer, a graded AlGaN layer, a GaN layer, an AlGaN layer (Al compositional proportion: 20%), a source electrode, a gate electrode, and a drain electrode, wherein the AlN layer, the graded AlGaN layer, the GaN layer, and the AlGaN (Al: 20%) layer are successively stacked on the substrate, and the electrodes are formed on the AlGaN (Al: 20%) layer so as to be separated from one another. In the graded AlGaN layer, the Al compositional proportion gradually decreases from 30% (at the side facing the AlN layer) to 5% (at the side facing the GaN layer). Provision of the graded AlGaN layer reduces strain between the AlN layer and the GaN layer. Therefore, the HFET exhibits reduced buffer leakage current.01-01-2009
20090001383Doped Diamond LED Devices and Associated Methods - LED devices and methods for making such devices are provided. One such method may include forming epitaxially a substantially single crystal SiC layer on a substantially single crystal Si wafer, forming epitaxially a substantially single crystal diamond layer on the SiC layer, doping the diamond layer to form a conductive diamond layer, removing the Si wafer to expose the SiC layer opposite to the conductive diamond layer, forming epitaxially a plurality of semiconductor layers on the SiC layer such that at least one of the semiconductive layers contacts the SiC layer, and coupling an n-type electrode to at least one of the semiconductor layers such that the plurality of semiconductor layers is functionally located between the conductive diamond layer and the n-type electrode.01-01-2009
20110254019ADAPTED SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor light-emitting device with light-modulating function and a method of fabrication the same are provided. The semiconductor light-emitting device as provided includes a light-emitting layer and a super-paramagnetic layer. The light-emitting layer functions for emitting a first light. In particular, a portion or most of the first light is modulated by the super-paramagnetic layer into a second light when the first light passes through the super-paramagnetic layer. In some embodiments, the semiconductor light-emitting device is designed in such a way that a portion of the first light, which is not modulated into the second light, blends with the second light into a third light, e.g., a white light.10-20-2011
20120267642Nitride semicondutor device and manufacturing method thereof - Provided is a nitride semiconductor device including: a nitride semiconductor layer over a substrate wherein the nitride semiconductor has a two-dimensional electron gas (2DEG) channel inside; a drain electrode in ohmic contact with the nitride semiconductor layer; a source electrode in Schottky contact with the nitride semiconductor layer wherein the source electrode is spaced apart from the drain electrode; a dielectric layer formed on the nitride semiconductor layer between the drain electrode and the source electrode and on at least a portion of the source electrode; and a gate electrode disposed on the dielectric layer to be spaced apart from the drain electrode, wherein a portion of the gate electrode is formed over a drain-side edge portion of the source electrode with the dielectric layer interposed therebetween, and a manufacturing method thereof.10-25-2012
20080246041METHOD OF FABRICATING SOI nMOSFET AND THE STRUCTURE THEREOF - A method of fabricating a silicon-on-insulator (SOI) N-channel metal oxide semiconductor field effect transistor (nMOSFET), where the transistor has a structure incorporating a gate disposed above a body of the SOI substrate. The body comprises of a first surface and a second surface. The second surface interfaces between the body and the insulator of the SOI. Between the first surface and second surface is defined a channel region separating a source region and a drain region. Each of the source region and drain region includes a third surface under which is embedded crystalline silicon-carbon (Si:C), which extends from the second surface to the third surface.10-09-2008
20080315211SIC semiconductor device with BPSG insulation film and method for manufacturing the same - A SiC device includes: a substrate; a drift layer; a base region; a source region; a channel layer connecting the drift layer and the source region; a gate oxide film on the channel layer and the source region; a gate electrode on the gate oxide film; an interlayer insulation film with a contact hole having a barrier layer and a BPSG insulation film on the gate electrode; a source electrode having upper and lower wiring electrodes on the interlayer insulation film and in the contact hole for connecting the base region and the source region; and a drain electrode on the substrate. The barrier layer prevents a Ni component in the lower wiring electrode from being diffused into the BPSG insulation film.12-25-2008
20120199846SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor device of an embodiment at least includes: a SiC substrate; and a gate insulating film formed on the SiC substrate, wherein at an interface between the SiC substrate and the gate insulating film, some of elements of both of or one of Si and C in an outermost surface of the SiC substrate are replaced with at least one type of element selected from nitrogen, phosphorus, and arsenic.08-09-2012
20110175106SEMICONDUCTOR RECTIFIER - A semiconductor rectifier includes: a wide bandgap semiconductor substrate of a first conductivity type; a wide bandgap semiconductor layer of the first conductivity type which is formed on an upper surface of the wide bandgap semiconductor substrate and has an impurity concentration of 1E+14 atoms/cm07-21-2011
20090085044SILICON CARBIDE SEMICONDUCTOR SUBSTRATE AND SILICON CARBIDE SEMICONDUCTOR DEVICE BY USING THEREOF - A manufacturing method is provided for a silicon carbide semiconductor substrate adapted for reduced basal plane dislocations in a silicon carbide epitaxial layer. Between a silicon carbide epitaxial layer for device fabrication (i.e., a drift layer) and a base substrate formed of a silicon carbide single-crystal wafer, a highly efficient dislocation conversion layer through which any basal plane dislocations in the silicon carbide single-crystal wafer are converted into threading edge dislocations very efficiently when the dislocations propagate into the layer epitaxially grown is provided by epitaxial growth. Assigning to the dislocation conversion layer a donor concentration lower than that of the drift layer, therefore, allows the above conversion of a larger number of basal plane dislocations than the case where the drift layer exists alone (without the dislocation conversion layer).04-02-2009
20090050902SEMICONDUCTOR DEVICE HAVING SILICON CARBIDE AND CONDUCTIVE PATHWAY INTERFACE - The present invention provides semiconductor device formed by an in situ plasma reducing process to reduce oxides or other contaminants, using a compound of nitrogen and hydrogen, typically ammonia, at relatively low temperatures prior to depositing a subsequent layer thereon. The adhesion characteristics of the layers are improved and oxygen presence is reduced compared to the typical physical sputter cleaning process of an oxide layer. This process may be particularly useful for the complex requirements of a dual damascene structure, especially with copper applications.02-26-2009
20080283845Silicon carbide semiconductor device having high channel mobility and method for manufacturing the same - A silicon carbide semiconductor device having a MOS structure includes: a substrate; a channel area in the substrate; a first impurity area; a second impurity area; a gate insulating film on the channel area; and a gate on the gate insulating film. The channel area provides an electric current path. The channel area and the gate insulating film have an interface therebetween. The interface includes a dangling bond, which is terminated by a hydrogen atom or a hydroxyl. The interface has a hydrogen concentration equal to or larger than 2.6×1011-20-2008
20110175109FILM OF N TYPE (100) ORIENTED SINGLE CRYSTAL DIAMOND SEMICONDUCTOR DOPED WITH PHOSPHOROUS ATOMS, AND A METHOD OF PRODUCING THE SAME - There is provided an n type (100) oriented single crystal diamond semiconductor film into which phosphorous atoms have been doped and a method of producing the same. The n type (100) oriented single crystal diamond semiconductor film, characterized in that (100) oriented diamond is epitaxially grown on a substrate under such conditions that; the diamond substrate is (100) oriented diamond, a means for chemical vapor deposition provides hydrogen, hydrocarbon and a phosphorous compound in the plasma vapor phase, the ratio of phosphorous atoms to carbon atoms in the plasma vapor phase is no less than 0.1%, and the ratio of carbon atoms to hydrogen atoms is no less than 0.05%, and the method of producing the same.07-21-2011
20130168700POWER SEMICONDUCTOR DEVICE - In a high speed switching power semiconductor device having a sense pad, a high voltage is generated during switching operations in well regions under the sense pad due to a displacement current flowing through its flow path with a resistance, whereby the power semiconductor device sometimes breaks down by dielectric breakdown of a thin insulating film such as a gate insulating film. In a power semiconductor device according to the invention, sense-pad well contact holes are provided on well regions positioned under the sense pad and penetrate a field insulating film thicker than the gate insulating film to connect to the source pad, thereby improving reliability.07-04-2013
20110254020DEVICE FORMED HARD MASK AND ETCH STOP LAYER - A method of etching a device in one embodiment includes providing a silicon carbide substrate, forming a silicon nitride layer on a surface of the silicon carbide substrate, forming a silicon carbide layer on a surface of the silicon nitride layer, forming a silicon dioxide layer on a surface of the silicon carbide layer, forming a photoresist mask on a surface of the silicon dioxide layer, and etching the silicon dioxide layer through the photoresist mask.10-20-2011
20110254018Semiconductor Switching Arrangement Having a Normally on and a Normally off Transistor - A semiconductor switching arrangement includes a normally on semiconductor component of a first conduction type and a normally off semiconductor component of a second conduction type which is the complement of the first conduction type. A load path of the normally off semiconductor component is connected in series with the load path of the normally on semiconductor component. A first actuation circuit connected between the control connection of the normally on semiconductor component and a load path connection of the normally on semiconductor component. The load path connection of the normally on semiconductor component is arranged between the normally on and normally off semiconductor components. A second actuation circuit is connected between the control connection of the normally off semiconductor component and a load path connection of the normally off semiconductor component. The load path connection of the normally off semiconductor component is arranged between the normally on and normally off semiconductor components.10-20-2011
20110254015METHOD FOR IMPROVING DEVICE PERFORMANCE USING EPITAXIALLY GROWN SILICON CARBON (SiC) OR SILICON-GERMANIUM (SiGe) - A semiconductor substrate including a field effect transistor (FET) and a method of producing the same wherein a stressor is provided in a recess before the source/drain region is formed. The device has an increased carrier mobility in the channel region adjacent to the gate electrode.10-20-2011
20120032191METHOD FOR MANUFACTURING SILICON CARBIDE SUBSTRATE AND SILICON CARBIDE SUBSTRATE - A method for manufacturing a silicon carbide substrate (02-09-2012
20080203402SiC semiconductor device and method for manufacturing the same - A SiC semiconductor device includes: a SiC substrate having a main surface; a channel region on the substrate; first and second impurity regions on upstream and downstream sides of the channel region, respectively; a gate on the channel region through a gate insulating film. The channel region for flowing current between the first and second impurity regions is controlled by a voltage applied to the gate. An interface between the channel region and the gate insulating film has a hydrogen concentration equal to or greater than 2.6×1008-28-2008
20080203398Silicon carbide self-aligned epitaxial MOSFET and method of manufacturing thereof - A self-aligned, silicon carbide power metal oxide semiconductor field effect transistor includes a trench formed in a first layer, with a base region and then a source region epitaxially regrown within the trench. A window is formed through the source region and into the base region within a middle area of the trench. A source contact is formed within the window in contact with a base and source regions. The gate oxide layer is formed on the source and base regions at a peripheral area of the trench and on a surface of the first layer. A gate electrode is formed on the gate oxide layer above the base region at the peripheral area of the trench, and a drain electrode is formed over a second surface of the first layer.08-28-2008
20080203401METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURED THEREFROM - A method for producing a semiconductor device includes forming a first hetero-semiconductor layer as a hetero-junction to a surface of a silicon carbide epitaxial layer. This layer is composed of polycrystalline silicon having a band gap different from that of the silicon carbide epitaxial layer. An etching stopper layer composed of a material having a different etching rate from that of the polycrystalline silicon is formed on the surface of the first hetero-semiconductor layer. A second hetero-semiconductor layer composed of polycrystalline silicon is formed so that the second hetero-semiconductor layer contacts the surface of the first hetero-semiconductor layer and the etching stopper layer. The etching stopper layer is removed, the first hetero-semiconductor layer is thermally oxidized, and the thermally oxidized portion is then removed.08-28-2008
20080203400SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - A semiconductor device and a method of manufacturing the device using a (000-1)-faced silicon carbide substrate are provided. A SiC semiconductor device having a high blocking voltage and high channel mobility is manufactured by optimizing the heat-treatment method used following the gate oxidation. The method of manufacturing a semiconductor device includes the steps of forming a gate insulation layer on a semiconductor region formed of silicon carbide having a (000-1) face orientation, forming a gate electrode on the gate insulation layer, forming an electrode on the semiconductor region, cleaning the semiconductor region surface. The gate insulation layer is formed in an atmosphere containing 1% or more H08-28-2008
20120199847SEMICONDUCTOR DEVICE - A semiconductor device according to one embodiment includes: a unit FET cell(s) having multi-fingers composed of parallel connection of a unit finger; a designated gate bus line(s) configured to connect gate fingers of the unit FET cell having multi-fingers in parallel; and a gate extracting line(s) configured to be connected to the designated gate bus line, wherein a connecting point between the gate extracting line and the designated gate bus line is shifted from a center in the unit FET cell having multi-fingers, and thereby the numbers of the gate fingers connected to one side of the connecting point is more than the number of the gate fingers connected to another side of the connecting point.08-09-2012
20100320476VERTICAL JUNCTION FIELD EFFECT TRANSISTORS AND DIODES HAVING GRADED DOPED REGIONS AND METHODS OF MAKING - Semiconductor devices and methods of making the devices are described. The devices can be junction field-effect transistors (JFETs) or diodes such as junction barrier Schottky (JBS) diodes or PiN diodes. The devices have graded p-type semiconductor layers and/or regions formed by epitaxial growth. The methods do not require ion implantation. The devices can be made from a wide-bandgap semiconductor material such as silicon carbide (SiC) and can be used in high temperature and high power applications.12-23-2010
20100283061HIGH TEMPERATURE GATE DRIVERS FOR WIDE BANDGAP SEMICONDUCTOR POWER JFETS AND INTEGRATED CIRCUITS INCLUDING THE SAME - Gate drivers for wide bandgap (e.g., >2 eV) semiconductor junction field effect transistors (JFETs) capable of operating in high ambient temperature environments are described. The wide bandgap (WBG) semiconductor devices include silicon carbide (SiC) and gallium nitride (GaN) devices. The driver can be a non-inverting gate driver which has an input, an output, a first reference line for receiving a first supply voltage, a second reference line for receiving a second supply voltage, a ground terminal, and six Junction Field-Effect Transistors (JFETs) wherein the first JFET and the second JFET form a first inverting buffer, the third JFET and the fourth JFET form a second inverting buffer, and the fifth JFET and the sixth JFET form a totem pole which can be used to drive a high temperature power SiC JFET. An inverting gate driver is also described.11-11-2010
20130168698POWER DEVICES AND METHOD FOR MANUFACTURING THE SAME - A power device includes a substrate, a silicon carbide (Si07-04-2013
20120199850SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF - A silicon carbide semiconductor device is provided that includes a semiconductor layer made of silicon carbide and having a surface tilted at an angle in a range of not less than 50° and not more than 65° relative to the {0001} plane, and an insulating film formed to contact the surface of the semiconductor layer. A maximum value of the nitrogen concentration in a region within 10 nm from the interface between the semiconductor layer and the insulating film is not less than 1×1008-09-2012
20120199849METHOD OF FABRICATION OF METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR - A method of fabrication of a metal oxide semiconductor field effect transistor includes first providing a substrate on which a gate structure is formed. Afterwards, a portion of the substrate is removed to form a first recess in the substrate at both ends of the gate structure. Additionally, a source/drain extension layer is deposited in the first recess and a number of spacers are formed at both ends of the gate structure. Subsequently, a portion of the source/drain extension and the substrate are removed to form a second recess in the source/drain extension and a portion of the substrate outside of the spacer. In addition, a source/drain layer is deposited in the second recess. Because the source/drain extension and the source/drain layer have specific materials and structures, short channel effect is improved and the efficiency of the metal oxide semiconductor field effect transistor is improved.08-09-2012
20110133212METHODS OF MAKING SEMICONDUCTOR DEVICES HAVING IMPLANTED SIDEWALLS AND DEVICES MADE THEREBY - Semiconductor devices and methods of making the devices are described. The devices can be junction field-effect transistors (JFETs) or diodes such as junction barrier Schottky (JBS) diodes or PiN diodes. The devices are made using selective ion implantation using an implantation mask. The devices have implanted sidewalls formed by scattering of normal or near normal incident ions from the implantation mask. Vertical junction field-effect transistors with long channel length are also described. The devices can be made from a wide-bandgap semiconductor material such as silicon carbide (SiC) and can be used in high temperature and high power applications.06-09-2011
20110133211SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A wide band gap semiconductor device having a JFET, a MESFET, or a MOSFET mainly includes a semiconductor substrate, a first conductivity type semiconductor layer, and a first conductivity type channel layer. The semiconductor layer is formed on a main surface of the substrate. A recess is formed in the semiconductor layer in such a manner that the semiconductor layer is divided into a source region and a drain region. The recess has a bottom defined by the main surface of the substrate and a side wall defined by the semiconductor layer. The channel layer has an impurity concentration lower than an impurity concentration of the semiconductor layer. The channel layer is formed on the bottom and the side wall of the recess by epitaxial growth.06-09-2011
20110254016VERTICAL JFET LIMITED SILICON CARBIDE METAL-OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTORS - Silicon carbide metal-oxide semiconductor field effect transistors (MOSFETs) may include an n-type silicon carbide drift layer, a first p-type silicon carbide region adjacent the drift layer and having a first n-type silicon carbide region therein, an oxide layer on the drift layer, and an n-type silicon carbide limiting region disposed between the drift layer and a portion of the first p-type region. The limiting region may have a carrier concentration that is greater than the carrier concentration of the drift layer.10-20-2011
20110254017MANUFACTURING METHOD FOR CRYSTAL, CRYSTAL, AND SEMICONDUCTOR DEVICE - A manufacturing method for a crystal, a crystal, and a semiconductor device capable of growing a high-quality crystal are provided. The manufacturing method for a crystal of the present invention includes the steps of: preparing a seed crystal having a frontside surface and a backside surface opposite to the frontside surface; fixing the backside surface of the seed crystal to a pedestal; and growing the crystal on the frontside surface of the seed crystal. In the step of fixing, the seed crystal is fixed to the pedestal by coating the backside surface of the seed crystal with a Si layer or disposing a Si layer on the backside surface of the seed crystal, and carbonizing the Si layer.10-20-2011
20130168694SUPER INTEGRATED CIRCUIT CHIP SEMICONDUCTOR DEVICE - The CP555 Super Integrated Circuit Chip has a ceramic package casing made from (B4-C) Boron Carbide: a non-conducting ceramic material. The IC is connected to connector pins by microcircuits and a custom formulated bond wire. The CP555 Integrated Circuit's ceramic Boron Carbide (B4-C) outer package casing, Heterodiamond substrates and dielectric components allows these integrated circuits to reduce electro-migration to a minimum, produce superior radiation hardness, heat resistance, electromagnetic shielding, and resistance to damage from harsh elements and environments. The CP555 Integrated Circuit can be used as a CMOS, PIC or DIE microcontroller circuit or computer processor (CPU). 07-04-2013
20130168695CMOS HAVING A SIC/SIGE ALLOY STACK - A delta doping of silicon by carbon is provided on silicon surfaces by depositing a silicon carbon alloy layer on silicon surfaces, which can be horizontal surfaces of a bulk silicon substrate, horizontal surfaces of a top silicon layer of a semiconductor-on-insulator substrate, or vertical surfaces of silicon fins. A p-type field effect transistor (PFET) region and an n-type field effect transistor (NFET) region can be differentiated by selectively depositing a silicon germanium alloy layer in the PFET region, and not in the NFET region. The silicon germanium alloy layer in the PFET region can overlie or underlie a silicon carbon alloy layer. A common material stack can be employed for gate dielectrics and gate electrodes for a PFET and an NFET. Each channel of the PFET and the NFET includes a silicon carbon alloy layer, and is differentiated by the presence or absence of a silicon germanium layer.07-04-2013
20130168696Silicon Carbide Schottky Diode Device with Mesa Termination and Manufacturing Method Thereof - A silicon carbide Schottky diode device with mesa terminations and the manufacturing method thereof are provided. The silicon carbide Schottky diode device includes an n-type epitaxial silicon carbide layer with mesa terminations on an n-type silicon carbide substrate, two p-type regions in the n-type epitaxial silicon carbide layer and a Schottky metal contact on the n-type epitaxial silicon carbide layer and the p-type regions, a dielectric layer on sidewalls and planes of the mesa terminations.07-04-2013
20110079793SEMICONDUCTOR SUBSTRATE AND ITS MANUFACTURING METHOD - A semiconductor substrate includes: a substrate having a single crystal silicon on at least one surface thereof; a buffer layer that is provided on the single crystal silicon and has at least one cobalt silicide layer primarily containing cobalt silicide; and a silicon carbide single crystal film provided on the buffer layer.04-07-2011
20110084285BASE MATERIAL FOR GROWING SINGLE CRYSTAL DIAMOND AND METHOD FOR PRODUCING SINGLE CRYSTAL DIAMOND SUBSTRATE - The present invention is a base material for growing a single crystal diamond comprising: at least a single crystal SiC substrate; and an iridium film or a rhodium film heteroepitaxially grown on a side of the single crystal SiC substrate where the single crystal diamond is to be grown. As a result, there is provided a base material for growing a single crystal diamond and a method for producing a single crystal diamond substrate which can grow the single crystal diamond having a large area and good crystallinity and produce a high quality single crystal diamond substrate at low cost.04-14-2011
20120199845METALLIC CARRIER FOR LAYER TRANSFER AND METHODS FOR FORMING THE SAME - Embodiments relate to semiconductor structures and methods of forming them. In some embodiments, the methods may be used to fabricate a semiconductor substrate by forming a weakened zone in a donor structure at a predetermined depth to define a transfer layer between an attachment surface and the weakened zone and a residual donor structure between the weakened zone and a surface opposite the attachment surface. A metallic layer is formed on the attachment surface and provides an ohmic contact between the metallic layer and the transfer layer, a matched Coefficient of Thermal Expansion (CTE) for the metallic layer that closely matches a CTE of the transfer layer, and sufficient stiffness to provide structural support to the transfer layer. The transfer layer is separated from the donor structure at the weakened zone to form a composite substrate comprising the transfer layer the metallic layer.08-09-2012
20110186862SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - There is provided a silicon carbide semiconductor device having excellent electrical characteristics such as channel mobility, and a method for manufacturing the same. A semiconductor device includes a substrate made of silicon carbide and having an off-angle of greater than or equal to 50° and less than or equal to 65° with respect to a surface orientation of {0001}, a p-type layer serving as a semiconductor layer, and an oxide film serving as an insulating film. The p-type layer is formed on the substrate and is made of silicon carbide. The oxide film is formed to contact with a surface of the p-type layer. A maximum value of the concentration of nitrogen atoms in a region within 10 nm of an interface between the semiconductor layer and the insulating film (interface between a channel region and the oxide film) is greater than or equal to 1×1008-04-2011
20110186861SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device having a JFET or a MESFET mainly includes a semiconductor substrate, a first conductivity type semiconductor channel layer on the substrate, a first conductivity type semiconductor layer on the channel layer, and an i-type sidewall layer on a sidewall of a recess that penetrates the semiconductor layer to divide the semiconductor layer into a source region and a drain region. The semiconductor layer has an impurity concentration greater than an impurity concentration of the channel layer. The semiconductor device further includes a second conductivity type gate region that is located on the channel layer in the recess and on the i-type sidewall layer. The gate region is spaced from the source region and the drain region by the i-type sidewall layer.08-04-2011
20120146057METHOD OF FABRICATING SPACERS IN A STRAINED SEMICONDUCTOR DEVICE - The present disclosure provides a method for fabricating a semiconductor device that includes forming a gate stack over a silicon substrate, forming dummy spacers on sidewalls of the gate stack, isotropically etching the silicon substrate to form recess regions on either side of the gate stack, forming a semiconductor material in the recess regions, the semiconductor material being different from the silicon substrate, removing the dummy spacers, forming spacer layers having an oxide-nitride-oxide configuration over the gate stack and the semiconductor material, and etching the spacer layers to form gate spacers on the sidewalls of the gate stack.06-14-2012
20120146052NITRIDE BASED SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - Disclosed herein is a nitride based semiconductor device. There is provided a nitride based semiconductor device including: a base substrate; an epitaxial growth layer disposed on the base substrate and generating 2-dimensional electron gas (2DEG) therein; and an electrode structure disposed on the epitaxial growth layer and having an extension extending into the epitaxial growth layer, wherein the epitaxial growth layer includes a depressing part depressed thereinto from the surface of the epitaxial growth layer, and the depressing part includes: a first area in which the extension is disposed; and a second area that is an area other than the first area.06-14-2012
20120146050MEASUREMENT OF CMOS DEVICE CHANNEL STRAIN BY X-RAY DIFFRACTION - A direct measurement of lattice spacing by X-ray diffraction is performed on a periodic array of unit structures provided on a substrate including semiconductor devices. Each unit structure includes a single crystalline strained material region and at least one stress-generating material region. For example, the single crystalline strained material region may be a structure simulating a channel of a field effect transistor, and the at least one stress-generating material region may be a single crystalline semiconductor region in epitaxial alignment with the single crystalline strained material region. The direct measurement can be performed in-situ at various processing states to provide in-line monitoring of the strain in field effect transistors in actual semiconductor devices.06-14-2012
20110095301SILICON CARBIDE SEMICONDUCTOR DEVICE - There was a problem that it was difficult to manufacture silicon carbide semiconductor devices with suppressed variations in characteristics without increasing the number of process steps. A silicon carbide semiconductor device according to the present invention includes an N type SiC substrate and an N type SiC epitaxial layer as a silicon carbide semiconductor substrate of a first conductivity type, a plurality of recesses intermittently formed in a surface of the N type SiC epitaxial layer, P type regions as second-conductivity-type semiconductor layers formed in the N type SiC epitaxial layer in the bottoms of the plurality of recesses, and a Schottky electrode selectively formed over the surface of the N type SiC epitaxial layer, wherein the plurality of recesses all have an equal depth.04-28-2011
20110095305SEMICONDUCTOR DEVICE - The semiconductor device includes: a substrate 04-28-2011
20110095304PROCESS FOR FORMING AN INTERFACE BETWEEN SILICON CARBIDE AND SILICON OXIDE WITH LOW DENSITY OF STATES - An embodiment of a process for forming an interface between a silicon carbide (SiC) layer and a silicon oxide (SiO04-28-2011
20110095303SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate, a cell region, an outer peripheral region, a field plate, an outermost peripheral ring, outer peripheral region layer, an insulator film, and a Zener diode. The semiconductor substrate has a superjunction structure. The outer peripheral region is disposed at an outer periphery of the cell region. The Zener diode is disposed on the insulator film for electrically connecting the field plate with the outermost peripheral ring. The Zener diode has a first conductivity type region and a second conductivity type region that are alternately arranged in a direction from the cell region to the outer peripheral region.04-28-2011
20110095302SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - An object is to provide a semiconductor device and its manufacturing method in which delay in switching and non-uniform operations are prevented and in which stresses occurring in trench regions are alleviated as much as possible. A gate electrode in a gate trench is formed of a polysilicon layer and a gate tungsten layer that is lower resistant than the polysilicon layer. Also, a source electrode is formed of source tungsten layers buried in source trenches and an AlSi layer in contact with the source tungsten layers and covering source layers and the gate electrodes with a thick insulating film interposed therebetween.04-28-2011
20100258815SILICON CARBIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - An objective is to provide a manufacturing method of a silicon carbide semiconductor device in which an electric field applied to a gate oxide film can be relaxed and thereby reliability can be ensured, and by the manufacturing method increase of the manufacturing cost can also be prevented as much as possible. Well regions, channel regions, and gate electrodes are formed so that, given that extending lengths, with respect to the inner sides of source regions, of each of the well regions, the channel regions, and the gate electrodes are Lwell, Lch, and Lg, respectively, a relationship of Lch10-14-2010
20110260175SEMICONDUCTOR DEVICE - A silicon carbide layer is provided on a substrate, has a hexagonal single-crystal structure, and has a surface at which a depletion layer is formed. A protective film is insulative and provided on the silicon carbide layer to directly cover the surface. The surface thus directly covered with the protective film includes a portion having an off angle of not more than 10° relative to the {0-33-8} plane of the silicon carbide layer. This results in reduced leakage current flowing in an interface between the protective film and the semiconductor layer.10-27-2011
20100059762HEAT REMOVAL FACILITATED WITH DIAMOND-LIKE CARBON LAYER IN SOI STRUCTURES - Described are Silicon-on-Insulator devices containing a diamond-like carbon layer, methods of making the Silicon-on-Insulator devices, and methods of using the Silicon-on-Insulator devices.03-11-2010
20110147766METHOD OF MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - A method of manufacturing a silicon carbide semiconductor device is provided that includes a step of forming in a surface of a silicon carbide wafer of first conductivity type a first region of second conductivity type having a predetermined space thereinside by ion-implanting aluminum as a first impurity and boron as a second impurity; a step of forming a JTE region in the surface of the silicon carbide wafer from the first region by diffusing the boron ion-implanted in the first region toward its neighboring zones by an activation annealing treatment; a step of forming a first electrode on the surface of the silicon carbide wafer at the space inside the first region and at an inner part of the first region; and a step of forming a second electrode on the opposite surface of the silicon carbide wafer. Thereby, a JTE region can be formed that has a wide range of impurity concentration and a desired breakdown voltage without increasing the number of steps of the manufacturing process.06-23-2011
20110147764TRANSISTORS WITH A DIELECTRIC CHANNEL DEPLETION LAYER AND RELATED FABRICATION METHODS - A metal-insulator-semiconductor field-effect transistor (MISFET) includes a semiconductor layer with source and drain regions of a first conductivity type spaced apart therein. A channel region of a first conductivity type extends between the source and drain regions. A gate contact is on the channel region. A dielectric channel depletion layer is between the gate contact and the channel region. The dielectric channel depletion layer provides a net charge having the same polarity as the first conductivity type charge carriers, and which may deplete the first conductivity type charge carriers from an adjacent portion of the channel region when no voltage is applied to the gate contact.06-23-2011
20110147765DUMMY STRUCTURE FOR ISOLATING DEVICES IN INTEGRATED CIRCUITS - The present disclosure provides an integrated circuit. The integrated circuit includes a first operational device having a first transistor of a first composition; a second operational device having a second transistor of the first composition; and an isolation transistor disposed between the first and second transistors, the isolation transistor having a second composition different from the first composition.06-23-2011
20100025695ANNEALING METHOD FOR SEMICONDUCTOR DEVICE WITH SILICON CARBIDE SUBSTRATE AND SEMICONDUCTOR DEVICE - In an atmosphere in which a silicon carbide (SiC) substrate implanted with impurities is annealed to activate the impurities, by setting a partial pressure of H02-04-2010
20100025696Process for Producing a Silicon Carbide Substrate for Microelectric Applications - The process according to the present invention is adapted to produce a silicon carbide substrate for microelectronic applications; it comprises the following steps: 02-04-2010
20110215340SEMICONDUCTOR LIGHT EMITTING ELEMENT AND METHOD FOR MANUFACTURING SAME - A semiconductor light-emitting device according to the present invention includes: a GaN substrate 09-08-2011
20100019250SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device and a method of forming thereof has a base body has a field stopping layer, a drift layer, a current spreading layer, a body region, and a source contact region layered in the order on a substrate. A trench that reaches the field stopping layer or the substrate is provided. A gate electrode is provided in the upper half section in the trench. In a section deeper than the position of the gate electrode in the trench, an insulator is buried that has a normal value of insulation breakdown electric field strength equal to or greater than the value of the insulation breakdown electric field strength of the semiconductor material of the base body. This inhibits short circuit between a gate and a drain due to insulation breakdown of an insulator film at the bottom of the trench to realize a high breakdown voltage in a semiconductor device using a semiconductor material such as SiC. The sidewall surfaces of the trench located below the gate electrode is inclined to form a trapezoidal profile.01-28-2010
20100019249JFET Devices with Increased Barrier Height and Methods of Making Same - Devices and methods for providing JFET transistors with improved operating characteristics are provided. Specifically, one or more embodiments of the present invention relate to JFET transistors with a higher diode turn-on voltage. For example, one or more embodiments include a JFET with a doped silicon-carbide gate, while other embodiments include a JFET with a metal gate. One or more embodiments also relate to systems and devices in which the improved JFET may be employed, as well as methods of manufacturing the improved JFET.01-28-2010
20090173950CONTROLLING DIAMOND FILM SURFACES AND LAYERING - A method comprising: providing at least one first diamond film comprising polycrystalline diamond, e.g., nanocrystalline or ultrananocrystalline diamond, disposed on a substrate, wherein the first diamond film comprises a surface comprising diamond asperities and having a first diamond film thickness, removing asperities from the first diamond film to form a second diamond film having a second diamond film thickness, wherein the second thickness is either substantially the same as the first thickness, or the second thickness is about 100 nm or less thinner than the first diamond film thickness, optionally patterning the second diamond film to expose substrate regions and, optionally, depositing semiconductor material on the exposed substrate regions, and depositing a solid layer on the second diamond film to form a first layered structure. Applications include for example dielectric isolation in the semiconductor industry, as well as surface acoustic wave devices, scanning probe microscope, and atomic force microscope devices.07-09-2009
20090173951COMPOUND SEMICONDUCTOR DEVICE USING SiC SUBSTRATE AND ITS MANUFACTURE - A compound semiconductor device includes: a conductive SiC substrate; an AlN buffer layer formed on said conductive SiC substrate and containing Cl; a compound semiconductor buffer layer formed on said AlN layer which contains Cl, said compound semiconductor buffer layer not containing Cl; and a device constituent layer or layers formed above said compound semiconductor buffer layer not containing Cl.07-09-2009
20080237608Molybdenum barrier metal for SiC Schottky diode and process of manufacture - A method for fabricating a diode is disclosed. In one embodiment, the method includes forming a Schottky contact on an epitaxial layer of silicon carbide (SiC) and annealing the Schottky contact at a temperature in the range of 300° C. to 700° C. The Schottky contact is formed of a layer of molybdenum.10-02-2008
20090242901SiC MOSFETS AND SELF-ALIGNED FABRICATION METHODS THEREOF - The present invention provides a method of fabricating a metal oxide semiconductor field effect transistor. The method includes the steps of forming a source region on a silicon carbide layer and annealing the source region. A gate oxide layer is formed on the source region and the silicon carbide layer. The method further includes providing a gate electrode on the gate oxide layer and disposing a dielectric layer on the gate electrode and the gate oxide layer. The method further includes etching a portion of the dielectric layer and a portion of the gate oxide layer to form sidewalls on the gate electrode. A metal layer is disposed on the gate electrode, the sidewalls and the source region. The method further includes forming a gate contact and a source contact by subjecting the metal layer to a temperature of at least about 800° C. The gate contact and the source contact comprise a metal silicide. The distance between the gate contact and the source contact is less than about 0.6 μm. A vertical SiC MOSFET is also provided.10-01-2009
20110073874METHOD OF REDUCING MEMORY EFFECTS IN SEMICONDUCTOR EPITAXY - A method of reducing memory effects during an epitaxial growth process is provided in which a gas mixture comprising hydrogen gas and a halogen-containing gas is used to flush the CVD reaction chamber between growth steps.03-31-2011
20110073873COMPOUND SEMICONDUCTOR DEVICE USING SIC SUBSTRATE AND ITS MANUFACTURE - A compound semiconductor device includes: a conductive SiC substrate; an AlN buffer layer formed on said conductive SiC substrate and containing Cl; a compound semiconductor buffer layer formed on said AlN layer which contains Cl, said compound semiconductor buffer layer not containing Cl; and a device constituent layer or layers formed above said compound semiconductor buffer layer not containing Cl.03-31-2011
20110073872HIGH BRIGHTNESS LIGHT EMITTING DIODE AND MANUFACTURING METHOD THEREOF - A high brightness light emitting diode includes a carrier substrate and an epitaxial multi-layer formed thereon. The carrier substrate includes a metal material and a medium, and a coefficient of thermal expansion (CTE) of the medium is less than a CTE of the metal material.03-31-2011
20120146054MOSFET WITH SOURCE SIDE ONLY STRESS - An integrated circuit contains a transistor with a stress enhancement region on the source side only. In a DeMOS transistor, forming the stress enhancement region on the source side only and not forming a stress enhancement region in the drain extension increases the resistance of the drain extension region enabling formation of a DeMOS transistor with reduced area. In a MOS transistor, by forming the stress enhancement region on the source side only and eliminating the stress enhancement region from the drain side, transistor leakage is reduced and CHC reliability improved.06-14-2012
20120146055SiC SEMICONDUCTOR DEVICE - A SiC semiconductor device includes a SiC semiconductor layer having a first-conductivity-type impurity, a field insulation film formed on a front surface of the SiC semiconductor layer and provided with an opening for exposing therethrough the front surface of the SiC semiconductor layer, an electrode connected to the SiC semiconductor layer through the opening of the field insulation film, and a guard ring having a second-conductivity-type impurity and being formed in a surface layer portion of the SiC semiconductor layer to make contact with a terminal end portion of the electrode connected to the SiC semiconductor layer. A second-conductivity-type impurity concentration in a surface layer portion of the guard ring making contact with the electrode is smaller than a first-conductivity-type impurity concentration in the SiC semiconductor layer.06-14-2012
20120146053SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device according to an embodiment includes a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, first gate sidewalls formed on both sides of the gate electrode, and a source/drain semiconductor layer formed on the semiconductor substrate to sandwich the first gate sidewalls with the gate electrode. Further, second gate sidewalls are provided on the first gate sidewalls and the source/drain semiconductor layer at both sides of the gate electrode, wherein the boundary of each of the second gate sidewalls with each of the first gate sidewalls is terminated at the side surface of the gate electrode, and each of the second gate sidewalls has a smaller Young's modulus and a lower dielectric constant than each of the first gate sidewalls.06-14-2012
20110024768SiC AVALANCHE PHOTODIODE WITH IMPROVED EDGE TERMINATION - An avalanche photodiode semiconductor device (02-03-2011
20120305945POWER SEMICONDUCTOR DEVICE - Provided is a power semiconductor device comprising a bonding joint that, even under a temperature environment of 150° C. or greater enabling operation of a wide bandgap semiconductor, reduces cracking-destruction occurring owing to thermal cycle while conductively connecting an electrode, connection terminal, and semiconductor device substrate.12-06-2012
20120305943SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A drift layer has a thickness direction throughout which a current flows and has an impurity concentration N12-06-2012
20120305942EPITAXIAL SUBSTRATE, LIGHT-EMITTING DIODE, AND METHODS FOR MAKING THE EPITAXIAL SUBSTRATE AND THE LIGHT-EMITTING DIODE - An epitaxial substrate includes: a base member; and a plurality of spaced apart light-transmissive members, each of which is formed on and tapers from an upper surface of the base member, and each of which is made of a light-transmissive material having a refractive index lower than that of the base member. A light-emitting diode having the epitaxial substrate, and methods for making the epitaxial substrate and the light-emitting diode are also disclosed.12-06-2012
20120305941WELL REGION FORMATION METHOD AND SEMICONDUCTOR BASE - A well region formation method and a semiconductor base in the field of semiconductor technology are provided. A method comprises: forming isolation regions in a semiconductor substrate to isolate active regions; selecting at least one of the active regions, and forming a first well region in the selected active region; forming a mask to cover the selected active region, and etching the rest of the active regions, so as to form grooves; and growing a semiconductor material by epitaxy to till the grooves. Another method comprises: forming isolation regions in a semiconductor substrate for isolating active regions; forming well regions in the active regions; etching the active regions to form grooves, such that the grooves have a depth less than or equal to a depth of the well regions; and growing a semiconductor material by epitaxy to till the grooves.12-06-2012
20120146056SILICON CARBIDE EPITAXIAL WAFER AND MANUFACTURING METHOD THEREFOR - Provided is a silicon carbide epitaxial wafer, the entire surface of which is free of step bunching. Also provided is a method for manufacturing said silicon carbide epitaxial wafer. The provided method for manufacturing a silicon carbide semiconductor device includes: a step wherein a 4H—SiC single-crystal substrate having an off-axis angle of 5° or less is polished until the lattice disorder layer on the surface of the substrate is 3 nm or less; a step wherein, in a hydrogen atmosphere, the polished substrate is brought to a temperature between 1400° C. and 1600° C. and the surface of the substrate is cleaned; a step wherein silicon carbide is epitaxially grown on the surface of the cleaned substrate as the amounts of SiH06-14-2012
20120037923LIGHT EMITTING DIODE ELEMENT AND METHOD FOR PRODUCING THE SAME - [PROBLEM] To provide a light emitting diode which can obtain emission at shorter wavelength side of emission range of normal 6H-type SiC doped with B and N, and a method for manufacturing the same.02-16-2012
20120037922SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - The invention provides an ultra-low-on-resistance, excellent-reliability semiconductor device that can finely be processed using SiC and a semiconductor device producing method. A semiconductor device includes: a silicon carbide substrate; a first-conductive-type first silicon carbide layer provided on a first principal surface of the silicon carbide substrate; a second-conductive-type first silicon carbide region formed at a surface of the first silicon carbide layer; a first-conductive-type second silicon carbide region formed at a surface of the first silicon carbide region; a second-conductive-type third silicon carbide region formed below the second silicon carbide region; a trench piercing through the second silicon carbide region to reach the third silicon carbide region; a gate insulating film; a gate electrode; an interlayer insulating film with which the gate electrode is covered; a first electrode that is formed on the second silicon carbide region and the interlayer insulating film in a side surface of the trench while containing a metallic element selected from a group consisting of Ni, Ti, Ta, Mo, and W; a second electrode that is formed on the third silicon carbide region in a bottom portion of the trench and the first electrode while containing Al; a first main electrode formed on the second electrode; and a second main electrode formed on a second principal surface of the silicon carbide substrate.02-16-2012
20120037921Electrical Devices With Enhanced Electrochemical Activity and Manufacturing Methods Thereof - In some aspects, a device is provided having a member with a region of enhanced electrochemical activity. In one aspect, a sensor of enhanced electrochemical activity is provided for detecting an analyte concentration level in a bio-fluid sample. The sensor may include a sensor member of a semiconductor material wherein the sensor member has a surface region of enhanced electrochemical activity. In other aspects, the member may be made of semiconducting foam having a surface region of enhanced electrochemical activity. In some embodiments, the region may be thermally-induced. Manufacturing methods and apparatus are also provided, as are numerous other aspects.02-16-2012
20120037920Silicone Carbide Trench Semiconductor Device - A semiconductor device as described herein includes a silicon carbide semiconductor body. A trench extends into the silicon carbide semiconductor body at a first surface. A gate dielectric and a gate electrode are formed within the trench. A body zone of a first conductivity type adjoins to a sidewall of the trench, the body zone being electrically coupled to a contact via a body contact zone including a higher maximum concentration of dopants than the body zone. An extension zone of the first conductivity type is electrically coupled to the contact via the body zone, wherein a maximum concentration of dopants of the extension zone along a vertical direction perpendicular to the first surface is higher than the maximum concentration of dopants of the body zone along the vertical direction. A distance between the first surface and a bottom side of the extension zone is larger than the distance between the first surface and the bottom side of the trench.02-16-2012
20120037924Junction Field-Effect Transistor - A junction field-effect transistor (02-16-2012
20120097980SILICON CARBIDE INSULATING GATE TYPE SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A termination configuration of a silicon carbide insulating gate type semiconductor device includes a semiconductor layer of a first conductivity type having a first main face, a gate electrode, and a source interconnection, as well as a circumferential resurf region. The semiconductor layer includes a body region of a second conductivity type, a source region of the first conductivity type, a contact region of the second conductivity type, and a circumferential resurf region of the second conductivity type. A width of a portion of the circumferential resurf region excluding the body region is greater than or equal to ½ the thickness of at least the semiconductor layer. A silicon carbide insulating gate type semiconductor device of high breakdown voltage and high performance can be provided.04-26-2012
20110316002CMOS IMAGE SENSOR - A complementary metal-oxide-semiconductor (CMOS) image sensor, including a wiring layer, a photodiode stacked with the wiring layer, a micro-lens stacked on the photodiode, an anti-reflection layer stacked on the photodiode. An anti-absorption layer may be provided between the photodiode and the anti-reflection layer. The photodiode may include a first portion and a second portion. Light may be focused on the first portion by the micro-lens and the second portion may at least partially surround the first portion. A material of the first portion may have a refractive index higher than a refractive index of a material of the second portion. The anti-absorption layer may include a compound semiconductor having an energy band gap greater than an energy band gap of a semiconductor included in the photodiode.12-29-2011
20110316003Multilayered Semiconductor Wafer and Process For Manufacturing The Same - Silicon carbide substrate wafers are prepared by transferring a monocrystalline silicon layer from a donor wafer onto a handle wafer, the silicon layer being implanted with carbon and annealed to form a monocrystalline SiC layer prior to or after transfer of the silicon layer.12-29-2011
20110101374MONOLITHIC HIGH VOLTAGE SWITCHING DEVICES AND RELATED METHODS OF FABRICATING THE SAME - Metal oxide semiconductor (MOS) power devices are provided including a MOS channel including a semiconductor material having high electron mobility on a silicon carbide (SiC) layer. Related methods are also provided herein.05-05-2011
20120043557SEMICONDUCTOR LIGHT-EMITTING DEVICE WITH IMPROVED LIGHT EXTRACTION EFFICIENCY - The present invention provides a semiconductor light-emitting device. The light-emitting device comprises a first conductive clad layer, an active layer, and a second conductive clad layer sequentially formed on a substrate. In the light-emitting device, the substrate has one or more side patterns formed on an upper surface thereof while being joined to one or more edges of the upper surface. The side patterns consist of protrusions or depressions so as to scatter or diffract light to an upper portion or a lower portion of the light-emitting device.02-23-2012
20120043556EPITAXIAL GROWTH OF SILICON DOPED WITH CARBON AND PHOSPHORUS USING HYDROGEN CARRIER GAS - A method for depositing epitaxial films of silicon carbon (Si:C). In one embodiment, the method includes depositing an n-type doped silicon carbon (Si:C) semiconductor material on a semiconductor deposition surface using a deposition gas precursor composed of a silane containing gas precursor, a carbon containing gas precursor, and an n-type gas dopant source. The deposition gas precursor is introduced to the semiconductor deposition surface with a hydrogen (H02-23-2012
20120061685Memory Devices And Memory Cells - A memory device includes an array of memory cells and peripheral devices. At least some of the individual memory cells include carbonated portions that contain SiC. At least some of the peripheral devices do not include any carbonated portions. A transistor includes a first source/drain, a second source/drain, a channel including a carbonated portion of a semiconductive substrate that contains SiC between the first and second sources/drains and a gate operationally associated with opposing sides of the channel.03-15-2012
20120001197LAYOUT FOR MULTIPLE-FIN SRAM CELL - The present disclosure provides a static random access memory (SRAM) cell. The SRAM cell includes a plurality of fin active regions formed on a semiconductor substrate, wherein the plurality of fin active regions include a pair adjacent fin active regions having a first spacing and a fin active region having a second spacing from adjacent fin active regions, the second spacing being greater than the first spacing; a plurality of fin field-effect transistors (FinFETs) formed on the plurality of fin active regions, wherein the plurality of FinFETs are configured to a first and second inverters cross-coupled for data storage and at least one port for data access; a first contact disposed between the first and second the fin active regions, electrically contacting both of the first and second the fin active regions; and a second contact disposed on and electrically contacting the third fin active region.01-05-2012
20120001198ISOLATION REGION, SEMICONDUCTOR DEVICE AND METHODS FOR FORMING THE SAME - An isolation region is provided. The isolation region includes a first groove and an insulation layer filling the first groove. The first groove is embedded into a semiconductor substrate and includes a first sidewall, a bottom surface and a second sidewall that extends from the bottom surface and joins to the first sidewall. An angle between the first sidewall and a normal line of the semiconductor substrate is larger than a standard value. A method for forming an isolation region is further provided. The method includes: forming a first trench on a semiconductor substrate, wherein an angle between a sidewall of the first trench and a normal line of the semiconductor substrate is larger than a standard value; forming a mask on the sidewall to form a second trench on the semiconductor substrate by using the mask; and forming an insulation layer to fill the first and second trenches. A semiconductor device and a method for forming the same are still further provided. In the semiconductor device, a material of the semiconductor substrate is interposed between a second groove bearing a semiconductor layer for forming an S/D region and the first and second sidewalls. The present invention is beneficial to reduce leakage current.01-05-2012
20120001200SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes: a semiconductor chip; a protective film and an insulating film sequentially stacked over the semiconductor chip, and each having openings that expose source, drain, and gate pads; a heat dissipation terminal made of a material having a higher thermal conductivity than the insulating film; connection terminals formed on the source, drain, and gate pads and surrounded by the insulating film; and a mount substrate having connection pads. The semiconductor chip has a source electrode having a plurality of source fingers, a drain electrode having a plurality of drain fingers, and a gate electrode having a plurality of gate fingers. The source, drain, and gate pads are connected to the source electrode, the drain electrode, and the gate electrode, respectively. The connection terminals are respectively connected to the connection pads. The heat dissipation terminal is in close contact with the mount substrate.01-05-2012
20120001199POWER SEMICONDUCTOR DEVICE - A bipolar power semiconductor device is provided with an emitter electrode on an emitter side and a collector electrode on a collector side. The device has a trench gate electrode and a structure with a plurality of layers of different conductivity types in the following order: at least one n doped source region, a p doped base layer, which surrounds the at least one source region, an n doped enhancement layer, a p doped additional well layer, an additional n doped enhancement layer, an additional p doped well layer, an n doped drift layer and a p doped collector layer. The trench gate electrode has a gate bottom, which is located closer to the collector side than the additional enhancement layer bottom.01-05-2012
20110156058SILICON CARBIDE MONOCRYSTAL SUBSTRATE AND MANUFACTURING METHOD THEREFOR - A method for producing a silicon carbide single crystal substrate according to the present invention includes steps of: (A) preparing a silicon carbide single crystal substrate having a mechanically polished main face; (B) performing chemical mechanical polishing on the main face of the silicon carbide single crystal substrate using a polishing slurry containing abrasive grains dispersed therein to finish the main face as a mirror surface; (C′1) oxidizing at least a part of the main face finished as a mirror surface by a gas phase to form an oxide; and (C′2) removing the oxide.06-30-2011
20110156057SUBSTRATE OF THE SEMICONDUCTOR ON INSULATOR TYPE WITH INTRINSIC AND DOPED DIAMOND LAYERS - A semiconductor substrate including at least a layer based on doped diamond with a thickness greater than or equal to approximately 10 μm, a layer based on at least one semiconductor or a stack of layers including the semiconductor-based layer, and a layer based on intrinsic diamond disposed against the layer based on doped diamond, between the layer based on doped diamond and the semiconductor-based layer.06-30-2011
20110156056WAVELENGTH-CONVERTED SEMICONDUCTOR LIGHT EMITTING DEVICE - A material such as a phosphor is optically coupled to a semiconductor structure including a light emitting region disposed between an n-type region and a p-type region, in order to efficiently extract light from the light emitting region into the phosphor. The phosphor may be phosphor grains in direct contact with a surface of the semiconductor structure, or a ceramic phosphor bonded to the semiconductor structure, or to a thin nucleation structure on which the semiconductor structure may be grown. The phosphor is preferably highly absorbent and highly efficient. When the semiconductor structure emits light into such a highly efficient, highly absorbent phosphor, the phosphor may efficiently extract light from the structure, reducing the optical losses present in prior art devices.06-30-2011
20110156055INTEGRATED DIAMOND TRANSDUCTION PIXELIZED IMAGER DEVICE AND MANUFACTURING PROCESS - Imaging device including several pixels, each pixel including at least:06-30-2011
20110156054SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A silicon carbide semiconductor device having a JFET or a MOSFET includes a semiconductor substrate and a trench. The semiconductor substrate has a silicon carbide substrate, a drift layer on the silicon carbide substrate, a first gate region on the drift layer, and a source region on the first gate region. The trench has a strip shape with a longitudinal direction and reaches the drift layer by penetrating the source region and the first gate region. The trench is filled with a channel layer and a second gate region on the channel layer. The source region is not located at an end portion of the trench in the longitudinal direction.06-30-2011
20110156053SEMICONDUCTOR DEVICE HAVING D MODE JFET AND E MODE JFET AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes: a substrate; and depletion and enhancement mode JFETs. The depletion mode JFET includes: a concavity on the substrate; a channel layer in the concavity; a first gate region on the channel layer; first source and drain regions on respective sides of the first gate region in the channel layer; first gate, source and drain electrodes. The enhancement mode JFET includes: a convexity on the substrate; the channel layer on the convexity; a second gate region on the channel layer; second source and drain regions on respective sides of the second gate region in the channel layer; second gate, source and drain electrodes. A thickness of the channel layer in the concavity is larger than a thickness of the channel layer on the convexity.06-30-2011
20110156052Semiconductor device having JFET and method for manufacturing the same - A semiconductor device having a JFET includes: a substrate made of semi-insulating semiconductor material; a gate region in a surface portion of the substrate; a channel region disposed on and contacting the gate region; a source region and a drain region disposed on both sides of the gate region so as to sandwich the channel region, respectively; a source electrode electrically coupled with the source region; a drain electrode electrically coupled with the drain region; and a gate electrode electrically coupled with the gate region. An impurity concentration of each of the source region and the drain region is higher than an impurity concentration of the channel region.06-30-2011
20120056202SEMICONDUCTOR DEVICE - A MOSFET, which is a semiconductor device allowing for reduced on-resistance while restraining stacking faults from being produced due to heat treatment in a device manufacturing process, includes: a silicon carbide substrate; an active layer made of single-crystal silicon carbide and disposed on one main surface of the silicon carbide substrate; a source contact electrode disposed on the active layer; and a drain electrode formed on the other main surface of the silicon carbide substrate. The silicon carbide substrate includes: a base layer made of silicon carbide; and a SiC layer made of single-crystal silicon carbide and disposed on the base layer. Further, the base layer has an impurity concentration greater than 2×1003-08-2012
20120056203SEMICONDUCTOR DEVICE - A JFET, which is a semiconductor device allowing for reduced manufacturing cost, includes: a silicon carbide substrate; an active layer made of single-crystal silicon carbide and disposed on one main surface of the silicon carbide substrate; a source electrode disposed on the active layer; and a drain electrode formed on the active layer and separated from the source electrode. The silicon carbide substrate includes: a base layer made of single-crystal silicon carbide, and a SiC layer made of single-crystal silicon carbide and disposed on the base layer. The SiC layer has a defect density smaller than that of the base layer.03-08-2012
20120056199Self-supporting CVD diamond film and method for producing a self-supporting CVD diamond film - The invention relates to a self-supporting CVD diamond film comprising a plurality of diamond layers (03-08-2012
20120056196SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device according to an embodiment includes a first-conductive-type semiconductor substrate; a first-conductive-type first semiconductor layer formed on the semiconductor substrate, and having an impurity concentration lower than that of the semiconductor substrate; a second-conductive-type second semiconductor layer epitaxially formed on the first semiconductor layer; and a second-conductive-type third semiconductor layer epitaxially formed on the second semiconductor layer, and having an impurity concentration higher than that of the second semiconductor layer. The semiconductor device also includes a recess formed in the third semiconductor layer, and at least a corner portion of a side face and a bottom surface is located in the second semiconductor layer. The semiconductor device also includes a first electrode in contact with the third semiconductor layer; a second electrode connected to the first electrode while being in contact with the second semiconductor layer at the bottom surface of the recess; and a third electrode in contact with a lower surface of the semiconductor substrate.03-08-2012
20120056200INTEGRATED ELECTRONIC DEVICE WITH EDGE-TERMINATION STRUCTURE AND MANUFACTURING METHOD THEREOF - An embodiment of an integrated electronic device formed in a semiconductor body delimited by a lateral surface, which includes: a substrate made of a first semiconductor material; a first epitaxial region made of a second semiconductor material, which overlies the substrate and defines a first surface; a second epitaxial region made of a third semiconductor material, which overlies the first surface and is in contact with the first epitaxial region, the third semiconductor material having a bandgap narrower than the bandgap of the second semiconductor material; an active area, extending within the second epitaxial region and housing at least one elementary electronic component; and an edge structure, arranged between the active area and the lateral surface, and including a dielectric region arranged laterally with respect to the second epitaxial region, which overlies the first surface and is in contact with the first epitaxial region.03-08-2012
20120056198SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device according to an embodiment includes a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a first semiconductor region of a second conductivity type, a second semiconductor region of the second conductivity type, a first electrode and a second electrode. The first semiconductor region is formed on at least a part of the first semiconductor layer formed on the semiconductor substrate. The second semiconductor region is formed on another part of the first semiconductor layer to reach an inside of the first semiconductor layer and having an impurity concentration higher than that of the first semiconductor region. The first electrode is formed on the second semiconductor region and a third semiconductor regions formed in a part of the first semiconductor region. The second electrode is formed to be in contact with a rear surface of the semiconductor substrate.03-08-2012
20120056195SEMICONDUCTOR DEVICE - One embodiment of a semiconductor device includes: a silicon carbide substrate including first and second principal surfaces; a first-conductive-type silicon carbide layer on the first principal surface; a second-conductive-type first silicon carbide region at a surface of the first silicon carbide layer; a first-conductive-type second silicon carbide region at the surface of the first silicon carbide region; a second-conductive-type third silicon carbide region at the surface of the first silicon carbide region; a second-conductive-type fourth silicon carbide region formed between the first silicon carbide region and the second silicon carbide region, and having an impurity concentration higher than that of the first silicon carbide region; a gate insulator; a gate electrode formed on the gate insulator; an inter-layer insulator; a first electrode connected to the second silicon carbide region and the third silicon carbide region; and a second electrode on the second principal surface.03-08-2012
20120056194BARRIER STRUCTURES AND METHODS OF FORMING SAME TO FACILITATE SILICON CARBIDE EPITAXY AND SILICON CARBIDE-BASED MEMORY FABRICATION - Embodiments of the invention relate generally to semiconductors and semiconductor fabrication techniques, and more particularly, to devices, integrated circuits, substrates, wafers and methods to form barrier structures to facilitate formation of silicon carbide epitaxy on a substrate, such as a silicon-based substrate, for fabricating various silicon carbide-based semiconductor devices, including silicon carbide-based memory elements and cells. In some embodiments, a semiconductor wafer includes a silicon substrate, a barrier-seed layer disposed over the silicon substrate, and a silicon carbide layer formed over the barrier-seed layer. The semiconductor wafer can be used to form a variety of SiC-based semiconductor devices. In one embodiment, a silicon carbide-based memory element is formed to include barrier-seed layer, multiple silicon carbide layers formed over the barrier-seed layer, and a dielectric layer formed over the multiple silicon carbide layers.03-08-2012
20120153301III-V SEMICONDUCTOR STRUCTURES INCLUDING ALUMINUM-SILICON NITRIDE PASSIVATION - A semiconductor structure includes a semiconductor layer that is passivated with an aluminum-silicon nitride layer. When the semiconductor layer in particular comprises a III-V semiconductor material such as a group III nitride semiconductor material or a gallium nitride semiconductor material, the aluminum-silicon nitride material provides a superior passivation in comparison with a silicon nitride material.06-21-2012
20120007104SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device employing silicon carbide, and the like are provided. In the semiconductor device, even when an electrode material and an upper electrode material are different, a problem does not take place at an interface at which these different types of metals are in contact with each other, thus obtaining high reliability in long-term use.01-12-2012
20120119226SEMICONDUCTOR DEVICE AND FABRICATION METHOD FOR THE SAME - A semiconductor device includes a substrate; a nitride based compound semiconductor layer placed on the substrate; an active area which is placed on the nitride based compound semiconductor layer, and is composed of an aluminum gallium nitride layer (Al05-17-2012
20120119225SILICON CARBIDE SUBSTRATE, EPITAXIAL LAYER PROVIDED SUBSTRATE, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SILICON CARBIDE SUBSTRATE - The present invention provides a silicon carbide substrate, an epitaxial layer provided substrate, a semiconductor device, and a method for manufacturing the silicon carbide substrate, each of which achieves reduced on-resistance. The silicon carbide substrate is a silicon carbide substrate having a main surface, and includes: a SiC single-crystal substrate formed in at least a portion of the main surface; and a base member disposed to surround the SiC single-crystal substrate. The base member includes a boundary region and a base region. The boundary region is adjacent to the SiC single-crystal substrate in a direction along the main surface, and has a crystal grain boundary therein. The base region is adjacent to the SiC single-crystal substrate in a direction perpendicular to the main surface, and has an impurity concentration higher than that of the SiC single-crystal substrate.05-17-2012
20120205667Semiconductor Device with Low-Conducting Field-controlling Element - A semiconductor device including a low conducting field-controlling element is provided. The device can include a semiconductor including an active region, and a set of contacts to the active region. The field-controlling element can be coupled to one or more of the contacts in the set of contacts. The field-controlling element can be formed of a low conducting layer having a sheet resistance between approximately 1008-16-2012
20120205668SWITCHING SEMICONDUCTOR DEVICES AND FABRICATION PROCESS - A switching semiconductor device is provided, in which a negative gate voltage can be applied to the semiconductor device in an OFF state so as to increase a breakdown voltage of the gate junction without impairing a normally-off function of the semiconductor device and the ON-resistance. The switching semiconductor device is fabricated by using a semiconductor substrate with a band gap of 2.0 eV or more. In a JFET structure where a p08-16-2012
20120205666JUNCTION TERMINATION STRUCTURES INCLUDING GUARD RING EXTENSIONS AND METHODS OF FABRICATING ELECTRONIC DEVICES INCORPORATING SAME - An electronic device includes a semiconductor layer, a primary junction in the semiconductor layer, a lightly doped region surrounding the primary junction and a junction termination structure in the lightly doped region adjacent the primary junction. The junction termination structure has an upper boundary, a side boundary, and a corner between the upper boundary and the side boundary, and the lightly doped region extends in a first direction away from the primary junction and normal to a point on the upper boundary by a first distance that is smaller than a second distance by which the lightly doped region extends in a second direction away from the primary junction and normal to a point on the corner. At least one floating guard ring segment may be provided in the semiconductor layer outside the corner of the junction termination structure. Related methods are also disclosed.08-16-2012
20120205670SEMICONDUCTOR DEVICE AND PROCESS FOR PRODUCTION THEREOF - A semiconductor device 08-16-2012
20120012861SEMICONDUCTOR DEVICE - A semiconductor device including a semiconductor layer of a first conductivity type; a plurality of body regions of a second conductivity type, each formed in a region extending from the surface of the semiconductor layer to a halfway portion of the same in the thickness direction, and each spaced apart from each other in a direction perpendicular to the thickness direction; source regions of the first conductivity type, each formed on the surface layer part of each body region and spaced away from the edges of each body region; a gate insulating film formed on the semiconductor layer; and gate electrodes formed on the gate insulating film. In the semiconductor layer, trenches extending between two neighboring source regions are formed by digging from the source of the semiconductor layer, the inside surface of the trenches are covered by the gate insulating film, and the gate electrodes comprise surface-facing parts, which face the surface of the semiconductor layer, and buried parts, which are buried in the trenches.01-19-2012
20120012860SIC SEMICONDUCTOR DEVICE - A SiC semiconductor device includes a reverse type MOSFET having: a substrate; a drift layer and a base region on the substrate; a base contact layer and a source region on the base region; multiple trenches having a longitudinal direction in a first direction penetrating the source region and the base region; a gate electrode in each trench via a gate insulation film; an interlayer insulation film covering the gate electrode and having a contact hole, through which the source region and the base contact layer are exposed; a source electrode coupling with the source region and the base region through the contact hole; a drain electrode on the substrate. The source region and the base contact layer extend along with a second direction perpendicular to the first direction, and are alternately arranged along with the first direction. The contact hole has a longitudinal direction in the first direction.01-19-2012
20130193445SOI STRUCTURES INCLUDING A BURIED BORON NITRIDE DIELECTRIC - Boron nitride is used as a buried dielectric of an SOI structure including an SOI layer and a handle substrate. The boron nitride is located between an SOI layer and a handle substrate. Boron nitride has a dielectric constant and a thermal expansion coefficient close to silicon dioxide. Yet, boron nitride has a wet as well as a dry etch resistance that is much better than silicon dioxide. In the SOI structure, there is a reduced material loss of boron nitride during multiple wet and dry etches so that the topography and/or bridging are not an obstacle for device integration. Boron nitride has a low dielectric constant so that devices built in SOI active regions do not suffer from a charging effect.08-01-2013
20120012862METHOD FOR MANUFACTURING SILICON CARBIDE SUBSTRATE, SILICON CARBIDE SUBSTRATE, AND SEMICONDUCTOR DEVICE - A method for manufacturing a silicon carbide substrate includes the steps of: preparing a base substrate made of silicon carbide and a SiC substrate made of single-crystal silicon carbide; and connecting the base substrate and SiC substrate to each other by forming an intermediate layer, which is made of carbon that is a conductor, between the base substrate and the SiC substrate.01-19-2012
20100148187SEMICONDUCTOR DEVICE - A semiconductor device according to an embodiment includes a transistor including a gate electrode formed on a semiconductor substrate of a predetermined crystal via a gate insulating film and a source-drain region formed in the semiconductor substrate so as to have a convex portion in a direction of a gate width and in which an epitaxial crystal having a lattice constant different from that of the predetermined crystal is embedded, and a contact plug formed on the source-drain region other than the convex portion.06-17-2010
20110049535SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes a first stacked body including a first radiator plate, a first insulating layer, a first conductive layer and a first semiconductor element in this order; a second stacked body including a second radiator plate, a second insulating layer, a second conductive layer and a second semiconductor element in this order and configured to be made of a semiconductor material different from that of the first semiconductor element; and a connecting part configured to electrically connect the first conductive layer and the second conductive layer, wherein the first stacked body and the second stacked body are thermally insulated.03-03-2011
20110049534SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In a semiconductor device and a method of manufacturing the same, a first insulation layer is removed from a cell area of a substrate and a first active pattern is formed on the first area by a laser-induced epitaxial growth (LEG) process. Residuals of the first insulation layer are passively formed into a first device isolation pattern on the first area. The first insulation layer is removed from the second area of the substrate and a semiconductor layer is formed on the second area of the substrate by a SEG process. The semiconductor layer on the second area is patterned into a second active pattern including a recessed portion and a second insulation pattern in the recessed portion is formed into a second device isolation pattern on the second area. Accordingly, grain defects in the LEG process and lattice defects in the SEG process are mitigated or eliminated.03-03-2011
20110049533SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREOF - A method of fabricating a semiconductor device is disclosed that is able to suppress a short channel effect and improve carrier mobility. In the method, trenches are formed in a silicon substrate corresponding to a source region and a drain region. When epitaxially growing p-type semiconductor mixed crystal layers to fill up the trenches, the surfaces of the trenches are demarcated by facets, and extended portions of the semiconductor mixed crystal layers are formed between bottom surfaces of second side wall insulating films and a surface of the silicon substrate, and extended portion are in contact with a source extension region and a drain extension region.03-03-2011
20110049532SILICON CARBIDE DUAL-MESA STATIC INDUCTION TRANSISTOR - A dual-mesa static induction transistor (SIT) structure includes a silicon carbide substrate having a layer arrangement formed thereon. Laterally spaced ion implanted gate regions are defined in the layer arrangement. Source regions are defined in the layer arrangement. Each of the source regions can include a channel mesa having a source mesa disposed thereon. The source mesa includes sidewalls relative to a principal plane of the substrate defining a horizontal dimension thereof. The channel mesa includes slanted sidewalls relative to the source mesa and the principal plane of the substrate. Also disclosed is a method of fabricating a dual-mesa SiC transistor device. The method includes implanting ions at a normal relative to a principal plane of the substrate to form gate junctions in upper portions of the substrate and lateral portions of the slanted channel mesas.03-03-2011
20110049531POWER SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR THE SAME - Provided is a power semiconductor device including: an insulating substrate; a circuit pattern formed on an upper surface of the insulating substrate; a power semiconductor formed on the circuit pattern; a plurality of metal socket electrode terminals formed perpendicularly to the circuit pattern or the power semiconductor so as to be in conduction with external terminals; an integral resin sleeve in which a plurality of sleeve parts are integrated, the plurality of sleeve parts being fitted with the plurality of metal socket electrode terminals from above the plurality of metal socket electrode terminals and having openings at both ends thereof; and a molding resin covering the insulating substrate, the circuit pattern, the power semiconductor, the electrode terminals, and the integral resin sleeve.03-03-2011
20110049530TRANSISTORS WITH A GATE INSULATION LAYER HAVING A CHANNEL DEPLETING INTERFACIAL CHARGE AND RELATED FABRICATION METHODS - A metal-insulator-semiconductor field-effect transistor (MISFET) includes a SiC layer with source and drain regions of a first conductivity type spaced apart therein. A first gate insulation layer is on the SiC layer and has a net charge along an interface with the SiC layer that is the same polarity as majority carriers of the source region. A gate contact is on the first gate insulation layer over a channel region of the SiC layer between the source and drain regions. The net charge along the interface between the first gate insulation layer and the SiC layer may deplete majority carriers from an adjacent portion of the channel region between the source and drain regions in the SiC layer, which may increase the threshold voltage of the MISFET and/or increase the electron mobility therein.03-03-2011
20120061688POWER SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE POWER SEMICONDUCTOR DEVICE - In a power semiconductor device that switches at a high speed, a displacement current flows at a time of switching, so that a high voltage occurs which may cause breakdown of a thin insulating film such as a gate insulating film. A semiconductor device includes: a semiconductor substrate of a first conductivity type; a drift layer of the first conductivity type formed on a first main surface of the semiconductor substrate; a first well region of a second conductivity type formed in a part of a surface layer of the drift layer; a second well region of the second conductivity type formed in a part of the surface layer of the drift layer at a distance from the first well region, the second well region having a smaller area than that of the first well region when seen above an upper surface thereof; a low-resistance region of the first conductivity type formed in a surface layer of the first well region, the low-resistance region having a higher impurity concentration than that of the first well region; a gate insulating film formed on and in contact with a surface of the first well region; and a gate electrode formed on and in contact with a surface of the gate insulating film.03-15-2012
20120061687SILICON CARBIDE SUBSTRATE AND SEMICONDUCTOR DEVICE - A silicon carbide substrate, which allows for reduced resistivity in the thickness direction thereof while restraining stacking faults from being produced due to heat treatment, includes: a base layer made of silicon carbide; and a SiC layer made of single-crystal silicon carbide and disposed on one main surface of the base layer. The base layer has an impurity concentration greater than 2×1003-15-2012
20120061684TRANSISTOR DEVICES AND METHODS OF MAKING - In an embodiment, a method of fabricating a transistor device comprises: providing a semiconductor topography comprising a gate conductor disposed above a semiconductor substrate between a pair of dielectric spacers; anisotropically etching exposed regions of the semiconductor substrate on opposite sides of the dielectric spacers to form recessed regions in the substrate; oxidizing exposed surfaces of the substrate in the recessed regions to form an oxide thereon; removing the oxide from bottoms of the recessed regions while retaining the oxide upon sidewalls of the recessed regions; and isotropically etching the substrate such that the recessed regions undercut the pair of dielectric spacers.03-15-2012
20120305944SEMICONDUCTOR ELEMENT - A semiconductor element according to the present invention can perform both a transistor operation and a diode operation via its channel layer. If the potential Vgs of its gate electrode 12-06-2012
20120061682SIC SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A SiC semiconductor device includes: a substrate, a drift layer, and a base region stacked in this order; first and second source regions and a contact layer in the base region; a trench penetrating the source and base regions; a gate electrode in the trench; an interlayer insulation film with a contact hole covering the gate electrode; a source electrode coupling with the source region and the contact layer via the contact hole; a drain electrode on the substrate; and a metal silicide film. The high concentration second source region is shallower than the low concentration first source region, and has a part covered with the interlayer insulation film, which includes a low concentration first portion near a surface and a high concentration second portion deeper than the first portion. The metal silicide film on the second part has a thickness larger than the first portion.03-15-2012
20120061686SILICON CARBIDE SUBSTRATE, SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING SILICON CARBIDE SUBSTRATE - A silicon carbide substrate allowing reduction in cost for manufacturing a semiconductor device including a silicon carbide substrate includes a base substrate composed of silicon carbide and an SiC layer composed of single crystal silicon carbide different from the base substrate and arranged on the base substrate in contact therewith. Thus, the silicon carbide substrate 03-15-2012
20120153299LED CHIP - The present invention provides a LED chip structure. The LED chip structure comprises a substrate and an N type layer disposed on the substrate; a P type layer disposed on the N type layer; a N type contact pad and a P type contact pad disposed below the substrate; conductive through holes disposed through the substrate to electrically connect the N type layer to the N type contact pad and the P type layer to the conduct heat generated by the P type layer and the N type layer downward.06-21-2012
20110042687GRAPHENE GROWTH ON A CARBON-CONTAINING SEMICONDUCTOR LAYER - A semiconductor-carbon alloy layer is formed on the surface of a semiconductor substrate, which may be a commercially available semiconductor substrate such as a silicon substrate. The semiconductor-carbon alloy layer is converted into at least one graphene layer during a high temperature anneal, during which the semiconductor material on the surface of the semiconductor-carbon alloy layer is evaporated selective to the carbon atoms. As the semiconductor atoms are selectively removed and the carbon concentration on the surface of the semiconductor-carbon alloy layer increases, the remaining carbon atoms in the top layers of the semiconductor-carbon alloy layer coalesce to form a graphene layer having at least one graphene monolayer. Thus, a graphene layer may be provided on a commercially available semiconductor substrate having a diameter of 200 mm or 300 mm.02-24-2011
20110042686SUBSTRATES AND METHODS OF FABRICATING DOPED EPITAXIAL SILICON CARBIDE STRUCTURES WITH SEQUENTIAL EMPHASIS - Embodiments of the invention relate generally to semiconductors and semiconductor fabrication techniques, and more particularly, to devices, integrated circuits, substrates, and methods to form silicon carbide structures, including doped epitaxial layers (e.g., P-doped silicon carbide epitaxial layers), by supplying sources of silicon and carbon with sequential emphasis. In some embodiments, a method of forming an epitaxial layer of silicon carbide can include depositing a layer in the presence of a silicon source, and purging gaseous materials subsequent to depositing the layer. Further, the method can include converting the layer into a sub-layer of silicon carbide in the presence of a carbon source and a dopant, and purging other gaseous materials. In some embodiments, the presence of the silicon source can be independent of the presence of the carbon source and/or the dopant.02-24-2011
20110079794METHOD FOR MANUFACTURING ELECTRONIC DEVICES INTEGRATED IN A SEMICONDUCTOR SUBSTRATE AND CORRESPONDING DEVICES - A method manufactures a vertical power MOS transistor on a semiconductor substrate comprising a first superficial semiconductor layer of a first conductivity type, comprising: forming trench regions in the first semiconductor layer, filling in said trench regions with a second semiconductor layer of a second conductivity type, to form semiconductor portions of the second conductivity type contained in the first semiconductor layer, carrying out an ion implantation of a first dopant type in the semiconductor portions for forming respective implanted body regions of said second conductivity type, carrying out an ion implantation of a second dopant type in one of the implanted body regions for forming an implanted source region of the first conductivity type inside one of the body regions, carrying out an activation thermal process of the first and second dopant types with low thermal budget suitable to complete said formation of the body and source regions.04-07-2011
20120153302RECESSED GATE-TYPE SILICON CARBIDE FIELD EFFECT TRANSISTOR AND METHOD OF PRODUCING SAME - A SiC MISFET, in which a source region and a drain region (06-21-2012
20120153303SEMICONDUCTOR ELEMENT AND METHOD FOR MANUFACTURING SAME - A semiconductor device 06-21-2012
20120153298EPITAXIAL GROWTH SYSTEM FOR FAST HEATING AND COOLING - A system for crystal growth having rapid heating and cooling. A fluid-cooling jacket having a reflective shield contained therein is disposed around a heating cylinder in which crystal growth takes place. A heating coil is disposed round the cooling jacket. The invention also includes a method of crystal growth and semiconductor devices formed using the inventive methods and systems.06-21-2012
20120153300SEMICONDUCTOR DEVICES WITH BACK SURFACE ISOLATION - Circuits, structures and techniques for independently connecting a surrounding material in a part of a semiconductor device to a contact of its respective device. To achieve this, a combination of one or more conductive wells that are electrically isolated in at least one bias polarity are provided.06-21-2012
20110079795SEMICONDUCTOR LIGHT EMITTING DEVICE, ILLUMINATION MODULE, ILLUMINATION APPARATUS, METHOD FOR MANUFACTURING SEMICONDUCTOR LIGHT EMITTING DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR LIGHT EMITTING ELEMENT - A semiconductor light emitting device (04-07-2011
20120112207METHOD TO REDUCE GROUND-PLANE POISONING OF EXTREMELY-THIN SOI (ETSOI) LAYER WITH THIN BURIED OXIDE - The present disclosure, which is directed to ultra-thin-body-and-BOX and Double BOX fully depleted SOI devices having an epitaxial diffusion-retarding semiconductor layer that slows dopant diffusion into the SOI channel, and a method of making these devices. Dopant concentrations in the SOI channels of the devices of the present disclosure having an epitaxial diffusion-retarding semiconductor layer between the substrate and SOI channel are approximately 50 times less than the dopant concentrations measured in SOI channels of devices without the epitaxial diffusion-retarding semiconductor layer.05-10-2012
20090134405SEMICONDUCTOR SUBSTRATE AND SEMICONDUCTOR DEVICE - A semiconductor substrate includes a silicon carbide substrate having a first impurity concentration, a first silicon carbide layer formed on the silicon carbide substrate and having a second impurity concentration, and a second silicon carbide layer of a first conductivity type formed on the first silicon carbide layer and having a third impurity concentration, wherein the second impurity concentration is higher than either the first impurity concentration or the third impurity concentration.05-28-2009
20090134404SILICON CARBIDE SEMICONDUCTOR DEVICE - On a major surface of an n-type silicon carbide inclined substrate (05-28-2009
20090134403DIAMOND ULTRAVIOLET SENSOR - In a conventional ultraviolet sensing device using a diamond semiconductor in a light-receiving unit, an Au-based electrode material is used for both a rectifier electrode and an ohmic electrode. However, the Au-based electrode material has fatal defects, such as poor adhesion to diamond, low mechanical strength, and furthermore poor thermal stability.05-28-2009
20090134402SILICON CARBIDE MOS FIELD-EFFECT TRANSISTOR AND PROCESS FOR PRODUCING THE SAME - In the SiC vertical MOSFET having a low-concentration p-type deposition film provided therein with a channel region and a base region resulting from reverse-implantation to n-type through ion implantation, dielectric breakdown of gate oxide film used to occur at the time of off, thereby preventing a further blocking voltage enhancement. This problem has been resolved by interposing of a low-concentration n-type deposition film between a low-concentration p-type deposition film and a high-concentration gate layer and selectively forming of a base region resulting from reverse-implantation to n-type through ion implantation in the low-concentration p-type deposition film so that the thickness of deposition film between the high-concentration gate layer and each of channel region and gate oxide layer is increased.05-28-2009
20110089433METHOD FOR MANUFACTURING NITROGEN COMPOUND SEMICONDUCTOR SUBSTRATE AND NITROGEN COMPOUND SEMICONDUCTOR SUBSTRATE, AND METHOD FOR MANUFACTURING SINGLE CRYSTAL SIC SUBSTRATE AND SINGLE CRYSTAL SIC SUBSTRATE - In order to provide a method for manufacturing a single crystal SiC substrate that can obtain an SiC layer with good crystallinity, an Si substrate 04-21-2011
20110089432WIDE BANDGAP DEVICE IN PARALLEL WITH A DEVICE THAT HAS A LOWER AVALANCHE BREAKDOWN VOLTAGE AND A HIGHER FORWARD VOLTAGE DROP THAN THE WIDE BANDGAP DEVICE - An electrical device on a single semiconductor substrate includes: an open base vertical PNP transistor placed in parallel with a wide bandgap, high voltage diode wherein the PNP transistor has a P doped collector region, an N-doped base layer, an N doped buffer layer, and a P doped emitter layer.04-21-2011
20110089431COMPOUND SINGLE CRYSTAL AND METHOD FOR PRODUCING THE SAME - A method for producing a compound single crystal includes a process (I) of growing the compound single crystal while causing an anti-phase boundary and a stacking fault to equivalently occur in a <110> direction parallel to the surface, the stacking fault being attributable to the elements A and B; a process (II) of merging and annihilating the stacking fault, attributable to the element A, and the anti-phase boundary, which occurs in the process (I); a process (III) of vanishing the stacking fault attributable to the element B, which occurs in the process (I); and a process (IV) of completely merging and annihilating the anti-phase boundary. The process (IV) is carried out simultaneously with the processes (II) and (III) or after the processes (II) and (III).04-21-2011
20090321746SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME - A low on-resistance silicon carbide semiconductor device is provided that includes an ohmic electrode of low contact resistance and high adhesion strength formed on a lower surface of silicon carbide.12-31-2009
20120161156TRIBOLOGY COMBINED WITH CORROSION RESISTANCE: A NEW FAMILY OF PVD- AND PACVD COATINGS - The present invention relates to a coating system on a substrate with improved protection against wear as well as corrosion. According to the invention the substrate is coated with a diamond like carbon (DLC) layer. This DLC layer is coated with an additional layer with material different from the DLC coating material, thereby closing the pin holes of the DLC layer.06-28-2012
20120161155SILICON CARBIDE SUBSTRATE, SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING SILICON CARBIDE SUBSTRATE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A main surface of a silicon carbide substrate is inclined by an off angle in an off direction from {0001} plane of a hexagonal crystal. The main surface has such a characteristic that, among emitting regions emitting photoluminescent light having a wavelength exceeding 650 nm of the main surface caused by excitation light having higher energy than band-gap of the hexagonal silicon carbide, the number of those having a dimension of at most 15 μm in a direction perpendicular to the off direction and a dimension in a direction parallel to the off direction not larger than a value obtained by dividing penetration length of the excitation light in the hexagonal silicon carbide by a tangent of the off angle is at most 1×1006-28-2012
20120161157SILICON CARBIDE SUBSTRATE - A silicon carbide substrate, which achieves restrained warpage even when a different-type material layer made of a material other than silicon carbide, includes: a base layer made of silicon carbide; and a plurality of SiC layers arranged side by side on the base layer when viewed in a planar view and each made of single-crystal silicon carbide. A gap is formed between end surfaces of adjacent SiC layers.06-28-2012
20120211770SEMICONDUCTOR DEVICE, COMBINED SUBSTRATE, AND METHODS FOR MANUFACTURING THEM - There are provided a semiconductor device of low cost and high quality, a combined substrate used for manufacturing the semiconductor device, and methods for manufacturing them. The method for manufacturing the semiconductor device includes the steps of: preparing a single-crystal semiconductor member; preparing a supporting base; connecting the supporting base and the single-crystal semiconductor member to each other through a connecting layer containing carbon; forming an epitaxial layer on a surface of the single-crystal semiconductor member; forming a semiconductor element using the epitaxial layer; separating the single-crystal semiconductor member from the supporting base by oxidizing and accordingly decomposing the connecting layer after the step of forming the semiconductor element; and dividing the single-crystal semiconductor member separated from the supporting base.08-23-2012
20120211769Sic single crystal wafer and process for production thereof - A SiC single crystal wafer on which a good quality epitaxial film by suppressing defects derived from the wafer can be grown has an affected surface layer with a thickness of at most 50 nm and a SiC single crystal portion with an oxygen content of at most 1.0×1008-23-2012
20120211768WIDE-BAND-GAP REVERSE-BLOCKING MOS-TYPE SEMICONDUCTOR DEVICE - A wide-band-gap reverse-blocking MOS-type semiconductor device includes a SiC n08-23-2012
20120211767POWER CONVERTER - The present power converter includes a power conversion semiconductor device, an electrode connection conductor which electrically connects multiple electrodes having the same potential, and also has a generally flat upper surface for electrically connecting to an exterior portion, and a sealing material provided so as to cover the power conversion semiconductor device, and also to expose the generally flat upper surface of the electrode connection conductor.08-23-2012
20120313112SEMICONDUCTOR DEVICE - A MOSFET includes a silicon carbide substrate, a drift layer made of silicon carbide and including a main surface having an off angle of 50° or more and 65° or less with respect to a {0001} plane, and a gate oxide film formed on and in contact with the main surface of the drift layer. The drift layer includes a p type body region formed to include a region in contact with the gate oxide film. The p type body region has an impurity density of 5×1012-13-2012
20100289033SINGLE-CRYSTAL SILICON CARBIDE INGOT, AND SUBSTRATE AND EPITAXIAL WAFER OBTAINED THEREFROM - The present invention provides a single-crystal silicon carbide ingot capable of providing a good-quality substrate low in dislocation defects, and a substrate and epitaxial wafer obtained therefrom.11-18-2010
20100289032DIFFUSED JUNCTION TERMINATION STRUCTURES FOR SILICON CARBIDE DEVICES AND METHODS OF FABRICATING SILICON CARBIDE DEVICES INCORPORATING SAME - An electronic device includes a silicon carbide layer having a first conductivity type and a main junction adjacent a surface of the silicon carbide layer, and a junction termination region at the surface of the silicon carbide layer adjacent the main junction. Charge in the junction termination region decreases with lateral distance from the main junction, and a maximum charge in the junction termination region may be less than about 2×1011-18-2010
20100289030DIAMOND SEMICONDUCTOR ELEMENT AND PROCESS FOR PRODUCING THE SAME - In a conventional diamond semiconductor element, because of high density of crystal defects, it is impossible to reflect the natural physical properties peculiar to a diamond, such as high thermal conductivity, high breakdown field strength, high-frequency characteristics and the like, in the transistor characteristics. By slightly shifting surface orientation of a diamond substrate in a [001] direction, a significant reduction in crystal defects peculiar to a diamond is possible. The equivalent effects are also provided by shifting surface orientation of a single-crystal diamond thin-film or channel slightly from a [001] direction. It is possible to obtain a significantly high transconductance gm as compared with that in a transistor produced using conventional surface orientation.11-18-2010
20120126249SEMICONDUCTOR DEVICE - The semiconductor device according to the present invention includes: a semiconductor layer made of SiC; an impurity region formed by doping the semiconductor layer with an impurity; and a contact wire formed on the semiconductor layer in contact with the impurity region, while the contact wire has a polysilicon layer in the portion in contact with the impurity region, and has a metal layer on the polysilicon layer.05-24-2012
20120126251METHOD FOR MANUFACTURING SILICON CARBIDE SUBSTRATE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, SILICON CARBIDE SUBSTRATE, AND SEMICONDUCTOR DEVICE - A method for manufacturing a silicon carbide substrate achieves reduced manufacturing cost. The method includes the steps of: preparing a base substrate and a SiC substrate; fabricating a stacked substrate by stacking the base substrate and the SiC substrate; fabricating a connected substrate by heating the stacked substrate; transferring a void, formed at a connection interface, in a thickness direction of the connected substrate by heating the connected substrate to cause the base substrate to have a temperature higher than that of the SiC substrate; and removing the void by removing a region including a main surface of the base substrate opposite to the SiC substrate.05-24-2012
20120126250SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - The present invention provides a silicon carbide semiconductor device having an ohmic electrode improved in adhesion of a wire thereto by preventing deposition of carbon so as not to form a Schottky contact, as well as a method for manufacturing such a silicon carbide semiconductor device. In the SiC semiconductor device, upon forming the ohmic electrode, a first metal layer made of one first metallic element is formed on one main surface of a SiC layer. Further, a Si layer made of Si is formed on an opposite surface of the first metal layer to its surface facing the SiC layer. The stacked structure thus formed is subjected to thermal treatment. In this way, there can be obtained a silicon carbide semiconductor device having an ohmic electrode adhered well to a wire by preventing deposition of carbon atoms on the surface layer of the electrode and formation of a Schottky contact resulting from Si and SiC.05-24-2012
20120126248MEMBRANE HAVING MEANS FOR STATE MONITORING - The invention relates to a membrane. Partly permeable membranes often have holes or perforations having a specific diameter to allow substances having a smaller particle diameter to pass through, but to hold back substances having a larger particle diameter. Such membranes are subject to wear primarily at the holes, i.e. cracks form which grow through the membrane proceeding from a hole. Particularly in the case of micromechanical membranes having holes having a small diameter in the range of 1 μm or less, it is very difficult to detect the state of the membrane, in particular whether the latter has cracks. Membranes having cracks can then undesirably allow passage even of those particles which should actually be held back. In medical or hygienic applications, the function can then be impaired.05-24-2012
20120126247SELF-POWERED INTEGRATED CIRCUIT WITH MULTI-JUNCTION PHOTOVOLTAIC CELL - A photovoltaic cell is provided as a composite unit together with elements of an integrated circuit on a common substrate. In a described embodiment, connections are established between a multiple photovoltaic cell portion and a circuitry portion of an integrated structure to enable self-powering of the circuitry portion by the multiple photovoltaic cell portion.05-24-2012
20120126246PACKAGE AND HIGH FREQUENCY TERMINAL STRUCTURE FOR THE SAME - According to one embodiment, provided is a package and high frequency terminal structure for the same including: a conductive base plate; a semiconductor device disposed on the conductive base plate; a metal wall disposed on the conductive base plate to house the semiconductor device; a through-hole disposed in input and output units of the metal wall; a lower layer feed through inserted into the through-hole and disposed on the conductive base plate; and an upper layer feed through disposed on the lower layer feed through, and adhered to a sidewall of the metal wall. The lower layer feed through is surrounded by the metal wall.05-24-2012
20120126245SHALLOW TRENCH ISOLATION STRUCTURE AND METHOD FOR FORMING THE SAME - The invention provides a STI structure and method for forming the same. The STI structure includes a semiconductor substrate; a first trench embedded in the semiconductor substrate and filled up with a first dielectric layer; and a second trench formed on a top surface of the semiconductor substrate and interconnected with the first trench, wherein the second trench is filled up with a second dielectric layer, a top surface of the second dielectric layer is flushed with that of the semiconductor substrate, and the second trench has a width smaller than that of the first trench. The invention reduces dimension of divots and improves performance of the semiconductor device.05-24-2012
20120126244SHALLOW TRENCH ISOLATION STRUCTURE AND METHOD FOR FORMING THE SAME - The invention provides a STI structure and a method for manufacturing the same. The STI includes a semiconductor substrate; a first trench formed on the upper surface of the semiconductor substrate and filled with an epitaxial layer, wherein the upper surface of the epitaxial layer is higher than that of the semiconductor substrate; and a second trench formed on the epitaxial layer and filled with a first dielectric layer, wherein the upper surface of the first dielectric layer is flush with that of the epitaxial layer, and the width of the second trench is smaller than that of the first trench. The invention reduces the influences of divots on performance of the semiconductor device.05-24-2012
20120126243TRANSISTOR INCLUDING SHALLOW TRENCH AND ELECTRICALLY CONDUCTIVE SUBSTRATE FOR IMPROVED RF GROUNDING - Disclosed is an RF power FET or HEMT including an electrically-conductive substrate, a grounding metallization layer disposed on a bottom surface of the electrically-conductive substrate, an active area comprising at least one cell including source, gate and drain electrodes disposed over a top surface of the electrically-conductive substrate, and an electrically-conductive shallow trench electrically connecting the source electrode to the grounding metallization layer by way of the electrically-conductive substrate. This configuration results in the effective RF ground being very close to the active area of the FET in order to reduce parasitic source inductance and resistance. This results in potentially higher gain, higher saturation point, higher 305-24-2012
20120248461SILICON CARBIDE SEMICONDUCTOR DEVICE - A silicon carbide layer is epitaxially formed on a main surface of a substrate. The silicon carbide layer is provided with a trench having a side wall inclined relative to the main surface. The side wall has an off angle of not less than 50° and not more than 65° relative to a {0001} plane. A gate insulating film is provided on the side wall of the silicon carbide layer. The silicon carbide layer includes: a body region having a first conductivity type and facing a gate electrode with the gate insulating film being interposed therebetween; and a pair of regions separated from each other by the body region and having a second conductivity type. The body region has an impurity density of 5×1010-04-2012
20120248462IGBT - An IGBT includes a groove provided in a silicon carbide semiconductor layer, a body region of a first conductivity type provided in the silicon carbide semiconductor layer, and an insulating film covering at least a sidewall surface of the groove, the sidewall surface of the groove being a surface having an off angle of 50° or more and 65° or less with respect to a {0001} plane, the sidewall surface of the groove including a surface of the body region, the insulating film being in contact with at least the surface of the body region at the sidewall surface of the groove, and a first conductivity type impurity concentration in the body region being 5×1010-04-2012
20120248460SYSTEMS AND METHODS FOR DEPOSITING MATERIALS ON EITHER SIDE OF A FREESTANDING FILM USING LASER-ASSISTED CHEMICAL VAPOR DEPOSITION (LA-CVD), AND STRUCTURES FORMED USING SAME - Embodiments of the present invention provide systems and methods for depositing materials on either side of a freestanding film using laser-assisted chemical vapor deposition (LA-CVD), and structures formed using same. A freestanding film, which is suspended over a cavity defined in a substrate, is exposed to a fluidic CVD precursor that reacts to form a solid material when exposed to light and/or heat. The freestanding film is then exposed to a laser beam in the presence of the precursor. The CVD precursor preferentially deposits on the surface(s) of the freestanding film.10-04-2012
20120161158COMBINED SUBSTRATE HAVING SILICON CARBIDE SUBSTRATE - A first silicon carbide substrate has a first backside surface connected to a supporting portion, a first front-side surface opposite to the first backside surface, and a first side surface connecting the first backside surface and the first front-side surface to each other. A second silicon carbide substrate has a second backside surface connected to the supporting portion, a second front-side surface opposite to the second backside surface, and a second side surface connecting the second backside surface and the second front-side surface to each other and forming a gap between the first side surface and the second side surface. A closing portion closes the gap. Thereby, foreign matters can be prevented from remaining in a gap between a plurality of silicon carbide substrates provided in a combined substrate.06-28-2012
20100207125SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device according to the present invention includes: a silicon carbide substrate (08-19-2010
20100207126MOS-Driver Compatible JFET Structure with Enhanced Gate Source Characteristics - A MOSFET driver compatible JFET device is disclosed. The JFET device can include a gate contact, a drain contact, and a source contact. The JFET device can further include a first gate region of semiconductor material adjacent the gate contact and a second region of semiconductor material adjacent the first gate region. The first gate region and the second gate region can form a first p-n junction between the first gate region and the second gate region. The JFET device can further include a channel region of semiconductor material adjacent the source contact. The channel region and the second gate region can form a second p-n junction between the second gate region and the channel region.08-19-2010
20120132926SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The semiconductor device according to the present invention includes: a semiconductor layer of a first conductivity type made of SiC having an Si surface; a gate trench dug down from the surface of the semiconductor layer; a gate insulating film formed on a bottom surface and a side surface of the gate trench so that the ratio of the thickness of a portion located on the bottom surface to the thickness of a portion located on the side surface is 0.3 to 1.0; and a gate electrode embedded in the gate trench through the gate insulating film.05-31-2012
20120132924SILICON CARBIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - In the manufacture of a silicon carbide semiconductor device having a termination region being a JTE region or FLR, the margin of the amount of etching for removing a damage layer formed in the surface of the termination region is enlarged. A silicon carbide semiconductor device has a termination region being a JTE (Junction Termination Extension) region or an FLR (Field Limiting Ring) at a termination of the semiconductor elements. The termination region is formed by one step of ion implantation in which the kind of impurity and the implant energy are fixed. In the impurity concentration profile of the termination region in the depth direction, the concentration peak in the shallowest position is in a position deeper than 0.35 μm from the surface, and the concentration in the surface portion is not more than one-tenth of the shallowest concentration peak.05-31-2012
20120132925METHOD FOR MANUFACTURING A SEMICONDUCTOR STRUCTURE, AND A CORRESPONDING SEMICONDUCTOR STRUCTURE - A method for manufacturing a semiconductor structure is provided which includes the following steps: a crystalline semiconductor substrate (05-31-2012
20120132927OHMIC ELECTRODE AND METHOD OF FORMING THE SAME - An ohmic electrode for a p-type SiC semiconductor, and a method of forming the ohmic electrode. The ohmic electrode has an ohmic electrode layer, which has an amorphous structure and which is made of a Ti05-31-2012
20120132928OHMIC ELECTRODE FOR USE IN A SEMICONDUCTOR DIAMOND DEVICE - In a semiconductor diamond device, there is provided an ohmic electrode that is chemically, and thermally stable, and is excellent in respect of low contact resistance, and high heat resistance. A nickel-chromium alloy, or a nickel-chromium compound, containing Ni, and Cr such as Ni05-31-2012
20110180814INSULATED GATE FIELD EFFECT TRANSISTOR - A MOSFET, which is capable of reducing on resistance by reducing channel mobility even when a gate voltage is high, includes: an n type substrate made of SiC and having a main surface with an off angle of 50°-65° relative to a {0001} plane; an n type reverse breakdown voltage holding layer made of SiC and formed on the main surface of the substrate; a p type well region formed in the reverse breakdown voltage holding layer distant away from a first main surface thereof; a gate oxide film formed on the well region; an n type contact region disposed between the well region and the gate oxide film; a channel region connecting the n type contact region and the reverse breakdown voltage holding layer; and a gate electrode disposed on the gate oxide film. In a region including an interface between the channel region and the gate oxide film, a high-concentration nitrogen region is formed.07-28-2011
20110180813INSULATED GATE BIPOLAR TRANSISTOR - An IGBT, which is capable of reducing on resistance by reducing channel mobility, includes: an n type substrate made of SiC and having a main surface with an off angle of not less than 50° and not more than 65° relative to a plane orientation of {0001}; a p type reverse breakdown voltage holding layer made of SiC and formed on the main surface of the substrate; an n type well region formed to include a second main surface of the reverse breakdown voltage holding layer; an emitter region formed in the well region to include the second main surface and including a p type impurity at a concentration higher than that of the reverse breakdown voltage holding layer; a gate oxide film formed on the reverse breakdown voltage holding layer; and a gate electrode formed on the gate oxide film. In a region including an interface between the well region and the gate oxide film, a high-concentration nitrogen region is formed to have a nitrogen concentration higher than those of the well region and the gate oxide film.07-28-2011
20110180812SEMICONDUCTOR DEVICE - A MOSFET which is a semiconductor device capable of achieving a stable reverse breakdown voltage and reduced on-resistance includes a SiC wafer of an n conductivity type, a plurality of p bodies of a p conductivity type formed to include a first main surface of the SiC wafer, and n07-28-2011
20110180811WIRELESS CHIP AND ELECTRONIC DEVICE HAVING WIRELESS CHIP - It is an object to provide a wireless chip which can increase a mechanical strength, and a wireless chip with a high durability. A wireless chip includes a transistor including a field-effect transistor, an antenna including a dielectric layer sandwiched between conductive layers, and a conductive layer connecting the chip and the antenna. Further, a wireless chip includes a transistor including a field-effect transistor, an antenna including a dielectric layer sandwiched between conductive layers, a sensor device, a conductive layer connecting the chip and the antenna, and a conductive layer connecting the chip and the sensor device. Moreover, a wireless chip includes a transistor including a field-effect transistor, an antenna including a dielectric layer sandwiched between conductive layers, a battery, a conductive layer connecting the chip and the antenna, and a conductive layer connecting the chip and the battery.07-28-2011
20110180810Semiconductor Arrangement and Method for Producing a Semiconductor Arrangement - A semiconductor arrangement includes a ceramic mount and at least one semiconductor component fixed-to the ceramic mount. The ceramic mount includes a first section, and the first section is electrically conductive.07-28-2011
20110180809SEMICONDUCTOR DEVICE MODULE - A P-side package unit and a N-side package unit are arranged on a main surface of a metal heatsink such that a main surface extends in a direction perpendicular to the main surface of the heatsink. Each of the P-side package unit and the N-side package unit is fixed by an end edge portion of a heatsink being clipped by a rail-shaped unit mounting part provided on the main surface of the heatsink.07-28-2011
20110180808METHOD OF MAKING A MOUNTED GALLIUM NITRIDE DEVICE - A method of making a mounted gallium nitride (GaN) device includes obtaining a device structure comprising a silicon layer, a silicon carbide (SiC) layer over the silicon layer, and a GaN layer over the SiC layer. The GaN layer is processed to form an active layer of active devices and interconnect over the GaN layer. After the step of processing the GaN layer, a gold layer is formed on the silicon layer. The device structure is attached to a heat sink structure using the gold layer. The mounted GaN device includes the SiC layer over the polysilicon layer and the GaN layer over the SiC layer. The active layer is over the GaN layer.07-28-2011
20110180807INFRARED EXTERNAL PHOTOEMISSIVE DETECTOR - An infrared external photoemissive detector can have an n-p heterojunction comprising an n-type semiconductor layer and a p-layer; the n-layer semiconductor comprising doped silicon embedded with nanoparticles forming Schottky barriers; and the p-layer is a p-type diamond film. The nanoparticles can be about 20-30 atomic percentage metal particles (such as silver) having an average particle size of about 5-10 nm. The p-layer can have a surface layer that has a negative electron affinity. The n-layer can be in the range of about 3 μm to 10 μm thick, and preferably about 3 μm thick. The doped silicon can be doped with elements selected from the list consisting of phosphorus and antimony.07-28-2011
20120132923SUBSTRATE FOR INTEGRATED CIRCUIT AND METHOD FOR FORMING THE SAME - The present invention relates to substrates for ICs and method for forming the same. The method comprises the steps of: forming a hard mask layer on the bulk silicon material; etching the hard mask layer and the bulk silicon material to form a first part for shallow trench isolation of at least one trench; forming a dielectric film on the sidewall of the at least one trench; further etching the bulk silicon material to deepen the at least one trench so as to form a second part of the at least one trench; completely oxidizing or nitridizing parts of the bulk silicon material which are between the second parts of the trenches, and parts of the bulk silicon material which are between the second parts of the trenches and side surfaces of the bulk silicon substrate; filling dielectric materials in the first and second parts of the at least one trench; and removing the hard mask layer.05-31-2012
20090057686SEMICONDUCTOR DEVICE AND ELECTRIC POWER CONVERTER, DRIVE INVERTER, GENERAL-PURPOSE INVERTER AND SUPER-POWER HIGH-FREQUENCY COMMUNICATION EQUIPMENT USING THE SEMICONDUCTOR DEVICE - In a semiconductor device that uses a silicon carbide semiconductor substrate having p type, n type impurity semiconductor regions formed by ion implantation, the electrical characteristics of the end semiconductor device can be improved by decreasing the roughness of the silicon carbide semiconductor substrate surface. The semiconductor device of this invention is a Schottky barrier diode or a p-n type diode comprising at least one of a p type semiconductor region and n type semiconductor region selectively formed in a silicon carbide semiconductor region having an outermost surface layer surface that is a (000-1) surface or a surface inclined at an angle to the (000-1) surface, and a metal electrode formed on the outermost surface layer surface, that controls a direction in which electric current flows in a direction perpendicular to the outermost surface layer surface from application of a voltage to the metal electrode.03-05-2009
20090057685BIPOLAR DEVICE AND FABRICATION METHOD THEREOF - In a mesa type bipolar transistor or a thyristor, since carriers injected from an emitter layer or an anode layer to a base layer or a gate layer diffuse laterally and are recombined, reduction in the size and improvement for the switching frequency is difficult.03-05-2009
20120168775STRESS ENHANCED TRANSISTOR DEVICES AND METHODS OF MAKING - A transistor device includes a gate conductor spaced above a semiconductor substrate by a gate dielectric, wherein the semiconductor substrate comprises a channel region underneath the gate conductor and recessed regions on opposite sides of the channel region, wherein the channel region comprises undercut areas under the gate conductor; a stressed material embedded in the undercut areas of the channel region under the gate conductor; and epitaxially grown source and drain regions disposed in the recessed regions of the semiconductor substrate laterally adjacent to the stressed material.07-05-2012
20120168774SILICON CARBIDE SUBSTRATE AND METHOD FOR MANUFACTURING SAME - A silicon carbide substrate and a method for manufacturing the silicon carbide substrate are obtained, each of which achieves reduced manufacturing cost of semiconductor devices using the silicon carbide substrate. A method for manufacturing a SiC-combined substrate includes the steps of: preparing a plurality of single-crystal bodies each made of silicon carbide (SiC); forming a collected body; connecting the single-crystal bodies to each other; and slicing the collected body. In the step, the plurality of SiC single-crystal ingots are arranged with a silicon (Si) containing Si layer interposed therebetween, so as to form the collected body including the single-crystal bodies. In the step, adjacent SiC single-crystal ingots are connected to each other via at least a portion of the Si layer, the portion being formed into silicon carbide by heating the collected body. In step, the collected body in which the SiC single-crystal ingots are connected to each other is sliced.07-05-2012
20120168773SEMICONDUCTOR-ON-DIAMOND DEVICES AND ASSOCIATED METHODS - Semiconductor-on-diamond (SOD) substrates and methods for making such substrates are provided. In one aspect, a method of making an SOD substrate may include depositing a base layer onto a lattice-orienting silicon (Si) substrate such that the base layer lattice is substantially oriented by the Si substrate, depositing a semiconductor layer onto the base layer such that the semiconductor layer lattice is substantially oriented with respect to the base layer lattice, and disposing a layer of diamond onto the semiconductor layer. The base layer may include numerous materials, including, without limitation, aluminum phosphide (AlP), boron arsenide (BAs), gallium nitride (GaN), indium nitride (InN), and combinations thereof. Additionally, the method may further include removing the lattice-orienting Si substrate and the base layer from the semiconductor layer. In one aspect, the Si substrate may be of a single crystal orientation.07-05-2012
20100051963POWER TRANSISTOR - A power transistor. One embodiment provides a power transistor having a first terminal, a second terminal and a control terminal. A support layer is formed of a first material having a first bandgap. An active region is formed of a second material having a second bandgap wider than the first bandgap, and is disposed on the support layer. The active region is arranged to form part of a current path between the first and second terminal in a forward mode of operation. The active region includes at least one pn-junction.03-04-2010
20100051964METHOD FOR PREPARING A SEMICONDUCTOR ULTRANANOCRYSTALLINE DIAMOND FILM AND A SEMICONDUCTOR ULTRANANOCRYSTALLINE DIAMOND FILM PREPARED THEREFROM - A method for preparing a semiconductor ultrananocrystalline diamond (UNCD) film includes doping an UNCD film with an ion source at a dose not less than 1003-04-2010
20120313111DIE ALIGNMENT WITH CRYSTALLOGRAPHIC AXES IN GaN-ON-SiC AND OTHER NON-CUBIC MATERIAL SUBSTRATES - A semiconductor chip comprises: a semiconductor structure having a single crystal substrate having a non-cubic crystallographic structure and epitaxial layers disposed on the substrate wherein adjacent sides of the semiconductor structure are at oblique angles. A method for separating a plurality of integrated circuit chips. The method includes: providing a semiconductor wafer having single crystal substrate, such substrate having a non-cubic crystallographic structure with an epitaxial layer disposed on the substrate; forming scribe lines at oblique angles to one another in the epitaxial layer; and cutting or cleaving through the substrate along the scribe lines to separate the chips.12-13-2012
20090127566Method of Selectively Forming Atomically Flat Plane on Diamond Surface, Diamond Substrate Produced by The Method, and Semiconductor Device Using The Same05-21-2009
20120175638SEMICONDUCTOR DEVICE - A MOSFET includes: a silicon carbide substrate having a main surface having an off angle of not less than 50° and not more than 65° relative to a {0001} plane; an active layer; a gate oxide film; a p type body region having p type conductivity and formed to include a region of the active layer, the region being in contact with the gate oxide film; an n07-12-2012
20120175637SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - According to one embodiment, a semiconductor device including: a substrate; a gate electrode formed above the substrate; a gate insulating film formed under the gate electrode; a channel layer formed under the gate insulating film by using a channel layer material; a source region and a drain region formed in the substrate so as to interpose the channel layer therebetween in a channel direction; and a source extension layer formed in the substrate between the channel layer and the source region so as to overlap a source-side end portion of the channel layer. The source extension layer forms a heterointerface with the channel layer. The heterointerface is a tunnel channel for carries.07-12-2012
20120175636PHOTODIODE DEVICE BASED ON WIDE BANDGAP MATERIAL LAYER AND BACK-SIDE ILLUMINATION (BSI) CMOS IMAGE SENSOR AND SOLAR CELL INCLUDING THE PHOTODIODE DEVICE - According to example embodiments, a photodiode system may include a substrate, and at least one photodiode in the substrate, and a wideband gap material layer on a first surface of the substrate. The at least one photodiode may be between an insulating material in a horizontal plane. According to example embodiments, a back-side-illumination (BSI) CMOS image sensor and/or a solar cell may include a photodiode device. The photodiode device may include a substrate, at least one photodiode in the substrate, a wide bandgap material layer on a first surface of the substrate, and an anti-reflective layer (ARL) on the wide bandgap material layer.07-12-2012
20120175635Semiconductor Device Arrangement with a First Semiconductor Device and with a Plurality of Second Semiconductor Devices - A semiconductor device arrangement includes a first semiconductor device having a load path, and a number of second transistors, each having a load path between a first and a second load terminal and a control terminal. The second transistors have their load paths connected in series and connected in series to the load path of the first transistor. Each of the second transistors has its control terminal connected to the load terminal of one of the other second transistors. One of the second transistors has its control terminal connected to one of the load terminals of the first semiconductor device.07-12-2012
20120175641DIAMOND N-TYPE SEMICONDUCTOR, METHOD OF MANUFACTURING THE SAME, SEMICONDUCTOR DEVICE, AND ELECTRON EMITTING DEVICE - The present invention relates to a diamond n-type semiconductor in which the amount of change in carrier concentration is fully reduced in a wide temperature range. The diamond n-type semiconductor comprises a diamond substrate, and a diamond semiconductor formed on a main surface thereof and turned out to be n-type. The diamond semiconductor exhibits a carrier concentration (electron concentration) negatively correlated with temperature in a part of a temperature region in which it is turned out to be n-type, and a Hall coefficient positively correlated with temperature. The diamond n-type semiconductor having such a characteristic is obtained, for example, by forming a diamond semiconductor doped with a large amount of a donor element while introducing an impurity other than the donor element onto the diamond substrate.07-12-2012
20120175640SEMICONDUCTOR DEVICES HAVING TENSILE AND/OR COMPRESSIVE STRESS AND METHODS OF MANUFACTURING - Semiconductor devices are provided which have a tensile and/or compressive strain applied thereto and methods of manufacturing. The structure includes a gate stack comprising an oxide layer, a polysilicon layer and sidewalls with adjacent spacers. The structure further includes an epitaxially grown straining material directly on the polysilicon layer and between portions of the sidewalls. The epitaxially grown straining material, in a relaxed state, strains the polysilicon layer.07-12-2012
20120175634Transistor Arrangement with a First Transistor and with a Plurality of Second Transistors - A transistor arrangement includes a first transistor having a drift region and a number of second transistors, each having a source region, a drain region and a gate electrode. The second transistors are coupled in series to form a series circuit that is coupled in parallel with the drift region of the first transistor.07-12-2012
20100270561Method for manufacturing a cubic silicon carbide single crystal thin film and semiconductor device based on the cubic silicon carbide single crystal thin film - A cubic silicon carbide single crystal thin film is manufactured by a method. A sacrificial layer is formed on a surface of a substrate. A cubic semiconductor layer is formed on the sacrificial layer, the cubic semiconductor layer having at least a surface of cubic crystal structure. A cubic silicon carbide single crystal layer is formed on the cubic semiconductor layer. The sacrificial layer is etched away to release a multilayer structure of the cubic semiconductor layer and the 3C—SiC layer from the substrate. A cubic silicon carbide single crystal thin film of a multilayer structure includes an Al10-28-2010
20120074429GROWTH OF NON-POLAR M-PLANE III-NITRIDE FILM USING METALORGANIC CHEMICAL VAPOR DEPOSITION (MOCVD) - A method of growing non-polar m-plane III-nitride film, such as GaN, AlN, AlGaN or InGaN, wherein the non-polar m-plane III-nitride film is grown on a suitable substrate, such as an m-SiC, m-GaN, LiGaO03-29-2012
20120074428SEMICONDUCTOR MODULE INCLUDING A SWITCH AND NON-CENTRAL DIODE - A semiconductor module having one or more silicon carbide diode elements mounted on a switching element is provided in which the temperature rise is reduced by properly disposing each of the diode elements on the switching element, to thereby provide a thermal dissipation path for the respective diode elements. The respective diode elements are arranged on a non-central portion of the switching element, to facilitate dissipation of the heat produced by each of the diode elements, whereby the temperature rise in the semiconductor module is reduced.03-29-2012
20100006861Silicon carbide semiconductor device and manufacturing method of the same - A SiC semiconductor device includes: a substrate; a drift layer on a first side of the substrate; a trench in the drift layer; a base region contacting a sidewall of the trench; a source region in an upper portion of the base region; a gate electrode in the trench via a gate insulation film; a source electrode on the source region; and a drain electrode on a second side of the substrate. The source region has multi-layered structure including a first layer and a second layer. The first layer as an upper layer contacts the source electrode with ohmic contact. The second layer as a lower layer has an impurity concentration, which is lower than an impurity concentration of the first layer.01-14-2010
20100006859Method of Manufacturing Substrates Having Improved Carrier Lifetimes - This invention relates to a method for depositing silicon carbide material onto a substrate such that the resulting substrate has a carrier lifetime of 0.5-1000 microseconds, the method comprising a. introducing a gas mixture comprising a chlorosilane gas, a carbon-containing gas, and hydrogen gas into a reaction chamber containing a substrate; and b. heating the substrate to a temperature of greater than 1000° C. but less than 2000° C.; with the proviso that the pressure within the reaction chamber is maintained in the range of 0.1 to 760 torr. This invention also relates to a method for depositing silicon carbide material onto a substrate such that the resulting substrate has a carrier lifetime of 0.5-1000 microseconds, the method comprising a. introducing a gas mixture comprising a non-chlorinated silicon-containing gas, hydrogen chloride, a carbon-containing gas, and hydrogen gas into a reaction chamber containing a substrate; and b. heating the substrate to a temperature of greater than 1000° C. but less than 2000° C.; with the proviso that the pressure within the reaction chamber is maintained in the range of 0.1 to 760 torr.01-14-2010
20120223339SEMICONDUCTOR DEVICE - A semiconductor device includes a first conduction type semiconductor substrate, a first conduction type semiconductor deposition layer, a trench, second conduction type wells, a JFET region, a first conduction type first source region, a first source region, a trench-type source electrode, a gate insulator film, a gate electrode, and a drain electrode. The trench is formed substantially perpendicularly to the semiconductor deposition layer so that the semiconductor deposition layer exposes to a bottom of the trench. The second conduction type second source region are formed in the first conduction type first source region. The trench-type source electrode is in contact with the first source region, the second source region, and the first conduction type semiconductor deposition layer to configure a Schottky junction.09-06-2012
20120223337NITRIDE SEMICONDUCTOR DIODE - In a Schottky electrode formation region on a nitride semiconductor, the total length of junctions of Schottky electrodes and a surface of a nitride semiconductor layer is longer than the perimeter of the Schottky electrode formation region. The total length is preferably 10 times longer than the perimeter. For example, the Schottky electrodes are formed concentrically and circularly.09-06-2012
20120223336SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate including a collector layer of a first conductivity type and a drift layer of a second conductivity type in contact with said collector layer, said drift layer receiving a supply of carriers from said collector layer. The semiconductor device further includes a lattice defect formed to penetrate through said semiconductor substrate and enclose a predetermined portion of said semiconductor substrate, a sense emitter electrode formed on the top surface of said predetermined portion, and a collector electrode formed on the bottom surface of said predetermined portion.09-06-2012
20120223332SEMICONDUCTOR RECTIFYING DEVICE - A semiconductor rectifying device of an embodiment includes a first-conductive-type semiconductor substrate made of a wide bandgap semiconductor, a first-conductive-type semiconductor layer formed on an upper surface of the semiconductor substrate and made of the wide bandgap semiconductor having an impurity concentration lower than that of the semiconductor substrate, a first-conductive-type first semiconductor region formed at a surface of the semiconductor layer and made of the wide bandgap semiconductor, a second-conductive-type second semiconductor region formed around the first semiconductor region and made of the wide bandgap semiconductor, a second-conductive-type third semiconductor region formed around the first semiconductor region and made of the wide bandgap semiconductor having a junction depth deeper than a junction depth of the second semiconductor region, a first electrode that is formed on the first, second, and third semiconductor regions, and a second electrode formed on a lower surface of the semiconductor substrate.09-06-2012
20120187421VERTICAL JUNCTION FIELD EFFECT TRANSISTORS AND DIODES HAVING GRADED DOPED REGIONS AND METHODS OF MAKING - Semiconductor devices and methods of making the devices are described. The devices can be junction field-effect transistors (JFETs) or diodes such as junction barrier Schottky (JBS) diodes or PiN diodes. The devices have graded p-type semiconductor layers and/or regions formed by epitaxial growth. The methods do not require ion implantation. The devices can be made from a wide-bandgap semiconductor material such as silicon carbide (SiC) and can be used in high temperature and high power applications.07-26-2012
20120187420STRUCTURE AND METHOD TO MAKE REPLACEMENT METAL GATE AND CONTACT METAL - An electrical device is provided that in one embodiment includes a p-type semiconductor device having a first gate structure that includes a gate dielectric that is present on the semiconductor substrate, a p-type work function metal layer, a metal layer composed of titanium and aluminum, and a metal fill composed of aluminum. An n-type semiconductor device is also present on the semiconductor substrate that includes a second gate structure that includes a gate dielectric, a metal layer composed of titanium and aluminum, and a metal fill composed of aluminum. An interlevel dielectric is present over the semiconductor substrate. The interlevel dielectric includes interconnects to the source and drain regions of the p-type and n-type semiconductor devices. The interconnects are composed of a metal layer composed of titanium and aluminum, and a metal fill composed of aluminum. The present disclosure also provides a method of forming the aforementioned structure.07-26-2012
20120187419Production Method for a Unipolar Semiconductor Component and Semiconductor Device - The invention relates to a production method for a unipolar semiconductor component having a drift layer (07-26-2012
20120187418SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - The present application provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure comprises a semiconductor substrate, a semiconductor fin located on the semiconductor substrate, and an etch stop layer located between the semiconductor substrate and the semiconductor fin, wherein a lateral sidewall of the semiconductor fin is substantially on the Si {07-26-2012
20120187417SEMICONDUCTOR DEVICE - A conventional DRAM needs to be refreshed at an interval of several tens of milliseconds to hold data, which results in large power consumption. In addition, a transistor therein is frequently turned on and off; thus, deterioration of the transistor is also a problem. These problems become significant as the memory capacity increases and transistor miniaturization advances. Another problem is that an increase in memory capacity leads to an increase in the area, despite an attempt at integration through advancement of transistor miniaturization. A transistor is provided which includes an oxide semiconductor and has a trench structure including a trench for a gate electrode and a trench for element isolation. In addition, a plurality of memory elements each including the transistor having a trench structure and including an oxide semiconductor is stacked in a semiconductor device, whereby the circuit area of the semiconductor device can be reduced.07-26-2012
20120187416SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate having a collector layer in which the carrier concentration is maximized at a carrier concentration peak position that is 1 μm or more from a surface of the semiconductor substrate. The semiconductor device further includes a collector electrode formed in contact with a surface of the collector layer.07-26-2012
20090302326SILICON CARBIDE SINGLE CRYSTAL WAFER AND PRODUCING METHOD THEREOF - A silicon carbide single crystal wafer wherein a substrate is cut out at an OFF angle from a (0001) c plane of an α-type silicon carbide single crystal of less than 2° and in an OFF direction in which a deviation from a (11-20) direction is less than 10°, the number of substantially triangular lamination defects exposed from a surface of a wafer which is epitaxial grown on the substrate is less than 4/cm12-10-2009
20120119224COMPOSITE SUBSTRATE AND METHOD FOR MANUFACTURING COMPOSITE SUBSTRATE - A metal film 05-17-2012
20120256196SCHOTTKY DIODE - A semiconductor system of a Schottky diode is described having an integrated PN diode as a clamping element, which is suitable in particular as a Zener diode having a breakdown voltage of approximately 20 V for use in motor vehicle generator systems. The semiconductor system of the Schottky diode includes a combination of a Schottky diode and a PN diode. The breakdown voltage of the PN diode is much lower than the breakdown voltage of the Schottky diode, the semiconductor system being able to be operated using high currents during breakdown operation.10-11-2012
20120256194SEMICONDUCTOR DEVICE - Disclosed is a semiconductor device having a structure capable of reducing the self-inductance of internal wiring. The semiconductor device includes: a lower board having a lower conductor layer formed on the surface thereof; a switching element bonded to the lower conductor layer in an element bonding area; a terminal bonded to the lower conductor layer in a terminal bonding area; an upper board stacked on the lower board in a board bonding area between the element bonding area and the terminal bonding area, and having an upper conductor layer on the surface thereof; and a switching element connecting member which connects the switching element with the upper conductor layer.10-11-2012
20120223333SEMICONDUCTOR RECTIFIER DEVICE - A semiconductor rectifier device according to an embodiment includes a semiconductor substrate of a first conductive type of a wide gap semiconductor, a semiconductor layer of the first conductive type of the wide gap semiconductor formed on an upper surface of the semiconductor substrate, wherein an impurity concentration of the semiconductor layer is between 1E+14 atoms/cm09-06-2012
20120223331SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A semiconductor device comprises: a semiconductor substrate located on an insulating layer; and an insulator located on the insulating layer and embedded in the semiconductor substrate, wherein the insulator applies stress therein to the semiconductor substrate. A method for forming a semiconductor device comprises: forming a semiconductor substrate on an insulating layer; forming a cavity within the semiconductor substrate so as to expose the insulating layer; forming an insulator in the cavity, wherein the insulator applies stress therein to the semiconductor substrate. It facilitates the reduction of the short channel effect, the resistance of source/drain regions and parasitic capacitance.09-06-2012
20120223340VERTICAL JUNCTION FIELD EFFECT TRANSISTORS HAVING SLOPED SIDEWALLS AND METHODS OF MAKING - Semiconductor devices and methods of making the devices are described. The devices can be junction field-effect transistors (JFETs). The devices have raised regions with sloped sidewalls which taper inward. The sidewalls can form an angle of 5° or more from vertical to the substrate surface. The devices can have dual-sloped sidewalls in which a lower portion of the sidewalls forms an angle of 5° or more from vertical and an upper portion of the sidewalls forms an angle of <5° from vertical. The devices can be made using normal (i.e., 0°) or near normal incident ion implantation. The devices have relatively uniform sidewall doping and can be made without angled implantation.09-06-2012
20120223338SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device includes the steps of forming a silicon oxide film on a silicon carbide substrate, annealing the silicon carbide substrate and the silicon oxide film in gas containing hydrogen, and forming an aluminum oxynitride film on the silicon oxide film after the annealing of the silicon carbide substrate and the silicon oxide film.09-06-2012
20120223335METHOD OF MARKING SiC SEMICONDUCTOR WAFER AND SiC SEMICONDUCTOR WAFER - Marking of an SiC wafer with an identifier is realized by irradiation with a pulsed laser using a harmonic of a wavelength four times that of a YAG laser. A speed at which a laser head moves, an orbit in which the laser head moves, the output power and Q-switch frequency of a pulsed laser to be applied, and the like are determined such that pulse-irradiated marks formed as a result of irradiation with corresponding pulses of the pulsed laser do not overlap each other.09-06-2012
20120223334DOPED DIAMOND LED DEVICES AND ASSOCIATED METHODS - LED devices and methods for making such devices are provided. One such method may include forming epitaxially a substantially single crystal SiC layer on a substantially single crystal Si wafer, forming epitaxially a substantially single crystal diamond layer on the SiC layer, doping the diamond layer to form a conductive diamond layer, removing the Si wafer to expose the SiC layer opposite to the conductive diamond layer, forming epitaxially a plurality of semiconductor layers on the SiC layer such that at least one of the semiconductive layers contacts the SiC layer, and coupling an n-type electrode to at least one of the semiconductor layers such that the plurality of semiconductor layers is functionally located between the conductive diamond layer and the n-type electrode.09-06-2012
20120256193MONOLITHIC INTEGRATED CAPACITORS FOR HIGH-EFFICIENCY POWER CONVERTERS - A semiconductor structure such as a power converter with an integrated capacitor is provided, and comprises a semiconductor substrate, a high-side output power device over the substrate at a first location, and a low-side output power device over the substrate at a second location adjacent to the first location. A first metal layer is over the high-side output power device and electrically coupled to the high-side output power device, and a second metal layer is over the low-side output power device and electrically coupled to the low-side output power device. A dielectric layer is over a portion of the first metal layer and a portion of the second metal layer, and a top metal layer is over the dielectric layer. The integrated capacitor comprises a first bottom electrode that includes the portion of the first metal layer, a second bottom electrode that includes the portion of the second metal layer, the dielectric layer over the portions of the first and second metal layers, and a top electrode that includes the top metal layer over the dielectric layer.10-11-2012
20120256195SEMICONDUCTOR DEVICE - A semiconductor device capable of decreasing a reverse leakage current and a forward voltage is provided. In the semiconductor device, an anode electrode undergoes Schottky junction by being connected to a surface of an SiC epitaxial layer that has the surface, a back surface, and trapezoidal trenches formed on the side of the surface each having side walls and a bottom wall. Furthermore, an edge portion of the bottom wall of each of the trapezoidal trenches is formed to be in the shape bent towards the outside of the trapezoidal trench in the manner that a radius of curvature R satisfies 0.0110-11-2012
20120256192RECESSED TERMINATION STRUCTURES AND METHODS OF FABRICATING ELECTRONIC DEVICES INCLUDING RECESSED TERMINATION STRUCTURES - An electronic device includes a drift region, a Schottky contact on a surface of the drift region, and an edge termination structure in the drift region adjacent the Schottky contact. The edge termination structure includes a recessed region that is recessed from the surface of the drift region by a distance d that may be about 0.5 microns.10-11-2012
20090020766POWER SEMICONDUCTOR DEVICE - A power semiconductor device less prone to cause a reaction between a metal material for interconnection and an electrode or the like connected to a semiconductor region during the high-temperature operation thereof and less prone to be strained during the high-temperature operation thereof. The power semiconductor device can be an SiC power device or the like in which a first metal layer containing at least one selected from the group consisting of Pt, Ti, Mo, W and Ta is formed on a source electrode formed on the semiconductor region, such as a source region or the like. A second metal layer containing at least one selected from the group consisting of Mo, W and Cu is formed on the first metal layer. A third metal layer containing at least one selected from the group consisting of Pt, Mo and W is formed on the second metal layer.01-22-2009
20090020765Semiconductor Device and Method for Manufacturing Same - A semiconductor device includes a first conductive type SiC semiconductor substrate; a second conductive type well formed on the SiC semiconductor substrate; a first impurity diffusion layer formed by introducing a first conductive type impurity so as to be partly overlapped with the well in a region surrounding the well; a second impurity diffusion layer formed by introducing the first conductive type impurity in a region spaced apart for a predetermined distance from the impurity diffusion layer in the well; and a gate electrode opposed to a channel region between the first and the second impurity diffusion layers with gate insulating film sandwiched therebetween.01-22-2009
20120228638Methods of Fabricating Silicon Carbide Devices Having Smooth Channels and Related Devices - Methods of forming silicon carbide power devices are provided. An n09-13-2012
20120228637SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device of an embodiment includes a first conductive type silicon carbide substrate having first and second main surfaces, a first conductive type silicon carbide layer formed on the first main surface, a second conductive type first silicon carbide region formed in the silicon carbide layer, and a first conductive type second silicon carbide region formed in the first silicon carbide region. The device includes a trench penetrating through the first and second silicon carbide regions, and a second conductive type third silicon carbide region formed on a bottom and a side surface of the trench. The third silicon carbide region is in contact with the first silicon carbide region, and is formed between the trench and the silicon carbide layer. In addition, the device includes a gate insulating film formed in the trench, a gate electrode, a first electrode, and a second electrode.09-13-2012
20120228636SCHOTTKY BARRIER DIODE - A third insulating layer is formed in a periphery region of a substrate over a first surface (main surface) of the substrate so as to straddle a second semiconductor layer closest to a guard ring layer and a second semiconductor layer closest to the second semiconductor layer. In other words, the third insulating layer is formed to cover a portion of the first semiconductor layer, which is exposed to the first surface (main surface) of the substrate and which is between the second semiconductor layers. Thereby, the third insulating layer electrically insulates the metal layer from the portion of the first semiconductor layer, which is exposed to the first surface (main surface) of the substrate and which is between the second semiconductor layers.09-13-2012
20120228635SEMICONDUCTOR RECTIFIER DEVICE - A semiconductor rectifier device using an SiC semiconductor at least includes: an anode electrode; an anode area that adjoins the anode electrode and is made of a second conductivity type semiconductor; a drift layer that adjoins the anode area and is made of a first conductivity type semiconductor having a low concentration; a minority carrier absorption layer that adjoins the drift layer and is made of a first conductivity type semiconductor having a higher concentration than that of the drift layer; a high-resistance semiconductor area that adjoins the minority carrier absorption layer, has less thickness than the drift layer and is made of a first conductivity type semiconductor having a concentration lower than that of the minority carrier absorption layer; a cathode contact layer that adjoins the semiconductor area; and a cathode electrode.09-13-2012
20120228634COMBINED SEMICONDUCTOR DEVICE - A combined semiconductor device performs low conduction loss and low recovery loss characteristics suited to a circuit technology in a soft switching mode at a low cost. The device has a SJ-MOSFET and a wide band gap Schottky barrier diode connected in parallel to a built-in body diode in the SJ-MOSFET. The device includes a MOS type semiconductor element having a superjunction structure and a wide band gap Schottky barrier diode antiparallel-connected to the MOS type semiconductor element. The MOS type semiconductor element has a resistance section series-connected to a built-in body diode in the element. A resistance value of the resistance section is such a value that the forward voltage drop of the built-in body diode in the MOS type semiconductor element is higher than the forward voltage drop of the wide band gap Schottky barrier diode at a rated current of the MOS type semiconductor element.09-13-2012
20120228633SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor substrate; a first conductivity type semiconductor layer that is formed on the substrate and is made of silicon carbide; an active area formed on a surface of the semiconductor layer; a first semiconductor area of a second conductivity type formed on the surface of the semiconductor layer to surround the active area; a second semiconductor area, provided to adjoin an outer side of the first semiconductor area on the surface of the semiconductor layer and surround the first semiconductor area, in which a second conductivity type impurity area having the same impurity concentration and the same depth as those of the first semiconductor area is formed in a mesh shape; a first electrode provided on the active area; and a second electrode provided on the rear surface of the semiconductor substrate.09-13-2012
20120261672MINIMIZING LEAKAGE CURRENT AND JUNCTION CAPACITANCE IN CMOS TRANSISTORS BY UTILIZING DIELECTRIC SPACERS - A semiconductor structure and method for forming dielectric spacers and epitaxial layers for a complementary metal-oxide-semiconductor field effect transistor (CMOS transistor) are disclosed. Specifically, the structure and method involves forming dielectric spacers that are disposed in trenches and are adjacent to the silicon substrate, which minimizes leakage current. Furthermore, epitaxial layers are deposited to form source and drain regions, wherein the source region and drain regions are spaced at a distance from each other. The epitaxial layers are disposed adjacent to the dielectric spacers and the transistor body regions (i.e., portion of substrate below the gates), which can minimize transistor junction capacitance. Minimizing transistor junction capacitance can enhance the switching speed of the CMOS transistor. Accordingly, the application of dielectric spacers and epitaxial layers to minimize leakage current and transistor junction capacitance in CMOS transistors can enhance the utility and performance of the CMOS transistors in low power applications.10-18-2012
20120261675VERTICAL JUNCTION FIELD EFFECT TRANSISTORS WITH IMPROVED THERMAL CHARACTERISTICS AND METHODS OF MAKING - Vertical junction field effect transistors (VJFETs) having improved heat dissipation at high current flow while maintaining the desirable specific on-resistance and normalized saturated drain current properties characteristic of devices having small pitch lengths are described. The VJFETs comprise one or more electrically active source regions in electrical contact with the source metal of the device and one or more electrically inactive source regions not in electrical contact with the source metal of the device. The electrically inactive source regions dissipate heat generated by the electrically active source regions during current flow.10-18-2012
20120261673SiC Semiconductor Power Device - A semiconductor power device includes a SiC semiconductor body. At least part of the SiC semiconductor body constitutes a drift zone. A first contact is at a first side of the SiC semiconductor body. A second contact is at a second side of the SiC semiconductor body. The first side is opposite the second side. A current path between the first contact and the second contact includes at least one graphene layer.10-18-2012
20120261674SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - The present invention provides a semiconductor device, which is formed on a semiconductor substrate, comprising a gate stack, a channel region, and source/drain regions, wherein the gate stack is on the channel region, the channel region is in the semiconductor substrate, the source/drain regions are embedded in the semiconductor substrate, and each of the source/drain regions comprises a sidewall and a bottom, a second semiconductor layer being sandwiched between the channel region and a portion of the sidewall distant from the bottom, a first semiconductor layer being sandwiched between the semiconductor substrate and at least a portion of the bottom distant from the sidewall, and an insulating layer being sandwiched between the semiconductor substrate and the other portions of the bottom and/or the other portions of the sidewall. The present invention also provides a method for forming the semiconductor device. The present invention helps preventing the dopants in the source/drain regions from diffusing into the substrate.10-18-2012
20120261676SiC FIELD EFFECT TRANSISTOR - A SiC field effect transistor includes: a SiC semiconductor layer; and a MIS transistor structure including a first conductivity type source region in the semiconductor layer, a second conductivity type body region in the semiconductor layer in contact with the source region, a first conductivity type drift region in the semiconductor layer in contact with the body region, a gate electrode opposed to the body region with a gate insulation film interposed between the electrode and the body region for forming a channel in the body region to cause electric current to flow between the drift region and the source region, and a barrier forming layer in contact with the drift region to form a junction barrier by the contact with the drift region, the junction barrier being lower than a diffusion potential of a body diode defined by a junction between the body region and the drift region.10-18-2012
20120228628SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device and methods of fabricating semiconductor devices are provided. A method involves forming a semiconductor substrate on a source region and a drain region, the semiconductor substrate comprises a first crystal. The method also involves forming an epitaxial layer of a second crystal on the semiconductor substrate. The first crystal has a first lattice constant and the second crystal has a second lattice constant. The first epitaxial layer does not touch a spacer or a gate electrode. Forming the epitaxial layer can comprise forming a first epitaxial layer and a second epitaxial layer, wherein the first epitaxial layer has a conductivity type impurity that is less than the conductivity type impurity of the second epitaxial layer.09-13-2012
20120228629Thyristors, Methods of Programming Thyristors, and Methods of Forming Thyristors - Some embodiments include thyristors having first and second electrode regions, first and second base regions, and material having a bandgap of at least 1.2 eV in at least one of the regions. The first base region is between the first electrode region and the second base region, and the second base region is between the second electrode region and the first base region. The first base region interfaces with the first electrode region at a first junction, and interfaces with the second base region at a second junction. The second base region interfaces with the second electrode region at a third junction. A gate is along the first base region, and in some embodiments does not overlap either of the first and second junctions. Some embodiments include methods of programming thyristors, and some embodiments include methods of forming thyristors.09-13-2012
20120228640SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - There are provided a high-quality semiconductor device having stable characteristics and a method for manufacturing such a semiconductor device. The semiconductor device includes: a substrate having a main surface; and a silicon carbide layer formed on the main surface of the substrate and including a side surface inclined relative to the main surface. The side surface substantially includes a {03-3-8} plane. The side surface includes a channel region.09-13-2012
20120228630SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device according to an embodiment includes a first electrode and a first silicon carbide (SiC) semiconductor part. The first electrode uses a conductive material and the first silicon carbide (SiC) semiconductor part is connected to the first electrode, in which at least one element of magnesium (Mg), calcium (Ca), strontium (Sr), and barium (Ba) is contained in an interface portion with the first electrode in such a way that a surface density thereof peaks, and whose conduction type is a p-type.09-13-2012
20110121318Silicon Carbide Switching Devices Including P-Type Channels - Methods of forming a p-channel MOS device in silicon carbide include forming an n-type well in a silicon carbide layer, and implanting p-type dopant ions to form a p-type region in the n-type well at a surface of the silicon carbide layer and at least partially defining a channel region in the n-type well adjacent the p-type region. A threshold adjustment region is formed in the channel region. The implanted ions are annealed in an inert atmosphere at a temperature greater than 1650° C. A gate oxide layer is formed on the channel region, and a gate is formed on the gate oxide layer. A silicon carbide-based transistor includes a silicon carbide layer, an n-type well in the silicon carbide layer, and a p-type region in the n-type well at a surface of the silicon carbide layer and at least partially defining a channel region in the n-type well adjacent the p-type region. A threshold adjustment region is in the channel region and includes p-type dopants at a dopant concentration of about 1×1005-26-2011
20110121317ANNEALING METHOD FOR SEMICONDUCTOR DEVICE WITH SILICON CARBIDE SUBSTRATE AND SEMICONDUCTOR DEVICE - In an atmosphere in which a silicon carbide (SiC) substrate implanted with impurities is annealed to activate the impurities, by setting a partial pressure of H05-26-2011
20110121316SILICON CARBIDE SEMICONDUCTOR DEVICE - The area of each body region is minimized, and the gate oxide films at the bottoms of the trenches are more effectively protected by depletion layers extending from the body regions.05-26-2011
20110121315SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A recess along a sidewall is formed in a pMOS region and an nMOS region. An SiC layer of which thickness is thicker than a depth of the recess is formed in the recess. A sidewall covering a part of the SiC layer is formed at both lateral sides of a gate electrode in the pMOS region. A recess is formed by selectively removing the SiC layer in the pMOS region. A side surface of the recess at the gate insulating film side is inclined so that the upper region of the side surface, the closer to the gate insulating film in a lateral direction at a region lower than the surface of the silicon substrate. An SiGe layer is formed in the recess in the pMOS region.05-26-2011
20080296587Silicon carbide semiconductor device having junction barrier schottky diode - A silicon carbide semiconductor device includes a substrate; a drift layer having a first conductivity type; an insulating layer; a Schottky electrode; an ohmic electrode; a resurf layer; and second conductivity type layers. The drift layer and the second conductivity type layers provide multiple PN diodes. Each second conductivity type layer has a radial width with respect to a center of a contact region between the Schottky electrode and the drift layer. A radial width of one of the second conductivity type layers is smaller than that of another one of the second conductivity type layers, which is disposed closer to the center of the contact region than the one of the second conductivity type layers.12-04-2008
20080296586COMPOSITE WAFERS HAVING BULK-QUALITY SEMICONDUCTOR LAYERS AND METHOD OF MANUFACTURING THEREOF - Method for producing composite wafers with thin high-quality semiconductor films atomically attached to synthetic diamond wafers is disclosed. Synthetic diamond substrates are created by depositing synthetic diamond onto a nucleating layer deposited on bulk semiconductor wafer which has been prepared to allow separation of the thin semiconductor film from the remaining bulk semiconductor wafer. The remaining semiconductor wafer is available for reuse. The synthetic diamond substrate serves as heat spreader and a mechanical substrate.12-04-2008
20120261677METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE AND THE SILICON CARBIDE SEMICONDUCTOR DEVICE - Silicon carbide semiconductor device includes trench, in which connecting trench section is connected to straight trench section. Straight trench section includes first straight trench and second straight trench extending in parallel to each other. Connecting trench section includes first connecting trench perpendicular to straight trench section, second connecting trench that connects first straight trench and first connecting trench to each other, and third connecting trench that connects second straight trench and first connecting trench to each other. Second connecting trench extends at 30 degrees of angle with the extension of first straight trench. Third connecting trench extends at 30 degrees of angle with the extension of second straight trench. A manufacturing method according to the invention for manufacturing a silicon carbide semiconductor device facilitates preventing defects from being causes in a silicon carbide semiconductor device during the manufacture thereof.10-18-2012
20110037076DIAMOND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The present invention is contemplated for providing a diamond semiconductor device where an impurity-doped diamond semiconductor is buried in a selected area, and a method of manufacturing the same.02-17-2011
20120299014SEMICONDUCTOR LIGHT EMITTING DEVICE, NITRIDE SEMICONDUCTOR LAYER GROWTH SUBSTRATE, AND NITRIDE SEMICONDUCTOR WAFER - According to one embodiment, a semiconductor light emitting device includes a first semiconductor layer of a first conductivity type and having a major surface, a second semiconductor layer of a second conductivity type, and a light emitting layer provided between the first and second semiconductor layers. The major surface is opposite to the light emitting layer. The first semiconductor layer has structural bodies provided in the major surface. The structural bodies are recess or protrusion. A centroid of a first structural body aligns with a centroid of a second structural body nearest the first structural. hb, rb, and Rb satisfy rb/(2·hb)≦0.7, and rb/Rb<1, where hb is a depth of the recess, rb is a width of a bottom portion of the recess, and Rb is a width of the protrusion.11-29-2012
20120319132SPLIT-GATE STRUCTURE IN TRENCH-BASED SILICON CARBIDE POWER DEVICE - An integrated structure includes a plurality of split-gate trench MOSFETs. A plurality of trenches is formed within the silicon carbide substrate composition, each trench is lined with a passivation layer, each trench being substantially filled with a first conductive region a second conductive region and an insulating material having a dielectric constant similar to a dielectric constant of the silicon carbide substrate composition. The first conductive region is separated from the passivation layer by the insulating material. The first and second conductive regions form gate regions for each trench MOSFET. The first conductive region is separated from the second conductive region by the passivation layer. A doped body region of a first conductivity type formed at an upper portion of the substrate composition and a doped source region of a second conductivity type formed inside the doped body region.12-20-2012
20120319133OPTICALLY ASSIST-TRIGGERED WIDE BANDGAP THYRISTORS HAVING POSITIVE TEMPERATURE COEFFICIENTS - A thyristor includes a first conductivity type semiconductor layer, a first conductivity type carrier injection layer on the semiconductor layer, a second conductivity type drift layer on the carrier injection layer, a first conductivity type base layer on the drift layer, and a second conductivity type anode region on the base layer. The thickness and doping concentration of the carrier injection layer are selected to reduce minority carrier injection by the carrier injection layer in response to an increase in operating temperature of the thyristor. A cross-over current density at which the thyristor shifts from a negative temperature coefficient of forward voltage to a positive temperature coefficient of forward voltage is thereby reduced.12-20-2012
20120319134SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A gate electrode includes a polysilicon film in contact with a gate insulating film, a barrier film provided on the polysilicon film, a metal film provided on the barrier film and made of refractory metal. An interlayer insulating film is arranged so as to cover the gate insulating film and the gate electrode provided on the gate insulating film. The interlayer insulating film has a substrate contact hole partially exposing a silicon carbide substrate in a region in contact with the gate insulating film. A interconnection is electrically connected to the silicon carbide substrate through the substrate contact hole and is electrically insulated from the gate electrode by the interlayer insulating film.12-20-2012
20120319136SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A SiC device includes an inversion type MOSFET having: a substrate, a drift layer, and a base region stacked in this order; source and contact regions in upper portions of the base region; a trench penetrating the source and base regions; a gate electrode on a gate insulating film in the trench; a source electrode coupled with the source and base region; a drain electrode on a back of the substrate; and multiple deep layers in an upper portion of the drift layer deeper than the trench. Each deep layer has an impurity concentration distribution in a depth direction, and an inversion layer is provided in a portion of the deep layer on the side of the trench under application of the gate voltage.12-20-2012
20120319137Electrostatic Discharge Protection Element and Electrostatic Discharge Protection Chip and Method of Producing the Same - An electrostatic discharge (ESD) protection element includes a collector area, a first barrier area, a semiconductor area, a second barrier area and an emitter area. The collector area has a first conductivity type. The first barrier area borders on the collector area and has a second conductivity type. The semiconductor area borders on the first barrier area and is an intrinsic semiconductor area, or has the first or second conductivity type and a dopant concentration which is lower than a dopant concentration of the first barrier area. The second barrier area borders on the semiconductor area and has the second conductivity type and a higher dopant concentration than the semiconductor area. The emitter area borders on the second barrier area and has the first conductivity type.12-20-2012
20120319135SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - An electrode layer lies on a silicon carbide substrate in contact therewith and has Ni atoms and Si atoms. The number of Ni atoms is not less than 67% of the total number of Ni atoms and Si atoms. A side of the electrode layer at least in contact with the silicon carbide substrate contains a compound of Si and Ni. On a surface side of the electrode layer, C atom concentration is lower than Ni atom concentration. Thus, improvement in electrical conductivity of the electrode layer and suppression of precipitation of C atoms at the surface of the electrode layer can both be achieved.12-20-2012
20110220917SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SAME - A semiconductor device of the present invention has a semiconductor element region 09-15-2011
20110227096SEMICONDUCTOR DEVICE - A semiconductor device having a construction capable of achieving suppressed deterioration of electric characteristics in an insulating member is provided. An n09-22-2011
20110227094STRAINED SILICON CARBIDE CHANNEL FOR ELECTRON MOBILITY OF NMOS - A semiconductor is formed on a (110) silicon (Si) substrate, with improved electron mobility. Embodiments include semiconductor devices having a silicon carbide (SiC) portion in the nFET channel region. An embodiment includes forming an nFET channel region and a pFET channel region in a Si substrate, such as a (110) Si substrate, and forming a silicon carbide (SiC) portion on the nFET channel region. The SiC portion may be formed by ion implantation of C followed by a recrystallization anneal or by epitaxial growth of SiC in a recess formed in the substrate. The use of SiC in the nFET channel region improves electron mobility without introducing topographical differences between NMOS and PMOS transistors.09-22-2011
20120273802JUNCTION BARRIER SCHOTTKY DIODES WITH CURRENT SURGE CAPABILITY - An electronic device includes a silicon carbide drift region having a first conductivity type, a Schottky contact on the drift region, and a plurality of junction barrier Schottky (JBS) regions at a surface of the drift region adjacent the Schottky contact. The JBS regions have a second conductivity type opposite the first conductivity type and have a first spacing between adjacent ones of the JBS regions. The device further includes a plurality of surge protection subregions having the second conductivity type. Each of the surge protection subregions has a second spacing between adjacent ones of the surge protection subregions that is less than the first spacing.11-01-2012
20120273799SEMICONDUCTOR DEVICE AND FABRICATION METHOD FOR THE SAME - According to an embodiment, a semiconductor device includes: a conductive base plate; a semiconductor chip bonded on the conductive base plate, a first adhesive agent disposed on a central part of a bonded surface between the semiconductor chip and the conductive base plate; and a second adhesive agent disposed on a peripheral part of the central part of the bonded surface between the semiconductor chip and the conductive base plate. A coefficient of thermal conductivity of the first adhesive agent is relatively higher than that of the second adhesive agent, and a bonding strength of the second adhesive agent is relatively higher than that of the first adhesive agent.11-01-2012
20120273798METHOD OF FORMING SILICIDE CONTACTS OF DIFFERENT SHAPES SELECTIVELY ON REGIONS OF A SEMICONDUCTOR DEVICE - A structure and method for fabricating silicide contacts for semiconductor devices is provided. Specifically, the structure and method involves utilizing chemical vapor deposition (CVD) and annealing to form silicide contacts of different shapes, selectively on regions of a semiconductor field effect transistor (FET), such as on source and drain regions. The shape of silicide contacts is a critical factor that can be manipulated to reduce contact resistance. Thus, the structure and method provide silicide contacts of different shapes with low contact resistance, wherein the silicide contacts also mitigate leakage current to enhance the utility and performance of FETs in low power applications.11-01-2012
20120080690Method for Manufacturing a Composite Wafer Having a Graphite Core, and Composite Wafer Having a Graphite Core - According to an embodiment, a composite wafer includes a carrier substrate having a graphite core and a monocrystalline semiconductor layer attached to the carrier substrate.04-05-2012
20110241022SUBSTRATE AND METHOD OF MANUFACTURING SUBSTRATE - A substrate, the presence of which can be detected with a method similar to a conventional method of detecting a Si substrate even if the substrate is transparent, and a method of manufacturing the substrate are provided. Light incident on an end portion of a transparent substrate is not transmitted through the substrate as with the light incident on a central portion of the substrate, but is totally reflected from a total reflection surface in a detection region present in at least a portion of the end portion of the substrate. A photoelectric sensor can recognize that a ratio of transmission of the light at the end portion of the substrate has become smaller, thereby detecting the presence of the substrate.10-06-2011
20120326168TRANSISTOR WITH BURIED SILICON GERMANIUM FOR IMPROVED PROXIMITY CONTROL AND OPTIMIZED RECESS SHAPE - A method of forming a semiconductor device that includes providing a substrate including a semiconductor layer on a germanium-containing silicon layer and forming a gate structure on a surface of a channel portion of the semiconductor layer. Well trenches are etched into the semiconductor layer on opposing sides of the gate structure. The etch process for forming the well trenches forms an undercut region extending under the gate structure and is selective to the germanium-containing silicon layer. Stress inducing semiconductor material is epitaxially grown to fill at least a portion of the well trench to provide at least one of a stress inducing source region and a stress inducing drain region having a planar base.12-27-2012
20120326164BETAVOLTAIC APPARATUS AND METHOD - An exemplary thinned-down betavoltaic device includes an N+ doped silicon carbide (SiC) substrate having a thickness between about 3 to 50 microns, an electrically conductive layer disposed immediately adjacent the bottom surface of the SiC substrate; an N− doped SiC epitaxial layer disposed immediately adjacent the top surface of the SiC substrate, a P+ doped SiC epitaxial layer disposed immediately adjacent the top surface of the N− doped SiC epitaxial layer, an ohmic conductive layer disposed immediately adjacent the top surface of the P+ doped SiC epitaxial layer, and a radioisotope layer disposed immediately adjacent the top surface of the ohmic conductive layer. The radioisotope layer can be 12-27-2012
20120280250SPACER AS HARD MASK SCHEME FOR IN-SITU DOPING IN CMOS FINFETS - A method of fabricating a semiconductor device that includes at least two fin structures, wherein one of the at least two fin structures include epitaxially formed in-situ doped second source and drain regions having a facetted exterior sidewall that are present on the sidewalls of the fin structure. In another embodiment, the disclosure also provides a method of fabricating a finFET that includes forming a recess in a sidewall of a fin structure, and epitaxially forming an extension dopant region in the recess that is formed in the fin structure. Structures formed by the aforementioned methods are also described.11-08-2012
20120280254SIC EPITAXIAL WAFER AND METHOD FOR MANUFACTURING SAME - According to the present invention, there is provided an SiC epitaxial wafer which reduces triangular defects and stacking faults, which is highly uniform in carrier concentration and film thickness, and which is free of step bunching, and its method of manufacture. The SiC epitaxial wafer of the present invention is an SiC epitaxial wafer in which an SiC epitaxial layer is formed on a 4H—SiC single crystal substrate that is tilted at an off angle of 0.4°-5°, wherein the density of triangular-shaped defects of said SiC epitaxial layer is 1 defect/cm11-08-2012
20120280255SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - An MOSFET includes a silicon carbide substrate, an active layer, a gate oxide film, and a gate electrode. The active layer includes a body region where an inversion layer is formed at a region in contact with the gate oxide film by application of voltage to the gate electrode. The body region includes a low concentration region arranged at a region where an inversion layer is formed, and containing impurities of low concentration, and a high concentration region adjacent to the low concentration region in the carrier mobile direction in the inversion layer, arranged in a region where the inversion layer is formed, and containing impurities higher in concentration than in the low concentration region.11-08-2012
20120280253Stress Regulated Semiconductor Devices and Associated Methods - Stress regulated semiconductor devices and associated methods are provided. In one aspect, for example, a stress regulated semiconductor device can include a semiconductor layer, a stress regulating interface layer including a carbon layer formed on the semiconductor layer, and a heat spreader coupled to the carbon layer opposite the semiconductor layer. The stress regulating interface layer is operable to reduce the coefficient of thermal expansion difference between the semiconductor layer and the heat spreader to less than or equal to about 10 ppm/° C.11-08-2012
20120280252Field Effect Transistor Devices with Low Source Resistance - A semiconductor device includes a drift layer having a first conductivity type, a well region in the drift layer having a second conductivity type opposite the first conductivity type, and a source region in the well region, The source region has the first conductivity type and defines a channel region in the well region. The source region includes a lateral source region adjacent the channel region and a plurality of source contact regions extending away from the lateral source region opposite the channel region. A body contact region having the second conductivity type is between at least two of the plurality of source contact regions and is in contact with the well region. A source ohmic contact overlaps at least one of the source contact regions and the body contact region. A minimum dimension of a source contact area of the semiconductor device is defined by an area of overlap between the source ohmic contact and the at least one source contact region.11-08-2012
20110297963SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF - A silicon carbide semiconductor device is provided that includes a semiconductor layer made of silicon carbide and having a surface with a trench having a sidewall formed of a crystal plane tilted at an angle in a range of not less than 50° and not more than 65° relative to the {0001} plane, and an insulating film formed to contact the sidewall of the trench. A maximum value of the nitrogen concentration in a region within 10 nm from the interface between the sidewall of the trench and the insulating film is not less than 1×1012-08-2011
20120091470Programmable Gate III-Nitride Power Transistor - A III-nitride semiconductor device which includes a charged floating gate electrode.04-19-2012
20120326166SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A substrate has a surface made of a semiconductor having a hexagonal single-crystal structure of polytype 4H. The surface of the substrate is constructed by alternately providing a first plane having a plane orientation of (0-33-8), and a second plane connected to the first plane and having a plane orientation different from the plane orientation of the first plane. A gate insulating film is provided on the surface of the substrate. A gate electrode is provided on the gate insulating film.12-27-2012
20120326162PROCESS FOR FORMING REPAIR LAYER AND MOS TRANSISTOR HAVING REPAIR LAYER - A repair layer forming process includes the following steps. Firstly, a substrate is provided, and a gate structure is formed on the substrate, wherein the gate structure at least includes a gate dielectric layer and a gate conductor layer. Then, a nitridation process is performed to form a nitrogen-containing superficial layer on a sidewall of the gate structure. Then, a thermal oxidation process is performed to convert the nitrogen-containing superficial layer into a repair layer. Moreover, a metal-oxide-semiconductor transistor includes a substrate, a gate dielectric layer, a gate conductor layer and a repair layer. The gate dielectric layer is formed on the substrate. The gate conductor layer is formed on the gate dielectric layer. The repair layer is at least partially formed on a sidewall of the gate conductor layer.12-27-2012
20120091469Semiconductor Devices Having Shallow Junctions - Semiconductor devices are provided including a substrate having a first surface and a second surface recessed from opposite sides of the first surface, a gate pattern formed on the first surface and having a gate insulating layer and a gate electrode, a carbon-doped silicon buffer layer formed on the second surface, and source and drain regions doped with an n-type dopant or p-type dopant, epitaxially grown on the silicon buffer layer to be elevated from a top surface of the gate insulating layer.04-19-2012
20120326167SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A silicon carbide substrate has a substrate surface. A gate insulating film is provided to cover a part of the substrate surface. A gate electrode covers a part of the gate insulating film. A contact electrode is provided on the substrate surfaces, adjacent to and in contact with the gate insulating film, and it contains an alloy having Al atoms. Al atoms do not diffuse from the contact electrode into a portion of the gate insulating film lying between the substrate surface and the gate electrode. Thus, in a case where a contact electrode having Al atoms is employed, reliability of the gate insulating film of a semiconductor device can be improved12-27-2012
20120091468SEMICONDUCTOR DEVICE WITH INTERPOSER AND METHOD MANUFACTURING SAME - A semiconductor device includes an interposer mounting a semiconductor chip. The interposer includes a silicon substrate having a recessed region formed on a first surface, a first through via penetrating a first region of the silicon substrate from the first surface to an opposing second surface, an insulator disposed in the recessed region, and a first wire pattern at least partially disposed on the insulator and electrically connecting the first through via to the semiconductor chip04-19-2012
20120091472SILICON CARBIDE SUBSTRATE - A first circular surface is provided with a first notch portion having a first shape. A second circular surface is opposite to the first circular surface and is provided with a second notch portion having a second shape. A side surface connects the first circular surface and the second circular surface to each other. The first notch portion and the second notch portion are opposite to each other. The side surface has a first depression connecting the first notch portion and the second notch portion to each other.04-19-2012
20120091471LIGHTLY DOPED SILICON CARBIDE WAFER AND USE THEREOF IN HIGH POWER DEVICES - A semiconductor device including a drift zone of a first conductivity type serving as a substrate layer having a front side and a back side. A first contact electrode is arranged at the front side of the drift zone. A control region is arranged at the front side and controls an injection of carriers of at least the first conductivity type into the drift zone. A second contact electrode is arranged at the backside of the drift zone. The drift zone is arranged to carry a carrier flow between the first and the second contact electrode. The drift zone includes a silicon carbide wafer with a net carrier concentration less than 1004-19-2012
20120326165HEMT INCLUDING AIN BUFFER LAYER WITH LARGE UNEVENNESS - A HEMT comprised of nitride semiconductor materials is disclosed. The HEMT includes, on a SiC substrate, a AlN buffer layer, a GaN channel layer, and a AlGaN doped layer. A feature of the HEMT is that the AlN buffer layer is grown on an extraordinary condition of the pressure, and has a large unevenness in a thickness thereof to enhance the release of carriers captured in traps in the substrate back to the channel layer.12-27-2012
20120326163SEMICONDUCTOR DEVICE WITH INCREASED CHANNEL MOBILITY AND DRY CHEMISTRY PROCESSES FOR FABRICATION THEREOF - Embodiments of a semiconductor device having increased channel mobility and methods of manufacturing thereof are disclosed. In one embodiment, the semiconductor device includes a substrate including a channel region and a gate stack on the substrate over the channel region. The gate stack includes an alkaline earth metal. In one embodiment, the alkaline earth metal is Barium (Ba). In another embodiment, the alkaline earth metal is Strontium (Sr). The alkaline earth metal results in a substantial improvement of the channel mobility of the semiconductor device.12-27-2012
20120286292POWER SEMICONDUCTOR MODULE - A power semiconductor module in which temperature rise of switching elements made of a Si semiconductor can be suppressed low and efficiency of cooling the module can be enhanced. To that end, the power semiconductor module includes switching elements made of the Si semiconductor and diodes made of a wide-bandgap semiconductor, the diodes are arranged in the middle region of the power semiconductor module, and the switching elements are arranged in both sides or in the periphery of the middle region of the power semiconductor module.11-15-2012
20120286293ELECTRONIC DEVICE AND MANUFACTURING THEREOF - An electronic device and manufacturing thereof. One embodiment provides a carrier and multiple contact elements. The carrier defines a first plane. A power semiconductor chip is attached to the carrier. A body is formed of an electrically insulating material covering the power semiconductor chip. The body defines a second plane parallel to the first plane and side faces extends from the first plane to the second plane. At least one of the multiple contact elements has a cross section in a direction orthogonal to the first plane that is longer than 60% of the distance between the first plane and the second plane.11-15-2012
20120286288SEMICONDUCTOR DEVICE AND SEMICONDUCTOR ELEMENT - A semiconductor device includes a semiconductor element including a first element portion having a first gate and a second element portion having a second gate, wherein the turning on and off of the first and second element portions are controlled by a signal from the first and second gates respectively. The semiconductor device further includes signal transmission means connected to the first gate and the second gate and transmitting a signal to the first gate and the second gate so that when the semiconductor element is to be turned on, the first element portion and the second element portion are simultaneously turned on, and so that when the semiconductor element is to be turned off, the second element portion is turned off a delay time after the first element portion is turned off.11-15-2012
20120286291SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A silicon carbide semiconductor device having excellent electrical characteristics including channel mobility and a method for manufacturing the same are provided. The method for manufacturing a silicon carbide semiconductor device includes: an epitaxial layer forming step of preparing a semiconductor film of silicon carbide; a gate insulating film forming step of forming an oxide film on a surface of the semiconductor film; a nitrogen annealing step of performing heat treatment on the semiconductor film on which the oxide film is formed, in a nitrogen-containing atmosphere; and a post heat treatment step of performing, after the nitrogen annealing step, post heat treatment on the semiconductor film on which the oxide film is formed, in an atmosphere containing an inert gas. The heat treatment temperature in the post heat treatment step is higher than that in the nitrogen annealing step and lower than a melting point of the oxide film.11-15-2012
20120286289SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - The invention concerns a semiconductor device comprising a structure, wherein the structure comprising a substrate, a first layer onto the substrate comprising GaN and a second layer comprising AlGaN. The second layer is deposited onto the first layer and the first and the second layer cover at least partially the substrate, and wherein the structure comprises a third layer comprising diamond11-15-2012
20120138958SILICON CARBIDE SEMICONDUCTOR DEVICE - A silicon carbide semiconductor device is provided which has a lower on-resistance and a higher breakdown voltage than those of a conventional silicon carbide semiconductor device. A JFET includes an n type substrate, a p type layer, an n type layer, a source region, a drain region, and a gate region. The n type substrate has a main surface having an off angle of not less than 32° relative to the {0001} plane, and is made of silicon carbide (SiC). The p type layer is formed on the main surface of the n type substrate, and has p type conductivity. The n type layer is formed on the p type layer, and has n type conductivity. The source region and the drain region are formed in n type layer with a space interposed therebetween. The gate region is formed in the n type layer at a region between the source region and the drain region.06-07-2012
20120138957LIGHT EMITTING DEVICE - Embodiments disclose a light emitting device including a substrate, a buffer layer disposed on an R-plane of the substrate, the buffer layer having a rock salt structured nitride, and a light emitting structure arranged on the buffer layer, the light emitting structure being grown in an a-plane.06-07-2012
20120138953STRUCTURE AND METHOD FOR Vt TUNING AND SHORT CHANNEL CONTROL WITH HIGH K/METAL GATE MOSFETs - A semiconductor device is provided that includes a semiconductor substrate having a well region located within an upper region thereof. A semiconductor material stack is located on the well region. The semiconductor material stack includes, from bottom to top, a semiconductor-containing buffer layer and a non-doped semiconductor-containing channel layer; the semiconductor-containing buffer layer of the semiconductor material stack is located directly on an upper surface of the well region. The structure also includes a gate material stack located directly on an upper surface of the non-doped semiconductor-containing channel layer. The gate material stack employed in the present disclosure includes, from bottom to top, a high k gate dielectric layer, a work function metal layer and a polysilicon layer.06-07-2012
20130009168SEMICONDUCTOR MODULE - A semiconductor module is disclosed that includes a semiconductor element, a capacitor configured to be electrically connected to the semiconductor element and a heat sink, wherein the semiconductor and the capacitor are stacked with each other via the heat sink, and wherein the semiconductor element is disposed in a position overlapping with the capacitor as viewed from a stack direction.01-10-2013
20130009169METHODS OF MAKING VERTICAL JUNCTION FIELD EFFECT TRANSISTORS AND BIPOLAR JUNCTION TRANSISTORS WITHOUT ION IMPLANTATION AND DEVICES MADE THEREWITH - Methods of making semiconductor devices such as vertical junction field effect transistors (VJFETs) or bipolar junction transistors (BJTs) are described. The methods do not require ion implantation. The VJFET device has an epitaxially regrown n-type channel layer and an epitaxially regrown p-type gate layer as well as an epitaxially grown buried gate layer. Devices made by the methods are also described.01-10-2013
20130009167LIGHT EMITTING DIODE WITH PATTERNED STRUCTURES AND METHOD OF MAKING THE SAME - A light emitting diode is provided which includes an active region in combination with a current spreading layer; and a crystalline epitaxial film light extraction layer in contact with the current spreading layer, the light extraction layer being patterned with nano/micro structures which increase extraction of light emitted from the active region.01-10-2013
20130009170EPITAXIAL SiC SINGLE CRYSTAL SUBSTRATE AND METHOD OF MANUFACTURE OF EPITAXIAL SiC SINGLE CRYSTAL SUBSTRATE - An epitaxial SiC single crystal substrate including a SiC single crystal wafer whose main surface is a c-plane or a surface that inclines a c-plane with an angle of inclination that is more than 0 degree but less than 10 degrees, and SiC epitaxial film that is formed on the main surface of the SiC single crystal wafer, wherein the dislocation array density of threading edge dislocation arrays that are formed in the SiC epitaxial film is 10 arrays/cm01-10-2013
20130009171SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device has a semiconductor layer and a substrate. The semiconductor layer constitutes at least a part of a current path, and is made of silicon carbide. The substrate has a first surface supporting the semiconductor layer, and a second surface opposite to the first surface. Further, the substrate is made of silicon carbide having a 4H type single-crystal structure. Further, the substrate has a physical property in which a ratio of a peak strength in a wavelength of around 500 nm to a peak strength in a wavelength of around 390 nm is 0.1 or smaller in photoluminescence measurement. In this way, the semiconductor device is obtained to have a low on-resistance.01-10-2013
20100133550STABLE POWER DEVICES ON LOW-ANGLE OFF-CUT SILICON CARBIDE CRYSTALS - A silicon carbide-based power device includes a silicon carbide drift layer having a planar surface that forms an off-axis angle with a <06-03-2010
20130015468SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAMEAANM KIKUCHI; MasaoAACI TokyoAACO JPAAGP KIKUCHI; Masao Tokyo JP - A semiconductor device of the present invention comprises a semiconductor element, a first metal body formed on a back surface of the semiconductor element, a first insulating layer formed on a back surface of the first metal body, a second metal body formed on a back surface of the first insulating layer, a third metal body formed on a front surface of the semiconductor element, a second insulating layer formed on a front surface of the third metal body and a fourth metal body formed on a front surface of the second insulating layer, and the second metal body is thinner than the first metal body and the fourth metal body is thicker than the third metal body. With this structure, it is possible to increase the heat radiation performance while suppressing stress to be exerted on the semiconductor element.01-17-2013
20130015467System and Method for Wafer Level PackagingAANM Krumbein; UlrichAACI RosenheimAACO DEAAGP Krumbein; Ulrich Rosenheim DEAANM Lohninger; GerhardAACI MuenchenAACO DEAAGP Lohninger; Gerhard Muenchen DEAANM Dehe; AlfonsAACI ReutlingenAACO DEAAGP Dehe; Alfons Reutlingen DE - In an embodiment, a semiconductor device includes a semiconductor substrate. The semiconductor substrate has a first cavity disposed through it, and conductive material covers at least the bottom portion of the first cavity. An integrated circuit is disposed on the top surface of the conductive material. The device further includes a cap disposed on the top surface of the substrate, such that a cavity disposed on a surface of the cap overlies the first cavity in the substrate.01-17-2013
20130015469METHOD FOR MANUFACTURING DIODE, AND DIODE - A semiconductor substrate having a first side and a second side made of single crystal silicon carbide is prepared. A mask layer having a plurality of openings and made of silicon oxide is formed on the second side. The plurality of openings expose a plurality of regions included in the second side, respectively. A plurality of diamond portions are formed by epitaxial growth on the plurality of regions, respectively. The epitaxial growth is stopped before the plurality of diamond portions come into contact with each other. A Schottky electrode is formed on each of the plurality of diamond portions. An ohmic electrode is formed on the first side.01-17-2013
20130020587POWER SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device includes a semiconductor substrate of a first conductivity type, a drift layer of the first conductivity type which is formed on a first main surface of the semiconductor substrate, a second well region of a second conductivity type which is formed to surround a cell region of the drift layer, and a source pad for electrically connecting the second well regions and a source region of the cell region through a first well contact hole provided to penetrate a gate insulating film on the second well region, a second well contact hole provided to penetrate a field insulating film on the second well region and a source contact hole.01-24-2013
20130020586SEMICONDUCTOR DEVICE - A semiconductor device having a low feedback capacitance and a low switching loss. The semiconductor device includes: a substrate; a drift layer formed on a surface of the semiconductor substrate; a plurality of first well regions formed on a surface of the drift layer; a source region which is an area formed on a surface of each of the first well regions and defining, as a channel region, the surface of each of the first well regions interposed between the area and the drift layer; a gate electrode formed over the channel region and the drift layer thereacross through a gate insulating film; and second well regions buried inside the drift layer below the gate electrode and formed to be individually connected to each of the first well regions adjacent to one another.01-24-2013
20120241767SIC SEMICONDUCTOR ELEMENT AND MANUFACTURING METHOD FOR SAME - Disclosed are an SiC semiconductor element and manufacturing method for an SiC semiconductor element in which the interface state density of the interface of the insulating film and the SiC is reduced, and channel mobility is improved. Phosphorus (09-27-2012
20120241765SEMICONDUCTOR DEVICES HAVING TENSILE AND/OR COMPRESSIVE STRAIN AND METHODS OF MANUFACTURING AND DESIGN STRUCTURE - A semiconductor device having a tensile and/or compressive strain applied thereto and methods of manufacturing the semiconductor devices and design structure to enhance channel strain. The gate structures for an NFET and a PFET have identically formed sidewalls, and stress materials are provided in recesses in source and drain regions of the NFET and the PFET.09-27-2012
20120241763ELECTRONIC FIELD EFFECT DEVICES AND METHODS FOR THEIR MANUFACTURE - Electronic field effect devices, and methods of manufacture of these electronic field effect devices are disclosed. In particular, there is disclosed an electronic field effect device which has improved electrical properties due to the formation of a highly mobile two-dimensional charge-carrier gas in a simple structure formed from diamond in combination with polar materials.09-27-2012
20120241761SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to an embodiment, a semiconductor device includes a first semiconductor layer of a first conductive type, a first main electrode provided on a first major surface side of the first semiconductor layer, and a second main electrode provided on a second major surface side of the first semiconductor layer. A pair of first control electrodes is provided within a trench provided from the first major surface side to the second major surface in the first semiconductor layer; and the first control electrodes are provided separately from each other in a direction parallel to the first major surface. Each of the first control electrodes faces an inner face of the trench via a first insulating film. A second control electrode is provided between the first control electrodes and a bottom face of the trench, and faces the inner face of the trench via a second insulating film.09-27-2012
20080237610COMPOUND SEMICONDUCTOR DEVICE INCLUDING AIN LAYER OF CONTROLLED SKEWNESS - A semiconductor epitaxial substrate includes: a single crystal substrate; an AlN layer epitaxially grown on the single crystal substrate; and a nitride semiconductor layer epitaxially grown on the AN layer, wherein an interface between the AlN layer and nitride semiconductor layer has a larger roughness than an interface between the single crystal substrate and AlN layer, and a skewness of the upper surface of the AlN layer is positive.10-02-2008
20080237609Low Micropipe 100 mm Silicon Carbide Wafer - A high quality single crystal wafer of SiC is disclosed having a diameter of at least about 100 mm and a micropipe density of less than about 25 cm10-02-2008
20090039358SiC Crystal Semiconductor Device - A method for improving the quality of a SiC layer by effectively reducing or eliminating the carrier trapping centers by high temperature annealing and a SiC semiconductor device fabricated by the method. The method for improving the quality of a SiC layer by eliminating or reducing some carrier trapping centers includes the steps of: (a) carrying out ion implantation of carbon atom interstitials (C), silicon atoms, hydrogen atoms, or helium atoms into a shallow surface layer (A) of the starting SiC crystal layer (E) to introduce excess carbon interstitials into the implanted surface layer, and (b) heating the layer for making the carbon interstitials (C) to diffuse out from the implanted surface layer (A) into a bulk layer (E) and for making the electrically active point defects in the bulk layer inactive. After the above steps, the surface layer (A) can be etched or mechanically removed. The SiC semiconductor device is fabricated by the method.02-12-2009
20130168697SILICON CARBIDE STRUCTURE AND MANUFACTURING METHOD THEREOF - A method of manufacturing a silicon carbide structure includes forming a silicon carbide layer by depositing silicon carbide on a base plate by chemical vapor deposition, removing the base plate, decreasing electrical conductivity by heat-treating the silicon carbide structure, and removing a thickness of 200 μm from an upper surface and a lower surface of the silicon carbide structure. In the present invention, silicon carbide is deposited by a CVD method, and the electrical conductivity of the silicon carbide is reduced to the electrical conductivity required for a protection ring of a plasma device through a post-treatment and a post-process. The electrical conductivity may be adjusted even without using separate additives.07-04-2013
20080230787Silicon carbide semiconductor device, and method of manufacturing the same - The silicon carbide semiconductor device includes a trench formed from a surface of a drift layer of a first conductivity type formed on a substrate of the first conductivity type, and a deep layer of a second conductivity type located at a position in the drift layer beneath the bottom portion of the trench. The deep layer is formed at a certain distance from base regions of the second conductivity type formed on the drift layer so as to have a width wider than the width of the bottom portion of the trench, and surround both the corner portions of the bottom portion of the trench.09-25-2008
20130140583SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - First, third, and fourth regions have a first conductivity type, and a second region has a second conductivity type. The second region is provided with a plurality of through holes exposing the first region. The third region includes a contact portion, a connecting portion, and a filling portion. The contact portion is in contact with a first portion of the second region. The connecting portion extends from the contact portion to each of the plurality of through holes in the second region. The filling portion fills each of the plurality of through holes in the second region. The fourth region, is provided on the first portion of the second region.06-06-2013
20130140584SEMICONDUCTOR DEVICE - Disclosed is a JBS diode wherein an increase in an on-voltage is suppressed by sufficiently spreading a current to the lower portion of a junction barrier (p06-06-2013
20130140585JUNCTION BARRIER SCHOTTKY RECTIFIERS HAVING EPITAXIALLY GROWN P+-N JUNCTIONS AND METHODS OF MAKING - A junction barrier Schottky (JBS) rectifier device and a method of making the device are described. The device comprises an epitaxially grown first n-type drift layer and p-type regions forming p06-06-2013
20130140586SILICON CARBIDE SEMICONDUCTOR ELEMENT AND METHOD FOR PRODUCING THE SAME - This silicon carbide semiconductor element includes: a body region of a second conductivity type which is located on a drift layer of a first conductivity type; an impurity region of the first conductivity type which is located on the body region; a trench which runs through the body region and the impurity region to reach the drift layer; a gate insulating film which is arranged on surfaces of the trench; and a gate electrode which is arranged on the gate insulating film. The surfaces of the trench include a first side surface and a second side surface which is opposed to the first side surface. The concentration of a dopant of the second conductivity type is higher at least locally in a portion of the body region which is located beside the first side surface than in another portion of the body region which is located beside the second side surface.06-06-2013
20080224150Silicon carbide semiconductor device - The SiC semiconductor device includes a substrate of a first conduction type made of silicon carbide, a drift layer of the first conduction type made of silicon carbide, the drift layer being less doped than the substrate, a cell portion constituted by a part of the substrate and a part of the drift layer, a circumferential portion constituted by another part of the substrate and another part of the drift layer, the circumferential portion being formed so as to surround the cell portion, and a RESURF layer of a second conduction type formed in a surface portion of the drift layer so as to be located in the circumferential portion. The RESURF layer is constituted by first and second RESURF layers having different impurity concentrations, the second RESURF layer being in contact with an outer circumference of the first RESURF layer and extending to a circumference of the cell portion.09-18-2008
20080224149Silicon Carbide Semiconductor Device and Manufacturing Method Thereof - The present invention provides a silicon carbide semiconductor device comprising a semiconductor substrate comprising silicon carbide, which contains a first conductivity type impurity diffused therein in a high concentration, a semiconductor layer formed over the semiconductor substrate and containing the first conductivity type impurity diffused therein in a low concentration, a plurality of well regions formed on a front surface side of a cell forming area set to the semiconductor layer and in which a second conductivity type impurity corresponding to a type opposite to the first conductivity type impurity is diffused, source layers formed on the front surface side lying within the well regions and each containing the first conductivity type impurity diffused therein in a high concentration, an outer peripheral insulating film thick in thickness, which is formed over the semiconductor layer in an outer peripheral area that surrounds the cell forming area, a gate oxide film formed over the front surface of the semiconductor layer in the cell forming area, and a gate electrode layer formed so as to extend from above the gate oxide film to above the outer peripheral insulating film, wherein each of steplike portions adjacent to the outer peripheral insulating film and thicker than the gate oxide film in thickness is provided at an edge portion of the gate oxide film.09-18-2008
20130175547FIELD EFFECT TRANSISTOR DEVICE - A method for forming a field effect transistor device includes forming a gate stack portion on a substrate, forming a spacer portion on the gates stack portion and a portion of the substrate, removing an exposed portion of the substrate, epitaxially growing a first silicon material on the exposed portion of the substrate, removing a portion of the epitaxially grown first silicon material to expose a second portion of the substrate, and epitaxially growing a second silicon material on the exposed second portion of the substrate and the first silicon material.07-11-2013
20130175548SEMICONDUCTOR DEVICE AND FABRICATION METHOD FOR THE SAME - A fabrication method for a semiconductor device includes the step of forming a gate insulating film on the side of a trench, the bottom thereof, and the periphery thereof. The step of forming a gate insulating film includes a step of forming a first insulating film on the side of the trench and a step of forming a second insulating film on the bottom and periphery of the trench using a high-density plasma chemical vapor deposition method. The thickness of the portions of the gate insulating film formed on the bottom and periphery of the trench is made larger than that of the portion of the gate insulating film formed on the side of the trench.07-11-2013
20130175549SEMICONDUCTOR DEVICE - A semiconductor device (07-11-2013
20130175545SEMICONDUCTOR DEVICE WITH STRAIN-INDUCING REGIONS AND METHOD THEREOF - Improved MOSFET devices are obtained by incorporating strain inducing source-drain regions whose closest facing “nose” portions underlying the gate are located at different depths from the device surface. In a preferred embodiment, the spaced-apart source-drain regions may laterally overlap. This close proximity increases the favorable impact of the strain inducing source-drain regions on the carrier mobility in an induced channel region between the source and drain. The source-drain regions are formed by epitaxially refilling asymmetric cavities etched from both sides of the gate. Cavity asymmetry is obtained by forming an initial cavity proximate only one sidewall of the gate and then etching the final spaced-apart source-drain cavities proximate both sidewalls of the gate along predetermined crystallographic directions. The finished cavities having different depths and nose regions at different heights extending toward each other under the gate, are epitaxially refilled with the strain inducing semiconductor material for the source-drain regions.07-11-2013
20130175546Diamond Semiconductor System and Method - Disclosed herein is a new and improved system and method for fabricating monolithically integrated diamond semiconductor. The method may include the steps of seeding the surface of a substrate material, forming a diamond layer upon the surface of the substrate material; and forming a semiconductor layer within the diamond layer, wherein the diamond semiconductor of the semiconductor layer has n-type donor atoms and a diamond lattice, wherein at least 0.16% of the donor atoms contribute conduction electrons with mobility greater than 770 cm07-11-2013
20130168699SEMICONDUCTOR DEVICE - The semiconductor device of the present invention includes a semiconductor region made of a material to which conductive impurities are added, an insulating film formed on a surface of the semiconductor region, and an electroconductive gate electrode formed on the insulating film. The gate electrode is made of a material whose Fermi level is closer to a Fermi level of the semiconductor region than a Fermi level of Si in at least a portion contiguous to the insulating film.07-04-2013
20130168701SILICON CARBIDE SEMICONDUCTOR ELEMENT AND METHOD FOR FABRICATING THE SAME - A SiC semiconductor element includes: a SiC substrate which has a principal surface tilted with respect to a (0001) Si plane; a SiC layer arranged on the principal surface of the substrate; a trench arranged in the SiC layer and having a bottom, a sidewall, and an upper corner region located between the sidewall and the upper surface of the SiC layer; a gate insulating film arranged on at least a part of the sidewall and on at least a part of the upper corner region of the trench and on at least a part of the upper surface of the SiC layer; and a gate electrode arranged on the gate insulating film. The upper corner region has a different surface from the upper surface of the SiC layer and from a surface that defines the sidewall. The gate electrode contacts with both of a first portion of the gate insulating film located on the upper corner region and a second portion of the gate insulating film located on the sidewall. The first portion of the gate insulating film is thicker than a third portion of the gate insulating film located on the upper surface of the SiC layer. And an end portion of the gate electrode is located on the upper corner region.07-04-2013
20090072241GRID-UMOSFET WITH ELECTRIC FIELD SHIELDING OF GATE OXIDE - A trench metal oxide semiconductor field effect transistor or UMOSFET, includes a buried region that extends beneath the trench and beyond a corner of the trench. The buried region is tied to a source potential of the UMOSFET, and splits the potential realized across the structure. This effectively shields the electric field from the corners of the trench to reduce gate oxide stress, and resultantly improves device performance and reliability.03-19-2009
20130181229SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A MOSFET includes: a substrate having a first trench formed therein, the first trench opening on a side of one main surface; a gate insulating film; and a gate electrode. The substrate includes an n type source region, a p type body region, an n type drift region, and a p type deep region making contact with the body region and extending to a region deeper than the first trench. The first trench is formed such that a distance between the wall surface and the deep region increases with increasing distance from the main surface of the substrate.07-18-2013
20130181230SEMICONDUCTOR SUBSTRATE AND SEMICONDUCTOR SUBSTRATE MANUFACTURING METHOD - A semiconductor substrate includes: a silicon substrate; a monocrystalline silicon carbide film formed on a surface of the silicon substrate; and a stress relieving film formed on the surface of the silicon substrate opposite from the side on which the monocrystalline silicon carbide film is formed, and that relieves stress in the silicon substrate by applying compressional stress to the silicon substrate surface on which the stress relieving film is formed, wherein a plurality of spaces is present in the monocrystalline silicon carbide film in portions on the side of the silicon substrate and along the interface between the monocrystalline silicon carbide film and the silicon substrate.07-18-2013
20130181231MICROPIPE-FREE SILICON CARBIDE AND RELATED METHOD OF MANUFACTURE - Micropipe-free, single crystal, silicon carbide (SiC) and related methods of manufacture are disclosed. The SiC is grown by placing a source material and seed material on a seed holder in a reaction crucible of the sublimation system, wherein constituent components of the sublimation system including the source material, reaction crucible, and seed holder are substantially free from unintentional impurities. By controlling growth temperature, growth pressure, SiC sublimation flux and composition, and a temperature gradient between the source material and the seed material or the SiC crystal growing on the seed material during the PVT process, micropipe-inducing process instabilities are eliminated and micropipe-free SiC crystal is grown on the seed material.07-18-2013
20130181227LED Package with Slanting Structure and Method of the Same - The LED package comprises a substrate with a first conductive type through-hole and a second conductive type through-hole through the substrate; a reflective layer formed on an upper surface of the substrate; a LED die having first conductive type pad and second conductive type pad, wherein the first conductive type pad is aligned with the first conductive type through-hole; a slanting structure of dielectric layer formed adjacent at least one side of the LED die for carrying conductive traces; a conductive trace formed on upper surface of the slanting structure to offer path between the second conductive type pad and the conductive type through-hole; and a refilling material within the first conductive type through-hole and second conductive type through-hole.07-18-2013
20130134442SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A MOSFET includes: a substrate provided with a trench having a side wall surface having an off angle of not less than 50° and not more than 65° relative to a {0001} plane; an oxide film; and a gate electrode. The substrate includes a source region, a body region, and a drift region formed to sandwich the body region between the source region and the drift region. The source region and the body region are formed by means of ion implantation. The body region has an internal region sandwiched between the source region and the drift region and having a thickness of 1 μm or smaller in a direction perpendicular to a main surface thereof. The body region has an impurity concentration of 3×1005-30-2013
20080217626DIAMOND SEMICONDUCTOR ELEMENT AND PROCESS FOR PRODUCING THE SAME - An integrated optical waveguide has a first optical waveguide, a second optical waveguide, and a groove. The second optical waveguide is coupled to the first optical waveguide and has a refractive index that is different from the first optical waveguide. The groove is disposed so as to traverse an optical path of the first optical waveguide and is separated from an interface between the first optical waveguide and the second optical waveguide by a predetermined spacing. The spacing from the interface and the width of the groove are determined such that reflection at a boundary between the first optical waveguide and the second optical waveguide is weakened. A semiconductor board may be disposed at a boundary between the first optical waveguide and the second optical waveguide. In this case, the width of the groove and the thickness of the semiconductor board are determined such that light reflected off an interface between the first optical waveguide and the groove is weakened by light reflected from an interface between the groove and the semiconductor board, and by light reflected from an interface between the semiconductor board and the second optical waveguide.09-11-2008
20120248463EPITAXIAL GROWTH ON LOW DEGREE OFF-AXIS SILICON CARBIDE SUBSTRATES AND SEMICONDUCTOR DEVICES MADE THEREBY - A method of epitaxially growing a SiC layer on a single crystal SiC substrate is described. The method includes heating a single-crystal SiC substrate to a first temperature of at least 1400° C. in a chamber, introducing a carrier gas, a silicon containing gas and carbon containing gas into the chamber; and epitaxially growing a layer of SiC on a surface of the SiC substrate. The SiC substrate is heated to the first temperature at a rate of at least 30° C./minute. The surface of the SiC substrate is inclined at an angle of from 1° to 3° with respect to a basal plane of the substrate material.10-04-2012
20130092958NORMALLY-OFF III-NITRIDE METAL-2DEG TUNNEL JUNCTION FIELD-EFFECT TRANSISTORS - Structures, devices and methods are provided for creating heterojunction AlGaN/GaN metal two-dimensional electron gas (2DEG) tunnel-junction field-effect transistors (TJ-FET). In one aspect, metal-2DEG Schottky tunnel junctions can be employed in group III-Nitride field-effect devices that enable normally-off operation, large breakdown voltage, low leakage current, and high on/off current ratio. As a further advantage, AlGaN/GaN metal-2DEG TJ-FETs are disclosed that can be fabricated in a lateral configuration and/or a vertical configuration. Further non-limiting embodiments are provided that illustrate the advantages and flexibility of the disclosed structures.04-18-2013
20130092957SELF-ALIGNED SILICIDATION FOR REPLACEMENT GATE PROCESS - A semiconductor device is formed with low resistivity self aligned silicide contacts with high-K/metal gates. Embodiments include postponing silicidation of a metal layer on source/drain regions in a silicon substrate until deposition of a high-K dielectric, thereby preserving the physical and morphological properties of the silicide film and improving device performance. An embodiment includes forming a replaceable gate electrode on a silicon-containing substrate, forming source/drain regions, forming a metal layer on the source/drain regions, forming an ILD over the metal layer on the substrate, removing the replaceable gate electrode, thereby forming a cavity, depositing a high-K dielectric layer in the cavity at a temperature sufficient to initiate a silicidation reaction between the metal layer and underlying silicon, and forming a metal gate electrode on the high-K dielectric layer.04-18-2013
20130092955LIGHT EMITTING DIODE AND FABRICATING METHOD THEREOF - A light-emitting diode (LED) and fabricating method thereof. The method includes: providing a first substrate and forming an epitaxial portion on the first substrate; forming at least one reflection layer on the epitaxial portion; forming a metal barrier portion on the reflection layer; etching the epitaxial portion and the barrier portion by a first etching process, so as to form a plurality of epitaxial layers and a plurality of metal barrier layers, an etch channel is formed between adjacent epitaxial layers, and each metal barrier layer enwraps a corresponding reflection layer and covers all of a surface of a corresponding epitaxial layer; forming a first bonding layer on the metal barrier layer; and forming a second substrate on the first bonding layer and removing the first substrate.04-18-2013
20130092956SILICON CARBIDE SUBSTRATE, SILICON CARBIDE SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SILICON CARBIDE SUBSTRATE, AND METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - Single crystal substrates are made of silicon carbide, and each have a first front-side surface and a first backside surface opposite to each other. A support substrate has a second front-side surface and a second backside surface opposite to each other. A connection layer has silicon carbide as a main component, and lies between the single crystal substrates and the support substrate for connecting each of the first backside surfaces and the second front-side surface such that each of the first backside surfaces faces the second front-side surface.04-18-2013
20130092954Strained Silicon Channel Semiconductor Structure and Method of Making the Same - A method for fabricating a strained channel semiconductor structure includes providing a substrate, forming at least one gate structure on said substrate, performing an etching process to form two recesses in said substrate at opposites sides of said gate structure, the sidewall of said recess being concaved in the direction to said gate structure and forming an included angle with respect to horizontal plane, and performing a pre-bake process to modify the recess such that said included angle between the sidewall of said recess and the horizontal plane is increased.04-18-2013
20130099253EPITAXIAL WAFER AND SEMICONDUCTOR DEVICE - A semiconductor device that can suppress deterioration in crystal quality caused by a lattice mismatch between a substrate and an epitaxial layer and that also can ensure a voltage sustaining performance, and a wafer for forming the semiconductor device. An epitaxial wafer of silicon carbide (SiC), which is used for manufacturing a semiconductor device, includes a low resistance substrate and an epitaxial layer provided thereon. The epitaxial layer is doped with the same dopant as a dopant doped into the substrate, and has a laminated structure including a low concentration layer and an ultrathin high concentration layer. A doping concentration in the low concentration layer is lower than that in the silicon carbide substrate. A doping concentration in the ultrathin high concentration layer is equal to that in the silicon carbide substrate.04-25-2013
20130099252METHOD OF MANUFACTURING SILICON CARBIDE SUBSTRATE AND SILICON CARBIDE SUBSTRATE - A method of manufacturing a silicon carbide substrate includes the steps of preparing an ingot composed of single crystal silicon carbide, obtaining a silicon carbide substrate by slicing the ingot, and polishing a surface of the silicon carbide substrate. In the step of obtaining a silicon carbide substrate, the ingot is sliced such that cutting proceeds in a direction in which an angle formed with respect to a <11-20> direction or a <1-100> direction is 15±5° in an orthogonal projection on a {0001} plane. In the step of polishing a surface of the silicon carbide substrate, at least one of main surfaces of the silicon carbide substrate is polished while the entire surface of at least one of the main surfaces of the silicon carbide substrate is in contact with a polishing surface.04-25-2013
20130099251SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - When viewed in a plan view, a termination region (TM) surrounds an element region (CL). A first side of a silicon carbide substrate (SB) is thermally etched to form a side wall (ST) and a bottom surface (BT) in the silicon carbide substrate (SB) at the termination region (TM). The side wall (ST) has a plane orientation of one of {0-33-8} and {0-11-4}. The bottom surface (BT) has a plane orientation of {000-1}. On the side wall (ST) and the bottom surface (BT), an insulating film (04-25-2013
20130099250STRUCTURE OF SEMICONDUCTOR CHIPS WITH ENHANCED DIE STRENGTH AND A FABRICATION METHOD THEREOF - An improved structure of semiconductor chips with enhanced die strength and a fabrication method thereof are disclosed. The improved structure comprises a substrate, an active layer, and a backside metal layer, in which the active layer is formed on the front side of the substrate and includes at least one integrated circuit; the backside metal layer is formed on the backside of the substrate, which fully covers the area corresponding to the area covered by the integrated circuits in the active layer. By using the specific dicing process of the present invention, the backside metal layer and the substrate can be diced tidily. Die cracking on the border between the substrate and the backside metal layer of the diced single chip can be prevented, and thereby the die strength can be significantly enhanced.04-25-2013
20130112995SEMICONDUCTOR WAFER AND METHOD FOR MANUFACTURING THE SAME - An embodiment of a method for manufacturing a semiconductor wafer includes providing a monocrystalline silicon wafer, epitaxially growing a first layer of a first material on the silicon wafer, and epitaxially growing a second layer of a second material on the first layer. For example, said first material may be monocrystalline silicon carbide, and said second material may be monocrystalline silicon.05-09-2013
20130112993SEMICONDUCTOR DEVICE AND WIRING SUBSTRATE - A semiconductor device according to one embodiment of the present invention includes an insulating substrate, a wiring layer formed on a first main surface of the insulating substrate and having a conductive property, and a semiconductor element mounted on the wiring layer. In the semiconductor device, the insulating substrate is composed of cBN or diamond.05-09-2013
20130112997SILICON CARBIDE SUBSTRATE, SEMICONDUCTOR DEVICE, AND SOI WAFER - Disclosed is a silicon carbide substrate which has less high frequency loss and excellent heat dissipating characteristics. The silicon carbide substrate (S) is provided with a first silicon carbide layer (05-09-2013
20130112996SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - There are provided a high-quality semiconductor device having stable characteristics and a method for manufacturing such a semiconductor device. The semiconductor device includes a substrate having a main surface, and a silicon carbide layer. The silicon carbide layer is formed on the main surface of the substrate. The silicon carbide layer includes a side surface as an end surface inclined relative to the main surface. The side surface substantially includes one of a {03-3-8} plane and a {01-1-4} plane in a case where the silicon carbide layer is of hexagonal crystal type, and substantially includes a {100} plane in a case where the silicon carbide layer is of cubic crystal type.05-09-2013
20130112992HIGH TEMPERATURE TRANSDUCER USING SOI, SILICON CARBIDE OR GALLIUM NITRIDE ELECTRONICS - There is disclosed a high temperature pressure sensing system which includes a SOI, silicon carbide, or gallium nitride Wheatstone bridge including piezoresistors. The bridge provides an output which is applied to an analog to digital converter also fabricated using SOI, silicon carbide, or gallium nitride materials. The output of the analog to digital converter is applied to microprocessor, which microprocessor processes the data or output of the bridge to produce a digital output indicative of bridge value. The microprocessor also receives an output from another analog to digital converter indicative of the temperature of the bridge as monitored by a span resistor coupled to the bridge. The microprocessor has a separate memory coupled thereto which is also fabricated from SOI, silicon carbide, or gallium nitride materials and which memory stores various data indicative of the microprocessor also enabling the microprocessor test and system test to be performed.05-09-2013
20130112991SILICON CARBIDE SCHOTTKY-BARRIER DIODE DEVICE AND METHOD FOR MANUFACTURING THE SAME - The present invention provides a silicon carbide Schottky-barrier diode device and a method for manufacturing the same. The silicon carbide Schottky bather diode device includes a primary n− epitaxial layer, an n+ epitaxial region, and a Schottky metal layer. The primary n− epitaxial layer is deposited on an n+ substrate joined with an ohmic metal layer at an undersurface thereof. The n+ epitaxial region is formed by implanting n+ ions into a central region of the primary n− epitaxial layer. The Schottky metal layer is deposited on the n+ epitaxial layer.05-09-2013
20130112994SEMICONDUCTOR MODULE AND METHOD FOR MANUFACTURING SEMICONDUCTOR MODULE - The semiconductor module includes a base and at least one circuit substrate. The at least one circuit substrate has a supporting substrate and a semiconductor element supported by the supporting substrate. The base and/or the supporting substrate has a structure for fitting the at least one circuit substrate with the base.05-09-2013
20130126910SILICON CARBIDE BIPOLAR JUNCTION TRANSISTOR - In at least one aspect, an apparatus can include a silicon carbide material, a base contact disposed on a first portion of the silicon carbide material, and an emitter contact disposed on a second portion of the silicon carbide material. The apparatus can also include a dielectric layer disposed on the silicon carbide material and disposed between the base contact and the emitter contact, and a surface electrode disposed on the dielectric layer and separate from the base contact and the emitter contact.05-23-2013
20130126908Memory Cells, And Methods Of Forming Memory Cells - Some embodiments include memory cells that contain floating bodies and diodes. The diodes may be gated diodes having sections doped to a same conductivity type as the floating bodies, and such sections of the gated diodes may be electrically connected to the floating bodies. The floating bodies may be adjacent channel regions, and spaced from the channel regions by a dielectric structure. The dielectric structure of a memory cell may have a first portion between the floating body and the diode, and may have a second portion between the floating body and the channel region. The first portion may be more leaky to charge carriers than the second portion. The diodes may be formed in semiconductor material that is different from a semiconductor material that the channel regions are in. The floating bodies may have bulbous lower regions. Some embodiments include methods of making memory cells.05-23-2013
20130126907GROUP III NITRIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - [Problem] To provide a group III nitride semiconductor device and a method for manufacturing the same in which dislocation density in a semiconductor layer can be precisely reduced.05-23-2013
20130126904SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A silicon carbide layer includes a first region having a first conductivity type, a second region provided on the first region and having a second conductivity type, and a third region provided on the second region and having the first conductivity type. A trench having an inner surface is formed in the silicon carbide layer. The trench penetrates the second and third regions. The inner surface of the trench has a first side wall and a second side wall located deeper than the first side wall and having a portion made of the second region. Inclination of the first side wall is smaller than inclination of the second side wall.05-23-2013
20110272711METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR APPARATUS - There is provided a method of manufacturing a semiconductor device, a semiconductor device, and a semiconductor apparatus, by which an electrode having an excellent ohmic property can be formed, and a semiconductor device having excellent device characteristics can be obtained with a high product yield. The method sequentially includes: a semiconductor device structure formation process in which a semiconductor device structure 11-10-2011
20110272710Solid state energy photovoltaic device - A solid state energy conversion device and method of making is disclosed for converting energy between electromagnetic and electrical energy. The solid state energy conversion device comprises a wide bandgap semiconductor material having a first doped region. A thermal energy beam is directed onto the first doped region of the wide bandgap semiconductor material in the presence of a doping gas for converting a portion of the first doped region into a second doped region in the wide bandgap semiconductor material. A first and a second Ohmic contact are applied to the first and the second doped regions of the wide bandgap semiconductor material. In one embodiment, the solid state energy conversion device operates as a light emitting device to produce electromagnetic radiation upon the application of electrical power to the first and second Ohmic contacts. In another embodiment, the solid state energy conversion device operates as a photovoltaic device to produce electrical power between the first and second Ohmic contacts upon the application of electromagnetic radiation.11-10-2011
20110272709RADIATION HEATING EFFICIENCY BY INCREASING OPTICAL ABSORPTION OF A SILICON CONTAINING MATERIAL - Embodiments of the present invention generally provide a process and apparatus for increasing the absorption coefficient of a chamber component disposed in a thermal process chamber. In one embodiment, a method generally includes providing a substrate carrier having a first surface and a second surface, the first surface is configured to support a substrate and being parallel and opposite to the second surface, subjecting the second surface of the substrate carrier to a surface treatment process to roughen the second surface of the substrate carrier, wherein the substrate carrier contains a material comprising silicon carbide, and forming an oxide-containing layer on the roughened second surface of the substrate carrier. The formed oxide-containing layer has optical absorption properties at wavelengths close to the radiation delivered from one or more energy sources used to heat the chamber component.11-10-2011
20100276703SILICON CARBIDE SEMICONDUCTOR DEVICE - A MOS type SiC semiconductor device having high reliability and a longer lifespan against TDDB of a gate oxide film is disclosed. The semiconductor device includes a MOS (metal-oxide-semiconductor) structure having a silicon carbide (SiC) substrate, a polycrystalline Si gate electrode, a gate oxide film interposed between the SiC substrate and the polycrystalline Si gate electrode and formed by thermally oxidizing a surface of the SiC substrate, and an ohmic contact electrically contacted with the SiC substrate. The semiconductor device further includes a polycrystalline Si thermally-oxidized film formed by oxidizing a surface of the polycrystalline Si gate electrode. The gate oxide film has a thickness of 20 nm or less, preferably 15 nm or less.11-04-2010
20080203399POLARIZATION DOPED TRANSISTOR CHANNELS IN SIC HETEROPOLYTYPES - Heteropolytype SiC heterojunctions display an abrupt change in polarization leading to 2 dimensional electron or hole gases at the lattice matched interface, depending on the direction of polarization. These channels carry a large amount of electric current which can be modulated with a gate electrode, giving rise to transistor operation in the lateral geometry without the need for n or p type doping. Furthermore, some of these structures display high turn-on voltages which may have applications in terahertz sources and exotic diodes in the transverse geometry.08-28-2008
20080203397Switching Device - A high voltage diamond based switching device capable of sustaining high currents in the on state with a relatively low impedance and a relatively low optical switching flux, and capable of being switched off in the presence of the high voltage being switched. The device includes a diamond body having a Schottky barrier contact, held in reverse bias by the applied voltage to be switched, to an essentially intrinsic diamond layer or portion in the diamond body, a second metal contact, and an optical source or other illuminating or irradiating device such that when the depletion region formed by the Schottky contact to the intrinsic diamond layer is exposed to its radiation charge carriers are generated. Cain in the total number of charge carriers then occurs as a result of these charge carriers accelerating under the field within the intrinsic diamond layer and generating further carriers by assisted avalanche breakdown.08-28-2008
20100078653TRANSISTOR HAVING A HIGH-K METAL GATE STACK AND A COMPRESSIVELY STRESSED CHANNEL - In a manufacturing flow for adapting the band gap of the semiconductor material with respect to the work function of a metal-containing gate electrode material, a strain-inducing material may be deposited to provide an additional strain component in the channel region. For instance, a layer stack with silicon/carbon, silicon and silicon/germanium may be used for providing the desired threshold voltage for a metal gate while also providing compressive strain in the channel region.04-01-2010
20130146898SiC MOSFETS AND SELF-ALIGNED FABRICATION METHODS THEREOF - The present application provides a method of fabricating a metal oxide semiconductor field effect transistor. The method includes the steps of forming a source region on a silicon carbide layer and annealing the source region. A gate oxide layer is formed on the source region and the silicon carbide layer. The method further includes providing a gate electrode on the gate oxide layer and disposing a dielectric layer on the gate electrode and the gate oxide layer. The method further includes etching a portion of the dielectric layer and a portion of the gate oxide layer to form sidewalls on the gate electrode. A metal layer is disposed on the gate electrode, the sidewalls and the source region. The method further includes forming a gate contact and a source contact by subjecting the metal layer to a temperature of at least about 800° C. The gate contact and the source contact comprise a metal silicide. The distance between the gate contact and the source contact is less than about 0.6 μm. A vertical SiC MOSFET is also provided.06-13-2013
20130146894BIPOLAR JUNCTION TRANSISTOR STRUCTURE FOR REDUCED CURRENT CROWDING - The present disclosure relates to a bipolar junction transistor (BJT) structure that significantly reduces current crowding while improving the current gain relative to conventional BJTs. The BJT includes a collector, a base region, and an emitter. The base region is formed over the collector and includes at least one extrinsic base region and an intrinsic base region that extends above the at least one extrinsic base region to provide a mesa. The emitter is formed over the mesa. The BJT may be formed from various material systems, such as the silicon carbide (SiC) material system. In one embodiment, the emitter is formed over the mesa such that essentially none of the emitter is formed over the extrinsic base regions. Typically, but not necessarily, the intrinsic base region is directly laterally adjacent the at least one extrinsic base region.06-13-2013
20130146895PINCH-OFF CONTROL OF GATE EDGE DISLOCATION - The embodiments of processes and structures described provide mechanisms for improving the mobility of carriers. A dislocation is formed in a source or drain region between gate structures or between a gate structure and an isolation structure by first amortizing the source or drain region and then recrystallizing the region by using an annealing process with a low pre-heat temperature. A doped epitaxial material may be formed over the recrystallized region. The dislocation and the strain created by the doped epitaxial material in the source or drain region help increase carrier mobility.06-13-2013
20130146896SEMICONDUCTOR OPTICAL DEVICE HAVING AN AIR MEDIA LAYER AND THE METHOD FOR FORMING THE AIR MEDIA LAYER THEREOF - A method for fabricating air media layer within the semiconductor optical device is provided. The step of method includes a substrate is provided, a GaN thin film is formed on the substrate, a sacrificial layer is formed on the GaN thin film, and a nitride-containing semiconductor layer is formed on the sacrificial layer. The semiconductor optical device is immersed with an acidic solution to remove the portion of sacrificial layer to form an air media layer around the residual sacrificial layer.06-13-2013
201301468974h-SiC SEMICONDUCTOR ELEMENT AND SEMICONDUCTOR DEVICE - A trench groove is formed and a silicon oxide film is buried in the periphery of a channel region of (0001) surface 4h-SiC semiconductor element. The oxide film in the trench groove is defined in such a planar layout that a tensile strain is applied along the direction of the c-axis and a compressive strain is applied along two or more of axes on a plane perpendicular to the c-axis. For example, trench grooves buried with an oxide film may be configured to such a layout that they are in a trigonal shape surrounding the channel, or are arranged symmetrically with respect to the channel as a center when arranged discretely.06-13-2013
20130126906SILICON CARBIDE EPITAXIAL WAFER AND MANUFACTURING METHOD THEREFOR, SILICON CARBIDE BULK SUBSTRATE FOR EPITAXIAL GROWTH AND MANUFACTURING METHOD THEREFOR AND HEAT TREATMENT APPARATUS - A method is provided in order to manufacture a silicon carbide epitaxial wafer whose surface flatness is very good and has a very low density of carrot defects and triangular defects arising after epitaxial growth. The silicon carbide epitaxial wafer is manufactured by a first step of annealing a silicon carbide bulk substrate that is tilted less than 5 degrees from <0001> face, in a reducing gas atmosphere at a first temperature T05-23-2013
20080197361INSULATED GATE SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - An insulated gate silicon carbide semiconductor device is provided having small on-resistance in a structure obtained by combining the SIT and MOSFET structures having normally-off operation. The device includes an n08-21-2008
20080197360Diode Having Reduced On-resistance and Associated Method of Manufacture - A diode structure having a reduced on-resistance in the forward-biased condition includes semiconductor layers, preferably of silicon carbide. The anode and cathode of the device are located on the same side of the bottom semiconductor layer, providing lateral conduction across the diode body. The anode is positioned on a semiconductor mesa, and the sides of the mesa are covered with a nonconductive spacer extending from the anode to the bottom layer. An ohmic contact, preferably a metal silicide, covers the surface of the bottom layer between the spacer material and the cathode. The conductive path extends from anode to cathode through the body of the mesa and across the bottom semiconductor layer, including the ohmic contact. The method of forming the diode includes reacting layers of silicon and metal on the appropriate regions of the diode to form an ohmic contact of metal silicide.08-21-2008
20110227095Semiconductor Device Including a Normally-On Transistor and a Normally-Off Transistor - A semiconductor device is disclosed. One embodiment includes a first semiconductor die having a normally-off transistor. In a second semiconductor die a plurality of transistor cells of a normally-on transistor are formed, wherein one of a source terminal/drain terminal of the normally-on transistor is electrically coupled to a gate terminal of the normally-on transistor and the other one the source terminal/drain terminal of the normally-off transistor is electrically coupled to one of a source terminal/drain terminal of the normally-on transistor. The second semiconductor die includes a gate resistor electrically coupled between the gate terminal of the normally-off transistor and respective gates of the plurality of transistor cells. A voltage clamping element is electrically coupled between the gate terminal and the one of the source terminal/drain terminal of the normally-on transistor.09-22-2011
20100308343SILICON CARBIDE SEMICONDUCTOR DEVICE - According to the embodiment, a semiconductor device includes an SiC substrate of a first or second conductivity type. An SiC layer of the first conductivity type is formed on a front surface of the substrate, a first SiC region of the second conductivity type is formed on the SiC layer, a second SiC region of the first conductivity type is formed within a surface of the first SiC region, a gate dielectric is continuously formed on the SiC layer, the second SiC region, and the surface of the first SiC region interposed between the SiC layer and the second SiC region, a gate electrode is formed on the gate dielectric, a first electrode is embedded in a trench selectively formed in a part where the first SiC region adjoins the second SiC region, and a second electrode is formed on a back surface of the substrate.12-09-2010
20100308341SEMICONDUCTOR MEMORY DEVICE - A switching resistance RAM that is highly integrated as well as reduced in a read-out time is realized. There is formed an NPN type bipolar transistor BT composed of a collector layer made of an N-well 12-09-2010
20120273803THERMAL DISSIPATION SUBSTRATE - The present invention related to a method for manufacturing a thermal dissipation substrate and a thermal dissipation substrate. The method includes steps of: (a) providing a substrate body having a surface; (b) forming a plurality of concave regions on the surface; and (c) filling the plurality of concave regions with a plurality of diamond materials. The thermal dissipation substrate includes: a substrate having a surface at a first horizontal; a plurality of regions formed on the surface at a second horizontal; and a plurality of diamond materials having a relatively high thermal coefficient and disposed on the plurality of regions.11-01-2012
20120273801SILICON CARBIDE SEMICONDUCTOR DEVICE - A SiC semiconductor device includes: a SiC substrate including a first or second conductive type layer and a first conductive type drift layer and including a principal surface having an offset direction; a trench disposed on the drift layer and having a longitudinal direction; and a gate electrode disposed in the trench via a gate insulation film. A sidewall of the trench provides a channel formation surface. The vertical semiconductor device flows current along with the channel formation surface of the trench according to a gate voltage applied to the gate electrode. The offset direction of the SiC substrate is perpendicular to the longitudinal direction of the trench.11-01-2012
20120273800COMPOSITE SUBSTRATE HAVING SINGLE-CRYSTAL SILICON CARBIDE SUBSTRATE - A first vertex of a first single-crystal silicon carbide substrate and a second vertex of a second single-crystal silicon carbide substrate abut each other such that a first side of the first single-crystal silicon carbide substrate and a second side of the second single-crystal silicon carbide substrate are aligned. In addition, at least a part of the first side and at least a part of the second side abut on a third side of a third single-crystal silicon carbide substrate. Thus, in manufacturing a semiconductor device including a composite substrate, process fluctuations caused by a gap between the single-crystal silicon carbide substrates can be suppressed.11-01-2012
20130187171METHOD TO FORM SILICIDE CONTACT IN TRENCHES - A method for forming silicide contacts includes forming a dielectric layer on a gate spacer, a gate stack, and a first semiconductor layer. The first semiconductor layer comprises source/drain regions. Contact trenches are formed in the dielectric layer so as to expose at least a portion of the source/drain regions. A second semiconductor layer is formed within the contact trenches. A metallic layer is formed on the second semiconductor layer. An anneal is performed to form a silicide region between the second semiconductor layer and the metallic layer. A conductive contact layer is formed on the metallic layer or the silicide region.07-25-2013
20110233562SUBSTRATE, SUBSTRATE WITH THIN FILM, SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A substrate achieving suppressed deterioration of processing accuracy of a semiconductor device due to bending of the substrate, a substrate with a thin film and a semiconductor device formed with the substrate above, and a method of manufacturing the semiconductor device above are obtained. A substrate according to the present invention has a main surface having a diameter of 2 inches or greater, a value for bow at the main surface being not smaller than −40 μm and not greater than −5 μm, and a value for warp at the main surface being not smaller than 5 μm and not greater than 40 μm. Preferably, a value for surface roughness Ra of the main surface of the substrate is not greater than 1 nm and a value for surface roughness Ra of a main surface is not greater than 100 nm.09-29-2011
20110233561SEMICONDUCTOR SUBSTRATE - A supporting portion is made of silicon carbide. At least one layer has first and second surfaces. The first surface is supported by the supporting portion. The at least one layer has first and second regions. The first region is made of silicon carbide of a single-crystal structure. The second region is made of graphite. The second surface has a surface formed by the first region. The first surface has a surface formed by the first region, and a surface formed by the second region. In this way, a semiconductor substrate can be provided which has a region made of silicon carbide having a single-crystal structure and a supporting portion made of silicon carbide and allows for reduced electric resistance of an interface therebetween.09-29-2011
20110233560Electrode for silicon carbide, silicon carbide semiconductor element, silicon carbide semiconductor device and method for forming electrode for silicon carbide - An electrode for silicon carbide includes a silicide region which is provided in contact with a surface of a silicon carbide (SiC) layer and a carbide region which is provided on the silicide region. The silicide region contains a silicide of a first metal in more amount than a carbide of a second metal whose free energy of carbide formation is less than that of silicon (Si). The carbide region contains the carbide of the second metal in more amount than the silicide of the first metal.09-29-2011
20110233563SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing of a semiconductor device (09-29-2011
20100314629SILICON CARBIDE SEMICONDUCTOR DEVICE - In order to obtain a silicon carbide semiconductor device that ensures both stability of withstand voltage and reliability in high-temperature operations in its termination end-portion provided for electric-field relaxation in the perimeter of a cell portion driven as a semiconductor element, the termination end-portion is provided with an inorganic protection film having high heat resistance that is formed on an exposed surface of a well region as a first region formed on a side of the cell portion, and an organic protection film having a high electrical insulation capability with a little influence by electric charges that is formed on a surface of an electric-field relaxation region formed in contact relation to an outer lateral surface of the well region and apart from the cell portion, and on an exposed surface of the silicon carbide layer.12-16-2010
20100314628PROCESS FOR TRANSFERRING A LAYER OF STRAINED SEMICONDUCTOR MATERIAL - Semiconductor wafers having a thin layer of strained semiconductor material. These structures include a substrate; an oxide layer upon the substrate; a silicon carbide (SiC) layer upon the oxide layer, and a strained layer of a semiconductor material in a strained state upon the silicon carbide layer, or a matching layer upon the donor substrate that is made from a material that induces strain in subsequent epitaxially grown layers thereon; a strained layer of a semiconductor material of defined thickness in a strained state; and an insulating or semi-insulating layer upon the strained layer in a thickness that retains the strained state of the strained layer. The insulating or semi-insulating layers are made of silicon carbide or oxides and act to retain strain in the strained layer.12-16-2010
20100314627DIAMOND GaN DEVICES AND ASSOCIATED METHODS - Semiconductor devices and methods of making thereof are provided. In one aspect, for example, a method for making a semiconductor device can include polishing a working surface of a diamond layer to a substantially flat surface, depositing a buffer layer on the working surface of the diamond layer, and depositing a semiconductor layer on the buffer layer. In one specific aspect, the c-axis of the buffer layer is oriented perpendicular to the working surface of the diamond layer.12-16-2010
20100314626SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A silicon carbide semiconductor device having excellent performance characteristics and a method of manufacturing the same are obtained. An extended terrace surface is formed at a surface of an initial growth layer on a 4H—SiC substrate by annealing with the initial growth layer covered with an Si film, and then a new growth layer is epitaxially grown on the initial growth layer. A 3C—SiC portion having a polytype stable at a low temperature is grown on the extended terrace surface, and a 4H—SiC portion is grown on the other region. A trench is formed by selectively removing the 3C—SiC portion with the 4H—SiC portion remaining, and a gate electrode of a UMOSFET is formed in the trench. A channel region of the UMOSFET can be controlled to have a low-order surface, and a silicon carbide semiconductor device having high channel mobility and excellent performance characteristics is obtained.12-16-2010
20110272708NITRIDE SEMICONDUCTOR DEVICE - According to one embodiment, a nitride semiconductor device includes a first, a second and a third semiconductor layer, a first and a second main electrode and a control electrode. The first layer made of a nitride semiconductor of a first conductivity type is provided on a substrate. The second layer made of a nitride semiconductor of a second conductivity type is provided on the first layer. The third layer made of a nitride semiconductor is provided on the second layer. The first electrode is electrically connected with the second layer. The second electrode is provided at a distance from the first electrode and electrically connected with the second layer. The control electrode is provided within a first trench via an insulating film. The first trench is disposed between the first and the second main electrodes, penetrates the third and the second layers, and reaches the first layer.11-10-2011
20110272707SUBSTRATES AND METHODS OF FORMING FILM STRUCTURES TO FACILITATE SILICON CARBIDE EPITAXY - Embodiments of the invention relate generally to semiconductors and semiconductor fabrication techniques, and more particularly, to devices, integrated circuits, substrates, wafers and methods to form film structures to facilitate formation of silicon carbide epitaxy on a substrate, such as a silicon-based substrate. In some embodiments, a method of preparing a substrate for silicon carbide epitaxial layer formation can include forming an ultrathin layer of oxide that is configured to inhibit contaminants from interacting with a silicon-based substrate. Further, the method can include forming a carbonized film on the silicon-based substrate that is configured to inhibit contaminants from interacting with the silicon-based substrate. The carbonized film can be configured to be transitory as fabrication parameters are modified to form an epitaxial layer of silicon carbide.11-10-2011
20130153925SEMICONDUCTOR DEVICE - A MOSFET includes: a substrate having a trench formed therein and made of silicon carbide, the trench being opened on one main surface side and having a side wall surface; a gate insulating film formed on the side wall surface in contact therewith; and a gate electrode formed on the gate insulating film in contact therewith, wherein a square region with each side of 100 nm in the side wall surface has a surface roughness of not more than 1.0 nm in RMS.06-20-2013
20130153926SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A MOSFET includes: a substrate made of silicon carbide and having a first trench and a second trench formed therein, the first trench having an opening at the main surface side, the second trench having an opening at the main surface side and being shallower than the first trench; a gate insulating film; a gate electrode; and a source electrode disposed on and in contact with a wall surface of the second trench. The substrate includes a source region, a body region, and a drift region. The first trench is formed to extend through the source region and the body region and reach the drift region. The second trench is formed to extend through the source region and reach the body region.06-20-2013
20130153929METHOD AND STRUCTURE FOR FORMING HIGH-K/METAL GATE EXTREMELY THIN SEMICONDUCTOR ON INSULATOR DEVICE - A semiconductor device is provided that includes a gate structure present on a substrate. The gate structure includes a gate conductor with an undercut region in sidewalls of a first portion of the gate conductor, wherein a second portion of the gate conductor is present over the first portion of the gate conductor and includes a protruding portion over the undercut region. A spacer is adjacent to sidewalls of the gate structure, wherein the spacer includes an extending portion filling the undercut region. A raised source region and a raised drain region is present adjacent to the spacers. The raised source region and the raised drain region are separated from the gate conductor by the extending portion of the spacers.06-20-2013
20130153928METHOD FOR CONTROLLED GROWTH OF SILICON CARBIDE AND STRUCTURES PRODUCED BY SAME - A method for controlled growth of silicon carbide and structures produced by the method are disclosed. A crystal of silicon carbide (SiC) can be grown by placing a sacrificial substrate in a growth zone with a source material. The source material may include a low-solubility impurity. SiC is then grown on the sacrificial substrate to condition the source material. The sacrificial substrate is then replaced with the final substrate, and SiC is grown on the final substrate. A single crystal of silicon carbide is produced, wherein the crystal of silicon carbide has substantially few micropipe defects. Such a crystal may also include a substantially uniform concentration of the low-solubility impurity, and may be used to make wafers and/or SiC die.06-20-2013
20120280251CAVITY-FREE INTERFACE BETWEEN EXTENSION REGIONS AND EMBEDDED SILICON-CARBON ALLOY SOURCE/DRAIN REGIONS - A gate stack is formed on a silicon substrate, and source/drain extension regions are formed around the gate stack. A dielectric spacer is formed around the gate stack. A pair of trenches is formed around the gate stack and the dielectric spacer by an etch so that sidewalls of the source/drain extension regions are exposed. Within each trench, an n-doped silicon liner is deposited on the sidewalls of the trenches by a first selective epitaxy process so that the interface between the dielectric spacer and the source/drain extension region is covered. Within each trench, an n-doped single crystalline silicon-carbon alloy is subsequently deposited to fill the trench by a second selective epitaxy process. A combination of an n-doped single crystalline silicon liner and an n-doped single crystalline silicon-carbon alloy functions as embedded source/drain regions of an n-type field effect transistor (NFET), which applies a tensile stress to the channel of the transistor.11-08-2012
20110278593METHOD FOR MANUFACTURING SILICON CARBIDE SUBSTRATE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, SILICON CARBIDE SUBSTRATE, AND SEMICONDUCTOR DEVICE - A method for manufacturing a silicon carbide substrate includes the steps of: preparing a SiC substrate made of single-crystal silicon carbide; disposing a base substrate in a crucible so as to face a main surface of the SiC substrate; and forming a base layer made of silicon carbide in contact with the main surface of the SiC substrate, by heating the base substrate in the crucible to fall within a range of temperature higher than a sublimation temperature of silicon carbide constituting the base substrate. In the step of forming the base layer, a gas containing silicon is introduced into the crucible.11-17-2011
20110278591POWER SEMICONDUCTOR SWITCH - A SiC JFET that includes a plurality of trenches formed in a SiC semiconductor body of one conductivity each trench having a region of another conductivity formed in the bottom and sidewalls thereof.11-17-2011
20110291108SEMICONDUCTOR PHOTODETECTOR WITH TRANSPARENT INTERFACE CHARGE CONTROL LAYER AND METHOD THEREOF - A detection device comprising a photodetector comprising a first semiconductor layer through which light first enters the photodetector; the first semiconductor layer to semiconductor material crystal lattice which terminates at an interface; the discontinuity of the semiconductor crystal lattice at the interface creating a first interface charge; the first semiconductor layer being an absorption layer in which photons in a predetermined wavelength range are absorbed and create photogenerated carriers; and a second polar semiconductor layer deposited on the crystal lattice of the first semiconductor layer, the second polar semiconductor being substantially transparent to light in the predetermined wavelength range, the second polar semiconductor layer having a total polarization different from the first semiconductor layer so that a second interface charge is induced at the interface between the first and second semiconductor layers; the induced second interface charge reduces or substantially cancels the first interface charge; whereby the reduction or substantial cancellation of the surface charge in the first semiconductor layer increases the collection of photogenerated carriers by the photodetector. A method of improving the quantum efficiency of a semiconductor photodetector comprising providing a semiconductor photodetector having a first layer which has a first interface through which light first enters the semiconductor photodetector; placing a layer of polar material transparent to the band of detection wavelengths that has a polarization substantially different than the polarization of the first layer such that the polarization charge induced at the interface between the layer of polar material and the first surface results in decreased interface recombination of photogenerated minority carriers and an increase in quantum efficiency of the photodetector.12-01-2011
20110297964AC SWITCH - An AC switch includes a first compound semiconductor MOSFET and a second compound semiconductor MOSFET whose sources are connected with each other, a first output terminal connected to the drain of the first compound semiconductor MOSFET, and a second output terminal connected to the drain of the second compound semiconductor MOSFET. The withstand voltage between the first output terminal and the second output terminal in an off state is not less than 400 V. The resistance between the first output terminal and the second output terminal in an on state is not more than 20 mΩ.12-08-2011
20110303925Semiconductor device and the method of manufacturing the same - A semiconductor device according to the invention includes p-type well region 3 and n12-15-2011
20110309376METHOD OF CLEANING SILICON CARBIDE SEMICONDUCTOR, SILICON CARBIDE SEMICONDUCTOR, AND SILICON CARBIDE SEMICONDUCTOR DEVICE - A method of cleaning an SiC semiconductor capable of exhibiting an effect of cleaning an SiC semiconductor is provided. An SiC semiconductor and an SiC semiconductor device capable of achieving improved characteristics are provided. The method of cleaning an SiC semiconductor includes the steps of forming an oxide film on a surface of an SiC semiconductor (step S12-22-2011
20110309375SEMICONDUCTOR DEVICE - A semiconductor device includes semiconductor elements mounted on a heat spreader, lead frames connected to the semiconductor elements, and a molding resin which holds them and forms a housing. Upper portions and side surfaces of the semiconductor elements are covered with an organic thin film which is formed between the semiconductor elements and the molding resin.12-22-2011
20130187172NITRIDE SEMICONDUCTOR EPITAXIAL WAFER AND FIELD EFFECT NITRIDE TRANSISTOR - A nitride semiconductor epitaxial wafer includes a substrate, a GaN layer provided over the substrate, and an AlGaN layer provided over the GaN layer. The GaN layer has a wurtzite crystal structure, and a ratio c/a of a lattice constant c in a c-axis orientation of the GaN layer to a lattice constant a in an a-axis orientation of the GaN layer is not more than 1.6266.07-25-2013
20130187173CONDUCTIVITY MODULATION IN A SILICON CARBIDE BIPOLAR JUNCTION TRANSISTOR - In one general aspect, a silicon carbide bipolar junction transistor (BJT) can include a collector region, a base region on the collector region, and an emitter region on the base region. The silicon carbide BJT can include a base contact electrically contacting the base region where the base region having an active part interfacing the emitter region. The silicon carbide BJT can also include an intermediate region of semiconductor material having at least a part extending from the active part of the base region to the base contact where the intermediate region having a doping level higher than a doping level of the active part of the base region.07-25-2013
20120018743SEMICONDUCTOR DEVICE - A MOSFET includes a silicon carbide substrate including a main surface having an off angle of not less than 50° and not more than 65° with respect to a {0001} plane, a buffer layer and a drift layer formed on the main surface, a gate oxide film formed on and in contact with the drift layer, and a p type body region of a p conductivity type formed in the drift layer to include a region in contact with the gate oxide film. The p type body region has a p type impurity density of not less than 5×1001-26-2012
20120018742SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a SiC substrate, a semiconductor layer formed on the SiC substrate, a via hole penetrating through the SiC substrate and the semiconductor layer, a Cu pad that is formed on the semiconductor layer and is in contact with the via hole, and a barrier layer covering an upper face and side faces of the Cu pad, and restrains Cu diffusion.01-26-2012
20120018741SEMICONDUCTOR APPARATUS - A semiconductor apparatus according to embodiments of the invention can include a first semiconductor device made of silicon, the first semiconductor devices being arranged collectively, whereby to form a first device group, and a second semiconductor device made of silicon carbide, the second semiconductor devices being arranged collectively, whereby to form a second device group. The apparatus can also include a wiring conductor connecting the first semiconductor device and the second semiconductor device, a cooling fin base comprising a projection formed thereon, whereby to dissipate heat generated from the first and second semiconductor devices, and the projections arranged under the second device group being spaced apart from each other more widely than the projections arranged under the first device group.01-26-2012
20120018740SEMICONDUCTOR ELEMENT AND MANUFACTURING METHOD THEREFOR - A semiconductor device 01-26-2012
20120018739BODY CONTACT DEVICE STRUCTURE AND METHOD OF MANUFACTURE - The present invention provides a body contact device structure and a method for manufacturing the same. According to the present invention, an opening is formed by removing one end of a dummy gate stack after forming the dummy gate stack, wherein a residual portion of the dummy gate stack is a body stack comprising a body pile-up layer that directly contacts a substrate. Next, a replacement gate stack is formed in the opening, and then a body contact is formed on the body pile-up layer in the body stack. The body contact device structure formed by the method of the present invention effectively reduces the parasitic effects and the device area, and improves the performance of the device structure.01-26-2012
20120018738ELECTRONIC DEVICE STRUCTURE WITH A SEMICONDUCTOR LEDGE LAYER FOR SURFACE PASSIVATION - Electronic device structures including semiconductor ledge layers for surface passivation and methods of manufacturing the same are disclosed. In one embodiment, the electronic device includes a number of semiconductor layers of a desired semiconductor material having alternating doping types. The semiconductor layers include a base layer of a first doping type that includes a highly doped well forming a first contact region of the electronic device and one or more contact layers of a second doping type on the base layer that have been etched to form a second contact region of the electronic device. The etching of the one or more contact layers causes substantial crystalline damage, and thus interface charge, on the surface of the base layer. In order to passivate the surface of the base layer, a semiconductor ledge layer of the semiconductor material is epitaxially grown on at least the surface of the base layer.01-26-2012
20120018737ELECTRONIC DEVICE STRUCTURE INCLUDING A BUFFER LAYER ON A BASE LAYER - Electronic device structures that compensate for non-uniform etching on a semiconductor wafer and methods of fabricating the same are disclosed. In one embodiment, the electronic device includes a number of layers including a semiconductor base layer of a first doping type formed of a desired semiconductor material, a semiconductor buffer layer on the base layer that is also formed of the desired semiconductor material, and one or more contact layers of a second doping type on the buffer layer. The one or more contact layers are etched to form a second contact region of the electronic device. The buffer layer reduces damage to the semiconductor base layer during fabrication of the electronic device. Preferably, a thickness of the semiconductor buffer layer is selected to compensate for over-etching due to non-uniform etching on a semiconductor wafer on which the electronic device is fabricated.01-26-2012
20130193448PATTERNED SUBSTRATE AND STACKED LIGHT EMITTING DIODE - A patterned substrate is provided, including: a substrate having a (0001) crystal plane and a plurality of alternatively arranged recess structures therein, thereby forming a plurality of alternatively arranged top surfaces; and a dielectric barrier layer covering the bottom surface and/or the sidewalls of the recess structures. Each of the alternatively arranged recess structures includes a bottom surface and a plurality of sidewalls surrounding the bottom surface.08-01-2013
20130193449PRODUCTION OF AN INTEGRATED CIRCUIT INCLUDING ELECTRICAL CONTACT ON SiC - Production of an integrated circuit including an electrical contact on SiC is disclosed. One embodiment provides for production of an electrical contact on an SiC substrate, in which a conductive contact is produced on a boundary surface of the SiC substrate by irradiation and absorption of a laser pulse on an SiC substrate.08-01-2013
20130193447SILICON CARBIDE SEMICONDUCTOR DEVICE - A silicon carbide semiconductor device includes an insulation film, and a silicon carbide layer having a surface covered with the insulation film. The surface includes a first region. The first region has a first plane orientation at least partially. The first plane orientation is any of a (0-33-8) plane, (30-3-8) plane, (-330-8) plane, (03-3-8) plane, (-303-8) plane, and (3-30-8) plane.08-01-2013
20120025206SEMICONDUCTOR DEVICE - A semiconductor device includes a first GaN layer provided on a SIC substrate, a second GaN layer provided on the first GaN layer, and an electron supply layer that is provided on the second GaN layer and has a band gap greater than that of GaN, the first GaN layer having an acceptor concentration higher than that of the second GaN layer.02-02-2012
20120056201INSULATED GATE BIPOLAR TRANSISTOR - An IGBT, which is a vertical type IGBT allowing for reduced on-resistance while restraining defects from being produced, includes: a silicon carbide substrate, a drift layer, a well region, an n03-08-2012
20120056197SEMICONDUCTOR RECTIFYING DEVICE - A wide bandgap semiconductor rectifying device of an embodiment includes a first-conductive-type wide bandgap semiconductor substrate and a first-conductive-type semiconductor layer that has an impurity concentration lower than that of the substrate. The device also includes a first-conductive-type first semiconductor region, and a second-conductive-type second semiconductor region that is formed between the first regions. The device also includes second-conductive-type third semiconductor regions in which at least part of the third regions are connected to the second wide bandgap semiconductor region, the third regions being formed between the first regions, the third regions having a width narrower than that of the second region. The device also includes a first electrode and a second electrode. In the device, a direction in which a longitudinal direction of the third regions are projected onto a (0001) plane of the layer has an angle of 90±30 degrees with respect to a <11-20> direction of the layer. A gap between the third regions is not lower than 203-08-2012
20130200392Semicondictor Device with Edge Termination and Method for Manufacturing a Semiconductor Device - According to an embodiment, a semiconductor device includes a semiconductor body having a first semiconductor material and a second semiconductor material having a band gap larger than a band gap of the first semiconductor material. A first pn-junction is formed in the first semiconductor material. A second pn-junction is formed by the second semiconductor material and extends deeper into the semiconductor body than the first pn-junction. The second semiconductor material is in contact with the first semiconductor material and forms part of an edge termination zone of the semiconductor device.08-08-2013
20130200393SEMICONDUCTOR STRUCTURE AND PROCESS THEREOF - A semiconductor structure includes a substrate, a resist layer, a dielectric material, two U-shaped metal layers and two metals. The substrate has an isolation structure. The resist layer is located on the isolation structure. The dielectric material is located on the resist layer. Two U-shaped metal layers are located at the two sides of the dielectric material and on the resist layer. Two metals are respectively located on the two U-shaped metal layers. This way a semiconductor process for forming said semiconductor structure is provided.08-08-2013
20130200394SEMICONDUCTOR-ON-DIAMOND DEVICES AND ASSOCIATED METHODS - Semiconductor-on-diamond devices and methods for making such devices are provided. One such method may include depositing a semiconductor layer on a semiconductor substrate, depositing an adynamic diamond layer on the semiconductor layer opposite the semiconductor substrate, and coupling a support substrate to the adynamic diamond layer opposite the semiconductor layer to support the adynamic layer.08-08-2013
20130200395LAYOUT FOR MULTIPLE-FIN SRAM CELL - The present disclosure provides a static random access memory (SRAM) cell. The SRAM cell includes a plurality of fin active regions formed on a semiconductor substrate, wherein the plurality of fin active regions include a pair adjacent fin active regions having a first spacing and a fin active region having a second spacing from adjacent fin active regions, the second spacing being greater than the first spacing; a plurality of fin field-effect transistors (FinFETs) formed on the plurality of fin active regions, wherein the plurality of FinFETs are configured to a first and second inverters cross-coupled for data storage and at least one port for data access; a first contact disposed between the first and second the fin active regions, electrically contacting both of the first and second the fin active regions; and a second contact disposed on and electrically contacting the third fin active region.08-08-2013
20120299013SEMICONDUCTOR LIGHT EMITTING STRUCTURE - A semiconductor light emitting structure including a substrate, a patterned structure, a first semiconductor layer, an active layer and a second semiconductor layer is provided. The patterned structure is protruded from or indented into a surface of the substrate, so that the surface of the substrate becomes a roughed surface. The patterned structure has an asymmetrical geometric shape. The first semiconductor layer is disposed on the roughed surface. The active layer is disposed on the first semiconductor layer. The second semiconductor is disposed on the active layer.11-29-2012
20130207123HIGH CURRENT DENSITY POWER MODULE - A power module is disclosed that includes a housing with an interior chamber wherein multiple switch modules are mounted within the interior chamber. The switch modules comprise multiple transistors and diodes that are interconnected to facilitate switching power to a load. In one embodiment, at least one of the switch modules supports a current density of at least 10 amperes per cm08-15-2013
20130207124SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - A first region of a silicon carbide layer constitutes a first surface, and is of a first conductivity type. A second region is provided on the first region, and is of a second conductivity type. A third region is provided on the second region, and is of the first conductivity type. A fourth region is provided in the first region, located away from each of the first surface and the second region, and is of the second conductivity type. A gate insulation film is provided on the second region so as to connect the first region with the third region. A gate electrode is provided on the gate insulation film. A first electrode is provided on the first region. A second electrode is provided on the third region.08-15-2013
20130207122METHOD FOR FABRICATING FINFETS AND SEMICONDUCTOR STRUCTURE FABRICATED USING THE METHOD - A method for fabricating FinFETs is described. A semiconductor substrate is patterned to form odd fins. Spacers are formed on the substrate and on the sidewalls of the odd fins, wherein each spacer has a substantially vertical sidewall. Even fins are then formed on the substrate between the spacers. A semiconductor structure for forming FinFETs is also described, which is fabricated using the above method.08-15-2013