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SPECIFIED WIDE BAND GAP (1.5EV) SEMICONDUCTOR MATERIAL OTHER THAN GAASP OR GAALAS

Subclass of:

257 - Active solid-state devices (e.g., transistors, solid-state diodes)

Patent class list (only not empty are listed)

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Class / Patent application numberDescriptionNumber of patent applications / Date published
257077000 Diamond or silicon carbide 858
257078000 II-VI compound 4
20100084664ZINC SULFIDE SUBSTRATES FOR GROUP III-NITRIDE EPITAXY AND GROUP III-NITRIDE DEVICES - A semiconductor structure includes a substrate which may be formed from a ZnS single crystal of wurtzite (2H) structure with a predetermined crystal orientation, and which has a first surface and a second surface. The structure includes a layer of a group III-nitride crystalline material deposited as an epitaxial layer on the first surface of the substrate. In one embodiment, the group III-nitride deposit is epitaxially grown using a MOCVD (or MOVPE) technique or a HVPE technique or a combination thereof. There may be a mask and/or a buffer layer on the first surface and/or a protective layer on the second surface.04-08-2010
20110140128MONOCHROMATIC LIGHT SOURCE WITH HIGH ASPECT RATIO - Light emitting systems are disclosed. The light emitting system includes an LED that emits light at a first wave-length. A primary portion of the emitted first wavelength light exits the LED from a top surface of the LED that has a minimum lateral dimension Wmin. The remaining portion of the emitted first wavelength light exits the LED from one or more sides of the LED that has a maximum edge thickness Tmax (06-16-2011
20110140129LIGHT SOURCE WITH IMPROVED MONOCHROMATICITY - Light emitting systems are disclosed. The light emitting system includes an LED that emits light at a first wavelength and includes a pattern that enhances emission of light from a top surface of the LED and suppresses emission of light from one or more sides of the LED. The light emitting system further includes a re-emitting semiconductor construction that includes a II-VI potential well. The re-emitting semiconductor construction receives the first wavelength light that exits the LED and converts at least a portion of the received light to light of a second wavelength. The integrated emission intensity of all light at the second wavelength that exit the light emitting system is at least 4 times the integrated emission intensity of all light at the first wavelength that exit the light emitting system.06-16-2011
20110121319SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD OF MAKING SAME - Light emitting devices and methods of fabricating the same are disclosed. The light emitting device includes a light emitting diode (LED) that emits blue or UV light and is attached to a semiconductor construction. The semiconductor construction includes a re-emitting semiconductor construction that includes at least one layer of a II-VI compound and converts at least a portion of the emitted blue or UV light to longer wavelength light. The semiconductor construction further includes an etch-stop construction that includes an AlInAs or a GaInAs compound. The etch-stop is capable of withstanding an etchant that is capable of etching InP.05-26-2011
Entries
DocumentTitleDate
20110175105SEMICONDUCTOR LIGHT-EMITTING DEVICE AND FABRICATION METHOD THEREOF - A plurality of protrusions is formed on the C-plane substrate with a corundum structure. A base film made of a III-V compound semiconductor including Ga and N is formed on the surface of the substrate. The surface of the base film is flatter than the surface of the substrate. A light emitting structure including Ga and N is disposed on the base film. The protrusions are regularly arranged in a first direction that is tilted by less than 15 degrees with respect to the a-axis of the base film and in a second direction that is orthogonal to the first direction. Each protrusion has two first parallel sides tilted by less than 15 degrees relative to an m-axis and two second parallel sides tilted by less than 15 degrees relative to the a-axis. An interval between the two second sides is wider than an interval between the two first sides.07-21-2011
20080315210High electron mobility transistor - A GaN-based semiconductor layer is stacked on a GaN-based single-crystal substrate. The GaN-based single-crystal substrate forms an electron transit layer, and the GaN-based semiconductor layer forms an electron supply layer. A principal growth plane of the GaN-based single-crystal substrate is an m-plane, and a principal growth plane of the GaN-based semiconductor layer formed on the GaN-based single-crystal substrate is also an m-plane. With such a layer structure, no piezoelectric field is generated since the m-plane is a nonpolar plane. This suppresses generation of a two-dimensional electron gas layer at the time when no gate voltage is applied and consequently enables achievement of a normally-off configuration.12-25-2008
20130043488EPITAXIAL SUBSTRATE AND METHOD FOR MANUFACTURING EPITAXIAL SUBSTRATE - Provided is a crack-free epitaxial substrate having excellent breakdown voltage properties in which a silicon substrate is used as a base. The epitaxial substrate includes a (111) single crystal Si substrate and a buffer layer including a plurality of first lamination units. Each of those units includes a composition modulation layer formed of a first composition layer made of AlN and a second composition layer made of Al02-21-2013
20130043487LAYOUT DESIGN FOR A HIGH POWER, GaN-BASED FET - A FET includes a first and second set of finger arrays that each include a source, gate and drain. A first source pad is electrically coupled to source electrodes in the first set of finger arrays. A second source pad is electrically coupled to the source electrodes in the second set of finger arrays. A common drain pad is electrically coupled to drain electrodes in the first and second set of finger arrays. A first gate pad is electrically coupled to gate electrodes in the first set of finger arrays. A second gate pad is electrically coupled to gate electrodes in the second set of finger arrays. A substrate is also provided on which are disposed the first and second set of finger arrays, the first and second source pads, the common drain pad, and the first and second gate pads.02-21-2013
20130043486SYSTEM AND METHODS FOR PREPARING FREESTANDING FILMS USING LASER-ASSISTED CHEMICAL ETCH, AND FREESTANDING FILMS FORMED USING SAME - Systems and methods for preparing freestanding films using laser-assisted chemical etch (LACE), and freestanding films formed using same, are provided. In accordance with one aspect a substrate has a surface and a portion defining an isotropically defined cavity; and a substantially continuous film is disposed at the substrate surface and spans the isotropically defined cavity. In accordance with another aspect, a substrate has a surface and a portion defining an isotropically defined cavity; and a film is disposed at the substrate surface and spans the isotropically defined cavity, the film including at least one of hafnium oxide (HfO02-21-2013
20130043484HEMT WITH INTEGRATED LOW FORWARD BIAS DIODE - A high electron mobility transistor includes a source, gate and drain, a first III-V semiconductor region having a two-dimensional electron gas (2DEG) which provides a first conductive channel controllable by the gate between the source and drain, and a second III-V semiconductor region below the first III-V semiconductor region and having a second conductive channel connected to the source or drain and not controllable by the gate. The first and second III-V semiconductor regions are spaced apart from one another by a region of the high electron mobility transistor having a different band gap than the first and second III-V semiconductor regions.02-21-2013
20130043485GaN-BASED SEMICONDUCTOR DEVICE - A p-type GaN-based semiconductor device is provided. Porivded is a GaN-based semiconductor device including: a first channel layer which is formed from a GaN-based semiconductor, and in which a carrier gas of a first conductivity type occurs; a barrier layer formed on the first channel layer from a GaN-based semiconductor having a higher bandgap than the first channel layer; and a second channel layer which is formed on the barrier layer from a GaN-based semiconductor having a lower bandgap than the barrier layer, and in which a carrier gas of a second conductivity type occurs, wherein the carrier concentration of the carrier gas of the second conductivity type is lower in a region below a first gate electrode than in other regions between a first source electrode and a first drain electrode, and is controlled by the first gate electrode.02-21-2013
20130043481HIGH-VOLTAGE SOLID-STATE TRANSDUCERS AND ASSOCIATED SYSTEMS AND METHODS - High-voltage solid-state transducer (SST) devices and associated systems and methods are disclosed herein. An SST device in accordance with a particular embodiment of the present technology includes a carrier substrate, a first terminal, a second terminal and a plurality of SST dies connected in series between the first and second terminals. The individual SST dies can include a transducer structure having a p-n junction, a first contact and a second contact. The transducer structure forms a boundary between a first region and a second region with the carrier substrate being in the first region. The first and second terminals can be configured to receive an output voltage and each SST die can a forward junction voltage less than the output voltage.02-21-2013
20130043482HIGH LINEARITY BANDGAP ENGINEERED TRANSISTOR - A high linearity bandgap engineered transistor device is provided. In one example configuration, the device generally includes a substrate and an oxide layer formed on the substrate. The device further includes a wide-bandgap body material formed between a portion of the oxide layer and a gate dielectric layer. The wide-bandgap body material has an energy bandgap of 1.35 eV or higher and is lattice matched to the substrate. The device further includes a source-drain material formed on the oxide layer adjacent to the wide-bandgap body material so as to define a hetero-structure interface where the source-drain material contacts the wide-bandgap body material. The wide-bandgap body material is also lattice matched to the source-drain material. The device further includes a gate material formed over the gate dielectric layer. Other features and variations will be apparent in light of this disclosure.02-21-2013
20130043483HIGH LINEARITY HYBRID TRANSISTOR DEVICE - A hybrid transistor device is provided. In one example case, the device includes a substrate, an oxide layer formed on the substrate, and a wide-bandgap body material formed between a portion of the oxide layer and a gate dielectric layer. The wide-bandgap body material has an energy bandgap higher than that of silicon. The device includes source-drain/emitter material formed on the oxide layer adjacent to the wide-bandgap body material so as to define a hetero-structure interface where the source-drain/emitter material contacts the wide-bandgap body material. The device includes a gate material formed over the gate dielectric layer, a base material formed over a portion of the source-drain/emitter material, and a collector material formed over a portion of the base material. The source-drain/emitter material is shared so as to electrically combine a drain of a first transistor type portion of the device and an emitter of a second transistor type portion.02-21-2013
20110204378GROWTH OF GROUP III-V MATERIAL LAYERS BY SPATIALLY CONFINED EPITAXY - Techniques for crack-free growth of GaN, and related, films on larger-size substrates via spatially confined epitaxy are described.08-25-2011
20110204376GROWTH OF MULTI-JUNCTION LED FILM STACKS WITH MULTI-CHAMBERED EPITAXY SYSTEM - Apparatus and method for growth of non-p-type GaN layers over p-type GaN layers. Embodiments include multi-junction LED film stacks, multi-junction LED devices paired into units and multi-junction LED arrays of the paired units. Epitaxial growths of p-type and non-p-type material layers are split between epitaxial chambers clustered onto a single platform to reduce p-type dopant cross-contamination. Arrayed multi-junction LED devices provide improved packing density and reduced blinking during AC operation.08-25-2011
20100019248GALLIUM NITRIDE MATERIAL DEVICES INCLUDING CONDUCTIVE REGIONS AND METHODS ASSOCIATED WITH THE SAME - Semiconductor structures comprising a III-nitride (e.g., gallium nitride) material region and methods associated with such structures are provided. In some embodiments, the structures include an electrically conductive material (e.g., gold) separated from certain other region(s) of the structure (e.g., a silicon substrate) by a barrier material in order to limit, or prevent, undesirable reactions between the electrically conductive material and the other component(s) which can impair device performance. In certain embodiments, the electrically conductive material may be formed in a via. For example, the via can extend from a topside of the device to a backside so that the electrically conductive material connects a topside contact to a backside contact. The structures described herein may form the basis of a number of semiconductor devices including transistors (e.g., FET), Schottky diodes, light-emitting diodes and laser diodes, amongst others.01-28-2010
20120168769METHOD OF MANUFACTURING LIGHT EMITTING DIODE AND LIGHT EMITTING DIODE MANUFACTURED THEREBY - There is provided a method of manufacturing a light emitting diode and a light emitting diode manufactured by the same. The method includes growing a first conductivity type nitride semiconductor layer and an undoped nitride semiconductor layer on a substrate sequentially in a first reaction chamber; transferring the substrate having the first conductivity type nitride semiconductor layer and the undoped nitride semiconductor layer grown thereon to a second reaction chamber; growing an additional first conductivity type nitride semiconductor layer on the undoped nitride semiconductor layer in the second reaction chamber; growing an active layer on the additional first conductivity type nitride semiconductor layer; and growing a second conductivity type nitride semiconductor layer on the active layer.07-05-2012
20120168767SEMICONDUCTOR DEVICE - A semiconductor device includes a plurality of floating regions, an insulating layer and a capacitance forming portion. The plurality of floating regions are arranged on a surface of a semiconductor substrate in a row, wherein the plurality of floating regions are provided with insulating regions therebetween. The plurality of floating regions include a first floating region and a second floating region. The second floating region is located farther than the first floating region from an island region of a predetermined potential on the semiconductor substrate. The insulating layer is interposed between each of the plurality of floating regions and a semiconductor material layer of the semiconductor substrate. The capacitance forming portion forms an external capacitance in parallel with the capacitance of the insulating region between the first floating region and the island region of the predetermined potential.07-05-2012
20080258151LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - Disclosed are a light emitting device and a method for manufacturing the same. A light emitting diode comprises a plurality of Un-GaN layers and a plurality of N-type semiconductor layers, an active layer on the N-type semiconductor layer, and a P-type semiconductor layer on the active layer, wherein at least two of the Un-GaN layers and at least two of the N-type semiconductor layers are alternatively stacked on each other.10-23-2008
20080258150METHOD TO FABRICATE III-N FIELD EFFECT TRANSISTORS USING ION IMPLANTATION WITH REDUCED DOPANT ACTIVATION AND DAMAGE RECOVERY TEMPERATURE - Structures to reduce dopant activation temperatures for ion implantation in III-N transistors, using low aluminum content layers in proximity to the conducting channel, are disclosed. A method to increase the temperature at which structures can be annealed by annealing in an active nitrogen ambient, for example, in NH10-23-2008
20110193095SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A semiconductor device includes a GaN-based semiconductor layer formed on a substrate, a gate insulating film that is formed on a surface of the GaN-based semiconductor layer and is made of aluminum oxide, and a gate electrode formed on the gate insulating film, the gate insulating film having a carbon concentration of 2×1008-11-2011
20110193094GROWTH OF PLANAR REDUCED DISLOCATION DENSITY M-PLANE GALLIUM NITRIDE BY HYDRIDE VAPOR PHASE EPITAXY - A method of growing highly planar, fully transparent and specular m-plane gallium nitride (GaN) films. The method provides for a significant reduction in structural defect densities via a lateral overgrowth technique. High quality, uniform, thick m-plane GaN films are produced for use as substrates for polarization-free device growth.08-11-2011
20110193093LIGHT EMITTING DEVICE AND LIGHT EMITTING DEVICE PACKAGE - Provided is a light emitting device. A light emitting device includes: a conductive support member; a light emitting structure for generating a light on the conductive support member, the light emitting structure comprising a first conductive type semiconductor layer, a second conductive type semiconductor layer, and an active layer; an electrode on the light emitting structure; and an oxide layer between the electrode and the light emitting structure. The light emitting structure includes an oxygen-injected region where oxygen is injected on an upper portion of the light emitting structure.08-11-2011
20110193092FIELD EFFECT TRANSISTOR WITH CONDUCTION BAND ELECTRON CHANNEL AND UNI-TERMINAL RESPONSE - A uni-terminal transistor device is described. In one embodiment, an n-channel transistor comprises a first semiconductor layer having a discrete hole level H08-11-2011
20110193091DENSITY OF STATES ENGINEERED FIELD EFFECT TRANSISTOR - Layer structures for use in density of states (“DOS”) engineered FETs are described. One embodiment comprises a layer structure for use in fabricating an n-channel transistor. The layer structure includes a first semiconductor layer having a conduction band minimum E08-11-2011
20110193096COMPOUND SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - An n-type GaN layer (08-11-2011
20100148184GAN-BASED FIELD EFFECT TRANSISTOR - A GaN-based field effect transistor (MOSFET) is comprised of a channel layer comprised of p-type GaN, an electron supply layer, a surface layer having band gap energy smaller than that of said electron supply layer, sequentially laminated on a substrate, and recess section is formed by removing a part of the drift layer, the electron supply layer, and the surface layer down to a depth that reaches to the channel layer. A source electrode and a drain electrode are formed so that the recess section positions between them, a gate insulation film is formed on the surface layer and on inner-surface of the recess section including the channel layer, and a gate electrode is formed on the gate insulating film in the recess section.06-17-2010
20130037820NITROGEN COMPOUND SEMICONDUCTOR LIGHT EMITTING ELEMENT AND MANUFACTURING METHOD THEREOF - A nitrogen compound semiconductor light emitting element having an n-type layer, an active layer comprising AlGaInN and a p-type layer, emitting ultraviolet radiation with an emission peak wavelength of at most 400 nm and having a high emission intensity as well as a manufacturing method thereof are provided. In the nitrogen compound semiconductor light emitting element of the present invention having an n-type layer, an active layer and a p-type layer, the active layer consists of a nitrogen compound semiconductor layer with an emission peak wavelength of at most 400 nm comprising AlGaN, and the n-type layer has an n-type AlGaN layer comprising AlGaN and a GaN protective layer which does not contain Al and has a thickness of at least 5 nm. The active layer is formed on the protective layer. The manufacturing method comprises processes of growing the n-type AlGaN layer at a high substrate temperature of at least 1000° C.; growing the GaN protective layer of at most 400 nm not containing Al thereon; interrupting the growth process and decreasing the substrate temperature; and forming the active layer on the protective layer at a low substrate temperature of less than 1000° C.02-14-2013
20100163888MANUFACTURING PROCESS OF A POWER ELECTRONIC DEVICE INTEGRATED IN A SEMICONDUCTOR SUBSTRATE WITH WIDE BAND GAP AND ELECTRONIC DEVICE THUS OBTAINED - An embodiment of a process for manufacturing an electronic device on a semiconductor body of a material with wide forbidden bandgap having a first conductivity type. The process comprises the steps of: forming, on the semiconductor body, a first mask having a first window and a second window above a first surface portion and a second surface portion of the semiconductor body; forming, within the first and second surface portions of the semiconductor body underneath the first and second windows, at least one first conductive region and one second conductive region having a second conductivity type, the first conductive region and the second conductive region facing one another; forming a second mask on the semiconductor body, the second mask having a plurality of windows above surface portions of the first conductive region and the second conductive region; forming, within the first conductive region and the second conductive region and underneath the plurality of windows, a plurality of third conductive regions having the first conductivity type; removing completely the first and second masks; performing an activation thermal process of the first, second, and third conductive regions at a high temperature; and forming body and source regions.07-01-2010
20130037819LIGHT EMITTING DEVICE - Disclosed are a light emitting device, a method of manufacturing the light emitting device, a light emitting device package and a lighting system. The light emitting device includes a silicon substrate; a nitride buffer layer on the silicon substrate; and a gallium nitride epitaxial layer on the nitride buffer layer, wherein the nitride buffer layer includes a first nitride buffer layer having a first aluminum nitride layer on the silicon substrate and a first gallium nitride layer on the first aluminum nitride layer.02-14-2013
20120175629SEMICONDUCTOR EPITAXIAL STRUCTURE - A semiconductor epitaxial structure is provided. The semiconductor epitaxial structure includes a substrate, a doped semiconductor epitaxial layer, and a carbon nanotube layer. The doped semiconductor epitaxial layer is located on the substrate. The carbon nanotube layer is located between the substrate and the doped semiconductor epitaxial layer. The carbon nanotube layer can be a carbon nanotube film drawn from a carbon nanotube array and including a plurality of successive and oriented carbon nanotubes joined end-to-end by van der Waals attractive force therebetween.07-12-2012
20100117094GALLIUM NITRIDE EPITAXIAL CRYSTAL, METHOD FOR PRODUCTION THEREOF, AND FIELD EFFECT TRANSISTOR - The present invention provides a gallium nitride type epitaxial crystal, a method for producing the crystal, and a field effect transistor using the crystal. The gallium nitride type epitaxial crystal comprises a base substrate and the following (a) to (e), wherein a connection layer comprising a gallium nitride type crystal is arranged in an opening of the non-gallium nitride type insulating layer to electrically connect the first buffer layer and the p-conductive type semiconductor crystal layer. (a) a gate layer, (b) a high purity first buffer layer containing a channel layer contacting an interface on the base substrate side of the gate layer, (c) a second buffer layer arranged on the base substrate side of the first buffer layer, (d) a non-gallium nitride type insulating layer arranged on the base substrate side of the second buffer layer, and having the opening at a part thereof, and (e) a p-conductive type semiconductor crystal layer arranged on the base substrate side of the insulating layer.05-13-2010
20130075750SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor layer formed on a substrate; a second semiconductor layer formed on the first semiconductor layer; a third semiconductor layer formed on the second semiconductor layer; a gate electrode formed on the third semiconductor layer; and a source electrode and a drain electrode formed on the second semiconductor layer. The third semiconductor layer is formed with a semiconductor material doped with a p-type impurity element. In the third semiconductor layer, a p-type area is formed immediately below the gate electrode, and a high resistance area having a higher resistance than the p-type area is formed in an area other than the p-type area.03-28-2013
20130032820Optoelectronic Component and Method for Producing an Optoelectronic Component - The invention concerns an optoelectronic component (02-07-2013
20130032819SEMICONDUCTOR TRANSISTOR - The semiconductor transistor according the present invention includes an active layer composed of a GaN-based semiconductor and a gate insulating film formed on the active layer. The gate insulating film has a first insulating film including one or more compounds selected from the group consisting of Al02-07-2013
20130032818SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a buffer layer that is disposed over a substrate, a high-resistance layer that is disposed over the buffer layer, the high-resistance layer being doped with a transition metal for achieving high resistance, a low-resistance region that is disposed in a portion of the high-resistance layer or over the high-resistance layer, the low-resistance region being doped with an impurity element for achieving low resistance, an electron travel layer that is disposed over the high-resistance layer including the low-resistance region, an electron supply layer that is disposed over the electron travel layer, a gate electrode that is disposed over the electron supply layer, and a source electrode and a drain electrode that are disposed over the electron supply layer.02-07-2013
20130032814METHOD AND SYSTEM FOR FORMATION OF P-N JUNCTIONS IN GALLIUM NITRIDE BASED ELECTRONICS - A semiconductor device includes a III-nitride substrate having a first conductivity type and a first electrode electrically coupled to the III-nitride substrate. The semiconductor device also includes a III-nitride material having a second conductivity type coupled to the III-nitride substrate at a regrowth interface and a p-n junction disposed between the III-nitride substrate and the regrowth interface.02-07-2013
20130032817POWER AMPLIFIER - A power amplifier includes a semiconductor substrate including transistor cells, a drain electrode for the transistor cells located on the semiconductor substrate, a drain pad located on the semiconductor substrate and connected to the drain electrode, an ion-implanted resistance located in the semiconductor substrate and extending along and in contact with the drain pad, a floating electrode located on the semiconductor substrate and in contact with the ion-implanted resistance, and an output matching circuit located outside the semiconductor substrate. The power amplifier further includes a wire connecting the drain pad to the output matching circuit.02-07-2013
20130032813METHOD AND SYSTEM FOR DOPING CONTROL IN GALLIUM NITRIDE BASED DEVICES - A method of growing a III-nitride-based epitaxial structure includes providing a substrate in an epitaxial growth reactor and heating the substrate to a predetermined temperature. The method also includes flowing a gallium-containing gas into the epitaxial growth reactor and flowing a nitrogen-containing gas into the epitaxial growth reactor. The method further includes flowing a gettering gas into the epitaxial growth reactor. The predetermined temperature is greater than 1000° C.02-07-2013
20130032816HIGH ELECTRON MOBILITY TRANSISTORS AND METHODS OF MANUFACTURING THE SAME - High electron mobility transistors (HEMTs) including a substrate and a HEMT stack on the substrate, the HEMT stack including a compound semiconductor layer that includes a 2-dimensional electron gas (2DEG), an upper compound semiconductor layer that has a polarization index higher than a polarization index of the compound semiconductor layer, and a source electrode, a drain electrode, and a gate that are disposed on the upper compound semiconductor layer. The substrate may be a nitride substrate that has a dielectric constant and a thermal conductivity higher than a dielectric constant and a thermal conductivity of a silicon substrate. The substrate may include an insulating layer that has a dielectric constant and a thermal conductivity higher than a dielectric constant and a thermal conductivity of the silicon substrate, a metal layer that is deposited on the insulating layer, and a plate that is attached to the metal layer.02-07-2013
20130032815LIGHT EMITTING DIODE ARRAY AND METHOD FOR MANUFACTURING THE SAME - An LED array includes a substrate, protrusions formed on a top surface of the substrate, and LEDs formed on the top surface of the substrate and located at a top of the protrusions. The LEDs are electrically connected with each other. Each LED includes a connecting layer, an n-type GaN layer, an active layer, and a p-type GaN layer formed on a top of the protrusions in sequence. A bottom surface of the n-type GaN layer connecting the connecting layer has a roughened exposed portion. The bottom surface of the n-type GaN layer has an N-face polarity.02-07-2013
20130032812METHOD AND SYSTEM FOR A GAN VERTICAL JFET UTILIZING A REGROWN CHANNEL - A vertical III-nitride field effect transistor includes a drain comprising a first III-nitride material, a drain contact electrically coupled to the drain, and a drift region comprising a second III-nitride material coupled to the drain. The field effect transistor also includes a channel region comprising a third III-nitride material coupled to the drain and disposed adjacent to the drain along a vertical direction, a gate region at least partially surrounding the channel region, having a first surface coupled to the drift region and a second surface on a side of the gate region opposing the first surface, and a gate contact electrically coupled to the gate region. The field effect transistor further includes a source coupled to the channel region and a source contact electrically coupled to the source. The channel region is disposed between the drain and the source along the vertical direction such that current flow during operation of the vertical III-nitride field effect transistor is along the vertical direction, and the channel region extends along at least a portion of the second surface of the gate region.02-07-2013
20130032811METHOD AND SYSTEM FOR A GAN VERTICAL JFET UTILIZING A REGROWN GATE - A vertical III-nitride field effect transistor includes a drain comprising a first III-nitride material, a drain contact electrically coupled to the drain, and a drift region comprising a second III-nitride material coupled to the drain and disposed adjacent to the drain along a vertical direction. The field effect transistor also includes a channel region comprising a third III-nitride material coupled to the drift region, a gate region at least partially surrounding the channel region, and a gate contact electrically coupled to the gate region. The field effect transistor further includes a source coupled to the channel region and a source contact electrically coupled to the source. The channel region is disposed between the drain and the source along the vertical direction such that current flow during operation of the vertical III-nitride field effect transistor is along the vertical direction.02-07-2013
20130032810LED ON SILICON SUBSTRATE USING ZINC-SULFIDE AS BUFFER LAYER - A vertical GaN-based blue LED has an n-type GaN layer that was grown over a ZnS layer that in turn was grown directly on a silicon substrate. In one example, the ZnS layer is a transitional buffer layer that is 50 nm thick, and the n-type GaN layer is at least 2000 nm thick. Growing the n-type GaN layer on the ZnS buffer layer reduces lattice defect density in the n-type layer. The ZnS buffer layer provides a good lattice constant match with the silicon substrate and provides a compound polar template for subsequent GaN growth. After the epitaxial layers of the LED are formed, a conductive carrier is wafer bonded to the structure. The silicon substrate and the ZnS buffer layer are then removed. Electrodes are added and the structure is singulated to form finished LED devices.02-07-2013
20130075752SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes: a first semiconductor layer formed on a substrate; a second semiconductor layer formed on the first semiconductor layer; a third semiconductor layer formed on the second semiconductor layer; a gate electrode formed on the third semiconductor layer; and a source electrode and a drain electrode formed in contact with the second semiconductor layer, wherein a semiconductor material of the third semiconductor layer is doped with a p-type impurity element; and the third semiconductor layer has a jutting out region that juts out beyond an edge of the gate electrode toward a side where the drain electrode is provided.03-28-2013
20130075755LIGHT EMITTING DEVICE AND MANUFACTURING METHOD THEREOF - Provided are a light emitting device and a manufacturing method thereof. The light emitting device comprises a first conductive semiconductor layer with a lower surface being uneven in height, an active layer on the first conductive semiconductor layer, and a second conductive semiconductor layer on the active layer.03-28-2013
20130075754SEMICONDUCTOR DEVICE, FABRICATION METHOD OF THE SEMICONDUCTOR DEVICES - In a semiconductor device, a YAG substrate is formed as a single-crystal substrate of any of surface orientations (100), (110), and (111). In the fabrication of the semiconductor device, a TMAl gas is first fed onto the YAG substrate so as to form a nucleation layer made of aluminum, which is a group-III element. Then, an NH03-28-2013
20130075753SEMICONDUCTOR DEVICE - A semiconductor device includes: a substrate comprised of gallium nitride; an active layer provided on the substrate; a first buffer layer that is provided between the substrate and the active layer and is comprised of indium aluminum nitride (In03-28-2013
20130075751COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - An embodiment of a compound semiconductor device includes: a substrate; an electron channel layer and an electron supply layer formed over the substrate; a gate electrode, a source electrode and a drain electrode formed on or above the electron supply layer; a p-type semiconductor layer formed between the electron supply layer and the gate electrode; and a hole barrier layer formed between the electron supply layer and the p-type semiconductor layer, a band gap of the hole barrier layer being larger than that of the electron supply layer.03-28-2013
20130075748METHOD AND SYSTEM FOR DIFFUSION AND IMPLANTATION IN GALLIUM NITRIDE BASED DEVICES - A method of forming a doped region in a III-nitride substrate includes providing the III-nitride substrate and forming a masking layer having a predetermined pattern and coupled to a portion of the III-nitride substrate. The III-nitride substrate is characterized by a first conductivity type and the predetermined pattern defines exposed regions of the III-nitride substrate. The method also includes heating the III-nitride substrate to a predetermined temperature and placing a dual-precursor gas adjacent the exposed regions of the III-nitride substrate. The dual-precursor gas includes a nitrogen source and a dopant source. The method further includes maintaining the predetermined temperature for a predetermined time period, forming p-type III-nitride regions adjacent the exposed regions of the III-nitride substrate, and removing the masking layer.03-28-2013
20100032683GaN-BASED SEMICONDUCTOR ELEMENT - The GaN-based semiconductor element 02-11-2010
20130082279GROUP III-V SUBSTRATE MATERIAL WITH PARTICULAR CRYSTALLOGRAPHIC FEATURES - A substrate including a body comprising a Group III-V material and having an upper surface, the body comprising an offcut angle defined between the upper surface and a crystallographic reference plane, and the body further having an offcut angle variation of not greater than about 0.6 degrees.04-04-2013
20130082278NITRIDE SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME - A nitride semiconductor device and a method to produce the same are disclosed. The method includes steps of sequentially growing a channel layer and a first layer with bandgap energy Eg greater than that of channel layer; forming a gate replica on the first layer; selectively growing a second layer with Eg also greater than or equal to Eg of the channel layer; removing the gate replica to form a recess in the second layer; and forming the gate electrode in the recess and onto the first layer.04-04-2013
20130082274LIGHT EMITTING DEVICES HAVING DISLOCATION DENSITY MAINTAINING BUFFER LAYERS - A method for forming a light emitting device comprises forming a buffer layer having a plurality of layers comprising a substrate, an aluminum gallium nitride layer adjacent to the substrate, and a gallium nitride layer adjacent to the aluminum gallium nitride layer. During the formation of each of the plurality of layers, one or more process parameters are selected such that an individual layer of the plurality of layers is strained.04-04-2013
20130082273P-TYPE DOPING LAYERS FOR USE WITH LIGHT EMITTING DEVICES - A light emitting diode (LED) comprises an n-type Group III-V semiconductor layer, an active layer adjacent to the n-type Group III-V semiconductor layer, and a p-type Group III-V semiconductor layer adjacent to the active layer. The active layer includes one or more V-pits. A portion of the p-type Group III-V semiconductor layer is in the V-pits. A p-type dopant injection layer provided during the formation of the p-type Group III-V layer aids in providing a predetermined concentration, distribution and/or uniformity of the p-type dopant in the V-pits.04-04-2013
20130082275METHOD FOR GROWING CONFORMAL EPI LAYERS AND STRUCTURE THEREOF - A method for forming a conformal buffer layer of uniform thickness and a resulting semiconductor structure are disclosed. The conformal buffer layer is used to protect highly-doped extension regions during formation of an epitaxial layer that is used for inducing mechanical stress on the channel region of transistors.04-04-2013
20130082277NITRIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The present invention relates to a nitride semiconductor device and a manufacturing method thereof. According to one aspect of the present invention, a nitride semiconductor device including: a nitride semiconductor layer having a 2DEG channel; a source electrode in ohmic contact with the nitride semiconductor layer; a drain electrode in ohmic contact with the nitride semiconductor layer; a plurality of p-type nitride semiconductor segments formed on the nitride semiconductor layer and each formed lengthways from a first sidewall thereof, which is spaced apart from the source electrode, to a drain side; and a gate electrode formed to be close to the source electrode and in contact with the nitride semiconductor layer between the plurality of p-type semiconductor segments and portions of the p-type semiconductor segments extending in the direction of a source-side sidewall of the gate electrode aligned with the first sidewalls of the p-type nitride semiconductor segments is provided.04-04-2013
20130082276NITRIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The present invention relates to a nitride semiconductor device and a manufacturing method thereof. According to one aspect of the present invention, a nitride semiconductor device including: a nitride semiconductor layer having a 2DEG channel; a source electrode in ohmic contact with the nitride semiconductor layer; a drain electrode in ohmic contact with the nitride semiconductor layer; a p-type nitride layer formed on the nitride semiconductor layer between the source and drain electrodes; an n-type nitride layer formed on the p-type nitride layer; and a gate electrode formed between the source and drain electrodes to be close to the source electrode and in contact with the n-type nitride layer so that a source-side sidewall thereof is aligned with source-side sidewalls of the p-type and n-type nitride layers is provided. Further, a method of manufacturing a nitride semiconductor device is provided.04-04-2013
20130075749COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - An embodiment of a compound semiconductor device includes: a substrate; an electron channel layer and an electron supply layer formed over the substrate; a gate electrode, a source electrode and a drain electrode formed on or above the electron supply layer; a first p-type semiconductor layer formed between the electron supply layer and the gate electrode; and a second p-type semiconductor layer formed between the electron supply layer and at least one of the source electrode and the drain electrode. The one of the source electrode and the drain electrode on the second p-type semiconductor layer includes: a first metal film; and a second metal film Which contacts the first metal film on the gate electrode side of the first metal film, and a resistance of which is higher than that of the first metal film.03-28-2013
20120025202SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a silicon substrate; a buffer layer provided on the silicon substrate and has a band gap greater than GaN; a first GaN layer provided on the buffer layer; and a second GaN layer provided directly on the first GaN layer, a carbon concentration of the first GaN layer being higher than a carbon concentration of the second GaN layer.02-02-2012
20100044719III-V Compound Semiconductor Epitaxy Using Lateral Overgrowth - A circuit structure includes a substrate; a patterned mask layer over the substrate, wherein the patterned mask layer includes a plurality of gaps; and a group-III group-V (III-V) compound semiconductor layer. The III-V compound semiconductor layer includes a first portion over the mask layer and second portions in the gaps, wherein the III-V compound semiconductor layer overlies a buffer/nucleation layer.02-25-2010
20100102329LIGHT-EMITTING DEVICE HAVING LIGHT-EMITTING ELEMENTS WITH A SHARED ELECTRODE - A light-emitting device operating on a high drive voltage and a small drive current. LEDs (04-29-2010
20100109019FORMING METHOD OF GALLIUM NITRIDE SYSTEM COMPOUND SEMICONDUCTOR LAYER, TRANSFER METHOD OF THE SAME, AND SUBSTRATE STRUCTURE WITH THE SAME BONDED THERETO - A method includes: forming a first layer containing silicon oxide on a first substrate; partially removing the first layer to form an exposure portion on the first substrate; depositing amorphous gallium nitride system compound semiconductor on the first substrate with the exposure portion; evaporating the semiconductor on the first layer to form cores of the semiconductor on the exposure portion of the first substrate; forming an epitaxial layer of the semiconductor on the first substrate through increase in a size of the core, combination of the cores, crystal growth, formation of facets, bending of dislocation lines, transverse crystal growth onto the first layer, collision between adjoining crystal grains, combination of the transversely grown crystals, formation of dislocation networks, and formation of a flat surface of the semiconductor; and removing the epitaxial layer of the semiconductor on the exposure portion on the first substrate to form a separating groove.05-06-2010
20100109020Diode having vertical structure and method of manufacturing the same - A light emitting diode includes a conductive layer, an n-GaN layer on the conductive layer, an active layer on the n-GaN layer, a p-GaN layer on the active layer, and a p-electrode on the p-GaN layer. The conductive layer is an n-electrode.05-06-2010
20100109018METHOD OF FABRICATING SEMI-INSULATING GALLIUM NITRIDE USING AN ALUMINUM GALLIUM NITRIDE BLOCKING LAYER - A method for fabricating a single crystal, high quality, semi-insulating (SI) gallium nitride (GaN) layer using an Al05-06-2010
20100109017GaN-BASED COMPOUND SEMICONDUCTOR DEVICE - A gallium nitride (GaN)-based compound semiconductor device having a structure improving a surface characteristic of a thin film growing on a substrate is provided. The GaN-based compound semiconductor device includes an Al05-06-2010
20100109016POWER SEMICONDUCTOR MODULE - Provided is a power semiconductor module in which two components are bonded by a Bi based solder material. A Cu layer is provided on the surfaces thereof to be bonded by the Bi based solder material on the two-component. Two components, i.e., the components to be bonded, are a combination of a semiconductor element and an insulating part, or a combination of an insulating part and a radiator plate. The insulating part is composed of a Cu/SiNx/Cu laminated body.05-06-2010
20100109015GALLIUM NITRIDE SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME - An insulating layer, an undoped first GaN layer and an AlGaN layer are laminated in this order on a surface of a semiconductor substrate. A surface barrier layer formed by a two-dimensional electron gas is provided in an interface between the first GaN layer and the AlGaN layer. A recess (first recess) which reaches the first GaN layer but does not pierce the first GaN layer is formed in a surface layer of the AlGaN layer. A first high withstand voltage transistor and a control circuit are formed integrally on the aforementioned semiconductor substrate. The first high withstand voltage transistor is formed in the first recess and on a surface of the AlGaN layer. The control circuit includes an n-channel MOSFET formed in part of the first recess, and a depression type n-channel MOSFET formed on a surface of the AlGaN layer. In this manner, there are provided a gallium nitride semiconductor device which can be used under a high temperature environment while reduction in total circuit size can be attained, and a method for producing the gallium nitride semiconductor device.05-06-2010
20130026488EPITAXIAL SUBSTRATE AND METHOD FOR MANUFACTURING EPITAXIAL SUBSTRATE - Provided is a crack-free epitaxial substrate having excellent breakdown voltage properties in which a silicon substrate is used as a base substrate thereof. The epitaxial substrate includes: a (111) single crystal Si substrate and a buffer layer including a plurality of composition modulation layers each formed of a first composition layer made of AlN and a second composition layer made of Al01-31-2013
20130026487NITRIDE SEMICONDUCTOR LIGHT EMITTING ELEMENT - An object of the present invention is to provide a nitride semiconductor light emitting element having a novel transparent electrode. The nitride semiconductor light emitting element has the transparent electrode on a p-type nitride semiconductor layer, wherein the p-type nitride semiconductor layer and the transparent electrode can be in good ohmic contact to each other and wherein the variability of the forward voltage (Vf) within the wafer can be reduced.01-31-2013
20130026486EPITAXIAL SUBSTRATE AND METHOD FOR MANUFACTURING EPITAXIAL SUBSTRATE - Provided is a crack-free epitaxial substrate having excellent breakdown voltage properties in which a silicon substrate is used as a base substrate thereof. The epitaxial substrate includes: a (111) single crystal Si substrate and a buffer layer including a composition modulation layer that is formed of a first composition layer made of AlN and a second composition layer made of Al01-31-2013
20130026485POWER SEMICONDUCTOR DEVICE - A power semiconductor device is provided. The power semiconductor device includes a source electrode disposed on a device activation region and widened in a direction toward a first side, a drain electrode arranged alternately with the source electrode on the device activation region and widened in a direction toward a second side facing the first side, an insulating layer disposed on the source electrode and the drain electrode and configured to include a plurality of via contacts contacting the source electrode and the drain electrode, a source electrode pad disposed in a first region on the insulating layer to be brought into contact with the source electrode, and a drain electrode pad disposed in a second region separated from the first region on the insulating layer and brought into contact with the plurality of via contacts contacting the drain electrode.01-31-2013
20130026484Multi-Color Light Emitting Devices with Compositionally Graded Cladding Group III-Nitride Layers Grown on Substrates - A light emitting device includes a substrate, multiple n-type layers, and multiple p-type layers. The n-type layers and the p-type layers each include a group III nitride alloy. At least one of the n-type layers is a compositionally graded n-type group III nitride, and at least one of the p-type layers is a compositionally graded p-type group III nitride. A first ohmic contact for injecting current is formed on the substrate, and a second ohmic contact is formed on a surface of at least one of the p-type layers. Utilizing the disclosed structure and methods, a device capable of emitting light over a wide spectrum may be made without the use of phosphor materials.01-31-2013
20130026483Gallium and Nitrogen Containing Triangular or Diamond-Shaped Configuration for Optical Devices - A gallium and nitrogen containing optical device has a base region and no more than three major planar side regions configured in a triangular arrangement provided from the base region.01-31-2013
20130026482Boron-Containing Buffer Layer for Growing Gallium Nitride on Silicon - A silicon wafer used in manufacturing GaN for LEDs includes a silicon substrate, a buffer layer of boron aluminum nitride (B01-31-2013
20130026481TEXTURED OPTOELECTRONIC DEVICES AND ASSOCIATED METHODS OF MANUFACTURE - Textured optoelectronic devices and associated methods of manufacture are disclosed herein. In several embodiments, a method of manufacturing a solid state optoelectronic device can include forming a conductive transparent texturing material on a substrate. The method can further include forming a transparent conductive material on the texturing material. Upon heating the device, the texturing material causes the conductive material to grow a plurality of protuberances. The protuberances can improve current spreading and light extraction from the device.01-31-2013
20130026480Nucleation of Aluminum Nitride on a Silicon Substrate Using an Ammonia Preflow - A silicon wafer used in manufacturing crystalline GaN for light emitting diodes (LEDs) includes a silicon substrate, a buffer layer of aluminum nitride (AlN) and an upper layer of GaN. The silicon wafer has a diameter of at least 200 millimeters and an Si(111)1×1 surface. The AlN buffer layer overlies the Si(111) surface. The GaN upper layer is disposed above the buffer layer. Across the entire wafer substantially no aluminum atoms of the AlN are present in a bottom most plane of atoms of the AlN, and across the entire wafer substantially only nitrogen atoms of the AlN are present in the bottom most plane of atoms of the AlN. A method of making the AlN buffer layer includes preflowing a first amount of ammonia equaling less than 0.01% by volume of hydrogen flowing through a chamber before flowing trimethylaluminum and then a subsequent amount of ammonia through the chamber.01-31-2013
20120211764SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes: a support base material, and a semiconductor element bonded to the support base material with a binder, the binder including: a porous metal material that contacts the support base material and the semiconductor element, and a solder that is filled in at least one part of pores of the porous metal material.08-23-2012
20100065854GROWTH AND MANUFACTURE OF REDUCED DISLOCATION DENSITY AND FREE-STANDING ALUMINUM NITRIDE FILMS BY HYDRIDE VAPOR PHASE EPITAXY - A Group III-nitride semiconductor film containing aluminum, and methods for growing this film. A film is grown by patterning a substrate, and growing the Group III-nitride semi-conductor film containing aluminum on the substrate at a temperature designed to increase the mobility of aluminum atoms to increase a lateral growth rate of the Group III-nitride semiconductor film. The film optionally includes a substrate patterned with elevated stripes separated by trench regions, wherein the stripes have a height chosen to allow the Group III-nitride semiconductor film to coalesce prior to growth from the bottom of the trenches reaching the top of the stripes, the temperature being greater than 1075° C., the Group III-nitride semiconductor film being grown using hydride vapor phase epitaxy, the stripes being oriented along a (1-100) direction of the substrate or the growing film, and a dislocation density of the grown film being less than 1003-18-2010
20100065855METHOD OF MANUFACTURING GROUP-III NITRIDE SEMICONDUCTOR LIGHT EMITTING DEVICE, GROUP-III NITRIDE SEMICONDUCTOR LIGHT EMITTING DEVICE AND LAMP - The object of the present invention is to provide a method of manufacturing a Group-III nitride semiconductor light-emitting device that is highly productive and that enables production of a device having excellent light-emitting properties; a Group-III nitride semiconductor light-emitting device; and a lamp using the light emitting device. The present invention provides a method of manufacturing a Group-III nitride semiconductor light-emitting device, comprising the steps of: activating a gas including a Group-V element and a metal material with plasma, thereby reacting the gas with the metal material; forming on a substrate an intermediate layer that is made of a Group-III nitride compound; and stacking an n-type semiconductor layer that is made of a Group-III nitride semiconductor, a light-emitting layer, and a p-type semiconductor layer, sequentially on the intermediate layer, wherein the Group-V element is nitrogen, the gas fraction of nitrogen in the gas is within a range of more than 20% to less than 99% during forming of the intermediate layer, and the intermediate layer is formed into a single crystal structure.03-18-2010
20100001289PROCESS FOR PRODUCING AN EPITAXIAL LAYER OF GALIUM NITRIDE - A method of manufacturing a low defect density GaN material comprising at least two steps of growing epitaxial layers of GaN with differences in growing conditions, (a.) a first step of growing an epitaxial layer GaN on an epitaxially competent layer under first growing conditions selected to induce island features formation, followed by (b.) a second step of growing an epitaxial layer of GaN under second growing conditions selected to enhance lateral growth until coalescence.01-07-2010
20130087805SEMICONDUCTOR LIGHT EMITTING DEVICE - According to one embodiment, a semiconductor light emitting device includes an n-type semiconductor layer, a p-type semiconductor layer and a light emitting layer. The emitting layer is provided between the n-type layer and the p-type layer, and includes a plurality of barrier layers and a plurality of well layers, being alternately stacked. The p-side barrier layer being closest to the p-type layer among the plurality of barrier layer includes a first layer and a second layer, containing group III elements. An In composition ratio in the group III elements of the second layer is higher than an In composition ratio in the group III elements of the first layer. An average In composition ratio of the p-side layer is higher than an average In composition ratio of an n-side barrier layer that is closest to the n-type layer among the plurality of barrier layers.04-11-2013
20130087807EPITAXIAL GROWTH SUBSTRATE, SEMICONDUCTOR DEVICE, AND EPITAXIAL GROWTH METHOD - In heteroepitaxially growing a group-III nitride semiconductor on a Si single crystal substrate, the occurrence of cracks initiating in the wafer edge portion can be suppressed. Region A is an outermost peripheral portion outside the principal surface, being a bevel portion tapered. Regions B and C are on the same plane (the principal surface), region B (mirror-surface portion) being the center portion of the principal surface, and region C a region in the principal surface edge portion surrounding region B. The principal surface has a plane orientation, and in region B, is mirror-surface-finished. Region B occupies most of the principal surface of this Si single crystal substrate, and a semiconductor device is manufactured therein. Region C (surface-roughened portion) has a plane orientation as with region B, however, region B is mirror-surface-finished, whereas region C is surface-roughened.04-11-2013
20130087804SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME - A semiconductor structure includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and different from the first III-V compound layer in composition. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. A carrier channel depleting layer is disposed on the second III-V compound layer. The carrier channel depleting layer is deposited using plasma and a portion of the carrier channel depleting layer is under at least a portion of the gate electrode.04-11-2013
20130087806SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR LIGHT EMITTING DEVICE - According to one embodiment, a semiconductor light emitting device includes a first semiconductor layer, a light emitting unit, a second semiconductor layer, a reflecting electrode, an oxide layer and a nitrogen-containing layer. The first semiconductor layer is of a first conductivity type. The light emitting unit is provided on the first semiconductor layer. The second semiconductor layer is provided on the light emitting unit and is of a second conductivity type. The reflecting electrode is provided on the second semiconductor layer and includes Ag. The oxide layer is provided on the reflecting electrode. The oxide layer is insulative and has a first opening. The nitrogen-containing layer is provided on the oxide layer. The nitrogen-containing layer is insulative and has a second opening communicating with the first opening.04-11-2013
20130087803MONOLITHICALLY INTEGRATED HEMT AND SCHOTTKY DIODE - An integrated device including a III-nitride HEMT and a Schottky diode includes a substrate comprising a first III-nitride material and a drift region comprising a second III-nitride material coupled to the substrate and disposed adjacent to the substrate along a vertical direction. The integrated device also includes a first barrier layer coupled to the drift region and a channel layer comprising a third III-nitride material having a first bandgap and coupled to the barrier layer. The integrated device further includes a second barrier layer characterized by a second bandgap and coupled to the channel layer and a Schottky contact coupled to the drift region. The second bandgap is greater than the first bandgap.04-11-2013
20120181547HIGH VOLTAGE SWITCHING DEVICES AND PROCESS FOR FORMING SAME - The present invention relates to various switching device structures including Schottky diode, P-N diode, and P-I-N diode, which are characterized by low defect density, low crack density, low pit density and sufficient thickness (>2.5 um) GaN layers of low dopant concentration (<1E16 cm07-19-2012
20120181546LIGHT-EMITTING DIODE - A light-emitting diode includes a first electrode, a conductive substrate layer, a reflective layer, a first electrical semiconductor layer, a active layer, a second electrical semiconductor layer, and at least one second electrode. The conductive substrate layer is formed on the first electrode. The reflective layer is formed on the conductive substrate layer. The first electrical semiconductor layer is formed on the reflective layer. The active layer is formed on the first electrical semiconductor layer. The second electrical semiconductor layer is formed on the active layer. The at least one second electrode is formed on the second electrical semiconductor layer. At least one third electrode is additionally disposed under the second electrical semiconductor layer. At least one connection channel is disposed between the second electrode and the third electrode, so that the second electrode and the third electrode are electrically connected.07-19-2012
20090045410GaN SUBSTRATE AND SEMICONDUCTOR DEVICE PREPARED BY USING METHOD AND APPARATUS OF POLISHING GaN SUBSTRATE - In a polishing method of a GaN substrate according to this invention, first, while supplying a polishing solution 02-19-2009
20100327293FIELD-EFFECT TRANSISTOR AND METHOD FOR FABRICATING THE SAME - An AlN buffer layer, an undoped GaN layer, an undoped AlGaN layer, a p-type GaN layer and a heavily doped p-type GaN layer are formed in this order. A gate electrode forms an Ohmic contact with the heavily doped p-type GaN layer. A source electrode and a drain electrode are provided on the undoped AlGaN layer. A pn junction is formed in a gate region by a two dimensional electron gas generated at an interface between the undoped AlGaN layer and the undoped GaN layer and the p-type GaN layer, so that a gate voltage can be increased.12-30-2010
20130049007WIDE-BANDGAP SEMICONDUCTOR DEVICE - A wide-bandgap semiconductor device includes: a semiconductor substrate made of a semiconductor material having a bandgap larger than 1.42 eV; a semiconductor layer on the semiconductor substrate and made of a semiconductor material having a bandgap larger than 1.42 eV; and an active region in the semiconductor layer and including a transistor, wherein the wide-bandgap semiconductor device is opaque to light in a visible light wavelength range, from a wavelength of 360 nm to a wavelength of 830 nm.02-28-2013
20130049008LIGHT EMITTING DEVICE AND LIGHT EMITTING DEVICE PACKAGE - A light emitting device according to the embodiment includes a support substrate; a first light emitting structure disposed on the support substrate and including a first conductive type first semiconductor layer, a first active layer, and a second conductive type second semiconductor layer; a first reflective electrode under the first light emitting structure; a first metal layer around the first reflective electrode; a second light emitting structure disposed on the support substrate and including a first conductive type third semiconductor layer, a second active layer, and a second conductive type fourth semiconductor layer; a second reflective electrode under the second light emitting structure; a second metal layer around the second reflective electrode; and a contact part making contact with an inner portion of the first conductive type first semiconductor layer of the first light emitting structure and electrically connected to the second reflective electrode.02-28-2013
20130049010HIGH DENSITY GALLIUM NITRIDE DEVICES USING ISLAND TOPOLOGY - A Gallium Nitride (GaN) series of devices—transistors and diodes are disclosed—that have greatly superior current handling ability per unit area than previously described GaN devices. The improvement is due to improved layout topology. The devices also include a simpler and superior flip chip connection scheme and a means to reduce the thermal resistance. A simplified fabrication process is disclosed and the layout scheme which uses island electrodes rather than finger electrodes is shown to increase the active area density by two to five times that of conventional inter-digitated structures. Ultra low on resistance transistors and very low loss diodes can be built using the island topology. Specifically, the present disclosure provides a means to enhance cost/effective performance of all lateral GaN structures.02-28-2013
20130049009Substrate For Vertical Light-Emitting Diode - A multi-layer substrate for a vertical light-emitting diode (LED) includes a conductive and reflective base substrate and an n-type gallium nitride (GaN) layer formed on the base substrate.02-28-2013
20100133547Semiconductor Sensor - A semiconductor sensor determines physical and/or chemical properties of a medium, in particular a pH sensor. The semiconductor sensor has an electronic component with a sensitive surface, said component being constructed for its part on the basis of semiconductors with a large band gap (wide-gap semiconductor). The sensitive surface is provided at least in regions with a functional layer sequence which has an ion-sensitive surface. The functional layer sequence has at least one layer which is impermeable at least for the medium and/or the materials or ions to be determined.06-03-2010
20100133548METHODS FOR IMPROVING THE QUALITY OF EPITAXIALLY-GROWN SEMICONDUCTOR MATERIALS - The invention provides methods which can be applied during the epitaxial growth of two or more layers of semiconductor materials so that the qualities of successive layer are successively improved. In preferred embodiments, surface defects present in one epitaxial layer are capped with a masking material. A following layer is then grown so it extends laterally above the caps according to the known phenomena of epitaxial lateral overgrowth. The methods of the invention can be repeated by capping surface defects in the following layer and then epitaxially growing a second following layer according to ELO. The invention also includes semiconductor structures fabricated by these methods.06-03-2010
20100264425TRANSISTORS FOR REPLACING METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTORS IN NANOELECTRONICS - Junction field effect transistors (JFETs) are shown to be a viable replacement for metal oxide semiconductor field effect transistors (MOSFETs) for gate lengths of less than about 40 nm, providing an alternative to the gate leakage problems presented by scaled down MOSFETs. Integrated circuit designs can have complementary JFET (CJFET) logic cells substituted for existing MOSFET-based logic cells to produce revised integrated circuit designs. Integrated circuits can include JFETS where the channel comprises a wide bandgap semiconductor material and the gate comprises a narrow bandgap semiconductor material. Mixtures of JFET and MOSFET transistors can be included on an integrated circuit design.10-21-2010
20120217512LATERAL POWER TRANSISTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A lateral power transistor device comprises a substrate and a multi-layer mesa structure comprising a heterojunction. A filled trench region is located adjacent the multi-layer mesa structure, the filled trench region being occupied by a metal.08-30-2012
20120217511VERTICAL POWER TRANSISTOR DEVICE, SEMICONDUCTOR DIE AND METHOD OF MANUFACTURING A VERTICAL POWER TRANSISTOR DEVICE - A vertical power transistor device comprises: a substrate formed from a III-V semiconductor material and a multi-layer stack at least partially accommodated in the substrate. The multi-layer stack comprises: a semi-insulating layer disposed adjacent the substrate and a first layer formed from a first III-V semiconductor material and disposed adjacent the semi-insulating layer. The multi-layer stack also comprises a second layer formed from a second III-V semiconductor material disposed adjacent the first layer and a heterojunction is formed at an interface of the first and second layers.08-30-2012
20120217509LIGHT EMITTING DEVICE AND METHOD FOR FABRICATING THE SAME - A light-emitting device comprises a first conductive type semiconductor layer; a second conductive type semiconductor layer under the first conductive type semiconductor layer; an active layer between the first conductive type semiconductor layer and the second conductive type semiconductor layer; a nonconductive semiconductor layer on the first conductive type semiconductor layer and including a light extraction structure formed in the nonconductive semiconductor layer; a recess disposed from the nonconductive semiconductor layer to an upper portion of the first conductive type semiconductor layer; a first electrode layer on the upper portion of the first conductive type semiconductor layer; a second electrode layer under the second conductive type semiconductor layer.08-30-2012
20120217508Semiconductor White Light Sources - A semiconductor white light source includes a blue emitting semiconductor; a dispersant material disposed about the blue emitting semiconductor; an ultraviolet emitting semiconductor; and a wavelength shifting medium with maximum excitation in the ultraviolet spectrum disposed about the dispersant material and the ultraviolet emitting semiconductor such that ultraviolet light output by the ultraviolet emitting semiconductor illuminates the wavelength shifting medium directly and blue light output by the blue emitting semiconductor illuminates the wavelength shifting medium after passage of the blue light through the dispersant material. The dispersant material and the wavelength shifting medium are separate materials. The blue emitting semiconductor and the ultraviolet emitting semiconductor are arranged to emit light into a common illumination field.08-30-2012
20120217507SEMICONDUCTOR APPARATUS AND METHOD FOR MANUFACTURING SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes a substrate, a semiconductor layer formed above the substrate and including a nitride semiconductor, an electrode formed above the semiconductor layer and including gold, a barrier film formed above the electrode and a protection film formed above the semiconductor layer and including one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The protection film is formed on the barrier film. The barrier film includes a metal oxide material, a metal nitride film, or a metal oxynitride film.08-30-2012
20120217506III-Nitride Heterojunction Devices Having a Multilayer Spacer - In accordance with one implementation of the present disclosure, a III-Nitride heterojunction device includes a III-Nitride channel layer, a III-Nitride multilayer spacer situated over the III-Nitride channel layer, and a III-Nitride barrier layer situated over the III-Nitride multilayer spacer. A two-dimensional electron gas (2DEG) is formed near an interface of said III-Nitride Channel layer and said III-Nitride multilayer spacer. The III-Nitride multilayer spacer includes a III-Nitride interlayer. In one implementation, the III-Nitride multilayer spacer includes a III-Nitride polarization layer that is situated over the III-Nitride interlayer. The III-Nitride polarization layer has a higher total polarization than the III-Nitride interlayer, the III-Nitride channel layer, and the III-Nitride barrier layer.08-30-2012
20120217504NITRIDE BASED LIGHT EMITTING DEVICE USING SILICON SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - Disclosed is a nitride-based light emitting device using a silicon substrate. The nitride-based light emitting device includes a silicon (Si) substrate, a seed layer for nitride growth formed on the silicon substrate, and a light emitting structure formed on the seed layer and having a plurality of nitride layers stacked therein. The seed layer for nitride growth is comprised of GaN powders, thereby minimizing occurrence of dislocations caused by a difference in lattice constant between a nitride layer and the silicon substrate. A method of manufacturing the same is also disclosed.08-30-2012
20120217503METHOD OF MANUFACTURING GaN POWDER AND NITRIDE-BASED LIGHT EMITTING DEVICE USING GaN POWDER MANUFACTURED BY THE METHOD - Disclosed herein is a method of manufacturing GaN powders using a GaN etching product produced during manufacture of a GaN-based light emitting device. The method includes collecting a GaN etching product produced during etching of the GaN-based light emitting device, cleaning the collected GaN etching product; heating the cleaned GaN etching product to remove indium (In) components from the GaN etching product, and pulverizing the GaN etching product having the indium components removed therefrom into powders. A nitride-based light emitting device using the GaN powders is also disclosed.08-30-2012
20110006308SEMICONDUCTOR DEVICE - To obtain a device in which a buffer leak on a GaN substrate is reduced.01-13-2011
20110057200GROUP III NITRIDE SEMICONDUCTOR DEVICE, EPITAXIAL SUBSTRATE, AND METHOD OF FABRICATING GROUP III NITRIDE SEMICONDUCTOR DEVICE - A group III nitride semiconductor device having a gallium nitride based semiconductor film with an excellent surface morphology is provided. A group III nitride optical semiconductor device 03-10-2011
20130056749BROAD-AREA LIGHTING SYSTEMS - In accordance with certain embodiments, illumination systems are formed by aligning light-emitting elements with optical elements and/or disposing light-conversion materials on the light-emitting elements, as well as by providing electrical connectivity to the light-emitting elements03-07-2013
20130056745Buffer Layer for GaN-on-Si LED - A buffer layer of zinc telluride (ZnTe) or titanium dioxide (TiO03-07-2013
20130056748LIGHT EMITTING DEVICE AND LIGHT EMITTING DEVICE PACKAGE - A light emitting device includes a light emitting layer, a substrate that is transparent to an emission wavelength of the light emitting layer and positioned to receive an emission wavelength from the light emitting layer, a convex pattern including a collection of a plurality of convex portions discretely arranged on a front surface of the substrate with a first pitch, an n type nitride semiconductor layer located on the front surface of the substrate to cover the convex pattern and a p type nitride semiconductor layer located on the light emitting layer. The light emitting layer is located on the n type semiconductor layer. Each of the convex portions includes a sub convex pattern comprising a plurality of fine convex portions discretely formed at the top of the convex portion with a second pitch smaller than the first pitch, and a base supporting the sub convex pattern.03-07-2013
20130056751Method for Integrating MEMS Microswitches on Gan Substrates Comprising Electronic Power Components - Methods of fabrication of electronic modules comprise, on the one hand, power electronic components fabricated on a substrate made of gallium nitride (GaN) and, on the other hand, micro-switches using electrostatic activation of the MEMS (Micro Electro Mechanical System) type. The electronic components and the micro-switches are fabricated on a single gallium nitride substrate and the fabrication method comprises at least the following steps: fabrication of the power components on the gallium nitride substrate; deposition of a first common passivation layer on said components and on the substrate; fabrication of the micro-switches on said substrate.03-07-2013
20130056750NITRIDE BASED SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME AND BONDING SUBSTRATE - A nitride based semiconductor package includes a nitride based semiconductor device, a package substrate, and a bonding substrate. The semiconductor device includes, on a surface thereof, a first electrode pattern having a source electrode, a drain electrode and a gate electrode. The bonding substrate includes, on a first surface thereof, a second electrode pattern corresponding to the first electrode pattern, and at least one first groove pattern. The first groove pattern exposes the second electrode pattern. The first electrode pattern is received in the at least one first groove pattern. The second electrode pattern is bonded to the first electrode pattern received in the at least one first groove pattern. A second surface of the bonding substrate is bonded to the package substrate.03-07-2013
20130056747NITRIDE SEMICONDUCTOR LIGHT EMITTING DEVICE AND MANUFACTURING METHOD THEREOF - A nitride semiconductor light emitting device and a manufacturing method thereof are provided. The nitride semiconductor light emitting device includes: forming a first conductivity-type nitride semiconductor layer on a substrate; forming an active layer on the first conductivity-type nitride semiconductor layer; and forming a second conductivity-type nitride semiconductor layer on the active layer. High output can be obtained by increasing doping efficiency in growing the conductivity type nitride semiconductor layer.03-07-2013
20130056743METHOD AND SYSTEM FOR LOCAL CONTROL OF DEFECT DENSITY IN GALLIUM NITRIDE BASED ELECTRONICS - A diode includes a substrate characterized by a first dislocation density and a first conductivity type, a first contact coupled to the substrate, and a masking layer having a predetermined thickness and coupled to the semiconductor substrate. The masking layer comprises a plurality of continuous sections and a plurality of openings exposing the substrate and disposed between the continuous sections. The diode also includes an epitaxial layer greater than 5 μm thick coupled to the substrate and the masking layer. The epitaxial layer comprises a first set of regions overlying the plurality of openings and characterized by a second dislocation density and a second set of regions overlying the set of continuous sections and characterized by a third dislocation density less than the first dislocation density and the second dislocation density. The diode further includes a second contact coupled to the epitaxial layer.03-07-2013
20130056744Semiconductor Devices with Guard Rings - Semiconductor devices with guard rings are described. The semiconductor devices may be, e.g., transistors and diodes designed for high-voltage applications. A guard ring is a floating electrode formed of electrically conducting material above a semiconductor material layer. A portion of an insulating layer is between at least a portion of the guard ring and the semiconductor material layer. A guard ring may be located, for example, on a transistor between a gate and a drain electrode. A semiconductor device may have one or more guard rings.03-07-2013
20120112205SEMICONDUCTOR STRUCTURES AND DEVICES INCLUDING SEMICONDUCTOR MATERIAL ON A NON-GLASSY BONDING LAYER - Methods of fabricating semiconductor structures and devices include bonding a seed structure to a substrate using a glass. The seed structure may comprise a crystal of semiconductor material. Thermal treatment of the seed structure bonded to the substrate using the glass may be utilized to control a strain state within the seed structure. The seed structure may be placed in a state of compressive strain at room temperature. The seed structure bonded to the substrate using the glass may be used for growth of semiconductor material, or, in additional methods, a seed structure may be bonded to a first substrate using a glass, thermally treated to control a strain state within the seed structure and a second substrate may be bonded to an opposite side of the seed structure using a non-glassy material.05-10-2012
20120112204NITRIDE SEMICONDUCTOR LIGHT EMITTING DEVICE AND EPITAXIAL SUBSTRATE - For a nitride semiconductor light emitting device, a c-axis vector of hexagonal GaN of a support substrate is inclined to an X-axis direction with respect to a normal axis Nx normal to a primary surface. In a semiconductor region an active layer, a first gallium nitride-based semiconductor layer, an electron block layer, and a second gallium nitride-based semiconductor layer are arranged along the normal axis on the primary surface of the support substrate. A p-type cladding layer is comprised of AlGaN, and the electron block layer is comprised of AlGaN. The electron block layer is subject to tensile strain in the X-axis direction. The first gallium nitride-based semiconductor layer is subject to compressive strain in the X-axis direction. The misfit dislocation density at an interface is smaller than that at an interface. A barrier to electrons at the interface is raised by piezoelectric polarization.05-10-2012
20120112203GROUP-III NITRIDE SEMICONDUCTOR DEVICE, METHOD FOR FABRICATING GROUP-III NITRIDE SEMICONDUCTOR DEVICE, AND EPITAXIAL SUBSTRATE - Provided is a Group III nitride semiconductor device, which comprises an electrically conductive substrate including a primary surface comprised of a first gallium nitride based semiconductor, and a Group III nitride semiconductor region including a first p-type gallium nitride based semiconductor layer and provided on the primary surface. The primary surface of the substrate is inclined at an angle in the range of not less than 50 degrees, and less than 130 degrees from a plane perpendicular to a reference axis extending along the c-axis of the first gallium nitride based semiconductor, an oxygen concentration Noxg of the first p-type gallium nitride based semiconductor layer is not more than 5×1005-10-2012
20120112202E-Mode High Electron Mobility Transistors And Methods Of Manufacturing The Same - An Enhancement-mode (E-mode) high electron mobility transistor (HEMT) includes a channel layer with a 2-Dimensional Electron Gas (2DEG), a barrier layer inducing the 2DEG in the channel layer, source and drain electrodes on the barrier layer, a depletion layer on the barrier layer between the source and drain electrodes, and a gate electrode on the depletion layer. The barrier layer is recessed below the gate electrode and the depletion layer covers a surface of the recess and extends onto the barrier layer around the recess.05-10-2012
20120112201HIGH MELTING POINT SOLDERING LAYER AND FABRICATION METHOD FOR THE SAME, AND SEMICONDUCTOR DEVICE - A high melting point soldering layer includes a low melting point metal layer, a first high melting point metal layer disposed on a surface of the low melting point metal layer, and a second high melting point metal layer disposed at a back side of the low melting point metal layer. The low melting point metal layer, the first high melting point metal layer, and the second high melting point metal layer are mutually alloyed by transient liquid phase bonding, by annealing not less than a melting temperature of the low melting point metal layer, diffusing the metal of the low melting point metal layer into an alloy of the first high melting point metal layer and the second high melting point metal layer. The high melting point soldering layer has a higher melting point temperature than that of the low melting point metal layer. It is provided a binary based high melting point soldering layer having TLP bonding of a high melting point according to a low temperature processing, a fabrication method for the high melting point soldering layer and a semiconductor device to which the high melting point soldering layer is applied.05-10-2012
20120305935APPARATUS FOR PRODUCING METAL CHLORIDE GAS AND METHOD FOR PRODUCING METAL CHLORIDE GAS, AND APPARATUS FOR HYDRIDE VAPOR PHASE EPITAXY, NITRIDE SEMICONDUCTOR WAFER, NITRIDE SEMICONDUCTOR DEVICE, WAFER FOR NITRIDE SEMICONDUCTOR LIGHT EMITTING DIODE, METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR FREESTANIDNG SUBSTRATE AND NITRIDE SEMICONDUCTOR CRYSTAL - There is provided an apparatus for producing metal chloride gas, comprising: a source vessel configured to store a metal source; a gas supply port configured to supply chlorine-containing gas into the source vessel; a gas exhaust port configured to discharge metal chloride-containing gas containing metal chloride gas produced by a reaction between the chlorine-containing gas and the metal source, to outside of the source vessel; and a partition plate configured to form a gas passage continued to the gas exhaust port from the gas supply port by dividing a space in an upper part of the metal source in the source vessel, wherein the gas passage is formed in one route from the gas supply port to the gas exhaust port, with a horizontal passage width of the gas passage set to 5 cm or less, with bent portions provided on the gas passage.12-06-2012
20130056746SEMICONDUCTOR DEVICE - A semiconductor device includes: an electron-transit layer made of a semiconductor, the electron-transit layer having a first band gap; an electron-supply layer disposed on the electron-transit layer, the electron-supply layer being made of a semiconductor having a second band gap that is wider than the first band gap; a barrier-forming layer disposed on the electron-supply layer, the barrier-forming layer being made of a semiconductor having a third band gap that is narrower than the second band gap; an upper-channel layer disposed on the barrier-forming layer, the upper-channel layer being made of a semiconductor doped with an impurity; a side-surface of the barrier-forming layer and the upper-channel layer formed by partly removing the barrier-forming layer and the upper-channel layer; an insulating-film disposed on the side-surface; a gate-electrode disposed on the insulating-film; a source-electrode connected to the upper-channel layer; and a drain-electrode connected to the electron-supply layer or the electron-transit layer.03-07-2013
20120187412Gallium-Nitride-on-Handle Substrate Materials and Devices and Method of Manufacture - A gallium and nitrogen containing substrate structure includes a handle substrate member having a first surface and a second surface and a transferred thickness of gallium and nitrogen material. The structure has a gallium and nitrogen containing active region grown overlying the transferred thickness and a recessed region formed within a portion of the handle substrate member. The substrate structure has a conductive material formed within the recessed region configured to transfer thermal energy from at least the transferred thickness of gallium and nitrogen material.07-26-2012
20090294775HEXAGONAL WURTZITE TYPE EPITAXIAL LAYER POSSESSING A LOW ALKALI-METAL CONCENTRATION AND METHOD OF CREATING THE SAME - A method of obtaining a hexagonal würtzite type epitaxial layer with a low impurity concentration of alkali-metal by using a hexagonal würtzite substrate possessing a higher impurity concentration of alkali-metal, wherein a surface of the substrate upon which the epitaxial layer is grown has a crystal plane which is different from the c-plane.12-03-2009
20090294774MANUFACTURING METHOD OF GaN THIN FILM TEMPLATE SUBSTRATE, GaN THIN FILM TEMPLATE SUBSTRATE AND GaN THICK FILM SINGLE CRYSTAL - Provided are a manufacturing method of a GaN single crystal in which the film thickness of the GaN single crystal can be controlled accurately, even when a hydride vapor phase epitaxy is applied; a GaN thin film template substrate which is suitable for growing a GaN thick film with a fine property; and a GaN single crystal growing apparatus. Provided is a manufacturing method of a GaN single crystal by a hydride vapor phase epitaxy, wherein the hydride vapor phase epitaxy comprises: spraying HCl (hydrogen chloride) onto Ga (gallium) which is heated and fused in a predetermined temperature to generate GaCl (gallium chloride); and forming a GaN thin film by a reaction of the generated GaCl (gallium chloride) with NH12-03-2009
20090065787COMPOUND SEMICONDUCTOR STRUCTURE - A method for manufacturing a compound semiconductor structure, includes (a) selecting a conductive SiC substrate in accordance with color and resistivity and (b) epitaxially growing a GaN series compound semiconductor layer on the selected conductive SiC substrate. The step (a) preferably selects a conductive SiC substrate whose main color is green, whose conductivity type is n-type and whose resistivity is 0.08 Ωcm to 1×1003-12-2009
20090267079EXTERNALLY CONFIGURABLE INTEGRATED CIRCUITS - A die comprising two or more active electronic components is provided. The active electronic components are capable of being interconnected using interconnections external to the die. The die may be encased within a package, and the active electronic components may be interconnected using interconnections external to the package. By interconnecting the active electronic components, either directly or through one or more additional components, a desired circuit may be formed. In some examples, the desired circuit may be a monolithic microwave integrated circuit (MMIC). Methods of forming the circuit are also disclosed.10-29-2009
20130062616GaN-BASED FIELD EFFECT TRANSISTOR - A GaN-based field effect transistor (MOSFET) is comprised of a channel layer comprised of p-type GaN, an electron supply layer, a surface layer having band gap energy smaller than that of said electron supply layer, sequentially laminated on a substrate, and recess section is formed by removing a part of the drift layer, the electron supply layer, and the surface layer down to a depth that reaches to the channel layer. A source electrode and a drain electrode are formed so that the recess section positions between them, a gate insulation film is formed on the surface layer and on inner-surface of the recess section including the channel layer, and a gate electrode is formed on the gate insulating film in the recess section.03-14-2013
20130062618LIGHT EMITTING DIODE WITH THERMORADIATION HEAT-DISSIPATION LAYERS - A light emitting diode (LED) includes a sapphire substrate, a first thermoradiation heat-dissipation layer, a second thermoradiation heat-dissipation layer, an epitaxy light emitting structure, a first metal contact layer and a second metal contact layer. The first and second thermoradiation heat-dissipation layers are fabricated from a mixture of metal and nonmetal, and are fabricated on the upper and lower surfaces of the sapphire substrate, respectively. The heat generated by the epitaxy light emitting structure propagates through the first and second thermoradiation heat-dissipation layers by directive thermal radiation. The efficiency of heat dissipation is improved to increase the efficiency of light emitting and prolong the lifespan of LED and LED products.03-14-2013
20130062617LIGHT EMITTING DIODE STRUCTURE WITH TRANSPARENT CONDUCTIVE HEAT DISSIPATION FILM - An LED structure includes a sapphire substrate, an epitaxy light emitting structure, a transparent conductive heat dissipation film, a first metal contact layer and a second metal contact layer. The transparent conductive heat dissipation film is electrically conductive and thermally radiative, and has a surface microscopic crystalline structure. The heat generated by the epitaxy light emitting structure is propagated by thermal radiation in a direction from the upper surface to the lower surface of the transparent conductive heat dissipation film. The transparent conductive heat dissipation film successfully replaces the transparent ITO (indium tin oxide) film to provide similar optical and electrical feature and performs fast heat dissipation by directive thermal radiation. The heat dissipation and efficiency of light emitting are greatly improved so as to prolong the lifetime of LED and final LED products.03-14-2013
20130062615SOLID STATE LIGHTING DEVICES WITH SELECTED THERMAL EXPANSION AND/OR SURFACE CHARACTERISTICS, AND ASSOCIATED METHODS - Solid state lighting (SSL) devices and methods are disclosed. A particular method includes forming an SSL formation structure having a CTE, selecting a first material of an interlayer structure to have a first material CTE greater than the substrate CTE, and selecting a second material based at least in part on the second material having a CTE less than the first material CTE. The intelayer structure is formed over the SSL formation structure e.g., with a first layer of the first material over the SSL formation structure, a portion of the second material over the first material, and a second layer of the first material over the second material. The CTE difference between the first and second materials can counteract a force placed on the formation structure by the first material. Particular formation structures can have an off-cut angle with a non-zero value of up to about 4.5 degrees.03-14-2013
20130062614GROUP III-V ENHANCEMENT MODE TRANSISTOR WITH THYRISTOR GATE - An apparatus includes an enhancement mode transistor having multiple Group III-V layers above a substrate and a gate above the Group III-V layers. The gate includes multiple layers of material that form at least a portion of a thyristor. The multiple layers of material may include a first p-type layer of material, an n-type layer of material on the first p-type layer, and a second p-type layer of material on the n-type layer. The multiple layers of material may also include a p-type layer of material, an n-type layer of material on the p-type layer, and a Schottky metal layer on the n-type layer. The enhancement mode transistor may represent a high electron mobility transistor (HEMT) or a heterostructure field effect transistor (HFET).03-14-2013
20130062613LIGHT EMITTING DEVICE - According to one embodiment, a light emitting device includes a first lead, a light emitting element, a second lead and a molded body. The light emitting element is fixed on the first lead. The second lead is provided away from the first lead and electrically connected to the light emitting element via a metal wire. The, molded body made of a sealing resin covers the light emitting element, end portions of the first lead and the second lead, the light emitting element being fixed on the end portion of the first read, and the metal wire being bonded on the end portion of the second lead. The first groove is provided between first and second portions in a front surface of the second lead, the first portion being in contact with an outer edge of the molded body and the metal wire being bonded on the second portion.03-14-2013
20130062610LATTICE MATCHED CRYSTALLINE REFLECTOR - A virtual substrate structure with a lattice matched crystalline reflector for a light emitting device including a single crystal rare earth oxide layer deposited on a silicon substrate and substantially crystal lattice matched to the silicon substrate. A reflective layer of single crystal electrically conductive material is deposited on the layer of single crystal rare earth oxide and a layer of single crystal semiconductor material is positioned in overlying relationship to the reflective layer and substantially crystal lattice matched to the reflective layer. A single crystal rare earth oxide layer is optionally deposited between the reflective layer and the layer of semiconductor material.03-14-2013
20130062609III-N FET ON SILICON USING FIELD SUPPRESSING REO - A III-N on silicon substrate with enhanced breakdown voltage including a rare earth oxide structure deposited on the silicon substrate and a layer of single crystal III-N semiconductor material deposited on the rare earth oxide structure. The rare earth oxide has a dielectric constant greater (approximately twice) than the III-N semiconductor material. The rare earth oxide structure is selected to cooperate with the layer of single crystal III-N semiconductor material to reduce the thickness of the layer of single crystal III-N semiconductor material required for a selected breakdown voltage to a value less than a thickness of the layer of single crystal III-N semiconductor material for the selected breakdown voltage without the cooperating single crystal rare earth oxide.03-14-2013
20130062612NITRIDE SEMICONDUCTOR DEVICE, NITRIDE SEMICONDUCTOR WAFER, AND METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR LAYER - According to one embodiment, a nitride semiconductor device includes a foundation layer, a first stacked intermediate layer, and a functional layer. The foundation layer includes an AlN buffer layer formed on a substrate. The first stacked intermediate layer is provided on the foundation layer. The first stacked intermediate layer includes a first AlN intermediate layer provided on the foundation layer, a first AlGaN intermediate layer provided on the first AlN intermediate layer, and a first GaN intermediate layer provided on the first AlGaN intermediate layer. The functional layer is provided on the first stacked intermediate layer. The first AlGaN intermediate layer includes a first step layer in contact with the first AlN intermediate layer. An Al composition ratio in the first step layer decreases stepwise in a stacking direction from the first AlN intermediate layer toward the first step layer.03-14-2013
20130062611SEMICONDUCTOR DEVICE - A semiconductor device of an embodiment includes: a first semiconductor layer made of Al03-14-2013
20120223328GROUP III NITRIDE EPITAXIAL LAMINATE SUBSTRATE - A Group III nitride epitaxial laminate substrate comprising a substrate, a buffer and a main laminate in this order, wherein the buffer includes an initial growth layer, a first superlattice laminate and a second superlattice laminate in this order, the first superlattice laminate includes five to 20 sets of first AlN layers and second GaN layers, the first AlN layers and the second GaN layers being alternately stacked, and each one set of the first AlN layer and the second GaN layer has a thickness of less than 44 nm, the second superlattice laminate includes a plurality of sets of first layers made of an AlN material or an AlGaN material and second layers made of an AlGaN material having a different band gap from the first layers, the first and second layers being alternately stacked.09-06-2012
20120223327Programmable Gate III-Nitride Semiconductor Device - A III-nitride semiconductor device which includes a charged gate insulation body.09-06-2012
20120223325MICROELECRONIC ASSEMBLY WITH AN EMBEDDED WAVEGUIDE ADAPTER AND METHOD FOR FORMING THE SAME - A microelectronic assembly and a method for forming a microelectronic assembly are provided. A semiconductor substrate is provided. The semiconductor substrate has first and second opposing sides and first and second portions. A tuning depression is formed on the second opposing side and the second portion of the semiconductor substrate. A radio frequency conductor is formed on the first opposing side of the first semiconductor substrate. The radio frequency conductor has a first end on the first portion of the first semiconductor substrate and a second end on the second portion of the first semiconductor substrate. A microelectronic die having an integrated circuit formed therein is attached to the first opposing side and the first portion of the semiconductor substrate such that the integrated circuit is electrically connected to the first end of the radio frequency conductor.09-06-2012
20120223324LIGHT EMITTING DIODE AND METHOD FOR MANUFACTURING THE SAME - An LED includes a substrate, a first n-type GaN layer, a connecting layer, a second n-type GaN layer, a light emitting layer, and a p-type GaN layer. The first n-type GaN layer, the connecting layer, and the second n-type GaN layer are formed on the substrate in sequence. The connecting layer is etchable by alkaline solution, and a bottom surface of the second n-type GaN layer facing towards the connecting layer has a roughed exposed portion. The GaN on the bottom surface of the second n-type GaN layer is N-face GaN. A top surface of the second n-type GaN layer facing away from the connecting layer includes a first area and a second area. The light emitting layer and the p-type GaN layer are formed on the first area of the top surface of the second n-type GaN layer in sequence.09-06-2012
20120223323WAFER, CRYSTAL GROWTH METHOD, AND SEMICONDUCTOR DEVICE - According to one embodiment, a wafer includes a substrate, a base layer, a foundation layer, an intermediate layer and a functional unit. The substrate has a major surface. The base layer is provided on the major surface and includes a silicon compound. The foundation layer is provided on the base layer and includes GaN. The intermediate layer is provided on the foundation layer and includes a layer including AlN. The functional unit is provided on the intermediate layer and includes a nitride semiconductor. The foundation layer has a first region on a side of the base layer, and a second region on a side of the intermediate layer. A concentration of silicon atoms in the first region is higher than a concentration of silicon atoms in the second region. The foundation layer has a plurality of voids provided in the first region.09-06-2012
20120223322III-Nitride Transistor Stacked with Diode in a Package - One exemplary disclosed embodiment comprises a two-terminal stacked-die package including a diode, such as a silicon diode, stacked atop a III-nitride transistor, such that a cathode of the diode resides on and is electrically coupled to a source of the III-nitride transistor. A first terminal of the package is coupled to a drain of the III-nitride transistor, and a second terminal of the package is coupled to an anode of the diode. In this manner, devices such as cascoded rectifiers may be packaged in a stacked-die form, resulting in reduced parasitic inductance and resistance, improved thermal dissipation, smaller form factor, and lower manufacturing cost compared to conventional packages.09-06-2012
20120223321III-Nitride Transistor Stacked with FET in a Package - One exemplary disclosed embodiment comprises a three-terminal stacked-die package including a field effect transistor (FET), such as a silicon FET, stacked atop a III-nitride transistor, such that a drain of the FET resides on and is electrically coupled to a source of the III-nitride transistor. A first terminal of the package is coupled to a gate of the FET, a second terminal of the package is coupled to a drain of the III-nitride transistor. A third terminal of the package is coupled to a source of the FET. In this manner, devices such as cascoded switches may be packaged in a stacked-die form, resulting in reduced parasitic inductance and resistance, improved thermal dissipation, smaller form factor, and lower manufacturing cost compared to conventional packages.09-06-2012
20120223320ELECTRODE CONFIGURATIONS FOR SEMICONDUCTOR DEVICES - A III-N semiconductor device can include an electrode-defining layer having a thickness on a surface of a III-N material structure. The electrode-defining layer has a recess with a sidewall, the sidewall comprising a plurality of steps. A portion of the recess distal from the III-N material structure has a first width, and a portion of the recess proximal to the III-N material structure has a second width, the first width being larger than the second width. An electrode is in the recess, the electrode including an extending portion over the sidewall of the recess. A portion of the electrode-defining layer is between the extending portion and the III-N material structure. The sidewall forms an effective angle of about 40 degrees or less relative to the surface of the III-N material structure.09-06-2012
20120223319SEMICONDUCTOR DIODES WITH LOW REVERSE BIAS CURRENTS - A diode is described with a III-N material structure, an electrically conductive channel in the III-N material structure, two terminals, wherein a first terminal is an anode adjacent to the III-N material structure and a second terminal is a cathode in ohmic contact with the electrically conductive channel, and a dielectric layer over at least a portion of the anode. The anode comprises a first metal layer adjacent to the III-N material structure, a second metal layer, and an intermediary electrically conductive structure between the first metal layer and the second metal layer. The intermediary electrically conductive structure reduces a shift in an on-voltage or reduces a shift in reverse bias current of the diode resulting from the inclusion of the dielectric layer. The diode can be a high voltage device and can have low reverse bias currents.09-06-2012
20120223318P-CHANNEL FLASH WITH ENHANCED BAND-TO-BAND TUNNELING HOT ELECTRON INJECTION - A p-channel flash memory is formed with a charge storage stack embedded in a hetero-junction layer in which a raised source/drain is formed. Embodiments include forming a dummy gate stack on a substrate, forming a layer on the substrate by selective epitaxial growth, on each side of the dummy gate stack, forming spacers on the layer, forming raised source/drains, removing the dummy gate stack, forming a cavity between the spacers, and forming a memory gate stack in the cavity. Different embodiments include forming the layer of a narrow bandgap material, a narrow bandgap layer under the spacers and a wide bandgap layer adjacent thereto, or a wide bandgap layer under the spacers, a narrow bandgap layer adjacent thereto, and a wide bandgap layer on the narrow bandgap layer.09-06-2012
20120223317OHMIC CONTACT SCHEMES FOR GROUP III-V DEVICES HAVING A TWO-DIMENSIONAL ELECTRON GAS LAYER - A semiconductor device includes a first layer and a second layer over the first layer. The first and second layers are configured to form an electron gas layer at an interface of the first and second layers. The semiconductor device also includes an Ohmic contact and multiple conductive vias through the second layer. The conductive vias are configured to electrically couple the Ohmic contact to the electron gas layer. The conductive vias could have substantially vertical sidewalls or substantially sloped sidewalls, or the conductive vias could form a nano-textured surface on the Ohmic contact. The first layer could include Group III-nitride nucleation, buffer, and channel layers, and the second layer could include a Group III-nitride barrier layer.09-06-2012
20110012128METHOD FOR MANUFACTURING A LAYER OF GALLIUM NITRIDE OR GALLIUM AND ALUMINUM NITRIDE - The present invention relates to a method for manufacturing a crack free monocrystalline nitride layer having the composition Al01-20-2011
20110012127GaN CRYSTAL SUBSTRATE AND METHOD OF MANUFACTURING THE SAME, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - In a GaN crystal substrate, a rear surface opposite to a crystal growth surface can have a warpage w01-20-2011
20110012126NITRIDE-BASED SEMICONDUCTOR LIGHT EMITTING DEVICE - An object is to provide a nitride-based semiconductor light emitting device capable of preventing a Schottky barrier from being formed at an interface between a contact layer and an electrode. LD 01-20-2011
20130214281METHOD OF GROWING A HIGH QUALITY III-V COMPOUND LAYER ON A SILICON SUBSTRATE - The present disclosure involves a method of fabricating a semiconductor device. A surface of a silicon wafer is cleaned. A first buffer layer is then epitaxially grown on the silicon wafer. The first buffer layer contains an aluminum nitride (AlN) material. A second buffer layer is then epitaxially grown on the first buffer layer. The second buffer layer includes a plurality of aluminum gallium nitride (Al08-22-2013
20130214282III-N ON SILICON USING NANO STRUCTURED INTERFACE LAYER - A method of fabricating a layer of single crystal semiconductor material on a silicon substrate including providing a crystalline silicon substrate and epitaxially depositing a nano structured interface layer on the substrate. The nano structured interface layer has a thickness up to a critical thickness. The method further includes epitaxially depositing a layer of single crystal semiconductor material in overlying relationship to the nano structured interface layer. Preferably, the method includes the nano structured interface layer being a layer of coherently strained nano dots of selected material. The critical thickness of the nano dots includes a thickness up to a thickness at which the nano dots become incoherent.08-22-2013
20130069079Method of Producing Template for Epitaxial Growth and Nitride Semiconductor Device - A surface of a sapphire (0001) substrate is processed so as to have recesses and protrusions so that protrusion tops are made flat and have a given plan-view pattern. An initial-stage AlN layer is epitaxially grown on the surface of the sapphire (0001) substrate so that new recesses are formed over the recesses, by performing C axis orientation control so that a C+ axis oriented AlN layer grows on flat surfaces of the protrusion tops, excluding edges. A first ELO layer including an AlN (0001) layer is epitaxially grown on the initial-stage AlN layer by an epitaxial lateral overgrowth method, and stops growing before a recess upper region above the new recesses is completely covered with the first ELO layer that is laterally grown from a protrusion upper surface of the initial-stage AlN layer. A second ELO layer including an Al03-21-2013
20130069078CRYSTAL PRODUCING APPARATUS, CRYSTAL PRODUCING METHOD, SUBSTRATE PRODUCING METHOD, GALLIUM NITRIDE CRYSTAL, AND GALLIUM NITRIDE SUBSTRATE - A crystal producing apparatus includes a crystal forming unit and a crystal growing unit. The crystal forming unit forms a first gallium nitride (GaN) crystal by supplying nitride gas into melt mixture containing metal sodium (Na) and metal gallium (Ga). The first GaN crystal is sliced and polished to form GaN wafers. The crystal growing unit grows a second GaN crystal on a substrate formed by using a GaN wafer, by the hydride vapor phase epitaxy method, thus producing a bulked GaN crystal.03-21-2013
20130069077White Organic Light Emitting Device - Disclosed white organic light emitting device includes an anode and a cathode opposing each other; a charge generation layer interposed between the anode and the cathode; a first stack interposed between the anode and the charge generation layer, the first stack including a first hole transport layer and a first light emitting layer emitting blue fluorescent light; and a second stack interposed between the charge generation layer and the cathode, the second stack including a second hole transport layer and a second light emitting layer formed by doping one host with at least one of phosphorescent dopant, wherein a triplet energy level of the first hole transport layer is higher than a triplet energy level of the first light emitting layer, and a hole mobility of the first hole transport layer is 5.0×1003-21-2013
20130069076NITRIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR THE SAME - Provided is a nitride semiconductor device comprising a base substrate; a buffer layer formed above the base substrate; an active layer formed on the buffer layer; and at least two electrodes formed above the active layer. The buffer layer includes one or more composite layers that each have a plurality of nitride semiconductor layers with different lattice constants, and at least one of the one or more composite layers is doped with carbon atoms and oxygen atoms in at least a portion of a carrier region of the nitride semiconductor having the largest lattice constant among the plurality of nitride semiconductor layers, the carrier region being a region in which carriers are generated due to the difference in lattice constants between this nitride semiconductor layer and the nitride semiconductor layer formed directly thereon.03-21-2013
20130069075NITRIDE SEMICONDUCTOR CRYSTAL PRODUCING METHOD, NITRIDE SEMICONDUCTOR EPITAXIAL WAFER, AND NITRIDE SEMICONDUCTOR FREESTANDING SUBSTRATE - A nitride semiconductor crystal producing method, a nitride semiconductor epitaxial wafer, and a nitride semiconductor freestanding substrate, by which it is possible to suppress the occurrence of cracking in the nitride semiconductor crystal and to ensure the enhancement of the yield of the nitride semiconductor crystal. The nitride semiconductor crystal producing method includes growing a nitride semiconductor crystal over a seed crystal substrate, while applying an etching action to an outer end of the seed crystal substrate during the growing of the nitride semiconductor crystal.03-21-2013
20130069074POWER DEVICE AND METHOD OF MANUFACTURING THE SAME - According to an example embodiment, a power device includes a substrate, a nitride-containing stack on the substrate, and an electric field dispersion unit. Source, drain, and gate electrodes are on the nitride-containing stack. The nitride-containing stack includes a first region that is configured to generate a larger electric field than that of a second region of the nitride-containing stack. The electric field dispersion unit may be between the substrate and the first region of the nitride-containing stack.03-21-2013
20130069073White Organic Light Emitting Device - The white organic light emitting device for improved efficiencies includes an anode and a cathode opposing each other on a substrate, a charge generation layer between the anode and the cathode, a first stack and a second stack interposed between the anode and the charge generation layer, and between the charge generation layer and the cathode, respectively, wherein at least one of a first hole transport layer and a second hole transport layer has a triplet energy level higher than a triplet energy level of the light emitting layer adjacent thereto, and a difference between a triplet energy level and a singlet energy level of 0.01 eV to 0.6 eV.03-21-2013
20130069072SEMICONDUCTOR CRYSTAL SUBSTRATE, MANUFACTURING METHOD OF SEMICONDUCTOR CRYSTAL SUBSTRATE, MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE, POWER UNIT, AND AMPLIFIER - A semiconductor crystal substrate includes a substrate; and a protection layer formed by applying nitride on a surface of the substrate. The protection layer is in an amorphous state in a peripheral area at an outer peripheral part of the substrate, and the protection layer is crystallized in an internal area of the protection layer that is inside the peripheral area of the protection layer.03-21-2013
20130069071SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - Compression strains are generated at an interface between the cap layer and the barrier layer and an interface between the channel layer and the buffer layer and a tensile strain is generated at an interface between the barrier layer and the channel layer. Therefore, negative charge is higher than positive charge at the interface between the cap layer and the barrier layer and the interface between the channel layer and the buffer layer, while positive charge is higher than negative charge at the interface between the barrier layer and the channel. The channel layer has a stacked layer structure of a first layer, a second layer, and a third layer. The second layer has a higher electron affinity than those of the first layer and the third layer.03-21-2013
20090008648GALLIUM NITRIDE-BASED SEMICONDUCTOR ELEMENT, OPTICAL DEVICE USING THE SAME, AND IMAGE DISPLAY APPARATUS USING OPTICAL DEVICE - A GaN-based semiconductor element which can suppress a leakage current generated during reverse bias application, an optical device using the same, and an image display apparatus using the optical device are provided. The GaN-based semiconductor element has a first GaN-based compound layer including an n-type conductive layer; a second GaN-based compound layer including a p-type conductive layer; and an active layer provided between the first GaN-based compound layer and the second GaN-based compound layer. In this GaN-based semiconductor element, the first GaN-based compound layer includes an underlayer having an n-type impurity concentration in the range of 3×1001-08-2009
20090008647Gallium nitride-on-silicon interface using multiple aluminum compound buffer layers - A thermal expansion interface between silicon (Si) and gallium nitride (GaN) films using multiple buffer layers of aluminum compounds has been provided, along with an associated fabrication method. The method provides a (111) Si substrate and deposits a first layer of AlN overlying the substrate by heating the substrate to a relatively high temperature of 1000 to 1200° C. A second layer of AlN is deposited overlying the first layer of AlN at a lower temperature of 500 to 800° C. A third layer of AlN is deposited overlying the second layer of AlN by heating the substrate to the higher temperature range. Then, a grading Al01-08-2009
20130161640NITRIDE SEMICONDUCTOR DEVICE - A nitride semiconductor device is provided that prevents development of cracks, that has nitride semiconductor thin films with uniform thicknesses and good growth surface flatness, and is thus consistent in characteristics, and that can be fabricated at a satisfactory yield. In this nitride semiconductor device, the nitride semiconductor thin films are grown on a substrate having an off-angle between a direction normal to the surface of ridges and the crystal direction <0001>. This helps either reduce or intentionally promote diffusion or movement of the atoms or molecules of a source material of the nitride semiconductor thin films through migration thereof. As a result, a nitride semiconductor growth layer with good surface flatness can be formed, and thus a nitride semiconductor device with satisfactory characteristics can be obtained.06-27-2013
20120235161GROUP III NITRIDE TEMPLATES AND RELATED HETEROSTRUCTURES, DEVICES, AND METHODS FOR MAKING THEM - A templated substrate includes a base layer, and a template layer is disposed on the base layer and having a composition including a single-crystal Group III nitride. The template layer includes a continuous sublayer on the base layer and a nanocolumnar sublayer on the first sublayer, wherein the nanocolumnar sublayer includes a plurality of nano-scale columns.09-20-2012
20120235160Normally-Off Semiconductor Devices - Normally-off semiconductor devices are provided. A Group III-nitride buffer layer is provided. A Group III-nitride barrier layer is provided on the Group III-nitride buffer layer. A non-conducting spacer layer is provided on the Group III-nitride barrier layer. The Group III-nitride barrier layer and the spacer layer are etched to form a trench. The trench extends through the barrier layer and exposes a portion of the buffer layer. A dielectric layer is formed on the spacer layer and in the trench and a gate electrode is formed on the dielectric layer. Related methods of forming semiconductor devices are also provided herein.09-20-2012
20120235158LIGHT EMITTING DEVICE HAVING A PLURALITY OF NON-POLAR LIGHT EMITTING CELLS AND A METHOD OF FABRICATING THE SAME - The present invention relates to a light emitting device having a plurality of non-polar light emitting cells and a method of fabricating the same. Nitride semiconductor layers are disposed on a Gallium Nitride substrate having an upper surface. The upper surface is a non-polar or semi-polar crystal and forms an intersection angle with respect to a c-plane. The nitride semiconductor layers may be patterned to form light emitting cells separated from one another. When patterning the light emitting cells, the substrate may be partially removed in separation regions between the light emitting cells to form recess regions. The recess regions are filled with an insulating layer, and the substrate is at least partially removed by using the insulating layer.09-20-2012
20120235157LIGHT EMITTING DIODE AND METHOD FOR MANUFACTURING THE SAME - An LED includes a substrate, a first n-type GaN layer, a connecting layer, a second n-type GaN layer, a light emitting layer, and a p-type GaN layer formed on the substrate in sequence, the connecting layer being etchable by alkaline solution, a bottom surface of the second n-type GaN layer facing towards the connecting layer having a roughened exposed portion, the GaN on the bottom surface of the second n-type GaN layer having an N-face polarity, a blind hole extending through the p-type GaN layer, the light emitting layer and the second n-type GaN layer to expose the connecting layer, and an annular rough portion formed on the bottom surface of the second n-type GaN layer and surrounding each blind hole.09-20-2012
20120235156NITRIDE SEMICONDUCTOR DEVICE - According to one embodiment, a nitride semiconductor device includes a semiconductor layer, a source electrode, a drain electrode, a first and a second gate electrode. The semiconductor layer includes a nitride semiconductor. The source electrode provided on a major surface of the layer forms ohmic contact with the layer. The drain electrode provided on the major surface forms ohmic contact with the layer and is separated from the source electrode. The first gate electrode is provided on the major surface between the source and drain electrodes. The second gate electrode is provided on the major surface between the source and first gate electrodes. When a potential difference between the source and first gate electrodes is 0 volts, a portion of the layer under the first gate electrode is conductive. The first gate electrode is configured to switch a constant current according to a voltage applied to the second gate electrode.09-20-2012
20130161633METHOD AND SYSTEM FOR JUNCTION TERMINATION IN GAN MATERIALS USING CONDUCTIVITY MODULATION - A semiconductor structure includes a GaN substrate having a first surface and a second surface opposing the first surface. The GaN substrate is characterized by a first conductivity type and a first dopant concentration. The semiconductor structure also includes a first GaN epitaxial layer of the first conductivity type coupled to the second surface of the GaN substrate and a second GaN epitaxial layer of a second conductivity type coupled to the first GaN epitaxial layer. The second GaN epitaxial layer includes an active device region, a first junction termination region characterized by an implantation region having a first implantation profile, and a second junction termination region characterized by an implantation region having a second implantation profile.06-27-2013
20130161634METHOD AND SYSTEM FOR FABRICATING EDGE TERMINATION STRUCTURES IN GAN MATERIALS - A method for fabricating an edge termination, which can be used in conjunction with GaN-based materials, includes providing a substrate of a first conductivity type. The substrate has a first surface and a second surface. The method also includes forming a first GaN epitaxial layer of the first conductivity type coupled to the first surface of the substrate and forming a second GaN epitaxial layer of a second conductivity type opposite to the first conductivity type. The second GaN epitaxial layer is coupled to the first GaN epitaxial layer. The substrate, the first GaN epitaxial layer and the second GaN epitaxial layer can be referred to as an epitaxial structure.06-27-2013
20130161635METHOD AND SYSTEM FOR A GAN SELF-ALIGNED VERTICAL MESFET - A semiconductor structure includes a III-nitride substrate and a drift region coupled to the III-nitride substrate along a growth direction. The semiconductor substrate also includes a channel region coupled to the drift region. The channel region is defined by a channel sidewall disposed substantially along the growth direction. The semiconductor substrate further includes a gate region disposed laterally with respect to the channel region.06-27-2013
20130161636METHODS OF FABRICATING SEMICONDUCTOR STRUCTURES USING THERMAL SPRAY PROCESSES, AND SEMICONDUCTOR STRUCTURES FABRICATED USING SUCH METHODS - Methods for fabricating a semiconductor substrate include forming a first substrate layer over a surface of a first semiconductor layer, and thermally spraying a second substrate layer on a side of the first substrate layer opposite the first semiconductor layer. At least one additional semiconductor layer is epitaxially grown over the first semiconductor layer on a side thereof opposite the first substrate layer. At least one of the first substrate layer and the second substrate layer may be formulated to exhibit a Coefficient of Thermal Expansion (CTE) closely matching a CTE of at least one of the first semiconductor layer and the at least one additional semiconductor layer. Semiconductor structures are fabricated using such methods.06-27-2013
20130161637SEMICONDUCTOR DEVICES INCLUDING SUBSTRATE LAYERS AND OVERLYING SEMICONDUCTOR LAYERS HAVING CLOSELY MATCHING COEFFICIENTS OF THERMAL EXPANSION, AND RELATED METHODS - Embodiments relate to semiconductor structures and methods of forming semiconductor structures. The semiconductor structures include a substrate layer having a CTE that closely matches a CTE of one or more layers of semiconductor material formed over the substrate layer. In some embodiments, the substrate layers may comprise a composite substrate material including two or more elements. The substrate layers may comprise a metal material and/or a ceramic material in some embodiments.06-27-2013
20130161638HIGH ELECTRON MOBILITY TRANSISTOR STRUCTURE WITH IMPROVED BREAKDOWN VOLTAGE PERFORMANCE - A HEMT includes a silicon substrate, an unintentionally doped gallium nitride (UID GaN) layer over the silicon substrate, a donor-supply layer over the UID GaN layer, a gate structure, a drain, and a source over the donor-supply layer, and a passivation material layer having one or more buried portions contacting or almost contacting the UID GaN layer. A carrier channel layer at the interface of the donor-supply layer and the UID GaN layer has patches of non-conduction in a drift region between the gate and the drain. A method for making the HEMT is also provided.06-27-2013
20130161639DRAIN INDUCED BARRIER LOWERING WITH ANTI-PUNCH-THROUGH IMPLANT - An integrated circuit containing an MOS transistor with epitaxial source and drain regions may be formed by implanting a retrograde anti-punch-through layer prior to etching the source drain regions for epitaxial replacement. The anti-punch-through layer is disposed between stressor tips of the epitaxial source and drain regions, and does not substantially extend into the epitaxial source and drain regions.06-27-2013
20130161641TRANSISTOR WITH ENHANCED CHANNEL CHARGE INDUCING MATERIAL LAYER AND THRESHOLD VOLTAGE CONTROL - High electron mobility transistors and fabrication processes are presented in which a barrier material layer of uniform thickness is provided for threshold voltage control under an enhanced channel charge inducing material layer (ECCIML) in source and drain regions with the ECCIML layer removed in the gate region.06-27-2013
20110042683CRACK FREE MULTILAYERED DEVICES, METHODS OF MANUFACTURE THEREOF AND ARTICLES COMPRISING THE SAME - Disclosed herein is an article comprising a substrate; an interlayer comprising aluminum nitride, gallium nitride, boron nitride, indium nitride or a solid solution of aluminum nitride, gallium nitride, boron nitride and/or indium nitride; the interlayer being directly disposed upon the substrate and in contact with the substrate; where the interlayer comprises a columnar film and/or nanorods and/or nanotubes; and a group-III nitride layer disposed upon the interlayer; where the group-III nitride layer completely covers a surface of the interlayer that is opposed to a surface in contact with the substrate; the group-III nitride layer being free from cracks.02-24-2011
20120037917LOW INTERCONNECT RESISTANCE INTEGRATED SWITCHES - Circuits and systems comprising one or more switches are provided. A circuit includes a first switch formed on a substrate; and a second switch formed on the substrate, the second switch including a first terminal coupled to a third terminal of the first switch. A system includes a supply; a first switch formed on a substrate, the first switch coupled to the supply; a second switch formed on the substrate, the second switch coupled to the first switch; a third switch formed on the substrate, the third switch coupled to the supply; a fourth switch formed on the substrate, the fourth switch coupled to the third switch; and a driver coupled to respective second terminals of the first, second, third, and fourth switches.02-16-2012
20110278589Gallium Nitride Semiconductor Device With Improved Forward Conduction - A gallium nitride based semiconductor diode includes a substrate, a semiconductor body including a first heavily doped GaN layer and a second lightly doped GaN layer. The semiconductor body includes mesas projecting upwardly from a lower surface where each of the mesas includes the second GaN layer and a portion of the first GaN layer. Schottky contacts are formed on the upper surface of the mesas and ohmic contacts are formed on the lower surface of the semiconductor body. An insulating layer is formed over the Schottky and ohmic contacts. Vias are formed in the insulating layer to the Schottky contacts and vias are formed in the semiconductor body to the Ohmic contacts. An anode electrode is formed in a first metal pad in electrical contact with the Schottky contacts. A cathode electrode is formed in a second metal pad in electrical contact with the ohmic contacts.11-17-2011
20110278588Method of Preparing and Storing GaN Substrate, Prepared and Stored GaN Substrate, and Semiconductor Device and Method of Its Manufacture - A GaN substrate storage method of storing, within an atmosphere in which the oxygen concentration is not greater than 15 vol. % and the water-vapor concentration is not greater than 20 g/m11-17-2011
20110278587Fast Annealing for GaN LEDs - Methods of performing fast thermal annealing in forming GaN light-emitting diodes (LEDs) are disclosed, as are GaN LEDs formed using fast thermal annealing. An exemplary method includes forming a GaN multilayer structure having a n-GaN layer and a p-GaN layer that sandwich an active layer. The method includes performing fast thermal annealing of the p-GaN layer using either a laser or a flash lamp. The method further includes forming a transparent conducting layer atop the GaN multilayer structure, and adding a p-contact to the transparent conducting layer and a n-contact to the n-GaN layer. The resultant GaN LEDs have enhanced output power, lower turn-on voltage and reduced series resistance.11-17-2011
20110278585GROWTH OF REDUCED DISLOCATION DENSITY NON-POLAR GALLIUM NITRIDE - Lateral epitaxial overgrowth (LEO) of non-polar gallium nitride (GaN) films results in significantly reduced defect density.11-17-2011
20110133209GaN SUBSTRATE, EPITAXIAL LAYER-PROVIDED SUBSTRATE, METHODS OF MANUFACTURING THE SAME, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A GaN substrate on which an epitaxially grown layer of good quality can be formed is obtained. A GaN substrate as a group III nitride substrate has a surface in which the number of chlorine atoms per square centimeter of the surface is not more than 2×1006-09-2011
20110260173SEMICONDUCTOR STRUCTURE - A semiconductor structure is provided. The semiconductor structure may comprise a substrate (10-27-2011
20120181548SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - There are provided a high current semiconductor device that has low on-resistance, high mobility, and good pinch-off characteristics and in which a kink phenomenon is not easily caused even if a drain voltage is increased, and a method for producing the semiconductor device. The semiconductor device of the present invention includes a GaN-based layered body 07-19-2012
20080272378METHOD FOR FORMING A NITRIDE SEMICONDUCTOR LAYER AND METHOD FOR SEPARATING THE NITRIDE SEMICONDUCTOR LAYER FROM THE SUBSTRATE - There is provided a method of forming a nitride semiconductor layer, including the steps of firstly providing a substrate on which a patterned epitaxy layer with a pier structure is formed. A protective layer is then formed on the patterned epitaxy layer, exposing a top surface of the pier structure. Next, a nitride semiconductor layer is formed over the patterned epitaxy layer connected to the nitride semiconductor layer through the pier structure, wherein the nitride semiconductor layer, the pier structure, and the patterned epitaxy layer together form a space exposing a bottom surface of the nitride semiconductor layer. Thereafter, a weakening process is performed to remove a portion of the bottom surface of the nitride semiconductor layer and to weaken a connection point between the top surface of the pier structure and the nitride semiconductor layer. Finally, the substrate is separated from the nitride semiconductor layer through the connection point.11-06-2008
20120080689LIGHT EMITTING DIODE, LIGHT EMITTING DIODE LAMP, AND LIGHTING APPARATUS - A light-emitting diode having a high output, high efficiency, and a long service life under a high-humidity environment is provided. The light-emitting diode (04-05-2012
20120286286NON-POLAR NITRIDE-BASED LIGHT EMITTING DEVICE AND METHOD FOR FABRICATING THE SAME - Disclosed are a non-polar nitride-based light emitting device and a method for fabricating the same. The non-polar nitride-based light emitting device includes a substrate, a first-type semiconductor layer on the substrate, an active layer on the active layer, a second-type semiconductor layer on the active layer, a light extraction layer on the second-type semiconductor layer and including at least one layer including indium having a plurality of unit structures having an inverted pyramidal intaglio shape, a first electrode electrically connected to the first-type semiconductor layer, and a second electrode electrically connected to the second-type semiconductor layer.11-15-2012
20120286284SEMICONDUCTOR LIGHT EMITTING DEVICE AND WAFER - According to one embodiment, a semiconductor light emitting device includes: a foundation layer, a first semiconductor layer, a light emitting part, and a second semiconductor layer. The foundation layer includes a nitride semiconductor. The foundation layer has a dislocation density not more than 5×1011-15-2012
20100117095GaN-Based Device Cascoded with an Integrated FET/Schottky Diode Device - A power semiconductor device is provided that includes a depletion mode (normally ON) main switching device cascoded with a higher speed switching device, resulting in an enhancement mode (normally OFF) FET device for switching power applications. The main switching device comprises a depletion mode GaN-based HEMT (High Electron Mobility Transistor) FET that does not include an intrinsic body diode. In one or more embodiments, the higher speed switching device comprises a high speed FET semiconductor switch arranged or connected in parallel with a Schottky diode. The high speed FET semiconductor switch may comprise a Si FET, GaN FET or any other type of FET which possesses higher speed switching capabilities and a lower voltage than that of the GaN-based HEMT FET. In some embodiments, the GaN-based HEMT FET and the higher speed switching device (i.e., the FET and Schottky diode) may be monolithically integrated on the same substrate.05-13-2010
20110297953LIGHT EMITTING DIODE AND METHOD FOR MANUFACTURING THE SAME - An exemplary light emitting diode includes a conductive base, an LED die, a transparent conductive layer and at least one pad. The LED die includes a p-type GaN layer connected to the base, an active layer on the p-type GaN layer, and an n-type GaN layer on the active layer. The transparent conductive layer is coated on an exposed side of the n-type GaN layer. The exposed side has an arched central portion, which in one embodiment is concave and in another embodiment is convex. The at least one n-side pad is mounted on the transparent conductive layer. The at least one n-side pad and the conductive base are for connecting with a power source.12-08-2011
20110140122LARGE AREA, UNIFORMLY LOW DISLOCATION DENSITY GaN SUBSTRATE AND PROCESS FOR MAKING THE SAME - Large area single crystal III-V nitride material having an area of at least 2 cm06-16-2011
20110297961FIELD EFFECT POWER TRANSISTORS - A normally OFF field effect transistor (FET) comprising: a plurality of contiguous nitride semiconductor layers having different composition and heterojunction interfaces between contiguous layers, a Fermi level, and conduction and valence energy bands; a source and a drain overlying a top nitride layer of the plurality of nitride layers and having source and drain access regions respectively comprising regions of at least two of the heterojunctions near the source and drain; a first gate between the source and drain; wherein when there is no potential difference between the gates and a common ground voltage, a two dimensional electron gas (2DEG) is present in the access region at a plurality of heterojunctions in each of the source and drain access regions, and substantially no 2DEG is present adjacent any regions of the heterojunctions under the first gate.12-08-2011
20110297957COMPOUND SEMINCONDUCTOR STRUCTURE - A method for manufacturing a compound semiconductor structure, includes (a) selecting a conductive SiC substrate in accordance with color and resistivity and (b) epitaxially growing a GaN series compound semiconductor layer on the selected conductive SiC substrate. The step (a) preferably selects a conductive SiC substrate whose main color is green, whose conductivity type is n-type and whose resistivity is 0.08 52 cm to 1×1012-08-2011
20100171126In situ dopant implantation and growth of a Ill-nitride semiconductor body - In one embodiment a method enabling in situ dopant implantation during growth of a III-nitride semiconductor body, comprises establishing a growth environment for the III-nitride semiconductor body in a composite III-nitride chamber having a dopant implanter and a growth chamber, growing the III-nitride semiconductor body in the growth chamber, and implanting the III-nitride semiconductor body in situ in the growth chamber using the dopant implanter. A semiconductor device produced using the disclosed method comprises a III-nitride semiconductor body having a first conductivity type formed over a support substrate, and at least one doped region produced by in situ dopant implantation of the III-nitride semiconductor body during its growth, that at least one doped region having a second conductivity type.07-08-2010
20100171125Thin film light emitting diode - Light emitting LEDs devices comprised of LED chips that emit light at a first wavelength, and a thin film layer over the LED chip that changes the color of the emitted light. For example, a blue LED chip can be used to produce white light. The thin film layer beneficially consists of a florescent material, such as a phosphor, and/or includes tin. The thin film layer is beneficially deposited using chemical vapor deposition.07-08-2010
20120286285METHOD OF IMPLANTING A WORKPIECE TO IMPROVE GROWTH OF A COMPOUND SEMICONDUCTOR - A workpiece is implanted to improve growth of a compound semiconductor, such as GaN. This workpiece may be implanted such that the workpiece has a dose at a center different from a dose at a periphery. This workpiece also may be implanted one or more times to form a pattern of lines, which may be a grid, a series of circles, or other shapes. The distance between certain pairs of lines may be different across the workpiece.11-15-2012
20110284868High Voltage III-Nitride Transistor - A high voltage durability III-nitride semiconductor device comprises a support substrate including a first silicon body, an insulator body over the first silicon body, and a second silicon body over the insulator body. The high voltage durability III-nitride semiconductor device further comprises a III-nitride semiconductor body characterized by a majority charge carrier conductivity type, formed over the second silicon body. The second silicon body has a conductivity type opposite the majority charge carrier conductivity type. In one embodiment, the high voltage durability III-nitride semiconductor device is a high electron mobility transistor (HEMT) comprising a support substrate including a <100> silicon layer, an insulator layer over the <100> silicon layer, and a P type conductivity <111> silicon layer over the insulator layer. The high voltage durability HEMT also comprises a III-nitride semiconductor body formed over the P type conductivity <111> silicon layer, the III-nitride semiconductor body forming a heterojunction of the HEMT.11-24-2011
20110284867LIGHT-EMITTING DIODE WITH INCREASED LIGHT EXTRACTION - Methods are disclosed for forming a vertical semiconductor light-emitting diode (VLED) device having an active layer between an n-doped layer and a p-doped layer; and securing a plurality of balls on a surface of the n-doped layer of the VLED device.11-24-2011
20110284869High Voltage Durability III-Nitride HEMT - A high voltage durability III-nitride semiconductor device comprises a support substrate including a first silicon body, an insulator body over the first silicon body, and a second silicon body over the insulator body. The high voltage durability III-nitride semiconductor device further comprises a III-nitride semiconductor body characterized by a majority charge carrier conductivity type, formed over the second silicon body. The second silicon body has a conductivity type opposite the majority charge carrier conductivity type. In one embodiment, the high voltage durability III-nitride semiconductor device is a high electron mobility transistor (HEMT) comprising a support substrate including a <100> silicon layer, an insulator layer over the <100> silicon layer, and a P type conductivity <111> silicon layer over the insulator layer. The high voltage durability HEMT also comprises a III-nitride semiconductor body formed over the P type conductivity <111> silicon layer, the III-nitride semiconductor body forming a heterojunction of the HEMT.11-24-2011
20110284866LIGHT-EMITTING DIODE (LED) STRUCTURE HAVING A WAVELENGTH-CONVERTING LAYER AND METHOD OF PRODUCING - A light emitting diode (LED) device having a substantially conformal wavelength-converting layer for producing uniform white light and a method of making said LED at both the wafer and individual die levels are provided. The LED device includes a metal substrate, a p-type semiconductor coupled to the metal substrate, an active region coupled to the p-type semiconductor, an n-type semiconductor coupled to the active region, and a wavelength converting layer coupled to the n-type semiconductor.11-24-2011
20110284862III-nitride switching device with an emulated diode - Some exemplary embodiments of a III-nitride switching device with an emulated diode have been disclosed. One exemplary embodiment comprises a GaN switching device fabricated on a substrate comprising a high threshold GaN transistor coupled across a low threshold GaN transistor, wherein a gate and a source of the low threshold GaN transistor are shorted with an interconnect metal to function as a parallel diode in a reverse mode. The high threshold GaN transistor is configured to provide noise immunity for the GaN switching device when in a forward mode. The high threshold GaN transistor and the low threshold GaN transistor are typically fabricated on the same substrate, and with significantly different thresholds. As a result, the superior switching characteristics of III-nitride devices may be leveraged while retaining the functionality and the monolithic structure of the inherent body diode in traditional silicon FETs.11-24-2011
20110284863III-V SEMICONDUCTOR STRUCTURES AND METHODS FOR FORMING THE SAME - Embodiments of the invention relate to methods of fabricating semiconductor structures, and to semiconductor structures fabricated by such methods. In some embodiments, the methods may be used to fabricate semiconductor structures of III-V materials, such as InGaN. A semiconductor layer is fabricated by growing sublayers using differing sets of growth conditions to improve the homogeneity of the resulting layer, to improve a surface roughness of the resulting layer, and/or to enable the layer to be grown to an increased thickness without the onset of strain relaxation.11-24-2011
20110284864LIGHT EMITTING DEVICE, LIGHT EMITTING DEVICE PACKAGE, AND LIGHTING DEVICE - A light emitting device includes a support member, a light emitting structure on the support member, the light emitting structure including a first conductive type semiconductor layer, a second conductive type semiconductor layer, and an active layer between the second conductive type semiconductor layer and the first conductive type semiconductor layer, a first nitride semiconductor layer disposed on the second conductive type semiconductor layer, a second nitride semiconductor layer disposed on the first nitride semiconductor layer and including an uneven structure, and a first electrode pad disposed on the light emitting structure wherein the second nitride semiconductor layer has an opening, the first electrode pad is in contact with the first nitride semiconductor layer through the opening, and the first nitride semiconductor layer has a work function smaller than that of the second nitride semiconductor layer.11-24-2011
20110297959CHAMFERED FREESTANDING NITRIDE SEMICONDUCTOR WAFER AND METHOD OF CHAMFERING NITRIDE SEMICONDUCTOR WAFER - Technology of making freestanding gallium nitride (GaN) wafers has been matured at length. Gallium nitride is rigid but fragile. Chamfering of a periphery of a GaN wafer is difficult. At present edges are chamfered by a rotary whetstone of gross granules with weak pressure. Minimum roughness of the chamfered edges is still about Ra 10 μm to Ra 6 μm. The large edge roughness causes scratches, cracks, splits or breaks in transferring process or wafer process. A wafer of the present invention is bevelled by fixing the wafer to a chuck of a rotor, bringing an edge of the wafer into contact with an elastic whetting material having a soft matrix and granules implanted on the soft matrix, rotating the wafer and feeding the whetting material. Favorably, several times of chamfering edges by changing the whetting materials of smaller granules are given to the wafer. The chamfering can realize small roughness of Ra 10 nm and Ra 5 μm at edges of wafers.12-08-2011
20110297960TRANSISTOR ASSEMBLY AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a transistor assembly includes the steps of: (a) forming a transistor; (b) polishing a base substrate; and (c) securing the transistor of which the base substrate is polished to a support substrate. The step (a) is a step of forming a first semiconductor layer and a second semiconductor layer on a principle surface of the base substrate. The step (b) is a step of polishing a surface of the base substrate opposite to the principle surface. The step (c) is a step of securing the transistor on the support substrate in the presence of a stress applied on the base substrate in such a direction that a warp of the base substrate is reduced. The base substrate is made of a material different from that of the first semiconductor layer and the second semiconductor layer, and a tensile stress is applied on the second semiconductor layer.12-08-2011
20110297954SEMICONDUCTOR DEVICE, SCHOTTKY BARRIER DIODE, ELECTRONIC APPARATUS, AND METHOD OF PRODUCING SEMICONDUCTOR DEVICE - [Problem to be Solved] Provided is a semiconductor device in which the trade-off between the pressure resistance and the on-state resistance is improved and the performance is improved.12-08-2011
20110297958Gate after Diamond Transistor - A gate after diamond transistor and method of making comprising the steps of depositing a first dielectric layer on a semiconductor substrate, depositing a diamond particle nucleation layer on the first dielectric layer, growing a diamond thin film layer on the first dielectric layer, defining an opening for the gate in the diamond thin film layer, patterning of the diamond thin film layer for a gate metal to first dielectric layer surface, etching the first dielectric layer, depositing and defining a gate metal, and forming a contact window opening in the diamond thin film layer and the first dielectric layer to the ohmic contact.12-08-2011
20110297956METHOD FOR MANUFACTURING GALLIUM NITRIDE COMPOUND SEMICONDUCTOR, AND SEMICONDUCTOR LIGHT EMITTING ELEMENT - The present invention is a method of manufacturing a gallium nitride-based compound semiconductor, including growing an m-plane InGaN layer whose emission peak wavelength is not less than 500 nm by metalorganic chemical vapor deposition. Firstly, step (A) of heating a substrate in a reactor is performed. Then, step (B) of supplying into the reactor a gas which contains an In source gas, a Ga source gas, and a N source gas and growing an m-plane InGaN layer of an In12-08-2011
20100090225NITRIDE SEMICONDUCTOR DEVICE - A nitride semiconductor device includes: a main semiconductor region comprising a first nitride semiconductor layer having a first band gap, and a second nitride semiconductor layer having a second band gap larger than the first band gap, a heterojunction being formed between the first nitride semiconductor layer and a the second nitride semiconductor layer such that two-dimensional electron gas layer can be caused inside the first nitride semiconductor layer based on the heterojunction; a source electrode formed on the main semiconductor region; a drain electrode formed on the main semiconductor region and separated from the source electrode; a third nitride semiconductor layer formed on the first nitride semiconductor layer and between the source electrode and the drain electrode; and a gate electrode formed on the third nitride semiconductor layer. The third nitride semiconductor layer has a third band gap smaller than the first band gap.04-15-2010
20110291103TRENCH SIDEWALL CONTACT SCHOTTKY PHOTODIODE AND RELATED METHOD OF FABRICATION - A Schottky photodiode may include a monocrystalline semiconductor substrate having a front surface, a rear surface, and a first dopant concentration and configured to define a cathode of the Schottky photodiode, a doped epitaxial layer over the front surface of the monocrystalline semiconductor substrate having a second dopant concentration less than the first dopant concentration, and parallel spaced apart trenches in the doped epitaxial layer and having of a depth less than a depth of the doped epitaxial layer. The Schottky photodiode may include a metal filler in the parallel spaced apart trenches to form a Schottky rectifying contact with the doped epitaxial layer, an anode current distributor metal layer on a surface of the doped epitaxial layer and in electrical contact with the metal filler of the parallel spaced apart trenches, a dielectric passivation layer on the anode current distributor metal layer, and a conductive metal layer over the rear surface of the monocrystalline semiconductor substrate and configured to provide an ohmic contact with the cathode.12-01-2011
20100102328NITRIDE SEMICONDUCTOR SUBSTRATE - A nitride semiconductor substrate is featured in comprising: a GaN semiconductor layer grown on a base layer, which has a substantially triangular cross-section along the thickness direction thereof, a periodic stripe shapes, and uneven surfaces arranged on the stripes inclined surfaces; and an overgrown layer composed of AlGaN or InAlGaN on the GaN semiconductor layer.04-29-2010
20120097973HIGH PERFORMANCE POWER SWITCH - In one example, we describe a new high performance AlGaN/GaN metal-insulator-semiconductor heterostructure field-effect transistor (MISHFET), which was fabricated using HfO2 as the surface passivation and gate insulator. The gate and drain leakage currents are drastically reduced to tens of nA, before breakdown. Without field plates, for 10 μm of gate-drain spacing, the off-state breakdown voltage is 1035V with a specific on-resistance of 0.9 mΩ-cm2. In addition, there is no current slump observed from the pulse measurements. This is the best performance reported on GaN-based, fast power-switching devices on sapphire, up to now, which efficiently combines excellent device forward, reverse, and switching characteristics. Other variations, features, and examples are also mentioned here.04-26-2012
20120097972LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING SAME - A method for manufacturing a light emitting device includes forming a multilayer body including a light emitting layer so that a first surface thereof is adjacent to a first surface side of a translucent substrate. A dielectric film on a second surface side opposite to the first surface of the multilayer body is formed having first and second openings on a p-side electrode and an n-side electrode. A seed metal on the dielectric film and an exposed surface of the first and second openings form a p-side metal interconnect layer and an n-side metal interconnect layer separating the seed metal into a p-side seed metal and an n-side seed metal by removing a part of the seed metal. A resin is formed in a space from which the seed metal is removed.04-26-2012
20120097971CONTIGUOUS AND VIRTUALLY CONTIGUOUS AREA EXPANSION OF SEMICONDUCTOR SUBSTRATES - Substrates are processed, with a high degree of topography, to produce a variety of semiconductors or other devices and are then stretched out, substantially flat, to achieve a significant increase in surface area. Devices made from a contiguous structure of a single, active crystalline material or from non-contiguous structures of multiple materials, such as a combination of dielectrics, thin film metals and active crystalline semiconductors, are fabricated by utilizing anisotropically etched, high aspect ratio configurations of the active material. The structure is then stretched out to achieve a significant increase in surface area, thereby enabling a substantial reduction in the cost of the substrate materials per unit area in the final product.04-26-2012
20120097970ATOMIC LAYER DEPOSITION ENCAPSULATION FOR POWER AMPLIFIERS IN RF CIRCUITS - Power amplifiers and methods of coating a protective film of alumina (Al04-26-2012
20120097968MULTILAYER SUBSTRATE HAVING GALLIUM NITRIDE LAYER AND METHOD FOR FORMING THE SAME - The present invention provides a method for forming a multilayer substrate having a gallium nitride layer, wherein a mesh layer having a plurality of openings is formed on a substrate, and a buffer layer, three aluminum gallium nitride layers with different aluminum concentrations and a gallium nitride layer are formed in sequence on the substrate in the openings. The three aluminum gallium nitride layers with different aluminum concentrations are capable of releasing stress, decreasing cracks on the surface of the gallium nitride layer and controlling interior defects, such that the present invention provides a gallium nitride layer with larger area, greater thickness, no cracks and high quality for facilitating the formation of high performance electronic components in comparison with the prior art. The present invention further provides a multilayer substrate having a gallium nitride layer.04-26-2012
20090315036SEMICONDUCTOR DEVICES INCLUDING SCHOTTKY DIODES HAVING DOPED REGIONS ARRANGED AS ISLANDS AND METHODS OF FABRICATING SAME - A semiconductor device according to some embodiments includes a semiconductor layer having a first conductivity type and a surface in which an active region of the semiconductor device is defined. A plurality of spaced apart first doped regions are arranged within the active region. The plurality of first doped regions have a second conductivity type that is opposite the first conductivity type, have a first dopant concentration, and define a plurality of exposed portions of the semiconductor layer within the active region. The plurality of first doped regions are arranged as islands in the semiconductor layer. A second doped region in the semiconductor layer has the second conductivity type and has a second dopant concentration that is greater than the first dopant concentration.12-24-2009
20100032684ION IMPLANTATION FOR SUPPRESSION OF DEFECTS IN ANNEALED SiGe LAYERS - A method for fabricating substantially relaxed SiGe alloy layers with a reduced planar defect density is disclosed The method of the present invention includes forming a strained Ge-containing layer on a surface of a Si-containing substrate; implanting ions at or below the Ge-containing layer/Si-containing substrate interface and heating to form a substantially relaxed SiGe alloy layer that has a reduced planar defect density. A substantially relaxed SiGe-on-insulator substrate material having a SiGe layer with a reduced planar defect density as well as heterostructures containing the same are also provided.02-11-2010
20090315037COMPOUND SEMICONDUCTOR DEVICE AND ITS MANUFACTURE METHOD - A vertical type GaN series field effect transistor having excellent pinch-off characteristics is provided. A compound semiconductor device includes a conductive semiconductor substrate, a drain electrode formed on a bottom surface of the conductive semiconductor substrate, a current blocking layer formed on a top surface of the conductive semiconductor substrate, made of high resistance compound semiconductor or insulator, and having openings, an active layer of compound semiconductor burying the openings and extending on an upper surface of the current blocking layer, a gate electrode formed above the openings and above the active layer, and a source electrode formed laterally spaced from the gate electrode and formed above the active layer.12-24-2009
20100102327Semiconductor device and passive component integration in a semiconductor package - According to one exemplary embodiment, a semiconductor package includes a substrate having lower and upper surfaces. The semiconductor package further includes at least one passive component coupled to first and second conductive pads on the upper surface of the substrate. The semiconductor package further includes at least one semiconductor device coupled to a first conductive pad on the lower surface of the substrate. The at least one semiconductor device has a first electrode for electrical and mechanical connection to a conductive pad external to the semiconductor package. The at least one semiconductor device can have a second electrode electrically and mechanically coupled to the first conductive pad on the lower surface of the substrate.04-29-2010
20100102326GALLIUM NITRIDE-BASED COMPOUND SEMICONDUCTOR LIGHT-EMITTING DEVICE - An object of the present invention is to provide a gallium nitride-based compound semiconductor light-emitting device having a positive electrode which comprises a first electrode and an over-coating layer covering the side surfaces and upper surface of the first electrode provided on a p-type semiconductor layer, the over-coating layer tending not to be exfoliated from the p-type semiconductor layer. The inventive gallium nitride-based compound semiconductor light-emitting device comprises an n-type semiconductor layer, a light-emitting layer and a p-type semiconductor layer of gallium nitride-based compound semiconductors which are formed in this order on a substrate, the negative electrode and the positive electrode being provided in contact with the n-type semiconductor layer and the p-type semiconductor layer, respectively, wherein the positive electrode comprises at least a first electrode and an over-coating layer covering the side surfaces and upper surface of the first electrode, and the area where the over-coating layer comes into contact with the p-type semiconductor layer is greater at the corner portions of the positive electrode than at the side portions thereof, per unit length of the outer edge of the first electrode.04-29-2010
20120025203SEMICONDUCTOR DEVICE - A semiconductor device includes a first GaN layer formed on a substrate, the first GaN layer including a transition metal and an impurity under constant concentration, the impurity forming a deeper energy level in the first GaN layer than energy level formed by the transition metal, a second GaN layer formed on the first GaN layer, the second GaN layer including the transition metal and the impurity under inclined concentration, an inclined direction of the transition metal being same as an inclined direction of the impurity, and an electron supply layer formed on the second GaN layer.02-02-2012
20120025201Inverted Trapezoidal Recess for Epitaxial Growth - A semiconductor device having an epitaxial layer a method of manufacture thereof is provided. The semiconductor device has a substrate with a trench formed therein and a recess formed below the trench. The recess has sidewalls with a (111) crystal orientation. The depth of the trench is such that the depth is greater than or equal to one-half a length of sidewalls of the recess. An epitaxial layer is formed in the recess and the trench. The depth of the trench is sufficient to cause dislocations formed between the interface of the semiconductor substrate and the epitaxial layer to terminate along sidewalls of the trench.02-02-2012
20080308812Ga-Containing Nitride Semiconductor Single Crystal, Production Method Thereof, and Substrate and Device Using the Crystal - A Ga-containing nitride semiconductor single crystal characterized in that (a) the maximum reflectance measured by irradiating the Ga-containing nitride semiconductor single crystal with light at a wavelength of 450 nm is 20% or less and the difference between the maximum reflectance and the minimum reflectance is within 10%, (b) the ratio of maximum value to minimum value (maximum value/minimum value) of the dislocation density measured by a cathode luminescence method is 10 or less, and/or (c) the lifetime measured by a time-resolved photoluminescence method is 95 ps or more.12-18-2008
20080272377Gallium Nitride Substrate and Gallium Nitride Film Deposition Method - Affords high-carrier-concentration, low-cracking-incidence gallium nitride substrates and methods of forming gallium nitride films. A gallium nitride film 11-06-2008
20110147759GROUP III NITRIDE SEMICONDUCTOR SUBSTRATE AND MANUFACTURING METHOD OF THE SAME - A Group III nitride semiconductor substrate is provided, with diameter of 25 mm or more and thickness of 250 μm or more, wherein in at least an outer edge side part of an outer edge part within 5 mm from an outer edge of the group III nitride semiconductor substrate, stress within a main surface of the group III nitride semiconductor substrate works as a tensile stress, with the tensile stress becoming relatively greater compared to that of a center side part from the outer edge side part of the group III nitride semiconductor substrate.06-23-2011
20090014729Semiconductor light emitting device including group III nitride semiconductor - A semiconductor light emitting device comprises: a substrate; a semiconductor stack formed on one of surfaces of the substrate, the semiconductor stack including an active layer composed of a group III nitride semiconductor having a substantially nonpolar or substantially semipolar plane as a main surface; a first electrode formed in a part of a first electrode surface which is the other surface of the substrate; and a second electrode formed on a second electrode surface opposite to the first electrode surface across the substrate and semiconductor stack.01-15-2009
20120292631SEMICONDUCTOR LIGHT EMITTING DEVICE - According to one embodiment, a semiconductor light emitting device includes a stacked structure body, a first electrode, a second electrode, and a dielectric body part. The stacked structure body includes a first semiconductor layer, having a first portion and a second portion juxtaposed with the first portion, a light emitting layer provided on the second portion, a second semiconductor layer provided on the light emitting layer. The first electrode includes a contact part provided on the first portion and contacting the first layer. The second electrode includes a first part provided on the second semiconductor layer and contacting the second layer, and a second part electrically connected with the first part and including a portion overlapping with the contact part when viewed from the first layer toward the second layer. The dielectric body part is provided between the contact part and the second part.11-22-2012
20110133203TRANSPARENT CERAMIC PHOTO-OPTICAL SEMICONDUCTOR HIGH POWER SWITCHES - A photoconductive semiconductor switch according to one embodiment includes a structure of sintered nanoparticles of a high band gap material exhibiting a lower electrical resistance when excited by light relative to an electrical resistance thereof when not exposed to the light. A method according to one embodiment includes creating a mixture comprising particles, at least one dopant, and at least one solvent; adding the mixture to a mold; forming a green structure in the mold; and sintering the green structure to form a transparent ceramic. Additional system, methods and products are also presented.06-09-2011
20100078648GALLIUM NITRIDE-BASED EPITAXIAL WAFER AND METHOD OF FABRICATING EPITAXIAL WAFER - A gallium nitride-based epitaxial wafer for a nitride light-emitting device comprises a gallium nitride substrate having a primary surface, a gallium nitride-based semiconductor film provided on the primary surface of the gallium nitride substrate, and, an active layer provided on the gallium nitride-based semiconductor film, the active layer having a quantum well structure. The active layer includes a well layer of a gallium nitride-based semiconductor. The gallium nitride-based semiconductor contains indium as a Group III element. A normal line of the primary surface and a C-axis of the gallium nitride substrate form an off angle with each other. The off angle is distributed on the primary surface, and the off angle monotonically increases on the line that extends from one point to another point through a center point of the primary surface of the gallium nitride substrate. The one point and the other point are on an edge of the primary surface, and indium contents of the well layer defined at n points (n: integer) on the line monotonically decrease in a direction from the one point to the other point. The thickness values of the well layer defined at the n points monotonically increase in the direction.04-01-2010
20110140125LIGHT EMITTING DIODES WITH SMOOTH SURFACE FOR REFLECTIVE ELECTRODE - A light emitting diode comprising an epitaxial layer structure, a first electrode, and a second electrode. The first and second electrodes are disposed on one side of the epitaxial layer structure. The epitaxial layer structure includes a transparent ohmic contact layer having a root-means-square (RMS) roughness less than about 3 nm at a surface whereon the second electrode is formed. The epitaxial layer structure includes a p-type epitaxial layer and a n-type epitaxial layer, wherein the n-type epitaxial layer is coupled between the first electrode and the p-type epitaxial layer, and the p-type epitaxial layer is between the second electrode and the n-type epitaxial layer. The first electrode is located on the n-type epitaxial layer.06-16-2011
20110140124PASSIVATION OF ALUMINUM NITRIDE SUBSTRATES - The present invention provides methods of protecting a surface of an aluminum nitride substrate. The substrate with the protected surface can be stored for a period of time and easily activated to be in a condition ready for thin film growth or other processing. In certain embodiments, the method of protecting the substrate surface comprises forming a passivating layer on at least a portion of the substrate surface by performing a wet etch, which can comprise the use of one or more organic compounds and one or more acids. The invention also provides aluminum nitride substrates having passivated surfaces.06-16-2011
20100117096VERTICAL STRUCTURE SEMICONDUCTOR DEVICES WITH IMPROVED LIGHT OUTPUT - The invention provides a reliable technique to fabricate a new vertical structure compound semiconductor devices with highly improved light output. An exemplary embodiment of a method of fabricating light emitting semiconductor devices comprising the steps of forming a light emitting layer, and forming an undulated surface over light emitting layer to improve light output. In one embodiment, the method further comprises the step of forming a lens over the undulated surface of each of the semiconductor devices. In one embodiment, the method of claim further comprises the steps of forming a contact pad over the semiconductor structure to contact with the light emitting layer, and packaging each of the semiconductor devices in a package including an upper lead frame and lower lead frame. Advantages of the invention include an improved technique for fabricating semiconductor devices with great yield, reliability and light output.05-13-2010
20090267080SEMICONDUCTOR DEVICE - In a semiconductor device by which peripheral circuit sections, such as a semiconductor element, a matching circuit section, a bias circuit section, a capacitor element, are placed on and connected to a substrate, the semiconductor element can be grounded, and the semiconductor device which can make heat radiation characteristics of the semiconductor element satisfactory is provided, without providing a via hole into a semiconductor substrate.10-29-2009
20090267078Enhancement Mode III-N HEMTs - A III-N semiconductor device that includes a substrate and a nitride channel layer including a region partly beneath a gate region, and two channel access regions on opposite sides of the part beneath the gate. The channel access regions may be in a different layer from the region beneath the gate. The device includes an AlXN layer adjacent the channel layer wherein X is gallium, indium or their combination, and a preferably n-doped GaN layer adjacent the AlXN layer in the areas adjacent to the channel access regions. The concentration of Al in the AlXN layer, the AlXN layer thickness and the n-doping concentration in the n-doped GaN layer are selected to induce a 2DEG charge in channel access regions without inducing any substantial 2DEG charge beneath the gate, so that the channel is not conductive in the absence of a switching voltage applied to the gate.10-29-2009
20100078649Light emitting element and light emitting device - A light emitting element which emits light of a wavelength, includes a substrate which is transparent to the wavelength of emitted light and includes a first surface and a second surface; a semiconductor layer stacked on the first surface; a first electrode which is reflective to the wavelength of emitted light and formed on a surface of the semiconductor layer, wherein electrical resistance of the first electrode in a farthest distance is equal to or smaller than 1Ω; and a second electrode which is reflective to the wavelength of emitted light and formed on the second surface, wherein electrical resistance of the second electrode in a farthest distance is equal to or smaller than 1Ω.04-01-2010
20110062449TECHNIQUE FOR THE GROWTH AND FABRICATION OF SEMIPOLAR (GA,AL,IN,B)N THIN FILMS, HETEROSTRUCTURES, AND DEVICES - A method for growth and fabrication of semipolar (Ga, Al, In, B)N thin films, heterostructures, and devices, comprising identifying desired material properties for a particular device application, selecting a semipolar growth orientation based on the desired material properties, selecting a suitable substrate for growth of the selected semipolar growth orientation, growing a planar semipolar (Ga, Al, In, B)N template or nucleation layer on the substrate, and growing the semipolar (Ga, Al, In, B)N thin films, heterostructures or devices on the planar semipolar (Ga, Al, In, B)N template or nucleation layer. The method results in a large area of the semipolar (Ga, Al, In, B)N thin films, heterostructures, and devices being parallel to the substrate surface.03-17-2011
20110062448Field effect semiconductor devices and methods of manufacturing field effect semiconductor devices - Field effect semiconductor devices and methods of manufacturing the same are provided, the field effect semiconductor devices include a second semiconductor layer on a first surface of a first semiconductor layer, a first and a second third semiconductor layer respectively on two sides of the second semiconductor layer, a source and a drain respectively on the first and second third semiconductor layer, and a gate electrode on a second surface of the first semiconductor layer.03-17-2011
20110198610NITRIDE SEMICONDUCTOR CRYSTAL, MANUFACTURING METHOD OF THE NITRIDE SEMICONDUCTOR FREESTANDING SUBSTRATE AND NITRIDE SEMICONDUCTOR DEVICE - To provide a nitride semiconductor crystal, comprising: laminated homogeneous nitride semiconductor layers, with a thickness of 2 mm or more, wherein the laminated homogeneous nitride semiconductor layers are constituted so that a nitride semiconductor layer with low dopant concentration and a nitride semiconductor layer with high dopant concentration are alternately laminated by two cycles or more.08-18-2011
20090090917GaN single-crystal substrate and method for producing GaN single crystal - A GaN single-crystal substrate has a substrate surface in which polarity inversion zones are included. The number density of the polarity inversion zones in the substrate surface is not more than 20 cm04-09-2009
20090278136Process for Growth of Low Dislocation Density Gan - High quality free standing GaN is obtained using a new modification of the Epitaxial Lateral Overgrowth technology in which 3D islands or features are created only by tuning the growth parameters. Smoothing these islands (2D growth) is achieved thereafter by setting growth conditions producing enhanced lateral growth. The repetition of 3D-2D growth results in multiple bending of the threading dislocations thus producing thick layers or free standing GaN with threading dislocation density below 1011-12-2009
20110198611III-Nitride Power Device with Solderable Front Metal - Some exemplary embodiments of a III-nitride power device including a HEMT with multiple interconnect metal layers and a solderable front metal structure using solder bars for external circuit connections have been disclosed. The solderable front metal structure may comprise a tri-metal such as TiNiAg, and may be configured to expose source and drain contacts of the HEMT as alternating elongated digits or bars. Additionally, a single package may integrate multiple such HEMTs wherein the front metal structures expose alternating interdigitated source and drain contacts, which may be advantageous for DC-DC power conversion circuit designs using III-nitride devices. By using solder bars for external circuit connections, lateral conduction is enabled, thereby advantageously reducing device Rdson.08-18-2011
20110198609Light-Emitting Devices with Through-Substrate Via Connections - Multiple through-substrate vias (TSVs) are used to make electrical connections for an LED formed over a substrate. A first TSV extends through the substrate from a back surface of the substrate to the front surface of the substrate and includes a first TSV conductor that electrically connects to a first cladding layer of the LED. A second TSV extends through the substrate and an active layer of the LED from the back surface of the substrate to a second cladding layer or an ITO layer. The second TSV includes an isolation layer that electrically isolates a second TSV conductor from the first cladding layer and the active layer. Additionally dummy TSVs may be formed to conduct heat away from the LED optionally through a package substrate.08-18-2011
20090283776WIDE BAND GAP SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME - A wide band gap semiconductor device is disclosed. A first trench in a gate electrode part and a second trench in a source electrode part (Schottky diode part) are disposed so that the first and second trenches are close to each other while and the second trench is deeper than the first trench. A metal electrode is formed in the second trench to form a Schottky junction on a surface of an n-type drift layer in the bottom of the second trench. Further, a p+-type region is provided in part of the built-in Schottky diode part being in contact with the surface of the n-type drift layer, preferably in the bottom of the second trench. The result is a wide band gap semiconductor device which is small in size and low in on-resistance and loss, and in which electric field concentration applied on a gate insulating film is relaxed to suppress lowering of withstand voltage to thereby increase avalanche breakdown tolerance at turning-off time.11-19-2009
20120138949LIGHT EMITTING DEVICE - Disclosed is a light emitting device including a substrate, a first buffer layer disposed on the substrate, the first buffer layer comprising aluminum nitride (AlN), an insertion layer disposed on the first buffer layer, the insertion layer comprising aluminum (Al), and a light emitting structure disposed on the insertion layer, the light emitting structure comprising a first semiconductor layer, a second semiconductor layer, and an active layer interposed between the first semiconductor layer and the second semiconductor layer.06-07-2012
20110169012NANOWIRE AND LARGER GaN BASED HEMTS - Nanowire and larger, post-based HEMTs, arrays of such HEMTs, and methods for their manufacture are provided. In one embodiment, a HEMT can include a III-N based core-shell structure including a core member (e.g., GaN), a shell member (e.g., AlGaN) surrounding a length of the core member and a two-dimensional electron gas (2-DEG) at the interface therebetween. The core member including a nanowire and/or a post can be disposed over a doped buffer layer and a gate material can be disposed around a portion of the shell member. Exemplary methods for making the nanowire HEMTs and arrays of nanowire HEMTs can include epitaxially forming nanowire(s) and epitaxially forming a shell member from each formed nanowire. Exemplary methods for making the post HEMTs and arrays of post HEMTs can include etching a III-N layer to form II-N post(s) followed by formation of the shell member(s).07-14-2011
20110204381SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - There are provided a semiconductor device that includes a bypass protection unit against surge voltage or the like, achieves good withstand voltage characteristics and low on-resistance (low On-state voltage), has a simple structure, and is used for large-current purpose and a method for producing the semiconductor device.08-25-2011
20110204380NITRIDE-BASED FET - According to an embodiment, in a nitride-based FET, a protrusion portion is formed at an upper portion of an undoped GaN layer by second recess etching. On the protrusion portion, an undoped AlGaN layer is provided which is formed by first recess etching the upper portion of the undoped AlGaN layer. A multilayer portion is composed of the protrusion portion of the undoped GaN layer, the undoped AlGaN layer, and an insulating film. A trench portion is formed by recess etching the insulating film, the undoped AlGaN layer and a surface of the undoped GaN layer. A gate insulating film is formed on the multilayer portion and the trench portion. A gate electrode is formed on the gate insulating film so as to cover the trench portion. A film thickness of the insulting film is set larger than that of the gate insulating film.08-25-2011
20090261346Integrating CMOS and Optical Devices on a Same Chip - An integrated circuit structure includes a semiconductor substrate having a first surface region and a second surface region, wherein the first surface region and the second surface region have different surface orientations; a semiconductor device formed at a surface of the first surface region; and a group-III nitride layer over the second surface region, wherein the group-III nitride layer does not extend over the first surface region.10-22-2009
20120292632NITRIDE SEMICONDUCTOR DEVICE, NITRIDE SEMICONDUCTOR WAFER AND METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR LAYER - According to one embodiment, a nitride semiconductor device includes a foundation layer and a functional layer. The foundation layer is formed on an Al-containing nitride semiconductor layer formed on a silicon substrate. The foundation layer has a thickness not less than 1 micrometer and including GaN. The functional layer is provided on the foundation layer. The functional layer includes a first semiconductor layer. The first semiconductor layer has an impurity concentration higher than an impurity concentration in the foundation layer and includes GaN of a first conductivity type.11-22-2012
20120292629LIGHT EMITTING DIODE AND METHOD OF FABRICATION THEREOF - A method includes providing an LED element including a substrate and a gallium nitride (GaN) layer disposed on the substrate. The GaN layer is treated. The treatment includes performing an ion implantation process on the GaN layer. The ion implantation process may provide a roughened surface region of the GaN layer. In an embodiment, the ion implantation process is performed at a temperature of less than approximately 25 degrees Celsius. In a further embodiment, the substrate is at a temperature less than approximately zero degrees Celsius during the ion implantation process.11-22-2012
20120292630LED SUBSTRATE AND LED - A light emitting diode (LED) substrate including a sapphire substrate is provided. The sapphire substrate has a surface consisting of a plurality of upper trigonal and lower hexagonal tapers, wherein each of the upper trigonal and lower hexagonal tapers is consisted of a hexagonal taper and a trigonal taper on the hexagonal taper, and a pitch of the upper trigonal and lower hexagonal tapers is less than 10 μm. This LED substrate has high light-emitting efficiency.11-22-2012
20120292633LIGHT EMITTING DIODE ARRAY AND METHOD FOR MANUFACTURING THE SAME - An LED array includes a substrate and a plurality of LEDs formed on the substrate. The LEDs are electrically connected with each other. Each of the LEDs includes a connecting layer, an n-type GaN layer, an active layer, and a p-type GaN layer formed on the substrate in sequence. The connecting layer is etchable by alkaline solution. A bottom surface of the n-type GaN layer which connects the connecting layer has a roughened exposed portion. The bottom surface of the n-type GaN layer has an N-face polarity. A method for manufacturing the LED array is also provided.11-22-2012
20110266554SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE DEVICE - In a manufacturing method of a semiconductor device, first, a first semiconductor layer, a second semiconductor layer, and a p-type third semiconductor layer are sequentially epitaxially grown on a substrate. After that, the third semiconductor layer is selectively removed. Then, a fourth semiconductor layer is epitaxially grown on the second semiconductor layer. Then, a gate electrode is formed on the third semiconductor layer.11-03-2011
20100102330NITRIDE SEMICONDUCTOR DEVICE HAVING OXYGEN-DOPED N-TYPE GALLIUM NITRIDE FREESTANDING SINGLE CRYSTAL SUBSTRATE - Oxygen can be doped into a gallium nitride crystal by preparing a non-C-plane gallium nitride seed crystal, supplying material gases including gallium, nitrogen and oxygen to the non-C-plane gallium nitride seed crystal, growing a non-C-plane gallium nitride crystal on the non-C-plane gallium nitride seed crystal and allowing oxygen to infiltrating via a non-C-plane surface to the growing gallium nitride crystal.04-29-2010
20110204377Methods of growing nitride semiconductors and methods of manufacturing nitride semiconductor substrates - Methods of growing nitride semiconductor layers including forming nitride semiconductor dots on a substrate and growing a nitride semiconductor layer on the nitride semiconductor dots. The nitride semiconductor layer may be separated from the substrate to be used as a nitride semiconductor substrate.08-25-2011
20080277667Method of producing III-nitride substrate11-13-2008
20080290347Gallium Nitride Semiconductor and Method of Manufacturing the Same - The present invention provides to a gallium nitride (GaN) semiconductor and a method of manufacturing the same, capable of reducing crystal defects caused by a difference in lattice parameters, and minimizing internal residual stress. In particular, since a high-quality GaN thin film is formed on a silicon wafer, manufacturing costs can be reduced by securing high-quality wafers with a large diameter at a low price, and applicability to a variety of devices and circuit can also be improved.11-27-2008
20080290346LIGHT EMITTING DEVICE AND MANUFACTURING METHOD THEREOF - Provided are a light emitting device and a manufacturing method thereof. The light emitting device comprises a first conductive semiconductor layer with a lower surface being uneven in height, an active layer on the first conductive semiconductor layer, and a second conductive semiconductor layer on the active layer.11-27-2008
20080303033FORMATION OF NITRIDE-BASED OPTOELECTRONIC AND ELECTRONIC DEVICE STRUCTURES ON LATTICE-MATCHED SUBSTRATES - A method of forming an AlInGaN alloy-based electronic or optoelectronic device structure on a nitride substrate and subsequent removal of the substrate. An AlInGaN alloy-based electronic or optoelectronic device structure formed on a nitride substrate is freed from the substrate on which it was grown.12-11-2008
20080303032Bulk Mono-Crystalline Gallium-Containing Nitride and Its Application - Bulk monocrystalline gallium-containing nitride, grown on the seed at least in the direction essentially perpendicular to the direction of the seed growth, essentially without propagation of crystalline defects as present in the seed, having the dislocation density not exceeding 1012-11-2008
20080308814GALLIUM NITRIDE SUBSTRATE AND GALLIUM NITRIDE LAYER FORMATION METHOD - There is disclosed a method for forming a gallium nitride layer of which resistivity is 1×1012-18-2008
20110204379NITRIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A nitride semiconductor device including: a substrate; a nitride semiconductor layer formed on the substrate and having a heterojunction interface; and a recess portion formed on the nitride semiconductor layer, wherein the nitride semiconductor layer includes: a carrier transit layer, which has a composition represented by the formula: Al08-25-2011
20130181226SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME - There are provided a semiconductor device in which a drain leak current can be reduced in the transistor operation while high vertical breakdown voltage is achieved and a method for producing the semiconductor device. In the semiconductor device, an opening 07-18-2013
20080308815GaN Substrate, Substrate with an Epitaxial Layer, Semiconductor Device, and GaN Substrate Manufacturing Method - Affords a GaN substrate from which enhanced-emission-efficiency light-emitting and like semiconductor devices can be produced, an epi-substrate in which an epitaxial layer has been formed on the GaN substrate principal surface, a semiconductor device, and a method of manufacturing the GaN substrate. The GaN substrate is a substrate having a principal surface with respect to whose normal vector the [0001] plane orientation is inclined in two different off-axis directions.12-18-2008
20130181225SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a metal substrate including a metal base plate, an insulating sheet located on the metal base plate, and a wiring pattern located on the insulating sheet, and a semiconductor element located on the metal substrate. The semiconductor element is sealed with a molding resin. The molding resin extends to side surfaces of the metal substrate. On the side surfaces of the metal substrate, the insulating sheet and the wiring pattern are not exposed from the molding resin, whereas the metal base plate includes a projecting portion exposed from the molding resin.07-18-2013
20130181224SEMICONDUCTOR STRUCTURE - A semiconductor structure includes a barrier layer, a spacer structure, and a channel layer. The barrier layer includes a group III nitride. The spacer structure includes first and second aluminum nitride layers and an intermediate layer. The intermediate layer includes a group III nitride and is between the first and second aluminum nitride layers. The intermediate layer has a first free charge carrier density at an interface with the second aluminum nitride layer. The spacer structure is between the barrier layer and the channel layer. The channel layer includes a group III nitride and has a second free charge carrier density at an interface with the first aluminum nitride layer of the spacer structure. The first aluminum nitride layer, the intermediate layer, and the second aluminum nitride layer have layer thicknesses so the first free charge carrier density is less than 10% of the second free charge carrier density.07-18-2013
20120292634GALIUM-NITRIDE LIGHT EMITTING DEVICE OF MICROARRAY TYPE STRUCTURE AND MANUFACTURING THEREOF - Disclosed are a microarray type nitride light emitting device and a method of manufacturing the same. More particularly, a uniform current distribution property is ensured by dividing a fine light emitting region by using a first transparent contact layer according to a resistance change property in heat treatment of a material of a transparent conducting oxide used as a transparent contact layer, and connecting the divided light emitting regions by using a second transparent contact layer.11-22-2012
20080303034Light-emitting gallium nitride-based III-V group compound semiconductor device and manufacturing method thereof - A light-emitting gallium nitride-based III-V group compound semiconductor device and a manufacturing method thereof are disclosed. The light emitting device includes a substrate, a n-type semiconductor layer over the substrate, an active layer over the n-type semiconductor layer, a p-type semiconductor layer over the active layer, a conductive layer over the p-type semiconductor layer, a first electrode disposed on the conductive layer and a second electrode arranged on exposed part of the n-type semiconductor layer. A resistant reflective layer or a contact window is disposed on the p-type semiconductor layer, corresponding to the first electrode so that current passes beside the resistant reflective layer or by the contact window to the active layer for generating light. When the light is transmitted to the conductive layer for being emitted, it is not absorbed or shielded by the first electrode. Thus the current is distributed efficiently over the conductive layer. Therefore, both LED brightness and efficiency are improved. Moreover, adhesion between the conductive layer and the p-type semiconductor layer is improved so that metal peel-off problem during manufacturing processes can be improved.12-11-2008
20130119394Termination Structure for Gallium Nitride Schottky Diode - A termination structure for a nitride-based Schottky diode includes a guard ring formed by an epitaxially grown P-type nitride-based compound semiconductor layer and dielectric field plates formed on the guard ring. The termination structure is formed at the edge of the anode electrode of the Schottky diode and has the effect of reducing electric field crowding at the anode electrode edge, especially when the Schottky diode is reverse biased. In one embodiment, the P-type epitaxial layer includes a step recess to further enhance the field spreading effect of the termination structure.05-16-2013
20130119397NITRIDE-BASED HETEROJUCTION SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACUTRING THE SAME - Disclosed is a semiconductor device. More specifically, disclosed are a nitride-based heterojunction semiconductor device and a method for manufacturing the same. The nitride-based heterojunction semiconductor device includes a first drain electrode, a conductive semiconductor layer including a nitride-based semiconductor disposed on the first drain electrode, a channel layer disposed on the conductive semiconductor layer, a barrier layer disposed on the channel layer, a source electrode and a second drain electrode spaced from each other on the barrier layer, and a gate electrode disposed between the source electrode and the second drain electrode.05-16-2013
20130119403Semiconductor Structure and a Method of Forming the Same - Some embodiments show a semiconductor structure including a substrate with a {100} crystal surface plane which includes a plurality of adjacent structured regions at a top side of the substrate. The plurality of adjacent structured regions includes adjacent substrate surfaces with {111} crystal planes and a III-V semiconductor material layer above the top side of the substrate. A semiconductor device region includes at least one semiconductor device structure. The semiconductor device region is arranged above the plurality of adjacent structured regions at the top side of the substrate.05-16-2013
20130119404DEVICE STRUCTURE INCLUDING HIGH-THERMAL-CONDUCTIVITY SUBSTRATE - Methods and apparatuses for forming a device structure including a high-thermal-conductivity substrate are disclosed herein. A method forming such a device structure may comprise forming an active layer over a first substrate in a manner such that a frontside of the active layer faces the first substrate and a backside of the active layer faces away from the first substrate, forming a second substrate over the backside of the active layer, and removing the first substrate to expose the frontside of the active layer. Other embodiments are described and claimed.05-16-2013
20110266552LIGHT EMITTING ELEMENT AND MANUFACTURING METHOD THEREOF - A light emitting element includes a substrate, a GaN layer formed on the substrate, a first low refractive index semiconductor layer formed on the GaN layer, and a lighting structure having a high refractive index formed on the first low refractive index semiconductor layer. A second low refractive index semiconductor layer is embedded in the first low refractive index semiconductor layer. The first low refractive index semiconductor layer and the GaN layer exhibit a lattice mismatch therebetween.11-03-2011
20080265259GaN-BASED PERMEABLE BASE TRANSISTOR AND METHOD OF FABRICATION - An etched grooved GaN-based permeable-base transistor structure is disclosed, along with a method for fabrication of same.10-30-2008
20080265258Group III Nitride Semiconductor Device and Epitaxial Substrate - Affords Group III nitride semiconductor devices in which the leakage current from the Schottky electrode can be decreased. In a high electron mobility transistor 10-30-2008
20110006307Group III-Nitride Semiconductor Schottky Diode and Its Fabrication Method - A group III-nitride semiconductor Schottky diode comprises a conducting substrate having a first surface, a stack of multiple layers including a buffer layer and a semiconductor layer sequentially formed on the first surface, wherein the semiconductor layer comprises a group III nitride compound, a first electrode on the semiconductor layer, and a second electrode formed in contact with the first surface at a position adjacent to the stack of multiple layers. In other embodiments, the application also describes a method of fabricating the group III-nitride semiconductor Schottky diode.01-13-2011
20110220910SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor light emitting device includes a semiconductor layer, a first electrode, a second electrode, an insulating film, a first interconnection, a second interconnection, a barrier metal layer, a first metal pillar, a second metal pillar, and a resin. The semiconductor layer has a first major surface, a second major surface formed on an opposite side to the first major surface, and a light emitting layer. The first electrode is provided on the second major surface of the semiconductor layer. The second electrode is provided on the second major surface of the semiconductor layer and includes a silver layer. The insulating film is provided on the second major surface side of the semiconductor layer. The barrier metal layer is provided between the second electrode and the insulating film and between the second electrode and the second interconnection to cover the second electrode.09-15-2011
20090289261GALLIUM NITRIDE CRYSTAL SUBSTRATE AND METHOD OF PRODUCING SAME - A low-distortion gallium nitride crystal substrate including low dislocation single crystal regions (Z) having a definite c-axis and a definite a-axis, C-plane growth regions (Y) having a c-axis and a-axis parallel to the c-axis and a-axis of the low dislocation single crystal regions (Z), voluminous defect accumulating regions (H) having a c-axis inverse to the c-axis of the low dislocation single crystal regions (Z) and an a-axis parallel with the a-axis of the low dislocation single crystal regions (Z), and 0.1/cm11-26-2009
20100200865GROUP III NITRIDE SEMICONDUCTOR SUBSTRATE AND METHOD FOR CLEANING THE SAME - A Group-III nitride semiconductor substrate having a flat surface with a dangling bond density of higher than 14.0 nm08-12-2010
20100200864Method for Fabricating a Semiconductor Component Based on GaN - A semiconductor component has a plurality of GaN-based layers, which are preferably used to generate radiation, produced in a fabrication process. In the process, the plurality of GaN-based layers are applied to a composite substrate that includes a substrate body and an interlayer. A coefficient of thermal expansion of the substrate body is similar to or preferably greater than the coefficient of thermal expansion of the GaN-based layers, and the GaN-based layers are deposited on the interlayer. The interlayer and the substrate body are preferably joined by a wafer bonding process.08-12-2010
20100200863ELECTRODE STRUCTURE, SEMICONDUCTOR DEVICE, AND METHODS FOR MANUFACTURING THOSE - A first layer containing Ti as a constituent element, a second layer containing Nb as a constituent element, and a third layer containing Au as a constituent element are formed on a GaN substrate 11. Thereafter, the GaN substrate 11 and the first to third layers are kept at 700° C. or higher and at 1300° C. or lower. This allows a metal oxide of Ti to be distributed to extend from the interface between the GaN substrate 11 and the electrode 14 over to the inside of the electrode 14. Further, a metal nitride of Nb is formed in the inside of the GaN substrate 11. The metal nitride of Nb will be distributed to extend from the inside of the electrode 14 over to the inside of the GaN substrate 11.08-12-2010
20120138948COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A compound semiconductor device includes: an electron transport layer formed over a substrate; an electron supply layer formed over the electron transport layer; and a cap layer formed over the electron supply layer; the cap layer includes a first compound semiconductor layer containing GaN; a second compound semiconductor layer containing AlN, which is formed over the first compound semiconductor layer; a third compound semiconductor layer containing GaN, which is formed over the second compound semiconductor layer; and at least one of a first AlGaN-containing layer and a second AlGaN-containing layer, with the first AlGaN-containing layer formed between the first compound semiconductor layer and the second compound semiconductor layer and the Al content increases toward the second compound semiconductor layer, and the second AlGaN-containing layer formed between the second compound semiconductor layer and the third compound semiconductor layer and the Al content increases toward the second compound semiconductor layer.06-07-2012
20080315209Group III Nitride Semiconductor Device and Epitaxial Substrate - Affords a Group III nitride semiconductor device having a structure that can improve the breakdown voltage. A Schottky diode (12-25-2008
20090001381Semiconductor device - A semiconductor device includes a substrate, laminated layers provided on the substrate. The laminated layers include an AlGaN barrier layer as an uppermost layer. A gate electrode is provided in a channel region of the laminated layers. A source electrode and a drain electrode are provided so as to face each other via the channel region interposed therebetween. A silicon nitride film is formed to cover an exposed surface of the laminated layers exposed via the gate electrode, the source electrode and the drain electrode. The silicon nitride film has characteristics that an etching rate thereof is in a range from 1 nm per/min to 2 nm/min for an etchant in which hydrofluoric acid having a concentration of 50 weight percent and ammonium fluoride having a concentration of 40 weight percent are mixed at a mixing ratio of 1:9.01-01-2009
20100276698GATE ELECTRODES FOR MILLIMETER-WAVE OPERATION AND METHODS OF FABRICATION - A transistor device having a tiered gate electrode fabricated with methods using a triple layer resist structure. The triple layer resist stack is deposited on a semiconductor structure. An exposure pattern is written onto the resist stack using an e-beam writer, for example. The exposure dose is non-uniform across the device. Portions of the three resist layers are removed with a sequential development process, resulting in tiered resist structure. A conductive material is deposited to form the gate electrode. The resulting “Air-T” gate also has a three-tiered structure. The fabrication process is well-suited for the production of gates small enough for use in millimeter wave devices.11-04-2010
20120068192CRYSTAL GROWTH OF M-PLANE AND SEMIPOLAR PLANES OF (Al, In, Ga, B)N ON VARIOUS SUBSTRATES - A method of reducing threading dislocation densities in non-polar such as a-{11-20} plane and m-{1-100} plane or semi-polar such as {10-1n} plane III-Nitrides by employing lateral epitaxial overgrowth from sidewalls of etched template material through a patterned mask. The method includes depositing a patterned mask on a template material such as a non-polar or semi polar GaN template, etching the template material down to various depths through openings in the mask, and growing non-polar or semi-polar III-Nitride by coalescing laterally from the tops of the sidewalls before the vertically growing material from the trench bottoms reaches the tops of the sidewalls. The coalesced features grow through the openings of the mask, and grow laterally over the dielectric mask until a fully coalesced continuous film is achieved.03-22-2012
20120068191METHOD OF CONTROLLING STRESS IN GROUP-III NITRIDE FILMS DEPOSITED ON SUBSTRATES - Methods of controlling stress in GaN films deposited on silicon and silicon carbide substrates and the films produced therefrom are disclosed. A typical method comprises providing a substrate and depositing a graded gallium nitride layer on the substrate having a varying composition of a substantially continuous grade from an initial composition to a final composition formed from a supply of at least one precursor in a growth chamber without any interruption in the supply. A typical semiconductor film comprises a substrate and a graded gallium nitride layer deposited on the substrate having a varying composition of a substantially continuous grade from an initial composition to a final composition formed from a supply of at least one precursor in a growth chamber without any interruption in the supply.03-22-2012
20120068190Gallium Nitride Devices with Electrically Conductive Regions - Semiconductor structures comprising a III-nitride (e.g., gallium nitride) material region and methods associated with such structures are provided. In some embodiments, the structures include an electrically conductive material (e.g., gold) separated from certain other region(s) of the structure (e.g., a silicon substrate) by a barrier material in order to limit, or prevent, undesirable reactions between the electrically conductive material and the other component(s) which can impair device performance. In certain embodiments, the electrically conductive material may be formed in a via. For example, the via can extend from a topside of the device to a backside so that the electrically conductive material connects a topside contact to a backside contact. The structures described herein may form the basis of a number of semiconductor devices including transistors (e.g., PET), Schottky diodes, light-emitting diodes and laser diodes, amongst others.03-22-2012
20120068189Method for Vertical and Lateral Control of III-N Polarity - Disclosed herein is a method of: depositing a patterned mask layer on an N-polar GaN epitaxial layer of a sapphire, silicon, or silicon carbide substrate; depositing an AlN inversion layer on the open areas; removing any remaining mask; and depositing a III-N epitaxial layer to simultaneously produce N-polar material and III-polar material. Also disclosed herein is: depositing an AlN inversion layer on an N-polar bulk III-N substrate and depositing a III-N epitaxial layer to produce III-polar material. Also disclosed herein is: depositing an inversion layer on a III-polar bulk III-N substrate and depositing a III-N epitaxial layer to produce N-polar material. Also disclosed herein is a composition having: a bulk III-N substrate; an inversion layer on portions of the substrate; and a III-N epitaxial layer on the inversion layer. The III-N epitaxial layer is of the opposite polarity of the surface of the substrate.03-22-2012
20120068188Defects Annealing and Impurities Activation in III-Nitride Compound Semiconductors - A GaN sample in a sealed enclosure is heated very fast to a high temperature above the point where GaN is thermodynamically stable and is then cooled down very fast to a temperature where it is thermodynamically stable. The time of the GaN exposure to a high temperature range above its thermodynamic stability is sufficiently short, in a range of few seconds, to prevent the GaN from decomposing. This heating and cooling cycle is repeated multiple times without removing the sample from the enclosure. As a result, by accumulating the exposure time in each cycle, the GaN sample can be exposed to a high temperature above its point of thermodynamic stability for a long time but the GaN sample integrity is maintained (i.e., the GaN doesn't decompose) due to the extremely short heating duration of each single cycle.03-22-2012
20090321745SEMICONDUCTOR LIGHT-EMITTING DEVICE - A semiconductor light-emitting device includes: a substrate; a first conductivity type layer formed on the substrate and including a plurality of group III-V nitride semiconductor layers of a first conductivity type; an active layer formed on the first conductivity type layer; and a second conductivity type layer formed on the active layer and including a group III-V nitride semiconductor layer of a second conductivity type. The first conductivity type layer includes an intermediate layer made of Al12-31-2009
20110220911SEMICONDUCTOR LIGHT-EMITTING DEVICE - According to one embodiment, a semiconductor light-emitting device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a light-emitting layer, a third semiconductor layer and a first electrode. The light-emitting layer is provided between the first and second semiconductor layers. The third semiconductor layer is provided on opposite side of the first semiconductor layer from the light-emitting layer, has a lower impurity concentration than the first semiconductor layer, and includes an opening exposing part of the first semiconductor layer. The first electrode is in contact with the first semiconductor layer through the opening. The third semiconductor layer further includes a rough surface portion which is provided on opposite side from the first semiconductor layer and includes a surface asperity larger than wavelength in the third semiconductor layer of peak wavelength of emission light emitted from the light-emitting layer.09-15-2011
20090085043SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - Disclosed are a semiconductor light emitting device, which can improve characteristics of the semiconductor light emitting device such as a forward voltage characteristic and a turn-on voltage characteristic, increase light emission efficiency by lowering an input voltage, and increase reliability of the semiconductor light emitting device by a low-voltage operation, and a method of manufacturing the same. The semiconductor light emitting device includes: an n-type GaN semiconductor layer; an active layer formed on a gallium face of the n-type GaN semiconductor layer; a p-type semiconductor layer formed on the active layer; and an n-type electrode formed on a nitrogen face of the n-type GaN semiconductor layer and including a lanthanum (La)-nickel (Ni) alloy.04-02-2009
20110140123Nitride-Based Transistors With a Protective Layer and a Low-Damage Recess - Transistors are fabricated by forming a nitride-based semiconductor barrier layer on a nitride-based semiconductor channel layer and forming a protective layer on a gate region of the nitride-based semiconductor barrier layer. Patterned ohmic contact metal regions are formed on the barrier layer and annealed to provide first and second ohmic contacts. The annealing is carried out with the protective layer on the gate region. A gate contact is also formed on the gate region of the barrier layer. Transistors having protective layer in the gate region are also provided as are transistors having a barrier layer with a sheet resistance substantially the same as an as-grown sheet resistance of the barrier layer.06-16-2011
20110140121ENHANCEMENT NORMALLY OFF NITRIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The present invention relates to an enhancement normally off nitride semiconductor device and a method of manufacturing the same. The method includes the steps of: forming a buffer layer on a substrate; forming a first nitride semiconductor layer on the buffer layer; forming a second nitride semiconductor layer on the first nitride semiconductor layer; etching a gate region above the second nitride semiconductor layer up to a predetermined depth of the first nitride semiconductor layer; forming an insulating film on the etched region and the second nitride semiconductor layer; patterning a source/drain region, etching the insulating film in the source/drain region, and forming electrodes in the source/drain region; and forming a gate electrode on the insulating film in the gate region. In this manner, the present invention provides a method of easily implementing a normally off enhancement semiconductor device by originally blocking 2DEG which is generated under a gate region. In addition, the present invention provides an enhancement normally off power semiconductor device with a simple and efficient driving circuit in a HEMT device.06-16-2011
20110227090Programmable III-Nitride Transistor with Aluminum-Doped Gate - Disclosed is a III-nitride heterojunction device that includes a conduction channel having a two dimensional electron gas formed at an interface between a first III-nitride material and a second III-nitride material. A modification including a contact insulator, for example, a gate insulator formed under a gate contact, is disposed over the conduction channel, wherein the contact insulator includes aluminum to alter formation of the two dimensional electron gas at the interface. The contact insulator can include AlSiN, or can be SiN doped with aluminum. The modification results in programming the threshold voltage of the III-nitride heterojunction device to, for example, make the device an enhancement mode device. The modification can further include a recess, an ion implanted region, a diffused region, an oxidation region, and/or a nitridation region. In one embodiment, the first III-nitride material comprises GaN and the second III-nitride material comprises AlGaN.09-22-2011
20090014728SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor layer and a first semiconductor element located in the first semiconductor layer. The semiconductor device also includes a second semiconductor layer of a transparent semiconductor material. The second semiconductor layer is disposed on the first semiconductor layer covering the first semiconductor element. The semiconductor device also includes a second semiconductor element located in the second semiconductor layer. The semiconductor device also includes a wire extending within the second semiconductor layer and electrically connecting the first and second semiconductor elements.01-15-2009
20120104413LIGHT EMITTING SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING - The light emitting semiconductor device (05-03-2012
20120104411TEXTURED III-V SEMICONDUCTOR - A method for fabricating a III-nitride semiconductor film, comprising depositing or growing a III-nitride semiconductor film in a semiconductor light absorbing or light emitting device structure; and growing a textured or structured surface of the III-nitride nitride semiconductor film in situ with the growing or the deposition of the III-nitride semiconductor film, by controlling the growing of the III-nitride semiconductor film to obtain a texture of the textured surface, or one or more structures of the structured surface, that increase output power of light from the light emitting device, or increase absorption of light in the light absorbing device.05-03-2012
20120104410Reflector, Manufacture Method Thereof And Light-Emitting Device Including The Reflector - A reflector for a GaN-based light-emitting device, method for manufacturing the reflector and GaN-haled light-emitting device including the reflector are provided. The reflector is formed on a p-type GaN-based epitaxial layer and includes: a whisker crystal of un-doped GaN, formed on a surface of the p-type GaN-based epitaxial layer with a predefined density distribution and at a position that corresponds to a dislocation defect of an epitaxial layer; and a metal reflective layer, formed on both the p-type GaN-based epitaxial layer and the whisker crystal. The whisker of un-doped GaN is positioned on the dislocation defect of the p-type GaN-based epitaxial layer, so that the Ag reflective layer can be separated from the dislocation defect of the p-type GaN-based epitaxial layer, thereby effectively preventing Ag from moving inside the dislocation defect via electromigration, and largely decreasing the possibility of current leakage of the light-emitting device including the Ag reflector.05-03-2012
20120104409FORMING LIGHT-EMITTING DIODES USING SEED PARTICLES - A seed layer for growing a group III-V semiconductor structure is embedded in a dielectric material on a carrier substrate. After the group III-V semiconductor structure is grown, the dielectric material is removed by wet etch to detach the carrier substrate. The group III-V semiconductor structure includes a thick gallium nitride layer of at least 100 microns or a light-emitting structure.05-03-2012
20120104408SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In an aspect of a semiconductor device, there are provided a substrate, a transistor including an electron transit layer and an electron supply layer formed over the substrate, a nitride semiconductor layer formed over the substrate and connected to a gate of the transistor, and a controller controlling electric charges moving in the nitride semiconductor layer.05-03-2012
20120104407LIGHT EMITTING DIODE AND METHOD FOR MANUFACTURING THE SAME - An LED includes a substrate, a first n-type GaN layer, a connecting layer, a second n-type GaN layer, a light emitting layer, and a p-type GaN layer. The first n-type GaN layer is formed on the substrate, the first n-type GaN layer has a first surface facing away from the substrate, and the first surface includes a first area and a second area. The connecting layer, the second n-type GaN layer, the light emitting layer, and the p-type GaN layer are formed on the first area in sequence. The connecting layer is etchable by alkaline solution; a bottom surface of the second n-type GaN layer facing towards the connecting layer has a roughened exposed portion; the GaN on the bottom surface of the second n-type GaN layer is N-face GaN.05-03-2012
20080283844Method for manufacturing a field effect transistor having a field plate - An opening for forming a gate electrode is provided by a first photoresist pattern formed on an insulating film. Reactive ion etching by inductively coupled plasma is applied to the insulating film through the first photoresist pattern as a mask to thereby expose the surface of a GaN semiconductor layer, evaporating thereon a gate metal such as NiAu, thereby forming the gate electrode by self-aligned process. This prevents an oxidized film from being formed on the surface of the semiconductor layer. After the gate electrode is formed, a second photoresist pattern is formed to form a field plate on the gate electrode and the insulating film through the second photoresist pattern as a mask. Thereby, Ti having a high adhesiveness with an insulating film made of SiN or the like can be used as a field plate metal.11-20-2008
20100264424GaN LAYER CONTAINING MULTILAYER SUBSTRATE, PROCESS FOR PRODUCING SAME, AND DEVICE - A GaN layer-containing multilayer substrate employing as a substrate a single crystal that can be made to have a large diameter, a process for producing same, and a device employing the multilayer substrate. The process for producing a multilayer substrate of the present invention includes a germanium growing step of heteroepitaxially growing a germanium layer above a (111) silicon substrate by chemical vapor deposition, a heat treatment step of carrying out a heat treatment of the obtained germanium layer above the silicon substrate in a temperature range of 700° C. to 900° C., and subsequently a GaN growing step of heteroepitaxially growing a GaN layer above the germanium layer.10-21-2010
20090256159GaN semiconductor device - This invention discloses a GaN semiconductor device comprising a substrate; a metal-rich nitride compound thin film on the substrate; a buffer layer formed on the metal-rich nitride compound thin film, and a semiconductor stack layer on the buffer layer wherein the metal-dominated nitride compound thin film covers a partial upper surface of the substrate. Because metal-rich nitride compound is amorphous, the epitaxial growth direction of the buffer layer grows upwards in the beginning and then turns laterally, and the epitaxy defects of the buffer layer also bend with the epitaxial growth direction of the buffer layer. Therefore, the probability of the epitaxial defects extending to the semiconductor stack layer is reduced and the reliability of the GaN semiconductor device is improved.10-15-2009
20100155739LIGHT-EMITTING DEVICE, METHOD FOR MANUFACTURING SAME, MOLDED BODY AND SEALING MEMBER - Disclosed is a light-emitting device comprising a light-emitting element (06-24-2010
20110127539NITRIDE SEMICONDUCTOR LIGHT-EMITTING DEVICE - A nitride semiconductor light-emitting device includes an n type nitride semiconductor layer, a light-emitting layer formed on the n type nitride semiconductor layer, a first p type nitride semiconductor layer formed on the light-emitting layer, an intermediate layer formed on the first p type nitride semiconductor layer to alternately cover and expose a surface of the first p type nitride semiconductor layer, and a second p type nitride semiconductor layer formed on the intermediate layer. The intermediate layer is made of a compound containing Si and N as constituent elements.06-02-2011
20100148185FLIP-CHIP LIGHT-EMITTING DIODE DEVICE - A flip-chip light-emitting diode (LED) device is provided. The flip-chip LED device includes a substrate, an n-GaN layer, an epitaxy layer, a p-GaN layer, a first electrode, and a second electrode. The n-GaN layer is formed on a surface of the substrate. The epitaxy layer is formed on the n-GaN layer. The p-GaN layer is formed on the epitaxy layer. The first electrode has a first polarity and is formed on the p-GaN layer. The first electrode substantially covers the p-GaN layer. The second electrode is formed on the n-GaN layer and has a second polarity opposite to the first polarity.06-17-2010
20100155738Light Emitting Diode and Method for Manufacturing Same - This invention provides a light emitting diode in which a thick transparent conductive electrode is formed on an emitting side of GaN based semiconductor light emitting element, and a light emitting efficiency of the GaN semiconductor light emitting element is improved. Further, it provides a manufacturing method of the light emitting diode by which a thick transparent electrode film of the light emitting diode is effectively formed. A light emitting diode which emits light in a blue or an ultraviolet region comprising a substrate and a light emitting layer thereon comprising at least an n-type GaN based semiconductor layer, a p-type GaN based semiconductor layer, and a GaN based semiconductor sandwiched between them, wherein a transparent conductive film having a thickness of 1-100 μm is provided on the light emitting layer.06-24-2010
20100155741COMPOUND SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A compound semiconductor device includes a carrier transit layer including GaN formed over a substrate; a carrier supply layer including GaN formed over the carrier transit layer; a source electrode and a drain electrode formed over the carrier supply layer; a first compound semiconductor layer including N in which a first opening is formed and that is located between the source electrode and the drain electrode over the carrier supply layer; a gate electrode extending from within the first opening to above the first compound semiconductor layer; and an insulator layer having a second opening that is smaller than the first opening, and insulating the gate electrode and the first compound semiconductor layer within the first opening. The gate electrode extends from within the second opening to above the first compound semiconductor layer.06-24-2010
20100187540GROUP III NITRIDE SUBSTRATE, EPITAXIAL LAYER-PROVIDED SUBSTRATE, METHODS OF MANUFACTURING THE SAME, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A group III nitride substrate on which an epitaxially grown layer of good quality can be formed, and a method of manufacturing the same are obtained. A GaN substrate is one of the following: a group III nitride substrate, wherein the number of atoms of an acid material per square centimeter of a surface is not more than 2×1007-29-2010
20100187541Doped Aluminum Nitride Crystals and Methods of Making Them - Fabrication of doped AlN crystals and/or AlGaN epitaxial layers with high conductivity and mobility is accomplished by, for example, forming mixed crystals including a plurality of impurity species and electrically activating at least a portion of the crystal.07-29-2010
20100258812GROUP-III NITRIDE SEMICONDUCTOR FREESTANDING SUBSTRATE AND MANUFACTURING METHOD OF THE SAME - To provide a group-III nitride semiconductor freestanding substrate, with carrier concentration of a peripheral part of a n-type group-III nitride semiconductor freestanding substrate set to be lower than the carrier concentration inside of the peripheral part. In this freestanding substrate, preferably value Δσ obtained by dividing a difference between a maximum value of the carrier concentration and a minimum value of the carrier concentration in a surface of the freestanding substrate by the maximum value of the carrier concentration is greater than 0.05, and the carrier concentration in any place in the surface of the freestanding substrate exceeds 5.0×1010-14-2010
20110042680LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING SAME - A light emitting device includes: a conductive substrate; a metal film provided above the conductive substrate; a light emitting layer provided above the metal film; an electrode provided partly above the light emitting layer; and a current suppression layer being in contact with the metal film, provided in a region including at least part of an immediately underlying region of the electrode, and configured to suppress current, a first portion of the metal film including at least part of a portion located between the current suppression layer and the electrode, being separated from an portion other than the first portion.02-24-2011
20100181576Epitaxial Structure Having Low Defect Density - An epitaxial structure having a low defect density includes: a base layer; a first epitaxial layer having a plurality of concentrated defect groups, and an epitaxial surface that has a plurality of first recesses corresponding in position to the concentrated defect groups, the sizes of the first recesses being close to each other; and a plurality of defect-termination blocks respectively and filling the first recesses and having polished surfaces. The defect-termination blocks are made of a material which is different in removal rate from that of the first epitaxial layer. The polished surfaces are substantially flush with the epitaxial surface so that the first epitaxial layer has a substantially planarized crystal growth surface07-22-2010
20120032182SOLID STATE LIGHTS WITH THERMAL CONTROL ELEMENTS - A solid state light (“SSL”), a solid state emitter (“SSE”), and methods of manufacturing SSLs and SSEs. In one embodiment, an SSL comprises a packaging substrate having an electrical contact and a light emitting structure having a front side and a back side. The back side of the light emitting structure is superimposed with the electrical contact of the packaging substrate. The SSL can further include a temperature control element aligned with the light emitting structure and the electrical contact of the packaging substrate.02-09-2012
20120032185LEAKAGE BARRIER FOR GaN BASED HEMT ACTIVE DEVICE - An improved HEMT formed from a GaN material system is disclosed which has reduced gate leakage current and eliminates the problem of current constrictions resulting from deposition of the gate metal over the step discontinuities formed over the gate mesa. One or more GaN based materials are layered and etched to form a gate mesa with step discontinuities defining source and drain regions. In order to reduce the leakage current, the step discontinuities are back-filled with an insulating material, such as silicon nitride (SiN), forming a flat surface relative to the source and drain regions, to enable to the gate metal to lay flat. By back-filling the source and drain regions with an insulating material, leakage currents between the gate and source and the gate and drain are greatly reduced. In addition, current constrictions resulting from the deposition of the gate metal over a step discontinuity are virtually eliminated.02-09-2012
20120032184SYSTEMS AND METHODS FOR PRODUCING WHITE-LIGHT LIGHT EMITTING DIODES - A vertical light-emitting diode (VLED) includes a metal substrate, a p-electrode coupled to the metal substrate, a p-contact coupled to the p-electrode, a p-GaN portion coupled to the p-electrode, an active region coupled to the p-GaN portion, an n-GaN portion coupled to the active region, and a phosphor layer coupled to the n-GaN portion.02-09-2012
20120032187Lattice-Mismatched GaInP LED Devices and Methods of Fabricating Same02-09-2012
20130214283Power Transistor Having Segmented Gate - There are disclosed herein various implementations of a transistor having a segmented gate region. Such a transistor may include at least one segmentation dielectric segment and two or more gate dielectric segments. The segmentation dielectric segment or segments are thicker than the gate dielectric segments, and is/are situated between the gate dielectric segments. The segmentation dielectric segment or segments cause an increase in the effective gate length so as to improve resistance to punch-through breakdown between a drain electrode and a source electrode of the transistor when the transistor is off.08-22-2013
20130214284METHOD FOR THE REUSE OF GALLIUM NITRIDE EPITAXIAL SUBSTRATES - A method for the reuse of gallium nitride (GaN) epitaxial substrates uses band-gap-selective photoelectrochemical (PEC) etching to remove one or more epitaxial layers from bulk or free-standing GaN substrates without damaging the substrate, allowing the substrate to be reused for further growth of additional epitaxial layers. The method facilitates a significant cost reduction in device production by permitting the reuse of expensive bulk or free-standing GaN substrates.08-22-2013
20130214285Semiconductor Component and Method for Producing a Semiconductor Component - A semiconductor component has a semiconductor layer sequence made of a nitridic composite semiconductor material on a substrate. The substrate includes a silicon surface facing the semiconductor layer sequence. The semiconductor layer sequence includes an active region and at least one intermediate layer made of an oxygen-doped AN composite semiconductor material between the substrate and the active region.08-22-2013
20130214286Method of Manufacturing Light Emitting Device - To make a light emitting device, a light emitting element is placed in a recess of a package, powders having a fluorescent material and coated with inorganic particles are provided, the fluorescent powders, fillers and a resin are mixed, the light emitting element placed in the recess of the package is sealed with the resin, and a centrifugal force is applied to the sealed package so that the fluorescent powders and the fillers sediment are pushed toward a bottom of the recess.08-22-2013
20130214287SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device is provided with: a GaN layer; an anode electrode that forms a Schottky junction with a Ga face of the GaN layer; and an InGaN layer positioned between at least a part of the anode electrode and the GaN layer.08-22-2013
20130214288NITRIDE SEMICONDUCTOR LIGHT-EMITTING ELEMENT AND MANUFACTURING METHOD THEREFOR - A nitride-based semiconductor light-emitting device of an embodiment includes a semiconductor multilayer structure having a growing plane which is an m-plane and being made of a GaN-based semiconductor. The semiconductor multilayer structure includes a n-type semiconductor layer, a p-type semiconductor layer, a p-side electrode provided on the p-type semiconductor layer, and an active layer interposed between the n-type semiconductor layer and the p-type semiconductor layer. The ratio of the thickness of the active layer to the thickness of the n-type semiconductor layer, D, is in the range of 1.8×1008-22-2013
20100187542SEMICONDUCTOR LIGHT EMITTING ELEMENT AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a semiconductor light emitting element from a wafer in which a gallium nitride compound semiconductor has been laminated on a sapphire substrate having an orientation flat, comprises of: laminating a semiconductor layer on a first main face of the sapphire substrate having an off angle θ in a direction Xo parallel to the orientation flat; forming a first break groove that extends in a direction Y substantially perpendicular to the direction Xo, on the semiconductor layer side; forming a second break line that is shifted by a predetermined distance in the ±Xo direction from a predicted split line within the first break groove and parallel to the first break groove in the interior of the sapphire substrate and corresponding to the inclination of the off angle θ; and splitting the wafer along the first and/or second break line.07-29-2010
20100258814Light emitting diode and method of fabrication thereof - There is provided a light emitting diode fabricating method including: a) forming, on a substrate and via a buffer layer, an epitaxial growth layer that includes a light emitting layer, and forming one electrode on a surface of the epitaxial growth layer; b) joining a supporting substrate to the one electrode; c) removing, by etching, the substrate and the buffer layer; and d) forming another electrode at a region, other than a region where output light is taken-out, at a reverse surface opposite the surface of the epitaxial growth layer on which the one electrode is formed.10-14-2010
20100258813Light Emitting Device and Fabrication Thereof - A light emitting diode of the invention via laser scribing method is used to build up the mesh texture on the backside of the sapphire of light emitting diodes. Then high reflectivity and thermal conductivity metals are deposited onto the mesh structure. Since the multiple-reflection from the texture, the light extraction efficiency will be increased. Meanwhile, the high thermal conductivity metal filled into the sapphire also lead to the better heat dissipation within the light emitting diodes, it will decrease the junction temperature and avoid the thermal effect to reduce light efficiency and the lifetime.10-14-2010
20120228626SEMICONDUCTOR DEVICE AND ITS FABRICATION METHOD - In a semiconductor device including a stack structure having heterojunction units formed by alternately stacking GaN (gallium nitride) films and barrier films which are different in forbidden band width, a first electrode formed in a Schottky barrier contact with one sidewall of the stack structure, and a second electrode formed in contact with the other sidewall, an oxide film is interposed between the first electrode and the barrier films. Therefore, the reverse leakage current is prevented from flowing through defects remaining in the barrier films due to processing of the barrier films, so that a reverse leakage current of a Schottky barrier diode is reduced.09-13-2012
20100181577NITRIDE SEMICONDUCTOR SUBSTRATE - There is provided a nitride semiconductor substrate. The nitride semiconductor substrate comprises a substrate, a patterned epitaxy layer, a protective layer and a gallium nitride semiconductor layer. The patterned epitaxy layer is disposed on the substrate, wherein the patterned epitaxy layer comprises a pier structure and the patterned epitaxy layer has an upper surface and a lower surface opposite to the upper surface and the lower surface faces to the substrate. The protective layer covers a portion of the upper surface of the patterned epitaxy layer to expose a top surface of the pier structure. The gallium nitride (GaN) semiconductor layer extends substantially across an entire area above the patterned epitaxy layer and connected to the exposed top surface of the pier structure.07-22-2010
20100213468LIGHT EMITTING DEVICE HAVING A PLURALITY OF LIGHT EMITTING CELLS AND METHOD OF FABRICATING THE SAME - Disclosed is a light emitting device having a plurality of light emitting cells. The light emitting device comprises a thermally conductive substrate, such as a SiC substrate, having a thermal conductivity higher than that of a sapphire substrate. The plurality of light emitting cells are connected in series on the thermally conductive substrate. Meanwhile, a semi-insulating buffer layer is interposed between the thermally conductive substrate and the light emitting cells. For example, the semi-insulating buffer layer may be formed of AlN or semi-insulating GaN. Since the thermally conductive substrate having a thermal conductivity higher than that of a sapphire substrate is employed, heat-dissipating performance can be enhanced as compared with a conventional sapphire substrate, thereby increasing the maximum light output of a light emitting device that is driven under a high voltage AC power source. In addition, since the semi-insulating buffer layer is employed, it is possible to prevent an increase in a leakage current through the thermally conductive substrate and between the light emitting cells.08-26-2010
20100155740SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A cavity-containing layer having a plurality of cavities is formed on a growth substrate by carrying out in alternating fashion a plurality of cycles of a first and second growth steps of growing a group III nitride at growth rates different from each other. The semiconductor epitaxial layer is subsequently formed on the cavity-containing layer, after which a support substrate is bonded to the semiconductor epitaxial layer. The growth substrate is separated from the cavity-containing layer.06-24-2010
20100276699Silicon Carbide and Related Wide Bandgap Semiconductor Based Optically-Controlled Power Switching Devices - An optically-controlled power switch for use as an electrical switch is generally provided. The device can include a wide bandgap semiconducting material defining a stack having a p-n junction, a metal mask overlying the top surface of the stack and defining at least one opening to allow light to pass through the metal mask; a first lead wire connected to the metal stack; and a second lead wire connected to the bottom surface of the stack.11-04-2010
20100276700 EXTERNAL EXTRACTION LIGHT EMITTING DIODE BASED UPON CRYSTALLOGRAPHIC FACETED SURFACES - A light emitting diode is disclosed that includes a support structure and a Group III nitride light emitting active structure mesa on the support structure. The mesa has its sidewalls along an indexed crystal plane of the Group III nitride. A method of forming the diode is also disclosed that includes the steps of removing a substrate from a Group III nitride light emitting structure that includes a sub-mount structure on the Group III nitride light emitting structure opposite the substrate, and thereafter etching the surface of the Group III nitride from which the substrate has been removed with an anisotropic etch to develop crystal facets on the surface in which the facets are along an index plane of the Group III nitride. The method can also include etching the light emitting structure with an anisotropic etch to form a mesa with edges along an index plane of the Group III nitride.11-04-2010
20100230685LIGHT EMITTING DEVICE, LIGHT EMITTING DEVICE PACKAGE AND LIGHTING SYSTEM INCLUDING THE SAME - Provided are a light emitting device, a light emitting device package and a lighting system including the same. The light emitting device (LED) comprises a light emitting structure comprising a second conductive type semiconductor layer, an active layer, and a first conductive type semiconductor layer and a first electrode over the light emitting structure. A portion of the light emitting structure is sloped at a predetermined angle.09-16-2010
20120138951SEMICONDUCTOR CHIP AND PROCESS FOR PRODUCTION THEREOF - A semiconductor chip of the present invention is a semiconductor device that includes a hexagonal semiconductor layer having anisotropic mechanical properties. A semiconductor chip (06-07-2012
20120138947Epitaxial Structure With An Epitaxial Defect Barrier Layer And Methods Making The Same - An epitaxial structure for an LED is provided. The epitaxial structure includes a patterned epitaxial defect barrier layer disposed over a first portion of a substantially flat substrate to expose a second portion of the substrate. The epitaxial structure also includes a patterned buffer layer over the second portion of the substrate. The epitaxial structure further includes a first semiconductor layer over the patterned buffer layer and the patterned epitaxial defect barrier layer, an active layer over the first semiconductor layer, and a second semiconductor layer over the active layer.06-07-2012
20120126241GROUP III NITRIDE SEMICONDUCTOR LIGHT-EMITTING DEVICE AND PRODUCTION METHOD THEREFOR - A Group III nitride semiconductor light-emitting device includes a sapphire substrate having an embossment on a surface thereof; and an n-type layer, a light-emitting layer, and a p-type layer, which are sequentially stacked on the embossed surface of the sapphire substrate via a buffer layer, and each of which is formed of a Group HI nitride semiconductor. The embossment has a structure including a first stripe-pattern embossment which is formed on a surface of the sapphire substrate, and whose stripe direction corresponds to the x-axis direction; and a second stripe-pattern embossment which is formed atop the first stripe-pattern embossment, and whose stripe direction corresponds to the y-axis direction, the y-axis direction being orthogonal to the x-axis direction.05-24-2012
20120126240Wafer level packaged GaN power device and the manufacturing method thereof - Disclosed are a GaN-based compound power semiconductor device and a manufacturing method thereof, in which on a GaN power semiconductor element, a contact pad is formed for flip-chip bonding, and a bonding pad of a module substrate to be mounted with the GaN power semiconductor element is formed with a bump so as to modularize an individual semiconductor element. In the disclosed GaN-based compound power semiconductor device, an AlGaN HEMT element is flip-chip bonded to the substrate, so that heat generated from the element can be efficiently radiated.05-24-2012
20120126239LAYER STRUCTURES FOR CONTROLLING STRESS OF HETEROEPITAXIALLY GROWN III-NITRIDE LAYERS - A III-N layer structure is described that includes a III-N buffer layer on a foreign substrate, an additional III-N layer, a first III-N structure, and a second III-N layer structure. The first III-N structure atop the III-N buffer layer includes at least two III-N layers, each having an aluminum composition, and the III-N layer of the two III-N layers that is closer to the III-N buffer layer having the larger aluminum composition. The second III-N structure includes a III-N superlattice, the III-N superlattice including at least two III-N well layers interleaved with at least two III-N barrier layer. The first III-N structure and the second III-N structure are between the additional III-N layer and the foreign substrate.05-24-2012
20100140627Package for Semiconductor Devices - A packaged semiconductor device including a semiconductor die mounted on a header of a leadframe. A plurality of spaced external conductors extends from the header and at least one of the external conductors has a bond wire post at one end thereof such that a bonding wire extends between the bond wire post and the semiconductor die. The package device also includes a housing, which encloses the semiconductor die, the header, the bonding wire and the bonding wire post resulting in an insulated packaged device.06-10-2010
20090309105Methods for producing improved crystallinity group III-nitride crystals from initial group III-Nitride seed by ammonothermal Growth - The present invention discloses methods to create higher quality group III-nitride wafers that then generate improvements in the crystalline properties of ingots produced by ammonothermal growth from an initial defective seed. By obtaining future seeds from carefully chosen regions of an ingot produced on a bowed seed crystal, future ingot crystalline properties can be improved. Specifically, the future seeds are optimized if chosen from an area of relieved stress on a cracked ingot or from a carefully chosen N-polar compressed area. When the seeds are sliced out, miscut of 3-10° helps to improve structural quality of successive growth. Additionally a method is proposed to improve crystal quality by using the ammonothermal method to produce a series of ingots, each using a specifically oriented seed from the previous ingot. When employed, these methods enhance the quality of Group III nitride wafers and thus improve the efficiency of any subsequent device.12-17-2009
20080296584III-V Nitride Semiconductor Layer-Bonded Substrate and Semiconductor Device - Affords III-V nitride semiconductor layer-bonded substrates from which semiconductor device of enhanced properties can be manufactured, and semiconductor devices incorporating the III-V nitride semiconductor layer-bonded substrates. The III-V nitride semiconductor layer-bonded substrate, in which a III-V nitride semiconductor layer and a base substrate are bonded together, is characterized in that thermal expansion coefficient difference between the III-V nitride semiconductor layer and the base substrate is 4.5×1012-04-2008
20100252834METHOD FOR GROWING GROUP III-V NITRIDE FILM AND STRUCTURE THEREOF - A method for growing a Group III-V nitride film and a structure thereof are presented. The method is carried out by hydride vapor phase epitaxy (HVPE). The method includes the steps of, inter alia, slowly epitaxially growing a temperature ramping nitride layer on a substrate by rising a first growth temperature of 900-950° C. to a second growth temperature of 1000-1050° C. at a temperature-rising rate of 0.5-10° C./min. The lattice quality of the temperature ramping nitride layer is slowly transformed with the layer height, so that a stress induced by lattice mismatch between a sapphire substrate and a gallium nitride (GaN) layer is relieved.10-07-2010
20100252835NITRIDE SEMICONDUCTOR AND NITRIDE SEMICONDUCTOR CRYSTAL GROWTH METHOD - A base at least one principal plane of which is a nitride is prepared for use in epitaxial growth. The base is placed on a susceptor in an epitaxial growth reactor and heated to a predetermined temperature (step A). The heating is started with inactive, nitrogen gas being supplied into the reactor. Then, active, NH10-07-2010
20120241751NITRIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a nitride semiconductor device includes a first semiconductor layer, a second semiconductor layer, a first electrode, a second electrode, a third electrode, a first insulating film and a second insulating film. The first semiconductor layer includes a nitride semiconductor. The second semiconductor layer is provided on the first layer, includes a nitride semiconductor, and includes a hole. The first electrode is provided in the hole. The second electrode is provided on the second layer. The third electrode is provided on the second layer so that the first electrode is disposed between the third and second electrodes. The first insulating film is provided between the first electrode and an inner wall of the hole and between the first and second electrodes, and is provided spaced from the third electrode. The second insulating film is provided in contact with the second layer between the first and third electrodes.09-27-2012
20130126890INTEGRATING ACTIVE MATRIX INORGANIC LIGHT EMITTING DIODES FOR DISPLAY DEVICES - A method of forming an active matrix, light emitting diode (LED) array includes removing, from a base substrate, a layer of inorganic LED material originally grown thereupon; and bonding the removed layer of inorganic LED material to an active matrix, thin film transistor (TFT) backplane array.05-23-2013
20130126894LOW VOLTAGE DIODE WITH REDUCED PARASITIC RESISTANCE AND METHOD FOR FABRICATING - A method of making a diode begins by depositing an Al05-23-2013
20130126899SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor light emitting device includes: a light emitting structure including a first conductive type semiconductor layer, a second conductive type semiconductor layer and an active layer between the first conductive type semiconductor layer and the second conductive type semiconductor layer; and a first electrode on the first conductive type semiconductor layer, wherein the light emitting structure includes an outer groove formed at an outer area of the light emitting structure, wherein a thickness of an outmost area of the light emitting structure is smaller than a thickness of an center area of the light emitting structure, and wherein the first conductive type semiconductor layer includes AlGaN layer and the second conductive type semiconductor layer includes AlGaN layer.05-23-2013
20120241756High Voltage Composite Semiconductor Device with Protection for a Low Voltage Device - There are disclosed herein various implementations of composite semiconductor devices including a voltage protected device. In one exemplary implementation, a normally OFF composite semiconductor device comprises a normally ON III-nitride power transistor having a first output capacitance, and a low voltage (LV) device cascoded with the normally ON III-nitride power transistor to form the normally OFF composite semiconductor device, the LV device having a second output capacitance. A ratio of the first output capacitance to the second output capacitance is set based on a ratio of a drain voltage of the normally ON III-nitride power transistor to a breakdown voltage of the LV device so as to provide voltage protection for the LV device.09-27-2012
20120241753SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to an embodiment, a semiconductor device includes a substrate, a nitride layer and a nitride semiconductor layer. The substrate includes an indented structure provided at a major surface. The nitride layer provided entirely on the major surface is at least one of polycrystalline and amorphous, and includes at least one of p-type impurity and n-type impurity. The nitride semiconductor layer is provided on the nitride layer.09-27-2012
20120241752LOW CONTACT RESISTANCE SEMICONDUCTOR STRUCTURE AND METHOD OF FABRICATING THE SAME - A low contact resistance semiconductor structure includes a substrate, a semiconductor stacked layer, a low contact resistance layer and a transparent conductive layer. The low contact resistance layer is formed on one side of a P-type GaN layer of the semiconductor stacked layer. The low contact resistance layer is formed at a thickness smaller than 100 Angstroms and made of a material selected from the group consisting of aluminum, gallium, indium, and combinations thereof. Through the low contact resistance layer, the resistance between the P-type GaN layer and transparent conductive layer can be reduced and light emission efficiency can be improved when being used on LEDs. The method of fabricating the low contact resistance semiconductor structure of the invention forms a thin and consistent low contact resistance layer through a Metal Organic Chemical Vapor Deposition (MOCVD) method to enhance matching degree among various layers.09-27-2012
20100127275GAN-BASED FIELD EFFECT TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - A GaN-based field effect transistor 05-27-2010
20110057201LED Element with a Thin-layer Semiconductor Element Made of Gallium Nitride - An LED module comprising an LED chip, with an active gallium nitride layer and a silicon platform on which the LED chip is arranged, wherein the silicon platform has two electrodes on the side facing away from the LED chip which are electrically connected to the LED chip and wherein the thickness of the gallium nitride layer of the LED chip is between 2 μm and 10 μm, preferably 1 μm to 5 μm.03-10-2011
20100127274Thin film light emitting diode - Light emitting LEDs devices comprised of LED chips that emit light at a first wavelength, and a thin film layer over the LED chip that changes the color of the emitted light. For example, a blue LED chip can be used to produce white light. The thin film layer beneficially consists of a florescent material, such as a phosphor, and/or includes tin. The thin film layer is beneficially deposited using chemical vapor deposition.05-27-2010
20110057199Antistatic Gallium Nitride Based Light Emitting Device and Method for Fabricating the Same - The invention provides an antistatic gallium nitride based light emitting device and a method for fabricating the same. The method includes: growing an n-type GaN-based epitaxial layer, an active layer, a p-type GaN-based epitaxial layer and an undoped GaN-based epitaxial layer sequentially on a substrate; etching to remove parts of the layers above, to expose a part of the n-type GaN-based epitaxial layer, with the unetched part defined as an emitting area; etching to remove a part of the undoped GaN-based epitaxial layer; forming an ohmic contact electrode on an exposed part of p-type GaN-based epitaxial layer, and forming a Schottky contact electrode on another part; forming a p-electrode on a transparent conducting layer such that the p-electrode is electrically connected with the ohmic contact electrode; forming an n-electrode on the exposed n-type GaN-based epitaxial layer; and forming a connecting conductor on an insulation layer such that the connecting conductor is electrically connected with the n-electrode and the Schottky contact electrode. By forming a GaN Schottky diode directly on a p-type GaN-based epitaxial layer, the fabrication process is simplified while providing antistatic ability at the same time, and the emitting area is made the maximum use of so as to avoid the drop in the luminous efficiency of the GaN-based LED.03-10-2011
20110057197GaN SINGLE CRYSTAL SUBSTRATE AND METHOD OF MANUFACTURING THEREOF AND GaN-BASED SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF - A GaN single crystal substrate has a main surface with an area of not less than 10 cm03-10-2011
20110057196GaN HEMT with Nitrogen-Rich Tungsten Nitride Schottky Gate and Method of Forming the Same - A GaN HEMT with Schottky gate is disclosed. The GaN HEMT sequentially has a GaN layer, an AlGaN layer, and a Schottky gate on a substrate, and a source and a drain on two sides of the Schottky gate. The Schottky gate is made by a material of nitrogen-rich tungsten nitride, which has a nitrogen content of about 0.5 molar ratio.03-10-2011
20100244046NITRIDE SEMICONDUCTOR DEVICE - On a processed substrate having an engraved region as a depressed portion formed thereon, a nitride semiconductor thin film is laid. The sectional area occupied by the nitride semiconductor thin film filling the depressed portion is 0.8 times the sectional area of the depressed portion or less.09-30-2010
20110127540SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate on which a GaN channel layer, an AlGaN electron supply layer and a GaN cap layer are stacked in this order, a gate electrode formed on the GaN cap layer, and a source electrode and a drain electrode formed on the AlGaN electron supply layer so as to interpose the gate electrode. A first recess is formed in the GaN cap layer and being located between the gate electrode and the source electrode. A thickness of the GaN cap layer in a bottom of the first recess is less than that of the GaN cap layer located under the gate electrode.06-02-2011
20120193638METHOD FOR HETEROEPITAXIAL GROWTH OF HIGH-QUALITY N-FACE GaN, InN, AND AIN AND THEIR ALLOYS BY METAL ORGANIC CHEMICAL VAPOR DEPOSITION - Methods for the heteroepitaxial growth of smooth, high quality films of N-face GaN film grown by MOCVD are disclosed. Use of a misoriented substrate and possibly nitridizing the substrate allow for the growth of smooth N-face GaN and other Group III nitride films as disclosed herein. The present invention also avoids the typical large (μm sized) hexagonal features which make N-face GaN material unacceptable for device applications. The present invention allows for the growth of smooth, high quality films which makes the development of N-face devices possible.08-02-2012
20120193639GaN-BASED SEMICONDUCTOR ELEMENT - A GaN-based semiconductor element includes a substrate, a buffer layer formed on the substrate, including an electrically conductive portion, an epitaxial layer formed on the buffer layer, and a metal structure in ohmic contact with the electrically conductive portion of the buffer layer for controlling an electric potential of the buffer layer.08-02-2012
20120193637LOW GATE-LEAKAGE STRUCTURE AND METHOD FOR GALLIUM NITRIDE ENHANCEMENT MODE TRANSISTOR - The present disclosure provides a semiconductor structure. The semiconductor structure includes a gallium nitride (GaN) layer on a substrate; an aluminum gallium nitride (AlGaN) layer disposed on the GaN layer; and a gate stack disposed on the AlGaN layer. The gate stack includes a III-V compound n-type doped layer; a III-V compound p-type doped layer adjacent the III-V compound n-type doped layer; and a metal layer formed over the III-V compound p-type doped layer and the III-V compound n-type doped layer.08-02-2012
20120193636Very high transmittance, back-illuminated, silicon-on-sapphire semiconductor wafer substrate for high quantum efficiency and high resolution, solid-state, imaging focal plane arrays - An advanced, very high transmittance, back-illuminated, silicon-on-sapphire wafer substrate design is presented for enabling high quantum efficiency and high resolution, silicon or silicon-germanium avalanche photodiode detector arrays. The wafer substrate incorporates a stacked antireflective bilayer between the sapphire and silicon layers, comprised of single crystal aluminum nitride (AlN) and non-stoichiometric, silicon rich, amorphous silicon nitride (a-SiN08-02-2012
20090127564GaN Substrate Manufacturing Method, GaN Substrate, and Semiconductor Device - A GaN substrate manufacturing method characterized in including a step of processing the surface of a substrate composed of a GaN single crystal into a concavely spherical form, based on differences in orientation of the crystallographic axis across the substrate surface. Processing the GaN substrate surface into a concavely spherical form reduces, in the post-process GaN substrate surface, differences in orientation of the crystallographic axis with respect to a normal. Furthermore, employing to manufacture semiconductor devices a GaN substrate in which differences in orientation of the crystallographic axis have been reduced makes it possible to uniformize in device characteristics a plurality of semiconductor devices fabricated from a single GaN substrate, which contributes to improving yields in manufacturing the semiconductor devices.05-21-2009
20090140262FIELD-EFFECT TRANSISTOR - A field-effect transistor includes a carrier transport layer made of nitride semiconductor, a gate electrode having first and second sidewall surfaces on first and second sides, respectively, an insulating film formed directly on the gate electrode to cover at least one of the first and second sidewall surfaces, first and second ohmic electrodes formed on the first and second sides, respectively, a passivation film including a first portion extending from the first ohmic electrode toward the gate electrode to cover a surface area between the first ohmic electrode and the gate electrode and a second portion extending from the second ohmic electrode toward the gate electrode to cover a surface area between the second ohmic electrode and the gate electrode, wherein the insulating film is in direct contact with at least the first and second passivation film portions, and has a composition different from that of the passivation film.06-04-2009
20080308813HIGH BREAKDOWN ENHANCEMENT MODE GALLIUM NITRIDE BASED HIGH ELECTRON MOBILITY TRANSISTORS WITH INTEGRATED SLANT FIELD PLATE - High breakdown enhancement mode gallium nitride (GaN) based high electron mobility transistors (HEMTs) with integrated slant field plates. These HEMTs have an epilayer structure comprised of AlGaN/GaN buffer. Before the formation of the gate electrode, a passivation layer is deposited, and then the opening for the gate is patterned. The passivation layer below the gate is etched using an etch condition that creates a slanted sidewalls. Then, the charge below the channel is removed either by Fluorine-based plasma treatment and/or by a recess etch. The gate metal is deposited with an angled rotation to form a gate structure with an inherent field plate with rounded edges.12-18-2008
20090072240III-Nitride Devices with Recessed Gates - III-nitride devices are described with recessed gates. In some embodiments, the material around the gates is formed by epitaxially depositing different III-nitride layers on a substrate and etching through at least the top two layers in the gate region. Because adjacent layers in the top three layers of the structure have different compositions, some of the layers act as etch stops to allow for precision etching. In some embodiments, a regrowth mask is used to prevent growth of material in the gate region. A gate electrode is deposited in the recess.03-19-2009
20100295056III-NITRIDE MATERIALS INCLUDING LOW DISLOCATION DENSITIES AND METHODS ASSOCIATED WITH THE SAME - Semiconductor structures including one, or more, III-nitride material regions (e.g., gallium nitride material region) and methods associated with such structures are provided. The III-nitride material region(s) advantageously have a low dislocation density and, in particular, a low screw dislocation density. In some embodiments, the presence of screw dislocations in the III-nitride material region(s) may be essentially eliminated. The presence of a strain-absorbing layer underlying the III-nitride material region(s) and/or processing conditions can contribute to achieving the low screw dislocation densities. In some embodiments, the III-nitride material region(s) having low dislocation densities include a gallium nitride material region which functions as the active region of the device. The low screw dislocation densities of the active device region (e.g., gallium nitride material region) can lead to improved properties (e.g., electrical and optical) by increasing electron transport, limiting non-radiative recombination, and increasing compositional/growth uniformity, amongst other effects.11-25-2010
20100295054SEMICONDUCTOR LIGHT-EMITTING ELEMENT AND METHOD FOR FABRICATING THE SAME - The semiconductor light-emitting element includes a group III nitride semiconductor multilayer structure having an active layer containing In as well as a p-type layer and an n-type layer stacked to hold the active layer therebetween. The group III nitride semiconductor multilayer structure is made of a group III nitride semiconductor having a major surface defined by a nonpolar plane whose offset angle in a c-axis direction is negative. A remarkable effect is attained when the emission wavelength of the active layer is not less than 450 nm. In the group III nitride semiconductor constituting the group III nitride semiconductor multilayer structure, the offset angle θ in the c-axis direction preferably satisfies −1°<θ<0°.11-25-2010
20100295055NITRIDE SEMICONDUCTOR SUBSTRATE AND MANUFACTURING METHOD OF THE SAME - To improve an adhesion to a substrate holder, and improve a device production yield by uniformizing a temperature distribution in a surface of a substrate and uniformizing characteristics such as a film thickness. When a concave warpage is set to be negative on a substrate front side, and a convex warpage is set to be positive on the substrate front side, then a line segment is drawn from one end of a substrate rear surface to the other end of the substrate rear surface, passing through a substrate center line, and a substrate is sliced by this line segment in a substrate thickness direction, a maximum value of shortest values of a distance from an arbitrary point on the drawn line segment to a rear side outline in a sliced surface, is defined as warpage H in a diameter direction, and when the warpage H in the diameter direction is obtained in a substrate peripheral direction, with its maximum value set to be Hmax, and its minimum value set to be Hmin, the warpage H in the diameter direction is defined to satisfy Hmax−Hmin≦30 μm.11-25-2010
20100295057DOWN-CONVERTED LIGHT SOURCE WITH UNIFORM WAVELENGTH EMISSION - An arrangement of light sources is attached to a semiconductor wavelength converter. Each light source emits light at a respective peak wavelength, and the arrangement of light sources is characterized by a first range of peak wavelengths. The semiconductor wavelength converter is characterized by a second range of peak wavelengths when pumped by the arrangement of light sources. The second range of peak wavelengths is narrower than the first range of peak wavelengths. The semiconductor wavelength converter is characterized by an absorption edge having a wavelength longer than the longest peak wavelength of the light sources. The wavelength converter may also be used for reducing the wavelength variation in the output from an extended light source.11-25-2010
20100301348Nitride semiconductor wafer, nitride semiconductor chip, and method of manufacture of nitride semiconductor chip - A nitride semiconductor chip is provided that offers enhanced luminous efficacy as a result of an improved EL emission pattern. The nitride semiconductor laser chip (nitride semiconductor chip) has an n-type GaN substrate having as a principal growth plane a plane having an off-angle in the a-axis direction relative to the m plane, and a nitride semiconductor layer formed on the principal growth plane of the n-type GaN substrate. The n-type GaN substrate includes a depressed portion (carved region), which is carved from the principal growth plane in the thickness direction, and an uncarved region, which is a region not carved. The nitride semiconductor layer formed on the n-type GaN substrate has a gradient thickness region whose thickness decreases in a gradient fashion toward the depressed portion (carved region) and an emission portion formation region whose thickness varies very little. In the emission portion formation region 12-02-2010
20110127541SEMICONDUCTOR HETEROSTRUCTURE DIODES - Planar Schottky diodes for which the semiconductor material includes a heterojunction which induces a 2DEG in at least one of the semiconductor layers. A metal anode contact is on top of the upper semiconductor layer and forms a Schottky contact with that layer. A metal cathode contact is connected to the 2DEG, forming an ohmic contact with the layer containing the 2DEG.06-02-2011
20100320475ETCHING TECHNIQUE FOR THE FABRICATION OF THIN (Al, In, Ga)N LAYERS - An etching technique for the fabrication of thin (Al, In, Ga)N layers. A suitable template or substrate is selected and implanted with foreign ions over a desired area to create ion implanted material. A regrowth of a device structure is then performed on the implanted template or substrate. The top growth surface of the template is bonded to a carrier wafer to created a bonded template/carrier wafer structure. The substrate is removed, as is any residual material, to expose the ion implanted material. The ion implanted material on the bonded template/carrier wafer structure is then exposed to a suitable etchant for a sufficient time to remove the ion implanted material.12-23-2010
20100252836GROUP-III NITRIDE STRUCTURE AND METHOD FOR PRODUCING A GROUP-III NITRIDE STRUCTURE - A group-III nitride structure includes a substrate 10-07-2010
20110108851VERTICAL LIGHT EMITTING DIODE HAVING AN OUTWARDLY DISPOSED ELECTRODE - The invention relates to a vertical light emitting diode (VLED) having an outwardly disposed electrode, the vertical light emitting diode comprises a conductive base, a semiconductor epitaxial structure formed on the conductive base, a passivation layer formed at the periphery of the semiconductor epitaxial structure, and a conductive frame formed on the passivation layer and contacting with the edge of the upper surface of the semiconductor epitaxial structure such that the conductive frame is electrically connected to the semiconductor epitaxial structure.05-12-2011
20110018002TRANSISTORS AND RECTIFIERS UTILIZING HYBRID ELECTRODES AND METHODS OF FABRICATING THE SAME - Systems, methods, and apparatus described herein are associated with devices including hybrid electrodes. A heterostructure semiconductor transistor can include a III-N-type semiconductor heterostructure including a barrier layer overlying an active layer and a hybrid electrode region including a hybrid drain electrode region. Further, a heterostructure semiconductor rectifier can include a III-N-type semiconductor heterostructure and a hybrid electrode region including a hybrid cathode electrode region. Furthermore, the hybrid electrode region of the transistor and rectifier can include permanently trapped charge located under a Schottky contact of the hybrid electrode region.01-27-2011
20110018003GROUP III NITRIDE SEMICONDUCTOR SUBSTRATE AND MANUFACTURING METHOD THEREOF - A method of manufacturing a group III nitride semiconductor substrate includes the growth step of epitaxially growing a first group III nitride semiconductor layer on an underlying substrate, and the process step of forming a first group III nitride semiconductor substrate by cutting and/or surface-polishing the first group III nitride semiconductor layer. In the growth step, at least one element selected from the group consisting of C, Mg, Fe, Be, Zn, V, and Sb is added as an impurity element by at least 1×1001-27-2011
20110108852GaN SUBSTRATE AND LIGHT-EMITTING DEVICE - The present GaN substrate can have an absorption coefficient not lower than 7 cm05-12-2011
20110108850METHOD OF MANUFACTURING AN INTEGRATED SEMICONDUCTOR SUBSTRATE STRUCTURE - An integrated semiconductor substrate structure is disclosed. In one aspect, the structure includes a substrate, a GaN-heterostructure and a semiconductor substrate layer. The GaN heterostructure is present in a first device area for definition of GaN-based devices, and is covered at least partially with a protection layer. The semiconductor substrate layer is present in a second device area for definition of CMOS devices. At least one of the GaN heterostructure and the semiconductor substrate layer is provided in at least one trench in the substrate, so that the GaN heterostructure and the semiconductor substrate layer are laterally juxtaposed.05-12-2011
20120032186WHITE ORGANIC LIGHT EMITTING DEVICE - Provided is a white organic light emitting device (OLED), including: a first electrode formed on a substrate; a hole transport layer formed on the first electrode; an emission layer formed on the hole transport layer; an electron transport layer formed on the emission layer; and an color control layer formed on at least one of the hole transport layer, the emission layer and the electron transport layer, and emitting green and/or red by energy transfer from the emission layer. The white OLED emits red, green and blue light with high efficiency, has excellent color reproducibility and a high color reproduction index.02-09-2012
20090065786PROCESS FOR PRODUCING THIN NITRIDE FILM ON SAPPHIRE SUBSTRATE AND THIN NITRIDE FILM PRODUCING APPARATUS - A method for growing a nitride thin film on a sapphire substrate, in which using no resists, miniaturization can be accomplished while relieving vexatious complication of the process; and a relevant device using nitride thin film. There is provided a method for growing a nitride thin film on a sapphire substrate, comprising irradiating a sapphire substrate having undergone high temperature hydrogen treatment with electron beams and depositing a nitride thin film on the substrate having undergone the electron beam irradiation by using the metal-organic chemical vapor deposition technique to thereby accomplish patterning of nitride thin film.03-12-2009
20090065785III-nitride power semiconductor device - A power semiconductor device that includes common conduction regions, charge compensation regions, each adjacent a respective common conduction region, and a stand off region over the common conduction regions and charge compensation regions.03-12-2009
20120241760SEMICONDUCTOR LIGHT EMITTING ELEMENT AND SEMICONDUCTOR LIGHT EMITTING DEVICE - Disclosed is a semiconductor light emitting element (09-27-2012
20110241019III-Nitride Power Semiconductor Device - A III-nitride semiconductor device which includes a barrier body between the gate electrode and the gate dielectric thereof.10-06-2011
20130153921NITRIDE SEMICONDUCTOR DEVICE USING SELECTIVE GROWTH AND MANUFACTURING METHOD THEREOF - A semiconductor device including a first GaN layer, an AlGaN layer, a second GaN layer, a gate electrode, a source electrode, and a drain electrode sequentially stacked on a substrate, capable of improving a leakage current and a breakdown voltage characteristics generated in the gate electrode by locally forming a p type GaN layer on the AlGaN layer, and a manufacturing method thereof, and a manufacturing method thereof are provided.06-20-2013
20110114966LIGHT EMITTING DIODE DEVICE - A high-brightness vertical light emitting diode (LED) device having an outwardly located metal electrode. The LED device is formed by: forming the metal electrode on an edge of a surface of a LED epitaxy structure using a deposition method, such as physical vapor deposition (PVD), chemical vapor deposition (CVD), evaporation, electro-plating, or any combination thereof; and then performing a packaging process. The composition of the LED may be a nitride, a phosphide or an arsenide. The LED of the invention has the following advantages: improving current spreading performance, reducing light-absorption of the metal electrode, increasing brightness, increasing efficiency, and thereby improving energy efficiency. The metal electrode is located on the edge of the device and on the light emitting side. The metal electrode has two side walls, among which one side wall can receive more emission light from the device in comparison with the other one.05-19-2011
20110114965METHODS OF FABRICATING SEMICONDUCTOR STRUCTURES AND DEVICES USING GLASS BONDING LAYERS, AND SEMICONDUCTOR STRUCTURES AND DEVICES FORMED BY SUCH METHODS - Methods of fabricating semiconductor structures and devices include bonding a seed structure to a substrate using a glass. The seed structure may comprise a crystal of semiconductor material. Thermal treatment of the seed structure bonded to a substrate using a glass may be utilized to control the strain state within the seed structure. The seed structure may be placed in a state of compressive strain at room temperature. The seed structure bonded to the glass may be used for growth of semiconductor material, or, in additional methods, a seed structure may be bonded to a first substrate using a glass, thermally treated to control the strain state within the seed structure and a second substrate may be bonded to an opposite side of the seed structure using a non-glassy material.05-19-2011
20100163887LIGHT EMITTING DEVICE HAVING A PLURALITY OF NON-POLAR LIGHT EMITTING CELLS AND A METHOD OF FABRICATING THE SAME - The present invention relates to a light emitting device having a plurality of non-polar light emitting cells and a method of fabricating the same. Nitride semiconductor layers are disposed on a Gallium Nitride substrate having an upper surface. The upper surface is a non-polar or semi-polar crystal and forms an intersection angle with respect to a c-plane. The nitride semiconductor layers may be patterned to form light emitting cells separated from one another. When patterning the light emitting cells, the substrate may be partially removed in separation regions between the light emitting cells to form recess regions. The recess regions are filled with an insulating layer, and the substrate is at least partially removed by using the insulating layer.07-01-2010
20100163886GALLIUM NITRIDE COMPOUND SEMICONDUCTOR LIGHT-EMITTING DEVICE, METHOD OF MANUFACTURING THE SAME, AND LAMP INCLUDING THE SAME - The present invention provides a gallium nitride compound semiconductor light-emitting device that prevents an increase in the specific resistance of a p-type semiconductor layer due to hydrogen annealing and reduces the specific resistance of a translucent conductive oxide film to lower a driving voltage Vf, a method of manufacturing the same, and a lamp including the same. The method of manufacturing the gallium nitride compound semiconductor light-emitting device includes: forming a positive electrode 07-01-2010
20100032682Large area thin freestanding nitride layers and their use as circuit layers - Thin flat crack-free freestanding nitride layers are fabricated by laser patterning of the interface and/or opposing surface of the nitride layer. The nitride layer is substantially flat once removed from the non-native substrate. The thin flat crack free nitride layers are between 3 and 250 microns thick and can have areas greater than 1 cm02-11-2010
20110241016NITRIDE-BASED SEMICONDUCTOR LIGHT-EMITTING ELEMENT - A nitride-based semiconductor light-emitting element LE10-06-2011
20110210337Monolithic integration of silicon and group III-V devices - Disclosed is a monolithically integrated silicon and group III-V device that includes a group III-V transistor formed in a III-V semiconductor body disposed over a silicon substrate. At least one via extends through the III-V semiconductor body to couple at least one terminal of the group III-V transistor to a silicon device formed in the silicon substrate. The silicon device can be a Schottky diode, and the group III-V transistor can be a GaN HEMT. In one embodiment an anode of the Schottky diode is formed in the silicon substrate. In another embodiment, the anode of the Schottky diode is formed in a lightly doped epitaxial silicon layer atop the silicon substrate. In one embodiment a parallel combination of the Schottky diode and the group III-V transistor is formed, while in another embodiment is series combination is formed.09-01-2011
20100012948Growth of Planar Non-Polar M-Plane and Semi-Polar Gallium Nitride with Hydride Vapor Phase Epitaxy (HVPE) - A method of growing planar non-polar m-plane or semi-polar III-Nitride material, such as an m-plane gallium nitride (GaN) epitaxial layer, wherein the III-Nitride material is grown on a suitable substrate, such as an m-plane Sapphire substrate, using hydride vapor phase epitaxy (HVPE). The method includes in-situ pretreatment of the substrate at elevated temperatures in the ambient of ammonia and argon, growing an intermediate layer such as an aluminum nitride (AlN) or aluminum-gallium nitride (AlGaN) on the annealed substrate, and growing the non-polar m-plane III-Nitride epitaxial layer on the intermediate layer using HVPE.01-21-2010
20110147760Semiconductor apparatus with thin semiconductor film - A semiconductor apparatus includes a substrate having at least one terminal, a thin semiconductor film including at least one semiconductor device, the thin semiconductor film being disposed and bonded on the substrate; and an individual interconnecting line formed as a thin conductive film extending from the semiconductor device in the thin semiconductor film to the terminal in the substrate, electrically connecting the semiconductor device to the terminal. Compared with conventional semiconductor apparatus, the invented apparatus is smaller and has a reduced material cost.06-23-2011
20100019247Light emitting device using gan led chip - A light emitting device is constituted by flip-chip mounting a GaN-based LED chip 01-28-2010
20090218578SEMICONDUCTOR DEVICE - A semiconductor device comprises an AlN layer, a GaN layer, and an AlGaN layer sequentially formed on a semiconductor substrate. A first opening extends through said GaN layer and said AlGaN layer and exposes part of an upper surface of the AlN layer. A second opening extends through the semiconductor substrate and exposes a part of a lower surface of the AlN layer, in a location facing the first opening. A upper electrode is exposed on an upper surface of the AlN layer in the first opening; and a lower electrode is disposed on a lower surface of the AlN layer in the second opening.09-03-2009
20100038652LIGHT EMITTING ELEMENT AND METHOD OF MAKING SAME - A light emitting element has a substrate of gallium oxides and a pn-junction formed on the substrate. The substrate is of gallium oxides represented by: (Al02-18-2010
20100044718Group III Nitride Articles and Methods for Making Same - Group III (Al, Ga, In)N single crystals, articles and films useful for producing optoelectronic devices (such as light emitting diodes (LEDs), laser diodes (LDs) and photodetectors) and electronic devices (such as high electron mobility transistors (HEMTs)) composed of III-V nitride compounds, and methods for fabricating such crystals, articles and films.02-25-2010
20100059760GALLIUM NITRIDE-BASED COMPOUND SEMICONDUCTOR LIGHT EMITTING DEVICE AND PROCESS FOR ITS PRODUCTION - It is an object of the present invention to provide a gallium nitride-based compound semiconductor light emitting device with high light emission output and low driving voltage.03-11-2010
20090032820Reliable Normally-Off III-Nitride Active Device Structures, and Related Methods and Systems - A field-effect transistor includes a first gate, a second gate held at a substantially fixed potential in a cascode configuration, and a semiconductor channel. The semiconductor channel has an enhancement mode portion and a depletion mode portion. The enhancement mode portion is gated to be turned on and off by the first gate, and has been modified to operate in enhancement mode. The depletion mode portion is gated by the second gate, and has been modified to operate in depletion mode and that is operative to shield the first gate from voltage stress.02-05-2009
20100065856Semiconductor package with integrated passives and method for fabricating same - According to one disclosed embodiment, a semiconductor package for integrated passives and a semiconductor device comprises a high permeability structure formed over a surface of the semiconductor package and surrounding a contact body of the semiconductor package, the contact body being connected to an output of the semiconductor device. The contact body can be, for example, a solder bump. The high permeability structure causes a substantial increase in inductance of the contact body so as to form an increased inductance inductor coupled to the output of the semiconductor device. In one embodiment, the semiconductor package further comprises a blanket insulator formed over the high permeability structure, and a capacitor stack formed over the blanket insulator. In one embodiment, the semiconductor device comprises a group III-V power semiconductor device.03-18-2010
20120199843HIGH REFLECTIVE BOARD OR SUBSTRATE FOR LEDS - Light emitting devices and methods are disclosed that provide improved light output. The devices have an LED mounted to a substrate, board or submount characterized by improved reflectivity, which reduces the absorption of LED light. This increases the amount of light that can emit from the LED device. The LED devices also exhibit improved emission characteristics by having a reflective coating on the submount that is substantially non-yellowing. One embodiment of a light emitting device according to the present invention comprises a submount having a circuit layer. A reflective coating is included between at least some of the elements of the circuit layer. A light emitting diode mounted to the circuit layer, the reflective coating being reflective to the light emitted by the light emitting diode. In some embodiments, the reflective coating comprises a carrier with scattering particles having a different index of refraction than said carrier material.08-09-2012
20120199842SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A highly integrated DRAM is provided. A bit line is formed over a first insulator, a second insulator is formed over the bit line, third insulators which are in a stripe shape and the like are formed over the second insulator, and a semiconductor region and a gate insulator are formed to cover one of the third insulators. The bit line is connected to the semiconductor region through first contact plugs. Then, a conductive film is formed and subjected to anisotropic etching to form word lines at side surfaces of the third insulators, and a second contact plug is formed to be connected to a capacitor at a top of the one of the third insulators. By synchronizing the word lines, electric charge is accumulated or released through the capacitor. With such a structure, the area of a memory cell can be 4F08-09-2012
20110175103SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device has a satisfactory ohmic contact on a p-type principal surface tilting from a c-plane. The principal surface 07-21-2011
20100127276GaN Based LED with Improved Light Extraction Efficiency and Method for Making the Same - A light-emitting device and the method for making the same are disclosed. The device includes a substrate, a light-emitting structure and a light scattering layer. The light-emitting structure includes an active layer sandwiched between a p-type GaN layer and an n-type GaN layer, the active layer emitting light of a predetermined wavelength when electrons and holes from the n-type GaN layer and the p-type GaN layer, respectively, combine therein. The light scattering layer includes a GaN crystalline layer characterized by an N-face surface. The N-face surface includes features that scatter light of the predetermined wavelength. The light-emitting structure is between the N-face surface and the substrate.05-27-2010
20110079790GROUP III NITRIDE SEMICONDUCTOR ELEMENT AND EPITAXIAL WAFER - A primary surface 04-07-2011
20110101371Gallium nitride semiconductor - A gallium nitride based semiconductor Schottky diode fabricated from a n+ doped GaN layer having a thickness between one and six microns disposed on a sapphire substrate; an n− doped GaN layer having a thickness greater than one micron disposed on said n+ GaN layer patterned into a plurality of elongated fingers and a metal layer disposed on the n− doped GaN layer and forming a Schottky junction therewith. The layer thicknesses and the length and width of the elongated fingers are optimized to achieve a device with breakdown voltage of greater than 500 volts, current capacity in excess of one ampere, and a forward voltage of less than three volts.05-05-2011
20110068349SEMICONDUCTOR LIGHT EMITTING ELEMENT, METHOD FOR MANUFACTURING SEMICONDUCTOR LIGHT EMITTING ELEMENT, AND LAMP - A semiconductor light-emitting device (03-24-2011
20100123139SEMICONDUCTOR WAFER, SEMICONDUCTOR DEVICE, SEMICONDUCTOR WAFER MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - An aspect of the present invention inheres in a semiconductor wafer includes a support substrate, a first nitride semiconductor layer, at least an upper surface of which has become monocrystalline, the first semiconductor layer being provided on the support substrate, and a second nitride semiconductor layer containing nitrogen and gallium, the second nitride semiconductor layer being provided on the upper surface of the first nitride semiconductor layer.05-20-2010
20110101373METHOD OF FORMING A COMPOSITE LASER SUBSTRATE - A composite substrate for laser devices is disclosed having improved wave guiding properties, improved lattice matching, improved thermal expansion matching, and improved thermal conductivity. The composite substrate has an intermediate layer (05-05-2011
20110101372NITRIDE SEMICONDUCTOR ELEMENT AND METHOD FOR PRODUCING THE SAME - A nitride-based semiconductor light-emitting device 05-05-2011
20110101370SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF - A semiconductor device and method of manufacturing the device is disclosed. In one aspect, the device includes a semiconductor substrate and a GaN-type layer stack on top of the semiconductor substrate. The GaN-type layer stack has at least one buffer layer, a first active layer and a second active layer. Active device regions are definable at an interface of the first and second active layer. The semiconductor substrate is present on an insulating layer and is patterned to define trenches according to a predefined pattern, which includes at least one trench underlying the active device region. The trenches extend from the insulating layer into at least one buffer layer of the GaN-type layer stack and are overgrown within the at least one buffer layer, so as to obtain that the first and the second active layer are continuous at least within the active device regions.05-05-2011
20110101369Gallium nitride semiconductor device with improved termination scheme - This invention discloses a gallium nitride based semiconductor power device disposed in a semiconductor substrate. The power device comprises a termination area disposed at a peripheral area of the semiconductor power device comprises a termination structure having at least a guard ring disposed in a trench filled with doped gallium-based epitaxial layer therein.05-05-2011
20110068347Nitride Semiconductor Structure and Method of Making Same - A structure method for producing same provides suppressed lattice defects when epitaxially forming nitride layers over non-c-plane oriented layers, such as a semi-polar oriented template layer or substrate. A patterned mask with “window” openings, or trenches formed in the substrate with appropriate vertical dimensions, such as the product of the window width times the cotangent of the angle between the surface normal and the c-axis direction, provides significant blocking of all diagonally running defects during growth. In addition, inclined posts of appropriate height and spacing provide a blocking barrier to vertically running defects is created. When used in conjunction with the aforementioned aspects of mask windows or trenches, the post structure provides significant blocking of both vertically and diagonally running defects during growth.03-24-2011
20110248282SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD OF THE SAME - The invention provides a semiconductor structure and a manufacturing method of the same, and relates to a field of semiconductor manufacture. The semiconductor structure comprises: a silicon substrate; a large bandgap semiconductor layer formed on the silicon substrates; and a silicon layer formed on the large bandgap semiconductor layer. The method comprises: growing a large bandgap semiconductor layer on a silicon substrate; and growing a silicon layer on the large bandgap semiconductor layer. The embodiments of the present invention can be applied to manufacture of semiconductor devices.10-13-2011
20100244045SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a first semiconductor layer which is formed above a substrate, a Schottky electrode and an ohmic electrode which are formed on the first semiconductor layer to be spaced from each other and a second semiconductor layer which is formed to cover the first semiconductor layer with the Schottky electrode and the ohmic electrode exposed. The second semiconductor layer has a larger band gap than that of the first semiconductor layer.09-30-2010
20100244041SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - An isolation layer for suppressing a leakage current is provided at least between a channel layer and a buffer layer formed under the channel layer in the buffer layer.09-30-2010
20110248283VIA STRUCTURE OF A SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - Semiconductor devices, such as GaN HEMT and HFET devices, and methods of forming such devices, with a via that provides an electrical connection between a contact and a corresponding external contact pad. Embodiments include semiconductor devices with a via extending through a dielectric material to connect a gate to a corresponding external contact pad, and semiconductor devices with a via extending through a dielectric material to connect an Ohmic contact and a corresponding external contact pad. Embodiments also include semiconductor devices with a via connecting an external contact pad to a gate that is formed above a dielectric material.10-13-2011
20110248281Nitride semiconductor substrate, production method therefor and nitride semiconductor device - A nitride semiconductor substrate includes two principal surfaces including an upper surface that is a growth face and a lower surface on its opposite side. An FWHM in a surface layer region at depths of from 0 to 250 nm from the upper surface is narrower than an FWHM in an inner region at depths exceeding 5 μm from the upper surface, where the FWHMs are obtained by X-ray rocking curve measurement using diffraction off a particular asymmetric plane inclined relative to the upper surface.10-13-2011
20120267641EPITAXIAL WAFER FOR LIGHT EMITTING DIODE, LIGHT EMITTING DIODE CHIP AND METHODS FOR MANUFACTURING THE SAME - An epitaxial wafer for a light emitting diode (LED) and a method for manufacturing the same are provided. The method comprises: providing a substrate; forming a first LED epitaxial structure on a first surface of the substrate, in which the first LED epitaxial structure comprises a first n-type semiconductor layer, a first light emitting layer, a first anti-diffusion layer between the first n-type semiconductor layer and the first light emitting layer, a first p-type semiconductor layer, and a second anti-diffusion layer between the first p-type semiconductor layer and the first light emitting layer; and forming a second LED epitaxial structure on a second surface of the substrate. An LED chip comprising the epitaxial wafer and a method for manufacturing the same are also provided.10-25-2012
20090242898METHOD OF CONTROLLING STRESS IN GALLIUM NITRIDE FILMS DEPOSITED ON SUBSTRATES - Methods of controlling stress in GaN films deposited on silicon and silicon carbide substrates and the films produced therefrom are disclosed. A typical method comprises providing a substrate and depositing a graded gallium nitride layer on the substrate having a varying composition of a substantially continuous grade from an initial composition to a final composition formed from a supply of at least one precursor in a growth chamber without any interruption in the supply. A typical semiconductor film comprises a substrate and a graded gallium nitride layer deposited on the substrate having a varying composition of a substantially continuous grade from an initial composition to a final composition formed from a supply of at least one precursor in a growth chamber without any interruption in the supply.10-01-2009
20080246040LIGHT EMITTING DEVICE HAVING LIGHT EMITTING ELEMENTS - A light-emitting device operating on a high drive voltage and a small drive current. LEDs (10-09-2008
20120199844NITRIDE-BASED SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A nitride-based semiconductor device according to the present disclosure includes a nitride-based semiconductor multilayer structure 08-09-2012
20110175104SEMICONDUCTOR DEVICE - An object is to provide a semiconductor device having a novel structure which includes a combination of semiconductor elements with different characteristics and is capable of realizing higher integration. A semiconductor device includes a first transistor, which includes a first channel formation region including a first semiconductor material, and a first gate electrode, and a second transistor, which includes one of a second source electrode and a second drain electrode combined with the first gate electrode, and a second channel formation region including a second semiconductor material and electrically connected to the second source electrode and the second drain electrode.07-21-2011
20080237607LIGHT EMITTING ELEMENT AND METHOD OF MAKING SAME - A light emitting element has a substrate of gallium oxides and a pn-junction formed on the substrate. The substrate is of gallium oxides represented by: (Al10-02-2008
20080303035COMPOUND SEMICONDUCTOR FILM, LIGHT EMITTING FILM, AND MANUFACTURING METHOD THEREOF - Provided are a compound semiconductor film which is manufactured at a low temperature and exhibits excellent p-type conductivity, and a light emitting film in which the compound semiconductor film and a light emitting material are laminated and with which high-intensity light emission can be realized. The compound semiconductor film has a composition represented by a Cu12-11-2008
20110254013HYBRID ORIENTATION ACCUMULATION MODE GAA CMOSFET - A hybrid orientation accumulation mode GAA (Gate-All-Around) CMOSFET includes a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The first channel and the second channel have a racetrack-shaped cross section and are formed of p-type Si(110) and n-type Si(100), respectively; the surfaces of the first channel and the second channel are substantially surrounded by the gate region; a buried oxide layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the Si substrate to isolate them from one another. The device structure according to the prevent invention is quite simple, compact and highly integrated. In an accumulation mode, current flows through the overall racetrack-shaped channel. The disclosed device results in high carrier mobility. Meanwhile polysilicon gate depletion and short channel effects are prevented, and threshold voltage is increased.10-20-2011
20110163324LIGHT EMITTING DEVICE - A light emitting diode of one embodiment includes a light emitting device having a plurality of N-type semiconductor layers including a first N-type semiconductor layer and a second N-type semiconductor layer on the first N-type semiconductor layer, an active layer on an upper layer of the plurality of N-type semiconductor layers, and a P-type semiconductor layer on the active layer. The first N-type semiconductor layer includes a first Si doped Nitride layer and the second N-type semiconductor layer includes a second Si doped Nitride layer. The first and second N-type semiconductor layers have a Si impurity concentration different from each other.07-07-2011
20080210948High-Heat-Resistive Semiconductor Device - The outer surface of a wide-gap semiconductor device is coated with a synthetic polymer compound containing one or more silicon-containing polymer having a bridged structure formed by a siloxane (Si—O—Si bond structure). The synthetic polymer compound may include, for example, a silicon-containing polymer which has one or more reactive groups (A′) selected from Si—R09-04-2008
20120032188COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Two layers of protection films are formed such that a sheet resistance at a portion directly below the protection film is higher than that at a portion directly below the protection film. The protection films are formed, for example, of SiN film, as insulating films. The protection film is formed to be higher, for instance, in hydrogen concentration than the protection film so that the protection film is higher in refractive index the protection film. The protection film is formed to cover a gate electrode and extend to the vicinity of the gate electrode on an electron supplying layer. The protection film is formed on the entire surface to cover the protection film. According to this configuration, the gate leakage is significantly reduced by a relatively simple configuration to realize a highly-reliable compound semiconductor device achieving high voltage operation, high withstand voltage, and high output.02-09-2012
20110163325METHOD OF MANUFACTURING GaN SUBSTRATE, METHOD OF MANUFACTURING EPITAXIALWAFER, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND EPITAXIALWAFER - Assuming that r (m) represents the radius of a GaN substrate, t07-07-2011
20110163326SUBSTRATE, EPITAXIAL LAYER PROVIDED SUBSTRATE, METHOD FOR PRODUCING SUBSTRATE, AND METHOD FOR PRODUCING EPITAXIAL LAYER PROVIDED SUBSTRATE - The present invention provides a substrate formed at a low cost and having a controlled plate shape, an epitaxial layer provided substrate obtained by forming an epitaxial layer on the substrate, and methods for producing them. The method for producing the substrate according to the present invention includes an ingot growing step serving as a step of preparing an ingot formed of gallium nitride (GaN); and a slicing step serving as a step of obtaining a substrate formed of gallium nitride, by slicing the ingot. In the slicing step, the substrate thus obtained by the slicing has a main surface with an arithmetic mean roughness Ra of not less than 0.05 μm and not more than 1 μm on a line of 10 mm.07-07-2011
20110163323GaN SINGLE CRYSTAL SUBSTRATE AND METHOD OF MAKING THE SAME - The method of making a GaN single crystal substrate comprises a mask layer forming step of forming on a GaAs substrate 07-07-2011
20110163322PHOSPHOR, PHOSPHOR MANUFACTURING METHOD, AND WHITE LIGHT EMITTING DEVICE - Provided are a phosphor, a phosphor manufacturing method, and a white light emitting device. The phosphor is represented as a chemical formula of M07-07-2011
20120199841Gallium and Nitrogen Containing Trilateral Configuration for Optical Devices - Techniques for manufacturing optical devices, such as light emitting diodes (LEDs) using a separation process of thick gallium and nitrogen containing substrate members, are described.08-09-2012
20100320474GALLIUM NITRIDE FOR LIQUID CRYSTAL ELECTRODES - Described herein is a liquid crystal (LC) device having Gallium Nitride HEMT electrodes. The Gallium Nitride HEMT electrodes can be grown on a variety of substrates, including but not limited to sapphire, silicon carbide, silicon, fused silica (using a calcium fluoride buffer layer), and spinel. Also described is a structure provided from GaN HEMT grown on large area silicon substrates and transferred to another substrate with appropriate properties for OPA devices. Such substrates include, but are not limited to sapphire, silicon carbide, silicon, fused silica (using a calcium fluoride buffer layer), and spinel. The GaN HEMT structure includes an AlN interlayer for improving the mobility of the structure.12-23-2010
20110068348THIN BODY MOSFET WITH CONDUCTING SURFACE CHANNEL EXTENSIONS AND GATE-CONTROLLED CHANNEL SIDEWALLS - A thin body MOSFET with conducting surface channel extensions and gate-controlled channel sidewalls is described. One embodiment is a MOSFET comprising a semiconductor substrate; a channel layer disposed on a top surface of the substrate; a gate dielectric layer interposed between a gate electrode and the channel layer; and dielectric extension layers disposed on top of the channel layer and interposed between the gate electrode and Ohmic contacts. The gate dielectric layer comprises a first material, the first material forming an interface of low defectivity with the channel layer. In contrast, the dielectric extensions comprise a second material different than the first material, the second material forming a conducting surface channel with the channel layer.03-24-2011
20100283060Field effect transistor - A material of a gate electrode is a conductive oxide having a higher work function than that of conventionally used Pd and so on, thereby achieving a normally-off transistor without reducing the sheet carrier concentration of a heterojunction. It is thus possible to achieve a normally-off operation while reducing an increase in the specific on-state resistance.11-11-2010
20110133206Compound semiconductor device - At a gate electrode formed on a compound semiconductor layer with a Schottky junction, a diffusion preventing layer made of Ti06-09-2011
20110133205FIELD-EFFECT TRANSISTOR - A field-effect transistor provided with a channel layer, a carrier supply layer forming a heterojunction with the channel layer, a recessed portion recessed from a surface of the carrier supply layer, a first insulating layer formed at least along the recessed portion, a first gate electrode formed on the first insulating layer, a source electrode formed on one side of the recessed portion in a channel lengthwise direction, and a drain electrode formed on an opposite side of the recessed portion in the channel lengthwise direction. The recessed portion snakes in a direction intersecting the channel lengthwise direction, in the range of a channel length between the source electrode and the drain electrode.06-09-2011
20110133210SCHOTTKY BARRIER DIODE AND METHOD FOR MANUFACTURING SCHOTTKY BARRIER DIODE - A method for manufacturing a Schottky barrier diode includes the following steps. First, a GaN substrate is prepared. A GaN layer is formed on the GaN substrate. A Schottky electrode including a first layer made of Ni or Ni alloy and in contact with the GaN layer is formed. The step of forming the Schottky electrode includes a step of forming a metal layer to serve as the Schottky electrode and a step of heat treating the metal layer. A region of the GaN layer in contact with the Schottky electrode has a dislocation density of 1×1006-09-2011
20110133208SEMICONDUCTOR ELEMENT - Light extraction efficiency of a semiconductor light-emitting element is improved. A buffer layer, an n-type GaN layer, an InGaN emission layer, and a p-type GaN layer are laminated on a sapphire substrate in a semiconductor light-emitting element. A ZnO layer functioning as a transparent electrode is provided on the p-type GaN layer and concave portions are formed on a surface of the ZnO layer at two-dimensional periodic intervals. If a wavelength of light from the InGaN emission layer in the air is λ, an index of refraction of the ZnO layer at the wavelength λ is n06-09-2011
20110133204LIGHT EMITTING DIODE AND MANUFACTURING METHOD THEREOF - A light emitting diode includes a thermal conductive substrate, an p-type GaN layer, an active layer and an n-type GaN layer sequentially stacked above the substrate and an electrode pad deposited on the n-type GaN layer. A surface of n-type GaN layer away from the active layer has a first diffusing section and a second diffusing section. The first diffusing section is adjacent to the electrode pad and the second diffusing section is located at the other side of the first diffusing section opposite to the electrode pad, wherein the doping concentration of the first diffusing section is less than that of the second diffusing section. The n-type GaN layer has an electrical resistance larger than that of the first diffusing section which in turn is larger than that of the second diffusing section.06-09-2011
20130168693PROTECTIVE-FILM-ATTACHED COMPOSITE SUBSTRATE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A protective-film-attached composite substrate includes a support substrate, an oxide film disposed on the support substrate, a semiconductor layer disposed on the oxide film, and a protective film protecting the oxide film by covering a portion that is a part of the oxide film and covered with none of the support substrate and the semiconductor layer. A method of manufacturing a semiconductor device includes the steps of: preparing the protective-film-attached composite substrate; and epitaxially growing, on the semiconductor layer of the protective-film-attached composite substrate, at least one functional semiconductor layer causing an essential function of a semiconductor device to be performed. Thus, there are provided a protective-film-attached composite substrate having a large effective region where a high-quality functional semiconductor layer can be epitaxially grown, and a method of manufacturing a semiconductor device in which the protective-film-attached composite substrate is used.07-04-2013
20110001142METHOD FOR MANUFACTURING ELECTRONIC DEVICE, METHOD FOR MANUFACTURING EPITAXIAL SUBSTRATE, III NITRIDE SEMICONDUCTOR ELEMENT AND GALLIUM NITRIDE EPITAXIAL SUBSTRATE01-06-2011
20110254014NITRIDE SEMICONDUCTOR WAFER AND NITRIDE SEMICONDUCTOR DEVICE - There is stably provided a nitride semiconductor wafer having a nitride semiconductor layer with high insulating properties, wherein a semi-insulating nitride semiconductor layer is provided on an insulating substrate, with a resistivity of 10 MΩcm or more and 100 MΩcm or less, and a film thickness of 0.1 μm or more and 1.5 μm or less.10-20-2011
20110186859High speed high power nitride semiconductor device - A nitride semiconductor device has: a substrate; a semiconductor lamination formed on the substrate, and including a channel layer of nitride semiconductor; source and drain electrodes formed on the semiconductor lamination in ohmic contact with the channel layer; an insulating layer formed on the semiconductor lamination, and having an opening in a gate electrode contact area, a total thickness portion having a flat surface and a total thickness in an area spaced apart from the opening, and a transient portion with monotonically changing thickness between the opening and the total thickness portion, a sidewall of the insulating layer facing the opening rising steeply to a partial thickness of the total thickness; and a T-shaped gate electrode contacting the semiconductor lamination layer in the opening and extending on the insulating film to portions with increased thickness thicker than the partial thickness.08-04-2011
20110186860NITRIDE-BASED SEMICONDUCTOR LIGHT EMITTING DEVICE, METHOD FOR MANUFACTURING NITRIDE-BASED SEMICONDUCTOR LIGHT EMITTING DEVICE, AND LIGHT EMITTING APPARATUS - Disclosed is a nitride-based semiconductor light emitting device with excellent light extraction efficiency. A light emitting device 08-04-2011
20110186858Gallium Nitride Power Devices Using Island Topography - A semiconductor device in provided having a substrate and a semiconductor layer formed on a main surface of the substrate. A plurality of first island electrodes and a plurality of second island electrodes are placed over the semiconductor layer. The plurality of first island electrodes and second island electrodes are spaced apart from each other so as to be alternatively arranged to produce two-dimensional active regions in all feasible areas of the semiconductor layer. Each side of the first island electrodes is opposite a side of the second island electrodes. The semiconductor device can also include a plurality of strip electrodes that are formed in the regions between the first island electrodes and the second island electrodes. The strip electrodes serve as the gate electrodes of a multi-island transistor. The first island electrodes serve as the source electrodes of the multi-island transistor. The second island electrodes serve as the drain electrodes of the multi-island transistor. A plurality of connections to the gate electrodes are provided at each interstice defined by corners of the first island electrodes and the second island electrodes.08-04-2011
20110186857LIGHT EMITTING DEVICE, LIGHT EMITTING DEVICE PACKAGE, AND LIGHTING SYSTEM - Provided is a light emitting device according to one embodiment including: a substrate which has protrusions on the C-face, and of which unit cells are constructed in a hexagonal structure; a semiconductor layer which is formed on the substrate, in which empty spaces are formed in sides of the protrusions, and of which unit cells are constructed in a hexagonal structure; and a light emitting structure layer comprising a first conductive semiconductor layer, a second conductive semiconductor layer, and an active layer formed between the first conductive semiconductor layer and second conductive semiconductor layer which are formed on the semiconductor layer, wherein the A-face of the substrate and the A-face of the semiconductor layer form an angle of greater than zero degree, and the protrusions include the R-faces.08-04-2011
20110186856LIGHT EMITTING ELEMENT AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a light emitting element includes providing a substrate, forming a buffer layer on the substrate, forming a GaN layer on the buffer layer, forming a rough layer on the GaN layer at low temperature, and forming an epitaxial layer on the rough layer, wherein a refraction index of the epitaxial layer exceeds a refraction index of the rough layer. Thus, most light scatters at the rough layer, and then emits upwardly to a light emitting surface, enhancing light extraction efficiency thereof. An epitaxial process of the method is processed in situ in an MOCVD reactor.08-04-2011
20110186855Enhancement-Mode GaN MOSFET with Low Leakage Current and Improved Reliability - An enhancement-mode GaN MOSFET with a low leakage current and an improved reliability is formed by utilizing a SiO08-04-2011
20120146049JFET DEVICES WITH INCREASED BARRIER HEIGHT AND METHODS OF MAKING THE SAME - Devices and methods for providing JFET transistors with improved operating characteristics are provided. Specifically, one or more embodiments of the present invention relate to JFET transistors with a higher diode turn-on voltage. For example, one or more embodiments include a JFET with a doped silicon-carbide gate, while other embodiments include a JFET with a metal gate. One or more embodiments also relate to systems and devices in which the improved JFET may be employed, as well as methods of manufacturing the improved JFET.06-14-2012
20120146047P-CONTACT AND LIGHT-EMITTING DIODE FOR THE ULTRAVIOLET SPECTRAL RANGE - The present invention relates to a p-doped contact for use in a light-emitting diode for the ultraviolet spectral range, comprising a p-contact layer having a first surface for contacting a radiation zone and a second surface comprising, on the side facing away from the first surface: a) a coating, which directly contacts 5%-99.99% of the second surface of the p-contact layer and contains or consists of a material having a maximum reflectivity of at least 60% for light with a wavelength of 200 nm to 400 nm; b) a plurality of p-injectors, which are disposed directly on the second surface of the p-contact layer.06-14-2012
20120146044Optoelectronic Semiconductor Chip and Method for Producing an Optoelectronic Semiconductor Chip - In at least one embodiment of the optoelectronic semiconductor chip (06-14-2012
20110180806MONOLITHIC INTEGRATION OF GALLIUM NITRIDE AND SILICON DEVICES AND CIRCUITS, STRUCTURE AND METHOD - A structure and method for a semiconductor device includes a silicon device layer and a gallium nitride (GaN) device layer. In an embodiment, the silicon device layer and the GaN device layer have upper surfaces which are coplanar with each other. In another embodiment, the GaN device layer does not directly underlie the silicon device layer, and the silicon device layer does not directly underlie the GaN device layer. The semiconductor device can further include a silicon-based semiconductor device formed on and/or within the silicon device layer, and a nitride-based semiconductor device formed on and/or within the GaN device layer. The GaN device layer can include a plurality of layers which can be formed as conformal blanket layers and then planarized, or which can be selectively formed then planarized.07-28-2011
20100059759NITRIDE SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR FORMING THE SAME - An active layer 03-11-2010
20130168688NITRIDE BASED SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A nitride based semiconductor device includes a first metallic junction layer, a Schottky junction layer on the first metallic junction layer, a first group III nitride semiconductor layer on the Schottky junction layer, a first insulating pattern layer on the first group III nitride semiconductor layer, the first insulating layer pattern including curved protrusions, a second group III nitride semiconductor layer laterally grown on the first group III nitride semiconductor layer, a first type group III nitride semiconductor layer on the second group III nitride semiconductor layer, the first type group III nitride semiconductor layer being simultaneously doped with aluminum (Al) and silicon (Si), an ohmic junction layer formed on the first type group III nitride semiconductor layer, a second metallic junction layer on the ohmic junction layer, and a metallic supporting substrate on the second metallic junction layer.07-04-2013
20080217625NITRIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - It is an object of the present invention to provide a nitride semiconductor device with low parasitic resistance by lowering barrier height to reduce contact resistance at an interface of semiconductor and metal. The nitride semiconductor device includes a GaN layer, a device isolation layer, an ohmic electrode, an n-type Al09-11-2008
20110147762Integrated Nitride and Silicon Carbide-Based Devices - Monolithic electronic devices are providing including a high bandgap layer. A first type of nitride device is provided on a first portion of the high bandgap layer, the first nitride device including first and second implanted regions respectively defining source and drain regions of the first type of nitride device. A second type of nitride device, different from the first type of nitride device, is provided on a second portion of the high bandgap layer, the second type of nitride device including an implanted highly conductive region. At least a portion of the implanted highly conductive region of the second type of nitride device is coplanar with at least a portion of both the first and second implanted regions of the first type of nitride device.06-23-2011
20110147761TWO-TERMINAL SWITCHING DEVICES AND THEIR METHODS OF FABRICATION - Two-terminal switching devices characterized by high on/off current ratios and by high breakdown voltage are provided. These devices can be employed as switches in the driving circuits of active matrix displays, e.g., in electrophoretic, rotating element and liquid crystal displays. The switching devices include two electrodes, and a layer of a broad band semiconducting material residing between the electrodes. According to one example, the cathode comprises a metal having a low work function, the anode comprises an organic material having a p+ or p++ type of conductivity, and the broad band semiconductor comprises a metal oxide. The work function difference between the cathode and the anode material is preferably at least about 0.6 eV. The on/off current ratios of at least 10,000 over a voltage range of about 15 V can be achieved. The devices can be formed, if desired, on flexible polymeric substrates having low melting points.06-23-2011
20100025694Apparatus and method for transformation of substrate - A method is disclosed for forming a layer of a wide bandgap material in a non-wide bandgap material. The method comprises providing a substrate of a non-wide bandgap material and converting a layer of the non-wide bandgap material into a layer of a wide bandgap material. An improved component such as wide bandgap semiconductor device may be formed within the wide bandgap material through a further conversion process.02-04-2010
20100025693Wide band gap semiconductor device including junction field effect transistor - A wide band gap semiconductor device has a transistor cell region, a diode forming region, an electric field relaxation region located between the transistor cell region and the diode forming region, and an outer peripheral region surrounding the transistor cell region and the diode forming region. In the transistor cell region, a junction field effect transistor is disposed. In the diode forming region, a diode is disposed. In the electric field relaxation region, an isolating part is provided. The isolating part includes a trench dividing the transistor cell region and the diode forming region, a first conductivity-type layer disposed on an inner wall of the trench, and a second conductivity-type layer disposed on a surface of the first conductivity-type layer so as to fill the trench. The first conductivity-type layer and the second conductivity-type layer provide a PN junction.02-04-2010
20110215339Termination and contact structures for a high voltage GaN-based heterojunction transistor - A semiconductor device is provided that includes a substrate, a first active layer disposed over the substrate, and a second active layer disposed on the first active layer. The second active layer has a higher bandgap than the first active layer such that a two-dimensional electron gas layer arises between the first active layer and the second active layer. A termination layer, which is disposed on the second active layer, includes InGaN. Source, gate and drain contacts are disposed on the termination layer.09-08-2011
20120146045SEMICONDUCTOR LIGHT EMITTING DEVICE - According to one embodiment, a semiconductor light emitting device includes a light emitting layer, a light transmitting layer and a first semiconductor layer. The light transmitting layer is transmittable with respect to light emitted from the light emitting layer. The first semiconductor layer contacts the light transmitting layer between the light emitting layer and the light transmitting layer. The light transmitting layer has a thermal expansion coefficient larger than a thermal expansion coefficient of the light transmitting layer, has a lattice constant smaller than a lattice constant of the active layer, and has a tensile stress in an in-plane direction.06-14-2012
20100276697SEMICONDUCTOR DEVICE - Semiconductor devices having strong excitonic binding are disclosed. In some embodiments, a semiconductor device includes at least one active layer composed of a first compound, and at least one barrier layer composed of a second compound and disposed on at least one surface of the at least one active layer. An energy band gap of the at least one barrier layer is wider than energy band gap of the at least one active layer, and the first and/or second compounds are selected to strengthen an excitonic binding between an electron and a hole in the at least one active layer.11-04-2010
20100301347WAFER BONDING TECHNIQUE IN NITRIDE SEMICONDUCTORS - A semiconductor arrangement is provided that includes one or more substrate structures. One or more nitride-based material structures are used in fabricating nitride-based devices. One or more intermediary layers are interposed between the one or more substrate structures and the one or more nitride-based material structures. The one or more intermediary layers support the lattice mismatch and thermal expansion coefficients between the one or more nitride-based material structure and the one or more substrate structures. Several new electronic devices based on this arrangement are described.12-02-2010
20100314625GaN Single-Crystal Mass and Method of Its Manufacture, and Semiconductor Device and Method of Its Manufacture - Affords a GaN single-crystal mass, a method of its manufacture, and a semiconductor device and method of its manufacture, whereby when the GaN single-crystal mass is being grown, and when the grown GaN single-crystal mass is being processed into a substrate or like form, as well as when an at least single-lamina semiconductor layer is being formed onto a single-crystal GaN mass in substrate form to manufacture semiconductor devices, cracking is controlled to a minimum. The GaN single-crystal mass 12-16-2010
20110073871GALLIUM NITRIDE SUBSTRATE - A gallium nitride substrate comprising a primary surface, the primary surface being tilted at an angle in a range of 20 to 160 degrees with respect to a C-plane of the substrate, and the substrate having a fracture toughness of more than or equal to 1.36 MN/m03-31-2011
20110073870III-NITRIDE SEMICONDUCTOR LIGHT EMITTING DEVICE - The present III-nitride semiconductor light-emitting device comprises: a first III-nitride semiconductor layer having a first conductivity type; a second III-nitride semiconductor layer having a second conductivity type different from the first conductivity type; an active layer disposed between the first III-nitride semiconductor layer and the second III-nitride semiconductor layer and generating light by recombination of electrons and holes; and a depletion barrier layer brought into contact with the active layer and having a first conductivity type.03-31-2011
20110133207GROUP III NITRIDE SUBSTRATE, EPITAXIAL LAYER-PROVIDED SUBSTRATE, METHODS OF MANUFACTURING THE SAME, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A group III nitride substrate on which an epitaxially grown layer of good quality can be formed, and a method of manufacturing the same are obtained. A GaN substrate (06-09-2011
20120097969LIGHT EMITTING DIODE CHIP AND MANUFACTURING METHOD THEREOF - An exemplary LED chip includes a substrate, a buffer layer formed on the substrate and a light emitting layer formed on the buffer layer. The light emitting layer includes an n-type semiconductor layer and a p-type semiconductor layer. A first electrode is electrically connected with one of the n-type semiconductor layer and the p-type semiconductor layer. A second electrode is electrically connected with the other one of the n-type semiconductor layer and the p-type semiconductor layer. A bonding pad is formed on a top surface of the first electrode. A bonding wire is secured to the bonding pad. A ratio between a contacting area between the bonding pad and the top surface of the first electrode and an area of the top surface of the first electrode is no less than 6:10.04-26-2012
20110147763GROUP III NITRIDE SEMICONDUCTOR MULTILAYER STRUCTURE AND PRODUCTION METHOD THEREOF - According to the present invention, an AlN crystal film seed layer having high crystallinity is combined with selective/lateral growth, whereby a Group III nitride semiconductor multilayer structure more enhanced in crystallinity can be obtained. The Group III nitride semiconductor multilayer structure of the present invention is a Group III nitride semiconductor multilayer structure where an AlN crystal film having a crystal grain boundary interval of 200 nm or more is formed as a seed layer on a C-plane sapphire substrate surface by a sputtering method and an underlying layer, an n-type semiconductor layer, a light-emitting layer and a p-type semiconductor layer, each composed of a Group III nitride semiconductor, are further stacked, wherein regions in which the seed layer is present and is absent are formed on the C-plane sapphire substrate surface and/or regions capable of epitaxial growth and incapable of epitaxial growth are formed in the underlying layer.06-23-2011
20120032183GaN Based LED having Reduced Thickness and Method for Making the Same - A device having a carrier, a light-emitting structure, and first and second electrodes is disclosed. The light-emitting structure includes an active layer sandwiched between a p-type GaN layer and an n-type GaN layer, the active layer emitting light of a predetermined wavelength in the active layer when electrons and holes from the n-type GaN layer and the p-type GaN layer, respectively, combine therein. The first and second electrodes are bonded to the surfaces of the p-type and n-type GaN layers that are not adjacent to the active layer. The n-type GaN layer has a thickness less than 1.25 μm. The carrier is bonded to the light emitting structure during the thinning of the n-type GaN layer. The thinned light-emitting structure can be transferred to a second carrier to provide a device that is analogous to conventional LEDs having contacts on the top surface of the LED.02-09-2012
20080308816TRANSISTORS FOR REPLACING METAL-OXIDE SEMICONDUCTOR FIELD-EFFECT TRANSISTORS IN NANOELECTRONICS - Junction field effect transistors (JFETs) are shown to be a viable replacement for metal oxide semiconductor field effect transistors (MOSFETs) for gate lengths of less than about 40 nm, providing an alternative to the gate leakage problems presented by scaled down MOSFETs. Integrated circuit designs can have complementary JFET (CJFET) logic cells substituted for existing MOSFET-based logic cells to produce revised integrated circuit designs. Integrated circuits can include JFETS where the channel comprises a wide bandgap semiconductor material and the gate comprises a narrow bandgap semiconductor material. Mixtures of JFET and MOSFET transistors can be included on an integrated circuit design.12-18-2008
20110114967NITRIDE SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A nitride semiconductor device includes: a substrate; a first nitride semiconductor layer formed over the substrate; a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a larger band gap energy than the first nitride semiconductor layer; a third nitride semiconductor layer formed on the second nitride semiconductor layer and including a p-type nitride semiconductor with at least a single-layer structure; a gate electrode formed on the third nitride semiconductor layer; and a source electrode and a drain electrode formed in regions located on both sides of the gate electrode, respectively. The third nitride semiconductor layer has a thickness greater in a portion below the gate electrode than in a portion below the side of the gate electrode.05-19-2011
20090152565PENDEO EPITAXIAL STRUCTURES AND DEVICES - A substrate comprising a trench lateral epitaxial overgrowth structure including a trench cavity, wherein the trench cavity includes a growth-blocking layer or patterned material supportive of a coalescent Pendeo layer thereon, on at least a portion of an inside surface of the trench. Such substrate is suitable for carrying out lateral epitaxial overgrowth to form a bridged lateral overgrowth formation overlying the trench cavity. The bridged lateral overgrowth formation provides a substrate surface on which epitaxial layers can be grown in the fabrication of microelectronic devices such as laser diodes, high electron mobility transistors, ultraviolet light emitting diodes, and other devices in which low dislocation density is critical. The epitaxial substrate structures of the invention can be formed without the necessity for deep trenches, such as are required in conventional Pendeo epitaxial overgrowth structures.06-18-2009
20120305939LIGHT EMITTING DIODES INCLUDING BARRIER SUBLAYERS - Semiconductor light emitting devices, such as light emitting diodes, include a substrate, an epitaxial region on the substrate that includes a light emitting region such as a light emitting diode region, and a multilayer conductive stack including a reflector layer, on the epitaxial region. A barrier layer is provided on the reflector layer and extending on a sidewall of the reflector layer. The multilayer conductive stack can also include an ohmic layer between the reflector and the epitaxial region. The barrier layer further extends on a sidewall of the ohmic layer. The barrier layer can also extend onto the epitaxial region outside the multilayer conductive stack. The barrier layer can be fabricated as a series of alternating first and second sublayers.12-06-2012
20120305937SEMICONDUCTOR LIGHT-EMITTING DEVICE - A semiconductor light-emitting diode, and method of fabricating same, wherein an indium (In)-containing light-emitting layer, as well as subsequent device layers, is deposited on a textured surface. The resulting device is a phosphor-free white light source.12-06-2012
20120305938NITRIDE SEMICONDUCTOR LIGHT-EMITTING DEVICE - A semiconductor light emitting device is provided. The semiconductor light emitting device includes a first nitride layer, an active layer, and a second nitride layer. The first nitride layer includes an irregular, uneven surface, and the active layer is formed on the irregular, uneven surface. The second nitride layer is formed on the active layer. A plurality of quantum dots are formed at the active layer.12-06-2012
20120305936SEMICONDUCTOR DEVICE - A semiconductor device includes: a nitride semiconductor layer; a source electrode, a gate electrode and a drain electrode; an insulating layer covering at least the gate electrode and a part of the nitride semiconductor layer; and a field plate on the insulating layer, a width of a region of the field plate between an edge of the field plate of a side of the drain electrode and an edge of the side face of the insulating layer covering a side face of the gate electrode of a side of the drain electrode being 0.1 μm or more, a distance between an edge of the field plate and an edge of the drain electrode in a contact face between the nitride semiconductor layer and the drain electrode being 3.5 μm or more, an operating frequency of the semiconductor device being 4 GHz or less.12-06-2012
20120305934NITRIDE SEMICONDUCTOR LIGHT EMITTING ELEMENT AND METHOD FOR MANUFACTURING THE SAME - A nitride semiconductor light emitting element has: a substrate for growth; an n-type nitride semiconductor layer formed on the substrate for growth; a light emitting layer formed on the n-type nitride semiconductor layer; and a p-type nitride semiconductor layer formed on the light emitting layer, wherein pipe holes are formed at a density of 5000 pipe holes/cm12-06-2012
20120305932LATERAL TRENCH MESFET - A transistor includes a trench formed in a semiconductor body, the trench having sidewalls and a bottom. The transistor further includes a first semiconductor material disposed in the trench adjacent the sidewalls and a second semiconductor material disposed in the trench and spaced apart from the sidewalls by the first semiconductor material. The second semiconductor material has a different band gap than the first semiconductor material. The transistor also includes a gate material disposed in the trench and spaced apart from the first semiconductor material by the second semiconductor material. The gate material provides a gate of the transistor. Source and drain regions are arranged in the trench with a channel interposed between the source and drain regions in the first or second semiconductor material so that the channel has a lateral current flow direction along the sidewalls of the trench.12-06-2012
20120305931GOLD-FREE OHMIC CONTACTS - A semiconductor structure is provided having: a semiconductor; a gold-free electrically conductive structure in ohmic contact with the semiconductor; and a pair of electrically conductive layers separated by a layer of silicon. The structure includes: a refractory metal layer disposed in contact with the semiconductor; and wherein one of the pair of electrically conductive layers separated by the layer of silicon is the refractory metal layer. A second layer of silicon is disposed on a second one of the pair of pair of electrically conductive layers and including a third electrically conducive layer on the second layer of silicon. In one embodiment, the semiconductor includes a III-V material.12-06-2012
20120305933GROUP III NITRIDE SEMICONDUCTOR LIGHT-EMITTING DEVICE - A group III nitride semiconductor light-emitting device includes a GaN crystal substrate and at least one group III nitride semiconductor layer disposed on a main surface of the GaN crystal substrate. The substrate includes a matrix crystal region and a c-axis-inverted crystal region. An off angle θ is formed between the main surface and a {0001} plane, and an off-angle component of a first direction has an absolute value |θ12-06-2012
20120146046SEMICONDUCTOR APPARATUS AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes a first semiconductor layer formed on a substrate, a second semiconductor layer formed on the first semiconductor layer, a gate recess formed by removing at least a portion of the second semiconductor layer, an insulation film formed on the gate recess and the second semiconductor layer, a gate electrode formed on the gate recess via the insulation film, source and drain electrodes formed on one of the first and the second semiconductor layers, and a fluorine containing region formed in at least one of a part of the first semiconductor layer corresponding to a region in which the gate recess is formed and a part of the second semiconductor layer corresponding to the region in which the gate recess is formed.06-14-2012
20120146048GALLIUM NITRIDE COMPOUND SEMICONDUCTOR LIGHT-EMITTING DEVICE - Provided is a gallium nitride-based compound semiconductor light-emitting element, in which the concentration of Mg which is a p-type dopant in a p-GaN layer in which the (10-10) m-plane of a hexagonal wurtzite structure grows is adjusted in a range from 1.0×1006-14-2012
20120037919NANOPORE ELECTRICAL SENSOR - A nanopore electrical sensor is provided. The sensor has layered structure, including a substrate (02-16-2012
20120037918SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING SAME - A semiconductor device includes a semiconductor layer (02-16-2012
20100327291Single crystal group III nitride articles and method of producing same by HVPE method incorporating a polycrystalline layer for yield enhancement - In a method for making a GaN article, an epitaxial nitride layer is deposited on a single-crystal substrate. A 3D nucleation GaN layer is grown on the epitaxial nitride layer by HVPE under a substantially 3D growth mode. A GaN transitional layer is grown on the 3D nucleation layer by HVPE under a condition that changes the growth mode from the substantially 3D growth mode to a substantially 2D growth mode. A bulk GaN layer is grown on the transitional layer by HVPE under the substantially 2D growth mode. A polycrystalline GaN layer is grown on the bulk GaN layer to form a GaN/substrate bi-layer. The GaN/substrate bi-layer may be cooled from the growth temperature to an ambient temperature, wherein GaN material cracks laterally and separates from the substrate, forming a free-standing article.12-30-2010
20110057198TECHNIQUE FOR DEVELOPMENT OF HIGH CURRENT DENSITY HETEROJUNCTION FIELD EFFECT TRANSISTORS BASED ON (10-10)-PLANE GaN BY DELTA-DOPING - A delta (δ)-doped (10-10)-plane GaN transistor is disclosed. Delta doping can achieve a transistor having at least 10 times higher current density than a conventional (10-10)-plane GaN transistor.03-10-2011
20120153294Semiconductor Structures Having Directly Bonded Diamond Heat Sinks and Methods for Making Such Structures - A semiconductor structure is bonded directly to a diamond substrate by Van der Waal forces. The diamond substrate is formed by polishing a surface of diamond to a first degree of smoothness; forming a material, such as diamond, BeO, GaN, MgO, or SiO06-21-2012
20110315998EPITAXIAL WAFER, METHOD FOR MANUFACTURING GALLIUM NITRIDE SEMICONDUCTOR DEVICE, GALLIUM NITRIDE SEMICONDUCTOR DEVICE AND GALLIUM OXIDE WAFER - A gallium nitride based semiconductor device is provided which includes a gallium nitride based semiconductor film with a flat c-plane surface provided on a gallium oxide wafer. A light emitting diode LED includes a gallium oxide support base 12-29-2011
20110315996SEMICONDUCTOR DEVICE, LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING SAME - Disclosed are a semiconductor device, a light emitting device, and a method of manufacturing the same. The semiconductor device includes a substrate, a plurality of rods aligned on the substrate, a metal layer disposed on the substrate between the rods, and a semiconductor layer disposed on and between the rods. Electrical and optical characteristics of the semiconductor device are improved due to the metal layer.12-29-2011
20110316001METHOD FOR GROWING GROUP III-V NITRIDE FILM AND STRUCTURE THEREOF - A method for growing a Group III-V nitride film and a structure thereof are presented. The method is carried out by hydride vapor phase epitaxy (HVPE). The method includes the steps of, inter alia, slowly epitaxially growing a temperature ramping nitride layer on a substrate by rising a first growth temperature of 900-950° C. to a second growth temperature of 1000-1050° C. at a temperature-rising rate of 0.5-10° C./min. The lattice quality of the temperature ramping nitride layer is slowly transformed with the layer height, so that a stress induced by lattice mismatch between a sapphire substrate and a gallium nitride (GaN) layer is relieved.12-29-2011
20110316000MANUFACTURING OF LOW DEFECT DENSITY FREE-STANDING GALLIUM NITRIDE SUBSTRATES AND DEVICES FABRICATED THEREOF - The invention relates to a method for manufacturing a single crystal of nitride by epitaxial growth on a support (12-29-2011
20100012947PROCESS FOR MAKING A GaN SUBSTRATE - The invention relates to a process for making a GaN substrate (01-21-2010
20120043555LIQUID FLUORESCENT COMPOSITION AND LIGHT EMITTING DEVICE - The invention provides a liquid fluorescent composition. The liquid fluorescent composition includes at least (a) 0.001-2 parts by weight of a fluorescent material; and (b) 100 parts by weight of a cyclic solvent having a boiling point above 100° C. The invention also provides a light emitting device containing the above liquid fluorescent composition.02-23-2012
20120043554LIGHT-EMITTING DEVICES - Light-emitting devices, and related components, systems and methods are disclosed.02-23-2012
20120043553Hybrid Semiconductor Device Having a GaN Transistor and a Silicon MOSFET - A hybrid device including a silicon based MOSFET operatively connected with a GaN based device.02-23-2012
20120043552System and Method for Selected Pump LEDs with Multiple Phosphors - An LED pump light with multiple phosphors is described. LEDs emitting radiation at violet and/or ultraviolet wavelengths are used to pump phosphor materials that emit other colors. The LEDs operating in different wavelength ranges are arranged to reduce light re-absorption and improve light output efficiency.02-23-2012
20120043551Second contact schottky metal layer to improve GaN schottky diode performance - A Schottky diode includes a first nitride-based semiconductor layer disposed atop a substrate. A second nitride-based semiconductor layer is disposed atop a portion of the first nitride-based semiconductor layer. The second layer has a doping concentration lower than that of the first layer. A first Schottky contact metal layer having a first metal work function is disposed on a top planar surface of the second layer, forming a first Schottky junction. A second Schottky contact metal layer having a second metal work function is disposed atop of and laterally surrounding the first Schottky contact metal layer, the metal work function of the second metal layer is higher than that of the first metal layer. A metal layer disposed on first and second planar surfaces forms an ohmic contact with the first nitride-based semiconductor layer.02-23-2012
20120043550SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor light emitting device includes a stacked structural body, first and second electrodes, a high resistance layer and a transparent conductive layer. The stacked structural body includes first and second semiconductor layers and a light emitting layer. The first semiconductor layer is disposed between the first electrode and the second semiconductor layer. The second semiconductor layer is disposed between the second electrode and the first semiconductor layer. The second electrode has reflectivity with respect to luminescent light. The high resistance layer is in contact with the second semiconductor layer between the second semiconductor layer and the second electrode and includes a portion overlapping with the first electrode. The transparent conductive layer is in contact with the second semiconductor layer between the second semiconductor layer and the second electrode. The transparent conductive layer has a resistance lower than a resistance of the high resistance layer.02-23-2012
20120001195SEMICONDUCTOR SUBSTRATE AND SEMICONDUCTOR DEVICE - A semiconductor substrate inclu8des an AlN layer that is formed so as to contact a Si substrate and has an FWMH of a rocking curve of a (002) plane by x-ray diffraction, the FWMH being less than or equal to 1500 seconds, and a GaN-based semiconductor layer formed on the AlN layer.01-05-2012
20120001193Polishing method, polishing apparatus and GaN wafer - A polishing method can process and flatten, in a practical processing time and with high surface accuracy, a surface of a substrate of a Ga element-containing compound semiconductor. The polishing method includes: bringing a Ga element-containing compound semiconductor substrate (01-05-2012
20120001194SEMICONDUCTOR DEVICE - A semiconductor device includes a Si substrate having a principal plane that is a crystal surface inclined at an off angle of 0.1 degrees or less with respect to a (111) plane, an AlN layer that is provided so as to contact the principal plane of the Si substrate and is configured so that an FWHM of a rocking curve of a (002) plane by x-ray diffraction is not greater than 2000 seconds, and a GaN-based semiconductor layer formed on the AlN layer.01-05-2012
20120001196LIGHT EMITTING DEVICE, METHOD OF MANUFACTURING THE SAME, LIGHT EMITTING DEVICE PACKAGE, AND LIGHTING SYSTEM - Provided are a light emitting device, a method of manufacturing the same, a light emitting device package, and a lighting system. The light emitting device includes: a light emitting structure layer including a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer; an oxide protrusion disposed on at least a portion of the second conducive semiconductor layer; and a current spreading layer on the second conductive semiconductor layer and the oxide protrusion.01-05-2012
20110156051SEMICONDUCTOR DEVICES WITH LOW LEAKAGE SCHOTTKY CONTACTS - Embodiments include semiconductor devices with low leakage Schottky contacts. An embodiment is formed by providing a partially completed semiconductor device including a substrate, a semiconductor on the substrate, and a passivation layer on the semiconductor, and using a first mask, locally etching the passivation layer to expose a portion of the semiconductor. Without removing the first mask, a Schottky contact is formed of a first material on the exposed portion of the semiconductor, and the first mask is removed. Using a further mask, a step-gate conductor of a second material electrically coupled to the Schottky contact is formed overlying parts of the passivation layer adjacent to the Schottky contact. By minimizing the process steps between opening the Schottky contact window in the passivation layer and forming the Schottky contact material in this window, the gate leakage of a resulting field effect device having a Schottky gate may be substantially reduced.06-30-2011
20110156050SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME - The semiconductor device includes a GaN-based layered body having an opening and including an n-type drift layer and a p-type layer located on the n-type drift layer, a regrown layer including a channel and located so as to cover the opening, and a gate electrode located on the regrown layer and formed along the regrown layer, wherein the opening reaches the n-type drift layer, and an edge of the gate electrode is not located outside a region of the p-type layer when viewed in plan.06-30-2011
20110156049LED DEVICE AND FABRICATION METHOD THEREOF - A LED device includes a n-type first semiconductor layer, a p-type second semiconductor layer, an active layer between the first semiconductor layer and the second semiconductor layer, an electrode positioned on a surface of the second semiconductor layer away from the active layer, and an ohmic contacting layer positioned on a surface of the second semiconductor layer away from the active layer. The ohmic contacting layer includes a resistance region corresponding to the electrode and a conductive region surrounding the resistance region, in which the conductive region having less resistance than that of the resistance region.06-30-2011
20110156048NITRIDE-BASED SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A nitride-based semiconductor light-emitting device 06-30-2011
20110156047NITRIDE SEMICONDUCTOR TEMPLATE AND METHOD OF MANUFACTURING THE SAME - A nitride semiconductor template and a manufacturing method thereof are provided. The nitride semiconductor template includes a carrier substrate with a first thermal expansion coefficient, a nitride semiconductor layer with a second thermal expansion coefficient different from the first thermal expansion coefficient, and a bonding layer. The nitride semiconductor layer disposed on the carrier substrate is at least 10 μm in thickness. A ratio of a dislocation density of the nitride semiconductor layer at a first surface to that at a second surface is from 0.1 to 10. The bonding layer is disposed between the carrier substrate and the nitride semiconductor layer to adhere the nitride semiconductor layer onto the carrier substrate. The second surface is near an interface between the nitride semiconductor layer and the bonding layer, and the first surface is 10 μm from the second surface.06-30-2011
20100171124Low-defect density gallium nitride semiconductor structures and fabrication methods - A low-defect gallium nitride structure including a first gallium nitride layer comprising a plurality of gallium nitride columns etched into the first gallium nitride layer and a first dislocation density; and a second gallium nitride layer that extends over the gallium nitride columns and comprises a second dislocation density, wherein the second dislocation density may be lower than the first dislocation density. In addition, a method for fabricating a gallium nitride semiconductor layer that includes masking an underlying gallium nitride layer with a mask that comprises an array of columns and growing the underlying gallium nitride layer through the columns and onto said mask using metal-organic chemical vapor deposition pendeo-epitaxy to thereby form a pendeo-epitaxial gallium nitride layer coalesced on said mask to form a continuous pendeo-epitaxial monocrystalline gallium nitride semiconductor layer.07-08-2010
20120012859LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided are a light emitting device and a method of manufacturing the same. A light emitting device includes an active layer; a first conductive semiconductor layer on the active layer; a second conductive semiconductor layer on the active layer so that the active layer is disposed between the first and second conductive semiconductor layers; and a photonic crystal structure comprising a first light extraction pattern on the first conductive semiconductor layer having a first period, and second light extraction pattern on the first conductive semiconductor layer having a second period, the first period being greater than λ/n, and the second period being identical to or smaller than λ/n, where n is a refractive index of the first conductive semiconductor layer, and λ is a wavelength of light emitted from the active layer.01-19-2012
20120056193Series Connected Segmented LED - A light source and method for making the same are disclosed. The light source includes a conducting substrate, and a light emitting structure that is divided into segments. The light emitting structure includes a first layer of semiconductor material of a first conductivity type deposited on the substrate, an active layer overlying the first layer, and a second layer of semiconductor material of an opposite conductivity type from the first conductivity type overlying the active layer. A barrier divides the light emitting structure into first and second segments that are electrically isolated from one another. A serial connection electrode connects the first layer in the first segment to the second layer in the second segment. A power contact is electrically connected to the second layer in the first segment, and a second power contact electrically connected to the first layer in the second segment.03-08-2012
20120056192COMPOUND SEMICONDUCTOR IMAGE SENSOR - A stack-type image sensor using a compound semiconductor. The stack-type image sensor includes a stack of photoelectric conversion units which are sequentially arranged in a light incident direction and which absorb light in ascending order of a wavelength from shortest to longest.03-08-2012
20120056191SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME, AND POWER SUPPLY APPARATUS - A semiconductor device includes a GaN electron transport layer provided over a substrate; a first AlGaN electron supply layer provided over the GaN electron transport layer; an AlN electron supply layer provided over the first AlGaN electron supply layer; a second AlGaN electron supply layer provided over the AlN electron supply layer; a gate recess provided in the second AlGaN electron supply layer and the AlN electron supply layer; and a gate electrode provided over the gate recess.03-08-2012
20120153296SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC DEVICE INCLUDING THE SEMICONDUCTOR DEVICE - A semiconductor device, a method of manufacturing the semiconductor device, and an electronic device including the semiconductor device are provided. The semiconductor device includes a silicon substrate; a plurality of nanorods formed on the silicon substrate; and a nitride semiconductor layer formed on the silicon substrate and the plurality of nanorods, wherein a plurality of voids are formed between the silicon substrate and the nitride semiconductor in regions between the plurality of nanorods.06-21-2012
20120007100LIGHT EMITTING DEVICE - Disclosed is a light emitting device including a substrate, a reflective layer provided on the substrate, and a light emitting structure, which includes a first conductive semiconductor layer, a second conductive semiconductor layer and an active layer placed between the first and second conductive semiconductor layers, wherein the first conductive semiconductor layer is an n-type semiconductor layer including GaN and doped with an n-type dopant, wherein the first conductive semiconductor layer includes a first n-type semiconductor layer and a second n-type semiconductor layer between the first n-type semiconductor layer and the active layer, wherein one surface of the first n-type semiconductor layer contacts the second n-type semiconductor layer, and wherein the surface of the first n-type semiconductor layer contacting the second n-type semiconductor layer is formed in an N-phase. The disclosed light emitting device may have improved luminous efficacy while showing reduction in crystal defects.01-12-2012
20120007097SCHOTTKY DIODE WITH COMBINED FIELD PLATE AND GUARD RING - A Schottky diode comprising a merged guard ring and field plate defining a Schottky contact region is provided. A Schottky metal is formed over at least partially over the Schottky contact region and at least partially over the merged guard ring and field plate.01-12-2012
20120007102High Voltage Device and Method for Optical Devices - A light emitting device comprising a gallium and nitrogen containing substrate. The device also has an electrically isolating material grown between the substrate and an active region such that the light emitting device is operable at a voltage greater than 10V.01-12-2012
20120007101SEMICONDUCTOR LIGHT-EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor light-emitting device, and a method of manufacturing the same. The semiconductor light-emitting device includes a first electrode layer, an insulating layer, a second electrode layer, a second semiconductor layer, an active layer, and a first semiconductor layer that are sequentially stacked on a substrate, a first contact that passes through the substrate to be electrically connected to the first electrode layer, and a second contact that passes through the substrate, the first electrode layer, and the insulating layer to communicate with the second electrode layer. The first electrode layer is electrically connected to the first semiconductor layer by filling a contact hole that passes through the second electrode layer, the second semiconductor layer, and the active layer, and the insulating layer surrounds an inner circumferential surface of the contact hole to insulate the first electrode layer from the second electrode layer.01-12-2012
20120007099MULTI-GAS SENSOR AND METHOD OF FABRICATING THE SENSOR - The present invention is a multi-gas sensor and a method for fabricating the multi-gas sensor.01-12-2012
20120007098TRANSISTOR AND METHOD FOR PRODUCING TRANSISTOR - Certain embodiments provide a transistor including a semiconductor conductive layer, a drain electrode, a source electrode, and a gate electrode. The semiconductor device is III nitride-based semiconductor conductive layer including an active layer, formed on a surface of a substrate. The drain electrode and the source electrode have a titanium layer and an aluminum layer formed on the titanium layer and having a film thickness ratio of 12 to 15 with respect to the titanium layer, and the drain electrode and the source electrode come into ohmic contact with the semiconductor layer. The gate electrode is in Schottky junction with the semiconductor layer between the drain electrode and source electrode.01-12-2012
20120119223Gallium Nitride Semiconductor Structures with Compositionally-Graded Transition Layer - The invention provides semiconductor materials including a gallium nitride material layer formed on a silicon substrate and methods to form the semiconductor materials. The semiconductor materials include a transition layer formed between the silicon substrate and the gallium nitride material layer. The transition layer is compositionally-graded to lower stresses in the gallium nitride material layer which can result from differences in thermal expansion rates between the gallium nitride material and the substrate. The lowering of stresses in the gallium nitride material layer reduces the tendency of cracks to form. Thus, the invention enables the production of semiconductor materials including gallium nitride material layers having few or no cracks. The semiconductor materials may be used in a number of microelectronic and optical applications.05-17-2012
20120119222TECHNIQUE FOR THE GROWTH OF PLANAR SEMI-POLAR GALLIUM NITRIDE - A method for growing planar, semi-polar nitride film on a miscut spinel substrate, in which a large area of the planar, semi-polar nitride film is parallel to the substrate's surface. The planar films and substrates are: (1) {1005-17-2012
20120119221SEMICONDUCTOR LIGHT EMITTING DEVICES INCLUDING FLEXIBLE UNITARY FILM ON ALUMINUM NITRIDE SUBSTRATE - Semiconductor light emitting devices include an aluminum nitride substrate, a light emitting diode on a face of the substrate and flexible silicone film that includes a silicone lens on the face of the substrate. The light emitting diode emits light through the silicone lens.05-17-2012
20120119219NITRIDE SEMICONDUCTOR ELEMENT AND NITRIDE SEMICONDUCTOR PACKAGE - A nitride semiconductor element capable of accommodating GaN electron transfer layers of a wide range of thickness, so as to allow greater freedom of device design, and a nitride semiconductor element package with excellent voltage tolerance performance and reliability are provided. On a substrate (05-17-2012
20120119218METHOD FOR FORMING A SEMICONDUCTOR DEVICE USING SELECTIVE EPITAXY OF GROUP III-NITRIDE - A method for forming a single crystalline Group-III Nitride film. A substrate is provided, having a first passivation layer, a monocrystalline layer, and a second passivation layer. The substrate is patterned to form a plurality of features with elongated sidewalls having a second crystal orientation. Group-III Nitride films are formed on the elongated sidewalls, but not on the first or second passivation layers. In one embodiment, the dimensions of the patterned features and the film deposition process result in a single crystalline Group-III Nitride film having a third crystal orientation normal to the substrate surface. In another embodiment, the dimensions and orientation of the patterned features and the film deposition process result in a plurality of single crystalline Group-III Nitride films. In other embodiments, additional layers are formed on the Group-III Nitride film or films to form semiconductor devices, for example, a light-emitting diode.05-17-2012
20120205663SEMICONDUCTOR DEVICE, POWER-SUPPLY UNIT, AMPLIFIER AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device, includes a semiconductor layer formed above a substrate; an insulating film formed on the semiconductor layer; and an electrode formed on the insulating film. The insulating film has a membrane stress at a side of the semiconductor layer lower than a membrane stress at a side of the electrode.08-16-2012
20120205665HIGH-QUALITY NON-POLAR/SEMI-POLAR SEMICONDUCTOR DEVICE ON POROUS NITRIDE SEMICONDUCTOR AND MANUFACTURING METHOD THEREOF - Provided are a high-quality non-polar/semi-polar semiconductor device having reduced defect density of a nitride semiconductor layer and improved internal quantum efficiency and light extraction efficiency, and a manufacturing method thereof. The method for manufacturing a semiconductor device is to form a template layer and a semiconductor device structure on a sapphire, SiC or Si substrate having a crystal plane for a growth of a non-polar or semi-polar nitride semiconductor layer. The manufacturing method includes: forming a nitride semiconductor layer on the substrate; performing a porous surface modification such that the nitride semiconductor layer has pores; forming the template layer by re-growing a nitride semiconductor layer on the surface-modified nitride semiconductor layer; and forming the semiconductor device structure on the template layer.08-16-2012
20100148183Method of Forming a Carbon Nanotube-Based Contact to Semiconductor - Manufacturers encounter limitations in forming low resistance ohmic electrical contact to semiconductor material P-type Gallium Nitride (p-GaN), commonly used in photonic applications, such that the contact is highly transparent to the light emission of the device. Carbon nanotubes (CNTs) can address this problem due to their combined metallic and semiconducting characteristics in conjunction with the fact that a fabric of CNTs has high optical transparency. The physical structure of the contact scheme is broken down into three components, a) the GaN, b) an interface material and c) the metallic conductor. The role of the interface material is to make suitable contact to both the GaN and the metal so that the GaN, in turn, will make good electrical contact to the metallic conductor that interfaces the device to external circuitry. A method of fabricating contact to GaN using CNTs and metal while maintaining protection of the GaN surface is provided.06-17-2010
20080210949SEMICONDUCTOR SUBSTRATE AND SEMICONDUCTOR DEVICE USING THE SAME - A semiconductor substrate includes: an AlN layer provided on a silicon substrate; an AlGaN layer that is provided on the AlN layer and has an Al composition ratio of 0.3 to 0.6; and a GaN layer provided on the AlGaN layer.09-04-2008
20130193443SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FORMANUFACTURING THE SAME - According to one embodiment, a semiconductor light emitting device includes a semiconductor stacked unit and a silver layer. The semiconductor stacked unit includes a light emitting layer, and a semiconductor layer containing gallium provided on the light emitting layer. The silver layer contacts the semiconductor layer. A peak height belonging to a (100) plane of silver is not more than 3% of a peak height belonging to a (111) plane in an X-ray analysis. A detected intensity of a complex of gallium and nitrogen atoms at a first position is 1/100 of a maximum value in the semiconductor layer in a mass analysis. A detected intensity of gallium atoms at a second position at 40 nm distance from the first position is higher than 0.4% and lower than 3.8% of a maximum value of the detected intensity of gallium atoms in the semiconductor layer in the mass analysis.08-01-2013
20130193444HIGH VOLTAGE SWITCHING DEVICES AND PROCESS FOR FORMING SAME - The present invention relates to various switching device structures including Schottky diode, P-N diode, and P-I-N diode, which are characterized by low defect density, low crack density, low pit density and sufficient thickness (>2.5 um) GaN layers of low dopant concentration (<1E16 cm08-01-2013
20120012857WIDE-GAP SEMICONDUCTOR SUBSTRATE AND METHOD TO FABRICATE WIDE-GAP SEMICONDUCTOR DEVICE USING THE SAME - A wide-gap semiconductor substrate includes a narrow-gap semiconductor layer, a wide-gap semiconductor layer and an alignment mark. The narrow-gap semiconductor layer has a main surface. The wide-gap semiconductor layer is epitaxially grown on the narrow-gap semiconductor layer. The alignment mark is preliminarily carved in a prescribed position on the main surface so that the alignment mark is preliminarily buried in the wide-gap semiconductor substrate.01-19-2012
20120012856GaN Light Emitting Diode and Method for Increasing Light Extraction on GaN Light Emitting Diode Via Sapphire Shaping - A method for enhancing light extraction efficiency of GaN light emitting diodes is disclosed. By cutting off a portion from each end of bottom of a sapphire substrate or forming depressions on the bottom of the substrate and forming a reflector, light beams emitted to side walls of the substrate can be guided to the light emitting diodes.01-19-2012
20120012855SOLID-STATE LIGHT EMITTERS HAVING SUBSTRATES WITH THERMAL AND ELECTRICAL CONDUCTIVITY ENHANCEMENTS AND METHOD OF MANUFACTURE - Solid-state lighting devices (SSLDs) including a carrier substrate with conductors and methods of manufacturing SSLDs. The conductors can provide (a) improved thermal conductivity between a solid-state light emitter (SSLE) and a package substrate and (b) improved electrical conductivity for the SSLE. In one embodiment, the conductors have higher thermal and electrical conductivities than the carrier substrate supporting the SSLE.01-19-2012
20090072239Gallium oxide single crystal composite, process for producing the same, and process for producing nitride semiconductor film utilizing gallium oxide single crystal composite - Provided are: a gallium oxide single crystal composite, which can provide, for example, upon a crystal growth of a nitride semiconductor, a high-quality cubic crystal in which mixing of a hexagonal crystal is reduced to thereby realize dominant growth of a cubic crystal over hexagonal crystal, and which can be utilized as a substrate particularly suitable for epitaxial growth of cubic GaN; a process for producing the same; and a process for producing a nitride semiconductor film. The gallium oxide single crystal composite has a gallium nitride layer formed of cubic gallium nitride on a surface of the gallium oxide single crystal; the process for producing the gallium oxide single crystal composite includes subjecting the surface of gallium oxide single crystal to nitriding treatment using ECR plasma or RF plasma to form the gallium nitride layer formed of cubic gallium nitride on the surface of the gallium oxide single crystal; and further, the process for producing the nitride semiconductor film includes growing the nitride semiconductor film on the surface of the gallium oxide single crystal composite by an RF-MBE method.03-19-2009
20100327292METHOD OF OBTAINING BULK MONO-CRYSTALLINE GALLIUM-CONTAINING NITRIDE, BULK MONO-CRYSTALLINE GALLIUM-CONTAINING NITRIDE, SUBSTRATES MANUFACTURED THEREOF AND DEVICES MANUFACTURED ON SUCH SUBSTRATES - The invention is related to a method of obtaining bulk mono-crystalline gallium-containing nitride, comprising a step of seeded crystallization of mono-crystalline gallium-containing nitride from supercritical ammonia-containing solution, containing ions of Group I metals and ions of acceptor dopant, wherein at process conditions the molar ratio of acceptor dopant ions to supercritical ammonia-containing solvent is at least 0.0001. According to said method, after said step of seeded crystallization the method further comprises a step of annealing said nitride at the temperature between 950° C. and 1200° C., preferably between 950° C. and 1150° C.12-30-2010
20100059761SCHOTTKY BARRIER DIODE - A Schottky barrier diode includes a GaN freestanding substrate having a front surface, a GaN epitaxial layer deposited on the front surface, and an insulation layer deposited on the GaN epitaxial layer at a front surface and having an opening. Furthermore, the Schottky barrier diode also includes an electrode. The electrode is configured by a Schottky electrode provided in the opening in contact with the GaN epitaxial layer, and a field plate electrode connected to the Schottky electrode and also overlapping the insulation layer. The GaN freestanding substrate has a dislocation density of at most 1×1003-11-2010
20110049529GaN-BASED SEMICONDUCTOR ELEMENT AND METHOD OF MANUFACTURING THE SAME - Provided is a GaN series semiconductor element, which is capable of obtaining an adequate normally-off characteristic, and a manufacturing method thereof.03-03-2011
20110049528METHODS FOR FABRICATING COMPOUND MATERIAL WAFERS - Reconditioned donor substrates that include a remainder substrate from a donor substrate wherein the remainder substrate has a detachment surface where a transfer layer was detached and an opposite surface; and an additional layer deposited upon the opposite surface of the remainder substrate to increase its thickness and to form the reconditioned substrate. The reconditioned substrate is recycled as a donor substrate for fabricating compound material wafers and is typically made from gallium nitride donor substrates.03-03-2011
20110049527SEMICONDUCTOR DEVICE - A semiconductor device comprising: an active layer, which has a composition represented by the formula: Al03-03-2011
20110049526Semiconductor Devices with Field Plates - A III-N device is described with a III-N material layer, an insulator layer on a surface of the III-N material layer, an etch stop layer on an opposite side of the insulator layer from the III-N material layer, and an electrode defining layer on an opposite side of the etch stop layer from the etch stop layer from the insulator layer. A recess is formed in the electrode defining layer. An electrode is formed in the recess. The insulator can have a precisely controlled thickness, particularly between the electrode and III-N material layer.03-03-2011
20120104412HIGH LIGHT EXTRACTION EFFICIENCY NITRIDE BASED LIGHT EMITTING DIODE BY SURFACE ROUGHENING - A III-nitride light emitting diode (LED) and method of fabricating the same, wherein at least one surface of a semipolar or nonpolar plane of a III-nitride layer of the LED is textured, thereby forming a textured surface in order to increase light extraction. The texturing may be performed by plasma assisted chemical etching, photolithography followed by etching, or nano-imprinting followed by etching.05-03-2012
20120205662SEMICONDUCTOR DEVICE, POWER SUPPLY DEVICE, AMPLIFIER, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor layer formed over a substrate; an insulating film formed over the semiconductor layer; and an electrode formed over the insulating film, wherein the insulating film includes an amorphous film including carbon.08-16-2012
20120061680GALLIUM NITRIDE BASED SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - Gallium nitride (GaN) based semiconductor devices and methods of manufacturing the same. The GaN-based semiconductor device may include a heat dissipation substrate (that is, a thermal conductive substrate); a GaN-based multi-layer arranged on the heat dissipation substrate and having N-face polarity; and a heterostructure field effect transistor (HFET) or a Schottky electrode arranged on the GaN-based multi-layer. The HFET device may include a gate having a double recess structure. While such a GaN-based semiconductor device is being manufactured, a wafer bonding process and a laser lift-off process may be used.03-15-2012
20120205664SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - Provided is a semiconductor light emitting device and a method for manufacturing the same. The semiconductor light emitting device comprises: an active layer; a first nitride semiconductor layer on the active layer; a first delta-doped layer on the first nitride semiconductor layer; a second nitride semiconductor layer on the first delta-doped layer; a second delta-doped layer on the second nitride semiconductor layer; a third nitride semiconductor layer on the second delta-doped layer.08-16-2012
20120205661SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a supporting substrate, a conductive layer placed on the supporting substrate, and at least one group III nitride semiconductor layer placed on the conductive layer. Of the group III nitride semiconductor layers, a conductive-layer-neighboring group III nitride semiconductor layer has n type conductivity, dislocation density of at most 1×1008-16-2012
20120068187SOLID STATE LIGHTING DEVICES WITH IMPROVED COLOR UNIFORMITY AND METHODS OF MANUFACTURING - Solid state lighting (SSL) devices with good color uniformity and methods of manufacturing are disclosed herein. In one embodiment, an SSL device includes a support structure, an SSL die in the support structure, and a converter material at least partially encapsulating the SSL die. The converter material is configured to emit under excitation. The converter material has a surface facing away from the SSL die, and the surface of the converter material has a generally convex shape.03-22-2012
20110042684Method of Growing AlN Crystals, and AlN Laminate - Affords an AlN crystal growth method, and an AlN laminate, wherein AlN of favorable crystalline quality is grown. The AlN crystal growth method is provided with the following steps. To begin with, a source material (02-24-2011
20110042682INCLUSION-FREE UNIFORM SEMI-INSULATING GROUP III NITRIDE SUBSTRATES AND METHODS FOR MAKING SAME - In a method for making an inclusion-free uniformly semi-insulating GaN crystal, an epitaxial nitride layer is deposited on a substrate. A 3D nucleation GaN layer is grown on the epitaxial nitride layer by HVPE under a substantially 3D growth mode, wherein a surface of the nucleation layer is substantially covered with pits and the aspect ratio of the pits is essentially the same. A GaN transitional layer is grown on the nucleation layer by HVPE under a condition that changes the growth mode from the substantially 3D growth mode to a substantially 2D growth mode. After growing the transitional layer, a surface of the transitional layer is substantially pit-free. A bulk GaN layer is grown on the transitional layer by HVPE. After growing the bulk layer, a surface of the bulk layer is smooth and substantially pit-free. The GaN is doped with a transition metal during at least one of the foregoing GaN growth steps.02-24-2011
20120153295IONIC JUNCTION FOR RADIATION DETECTORS - Radiation detector. The detector includes an ionic junction having an ionically bonded wide band gap material having a first region dominated by positively charged ionic defects in intimate contact with a second region dominated by negatively charged ionic defects forming depleted regions on both sides of the junction resulting in a built-in electric field. The detector also includes an ionic junction having a first ionically bonded wide band gap material dominated by positively charged ionic defects in intimate contact with a second ionically bonded wide band gap material dominated by negatively charged ionic defects forming depleted regions on both sides of the junction resulting in a built-in electric field. Circuit means are provided to establish a voltage across the junction so that radiation impinging upon the junction will cause a current to flow in the circuit.06-21-2012
20120153297OHMIC CATHODE ELECTRODE ON THE BACKSIDE OF NONPOLAR M-PLANE (1-100) AND SEMIPOLAR (20-21) BULK GALLIUM NITRIDE SUBSTRATES - Ohmic cathode electrodes are formed on the backside of nonpolar m-plane (1-100) and semipolar (20-21) bulk gallium nitride (GaN) substrates. The GaN substrates are thinned using a mechanical polishing process. For m-plane GaN, after the thinning process, dry etching is performed, followed by metal deposition, resulting in ohmic I-V characteristics for the contact. For (20-21) GaN, after the thinning process, dry etching is performed, followed by metal deposition, followed by annealing, resulting in ohmic I-V characteristics for the contact as well.06-21-2012
20110089430Compound semiconductor device and method for fabricating the same - The compound semiconductor device comprises an i-GaN buffer layer 04-21-2011
20120119220NITRIDE SEMICONDUCTOR STRUCTURE - A nitride semiconductor substrate includes an epitaxy substrate, a patterned nitride semiconductor pillar layer, a nitride semiconductor layer, and a mask layer is provided. The nitride semiconductor pillar layer includes a plurality of first patterned arranged hollow structures and a plurality of second patterned arranged hollow structures formed among the first patterned arranged hollow structures. The second patterned arranged hollow structures have nano dimensions. The nitride semiconductor pillar layer is formed on the epitaxy substrate, and the nitride semiconductor layer is formed on the nitride semiconductor pillar layer. The mask layer covers surfaces of the nitride semiconductor pillar layer and the epitaxy substrate.05-17-2012
20130015466EPITAXIAL SUBSTRATE FOR SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - Provided is an epitaxial substrate for a semiconductor device, which has excellent schottky contact characteristics that are stable over time. The epitaxial substrate for a semiconductor device includes a base substrate, a channel layer formed of a first group III nitride containing at least Ga and having a composition of In01-17-2013
20120161152EPITAXIAL SUBSTRATE AND METHOD FOR MANUFACTURING EPITAXIAL SUBSTRATE - Provided is a crack-free epitaxial substrate having a small amount of warping, in which a silicon substrate is used as a base substrate. The epitaxial substrate includes a (111) single crystal Si substrate, a buffer layer, and a crystal layer. The buffer layer is formed of a first lamination unit and a second lamination unit being alternately laminated. The first lamination unit includes a composition modulation layer and a first intermediate layer. The composition modulation layer is formed of a first unit layer and a second unit layer having different compositions being alternately and repeatedly laminated so that a compressive strain exists therein. The first intermediate layer enhances the compressive strain existing in the composition modulation layer. The second lamination unit is a second intermediate layer that is substantially strain-free.06-28-2012
20120161153SEMICONDUCTOR DEVICE - A semiconductor device of one embodiment, including the semiconductor layer including a III-V group nitride semiconductor; a groove portion formed in the semiconductor layer; the gate insulating film formed at least on a bottom surface of the groove portion, the gate insulating film being a stacked film of a first insulating film and a second insulating film of which dielectric constant is higher than that of the first insulating film; the gate electrode formed on the gate insulating film; and a source electrode and a drain electrode formed on the semiconductor layer across the gate electrode, in which the second insulating film is selectively formed only under the gate electrode.06-28-2012
20120161151SOLID STATE LIGHTING DEVICES AND ASSOCIATED METHODS OF MANUFACTURING - Solid state lighting devices and associated methods of manufacturing are disclosed herein. In one embodiment, a solid state light device includes a light emitting diode with an N-type gallium nitride (GaN) material, a P-type GaN material spaced apart from the N-type GaN material, and an indium gallium nitride (InGaN) material directly between the N-type GaN material and the P-type GaN material. At least one of the N-type GaN, InGaN, and P-type GaN materials has a non-planar surface.06-28-2012
20120161150METHOD FOR DETERMINING THE STRUCTURE OF A TRANSISTOR - A method for determining the structure of a transistor having at least one first layer including GaN, one second layer including Al06-28-2012
20120161149INTERMEDIATE EPITAXIAL STRUCTURE AND METHOD FOR FABRICATING AN EPITAXIAL STRUCTURE - A method for fabricating an epitaxial structure includes: (a) forming over a temporary substrate a patterned sacrificial layer that partially exposes the temporary substrate; (b) growing laterally and epitaxially a temporary epitaxial film over the patterned sacrificial layer and the temporary substrate; (c) forming over the temporary epitaxial film an etching-stop layer; (d) forming an epitaxial layer unit over the etching-stop layer; (e) removing the patterned sacrificial layer using a first etchant; and (f) removing the temporary epitaxial film using a second etchant.06-28-2012
20120161148NITRIDE SEMICONDUCTOR SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME - A nitride semiconductor substrate and a method for manufacturing the same are provided. The nitride semiconductor substrate includes a base material, a patterned nitride semiconductor, a protection layer, and a nitride semiconductor layer. The patterned nitride semiconductor layer is located on the base material and includes a plurality of nanorod structures and a plurality of block patterns, and an upper surface of the nanorod structures is substantially coplanar with an upper surface of the block patterns. The protection layer covers a side wall of the nanorod structure sand a side wall of the block patterns. The nitride semiconductor layer is located on the patterned nitride semiconductor layer, and a plurality of nanopores are located between the nitride semiconductor layer and the patterned nitride semiconductor layer.06-28-2012
20120161147HIGH TEMPERATURE STRAIN SENSOR - An example sensor that includes a first Schottky diode, a second Schottky diode and an integrated circuit. The sensor further includes a voltage generator that generates a first voltage across the first Schottky diode and a second voltage across the second Schottky diode. When the first Schottky diode and the second Schottky diode are subjected to different strain, the integrated circuit measures the values of the currents flowing through the first Schottky diode and the second Schottky diode to determine the strain on an element where the first Schottky diode and the second Schottky diode are attached.06-28-2012
20120161146SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The present invention includes a semiconductor substrate, a gate electrode which is provided on the semiconductor substrate, a source electrode and a drain elect rode which are provided on the semiconductor substrate to sandwich the gate electrode, and a recess provided below edges of the gate electrode at least on a drain electrode side.06-28-2012
20120211766IMAGE DISPLAY DEVICE AND LIGHT EMISSION DEVICE - An image display device including a light emission section which emits light to an intensity adjusting section and a wavelength conversion section which change the intensity and wavelength of the emitted light. Phosphors and phosphor like materials are employed in wavelength conversion and a liquid crystal is employed for the light adjustment. The light emission device may include plural semiconductor light emitting elements having a different wavelength ranges such as diodes stacked in a compact and predetermined order such that wavelengths of light from each diode are emitted from the light emitting elements.08-23-2012
20120211765EPITAXIAL SUBSTRATE FOR SEMICONDUCTOR ELEMENT, SEMICONDUCTOR ELEMENT, AND METHOD FOR PRODUCING EPITAXIAL SUBSTRATE FOR SEMICONDUCTOR ELEMENT - Provided is an epitaxial substrate using a silicon substrate as a base substrate. An epitaxial substrate, in which a group of group-III nitride layers are formed on a (111) single crystal Si substrate such that a (0001) crystal plane of the group of group-III nitride layers is substantially in parallel with a surface of the substrate, includes: a first group-III nitride layer made of AlN with many defects configured of at least one kind from a columnar or granular crystal or domain; a second group-III nitride layer whose interface with the first group-III nitride layer is shaped into a three-dimensional concave-convex surface; and a third group-III nitride layer epitaxially formed on the second group-III nitride layer as a graded composition layer in which the proportion of existence of Al is smaller in a portion closer to a fourth group-III nitride.08-23-2012
20120211763NITRIDE SEMICONDUCTOR SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - A nitride semiconductor substrate suitable for a normally-off type high breakdown-voltage device and a method of manufacturing the substrate are provided allowing both a higher threshold voltage and improvement in current collapse.08-23-2012
20120211762SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND ELECTRONIC CIRCUIT - A semiconductor device includes: a semiconductor chip having an electrode; a lead corresponding to the electrode; a metal line coupling the electrode to the lead; a first resin portion covering a coupling portion between the metal line and the electrode and a coupling portion between the metal line and the lead; and a second resin portion covering the metal line, the first resin portion, and the semiconductor chip.08-23-2012
20120211761SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor layer disposed above a substrate; an insulating film formed by oxidizing a portion of the semiconductor layer; and an electrode disposed on the insulating film, wherein the insulating film includes gallium oxide, or gallium oxide and indium oxide.08-23-2012
20120211760SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME, AND POWER SUPPLY APPARATUS - A semiconductor device includes a nitride semiconductor stacked structure including a carrier transit layer and a carrier supply layer; a p-type nitride semiconductor layer provided over the nitride semiconductor stacked structure and including an active region and an inactive region; an n-type nitride semiconductor layer provided on the inactive region in the p-type nitride semiconductor layer; and a gate electrode provided over the active region in the p-type nitride semiconductor layer.08-23-2012
20120211759STRUCTURE AND METHOD TO REDUCE WAFER WARP FOR GALLIUM NITRIDE ON SILICON WAFER - The present disclosure provides a semiconductor structure. The semiconductor structure includes a dielectric material layer on a silicon substrate, the dielectric material layer being patterned to define a plurality of regions separated by the dielectric material layer; a first buffer layer disposed on the silicon substrate; a heterogeneous buffer layer disposed on the first buffer layer; and a gallium nitride layer grown on the heterogeneous buffer layer only within the plurality of regions.08-23-2012
20120313107Semiconductor Device - A semiconductor device includes a main body made of a GaN-based semiconductor material, and at least one electrode structure. The electrode structure includes an ohmic contact layer that is formed on the main body, a buffer layer that is formed on the ohmic contact layer opposite to the main body, and a circuit layer that is made of a copper-based material and that is formed on the buffer layer opposite to the ohmic contact layer. The ohmic contact layer is made of a material selected from titanium, aluminum, nickel, and alloys thereof. The buffer layer is made of a material different from the material of the ohmic contact layer and selected from titanium, tungsten, titanium nitride, tungsten nitride, and combinations thereof.12-13-2012
20100289029EPITAXIAL SUBSTRATE FOR SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING EPITAXIAL SUBSTRATE FOR SEMICONDUCTOR DEVICE - An epitaxial substrate having preferable two dimensional electron gas characteristic and contact characteristic is provided in the present invention. A channel layer is formed on a base substrate with GaN. A spacer layer is formed on the channel layer with AlN. A barrier layer is formed on the spacer layer with group III nitride having a composition of In11-18-2010
20120126242LIGHT EMITTING DEVICE AND LIGHTING APPARATUS - Provided are a light emitting device, a light emitting device package, and a lighting apparatus. The light emitting device includes: an n-type semiconductor layer including a first area and a second area in a plane; an n-type contact layer disposed on the n-type semiconductor layer and has a first thickness in the first area and a second thickness in the second area; an undoped semiconductor layer disposed on the n-type contact layer having the first thickness in the first area; an active layer disposed on the undoped semiconductor layer in the first area; a p-type semiconductor layer disposed on the active layer in the first area; a first electrode disposed on the n-type contact layer having the second thickness in the second area; and a second electrode disposed on the p-type semiconductor layer.05-24-2012
20120248459SUBSTRATE, TEMPLATE SUBSTRATE, SEMICONDUCTOR LIGHT EMITTING ELEMENT, SEMICONDUCTOR LIGHT EMITTING ELEMENT PRODUCING METHOD, ILLUMINATION DEVICE USING SEMICONDUCTOR LIGHT EMITTING ELEMENT AND ELECTRONIC DEVICE - Disclosed is a semiconductor light emitting element (LC) provided with a substrate (10-04-2012
20120248456NITRIDE SEMICONDUCTOR MULTILAYER STRUCTURE, METHOD FOR PRODUCING SAME, AND NITRIDE SEMICONDUCTOR LIGHT-EMITTING ELEMENT - The nitride semiconductor light-emitting element of the invention has a stacked structure of a buffer layer, an n-type nitride semiconductor layer, a light-emitting layer, and a p-type nitride semiconductor layer, on one surface side of a single crystal substrate of a sapphire substrate. A nitride semiconductor multilayer structure as the buffer layer includes: a plurality of island-like nuclei formed of AlN and formed on the one surface of the single crystal substrate; a first nitride semiconductor layer formed of an AlN layer and formed on the one surface side of the single crystal substrate so as to fill gaps between adjacent nuclei and to cover all the nuclei; and a second nitride semiconductor layer formed of an AlN layer and formed on the first nitride semiconductor layer.10-04-2012
20100207123LIGHT EMITTING DEVICE - A light emitting device is provided. The light emitting device may include a plurality of light emitting elements formed on a first common electrode, each light emitting element having a first conductive layer formed over the first common electrode. The light emitting device may also include an active layer formed over the first conductive layer, a second conductive layer formed over the active layer, and an insulator formed between adjacent light emitting elements. A plurality of electrodes may be respectively formed on the plurality of light emitting elements, and a second common electrode may couple the plurality electrodes. Such a light emitting structure may improve emission characteristics, heat dissipation and high temperature reliability.08-19-2010
20100207124COMPOUND SEMICONDUCTOR DEVICE INCLUDING AIN LAYER OF CONTROLLED SKEWNESS - A semiconductor epitaxial substrate includes: a single crystal substrate; an AlN layer epitaxially grown on the single crystal substrate; and a nitride semiconductor layer epitaxially grown on the AlN layer, wherein an interface between the AlN layer and nitride semiconductor layer has a larger roughness than an interface between the single crystal substrate and AlN layer, and a skewness of the upper surface of the AlN layer is positive.08-19-2010
20120168768SEMICONDUCTOR STRUCTURES AND METHOD FOR FABRICATING THE SAME - A semiconductor structure is provided. The semiconductor structure includes: a substrate; one or more semiconductor device layers formed on the substrate; and one or more lattice breaking areas formed on the surface of the substrate between the semiconductor device layers. The invention also provides a method for fabricating a semiconductor structure.07-05-2012
20120168766LATERAL EXTENDED DRAIN METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR (LEDMOSFET) WITH TAPERED DIELECTRIC PLATES TO ACHIEVE A HIGH DRAIN-TO-BODY BREAKDOWN VOLTAGE, A METHOD OF FORMING THE TRANSISTOR AND A PROGRAM STORAGE DEVICE FOR DESIGNING THE TRANSISTOR - A lateral, extended drain, metal oxide semiconductor, field effect transistor (LEDMOSFET) with a high drain-to-body breakdown voltage (Vb) incorporates gate structure extensions on opposing sides of a drain drift region. The extensions are tapered such that a distance between each extension and the drift region increases linearly from one end adjacent to the channel region to another end adjacent to the drain region. In one embodiment, these extensions can extend vertically through the isolation region that surrounds the LEDMOSFET. In another embodiment, the extensions can sit atop the isolation region. In either case, the extensions create a strong essentially uniform horizontal electric field profile within the drain drift. Also disclosed are a method for forming the LEDMOSFET with a specific Vb by defining the dimensions of the extensions and a program storage device for designing the LEDMOSFET to have a specific Vb.07-05-2012
20110180805GROUP-III NITRIDE SEMICONDUCTOR DEVICE, EPITAXIAL SUBSTRATE, AND METHOD OF FABRICATING GROUP-III NITRIDE SEMICONDUCTOR DEVICE - A III-nitride semiconductor device has a support base comprised of a III-nitride semiconductor and having a primary surface extending along a first reference plane perpendicular to a reference axis inclined at a predetermined angle ALPHA with respect to the c-axis of the III-nitride semiconductor, and an epitaxial semiconductor region provided on the primary surface of the support base. The epitaxial semiconductor region includes a plurality of GaN-based semiconductor layers. The reference axis is inclined at a first angle ALPHA07-28-2011
20110180804SOLID STATE LIGHT EMITTING DEVICE - A light emitting device comprises: an LED chip array comprising a plurality of LEDs formed on a single die (monolithic chip array) and at least one discrete LED that is separate from the LED chip array connected in series with the LED chip array. In an AC-drivable device the LED chip array is AC-drivable and two or more discrete LEDs are configured to be AC-drivable. The device can further comprise a package in which the LED chip array and discrete LED(s) are mounted. The discrete LEDs are configured such that positive and negative half wave periods of an AC drive voltage are mapped onto oppositely connected LED such that oppositely connected LED chips are alternately operable on a respective half wave period.07-28-2011
20120132922COMPOSITE SUBSTRATE WITH CRYSTALLINE SEED LAYER AND CARRIER LAYER WITH A COINCIDENT CLEAVAGE PLANE - A structure and a method can provide a crystalline seed layer material, such as GaN, on a crystalline carrier material, such as sapphire, aligned such that a common crystal plane exists between the two materials. The common crystal plane may provide for a fracture surface along a cleavage plane that may be oriented to be perpendicular to the top surface of an optoelectronic device as well as perpendicular to a light emission direction.05-31-2012
20120132921REDUCING WAFER DISTORTION THROUGH A HIGH CTE LAYER - Provided is a method of fabricating a semiconductor device. The method includes providing a silicon substrate having opposite first and second sides. At least one of the first and second sides includes a silicon (05-31-2012
20120313109Nitride Semiconductor Light Emitting Device and Fabrication Method Thereof - Provided is a nitride semiconductor light emitting device including: a first nitride semiconductor layer; an active layer formed above the first nitride semiconductor layer; and a delta doped second nitride semiconductor layer formed above the active layer. According to the present invention, the optical power of the nitride semiconductor light emitting device is enhanced, optical power down phenomenon is improved and reliability against ESD (electro static discharge) is enhanced.12-13-2012
20090057684Nitride semiconductor device and method for producing nitride semiconductor device - A nitride semiconductor device includes: a semiconductor base layer made of a conductive group III nitride semiconductor having a principal plane defined by a nonpolar plane or a semipolar plane; an insulating layer formed on the principal plane of the semiconductor base layer with an aperture partially exposing the principal plane; a nitride semiconductor multilayer structure portion, formed on a region extending onto the insulating layer from the aperture, having a parallel surface parallel to the principal plane of the semiconductor base layer as well as a +c-axis side first inclined surface and a −c-axis side second inclined surface inclined with respect to the principal plane of the semiconductor base layer and including two types of group III nitride semiconductor layers at least having different lattice constants; a gate electrode formed to be opposed to the second inclined surface; a source electrode arranged to be electrically connected with the group III nitride semiconductor layers; and a drain electrode formed on a back surface of the semiconductor base layer opposite to the principal plane.03-05-2009
20120168770HEAT DISSIPATION STRUCTURE OF CHIP - A heat dissipation structure of a chip in the field of microelectronics is provided. The heat dissipation structure includes a P-type superlattice layer and an N-type superlattice layer formed over an upper surface of the chip by oxidation isolation. The P-type superlattice and the N-type superlattice are isolated by silicon oxide. Through a contact hole the P-type superlattice is electrically connected to a metal layer that is applied with a low potential in the chip, and a metal layer to be connected with an external power source is formed over the P-type superlattice. Through a contact hole the N-type superlattice is electrically connected to a metal layer that is applied with a high-potential power source in the chip, and a metal layer to be connected with an external power source is formed over the N-type superlattice. The potential of the external power source connected with the P-type superlattice is lower than that of the external power source connected with the N-type superlattice. The present invention can achieve heat dissipation of the chip and meanwhile prevent the ambient heat from transferring into the chip, by using the feature that the superlattice has a low thermal conductivity and phonon-localization-like behavior.07-05-2012
20120168772PASSIVATION OF ALUMINUM NITRIDE SUBSTRATES - The present invention provides methods of protecting a surface of an aluminum nitride substrate. The substrate with the protected surface can be stored for a period of time and easily activated to be in a condition ready for thin film growth or other processing. In certain embodiments, the method of protecting the substrate surface comprises forming a passivating layer on at least a portion of the substrate surface by performing a wet etch, which can comprise the use of one or more organic compounds and one or more acids. The invention also provides aluminum nitride substrates having passivated surfaces.07-05-2012
20120168771SEMICONDUCTOR ELEMENT, HEMT ELEMENT, AND METHOD OF MANUFACTURING SEMICONDUCTOR ELEMENT - A semiconductor device is provided such that a reverse leak current is suppressed, and a Schottky junction is reinforced. The semiconductor device includes an epitaxial substrate formed by laminating a group of group-III nitride layers on a base substrate in such a manner that (0001) surfaces of said group-III nitride layers are substantially parallel to a substrate surface, and a Schottky electrode, in which the epitaxial substrate includes a channel layer formed of a first group-III nitride having a composition of In07-05-2012
20100051962Compound semiconductor device and the fabricating method of the same - A GaN layer functions as an electron transit layer and is formed to exhibit, at least at a portion thereof, A/B ratio of 0.2 or less obtained by a photoluminescence measurement, where “A” is the light-emission intensity in the 500-600 nm band, and “B” is the light-emission intensity at the GaN band-edge.03-04-2010
20100051961EPITAXIAL SUBSTRATE, SEMICONDUCTOR DEVICE SUBSTRATE, AND HEMT DEVICE - A buffer layer formed of In03-04-2010
20100051960DEVICE AND PROCESS OF FORMING DEVICE WITH PRE-PATTERNED TRENCH AND GRAPHENE-BASED DEVICE STRUCTURE FORMED THEREIN - A graphene-based device is formed with a trench in one or more layers of material, a graphene layer within the trench, and a device structure on the graphene layer and within the trench. Fabrication techniques includes forming a trench defined by one or more layers of material, forming a graphene layer within the trench, and forming a device structure on the graphene layer and within the trench.03-04-2010
20120313106Enhancement Mode Group III-V High Electron Mobility Transistor (HEMT) and Method for Fabrication - According to one disclosed embodiment, an enhancement mode high electron mobility transistor (HEMT) comprises a heterojunction including a group III-V barrier layer situated over a group III-V semiconductor body, and a gate structure formed over the group III-V barrier layer and including a P type group III-V gate layer. The P type group III-V gate layer prevents a two dimensional electron gas (2DEG) from being formed under the gate structure. One embodiment of a method for fabricating such an enhancement mode HEMT comprises providing a substrate, forming a group III-V semiconductor body over the substrate, forming a group III-V barrier layer over the group III-V semiconductor body, and forming a gate structure including the P type group III-V gate layer over the group III-V barrier layer.12-13-2012
20120175633NITRIDE SEMICONDUCTOR SUBSTRATE - A nitride semiconductor substrate is featured in comprising: a GaN semiconductor layer grown on a base layer, which has a substantially triangular cross-section along the thickness direction thereof, a periodic stripe shapes, and uneven surfaces arranged on the stripes inclined surfaces; and an overgrown layer composed of AlGaN or InAlGaN on the GaN semiconductor layer.07-12-2012
20120175632LIGHT EMITTING DEVICE - The light emitting device, and corresponding method of manufacture, the light emitting device including a second electrode layer; a second conductive type semiconductor layer formed on the second electrode layer; an active layer formed on the second conductive type semiconductor layer; a first conductive type semiconductor layer formed with a first photonic crystal that includes a mask layer and an air gap formed on the active layer; and a first electrode layer formed on the first conductive type semiconductor layer.07-12-2012
20120175630LIGHT EMITTING DIODES AND METHOD FOR MANUFACTURING THE SAME - An LED comprises an electrode layer comprising a first a second sections electrically insulated from each other; an electrically conductive layer on the second section, an electrically conductive pole protruding from the electrically conductive layer; an LED die comprising an electrically insulating substrate on the electrically conductive layer, and a P-N junction on the electrically insulating substrate, the P-N junction comprising a first electrode and a second electrode, the electrically conductive pole extending through the electrically insulating substrate to electrically connect the first electrode to the second section; a transparent electrically conducting layer on the LED die, the transparent electrically conducting layer electrically connecting the second electrode to the first section; and an electrically insulating layer between the LED die, the electrically conductive layer, and the transparent electrically conducting layer, wherein the electrically insulating layer insulates the transparent electrically conducting layer from the electrically conductive layer and the second section.07-12-2012
20120175628LIGHT EMITTING DIODES AND METHOD FOR MANUFACTURING THE SAME - An exemplary LED includes an electrode layer, an LED die, a transparent electrically conductive layer, and an electrically insulating layer. The electrode layer includes a first section and a second section electrically insulated from the first section. The LED die is arranged on and electrically connected to the second section of the electrode layer. The transparent electrically conductive layer is formed on the LED die and electrically connects the LED die to the first section of the electrode layer. The electrically insulating layer is located between the LED die and the transparent electrically conductive layer to insulate the transparent electrically conductive layer from the second section of the electrode layer.07-12-2012
20120256190Stacked Composite Device Including a Group III-V Transistor and a Group IV Diode - In one implementation, a stacked composite device comprises a group IV diode and a group III-V transistor stacked over the group IV diode. A cathode of the group IV diode is in contact with a source of the group III-V transistor, an anode of the group IV diode is coupled to a gate of the group III-V transistor to provide a composite anode on a bottom side of the stacked composite device, and a drain of the group III-V transistor provides a composite cathode on a top side of the stacked composite device.10-11-2012
20120256189Stacked Composite Device Including a Group III-V Transistor and a Group IV Vertical Transistor - In one implementation, a stacked composite device comprises a group IV vertical transistor and a group III-V transistor stacked over the group IV vertical transistor. A drain of the group IV vertical transistor is in contact with a source of the group III-V transistor, a source of the group IV vertical transistor is coupled to a gate of the group III-V transistor to provide a composite source on a bottom side of the stacked composite device, and a drain of the group III-V transistor provides a composite drain on a top side of the stacked composite device. A gate of the group IV vertical transistor provides a composite gate on the top side of the stacked composite device.10-11-2012
20120175631ENHANCEMENT MODE GaN HEMT DEVICE WITH GATE SPACER AND METHOD FOR FABRICATING THE SAME - Enhancement-mode GaN devices having a gate spacer, a gate metal material and a gate compound that are self-aligned, and a methods of forming the same. The materials are patterned and etched using a single photo mask, which reduces manufacturing costs. An interface of the gate spacer and the gate compound has lower leakage than the interface of a dielectric film and the gate compound, thereby reducing gate leakage. In addition, an ohmic contact metal layer is used as a field plate to relieve the electric field at a doped III-V gate compound corner towards the drain contact, which leads to lower gate leakage current and improved gate reliability.07-12-2012
20120313108SEMICONDUCTOR DIODE - To provide a semiconductor diode with a part of a semiconductor lamination portion having a mesa structure portion, which is the part where a pn-junction is formed by lamination of an n-type semiconductor layer and a p-type semiconductor layer on a substrate, comprising: a protective insulating film formed by coating a main surface of the mesa structure portion, a side face of the mesa structure portion in which an interface of the pn-junction is exposed, and an etched and exposed surface of the n-type semiconductor layer; and an anode electrode formed in ohmic-contact with the p-type semiconductor layer exposed from an opening formed on a part of the main surface of the mesa structure portion of the protective insulating film, extending from the main surface, through the side face of the mesa structure portion, to the surface of the n-type semiconductor layer.12-13-2012
20100270560SYSTEM AND METHOD FOR EMITTER LAYER SHAPING - Embodiments of an LED disclosed has an emitter layer shaped to a controlled depth or height relative to a substrate of the LED to maximize the light output of the LED and to achieve a desired intensity distribution. In some embodiments, the exit face of the LED may be selected to conserve radiance. In some embodiments, shaping the entire LED, including the substrate and sidewalls, or shaping the substrate alone can extract 100% or approximately 100% of the light generated at the emitter layers from the emitter layers. In some embodiments, the total efficiency is at least 90% or above. In some embodiments, the emitter layer can be shaped by etching, mechanical shaping, or a combination of various shaping methods. In some embodiments, only a portion of the emitter layer is shaped to form the tiny emitters. The unshaped portion forms a continuous electrical connection for the LED.10-28-2010
20100270559FIELD EFFECT TRANSISTOR AND PROCESS FOR MANUFACTURING SAME - A field effect transistor includes: a channel layer 10-28-2010
20120217510LIGHT-EMITTING SEMICONDUCTOR DEVICE USING GROUP III NITROGEN COMPOUND - A method of producing a light-emitting semiconductor device of a group III nitride compound includes forming a high carrier concentration N08-30-2012
20120217505SEMICONDUCTOR DEVICE - A semiconductor device including a field effect transistor having a buffer layer subjected to lattice relaxation, a channel layer, and an electron supply layer formed in this order with group-III nitride semiconductors respectively in a growth mode parallel with a [0001] or [000-1] crystallographic axis over a substrate and having a source electrode and a drain electrode, those being coupled electrically to the channel layer, and a gate electrode formed over the electron supply layer, in which, in the buffer layer and the electron supply layer, a layer existing on the group-III atomic plane side of the channel layer has an A-axis length larger than a layer existing on the group-V atomic plane side of the channel layer; and the electron supply layer has a bandgap larger than the channel layer.08-30-2012
20120074427METHOD FOR MANUFACTURING A LAYER OF GALLIUM NITRIDE OR GALLIUM AND ALUMINUM NITRIDE - The present invention relates to a crack-free monocrystalline nitride layer having the composition AlxGa03-29-2012
20120074425GROWTH OF REDUCED DISLOCATION DENSITY NON-POLAR GALLIUM NITRIDE - Lateral epitaxial overgrowth (LEO) of non-polar gallium nitride (GaN) films results in significantly reduced defect density.03-29-2012
20120074424GALLIUM NITRIDE BASED SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - Gallium nitride (GaN) based semiconductor devices and methods of manufacturing the same. The GaN-based semiconductor device may include a conductive heat dissipation substrate (that is, a thermal conductive substrate); an GaN-based multi-layer arranged on the heat dissipation substrate; and a Schottky electrode arranged on the GaN-based multi-layer. While such a GaN-based semiconductor device is being manufactured, a wafer bonding process and a laser lift-off process may be used.03-29-2012
20120248458VERTICALLY STRUCTURED GROUP III NITRIDE SEMICONDUCTOR LED CHIP AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing vertically structured Group III nitride semiconductor LED chips includes a step of forming a light emitting laminate on a growth substrate; a step of forming a plurality of separate light emitting structures by partially removing the light emitting laminate to partially expose the growth substrate; a step of forming a conductive support on the plurality of light emitting structures; a step of lifting off the growth substrate from the plurality of light emitting structures; and a step of cutting the conductive support thereby singulating a plurality of LED chips each having the light emitting structure. The step of partially removing the light emitting laminate is performed such that each of the plurality of light emitting structures has a top view shape of a circle or a 4n-gon en” is a positive integer) having rounded corners.10-04-2012
20100006857MULTILAYER STRUCTURE AND FABRICATION THEREOF - A process for fabricating a multilayer structure is provided as well as the structure itself. In accordance with one embodiment, the process includes growing a growth layer on a silicon substrate by epitaxial growth, forming at least one pattern from the growth layer, depositing an oxide layer on the silicon substrate, transferring a silicon active layer onto the oxide layer, forming a cavity in the silicon active layer oxide layer above the pattern, and growing a III-V material in the cavity.01-14-2010
20100244044GaN-BASED FIELD EFFECT TRANSISTOR - The invention provides a GaN-based compound semiconductor device that is operable with low ON-resistance and high withstanding voltage. The GaN-based field effect transistor includes a buffer layer formed on a substrate, a channel layer, a drift layer formed on the channel layer, source and drain electrodes formed on the drift layer, an insulating film formed on the inner surface of a recess form in the drift layer and on the surface of the drift layer and a gate electrode formed on the insulating film and having a field plate portion. The drift layer has a reducing surface field region composed of n-type GaN-based compound semiconductor whose sheet carrier density is more than 5×1009-30-2010
20100244043ELECTRICAL DEVICES HAVING IMPROVED TRANSFER CHARACTERISTICS AND METHOD FOR TAILORING THE TRANSFER CHARACTERISTICS OF AN ELECTRICAL DEVICE - The invention concerns about electrical devices having improved transfer characteristics and a corresponding method of tailoring the transfer characteristics of such electrical devices. According to one aspect of the invention, there is provided an electrical device including at least two transistor segments or at least two transistors connected in parallel or in series characterized in that the at least two segments of the transistor or the at least two of the transistors have a different single transfer characteristic due to at least one of different topology and different material properties.09-30-2010
20100244042Group III nitride compound semiconductor light emitting element and manufacturing method thereof - A group III nitride compound semiconductor light emitting element comprising: a first layer which is a single crystal layer of a group III nitride compound semiconductor, the first layer formed on the buffer layer and including a threading dislocation; a second layer of a group III nitride compound semiconductor formed on the first layer, the second layer including a pit and a flat portion, wherein the pit continuing from the threading dislocations and having a cross section parallel to the substrate expanding in a growth direction of the second layer; a luminescent layer including a flat portion and a pit corresponding to those of the second layer. The indium concentration in the pit of the luminescent layer is smaller than that in the flat portion of the luminescent layer. A luminescent spectrum width of thereof is expanded as compared to a case where the pit does not exist.09-30-2010
20100244040GROUP-III NITRIDE COMPOUND SEMICONDUCTOR LIGHT-EMITTING DEVICE, METHOD OF MANUFACTURING GROUP-III NITRIDE COMPOUND SEMICONDUCTOR LIGHT-EMITTING DEVICE, AND LAMP - A group-III nitride compound semiconductor light-emitting device, a method of manufacturing the group-III nitride compound semiconductor light-emitting device, and a lamp. The method includes the steps of: forming an intermediate layer (09-30-2010
20120313110LIGHT EMITTING DEVICE - Disclosed are a light emitting device. A light emitting diode comprises a light emitting device comprises a plurality of N-type semiconductor layers including a first N-type semiconductor layer and a second N-type semiconductor layer on the first N-type semiconductor layer, an active layer on the second N-type semiconductor layer, and a P-type semiconductor layer on the active layer, wherein the first N-type semiconductor layer comprises a Si doped Nitride layer and the second N-type semiconductor layer comprises a Si doped Nitride layer, and wherein the first and second N-type semiconductor layers have a Si impurity concentration different from each other.12-13-2012
20120313105UNIPOLAR DIODE WITH LOW TURN-ON VOLTAGE - A unipolar diode with low turn-on voltage includes a subcathode semiconductor layer, a low-doped, wide bandgap cathode semiconductor layer, and a high-doped, narrow bandgap anode semiconductor layer. A junction between the cathode layer and the anode layer creates an electron barrier in the conduction band, with the barrier configured to produce a low turn-on voltage for the diode. A unipolar diode with low turn-on voltage includes an n12-13-2012
20120223326LIGHT EMITTING DIODE AND METHOD FOR FABRICATING THE SAME - A light emitting diode and a method for fabricating the same are provided. The light emitting diode includes: a transparent substrate; a semiconductor material layer formed on the top surface of a substrate with an active layer generating light; and a fluorescent layer formed on the back surface of the substrate with controlled varied thicknesses. The ratio of light whose wavelength is shifted while propagating through the fluorescent layer and the original light generated in the active layer can be controlled by adjusting the thickness of the fluorescent layer, to emit desirable homogeneous white light from the light emitting diode.09-06-2012
20100301349WAFER LEVEL LED PACKAGE STRUCTURE FOR INCREASING LIGHT-EMITTING EFFICIENCY AND HEAT-DISSIPATING EFFECT AND METHOD FOR MANUFACTURING THE SAME - A wafer level LED package structure includes a light-emitting unit, a reflecting unit, a first conductive unit and a second conductive unit. The light-emitting unit has a substrate body, a light-emitting body disposed on the substrate body, a positive and a negative conductive layers formed on the light-emitting body, and a light-emitting area formed in the light-emitting body. The reflecting unit has a reflecting layer formed between the positive and the negative conductive layers and on the substrate body for covering external sides of the light-emitting body. The first conductive unit has a first positive conductive layer formed on the positive conductive layer and a first negative conductive layer formed on the negative conductive layer. The second conductive unit has a second positive conductive structure formed on the first positive conductive layer and a second negative conductive structure formed on the first negative conductive layer.12-02-2010
20120223329 Production Method of a Layered Body - Disclosed is a novel method for group III polarity growth on a sapphire substrate. Specifically disclosed is a method for producing a laminate wherein a group III nitride single crystal layer is laminated on a sapphire substrate by an MOCVD method. The method for producing a laminate comprises: a pretreatment step in which an oxygen source gas is supplied onto the sapphire substrate; a first growth step in which an initial single crystal layer that contains oxygen at a concentration of 5×1009-06-2012
20120187415METHOD FOR CONDUCTIVITY CONTROL OF (Al,In,Ga,B)N - A method of controlled p-type conductivity in (Al,In,Ga,B)N semiconductor crystals. Examples include {10 07-26-2012
20120256191EPITAXIAL GROWTH METHOD AND DEVICES - Epitaxial growth methods and devices are described that include a textured surface on a substrate. Geometry of the textured surface provides a reduced lattice mismatch between an epitaxial material and the substrate. Devices formed by the methods described exhibit better interfacial adhesion and lower defect density than devices formed without texture. Silicon substrates are shown with gallium nitride epitaxial growth and devices such as LEDs are formed within the gallium nitride.10-11-2012
20120256187DOUBLE SUBSTRATE MULTI-JUNCTION LIGHT EMITTING DIODE ARRAY STRUCTURE - The present disclosure provides one embodiment of a light-emitting structure. The light-emitting structure includes a carrier substrate having first metal features; a transparent substrate having second metal features; a plurality of light-emitting diodes (LEDs) bonded with the carrier substrate and the transparent substrate, sandwiched between the carrier substrate and the transparent substrate; and metal pillars bonded to the carrier substrate and the transparent substrate, each of the metal pillars being disposed between adjacent two of the plurality of LEDs, wherein the first metal features, the second metal features and the metal pillars are configured to electrically connect the plurality of LEDs.10-11-2012
20120256188Stacked Composite Device Including a Group III-V Transistor and a Group IV Lateral Transistor - In one implementation, a stacked composite device comprises a group IV lateral transistor and a group III-V transistor stacked over the group IV lateral transistor. A drain of the group IV lateral transistor is in contact with a source of the group III-V transistor, a source of the group IV lateral transistor is coupled to a gate of the group III-V transistor to provide a composite source on a top side of the stacked composite device, and a drain of the group III-V transistor provides a composite drain on the top side of the stacked composite device. A gate of the group IV lateral transistor provides a composite gate on the top side of the stacked composite device, and a substrate of the group IV lateral transistor is on a bottom side of the stacked composite device.10-11-2012
20120187413NITRIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a nitride semiconductor device includes a first semiconductor, a second semiconductor layer, a third semiconductor layer, a fourth semiconductor layer, a first electrode, a second electrode and a third electrode. The first, second and fourth semiconductor layers include a nitride semiconductor. The second semiconductor layer is provided on the first semiconductor layer, has a band gap not less than that of the first semiconductor layer. The third semiconductor layer is provided on the second semiconductor layer. The third semiconductor layer is GaN. The fourth semiconductor layer is provided on the third semiconductor layer to have an interspace on a part of the third semiconductor layer, has a band gap not less than that of the second semiconductor layer. The first electrode is provided on a portion of the third semiconductor layer. The fourth semiconductor layer is not provided on the portion.07-26-2012
20120187414SEMICONDUCTOR LIGHT-EMITTING DEVICE AND PROCESS FOR PRODUCTION THEREOF - One aspect of the present invention provides a semiconductor light-emitting device improved in luminance, and also provides a process for production thereof. The process comprises a procedure of forming a relief structure on the light-extraction surface of the device by use of a self-assembled film. In that procedure, the light-extraction surface is partly covered with a protective film so as to protect an area for an electrode to be formed therein. The electrode is then finally formed there after the procedure. The process thus reduces the area incapable, due to thickness of the electrode, of being provided with the relief structure. Between the electrode and the light-extraction surface, a contact layer is formed so as to establish ohmic contact between them.07-26-2012
20120228627METHOD FOR PRODUCING COMPOUND SEMICONDUCTOR CRYSTAL, METHOD FOR PRODUCING ELECTRONIC DEVICE, AND SEMICONDUCTOR WAFER - A method for producing a compound semiconductor crystal, includes; a sacrificial layer formation step of forming a sacrificial layer containing C09-13-2012
20120228625NITRIDE SEMICONDUCTOR DEVICE - According to one embodiment, a nitride semiconductor device includes a first, a second, a third and a fourth transistor of n-type channel and a resistor. The first transistor has a first gate, a first source, and a first drain. The second transistor has a second gate, a second source electrically connected to the first gate, and a second drain. The third transistor has a third gate, a third source electrically connected to the first source, and a third drain electrically connected to the first gate and the second source. The fourth transistor has a fourth gate electrically connected to the third gate, a fourth source electrically connected to the first source and the third source, and a fourth drain electrically connected to the second gate. The resistor has one end electrically connected to the second drain and one other end electrically connected to the second gate and the fourth drain.09-13-2012
20110121314ENHANCEMENT MODE GALLIUM NITRIDE POWER DEVICES - Enhancement mode III-nitride devices are described. The 2DEG is depleted in the gate region so that the device is unable to conduct current when no bias is applied at the gate. Both gallium face and nitride face devices formed as enhancement mode devices.05-26-2011
20110121313Enhancement Mode III-Nitride Transistors with Single Gate Dielectric Structure - According to one embodiment, a III-nitride transistor includes a conduction channel formed between first and second III-nitride bodies, the conduction channel including a two-dimensional electron gas. The transistor also includes at least one gate dielectric layer having a charge confined within to cause an interrupted region of the conduction channel and a gate electrode operable to restore the interrupted region of the conduction channel. The transistor can be an enhancement mode transistor. In one embodiment, the gate dielectric layer is a silicon nitride layer. In another embodiment, the at least one gate dielectric layer is a silicon oxide layer. The charge can be ion implanted into the at least one gate dielectric layer. The at least one gate dielectric layer can also be grown with the charge.05-26-2011
20110121311METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, SEMICONDUCTOR SUBSTRATE, AND SEMICONDUCTOR DEVICE - The present invention provides a method for manufacturing a semiconductor substrate including a low-resistance nitride layer laminated on a substrate, a method for manufacturing a semiconductor device, a semiconductor substrate, and a semiconductor device. A method for manufacturing a semiconductor substrate of the present invention includes the following steps: A nitride substrate having a principal surface and a back surface opposite to the principal surface is prepared. Vapor-phase ions are implanted into the back surface of the nitride substrate. The back surface of the nitride substrate is bonded to a dissimilar substrate to form a bonded substrate. The nitride substrate is partially separated from the bonded substrate to form a laminated substrate including the dissimilar substrate and a nitride layer. The laminated substrate is heat-treated at a temperature over 700° C.05-26-2011
20110121312OPTICAL SEMICONDUCTOR DEVICE HAVING UNEVEN SEMICONDUCTOR LAYER WITH NON-UNIFORM CARRIER DENSITY - In an optical semiconductor device including a first semiconductor layer of a first conductivity type, an active layer provided on the first semiconductor layer, a second semiconductor layer of a second conductivity type provided on the active layer, an insulating layer provided on a part of the second semiconductor layer, an uneven semiconductor layer of the second conductivity type provided on another part of the second semiconductor layer, and an electrode layer provided on the insulating layer and the uneven semiconductor layer, a density of carriers of the second conductivity type being larger at a tip portion of the uneven semiconductor layer than at a bottom portion of the uneven semiconductor layer.05-26-2011
20110121310SOLID STATE LIGHTING DEVICES WITH SELECTED THERMAL EXPANSION AND/OR SURFACE CHARACTERISTICS, AND ASSOCIATED METHODS - Solid state lighting devices with selected thermal expansion and/or surface characteristics, and associated methods are disclosed. A method in accordance with a particular embodiment includes forming an SSL (solid state lighting) formation structure having a formation structure coefficient of thermal expansion (CTE), selecting a first material of an interlayer structure to have a first material CTE greater than the substrate CTE, and selecting a second material of the interlayer structure based at least in part on the second material having a second material CTE less than the first material CTE. The method can further include forming the interlayer structure over the SSL formation structure by disposing (at least) a first layer of the first material over the SSL formation structure, a portion of the second material over the first material, and a second layer of the first material over the second material. The SSL formation structure supports an SSL emitter material, and the method further includes counteracting a force placed on the formation structure by the first material, by virtue of the difference between the second material CTE and the first material CTE. In other embodiments, the SSL formation structure can have an off-cut angle with a non-zero value of up to about 4.5 degrees.05-26-2011
20080296585GROWTH METHOD OF GaN CRYSTAL, AND GaN CRYSTAL SUBSTRATE - A method of producing a GaN crystal is directed to growing a GaN crystal on a GaN seed crystal substrate. The method includes the steps of preparing a GaN seed crystal substrate including a first dopant such that the thermal expansion coefficient of the GaN seed crystal substrate becomes greater than that of the GaN crystal, and growing the GaN crystal to a thickness of at least 1 mm on the GaN seed crystal substrate. Accordingly, there can be provided a method of producing a GaN crystal that can suppress generation of a crack and grow a thick GaN crystal, and a GaN crystal substrate.12-04-2008
20120235159Group III Nitride Field Effect Transistors (FETS) Capable of Withstanding High Temperature Reverse Bias Test Conditions - Group III Nitride based field effect transistor (FETs) are provided having a power degradation of less than about 3.0 dB when operated at a drain-to-source voltage (V09-20-2012
20120319130LIGHT EMITTING DEVICE AND METHOD OF FABRICATING THE SAME - Provided are a light emitting device and a method of fabricating the same. The light emitting device comprises: a first conductive semiconductor layer; an active layer comprising an InGaN well layer and a GaN barrier layer on the first conductive semiconductor layer; and a second conductive semiconductor layer on the active layer. The GaN barrier layer comprises an AlGaN layer.12-20-2012
20120319131METHODS OF GROWING NITRIDE SEMICONDUCTORS AND METHODS OF MANUFACTURING NITRIDE SEMICONDUCTOR SUBSTRATES - Methods of growing nitride semiconductor layers including forming nitride semiconductor dots on a substrate and growing a nitride semiconductor layer on the nitride semiconductor dots. The nitride semiconductor layer may be separated from the substrate to be used as a nitride semiconductor substrate.12-20-2012
20110037075PROCESS FOR FABRICATING A STRUCTURE FOR EPITAXY WITHOUT AN EXCLUSION ZONE - A process for fabricating a composite structure for epitaxy, including at least one crystalline growth seed layer of semiconductor material on a support substrate, with the support substrate and the crystalline growth seed layer each having, on the periphery of their bonding face, a chamfer or an edge rounding zone. The process includes at least one step of wafer bonding the crystalline growth seed layer directly onto the support substrate and at least one step of thinning the crystalline growth seed layer. After thinning, the crystalline growth seed layer has a diameter identical to its initial diameter.02-17-2011
20120299012Gallium Nitride for Liquid Crystal Electrodes - Described herein is a liquid crystal (LC) device having Gallium Nitride HEMT electrodes. The Gallium Nitride HEMT electrodes can be grown on a variety of substrates, including but not limited to sapphire, silicon carbide, silicon, fused silica (using a calcium flouride buffer layer), and spinel. Also described is a structure provided from GaN HEMT grown on large area silicon substrates and transferred to another substrate with appropriate properties for OPA devices. Such substrates include, but are not limited to sapphire, silicon carbide, silicon, fused silica (using a calcium fluoride buffer layer), and spinel. The GaN HEMT structure includes an AlN interlayer for improving the mobility of the structure.11-29-2012
20120299011FIELD-EFFECT TRANSISTOR AND METHOD FOR FABRICATING THE SAME - An AlN buffer layer, an undoped GaN layer, an undoped AlGaN layer, a p-type GaN layer and a heavily doped p-type GaN layer are formed in this order. A gate electrode forms an Ohmic contact with the heavily doped p-type GaN layer. A source electrode and a drain electrode are provided on the undoped AlGaN layer. A pn junction is formed in a gate region by a two dimensional electron gas generated at an interface between the undoped AlGaN layer and the undoped GaN layer and the p-type GaN layer, so that a gate voltage can be increased.11-29-2012
20120299010GROUP-III NITRIDE SEMICONDUCTOR DEVICE, EPITAXIAL SUBSTRATE, AND METHOD OF FABRICATING GROUP-III NITRIDE SEMICONDUCTOR DEVICE - A III-nitride semiconductor device has a support base comprised of a III-nitride semiconductor and having a primary surface extending along a first reference plane perpendicular to a reference axis inclined at a predetermined angle with respect to a c-axis of the III-nitride semiconductor, and an epitaxial semiconductor region provided on the primary surface of the support base. The epitaxial semiconductor region includes GaN-based semiconductor layers. The reference axis is inclined at a first angle from the c-axis of the III-nitride semiconductor toward a first crystal axis, either the m-axis or a-axis. The reference axis is inclined at a second angle from the c-axis of the III-nitride semiconductor toward a second crystal axis, the other of the m-axis and a-axis. Morphology of an outermost surface of the epitaxial semiconductor region includes a plurality of pits. A pit density of the pits is not more than 5×1011-29-2012
20120267640SEMICONDUCTOR HETEROSTRUCTURE DIODES - Planar Schottky diodes for which the semiconductor material includes a heterojunction which induces a 2DEG in at least one of the semiconductor layers. A metal anode contact is on top of the upper semiconductor layer and forms a Schottky contact with that layer. A metal cathode contact is connected to the 2DEG, forming an ohmic contact with the layer containing the 2DEG.10-25-2012
20120267638GaN FILM STRUCTURE, METHOD OF FABRICATING THE SAME, AND SEMICONDUCTOR DEVICE INCLUDING THE SAME - A method of fabricating a gallium nitride (GaN) thin layer structure includes forming a sacrificial layer on a substrate, forming a first buffer layer on the sacrificial layer, forming an electrode layer on the first buffer layer, forming a second buffer layer on the electrode layer, partially etching the sacrificial layer to form at least two support members configured to support the first buffer layer and define at least one air cavity between the substrate and the first buffer layer, and forming a GaN thin layer on the second buffer layer.10-25-2012
20120267639NITRIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - Disclosed herein are a nitride semiconductor device and a method for manufacturing the same. According to an exemplary embodiment, there is provided a nitride semiconductor device, including: a nitride semiconductor layer having a 2DEG channel; a drain electrode ohmic-contacted with the nitride semiconductor layer; a source electrode Schottky-contacted with the nitride semiconductor layer, including a plurality of patterned protrusion portions protruded to the drain electrode direction, and including an ohmic pattern ohmic-contacted with the nitride semiconductor layer therein; a dielectric layer disposed on the nitride semiconductor layer between the drain electrode and the source electrode and over at least a portion of the source electrode including the patterned protrusion portions; and a gate electrode disposed on the dielectric, wherein a portion of the gate electrode is disposed on the dielectric layer over the patterned protrusion portions and a drain direction edge portion of the source electrode.10-25-2012
20120267636Lateral High Electron Mobility Transistor - A lateral HEMT includes a substrate, a first semiconductor layer above the substrate and a second semiconductor layer on the first semiconductor layer. The lateral HEMT further includes a gate electrode, a source electrode, a drain electrode and a rectifying Schottky junction. A first terminal of the rectifying Schottky junction is electrically coupled to the source electrode and a second terminal of the rectifying Schottky junction is electrically coupled to the second semiconductor layer.10-25-2012
20120267637Nitride semiconductor device and manufacturing method thereof - Provided is a nitride semiconductor device including: a nitride semiconductor layer over a substrate wherein the nitride semiconductor has a two-dimensional electron gas (2DEG) channel inside; a drain electrode in ohmic contact with the nitride semiconductor layer; a source electrode in Schottky contact with the nitride semiconductor layer wherein the source electrode is spaced apart from the drain electrode; a floating guard ring in Schottky contact with the nitride semiconductor layer between the drain electrode and the source electrode; a dielectric layer formed on the nitride semiconductor layer between the drain electrode and the source electrode and on at least a portion of the source electrode wherein the dielectric layer is applied to the floating guard ring between the drain electrode and the source electrode; and a gate electrode formed on the dielectric layer to be spaced apart from the drain electrode, wherein a portion of the gate electrode is formed over a drain-side edge portion of the source electrode with the dielectric layer interposed therebetween, and a manufacturing method thereof.10-25-2012
20120319129SUBSTRATE, EPITAXIAL LAYER PROVIDED SUBSTRATE, METHOD FOR PRODUCING SUBSTRATE, AND METHOD FOR PRODUCING EPITAXIAL LAYER PROVIDED SUBSTRATE - The present invention provides a substrate formed at a low cost and having a controlled plate shape, an epitaxial layer provided substrate obtained by forming an epitaxial layer on the substrate, and methods for producing them. The method for producing the substrate according to the present invention includes an ingot growing step (S12-20-2012
20120319128SEMICONDUCTOR STRUCTURES, DEVICES AND ENGINEERED SUBSTRATES INCLUDING LAYERS OF SEMICONDUCTOR MATERIAL HAVING REDUCED LATTICE STRAIN - Methods of fabricating semiconductor devices or structures include forming structures of a semiconductor material overlying a layer of a compliant material, subsequently changing the viscosity of the compliant material to relax the semiconductor material structures, and utilizing the relaxed semiconductor material structures as a seed layer in forming a continuous layer of relaxed semiconductor material. In some embodiments, the layer of semiconductor material may comprise a III-V type semiconductor material, such as, for example, indium gallium nitride. Novel intermediate structures are formed during such methods. Engineered substrates include a continuous layer of semiconductor material having a relaxed lattice structure.12-20-2012
20120319126Optoelectronic Semiconductor Chip and Method for Fabrication Thereof - An optoelectronic semiconductor chip has a first semiconductor layer sequence which comprises a multiplicity of microdiodes, and a second semiconductor layer sequence which comprises an active region the first semiconductor layer sequence and the second semiconductor layer sequence are based on a nitride compound semiconductor material, the first semiconductor layer sequence is before the first semiconductor layer sequence in the direction of growth, and the microdiodes form an ESD protection for the active region.12-20-2012
20120319127CURRENT APERTURE VERTICAL ELECTRON TRANSISTORS WITH AMMONIA MOLECULAR BEAM EPITAXY GROWN P-TYPE GALLIUM NITRIDE AS A CURRENT BLOCKING LAYER - A current aperture vertical electron transistor (CAVET) with ammonia (NH12-20-2012
20120319125SILICON CARBIDE SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - A first single crystal substrate has a first side surface and it is composed of silicon carbide. A second single crystal substrate has a second side surface opposed to the first side surface and it is composed of silicon carbide. A bonding portion connects the first and second side surfaces to each other between the first and second side surfaces. At least a part of the bonding portion is made of particles composed of silicon carbide and having a maximum length not greater than 1 μm.12-20-2012
20110042681N-SIDE ELECTRODE, NITRIDE SEMICONDUCTOR LIGHT-EMITTING ELEMENT, AND METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR LIGHT-EMITTING ELEMENT - An n-side electrode that can inhibit the reduction in ohmic properties is provided. The n-side electrode is an n-side electrode for a nitride semiconductor light-emitting element, and includes an Al layer forming an ohmic contact to an n-type nitride semiconductor layer and having a thickness of 30 nm or greater.02-24-2011
20110227093FIELD EFFECT TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - The present invention has an object to provide an FET and a method of manufacturing the FET that are capable of increasing the threshold voltage as well as decreasing the on-resistance. The FET of the present invention includes a first undoped GaN layer; a first undoped AlGaN layer formed on the first undoped GaN layer, having a band gap energy greater than that of the first undoped GaN layer; a second undoped GaN layer formed on the first undoped AlGaN layer; a second undoped AlGaN layer formed on the second undoped GaN layer, having a band gap energy greater than that of the second undoped GaN layer; a p-type GaN layer formed in the recess of the second undoped AlGaN layer; a gate electrode formed on the p-type GaN layer; and a source electrode and a drain electrode which are formed in both lateral regions of the gate electrode, wherein a channel is formed at the heterojunction interface between the first undoped GaN layer and the first undoped AlGaN layer.09-22-2011
20110227092III-Nitride Semiconductor Device - A III-nitride heterojunction power semiconductor device having a barrier layer that includes a region of reduced nitrogen content.09-22-2011
20120273796HIGH INDIUM UPTAKE AND HIGH POLARIZATION RATIO FOR GROUP-III NITRIDE OPTOELECTRONIC DEVICES FABRICATED ON A SEMIPOLAR (20-2-1) PLANE OF A GALLIUM NITRIDE SUBSTRATE - A Group-III nitride optoelectronic device fabricated on a semipolar (20-2-1) plane of a Gallium Nitride (GaN) substrate is characterized by a high Indium uptake and a high polarization ratio.11-01-2012
20120273794SEMICONDUCTOR LIGHT EMITTING DEVICE, WAFER, AND METHOD FOR MANUFACTURING SEMICONDUCTOR LIGHT EMITTING DEVICE - According to one embodiment, a semiconductor light emitting device includes a first semiconductor layer, an active layer, and a second semiconductor layer. The first layer has a first upper surface and a first side surface. The active layer has a first portion covering the first upper surface and having a second upper surface, and a second portion covering the first side surface and having a second side surface. The second layer has a third portion covering the second upper surface, and a fourth portion covering the second side surface. The first and second layers include a nitride semiconductor. The first portion along a stacking direction has a thickness thicker than the second portion along a direction from the first side surface toward the second side surface. The third portion along the stacking direction has a thickness thicker than the fourth portion along the direction.11-01-2012
20120273797SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - There are provided a semiconductor device that includes a bypass protection unit against surge voltage or the like, achieves good withstand voltage characteristics and low on-resistance (low On-state voltage), has a simple structure, and is used for large-current purpose and a method for producing the semiconductor device.11-01-2012
20120080688ULTRA-THIN OHMIC CONTACTS FOR P-TYPE NITRIDE LIGHT EMITTING DEVICES - A flip-chip semiconductor based Light Emitting Device (LED) can include an n-type semiconductor substrate and an n-type GaN epi-layer on the substrate. A p-type GaN epi-layer can be on the n-type GaN epi-layer and a metal ohmic contact p-electrode can be on the p-type GaN epi-layer, where the metal ohmic contact p-electrode can have an average thickness less than about 25 Å. A reflector can be on the metal ohmic contact p-electrode and a metal stack can be on the reflector. An n-electrode can be on the substrate opposite the n-type GaN epi-layer and a bonding pad can be on the n-electrode.04-05-2012
20120080687NITRIDE SEMICONDUCTOR DEVICE - A nitride semiconductor device of an embodiment includes: a nitride semiconductor device, including: a nitride semiconductor substrate; a first anode electrode formed on the substrate; a recess structure formed on the substrate of an outer peripheral portion of the first anode electrode by engraving the substrate; a second anode electrode formed so as to cover the first anode electrode and so as to be embedded in the recess structure; and a cathode electrode formed on the substrate.04-05-2012
20120080686Semiconductor Devices and Methods of Manufacturing Thereof - In one embodiment, a method of forming a semiconductor device includes forming a first porous semiconductor layer over a top surface of a substrate. A first epitaxial layer is formed over the first porous semiconductor layer. A circuitry is formed within and over the first epitaxial layer. The circuitry is formed without completely oxidizing the first epitaxial layer.04-05-2012
20110266551HIGH BRIGHTNESS LIGHT EMITTING DIODE COVERED BY ZINC OXIDE LAYERS ON MULTIPLE SURFACES GROWN IN LOW TEMPERATURE AQUEOUS SOLUTION - A high brightness III-Nitride based Light Emitting Diode (LED), comprising multiple surfaces covered by Zinc Oxide (ZnO) layers, wherein the ZnO layers are grown in a low temperature aqueous solution and each have a (0001) c-orientation and a top surface that is a (0001) plane.11-03-2011
20120326159LED STRUCTURE WITH ENHANCED MIRROR REFLECTIVITY - Embodiments of the present invention are generally related to LED chips having improved overall emission by reducing the light-absorbing effects of barrier layers adjacent mirror contacts. In one embodiment, a LED chip comprises one or more LEDs, with each LED having an active region, a first contact under the active region having a highly reflective mirror, and a barrier layer adjacent the mirror. The barrier layer is smaller than the mirror such that it does not extend beyond the periphery of the mirror. In another possible embodiment, an insulator is further provided, with the insulator adjacent the barrier layer and adjacent portions of the mirror not contacted by the active region or by the barrier layer. In yet another embodiment, a second contact is provided on the active region. In a further embodiment, the barrier layer is smaller than the mirror such that the periphery of the mirror is at least 40% free of the barrier layer, and the second contact is below the first contact and accessible from the bottom of the chip.12-27-2012
20100230687III NITRIDE ELECTRONIC DEVICE AND III NITRIDE SEMICONDUCTOR EPITAXIAL SUBSTRATE - In a group III nitride hetero junction transistor 09-16-2010
20100230686LIGHT EMITTING DEVICE - Disclosed are a light emitting device and a method of manufacturing the same. The light emitting device includes a plurality of compound semiconductor layers that includes a first conductive semiconductor layer, an active layer under the first conductive semiconductor layer, and a second conductive semiconductor layer under the active layer. An electrode is formed on the compound semiconductor layers. A groove is formed at an upper portion of the compound semiconductor layers. An electrode layer is formed under the compound semiconductor layers.09-16-2010
20100230684SEMICONDUCTOR DEVICE - A semiconductor device includes a channel layer, an electron-supplying layer provided on the channel layer, a cap layer provided on the electron-supplying layer and creating lattice match with the channel layer, and ohmic electrodes provided on the cap layer. The cap layer has a composition of (In09-16-2010
20120280247High Voltage Cascoded III-Nitride Rectifier Package Utilizing Clips on Package Support Surface - Some exemplary embodiments of high voltage cascoded III-nitride semiconductor package utilizing clips on a package support surface have been disclosed. One exemplary embodiment comprises a III-nitride transistor attached to a package support surface and having an anode of a diode stacked over a source of the III-nitride transistor, a first conductive clip coupled to a gate of the III-nitride transistor and the anode of the diode, and a second conductive clip coupled to a drain of the III-nitride transistor. The conductive clips are connected to the package support surface and expose respective flat portions that are surface mountable. In this manner, reduced package footprint, improved surge current capability, and higher performance may be achieved compared to conventional wire bonded packages. Furthermore, since a low cost printed circuit board (PCB) may be utilized for the package support surface, expensive leadless fabrication processes may be avoided for cost effective manufacturing.11-08-2012
20120280246High Voltage Cascoded III-Nitride Rectifier Package with Etched Leadframe - Some exemplary embodiments of high voltage cascaded III-nitride semiconductor package with an etched leadframe have been disclosed. One exemplary embodiment comprises a III-nitride transistor having an anode of a diode stacked over a source of the III-nitride transistor, and a leadframe that is etched to form a first leadframe paddle portion coupled to a gate of the III-nitride transistor and the anode of the diode, and a second leadframe paddle portion coupled to a drain of the III-nitride transistor. The leadframe paddle portions enable the package to be surface mountable. In this manner, reduced package footprint, improved surge current capability, and higher performance may be achieved compared to conventional wire bonded packages. Furthermore, since multiple packages may be assembled at a time, high integration and cost savings may be achieved compared to conventional methods requiring individual package processing and externally sourced parts.11-08-2012
20120280243SEMICONDUCTOR SUBSTRATE AND FABRICATING METHOD THEREOF - A fabricating method of a semiconductor substrate is provided. A patterned mask layer is formed on a substrate base. The patterned mask layer includes a plurality of apertures, and each aperture exposes a portion of the substrate base. A plurality of nano-pillars is formed on the substrate base, wherein each nano-pillar is grown on the portion of the substrate base exposed by each aperture. An insulating layer is formed on a sidewall of each nano-pillar. An epitaxial lateral overgrowth process is performed on a top portion of each nano-pillar, so as to form a semiconductor layer on the nano-pillars, wherein the semiconductor layer is exposed by a plurality of gaps disposed between the nano-pillars.11-08-2012
20120280245High Voltage Cascoded III-Nitride Rectifier Package with Stamped Leadframe - Some exemplary embodiments of high voltage cascoded III-nitride semiconductor package with a stamped leadframe have been disclosed. One exemplary embodiment comprises a III-nitride transistor having an anode of a diode stacked atop a source of the III-nitride transistor, and a stamped leadframe comprising a first bent lead coupled to a gate of the III-nitride transistor and the anode of the diode, and a second bent lead coupled to a drain of the III-nitride transistor. The bent leads expose respective flat portions that are surface mountable. In this manner, reduced package footprint, improved surge current capability, and higher performance may be achieved compared to conventional wire bonded packages. Furthermore, since multiple packages may be assembled at a time, high integration and cost savings may be achieved compared to conventional methods requiring individual package processing and externally sourced parts.11-08-2012
20120280249METHODS FOR IMPROVING THE QUALITY OF STRUCTURES COMPRISING SEMICONDUCTOR MATERIALS - Methods which can be applied during the epitaxial growth of semiconductor structures and layers of III-nitride materials so that the qualities of successive layers are successively improved. An intermediate epitaxial layer is grown on an initial surface so that growth pits form at surface dislocations present in the initial surface. A following layer is then grown on the intermediate layer according to the known phenomena of epitaxial lateral overgrowth so it extends laterally and encloses at least the agglomerations of intersecting growth pits. Preferably, prior to growing the following layer, a discontinuous film of a dielectric material is deposited so that the dielectric material deposits discontinuously so as to reduce the number of dislocations in the laterally growing material. The methods of the invention can be performed multiple times to the same structure. Also, semiconductor structures fabricated by these methods.11-08-2012
20110278586BIPOLAR TRANSISTOR - A bipolar transistor is provided with an emitter layer, a base layer and a collector layer. The emitter layer is formed above a substrate and is an n-type conductive layer including a first nitride semiconductor. The base layer is formed on the emitter layer and is a p-type conductive including a second nitride semiconductor. The collector layer is formed on the base layer and includes a third nitride semiconductor. The collector layer, the base layer and the emitter layer are formed such that a crystal growth direction to the substrate surface is parallel to a substrate direction of [000-1]. The third nitride semiconductor contains In11-17-2011
20110297955Semiconductor Light Emitting Diode - A highly-efficient semiconductor light emitting diode with improved light extraction efficiency comprising at least a substrate having a plurality of crystal planes, a first conductivity-type barrier layer, an active layer serving as a light emitting layer and a second conductivity-type barrier layer stacked on the substrate. The semiconductor light emitting diode comprises a ridge structure configured from one flat surface and at least two inclining surfaces in the in-plane direction. The width (W) of the flat surface of the ridge structure is 2λ (λ: light emission wavelength) or less. The active layer is positioned in the laminating direction so that the shortest length (L) between two points is λ (light emission wavelength) or less, wherewith the first point is the shortest point where the light emitted from the center (C) of the active layer begins total internal reflection at the interface between the inclining surfaces of the ridge structure and air, and the second point is a point where the flat surface begins.12-08-2011
20090315038COMPOUND SEMICONDUCTOR ELEMENT RESISTIBLE TO HIGH VOLTAGE - A compound semiconductor element is provided which electrically connects an electrode 12-24-2009
20120326161NITRIDE SEMICONDUCTOR ELEMENT AND MANUFACTURING METHOD THEREFOR - An exemplary nitride-based semiconductor device includes: a semiconductor multilayer structure 12-27-2012
20120091467IN-SITU DEFECT REDUCTION TECHNIQUES FOR NONPOLAR AND SEMIPOLAR (Al, Ga, In)N - A method for growing reduced defect density planar gallium nitride (GaN) films is disclosed. The method includes the steps of (a) growing at least one silicon nitride (SiN04-19-2012
20120091466Smart Integrated Semiconductor Light Emitting System Including Nitride Based Light Emitting Diodes (LED) And Application Specific Integrated Circuits (ASIC) - A light emitting diode (LED) system includes a substrate, an application specific integrated circuit (ASIC), and at least one light emitting diode (LED) that includes a Group-III nitride based material such as GaN, InGaN, AlGaN, AlInGaN or other (Ga, In or Al) N-based materials. The light emitting diode (LED) system can also include a polymer lens, and a phosphor layer on the lens or light emitting diode (LED) for producing white light. In addition, multiple light emitting diodes (LEDs) can be mounted on the substrate, and can have different colors for smart color control lighting. The substrate and the application specific integrated circuit (ASIC) are configured to provide an integrated LED circuit having smart functionality. In addition, the substrate is configured to compliment and expand the functions of the application specific integrated circuit (ASIC), and can also include built in integrated circuits for performing additional electrical functions.04-19-2012
20120091465Method of Making Bulk InGaN Substrates and Devices Thereon - A relaxed epitaxial Al04-19-2012
20120091464GaN LEDs with Improved Area and Method for Making the Same - Enlightening device and method for making the same are disclosed. Individual light emitting devices such as LEDs are separated to form individual dies by process in which a first narrow trench cuts the light emitting portion of the device and a second trench cuts the substrate to which the light emitting portion is attached. The first trench can be less than 10 μm. Hence, a semiconductor area that would normally be devoted to dicing streets on the wafer is substantially reduced thereby increasing the yield of devices. The devices generated by this method can also include base members that are electrically conducting as well as heat conducting in which the base member is directly bonded to the light emitting layers thereby providing improved heat conduction.04-19-2012
20120091463NITRIDE SEMICONDUCTOR LIGHT-EMITTING ELEMENT AND MANUFACTURING METHOD THEREFOR - A nitride-based semiconductor light-emitting device according to the present invention has a nitride-based semiconductor multilayer structure 04-19-2012
20120326160SEMICONDUCTOR DEVICE HAVING NITRIDE SEMICONDUCTOR LAYER - A semiconductor device includes a silicon substrate, an aluminum nitride layer which is arranged on the silicon substrate and has a region where silicon is doped thereof as an impurity, a buffer layer which is arranged on the aluminum nitride layer and has a structure where a plurality of nitride semiconductor films are laminated, and a semiconductor functional layer which is arranged on the buffer layer and made of nitride semiconductor.12-27-2012
20100219416METHOD OF IMPROVING SURFACE MORPHOLOGY OF (GA,AL,IN,B)N THIN FILMS AND DEVICES GROWN ON NONPOLAR OR SEMIPOLAR (GA,AL,IN,B)N SUBSTRATES - A method for improving the growth morphology of (Ga,Al,In,B)N thin films on nonpolar or semipolar (Ga,Al,In,B)N substrates, wherein a (Ga,Al,In,B)N thin film is grown directly on a nonpolar or semipolar (Ga,Al,In,B)N substrate or template and a portion of the carrier gas used during growth is comprised of an inert gas. Nonpolar or semipolar nitride LEDs and diode lasers may be grown on the smooth (Ga,Al,In,B)N thin films grown by the present invention.09-02-2010
20120286287VERTICAL GALLIUM NITRIDE-BASED LIGHT EMITTING DIODE AND METHOD OF MANUFACTURING THE SAME - The present disclosure provides a vertical GaN-based semiconductor diode and a method of manufacturing the same. The GaN-based πi-V group semiconductor device includes a substrate, a p-type ohmic electrode layer on the substrate, a p-type GaN-based πi-V group compound semiconductor layer on the p-type ohmic electrode layer, an n-type GaN-based πi-V group compound semiconductor layer on the p-type GaN-based πi-V group compound semiconductor layer, and an n-type ohmic electrode layer on the n-type GaN-based IE-V group compound semiconductor layer. The p-type ohmic electrode layer is an Ag-based highly reflective electrode having a high reflectivity of 70% or more, and a surface of the n-type GaN-based E-V group compound semiconductor layer is subjected to at least one of a process of forming photonic crystals and a process of surface roughening.11-15-2012
20120138952HIGH PRESSURE CHEMICAL VAPOR DEPOSITION APPARATUSES, METHODS, AND COMPOSITIONS PRODUCED THEREWITH - A composition, reactor apparatus, method, and control system for growing epitaxial layers of group III-nitride alloys. Super-atmospheric pressure is used as a process parameter to control the epitaxial layer growth where the identity of alloy layers differ within a heterostructure stack of two or more layers.06-07-2012
20120138950ISLAND MATRIXED GALLIUM NITRIDE MICROWAVE AND POWER SWITCHING TRANSISTORS - A gallium nitride (GaN) device that has greatly superior current handling ability per unit area than previously described GaN devices. The improvement is due to improved layout topology. The layout scheme, which uses island electrodes rather than finger electrodes, is shown to increase the active area density over that of conventional interdigitated structures. Ultra low on resistance transistors can be built using the island topology. Specifically, the present invention, which uses conventional GaN lateral technology and electrode spacing, provides a means to enhance cost/effective performance of all lateral GaN structures.06-07-2012
20120138946SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a cooler having a main surface constructed of a metal base, joined layers fixed on the metal base through joining layers, insulating layers fixed on the joined layers and which contain an organic resin as a base material, metal layers provided on the insulating layers, and semiconductor elements provided on the metal layers. A stacked structure with the joined layers, the insulating layers, and the metal layers is divided into parts containing one or the plurality of semiconductor elements, and is fixed through the joining layers on the metal base.06-07-2012
20120138945REDUCING WAFER DISTORTION THROUGH A LOW CTE LAYER - Provided is a method of fabricating a semiconductor device. The method includes forming a first layer on a first side of a first silicon wafer. The first silicon wafer has a second side opposite the first side. The first layer has a coefficient-of-thermal-expansion (CTE) that is lower than that of silicon. The method includes bonding the first wafer to a second silicon wafer in a manner so that the first layer is disposed in between the first and second silicon wafers. The method includes removing a portion of the first silicon wafer from the second side. The method includes forming a second layer over the second side of the first silicon wafer. The second layer has a CTE higher than that of silicon.06-07-2012
20130009166SEMICONDUCTOR DEVICE - One embodiment of a semiconductor device according to the present invention includes a substrate, a base compound semiconductor layer layered on the substrate to form a base, a channel defining compound semiconductor layer layered on the base compound semiconductor layer to define a channel, and an impact ionization control layer that is layered within a layering range of the base compound semiconductor layer and controls the location of impact ionization, wherein the base compound semiconductor layer is formed of a first compound semiconductor, the channel defining compound semiconductor layer is formed of a second compound semiconductor, and the impact ionization control layer is formed of a third compound semiconductor that has a smaller band gap than the first compound semiconductor.01-10-2013
20130009164POWER DEVICE AND METHOD FOR MANUFACTURING THE SAME - Provided is a power device. The power device may include a two-dimensional electron gas (2-DEG) layer in a portion corresponding to a gate electrode pattern since a second nitride layer is further formed on a lower portion of the gate electrode pattern after a first nitride layer is formed and thus, may be capable of performing a normally-OFF operation. Accordingly, the power device may adjust generation of the 2-DEG layer based on a voltage of a gate, and may reduce power consumption. The power device may regrow only the portion corresponding to the gate electrode pattern or may etch a portion excluding the portion corresponding to the gate electrode pattern and thus, a recess process may be omissible, a reproducibility of the power device may be secured, and a manufacturing process may be simplified.01-10-2013
20130009165NITRIDE SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING THE SAME AND NITRIDE SEMICONDUCTOR POWER DEVICE - Disclosed herein are a nitride semiconductor device, a method for manufacturing the same, and a nitride semiconductor power device. According to an exemplary embodiment of the present invention, a nitride semiconductor device includes: a nitride semiconductor layer over a substrate wherein the nitride semiconductor layer has a two-dimensional electron gas (2DEG) channel formed therein; a D-mode FET that includes a gate electrode Schottky-contacting with the nitride semiconductor layer to form a normally-on operating depletion-mode (D-mode) HEMT structure; and a Schottky diode part that includes an anode electrode Schottky-contacting with the nitride semiconductor layer and increases a gate driving voltage of the D-mode FET, the anode electrode being connected to the gate electrode of the D-mode FET. In addition, the nitride semiconductor power device and the method for manufacturing a nitride semiconductor device are proposed.01-10-2013
20130015460SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAMEAANM CHEN; Po-ChihAACI Hsinchu CityAACO TWAAGP CHEN; Po-Chih Hsinchu City TWAANM YU; Jiun-Lei JerryAACI Zhudong TownshipAACO TWAAGP YU; Jiun-Lei Jerry Zhudong Township TWAANM YAO; Fu-WeiAACI Hsinchu CityAACO TWAAGP YAO; Fu-Wei Hsinchu City TWAANM HSU; Chun-WeiAACI Taichung CityAACO TWAAGP HSU; Chun-Wei Taichung City TWAANM YANG; Fu-ChihAACI Fengshan CityAACO TWAAGP YANG; Fu-Chih Fengshan City TWAANM TSAI; Chun LinAACI HsinchuAACO TWAAGP TSAI; Chun Lin Hsinchu TW - An embodiment of the disclosure includes a semiconductor structure. The semiconductor structure includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and different from the first III-V compound layer in composition. An interface is defined between the first III-V compound layer and the second III-V compound layer. A gate is disposed on the second III-V compound layer. A source feature and a drain feature are disposed on opposite side of the gate. Each of the source feature and the drain feature includes a corresponding metal feature at least partially embedded in the second III-V compound layer. A corresponding intermetallic compound underlies each metal feature. Each intermetallic compound contacts a carrier channel located at the interface.01-17-2013
20130015462TRANSISTORS WITH DUAL LAYER PASSIVATION - Semiconductor devices are provided with dual passivation layers. A semiconductor layer is formed on a substrate and covered by a first passivation layer (PL-01-17-2013
20130015464POWER SEMICONDUCTOR DEVICEAANM HUR; Seung BaeAACI Suwon-siAACO KRAAGP HUR; Seung Bae Suwon-si KRAANM Kim; Ki SeAACI Suwon-siAACO KRAAGP Kim; Ki Se Suwon-si KR - A power semiconductor device and a manufacturing method thereof are provided. The power semiconductor device includes an anode electrode including an anode electrode pad, electrode bus lines connected to a first side and a second side on the anode electrode pad, the electrode bus lines each having a decreasing width in a direction away from the anode electrode pad, and pluralities of first anode electrode fingers and second anode electrode fingers connected with a third side and a fourth side on the anode electrode pad and with both sides of the electrode bus line, a cathode electrode including a first cathode electrode pad and a second cathode electrode pad, a plurality of cathode electrode fingers connected with the first cathode electrode pad, and a plurality of second cathode electrode fingers connected with the second cathode electrode pad, and an insulation layer disposed at an external portion of the anode.01-17-2013
20130015461Light-emitting Device Capable of Producing White Light And Light Mixing Method For Producing White Light With SameAANM Lin; Kuen-ChiuanAACO USAAGP Lin; Kuen-Chiuan US - A light-emitting device capable of producing white light includes at least two types of LED elements and at least one encapsulant material. Each of the LED elements has an epitaxial light-emitting layer grown on a substrate; and the epitaxial light-emitting layers for the LED elements are the same series of AlGaInN materials having emission wavelengths in a region from violet to green light and different from one another by at least 30 nm. The encapsulant material encapsulates the LED elements and contains an adequate amount of fluorescent powder, which can be excited to emit complementary color lights to mix with color lights from the LED elements to produce bluish, yellowish, greenish or reddish white light. At least two types of the white light-emitting devices can be differently arrayed in a module or a system to produce a white light with high color-rendering index and good light mixing effect.01-17-2013
20130015463NITRIDE-BASED SEMICONDUCTOR DEVICE HAVING EXCELLENT STABILITYAANM LEE; Jae HoonAACI Suwon-siAACO KRAAGP LEE; Jae Hoon Suwon-si KR - A nitride-based semiconductor device is provided. The nitride-based semiconductor device may include an aluminum silicon carbide (AlSi01-17-2013
20130015465NITRIDE SEMICONDUCTOR LIGHT-EMITTING DEVICEAANM LEE; Jae-hoonAACI Suwon-siAACO KRAAGP LEE; Jae-hoon Suwon-si KR - A nitride light-emitting device includes an N-type nitride semiconductor layer; an active layer disposed on the N-type nitride semiconductor layer; and a P-type nitride semiconductor layer disposed on the active layer. The P-type nitride semiconductor includes a heterojunction structure having a GaN layer and an N-type Al01-17-2013
20130020580HETEROEPITAXIAL GROWTH USING ION IMPLANTATION - In one embodiment, a method of growing a heteroepitaxial layer comprises providing a patterned substrate containing patterned features having sidewalls. The method also includes directing ions toward the sidewalls in an exposure, wherein altered sidewall regions are formed, and depositing the heteroepitaxial layer under a set of deposition conditions effective to preferentially promote epitaxial growth on the sidewalls in comparison to other surfaces of the patterned features.01-24-2013
20130020582RAPID FABRICATION METHODS FOR FORMING NITRIDE BASED SEMICONDUCTORS BASED ON FREESTANDING NITRIDE GROWTH SUBSTRATES - High temperature bonding and interconnect methods can be used for LED and other optoelectronic devices based on freestanding nitride devices. Inorganic glasses, especially those which exhibit a CTE, which substantially matches the CTE of the freestanding nitride devices, can provide hermetic sealing of the freestanding nitride devices or the contact regions of the freestanding nitride devices. The freestanding nitride devices are typically freestanding nitride veneers.01-24-2013
20130020581EPITAXIAL WAFER INCLUDING NITRIDE-BASED SEMICONDUCTOR LAYERS - An epitaxial wafer including nitride-based semiconductor layers usable for a hetero-junction field effect type transistor, includes a first buffer layer of AlN or AlON, a second buffer layer of Al01-24-2013
20130020584SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - In the present invention, provided is a semiconductor device, including: a GaN channel layer which is provided on a substrate and through which electrons run; a barrier layer which is provided on the GaN channel layer and which contains at least one of In, Al, and Ga and contains N; a gate electrode which is provided on the barrier layer; and a source electrode and a drain electrode which are provided on the substrate across the gate electrode, in which, in a portion of the barrier layer between the gate electrode and the drain electrode, a magnitude of polarization of the barrier layer is smaller on the gate electrode side than on the drain electrode side. Thus, PAE can be improved by reducing Rd and Cgd simultaneously.01-24-2013
20130020583EPITAXIAL SUBSTRATE AND METHOD FOR MANUFACTURING EPITAXIAL SUBSTRATE - Provided is a crack-free epitaxial substrate. The epitaxial substrate includes: a (111) single crystal Si substrate and a buffer layer formed of a first and a second lamination unit being alternately laminated such that each of an uppermost and a lowermost portion of the buffer layer is formed of the first lamination unit. The first lamination unit is formed of a first and a second composition layer having different compositions being alternately laminated so as to increase the thickness of the second composition layer in a portion more distant from the base substrate side, to thereby cause a compressive strain to exist in the first lamination unit such that it increases in a portion more distant from the base substrate. The second lamination unit is formed as an intermediate layer that is substantially strain-free and formed with a thickness of 15 nm or more and 150 nm or less.01-24-2013
20120241759NITRIDE SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE - A nitride semiconductor device having a high withstand voltage and being capable of reducing a leakage current, is provided. The nitride semiconductor device 09-27-2012
20120241758COMPOUND SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A compound semiconductor device is provided with a first nitride semiconductor layer of a first conductivity type, a second nitride semiconductor layer of the first conductivity type which is formed over the first nitride semiconctor layer and being in contact with the first nitride semiconductor layer, a third nitride semiconductor layer of a second conductivity type being in contact with the second nitride semiconductor layer, a fourth nitride semiconductor layer of the first conductivity type being in contact with the third nitride semiconductor layer, and an insulating film insulating the first nitride semiconductor layer and the fourth nitride, semiconductor layer from each other. A source electrode is positioned inside an Outer edge of the insulating film in planar view.09-27-2012
20120241757LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - A light emitting device and a method of manufacturing the same are disclosed. The light emitting device includes a buffer layer formed on a substrate, a nitride semiconductor layer including a first semiconductor layer, an active layer, and a second semiconductor layer, which are sequentially stacked on the buffer layer, a portion of the first semiconductor layer being exposed to the outside by performing mesa etching from the second semiconductor layer to the portion of the first semiconductor layer, and at least one nanocone formed on the second semiconductor layer.09-27-2012
20120241755 METHOD FOR REDUCING INTERNAL MECHANICAL STRESSES IN A SEMICONDUCTOR STRUCTURE AND A LOW MECHANICAL STRESS SEMICONDUCTOR STRUCTURE - A semiconductor structure with low mechanical stresses, formed of nitrides of group III metals on a (0001) oriented foreign substrate (09-27-2012
20120241754LIGHT EMITTING DIODE AND METHOD OF MANUFACTURING THEREOF - This invention directs to a light-emitting diode. The light-emitting diode includes a substrate, a semiconductor layer and an active layer. The semiconductor layer is disposed on the substrate and has a plurality of undulating structures. The active layer is conformably disposed on the semiconductor layer to have another plurality of undulating structures.09-27-2012
20130134435HIGH ELECTRON MOBILITY TRANSISTOR STRUCTURE WITH IMPROVED BREAKDOWN VOLTAGE PERFORMANCE - A high electron mobility transistor (HEMT) includes a silicon substrate, an unintentionally doped gallium nitride (UID GaN) layer over the silicon substrate. The HEMT further includes a donor-supply layer over the UID GaN layer, a gate structure, a drain, and a source over the donor-supply layer. The HEMT further includes a dielectric layer having one or more dielectric plug portions in the donor-supply layer and top portions between the gate structure and the drain over the donor-supply layer. A method for making the HEMT is also provided.05-30-2013
20130134433Metallization structure for high power microelectronic devices - A semiconductor device structure is disclosed that includes a wide-bandgap semiconductor portion selected from the group consisting of silicon carbide and the Group III nitrides. An interconnect structure is made to the semiconductor portion, and the interconnect structure includes at least two diffusion barrier layers alternating with two respective high electrical conductivity layers. The diffusion barrier layers have a coefficient of thermal expansion different from and lower than the coefficient of thermal expansion of the high electrical conductivity layers. The difference in the respective coefficients of thermal expansions are large enough to constrain the expansion of the high conductivity layers but less than a difference that would create a strain between adjacent layers that would exceed the bond strength between the layers.05-30-2013
20080237606COMPOUND SEMICONDUCTOR DEVICE - A compound semiconductor device having a transistor structure, includes a substrate, a first layer formed on the substrate and comprising GaN, a second layer formed over the first layer and containing InN whose lattice constant is larger than the first layer, a third layer formed over the second layer and comprising GaN whose energy bandgap is smaller than the second layer, and a channel region layer formed on the third layer.10-02-2008
20080237605SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor device includes: a first semiconductor layer which is made of a first group III nitride semiconductor; a cap layer which is formed on the first semiconductor layer, which is made of a second group III nitride semiconductor, and which has an opening for exposing the first semiconductor layer; and a source electrode and a drain electrode which are formed on the cap layer so as to oppose to each other with the opening interposed. A gate electrode is formed on the bottom face of the opening with an insulating film interposed. The insulating film is formed on at least a part of the first semiconductor layer which is exposed through the opening.10-02-2008
20080230786High temperature performance capable gallium nitride transistor - A transistor device capable of high performance at high temperatures. The transistor comprises a gate having a contact layer that contacts the active region. The gate contact layer is made of a material that has a high Schottky barrier when used in conjunction with a particular semiconductor system (e.g., Group-III nitrides) and exhibits decreased degradation when operating at high temperatures. The device may also incorporate a field plate to further increase the operating lifetime of the device.09-25-2008
20080230785Termination and contact structures for a high voltage GaN-based heterojunction transistor - A semiconductor device is provided that includes a substrate, a first active layer disposed over the substrate, and a second active layer disposed on the first active layer. The second active layer has a higher bandgap than the first active layer such that a two-dimensional electron gas layer arises between the first active layer and the second active layer. A termination layer, which is disposed on the second active layer, includes InGaN. Source, gate and drain contacts are disposed on the termination layer.09-25-2008
20080230784Cascode circuit employing a depletion-mode, GaN-based fet - A circuit includes an input drain, source and gate nodes. The circuit also includes a group III nitride depletion mode FET having a source, drain and gate, wherein the gate of the depletion mode FET is coupled to a potential that maintains the depletion mode FET in its on-state. In addition, the circuit further includes an enhancement mode FET having a source, drain and gate. The source of the depletion mode FET is serially coupled to the drain of the enhancement mode FET. The drain of the depletion mode FET serves as the input drain node, the source of the enhancement mode FET serves as the input source node and the gate of the enhancement mode FET serves as the input gate node.09-25-2008
20130168685HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD OF FORMING THE SAME - A high electron mobility transistor (HEMT) includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer. A p-type layer is disposed on a portion of the second III-V compound layer between the source feature and the drain feature. A gate electrode is disposed on the p-type layer. The gate electrode includes a refractory metal. A depletion region is disposed in the carrier channel and under the gate electrode.07-04-2013
20130168686HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD OF FORMING THE SAME - A high electron mobility transistor (HEMT) includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer. Each of the source feature and the drain feature comprises a corresponding intermetallic compound at least partially embedded in the second III-V compound layer. Each intermetallic compound is free of Au and comprises Al, Ti or Cu. A p-type layer is disposed on a portion of the second III-V compound layer between the source feature and the drain feature. A gate electrode is disposed on the p-type layer. A depletion region is disposed in the carrier channel and under the gate electrode.07-04-2013
20130140582SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - The present invention relates to a semiconductor device and a method for manufacturing the same. A RESURF layer (06-06-2013
20130140581OPTICAL DEVICE - An optical device is provided. Multi-layer structures are disposed on a substrate, wherein each of the multi-layer structures is consisting of at least two insulated layers with different refractive indexes formed alternately. A buffer layer covers the multi-layer structures, so that said multi-layer structures are disposed between the buffer layer and the substrate, wherein said buffer layer is an un-doped GaN based semiconductor layer. A first conductive semiconductor layer is disposed on the buffer layer. An active layer is disposed on said first conductive semiconductor layer. A second conductive semiconductor layer is disposed on said active layer and a transparent conductive layer is disposed on said second conductive semiconductor layer.06-06-2013
20130140579METHOD OF INTEGRATING A PLURALITY OF BENZOCYCLOBUTENE LAYERS WITH A SUBSTRATE AND AN ASSOCIATED DEVICE - A method of integrating benzocyclobutene (BCB) layers with a substrate is provided along with a corresponding device. A method includes forming a first BCB layer on the substrate and depositing a first metal layer on the first BCB layer and within vias defined by the first metal layer. The method also forms a second BCB layer on the first metal layer and deposits a second metal layer on the second BCB layer and within vias defined by the second metal layer. The second metal layer extends through the vias defined by the second metal layer to establish an operable connection with the first metal layer. The first and second metal layers are independent of an electrical connection to any circuit element carried by the substrate, but the first and second metal layers secure the second BCB layer to the underlying structure and reduce the likelihood of delamination.06-06-2013
20080224148SEMICONDUCTOR SENSING DEVICE - A semiconductor sensing device in which a sensing layer is exposed to a medium being tested in an area below and/or adjacent to a contact. In one embodiment, the device comprises a field effect transistor in which the sensing layer is disposed below a gate contact. The sensing layer is exposed to the medium by one or more perforations that are included in the gate contact and/or one or more layers disposed above the sensing layer. The sensing layer can comprise a dielectric layer, a semiconductor layer, or the like.09-18-2008
20130175539HIGH ELECTRON MOBILITY TRANSISTORS AND METHODS OF MANUFACTURING THE SAME - According to example embodiments, a high electron mobility transistor (HEMT) includes a channel supply layer and a channel layer. The channel layer may include an effective channel region and a high resistivity region. The effective channel region may be between the high resistivity region and the channel supply layer. The high resistivity region may be a region into which impurities are ion-implanted. According to example embodiments, a method of forming a HEMT includes forming a device unit, including a channel layer and a channel supply layer, on a first substrate; adhering a second substrate to the device unit; removing the first substrate; and forming a high resistivity region by ion-implanting impurities into at least a portion of the channel layer.07-11-2013
20130175540DOPED DIAMOND LED DEVICES AND ASSOCIATED METHODS - LED devices and methods for making such devices are provided. One such method may include forming epitaxially a substantially single crystal SiC layer on a substantially single crystal Si wafer, forming epitaxially a substantially single crystal diamond layer on the SiC layer, doping the diamond layer to form a conductive diamond layer, removing the Si wafer to expose the SiC layer opposite to the conductive diamond layer, forming epitaxially a plurality of semiconductor layers on the SiC layer such that at least one of the semiconductive layers contacts the SiC layer, and coupling an n-type electrode to at least one of the semiconductor layers such that the plurality of semiconductor layers is functionally located between the conductive diamond layer and the n-type electrode.07-11-2013
20130175541METHOD OF GROWING NITRIDE SEMICONDUCTOR LAYER - A method of growing a nitride semiconductor layer may include preparing a substrate in a reactor, growing a first nitride semiconductor on the substrate at a first temperature, the first nitride semiconductor having a thermal expansion coefficient different from a thermal expansion coefficient of the substrate, and removing the substrate at a second temperature.07-11-2013
20130175542Group III-V and Group IV Composite Diode - In one implementation, a group III-V and group IV composite diode includes a group IV diode in a lower active die, the group IV diode having an anode situated on a bottom side of the lower active die. The group III-V and group IV composite diode also includes a group III-V transistor in an upper active die stacked over the lower active die, the group III-V transistor having a drain, a source, and a gate situated on a top side of the upper active die. The source of the group III-V transistor is electrically coupled to a cathode of the group IV diode using a through-semiconductor via (TSV) of the upper active die.07-11-2013
20130175543COMPOSITE GaN SUBSTRATE, METHOD FOR MANUFACTURING COMPOSITE GaN SUBSTRATE, GROUP III NITRIDE SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING GROUP III NITRIDE SEMICONDUCTOR DEVICE - A composite GaN substrate of the present invention includes: a conductive GaN substrate having a specific resistance of less than 1 Ωcm; and a semi-insulative GaN layer disposed on the conductive GaN substrate, having a specific resistance of 1×1007-11-2013
20130175544SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - It is an object to attain both high gain and a broad band (that is, to attain both reduction in a gate-drain capacitance and reduction in a source-drain capacitance). Provided is a semiconductor device, including: a GaN channel layer (07-11-2013
20130168687ENHANCEMENT MODE GALLIUM NITRIDE BASED TRANSISTOR DEVICE - Provided is an enhancement mode GaN-based transistor device including an epitaxial stacked layer disposed on a substrate; a source layer and a drain layer disposed on a surface of the epitaxial stacked layer; a p-type metal oxide layer disposed between the source layer and the drain layer; and a gate layer disposed on the p-type metal oxide layer. Besides, the p-type metal oxide layer includes a body part disposed on the surface of the epitaxial stacked layer, and a plurality of extension parts connecting the body part and extending into the epitaxial stacked layer. With such structure, the enhancement mode GaN-based transistor device can effectively suppress generation of the gate leakage current.07-04-2013
20130168689NITRIDE BASED SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - With the formation of a Si07-04-2013
20130168690SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - A first nitride semiconductor layer contains Ga. The first nitride semiconductor layer is, for example, a GaN layer, an AlGaN layer, or an AlInGaN layer. Then, an aluminum oxide layer has tetra-coordinated Al atoms each surrounded by four O atoms and hexa-coordinated Al atoms each surrounded by six O atoms as Al atoms in the interface region with respect to the first nitride semiconductor layer. The interface region is a region apart, for example, by 1.5 nm or less from the interface with respect to the first nitride semiconductor layer. Then, in the interface region, the tetra-coordinated Al atoms are present by 30 at % or more and less than 50 at % based on the total number of Al atoms.07-04-2013
20130168692POLYCRYSTALLINE ALUMINUM NITRIDE BASE MATERIAL FOR CRYSTAL GROWTH OF GaN-BASE SEMICONDUCTOR AND METHOD FOR MANUFACTURING GaN-BASE SEMICONDUCTOR USING THE SAME - There is provided a polycrystalline aluminum nitride substrate that is effective in growing a GaN crystal. The polycrystalline aluminum nitride base material for use as a substrate material for grain growth of GAN-base semiconductors, contains 1 to 10% by weight of a sintering aid component and has a thermal conductivity of not less than 150 W/m·K, the substrate having a surface free from recesses having a maximum diameter of more than 200 μm.07-04-2013
20120248457GROUP III NITRIDE SEMICONDUCTOR MULTILAYER STRUCTURE AND PRODUCTION METHOD THEREOF - According to the present invention, an AlN crystal film seed layer having high crystallinity is combined with selective/lateral growth, whereby a Group III nitride semiconductor multilayer structure more enhanced in crystallinity can be obtained. The Group III nitride semiconductor multilayer structure of the present invention is a Group III nitride semiconductor multilayer structure where an AlN crystal film having a crystal grain boundary interval of 200 nm or more is formed as a seed layer on a C-plane sapphire substrate surface by a sputtering method and an underlying layer, an n-type semiconductor layer, a light-emitting layer and a p-type semiconductor layer, each composed of a Group III nitride semiconductor, are further stacked, wherein regions in which the seed layer is present and is absent are formed on the C-plane sapphire substrate surface and/or regions capable of epitaxial growth and incapable of epitaxial growth are formed in the underlying layer.10-04-2012
20130134434NITRIDE SEMICONDUCTOR SUBSTRATE - A nitride semiconductor device includes a main surface and an indicator portion. The main surface is a plane inclined by at least 71° and at most 79° in a [1-100] direction from a (0001) plane or a plane inclined by at least 71° and at most 79° in a [−1100] direction from a (000-1) plane. The indicator portion indicates a (−1017) plane, a (10-1-7) plane, or a plane inclined by at least −4° and at most 4° in the [1-100] direction from these planes and inclined by at least −0.5° and at most 0.5° in a direction orthogonal to the [1-100] direction.05-30-2013
20130168691METHOD OF MANUFACTURING SEMICONDUCTOR LIGHT EMITTING ELEMENT, SEMICONDUCTOR LIGHT EMITTING ELEMENT, ELECTRONIC DEVICE, AND MACHINE DEVICE - Provided is a method of manufacturing a semiconductor light emitting element that is capable of making a light emitting wavelength distribution σ of a semiconductor light emitting layer that is obtained small. The method includes a process of laminating a re-growth layer of a compound semiconductor layer on the compound semiconductor substrate which is obtained by forming at least one compound semiconductor layer on a substrate and in which a warping amount H is within a range of 50 μm≦H≦250 μm. The method adopts a method of manufacturing a semiconductor light emitting element including an n-type semiconductor layer, a light emitting layer, and a p-type semiconductor layer that are formed from a compound semiconductor. This method includes: a process of preparing a compound semiconductor substrate which is obtained by forming at least one compound semiconductor layer on a substrate and in which a warping amount H is within a range of 50 μm≦H≦250 μm; and a process of laminating a re-growth layer of the compound semiconductor layer on the compound semiconductor layer of the compound semiconductor substrate in a metalorganic chemical vapor deposition apparatus.07-04-2013
20130134440High-resolution Parallel-detection Sensor Array Using Piezo-Phototronics Effect - A pressure sensor element includes a substrate, a first type of semiconductor material layer and an array of elongated light-emitting piezoelectric nanostructures extending upwardly from the first type of semiconductor material layer. A p-n junction is formed between each nanostructure and the first type semiconductor layer. An insulative resilient medium layer is infused around each of the elongated light-emitting piezoelectric nanostructures. A transparent planar electrode, disposed on the resilient medium layer, is electrically coupled to the top of each nanostructure. A voltage source is coupled to the first type of semiconductor material layer and the transparent planar electrode and applies a biasing voltage across each of the nanostructures. Each nanostructure emits light in an intensity that is proportional to an amount of compressive strain applied thereto.05-30-2013
20130134438Light Emitting, Photovoltaic Or Other Electronic Apparatus and System - The present invention provides an electronic apparatus, such as a lighting device comprised of light emitting diodes (LEDs) or a power generating apparatus comprising photovoltaic diodes, which may be created through a printing process, using a semiconductor or other substrate particle ink or suspension and using a lens particle ink or suspension. An exemplary apparatus comprises a base; at least one first conductor; a plurality of diodes coupled to the at least one first conductor; at least one second conductor coupled to the plurality of diodes; and a plurality of lenses suspended in a polymer deposited or attached over the diodes. The lenses and the suspending polymer have different indices of refraction. In some embodiments, the lenses and diodes are substantially spherical, and have a ratio of mean diameters or lengths between about 10:1 and 2:1. The diodes may be LEDs or photovoltaic diodes, and in some embodiments, have a junction formed at least partially as a hemispherical shell or cap.05-30-2013
20130134441GAN-BASED LEDS ON SILICON SUBSTRATES WITH MONOLITHICALLY INTEGRATED ZENER DIODES - GaN LEDs monolithically integrated with silicon-based ESD protection diodes. Hybrid MOCVD or HVPE epitaxial systems may be utilized for in-situ epitaxially growth of doped silicon containing films to form both the silicon-based ESD protection diode material stacks as well as a silicon containing transition layer prior to growth of a GaN-based LED material stack. The silicon-based ESD protection diodes may be interconnected with layers of a GaN LED material stack to form Zener diodes connected with the GaN LEDs.05-30-2013
20130134439EPITAXIAL SUBSTRATE FOR SEMICONDUCTOR ELEMENT, SEMICONDUCTOR ELEMENT, PN JUNCTION DIODE, AND METHOD FOR MANUFACTURING AN EPITAXIAL SUBSTRATE FOR SEMICONDUCTOR ELEMENT - Provided is an epitaxial substrate for use in a semiconductor element, having excellent characteristics and capable of suitably suppressing diffusion of elements from a cap layer. An epitaxial substrate for use in a semiconductor element, in which a group of group-III nitride layers are laminated on a base substrate such that a (0001) crystal plane of the group of group-III nitride layers is substantially in parallel with a substrate surface of the base substrate, includes: a channel layer made of a first group-III nitride having a composition of In05-30-2013
20130175537HIGH ELECTRON MOBILITY GaN-BASED TRANSISTOR STRUCTURE - A high electron mobility GaN-based transistor structure comprises a substrate, an epitaxial GaN layer formed on the substrate, at least one ohmic contact layer formed on the epitaxial GaN layer, a metallic gate layer formed on the epitaxial GaN layer, and a diffusion barrier layer interposed between the metallic gate layer and the epitaxial GaN layer. The diffusion barrier layer hinders metallic atoms of the metallic gate layer from diffusing into the epitaxial GaN layer, whereby are improved the electric characteristics and reliability of the GaN-based transistor.07-11-2013
20130175538SUBSTRATE STRUCTURE, SEMICONDUCTOR DEVICE FABRICATED FROM THE SAME, AND METHOD OF FABRICATING THE SEMICONDUCTOR DEVICE - According to example embodiments, a substrate structure may include a GaN-based third material layer, a GaN-based second material layer, a GaN-based first material layer, and a buffer layer on a non-GaN-based substrate. The GaN-based first material layer may be doped with a first conductive type impurity. The GaN-based second material layer may be doped with a second conductive type impurity at a density that is less than a density of the first conductive type impurity in the first GaN-based material layer. The GaN-based third material layer may be doped with a first conductive type impurity at a density that is less than the density of the first conductive type impurity of the GaN-based first material layer. After a second substrate is attached onto the substrate structure, the non-GaN-based substrate may be removed and a GaN-based vertical type semiconductor device may be fabricated on the second substrate.07-11-2013
20130092952SEMICONDUCTOR DEVICE - A transistor which includes an electron transit layer and an electron supply layer which are stacked in a thickness direction of a substrate; an electron transit layer formed over the substrate in parallel to the electron transit layer and the electron supply layer; an anode electrode which forms a Schottky junction with the electron transit layer; and a cathode electrode which forms an ohmic junction with the electron transit layer are provided. The anode electrode is connected to a source of the transistor, and the cathode electrode is connected to a drain of the transistor.04-18-2013
20130092953EPITAXIAL SUBSTRATE AND METHOD FOR MANUFACTURING EPITAXIAL SUBSTRATE - Provided is a crack-free epitaxial substrate having a small amount of warping, in which a silicon substrate is used as a base substrate. The epitaxial substrate includes: a (111) single crystal Si substrate and a buffer layer formed of a plurality of lamination units being continuously laminated. The lamination unit includes: a composition modulation layer formed of a first and a second unit layer having different compositions being alternately and repeatedly laminated such that a compressive strain exists therein; a termination layer formed on an uppermost portion of the composition modulation layer, the termination layer acting to maintain the compressive strain existing in the composition modulation layer; and a strain reinforcing layer formed on the termination layer, the strain reinforcing layer acting to enhance the compressive strain existing in the composition modulation layer.04-18-2013
20130092949SEMICONDUCTOR DEVICE, SEMICONDUCTOR SUBSTRATE, METHOD FOR MANUFACTURING DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE - A second epitaxial layer is grown epitaxially over a first epitaxial layer. The first epitaxial layer includes an epitaxially grown layer and a defect layer. The defect layer is disposed over the epitaxially grown layer and serves as a surface layer of the first epitaxial layer. The defect density of the defect layer is 5×1004-18-2013
20130092950NITRIDE SEMICONDUCTOR GROWTH SUBSTRATE AND MANUFACTURING METHOD OF THE SAME, NITRIDE SEMICONDUCTOR EPITAXIAL SUBSTRATE AND NITRIDE SEMICONDUCTOR ELEMENT - A nitride semiconductor growth substrate includes a principal surface including a C-plane of a sapphire substrate, and a convex portion that is formed on the principal surface, has a cone or pyramid shape or a truncated cone or pyramid shape, is disposed to form a lattice pattern in a top view thereof, and includes a side surface inclined at an angle of less than 90 degrees relative to the principal surface. The convex portion has a height of 0.5 to 3 μm from the principal surface. A distance between adjacent ones of the convex portion is 1 to 6 μm. The side surface of the convex portion has a surface roughness (RMS) of not more than 10 nm.04-18-2013
20130092951GALLIUM NITRIDE-BASED SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A gallium nitride-based semiconductor device includes a composite substrate and a gallium nitride layer. The composite substrate includes a silicon substrate and a filler. The silicon substrate includes a first surface and a second surface opposite to the first surface, and the first surface defines a number of grooves therein. The filler is filled into the number of grooves on the first surface of the silicon substrate. A thermal expansion coefficient of the filler is bigger than that of the silicon substrate. The gallium nitride layer is formed on the second surface of the silicon substrate.04-18-2013
20130092947SEMICONDUCTOR DEVICE AND METHOD OF MAKING - In some embodiments, a metal insulator semiconductor heterostructure field effect transistor (MISHFET) is disclosed that has a source, a drain, an insulation layer, a gate dielectric, and a gate. The source and drain are on opposing sides of a channel region of a channel layer. The channel region is an upper portion of the channel layer. The channel layer comprises gallium nitride. The insulation layer is over the channel layer and has a first portion and a second portion. The first portion is nearer the drain than the source and has a first thickness. The second portion is nearer the source than drain and has the first thickness. The insulation layer has an opening through the insulation layer. The opening is between the first portion and the second portion.04-18-2013
20130099243SUBSTRATE BREAKDOWN VOLTAGE IMPROVEMENT FOR GROUP III-NITRIDE ON A SILICON SUBSTRATE - A circuit structure includes a substrate, a nucleation layer of undoped aluminum nitride, a graded buffer layer comprising aluminum, gallium, nitrogen, one of silicon and oxygen, and a p-type conductivity dopant, a ungraded buffer layer comprising gallium, nitrogen, one of silicon and oxygen, and a p-type conductivity dopant without aluminum, and a bulk layer of undoped gallium nitride over the ungraded buffer layer. The various dopants in the graded buffer layer and the ungraded buffer layer increases resistivity and results in layers having an intrinsically balanced conductivity.04-25-2013
20130099248NITRIDE SEMICONDUCTOR LIGHT EMITTING DEVICE - There is provided a nitride semiconductor light emitting device including an n-type nitride semiconductor layer, an active layer disposed on the n-type nitride semiconductor layer, and a p-type nitride semiconductor layer disposed on the active layer. One or more current diffusion layers are disposed on a surface of the n-type nitride semiconductor layer. The current diffusion layer(s) includes a material having greater band gap energy than that of a material forming the n-type nitride semiconductor layer so as to form a two-dimensional electron gas layer at an interface with the material forming the n-type nitride semiconductor layer.04-25-2013
20130099247SEMICONDUCTOR DEVICES HAVING A RECESSED ELECTRODE STRUCTURE - An electrode structure is described in which conductive regions are recessed into a semiconductor region. Trenches may be formed in a semiconductor region, such that conductive regions can be formed in the trenches. The electrode structure may be used in semiconductor devices such as field effect transistors or diodes. Nitride-based power semiconductor devices are described including such an electrode structure, which can reduce leakage current and otherwise improve performance.04-25-2013
20130099246SUBSTRATE FOR EPITAXIAL GROWTH - A surface of the substrate consists in plurality of neighbouring stripe shaped flat surfaces of a width from 1 to 2000 μm. Longer edges of the flat surfaces are parallel one to another and planes of these surfaces are disoriented relatively to the crystallographic plane of gallium nitride crystal defined by Miller-Bravais indices (0001), (11-22) or (11-20). Disorientation angle of each of the flat surfaces is between 0 and 3 degree and is different for each pair of neighbouring flat surfaces. Substrate according to the invention allows epitaxial growth of a layered AlInGaN structure by MOCVD or MBE method which permits for realization of a non-absorbing mirrors laser diode emitting a light of the wavelength from 380 to 550 nm and a laser diodes array which may emit simultaneously light of various wavelengths in the range of 380 to 550 nm.04-25-2013
20130099245FIELD EFFECT TRANSISTOR, METHOD FOR PRODUCING THE SAME, AND ELECTRONIC DEVICE - The present invention provides a field effect transistor which can achieve both of a high threshold voltage and a low on-state resistance, a method for producing the same, and an electronic device. In the field effect transistor, each of a buffer layer 04-25-2013
20130099244METHOD OF GROWING SEMICONDUCTOR HETEROSTRUCTURES BASED ON GALLIUM NITRIDE - The method of growing non-polar epitaxial heterostructures for light-emitting diodes producing white emission and lasers, on the basis of compounds and alloys in AlGaInN system, comprising the step of vapor-phase deposition of one or multiple heterostructures layers described by the formula Al04-25-2013
20130099249NITRIDE UV LIGHT SENSORS ON SILICON SUBSTRATES - An ultraviolet light sensor and method of manufacturing thereof are disclosed. The ultraviolet light sensor includes Group-III Nitride layers adjacent to a silicon wafer with one of the layers at least partially exposed such that a surface thereof can receive UV light to be detected. The Group-III Nitride layers include a p-type layer and an n-type layer, with p/n junctions therebetween forming at least one diode. Conductive contacts are arranged to conduct electrical current through the sensor as a function of ultraviolet light received at the outer Group-III Nitride layer. The Group-III Nitride layers may be formed from, e.g., GaN, InGaN, AlGaN, or InAlN. The sensor may include a buffer layer between one of the Group-III Nitride layers and the silicon wafer. By utilizing silicon as the substrate on which the UV sensor diode is formed, a UV sensor can be produced that is small, efficient, cost-effective, and compatible with other semiconductor circuits and processes. The sensor may be configured to be sensitive to a specific subtype or subband of ultraviolet radiation to be detected by selecting a specific composition of said Group-III Nitride layers.04-25-2013
20130112990Gallium Nitride Devices with Compositionally-Graded Transition Layer - The invention provides semiconductor materials including a gallium nitride material layer formed on a silicon substrate and methods to form the semiconductor materials. The semiconductor materials include a transition layer formed between the silicon substrate and the gallium nitride material layer. The transition layer is compositionally-graded to lower stresses in the gallium nitride material layer which can result from differences in thermal expansion rates between the gallium nitride material and the substrate. The lowering of stresses in the gallium nitride material layer reduces the tendency of cracks to form. Thus, the invention enables the production of o semiconductor materials including gallium nitride material layers having few or no cracks. The semiconductor materials may be used in a number of microelectronic and optical applications.05-09-2013
20130112989BROAD-AREA LIGHTING SYSTEMS - In accordance with certain embodiments, illumination systems are formed by aligning light-emitting elements with optical elements and/or disposing light-conversion materials on the light-emitting elements, as well as by providing electrical connectivity to the light-emitting elements05-09-2013
20130112988SEMICONDUCTOR LIGHT EMITTING DEVICE AND WAFER - A semiconductor light emitting device includes a first layer including at least one of n-type GaN and n-type AlGaN; a second layer including Mg-containing p-type AlGaN; and a light emitting section provided between the first and second layers. The light emitting section includes barrier layers of Si-containing Al05-09-2013
20130112987LIGHT EMITTING DIODE AND FABRICATING METHOD THEREOF - A light emitting diode including a GaN substrate, a first type semiconductor layer, a light emitting layer, a second type semiconductor layer, a first electrode, and a second electrode is provided. The GaN substrate has a first surface and a second surface opposite thereto, and the second surface has a plurality of protuberances, the height of the protuberance is h μm and the distribution density of the protuberance on the second surface is d cm05-09-2013
20130112986Gallium Nitride Semiconductor Devices and Method Making Thereof - The present disclosure relates to an enhancement mode gallium nitride (GaN) transistor device. The GaN transistor device has an electron supply layer located on top of a GaN layer. An etch stop layer (e.g., AlN) is disposed above the electron supply layer. A gate structure is formed on top of the etch stop layer, such that the bottom surface of the gate structure is located vertically above the etch stop layer. The position of etch stop layer in the GaN transistor device stack allows it to both enhance gate definition during processing (e.g., selective etching of the gate structure located on top of the AlN layer) and to act as a gate insulator that reduces gate leakage of the GaN transistor device.05-09-2013
20130112985MONOLITHICALLY INTEGRATED VERTICAL JFET AND SCHOTTKY DIODE - An integrated device including a vertical III-nitride FET and a Schottky diode includes a drain comprising a first III-nitride material, a drift region comprising a second III-nitride material coupled to the drain and disposed adjacent to the drain along a vertical direction, and a channel region comprising a third III-nitride material coupled to the drift region. The integrated device also includes a gate region at least partially surrounding the channel region, a source coupled to the channel region, and a Schottky contact coupled to the drift region. The channel region is disposed between the drain and the source along the vertical direction such that current flow during operation of the vertical III-nitride FET and the Schottky diode is along the vertical direction.05-09-2013
20130119400SELF-ALIGNED SIDEWALL GATE GaN HEMT - A method of fabricating a GaN HEMT includes growing a first epitaxial layer on a substrate, growing a second epitaxial layer on the first epitaxial layer, growing a third epitaxial layer on the second epitaxial layer, depositing a first dielectric film on the third epitaxial layer, using dielectric films to form a first sidewall dielectric spacer, forming a sidewall gate adjacent the first sidewall dielectric spacer. The sidewall gate may be made to be less than 50 nm in length.05-16-2013
20130119398NITRIDE-BASED SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A nitride-based semiconductor light-emitting device 05-16-2013
20130119395Tunnel FET and Methods for Forming the Same - A tunnel field-effect transistor (TFET) includes a gate electrode, a source region, and a drain region. The source and drain regions are of opposite conductivity types. A channel region is disposed between the source region and the drain region. A source diffusion barrier is disposed between the channel region and the source region. The source diffusion barrier and the source region are under and overlapping the gate electrode. The source diffusion barrier has a first bandgap greater than second bandgaps of the source region, the drain region, and the channel region.05-16-2013
20110266555METHOD OF GROWING SEMICONDUCTOR HETEROSTRUCTURES BASED ON GALLIUM NITRIDE - The method of growing non-polar epitaxial heterostructures for light-emitting diodes producing white emission and lasers, on the basis of compounds and alloys in AlGaInN system, comprising the step of vapor-phase deposition of one or multiple heterostructures layers described by the formula Al11-03-2011
20110266553NITRIDE SEMICONDUCTOR LIGHT-EMITTING ELEMENT AND METHOD OF MANUFACTURING THE SAME - An object of the present invention is to provide a nitride semiconductor light-emitting device in which contact resistance generated between an n-contact layer and an n-side electrode is effectively reduced while maintaining satisfactory external quantum efficiency, and a method of efficiently producing the nitride semiconductor light-emitting device. Specifically, the present invention characteristically provides a nitride semiconductor light-emitting device having a semiconductor laminated body including an n-type laminate, a light-emitting layer and a p-type laminate, and an n-side electrode and a p-side electrode, characterized in that: the n-type laminate includes an n-contact layer made of an Al11-03-2011
20130119401LARGE AREA NITRIDE CRYSTAL AND METHOD FOR MAKING IT - Techniques for processing materials in supercritical fluids including processing in a capsule disposed within a high-pressure apparatus enclosure are disclosed. The disclosed techniques are useful for growing crystals of GaN, AlN, InN, and their alloys, including InGaN, AlGaN, and AlInGaN for the manufacture of bulk or patterned substrates, which in turn can be used to make optoelectronic devices, lasers, light emitting diodes, solar cells, photoelectrochemical water splitting and hydrogen generation devices, photodetectors, integrated circuits, and transistors.05-16-2013
20130126888Edge Termination by Ion Implantation in GaN - An edge terminated semiconductor device is described including a GaN substrate; a doped GaN epitaxial layer grown on the GaN substrate including an ion-implanted insulation region, wherein the ion-implanted region has a resistivity that is at least 90% of maximum resistivity and a conductive layer, such as a Schottky metal layer, disposed over the GaN epitaxial layer, wherein the conductive layer overlaps a portion of the ion-implanted region. A Schottky diode is prepared using the Schottky contact structure.05-23-2013
20130126892P-Type Amorphous GaNAs Alloy as Low Resistant Ohmic Contact to P-Type Group III-Nitride Semiconductors - A new composition of matter is described, amorphous GaN05-23-2013
20130126895Gallium Nitride Devices with Vias - Semiconductor structures comprising a III-nitride (e.g., gallium nitride) material region and methods associated with such structures are provided. In some embodiments, the structures include an electrically conductive material (e.g., gold) separated from certain other region(s) of the structure (e.g., a silicon substrate) by a barrier material in order to limit, or prevent, undesirable reactions between the electrically conductive material and the other component(s) which can impair device performance. In certain embodiments, the electrically conductive material may be formed in a via. For example, the via can extend from a topside of the device to a backside so that the electrically conductive material connects a topside contact to a backside contact. The structures described herein may form the basis of a number of semiconductor devices including transistors (e.g., FET), Schottky diodes, light-emitting diodes and laser diodes, amongst others.05-23-2013
20130126887LIGHT EMITTING DIODE - An LED includes a seat and an LED chip. The seat includes a main body, a first electrode protruding upwardly from the main body, and a second electrode formed on the main body. The LED chip includes a substrate, a first semiconductor layer disposed on the substrate, a light-emitting layer disposed on the first semiconductor layer, a second semiconductor layer disposed on the light-emitting layer, and a third electrode fixed on the second semiconductor layer. The first electrode extends through the substrate and electrically connects with the first semiconductor layer, and the third electrode electrically connects with the second electrode via a wire.05-23-2013
20130126891MICRO LIGHT EMITTING DIODE - A micro light emitting diode (LED) and a method of forming an array of micro LEDs for transfer to a receiving substrate are described. The micro LED structure may include a micro p-n diode and a metallization layer, with the metallization layer between the micro p-n diode and a bonding layer. A conformal dielectric barrier layer may span sidewalls of the micro p-n diode. The micro LED structure and micro LED array may be picked up and transferred to a receiving substrate.05-23-2013
20130126893SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A nitride semiconductor layer formed from a nitride semiconductor is provided on at least one surface side of a semiconductor substrate. Impurity regions (a source region, a drain region, and the like) are provided on one surface side in the nitride semiconductor layer and contain an impurity of a first conductivity type. In addition, amorphous regions (a first amorphous region and a second amorphous region) are a part of the impurity regions and are located in a surface layer of the impurity regions. In addition, metallic layers (a source electrode and a drain electrode) come into contact with the amorphous regions (the first amorphous region and the second amorphous region).05-23-2013
20130126902SEMICONDUCTOR LIGHT EMITTING ELEMENT - A semiconductor light-emitting element according to the present invention includes: an n-type nitride semiconductor layer 05-23-2013
20130126897COMPOUND SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - An electrode (05-23-2013
20130126898GALLIUM NITRIDE COMPOUND SEMICONDUCTOR LIGHT EMITTING ELEMENT AND LIGHT SOURCE PROVIDED WITH SAID LIGHT EMITTING ELEMENT - In a gallium nitride based compound semiconductor light-emitting element including an active layer, the active layer includes a well layer 05-23-2013
20130126901SEMICONDUCTOR LIGHT-EMITTING ELEMENT - A semiconductor light-emitting element according to the present invention includes: an n-type nitride semiconductor layer 05-23-2013
20130134437METHOD FOR FORMING GALLIUM NITRIDE DEVICES WITH CONDUCTIVE REGIONS - Semiconductor structures comprising a III-nitride (e.g., gallium nitride) material region and methods associated with such structures are provided. In some embodiments, the structures include an electrically conductive material (e.g., gold) separated from certain other region(s) of the structure (e.g., a silicon substrate) by a barrier material in order to limit, or prevent, undesirable reactions between the electrically conductive material and the other component(s) which can impair device performance. In certain embodiments, the electrically conductive material may be formed in a via. For example, the via can extend from a topside of the device to a backside so that the electrically conductive material connects a topside contact to a backside contact. The structures described herein may form the basis of a number of semiconductor devices including transistors (e.g., FET), Schottky diodes, light-emitting diodes and laser diodes, amongst others.05-30-2013
20130134436METHOD FOR BONDING SEMICONDUCTOR SUBSTRATES - A method is provided for bonding a first substrate carrying a semiconductor device layer on its front surface to a second substrate. The method comprises producing the semiconductor device layer on the front surface of the first substrate, depositing a first metal bonding layer or a stack of metal layers on the first substrate, on top of the semiconductor device layer, depositing a second metal bonding layer or a stack of metal layers on the front surface of the second substrate, depositing a metal stress-compensation layer on the back side of the second substrate, thereafter establishing a metal bond between the first and second substrate, by bringing the first and second metal bonding layers or stacks of layers into mutual contact under conditions of mechanical pressure and temperature suitable for obtaining the metal bond, and removing the first substrate.05-30-2013
20130140578CIRCUIT STRUCTURE HAVING ISLANDS BETWEEN SOURCE AND DRAIN - A circuit structure includes a substrate, an unintentionally doped gallium nitride (UID GaN) layer over the substrate, a donor-supply layer over the UID GaN layer, a gate structure, a drain, and a source over the donor-supply layer. A number of islands are over the donor-supply layer between the gate structure and the drain. The gate structure disposed between the drain and the source. The gate structure is adjoins at least a portion of one of the islands and/or partially disposed over at least a portion of at least one of the islands.06-06-2013
20130140580Optoelectronic Component - An optoelectronic component can be used for mixing electromagnetic radiation having different wavelengths, in particular in the far field. The optoelectronic component includes a carrier. A first semiconductor chip has a first radiation exit surface for emitting electromagnetic radiation in a first spectral range is provided on the carrier and a second semiconductor chip as a second radiation exit surface for emitting electromagnetic radiation in a second spectral range is provided on the carrier. A diffusing layer is provided on the radiation exit surfaces of the semiconductor chips which face away from the carrier.06-06-2013
20130119393Vertical Gallium Nitride Schottky Diode - A vertical conduction nitride-based Schottky diode is formed using an insulating substrate which was lifted off after the diode device is encapsulated on the front side with a wafer level molding compound. The wafer level molding compound provides structural support on the front side of the diode device to allow the insulating substrate to be lifted off so that a conductive layer can be formed on the backside of the diode device as the cathode electrode. A vertical conduction nitride-based Schottky diode is thus realized. In another embodiment, a protection circuit for a vertical GaN Schottky diode employs a silicon-based vertical PN junction diode connected in parallel to the GaN Schottky diode to divert reverse bias avalanche current.05-16-2013
20130146890HIGH ELECTRON MOBILITY TRANSISTOR - A high electron mobility transistor (HEMT) according to example embodiments includes a first semiconductor layer, a second semiconductor layer on the first semiconductor layer, and a reverse diode gate structure on the second semiconductor layer. A source and a drain may be on at least one of the first semiconductor layer and the second semiconductor layer. A gate electrode may be on the reverse diode gate structure.06-13-2013
20130146893SIC CRYSTALLINE ON SI SUBSTRATES TO ALLOW INTEGRATION OF GAN AND SI ELECTRONICS - A silicon substrate with a GaN-based device and a Si-based device on the silicon substrate is provided. The silicon substrate includes the GaN-based device on a SiC crystalline region. The SiC crystalline region is formed in the silicon substrate. The silicon substrate also includes the Si-based device on a silicon region, and the silicon region is next to the SiC crystalline region on the silicon substrate.06-13-2013
20130146885Vertical GaN-Based Metal Insulator Semiconductor FET - A semiconductor structure includes a III-nitride substrate having a top surface and an opposing bottom surface and a first III-nitride layer of a first conductivity type coupled to the top surface of the III-nitride substrate. The semiconductor structure also includes a second III-nitride layer of a second conductivity type coupled to the first III-nitride layer along a vertical direction and a third III-nitride layer of a third conductivity type coupled to the second III-nitride layer along the vertical direction. The semiconductor structure further includes a first trench extending through a portion of the third III-nitride layer to the first III-nitride layer, a second trench extending through another portion of the third III-nitride layer to the second III-nitride layer, and a first metal layer coupled to the second and the third III-nitride layers.06-13-2013
20130146887DIODE FOR USE IN A SWITCHED MODE POWER SUPPLY - A tunable depletion diode is provided. Within this depletion diode, there is a depletion mode transistor that is coupled to the anode terminal at its gate and the cathode terminal at its drain. A diode is coupled between the source of the depletion mode transistor and the anode terminal, and a variable capacitor is coupled between the source of the depletion mode transistor and the anode terminal, where the capacitance of the variable capacitor is controls the reverse recovery time of the tunable depletion diode.06-13-2013
20130146888MONOLITHIC SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - Disclosed herein is a monolithic semiconductor device including: a substrate; a high electron mobility transistor (HEMT) structure that is a first device structure formed on the substrate; and a laterally diffused metal oxide field effect transistor (LDMOSFET) structure that is a second device structure formed to be connected with the HEMT structure on the substrate.The monolithic semiconductor device according to preferred embodiments of the present invention is a device having characteristics of a normally-off device while maintaining high current characteristics in a normally-on state, thereby improving high current and high voltage operation characteristics.06-13-2013
20130146889COMPOUND SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - An embodiment of a compound semiconductor device includes: a substrate; a nitride compound semiconductor stacked structure formed on or above the substrate; and a gate electrode, a source electrode and a drain electrode formed on or above the compound semiconductor stacked structure. A recess positioning between the gate electrode and the drain electrode in a plan view is formed at a surface of the compound semiconductor stacked structure.06-13-2013
20130146891ENHANCEMENT-MODE HFET CIRCUIT ARRANGEMENT HAVING HIGH POWER AND A HIGH THRESHOLD VOLTAGE - A circuit includes input drain, source and gate nodes. The circuit also includes a group III nitride enhancement-mode HFET having a source, drain and gate and a voltage shifter having a first terminal connected to the gate of the enhancement mode HFET at a common junction. The circuit also includes a load resistive element connected to the common junction. The drain of the enhancement-mode HFET serves as the input drain node, the source of the enhancement-mode HFET serves as the input source node and a second terminal of the voltage shifter serves as the input gate node.06-13-2013
20130146892METHOD FOR MANUFACTURING SUBSTRATE FOR SEMICONDUCTOR LIGHT EMITTING ELEMENT AND SEMICONDUCTOR LIGHT EMITTING ELEMENT USING THE SAME - A light emitting element having a recess-protrusion structure on a substrate is provided. A semiconductor light emitting element 06-13-2013
20110210338Efficient High Voltage Switching Circuits and Monolithic Integration of Same - A high voltage switching circuit includes first and second group III-V transistors, the second group III-V transistor having a greater breakdown voltage than the first group III-V transistor. The circuit further includes a silicon diode in a parallel arrangement with the first group III-V transistor, the parallel arrangement being in cascade with the second group III-V transistor. The circuit is effectively a three-terminal device, where a first terminal is coupled to a gate of the second III-V transistor, a source of the first III-V transistor, and an anode of the silicon diode. A second terminal is coupled to a gate of the first group III-V transistor, and a third terminal is coupled to a drain of the second group III-V transistor. The first group III-V transistor might be an enhancement mode transistor. The second group III-V transistor might be a depletion mode transistor. The first and second group III-V transistors can be GaN HEMTs.09-01-2011
20130126900SEMICONDUCTOR LIGHT-EMITTING DEVICE - Around a nitride-based semiconductor light-emitting element which has a polarization characteristic, a transparent encapsulating member which has a cylindrical shape is provided such that the symmetry plane of the cylindrical shape forms an angle of 25° to 65° with respect to the polarization direction of the nitride-based semiconductor light-emitting element.05-23-2013
20130126896III-V SEMICONDUCTOR STRUCTURES AND METHODS FOR FORMING THE SAME - Embodiments of the invention relate to methods of fabricating semiconductor structures, and to semiconductor structures fabricated by such methods. In some embodiments, the methods may be used to fabricate semiconductor structures of III-V materials, such as InGaN. A semiconductor layer is fabricated by growing sublayers using differing sets of growth conditions to improve the homogeneity of the resulting layer, to improve a surface roughness of the resulting layer, and/or to enable the layer to be grown to an increased thickness without the onset of strain relaxation.05-23-2013
20130126889Manufacturable Enhancement-Mode Group III-N HEMT with a Reverse Polarization Cap - An enhancement-mode group III-N high electron mobility transistor (HEMT) with a reverse polarization cap is formed in a method that utilizes a reverse polarization cap structure, such as an InGaN cap structure, to deplete the two-dimensional electron gas (2DEG) and form a normally off device, and a spacer layer that lies below the reverse polarization cap structure and above the barrier layer of the HEMT which allows the reverse polarization cap layer to be etched without etching into the barrier layer.05-23-2013
20080197359COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A compound semiconductor device has a buffer layer formed on a conductive SiC substrate, an AlxGa1-xN layer formed on the buffer layer in which an impurity for reducing carrier concentration from an unintentionally doped donor impurity is added and in which the Al composition x is 008-21-2008
20080197358WIDE-BANDGAP SEMICONDUCTOR DEVICES08-21-2008
20110220912Semi-insulating Group III Metal Nitride and Method of Manufacture - A large-area, high-purity, low-cost single crystal semi-insulating gallium nitride that is useful as substrates for fabricating GaN devices for electronic and/or optoelectronic applications is provided. The gallium nitride is formed by doping gallium nitride material during ammonothermal growth with a deep acceptor dopant species, e.g., Mn, Fe, Co, Ni, Cu, etc., to compensate donor species in the gallium nitride, and impart semi-insulating character to the gallium nitride.09-15-2011
20110227091SOLID-STATE IMAGING DEVICE, METHOD FOR MANUFACTURING SOLID-STATE IMAGING DEVICE, AND ELECTRONIC APPARATUS - A solid-state imaging device is provided with a pixel region in which a plurality of pixels including photoelectric conversion films are arrayed and pixel isolation portions are interposed between the plurality of pixels, wherein the photoelectric conversion film is a chalcopyrite-structure compound semiconductor composed of a copper-aluminum-gallium-indium-sulfur-selenium based mixed crystal or a copper-aluminum-gallium-indium-zinc-sulfur-selenium based mixed crystal and is disposed on a silicon substrate in such a way as to lattice-match the silicon substrate concerned, and the pixel isolation portion is formed from a compound semiconductor subjected to doping concentration control or composition control in such a way as to become a potential barrier between the photoelectric conversion films disposed in accordance with the plurality of pixels.09-22-2011
20110227089MULTILAYER DIFFUSION BARRIERS FOR WIDE BANDGAP SCHOTTKY BARRIER DEVICES - Semiconductor Schottky barrier devices include a wide bandgap semiconductor layer, a Schottky barrier metal layer on the wide bandgap semiconductor layer and forming a Schottky junction, a current spreading layer on the Schottky barrier metal layer remote from the wide bandgap semiconductor layer and two or more diffusion barrier layers between the current spreading layer and the Schottky barrier metal layer. The first diffusion barrier layer reduces mixing of the current spreading layer and the second diffusion barrier layer at temperatures of the Schottky junction above about 300° C. and the second diffusion barrier layer reduces mixing of the first diffusion barrier layer and the Schottky barrier metal layer at the temperatures of the Schottky junction above about 300° C.09-22-2011
20110241018FABRICATING A GALLIUM NITRIDE DEVICE WITH A DIAMOND LAYER - In one aspect, a method includes fabricating a device. The device includes a gallium nitride (GaN) layer, a diamond layer disposed on the GaN layer and a gate structure disposed in contact with the GaN layer and the diamond layer.10-06-2011
20110241017FIELD EFFECT TRANSISTOR - A field effect transistor includes: a buffer layer that is formed on a substrate; a high resistance layer or a foundation layer that is formed on the buffer layer; a carbon-containing carrier concentration controlling layer that is formed on the high resistance layer or the foundation layer; a carrier traveling layer that is formed on the carrier concentration controlling layer; a carrier supplying layer that is formed on the carrier traveling layer; a recess that is formed from the carrier supplying layer up to a predetermined depth; source/drain electrodes that are formed on the carrier supplying layer with the recess intervening therebetween; a gate insulating film that is formed on the carrier supplying layer so as to cover the recess; and a gate electrode that is formed on the gate insulating film in the recess10-06-2011
20130146886Vertical GaN JFET with Gate Source Electrodes on Regrown Gate - A semiconductor structure includes a GaN substrate with a first surface and a second surface. The GaN substrate is characterized by a first conductivity type and a first dopant concentration. A first electrode is electrically coupled to the second surface of the GaN substrate. The semiconductor structure further includes a first GaN epitaxial layer of the first conductivity type coupled to the first surface of the GaN substrate and a second GaN layer of a second conductivity type coupled to the first GaN epitaxial layer. The first GaN epitaxial layer comprises a channel region. The second GaN epitaxial layer comprises a gate region and an edge termination structure. A second electrode coupled to the gate region and a third electrode coupled to the channel region are both disposed within the edge termination structure.06-13-2013
20130126886GAN-BASED SCHOTTKY BARRIER DIODE WITH ALGAN SURFACE LAYER - A method of fabricating a Schottky diode using gallium nitride (GaN) materials includes providing an n-type GaN substrate having a first surface and a second surface. The second surface opposes the first surface. The method also includes forming an ohmic metal contact electrically coupled to the first surface of the n-type GaN substrate and forming an n-type GaN epitaxial layer coupled to the second surface of the n-type GaN substrate. The method further includes forming an n-type aluminum gallium nitride (AlGaN) surface layer coupled to the n-type GaN epitaxial layer and forming a Schottky contact electrically coupled to the n-type AlGaN surface layer.05-23-2013
20130126885METHOD AND SYSTEM FOR FABRICATING FLOATING GUARD RINGS IN GAN MATERIALS - A method for fabricating an edge termination structure includes providing a substrate having a first surface and a second surface and a first conductivity type, forming a first GaN epitaxial layer of the first conductivity type coupled to the first surface of the substrate, and forming a second GaN epitaxial layer of a second conductivity type opposite to the first conductivity type. The second GaN epitaxial layer is coupled to the first GaN epitaxial layer. The method also includes implanting ions into a first region of the second GaN epitaxial layer to electrically isolate a second region of the second GaN epitaxial layer from a third region of the second GaN epitaxial layer. The method further includes forming an active device coupled to the second region of the second GaN epitaxial layer and forming the edge termination structure coupled to the third region of the second GaN epitaxial layer.05-23-2013
20130126884ALUMINUM GALLIUM NITRIDE ETCH STOP LAYER FOR GALLIUM NITRIDE BASES DEVICES - A semiconductor structure includes a III-nitride substrate with a first side and a second side opposing the first side. The III-nitride substrate is characterized by a first conductivity type and a first dopant concentration. The semiconductor structure also includes a III-nitride epitaxial layer of the first conductivity type coupled to the first surface of the III-nitride substrate, and a first metallic structure electrically coupled to the second surface of the III-nitride substrate. The semiconductor structure further includes an AlGaN epitaxial layer coupled to the III-nitride epitaxial layer of the first conductivity type, and a III-nitride epitaxial structure of a second conductivity type coupled to the AlGaN epitaxial layer. The III-nitride epitaxial structure comprises at least one edge termination structure.05-23-2013
20110248280TRANSISTOR HAVING THERMO ELECTRON COOLING - A semiconductor structure having a transistor and a thermo electronic structure. The transistor has a control electrode for controlling a flow of carriers through a semiconductor layer between a pair of electrodes. The thermo electronic structure has a first portion disposed on at least one of the pair of electrodes and a second portion disposed over a region of the semiconductor layer proximate the control electrode between the control electrode and said at least one of the pair of electrode. The thermo electronic structure extends from the first portion to the second portion for removing heat generated heat from said region in the semiconductor layer.10-13-2011
20130092948SEMICONDUCTOR DEVICE AND FABRICATION METHOD OF THE SEMICONDUCTOR DEVICE - The semiconductor device having flip chip structure includes: an insulating substrate; a signal wiring electrode disposed on the insulating substrate; a power wiring electrode disposed on the insulating substrate or disposed so as to pass through the insulating substrate; a semiconductor chip disposed in flip chip configuration on the insulating substrate and comprising a semiconductor substrate, a source pad electrode and a gate pad electrode disposed on a surface of the semiconductor substrate, and a drain pad electrode disposed on a back side surface of the semiconductor substrate; agate connector disposed on the gate pad electrode; and a source connector disposed on the source pad electrode. The gate connector, the gate pad electrode and the signal wiring electrode are bonded, and the source connector, the source pad electrode and the power wiring electrode are bonded, by using solid phase diffusion bonding.04-18-2013
20100308339LIGHT EMITTING DEVICE, LIGHT EMITTING DEVICE PACKAGE AND LIGHTING SYSTEM INCLUDING THE SAME - Provided are a light emitting device (LED), a light emitting device package and a lighting system including the same. The LED includes a light emitting structure having a second semiconductor layer of a second conductivity type, an active layer on the second semiconductor layer, and a first semiconductor layer of a first conductivity type on the active layer, a current blocking layer below the second semiconductor layer, a second electrode below the second semiconductor layer, and a first electrode on the first semiconductor layer. The current blocking layer includes a non second conductive region.12-09-2010
20120273795SEMICONDUCTOR DEVICE - Provided is a semiconductor device comprising a back barrier layer that is formed by a group III-V compound semiconductor above a substrate; a channel layer that is formed of a group III-V compound semiconductor having less bandgap energy than the back barrier layer, is formed on the back barrier layer, and includes a recessed portion formed in at least a portion of the channel layer above the back barrier layer to be thinner than other portions of the channel layer; a first electrode that is in ohmic contact with the channel layer; and a second electrode formed at least above the recessed portion of the channel layer.11-01-2012
20120273793SEMICONDUCTOR LIGHT EMITTING DEVICE - According to one embodiment, a semiconductor light emitting device includes a substrate, a first electrode, a first conductivity type layer, a light emitting layer, a second conductivity type layer and a second electrode. The first conductivity type layer includes a first contact layer, a window layer having a lower impurity concentration than the first contact layer and a first cladding layer. The second conductivity type layer includes a second cladding layer, a current spreading layer and a second contact layer. The second electrode includes a narrow-line region on the second contact layer and a pad region electrically connected to the narrow-line region. Band gap energies of the first contact and window layers are larger than that of the light emitting layer. The first contact layer is provided selectively between the window layer and the first electrode and without overlapping the second contact layer as viewed from above.11-01-2012
20130187169SYSTEMS AND METHODS FOR DEPOSITING MATERIALS ON EITHER SIDE OF A FREESTANDING FILM USING SELECTIVE THERMALLY-ASSISTED CHEMICAL VAPOR DEPOSITION (STA-CVD), AND STRUCTURES FORMED USING SAME - Embodiments of the present invention provide systems and methods for depositing materials on either side of a freestanding film using selectively thermally-assisted chemical vapor deposition (STA-CVD), and structures formed using same. A freestanding film, which is suspended over a cavity defined in a substrate, is exposed to a fluidic CVD precursor that reacts to form a solid material when exposed to heat. The freestanding film is then selectively heated in the presence of the precursor. The CVD precursor preferentially deposits on the surface(s) of the freestanding film.07-25-2013
20130187170METHOD FOR PRODUCING ALUMINUM NITRIDE CRYSTALS - Provided is a method for producing inexpensive and high-quality aluminum nitride crystals. Gas containing N atoms is introduced into a melt of a Ga—Al alloy, whereby aluminum nitride crystals are made to epitaxially grow on a seed crystal substrate in the melt of the Ga—Al alloy. A growth temperature of aluminum nitride crystals is set at not less than 1000 degrees C. and not more than 1500 degrees C., thereby allowing GaN to be decomposed into Ga metal and nitrogen gas.07-25-2013
20110233559FIELD-EFFECT TRANSISTOR - A field-effect transistor (FET) in which a gate electrode is located between a source electrode formed on one side of the gate electrode and a drain electrode formed on the other side, a source ohmic contact is formed under the source electrode and a drain ohmic contact is formed under the drain electrode. In the FET, the rise in the channel temperature is suppressed, the parasitic capacitance with a substrate is decreased, and the temperature dependence of drain efficiency is reduced, so that highly efficient operation can be achieved at high temperatures. The drain electrode is divided into a plurality of drain sub-electrodes spaced from each other and an insulating region is formed between the drain ohmic contacts formed under the drain sub-electrodes.09-29-2011
20110233558LIGHT-EMITTING DEVICE, LIGHT-EMITTING DEVICE PACKAGE AND LIGHTING SYSTEM - Disclosed is a light-emitting device including: a support member; and a light-emitting structure on the support member, the light-emitting structure including a first semiconductor layer, at least one intermediate layer, an active layer and a second semiconductor layer, wherein the intermediate layer is on at least one of upper and lower regions of the active layer and comprises at least four layers, wherein the layers have different band gaps, and wherein, among the layers, a layer having the largest band gap contacts a layer having the smallest band gap. Based on this configuration, it is possible to reduce crystal defects and improve brightness of the light-emitting device through effective diffusion of current.09-29-2011
20110254012Ultra high voltage GaN ESD protection device - In an ultra high voltage lateral GaN structure having a 2DEG region extending between two terminals, an isolation region is provided between the two terminals to provide for reversible snapback.10-20-2011
20110272706LIGHT EMITTING DIODE AND METHOD FOR FABRICATING THE SAME - A light emitting diode and a method for fabricating the same are provided. The light emitting diode includes: a transparent substrate; a semiconductor material layer formed on the top surface of a substrate with an active layer generating light; and a fluorescent layer formed on the back surface of the substrate with controlled varied thicknesses. The ratio of light whose wavelength is shifted while propagating through the fluorescent layer and the original light generated in the active layer can be controlled by adjusting the thickness of the fluorescent layer, to emit desirable homogeneous white light from the light emitting diode.11-10-2011
20110272705Interdigitated Conductive Support for GaN Semiconductor Die - A GaN die having a plurality of parallel alternating and closely spaced source and drain strips is contacted by parallel coplanar comb-shaped fingers of source and drain pads. A plurality of enlarged area coplanar spaced gate pads having respective fingers contacting the gate contact of the die. The pads may be elements of a lead frame, or conductive areas on an insulation substrate. Other semiconductor die can be mounted on the pads and connected in predetermined circuit arrangements with the GaN die.11-10-2011
20110272704COMPOUND SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - An AlN layer (11-10-2011
20110272703SEMICONDUCTOR DEVICE, LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - Disclosed are a semiconductor device, a light emitting device and a method for manufacturing the same. The semiconductor device includes a substrate, a plurality of rods disposed on the substrate, a plurality of particles disposed between the rods and on the substrate, and a first semiconductor layer disposed on the rods. The method for manufacturing the semiconductor device includes preparing a substrate, disposing a plurality of first particles on the substrate, and forming a plurality of rods by etching a portion of the substrate by using the first particles as an etch mask. The semiconductor device effectively reflects in an upward direction light by the above particles, so that light efficiency is improved. The rods are easily formed by using the first particles.11-10-2011
20130153917INGAN OHMIC SOURCE CONTACTS FOR VERTICAL POWER DEVICES - A vertical III-nitride field effect transistor includes a drain comprising a first III-nitride material, a drain contact electrically coupled to the drain, and a drift region comprising a second III-nitride material coupled to the drain and disposed adjacent to the drain along a vertical direction. The field effect transistor also includes a channel region comprising a third III-nitride material coupled to the drift region, a gate region at least partially surrounding the channel region, and a gate contact electrically coupled to the gate region. The field effect transistor further includes a source coupled to the channel region. The source includes a GaN-layer coupled to an InGaN layer. The channel region is disposed between the drain and the source along the vertical direction such that current flow during operation of the vertical III-nitride field effect transistor is along the vertical direction.06-20-2013
20130153918REO-Si TEMPLATE WITH INTEGRATED REO LAYERS FOR LIGHT EMISSION - A III-N on silicon LED constructed to emit light in the visible range includes a layer of single crystal III-N with a light emitting diode formed therein and designed to emit light at a first wavelength through a lower surface, a REO-Si template mated to the layer of single crystal III-N and designed to approximately crystal lattice match a silicon substrate, and a light emission layer of rare earth oxide selected to receive and absorb light at the first wavelength, up-convert the absorbed light, and re-emit light at a second wavelength in the visible range. The lower surface of the REO-Si template is either mated to the upper surface of a crystalline silicon substrate with the light emission layer integrated into the REO-Si template or mated to an upper surface of the light emission layer with a lower surface of the light emission layer mated to the crystalline silicon substrate.06-20-2013
20130153920SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING SAME - According to an embodiment, a semiconductor light emitting device includes a light emitting body including a semiconductor light emitting layer, a support substrate supporting the light emitting body, and a bonding layer provided between the light emitting body and the support substrate, the bonding layer bonding the light emitting body and the support substrate together. The device also includes a first barrier metal layer provided between the light emitting body and the bonding layer, and an electrode provided between the light emitting body and the first barrier metal layer. The first barrier layer includes a first layer made of nickel and a second layer made of a metal having a smaller linear expansion coefficient than nickel, and the first layer and the second layer are alternately disposed in a multiple-layer structure. The electrode is electrically connected to the light emitting body.06-20-2013
20130153922SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD OF FABRICATING SEMICONDUCTOR LIGHT EMITTING DEVICE - A semiconductor light emitting device has a light emitting element, a first electrode layer, a second electrode layer, a seed electrode layer and a plated layer. The light emitting element has a nitride-based III-V compound semiconductor on a substrate and a light extraction surface. The first electrode layer is provided on the light extraction surface. The second electrode layer is provided on a surface opposite to the light extraction surface. The seed electrode layer is configured to cover the entire surface of the second electrode layer. The plated layer is provided on the seed electrode layer. The light emitting element has a light emitting layer, first conductive type semiconductor layer, and second conductive type semiconductor layer, and has a forward tapered shape of a width which gradually narrows in order of the second conductive type semiconductor layer, the light emitting layer and the first conductive type semiconductor layer.06-20-2013
20130153923ENHANCEMENT MODE III-NITRIDE DEVICE AND METHOD FOR MANUFACTURING THEREOF - Enhancement mode III-nitride HEMT and method for manufacturing an enhancement mode III-nitride HEMT are disclosed. In one aspect, the method includes providing a substrate having a stack of layers on the substrate, each layer including a III-nitride material, and a passivation layer having high temperature silicon nitride overlying and in contact with an upper layer of the stack of III-nitride layers, wherein the HT silicon nitride is formed by MOCVD or LPCVD or any equivalent technique at a temperature higher than about 450° C. The method also includes forming a recessed gate region by removing the passivation layer only in the gate region, thereby exposing the underlying upper layer. The method also includes forming a p-doped GaN layer at least in the recessed gate region, thereby filling at least partially the recessed gate region, and forming a gate contact and source/drain contacts.06-20-2013
20130153919III-V Semiconductor Devices with Buried Contacts - A semiconductor device such as a diode or transistor includes a semiconductor substrate, a first region of III-V semiconductor material on the semiconductor substrate and a second region of III-V semiconductor material on the first region. The second region is spaced apart from the semiconductor substrate by the first region. The second region is of a different composition than the first region. The semiconductor device further includes a buried contact extending from the semiconductor substrate to the second region through the first region. The buried contact electrically connects the second region to the semiconductor substrate.06-20-2013
20120280248SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided are a semiconductor light emitting device and a method of manufacturing the same. The semiconductor light emitting device comprises a first conductive type semiconductor layer, an active layer, a first thin insulating layer, and a second conductive type semiconductor layer. The active layer is formed on the first conductive type semiconductor layer. The first thin insulating layer is formed on the active layer. The second conductive type semiconductor layer is formed on the thin insulating layer.11-08-2012
20120280244High Electron Mobility Transistors And Methods Of Manufacturing The Same - High electron mobility transistors (HEMTs) and methods of manufacturing the same. A HEMT may include a channel layer and a channel supply layer, and the channel supply layer may be a multilayer structure. The channel supply layer may include an etch stop layer and an upper layer on the etch stop layer. A recess region may be in the upper layer. The recess region may be a region recessed to an interface between the upper layer and the etch stop layer. A gate electrode may be on the recess region.11-08-2012
20110284865HETEROJUNCTION FIELD EFFECT TRANSISTOR, METHOD FOR PRODUCING HETEROJUNCTION FIELD EFFECT TRANSISTOR, AND ELECTRONIC DEVICE - A heterojunction filed effect transistor with a low access resistance, a low on resistance, and the like, a method for producing a heterojunction filed effect transistor and an electron device are provided. In the heterojunction field effect transistor, an electron transit layer 11-24-2011
20130119402LIGHT EMITTING DEVICE - Disclosed is a method for fabricating a light emitting device. The method includes forming an oxide including gallium aluminum over a gallium oxide substrate, forming a nitride including gallium aluminum over the oxide including gallium aluminum and forming a light emitting structure over the nitride including gallium aluminum.05-16-2013
20130119399METHOD FOR TESTING GROUP III-NITRIDE WAFERS AND GROUP III-NITRIDE WAFERS WITH TEST DATA - The present invention discloses a new testing method of group III-nitride wafers. By utilizing the ammonothermal method, GaN or other Group III-nitride wafers can be obtained by slicing the bulk GaN ingots. Since these wafers originate from the same ingot, these wafers have similar properties/qualities. Therefore, properties of wafers sliced from an ingot can be estimated from measurement data obtained from selected number of wafers sliced from the same ingot or an ingot before slicing. These estimated properties can be used for product certificate of untested wafers. This scheme can reduce a significant amount of time, labor and cost related to quality control.05-16-2013
20130119396TWO-TERMINAL SWITCHING DEVICES AND THEIR METHODS OF FABRICATION - Two-terminal switching devices characterized by high on/off current ratios and by high breakdown voltage are provided. These devices can be employed as switches in the driving circuits of active matrix displays, e.g., in electrophoretic, rotating element and liquid crystal displays. The switching devices include two electrodes, and a layer of a broad band semiconducting material residing between the electrodes. According to one example, the cathode comprises a metal having a low work function, the anode comprises an organic material having a p+ or p++ type of conductivity, and the broad band semiconductor comprises a metal oxide. The work function difference between the cathode and the anode material is preferably at least about 0.6 eV. The on/off current ratios of at least 10,000 over a voltage range of about 15 V can be achieved. The devices can be formed, if desired, on flexible polymeric substrates having low melting points.05-16-2013
20110303924LIGHT-EMITTING DEVICE AND PROJECTOR - A light-emitting device includes a first layer, a second layer, and a semiconductor body interposed between the first and second layers, wherein the semiconductor body has a first fine-wall-shape member, a second fine-wall-shape member, and a semiconductor member interposed between the first and second fine-wall-shape members, the first and second fine-wall-shape members have a third layer, a fourth layer, and a fifth layer interposed between the third and fourth layers, the fifth layer is a layer that generates light and guides the light, the third and fourth layers are layers that guide the light generated in the fifth layer, and the first and second layers are layers that suppress leakage of the light generated in the fifth layer.12-15-2011
20110309374Fast thermal annealing of GaN LEDs - Methods of performing fast thermal annealing in forming GaN light-emitting diodes (LEDs) are disclosed, as are GaN LEDs formed using fast thermal annealing having a time duration of 10 seconds or faster. An exemplary method includes forming a GaN multilayer structure having a n-GaN layer and a p-GaN layer that sandwich an active layer. The method includes performing fast thermal annealing of the p-GaN layer using either a laser or a flash lamp. The method further includes forming a transparent conducting layer atop the GaN multilayer structure, and adding a p-contact to the transparent conducting layer and a n-contact to the n-GaN layer. The resultant GaN LEDs have enhanced output power, lower turn-on voltage and reduced series resistance.12-22-2011
20110309373Singulation Method and Resulting Device of Thick Gallium and Nitrogen Containing Substrates - A method for singulation of thick GaN wafers (e.g., 300-400 um) through the use of a double-side laser-scribe process. In a preferred embodiment, the patterned GaN substrate is processed using a laser-scribe on each side of the substrate to form scribe lines. The scribe lines are aligned to each other. In a preferred embodiment, the substrate has not been subjected to a thinning or polishing process for reducing its thickness.12-22-2011
20110309372ENHANCEMENT-MODE HFET CIRCUIT ARRANGEMENT HAVING HIGH POWER AND A HIGH THRESHOLD VOLTAGE - A circuit includes input drain, source and gate nodes. The circuit also includes a group III nitride enhancement-mode HFET having a source, drain and gate and a voltage shifter having a first terminal connected to the gate of the enhancement mode HFET at a common junction. The circuit also includes a load resistive element connected to the common junction. The drain of the enhancement-mode HFET serves as the input drain node, the source of the enhancement-mode HFET serves as the input source node and a second terminal of the voltage shifter serves as the input gate node.12-22-2011
20110309371SCHOTTKY DIODE STRUCTURE AND METHOD FOR FABRICATING THE SAME - A Schottky diode structure and a method for fabricating the same, which are based on the principle of charge compensation, wherein a P-type gallium nitride layer is added to a Schottky diode structure, and wherein the PN junction of the P-type gallium nitride layer and the N-type gallium nitride layer decreases the non-uniformity of the surface electric field distribution, whereby the breakdown voltage of the element is raised.12-22-2011
20130187168GaN-CONTAINING SEMICONDUCTOR LIGHT EMITTING DEVICE - A GaN-containing semiconductor light emitting device includes: an n-type semiconductor layer formed of GaN-containing semiconductor, an active layer formed on the n-type semiconductor layer, formed of GaN-containing semiconductor, and having a multiple quantum well structure including a plurality of barrier layers and well layers stacked alternately, and a p-type semiconductor layer formed on the active layer and formed of GaN-containing semiconductor, wherein: the barrier layers comprise: a first barrier layer disposed nearest to the n-type semiconductor layer among the barrier layers and formed of a GaN/AlGaN layer, and second barrier layers disposed nearer to the p-type semiconductor layer than the first barrier layer and including an InGaN/GaN layer which has a layered structure of a InGaN sublayer and a GaN sublayer; and the well layers are each formed of an InGaN layer having a narrower band gap than that in the InGaN sublayer.07-25-2013
20090039356PLANAR NONPOLAR M-PLANE GROUP III-NITRIDE FILMS GROWN ON MISCUT SUBSTRATES - A nonpolar III-nitride film grown on a miscut angle of a substrate. The miscut angle towards the <000-1> direction is 0.75° or greater miscut and less than 27° miscut towards the <000-1> direction. Surface undulations are suppressed and may comprise faceted pyramids. A device fabricated using the film is also disclosed. A nonpolar III-nitride film having a smooth surface morphology fabricated using a method comprising selecting a miscut angle of a substrate upon which the nonpolar III-nitride films are grown in order to suppress surface undulations of the nonpolar III-nitride films. A nonpolar III-nitride-based device grown on a film having a smooth surface morphology grown on a miscut angle of a substrate which the nonpolar III-nitride films are grown. The miscut angle may also be selected to achieve long wavelength light emission from the nonpolar film.02-12-2009
20110315999Gallium and Nitrogen Containing Triangular or Diamond-shaped Configuration for Optical Devices - A gallium and nitrogen containing optical device has a base region and no more than three major planar side regions configured in a triangular arrangement provided from the base region.12-29-2011
20110315997GaN Substrate and Method of Its Manufacture, Method of Manufacturing GaN Layer-Bonded Substrate, and Method of Manufacturing Semiconductor Device - The present invention makes available a GaN substrate, and a method of its manufacture, that, with minimal machining allowances, facilitates consistent machining, and makes available a method of manufacturing a GaN layer-bonded substrate, and a semiconductor device, utilizing the GaN substrate. A GaN substrate (12-29-2011
20120012858SEMICONDUCTOR DEVICE - A semiconductor device includes source fingers and drain fingers provided on an active region of a nitride semiconductor layer alternately, gate fingers having a side edge and a distal edge, a first insulation film provided on the nitride semiconductor layer and covers a top face, the side and distal edges of the gate fingers, field plates provided on the first insulation film between the gate fingers and the drain fingers, a minimum distance between the side face of the first insulation film located on the side edge of the gate fingers and the field plate being at least 100 nm, and field plate interconnections provided on the first insulation film and located outside of the active region and electrically connected with the source fingers and the field plates, a minimum distance between the side face of the first insulation film located on the distal edge of the gate fingers and the field plate interconnections being at least 100 nm.01-19-2012
20130193441Semiconductor Substrates Using Bandgap Material Between III-V Channel Material and Insulator Layer - Improved semiconductor substrates are provided that employ a wide bandgap material between the channel and the insulator. A semiconductor substrate comprises a channel layer comprised of a III-V material; an insulator layer; and a wide bandgap material between the channel layer and the insulator layer, wherein a conduction band offset (ΔE08-01-2013
20120018736GROUP III NITRIDE SUBSTRATE, SEMICONDUCTOR DEVICE COMPRISING THE SAME, AND METHOD FOR PRODUCING SURFACE-TREATED GROUP III NITRIDE SUBSTRATE - A group III nitride substrate in one embodiment has a surface layer. The surface layer contains 3 at. % to 25 at. % of carbon and 5×1001-26-2012
20120018735SEMICONDUCTOR DEVICE - A semiconductor device includes a source electrode and a drain electrode formed on an active region of the semiconductor layer, a gate electrode formed on the active region of the semiconductor layer, a first insulating film formed on the semiconductor layer and covering the gate electrode, the first insulating film having a step portion following a shape of the gate electrode, a first field plate formed on the insulating film and located between the gate electrode and the drain electrode and separated from the step portion, a second insulating film formed on the first insulating film to cover the step portion and the first field plate, and a shield electrode formed on the second insulating film, the shield electrode extending from a portion located above the first field plate and a portion located above the gate electrode.01-26-2012
20120018734Light-emitting devices and methods of manufacturing the same - Example embodiments are directed to light-emitting devices (LEDs) and methods of manufacturing the same. The LED includes a first semiconductor layer; a second semiconductor layer; an active layer formed between the first and second semiconductor layers; and an emission pattern layer including a plurality of layers on the first semiconductor layer, the emission pattern including an emission pattern for externally emitting light generated from the active layer.01-26-2012
20130193442Light Emitting Device And Method For Manufacturing The Same - Provided are a light emitting device and a method for manufacturing the same. The light emitting device comprises a first conductive type semiconductor layer, an active layer, a second conductive type semiconductor layer, and a light extraction layer. The active layer is formed on the first conductive type semiconductor layer. The second conductive type semiconductor layer is formed on the active layer. The light extraction layer is formed on the second conductive type semiconductor layer. The light extraction layer has a refractive index smaller than or equal to a refractive index of the second conductive type semiconductor layer.08-01-2013
20090261345METHOD FOR MANUFACTURING COMPLIANT SUBSTRATE, COMPLIANT SUBSTRATE MANUFACTURED THEREBY, GALLIUM NITRIDE BASED COMPOUND SEMICONDUCTOR DEVICE HAVING THE COMPLIANT SUBSTRATE AND MANUFACTURING METHOD THEREOF - A compliant substrate having a reduced stress, a method for manufacturing the same having a reduced manufacturing time, a gallium nitride based compound semiconductor device including the compliant substrate and a method for manufacturing the same are disclosed. The compliant substrate is manufactured by heating a substrate and a group III metal including at least one of an aluminum, a gallium and an indium, and a chloride based compound generated by introducing a HCl gas to the melted group III metal reacts with a NH10-22-2009
20120292635COMPOSITE SEMICONDUCTOR DEVICE - This composite semiconductor device has a normally-on first field effect transistor and a normally-off second field effect transistor connected in series between first and second terminals, gates of the first and second field effect transistors being connected to second and third terminals, respectively, and N diodes being connected in series in a forward direction between a drain and a source of the second field effect transistor. Therefore, a drain-source voltage (Vds) of the second field effect transistor can be restricted to a voltage not higher than a withstand voltage of the second field effect transistor.11-22-2012
20090242897INDIUM GALLIUM NITRIDE-BASED OHMIC CONTACT LAYERS FOR GALLIUM NITRIDE-BASED DEVICES - Light emitting devices include a gallium nitride-based epitaxial structure that includes an active light emitting region and a gallium nitride-based outer layer, for example gallium nitride. A indium nitride-based layer, such as indium gallium nitride, is provided directly on the outer layer. A reflective metal layer or a transparent conductive oxide layer is provided directly on the indium gallium nitride layer opposite the outer layer. The indium gallium nitride layer forms a direct ohmic contact with the outer layer. An ohmic metal layer need not be used. Related fabrication methods are also disclosed.10-01-2009
20130200387NITRIDE BASED HETEROJUNCTION SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A nitride based heterojunction semiconductor device includes a GaN layer on a substrate, an Al-doped GaN layer on the GaN layer, an AlGaN layer on the Al-doped GaN layer, a source electrode, a gate electrode, and a drain electrode on the AlGaN layer, a first field plate on the AlGaN layer, the first field plate being in contact with the gate electrode, and a second field plate on the AlGaN layer, the second field plate being separated from the first field plate by a distance.08-08-2013
20130200388NITRIDE BASED HETEROJUNCTION SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A nitride based heterojunction semiconductor device includes a gallium nitride (GaN) layer disposed on a substrate, an aluminum (Al)-doped GaN layer disposed on the GaN layer, a Schottky electrode disposed in a first area on the Al-doped GaN layer, an AlGaN layer disposed in a second area on the Al-doped GaN layer, and an ohmic electrode disposed on the AlGaN layer. The first area is different from the second area.08-08-2013
20130200389NITRIDE BASED HETEROJUNCTION SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A nitride based heterojunction semiconductor device includes a gallium nitride (GaN) layer disposed on a substrate, an aluminum (Al)-doped GaN layer disposed on the GaN layer, an AlGaN layer disposed on the Al-doped GaN layer, an ion-implanted layer disposed in an area on the AlGaN layer, excluding a first area and a second area.08-08-2013
20130200390SEMICONDUCTOR LIGHT-EMITTING DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor light-emitting device includes an n-type semiconductor layer including a nitride semiconductor, a p-type semiconductor layer including a nitride semiconductor, a light-emitting portion and a stacked body. The light-emitting portion is provided between the n-type and p-type semiconductor layers and includes a barrier layer and a well layer. The well layer is stacked with the barrier layer. The stacked body is provided between the light-emitting portion and the n-type semiconductor layer and includes a first layer and a second layer. The second layer is stacked with the first layer. Average In composition ratio of the stacked body is higher than 0.4 times average In composition ratio of the light-emitting portion. The layer thickness t08-08-2013
20130200391GALLIUM NITRIDE BASED STRUCTURES WITH EMBEDDED VOIDS AND METHODS FOR THEIR FABRICATION - A gallium nitride-based structure includes a substrate, a first layer of gallium nitride disposed on a growth surface of the substrate, and a second gallium nitride layer disposed on the first gallium nitride layer. The first layer includes a region in which a plurality of voids is dispersed. The second layer has a lower defect density than the gallium nitride of the interfacial region. The gallium nitride-based structure is fabricated by depositing GaN on the growth surface to form the first layer, forming a plurality of gallium nitride nanowires by removing gallium nitride from the first layer, and growing additional GaN from facets of the nanowires. Gallium nitride crystals growing from neighboring facets coalesce to form a continuous second layer, below which the voids are dispersed in the first layer. The voids serve as sinks or traps for crystallographic defects, and also as expansion joints that ameliorate thermal mismatch between the Ga.N and the underlying substrate. The voids also provide improved light transmission properties in optoelectronic applications.08-08-2013
20120068186Electronic Device - An electronic device includes a carrier, a plurality of pins, and an electronic circuit that includes a first semiconductor chip and a second semiconductor chip. The first semiconductor chip is attached to the carrier and the second semiconductor chip is attached to one of the plurality of pins.03-22-2012
20120074426FIELD-EFFECT TRANSISTOR - A field-effect transistor includes a carrier transport layer made of nitride semiconductor, a gate electrode having first and second sidewall surfaces on first and second sides, respectively, an insulating film formed directly on the gate electrode to cover at least one of the first and second sidewall surfaces, first and second ohmic electrodes formed on the first and second sides, respectively, a passivation film including a first portion extending from the first ohmic electrode toward the gate electrode to cover a surface area between the first ohmic electrode and the gate electrode and a second portion extending from the second ohmic electrode toward the gate electrode to cover a surface area between the second ohmic electrode and the gate electrode, wherein the insulating film is in direct contact with at least the first and second passivation film portions, and has a composition different from that of the passivation film.03-29-2012
20130207120Power Device with Solderable Front Metal - Some exemplary embodiments of a III-nitride power device including a HEMT with multiple interconnect metal layers and a solderable front metal structure using solder bars for external circuit connections have been disclosed. The solderable front metal structure may comprise a tri-metal such as TiNiAg, and may be configured to expose source and drain contacts of the HEMT as alternating elongated digits or bars. Additionally, a single package may integrate multiple such HEMTs wherein the front metal structures expose alternating interdigitated source and drain contacts, which may be advantageous for DC-DC power conversion circuit designs using III-nitride devices. By using solder bars for external circuit connections, lateral conduction is enabled, thereby advantageously reducing device Rdson.08-15-2013
20120086017HETEROGENEOUS SUBSTRATE, NITRIDE-BASED SEMICONDUCTOR DEVICE USING SAME, AND MANUFACTURING METHOD THEREOF - Provided are a heterogeneous substrate, a nitride-based semiconductor device using the same, and a manufacturing method thereof to form a high-quality non-polar or semi-polar nitride layer on a non-polar or semi-polar plane of the heterogeneous substrate by adjusting a crystal growth mode. A base substrate having one of a non-polar plane and a semi-polar plane is prepared, and a nitride-based nucleation layer is formed on the plane of the base substrate. A first buffer layer is grown faster in the vertical direction than in the lateral direction on the nucleation layer. A lateral growth layer is grown faster in the lateral direction than in the vertical direction on the first buffer layer. A second buffer layer is formed on the lateral growth layer. A silicon nitride layer having a plurality of holes may be formed between the lateral growth layer on the first buffer layer and the second buffer layer.04-12-2012
20120086016GROUP III NITRIDE SEMICONDUCTOR AND GROUP III NITRIDE SEMICONDUCTOR STRUCTURE - There is provided a surface treatment method of a group III nitride semiconductor including: providing a group III nitride semiconductor including a first surface having a group III polarity and a second surface opposing the first surface and having a nitrogen polarity; and irradiating a laser beam onto the second surface to change the nitrogen polarity of the second surface to the group III polarity.04-12-2012
20120086015GROUP III NITRIDE SEMICONDUCTOR DEVICE, EPITAXIAL SUBSTRATE, AND METHOD OF FABRICATING GROUP III NITRIDE SEMICONDUCTOR DEVICE - A group III nitride semiconductor device having a gallium nitride based semiconductor film with an excellent surface morphology is provided. A group III nitride optical semiconductor device includes a group III nitride semiconductor supporting base, a GaN based semiconductor region, an active layer, and a GaN semiconductor region. The primary surface of the group III nitride semiconductor supporting base is not any polar plane, and forms a finite angle with a reference plane that is orthogonal to a reference axis extending in the direction of a c-axis of the group III nitride semiconductor. The GaN based semiconductor region, grown on the semipolar primary surface, includes a semiconductor layer of, for example, an n-type GaN based semiconductor doped with silicon. A GaN based semiconductor layer of an oxygen concentration of 5×1004-12-2012
20120086014Semiconductor Device Having Glue Layer And Supporter - A plurality of metal patterns are disposed on a substrate. A support structure is provided between the plurality of metal patterns. The support structure has a supporter and a glue layer. Each of the plurality of metal patterns has a greater vertical length than a horizontal length on the substrate when viewed from a cross-sectional view. The supporter has a band gap energy of at least 4.5eV. The glue layer is in contact with the plurality of metal patterns. The supporter and the glue layer are formed of different materials.04-12-2012
20130207121POWER CONVERSION DEVICE - A power conversion device includes a power conversion semiconductor element having an electrode, an electrode conductor electrically connected to the electrode of the power conversion semiconductor element and including a side face and an upper end portion having a substantially flat upper end face, and a seal material formed of resin to cover the power conversion semiconductor element and the side face of the electrode conductor. The substantially flat upper end face of the electrode conductor is exposed from an upper surface of the seal material, and the upper end portion of the electrode conductor having the substantially flat upper end face has a projecting portion projecting sideward.08-15-2013
20130207118LIGHT EMITTING DIODE AND FABRICATION METHOD THEREOF - The present invention discloses an LED and its fabrication method. The LED comprises: a substrate; an epitaxial layer, an active layer and a capping layer arranged on the substrate in sequence; wherein a plurality of bifocal microlens structures are formed on the surface of the substrate away from the epitaxial layer. When the light emitted from the active layer passes through the surfaces of the bifocal microlens structures, the incident angle is always smaller than the critical angle of total reflection, thus preventing total reflection and making sure that most of the light pass through the surfaces of the bifocal microlens structures, in this way improving external quantum efficiency of the LED, avoiding the rise of the internal temperature of the LED and improving the performance of the LED.08-15-2013
20130207119LOW-DEFECT DENSITY GALLIUM NITRIDE SEMICONDUCTOR STRUCTURES AND FABRICATION METHODS - A low-defect gallium nitride structure including a first gallium nitride layer comprising a plurality of gallium nitride columns etched into the first gallium nitride layer and a first dislocation density; and a second gallium nitride layer that extends over the gallium nitride columns and comprises a second dislocation density, wherein the second dislocation density may be lower than the first dislocation density. In addition, a method for fabricating a gallium nitride semiconductor layer that includes masking an underlying gallium nitride layer with a mask that comprises an array of columns and growing the underlying gallium nitride layer through the columns and onto said mask using metal-organic chemical vapor deposition pendeo-epitaxy to thereby form a pendeo-epitaxial gallium nitride layer coalesced on said mask to form a continuous pendeo-epitaxial monocrystalline gallium nitride semiconductor layer.08-15-2013