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Amorphous semiconductor material

Subclass of:

257 - Active solid-state devices (e.g., transistors, solid-state diodes)

257049000 - NON-SINGLE CRYSTAL, OR RECRYSTALLIZED, SEMICONDUCTOR MATERIAL FORMS PART OF ACTIVE JUNCTION (INCLUDING FIELD-INDUCED ACTIVE JUNCTION)

Patent class list (only not empty are listed)

Deeper subclasses:

Class / Patent application numberDescriptionNumber of patent applications / Date published
257057000 Field effect device in amorphous semiconductor material 1553
257053000 Responsive to nonelectrical external signals (e.g., light) 88
257062000 With impurity other than hydrogen to passivate dangling bonds (e.g., halide) 4
20120193632SILICON STRUCTURE AND MANUFACTURING METHODS THEREOF AND OF CAPACITOR INCLUDING SILICON STRUCTURE - Provided is a silicon structure with a three-dimensionally complex shape. Further provided is a simple and easy method for manufacturing the silicon structure with the use of a phenomenon in which an ordered pattern is formed spontaneously to form a nano-structure. Plasma treatment under hydrogen atmosphere is performed on an amorphous silicon layer and the following processes are performed at the same time: a reaction process for growing microcrystalline silicon on a surface of the silicon layer and a reaction process for etching the amorphous silicon layer which is exposed, so that a nano-structure including an upper structure in a microcrystalline state and a lower structure in an amorphous state, over the silicon layer is formed; accordingly, a silicon structure with a three-dimensionally complex shape can be provided.08-02-2012
20110101363SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A separation layer containing a halogen element is formed over a glass substrate by a plasma CVD method; a semiconductor element is formed over the separation layer; and separation is then performed inside the separation layer or at its interface, so that the large-area glass substrate and the semiconductor element are detached from each other. In order to perform detachment at the interface between the glass substrate and the separation layer, the separation layer may have concentration gradient of the halogen element, and the halogen element is contained more near the interface between the separation layer and the glass substrate than in the other areas.05-05-2011
20120074417Method of Bonding Wafers - A method of bonding wafers with an aluminum-germanium bond includes forming an aluminum layer on a first wafer, and a germanium layer on a second wafer, and implanting the germanium layer with non-germanium atoms prior to forming a eutectic bond at the aluminum-germanium interface. The wafers are aligned to a desired orientation and the two layers are held in contact with one another. The aluminum-germanium interface is heated to a temperature that allows the interface of the layers to melt, thus forming a bond. A portions of the germanium layer may be removed from the second wafer to allow infrared radiation to pass through the second wafer to facilitate wafer alignment.03-29-2012
20120267632SELECT DEVICES - Methods, devices, and systems are provided for a select device that can include a semiconductive stack of at least one semiconductive material formed on a first electrode, where the semiconductive stack can have a thickness of about 700 angstroms (Å) or less. Each of the at least one semiconductive material can have an associated band gap of about 4 electron volts (eV) or less and a second electrode can be formed on the semiconductive stack.10-25-2012
257063000 Amorphous semiconductor is alloy or contains material to change band gap (e.g., Si x Ge 1-x , SiN y ) 3
20130075740P-TYPE OXIDE ALLOYS BASED ON COPPER OXIDES, TIN OXIDES, TIN-COPPER ALLOY OXIDES AND METAL ALLOY THEREOF, AND NICKEL OXIDE, WITH EMBEDDED METALS THEREOF, FABRICATION PROCESS AND USE THEREOF - The present invention relates to thin films comprising non-stoichiometric monoxides of: copper (OCu03-28-2013
20090189159GETTERING LAYER ON SUBSTRATE - Disclosed herein are devices, methods and systems for implementing gettering layers. Devices including gettering layers can be implemented such that a gettering layer doped with carbon, boron, fluorine or any other appropriate impurity is formed on a semiconductor substrate, a device layer is formed on the gettering layer, and a device region is formed in the device layer having a depth that maintains a distance in the device layer between the gettering layer and the device region.07-30-2009
20110169007STRUCTURES INCLUDING PASSIVATED GERMANIUM - A passivated germanium surface that is a germanium carbide material formed on and in contact with the termanium material. An intermediate semiconductor device structure and a semiconductor device structure, each of which comprises the passivated germanium having germanium carbide material thereon, are also disclosed.07-14-2011
Entries
DocumentTitleDate
20110204361DISPLAY DEVICE MANUFACTURING METHOD AND LAMINATED STRUCTURE - A method for manufacturing a display device includes; a step of preparing a flexible substrate including a delamination layer on its back surface, a step of bonding a support substrate to the delamination layer of the flexible substrate via an adhesive layer, a step of forming predetermined devices on a front surface of the flexible substrate having the support substrate bonded thereto, and a step of removing the support substrate by delaminating the delamination layer from the flexible substrate having the devices formed thereon.08-25-2011
20100155729FAN-OUT UNIT AND THIN-FILM TRANSISTOR ARRAY SUBSTRATE HAVING THE SAME - A fan-out unit which can control a resistance difference among channels with efficient space utilization and a thin-film transistor (TFT) array substrate having the fan-out unit are presented. The fan-out unit includes: an insulating substrate; a first wiring layer which is formed on the insulating substrate and connected to a pad; a second wiring layer which is formed on the insulating substrate and connected to a TFT; and a resistance controller which is connected between the first wiring layer and the second wiring layer and includes a plurality of first resistors extending parallel to the first wiring layer and a plurality of second resistors extending perpendicular to the first resistors and alternately connecting to the first resistors, wherein the first resistors are longer than the second resistors.06-24-2010
20100044706METHODS OF FORMING A LAYER OF MATERIAL ON A SUBSTRATE AND STRUCTURES FORMED THEREFROM - Various structures that include at least one thin layer of an amorphous material on a supporting substrate. One structure generally has a receiving substrate, a central crystalline layer and an amorphous layer, all of which may lack any end of range point defects. Another structure includes an intermediate substrate having an upper face, an upper portion and a lower portion, an amorphous layer that does not contain end of range point defects, and a first crystalline layer containing end of range point defects subjacent the amorphous layer and located in the lower portion; and a supporting substrate bonded to the upper face of the intermediate substrate. That structure can also contain a weakened zone or porous layer to facilitate removal of the first crystalline layer to provide the amorphous layer as an upper layer of the semiconductor structure.02-25-2010
20120205654SILICON LAYERS FORMED FROM POLYMER-MODIFIED LIQUID SILANE FORMULATIONS - The invention relates to a formulation which contains at least one silane and at least one carbon polymer in a solvent, and to the production of a silicon layer on a substrate which is coated with such a formulation.08-16-2012
20130026470WIRING STRUCTURE, DISPLAY APPARATUS, AND SEMICONDUCTOR DEVICE - Disclosed is a wiring structure that attains excellent low-contact resistance even if eliminating a barrier metal layer that normally is disposed between a Cu alloy wiring film and a semiconductor layer, and wiring structure with excellent adhesion. The wiring structure is provided with a semiconductor layer, and a Cu alloy layer, on a substrate in this order from the substrate side. A laminated structure is included between the semiconductor layer, and the Cu alloy layer. The laminated structure is composed of a (N, C, F, O) layer which contains at least one element selected from among a group composed of nitrogen, carbon, fluorine, and oxygen, and a Cu—Si diffusion layer which includes Cu and Si, in this order from the substrate side. At least one element selected from among the group composed of nitrogen, carbon, fluorine, and oxygen that composes the (N, C, F, O) layer is bonded to Si in the semiconductor layer. The Cu alloy layer is a laminated structure containing a Cu—X alloy layer (a first layer) and a second layer.01-31-2013
20130048988Nanopillar E-Fuse Structure and Process - Techniques for incorporating nanotechnology into electronic fuse (e-fuse) designs are provided. In one aspect, an e-fuse structure is provided. The e-fuse structure includes a first electrode; a dielectric layer on the first electrode having a plurality of nanochannels therein; an array of metal silicide nanopillars that fill the nanochannels in the dielectric layer, each nanopillar in the array serving as an e-fuse element; and a second electrode in contact with the array of metal silicide nanopillars opposite the first electrode. Methods for fabricating the e-fuse structure are also provided as are semiconductor devices incorporating the e-fuse structure.02-28-2013
20130048987P-I-N STRUCTURES AND METHODS FOR FORMING P-I-N STRUCTURES HAVING AN I-LAYER FORMED VIA HOT WIRE CHEMICAL VAPOR DEPOSITION (HWCVD) - Embodiments of the present invention provide p-i-n structures and methods for forming p-i-n structures useful, for example, in photovoltaic cells. In some embodiments, a method for forming a p-i-n structure on a substrate may include forming a bi-layer p-type layer on the substrate by: depositing a microcrystalline p-type layer atop the protective layer; and depositing an amorphous p-type layer atop the microcrystalline p-type layer; depositing an amorphous i-type layer via hot wire chemical vapor deposition atop the amorphous p-type layer; and depositing an amorphous n-type layer atop the amorphous i-type layer. A p-i-n structure may include a bi-layer p-type layer disposed above a substrate, the bi-layer p-type layer having a microcrystalline p-type layer and an amorphous p-type layer disposed atop the microcrystalline p-type layer; an amorphous i-type layer disposed atop the bi-layer p-type layer; and an n-type layer disposed atop the i-type layer.02-28-2013
20130048986ORGANIC LIGHT EMITTING DIODE DISPLAY AND MANUFACTURING METHOD THEREOF - An OLED display includes: a first pixel including a first pixel electrode of a pixel electrode, a second pixel including a second pixel electrode of the pixel electrode, and a third pixel including a third pixel electrode of the pixel electrode; a resonance assistance layer on the first pixel electrode; an organic emission layer including a first organic emission layer on the resonance assistance layer and the second pixel electrode, a second organic emission layer on the first organic emission layer, and a third organic emission layer on the third pixel electrode; a common electrode on the organic emission layer; and a color mixture preventing layer on the common electrode and configured to absorb overlapped light in an overlapped wavelength region of a wavelength region of first light emitted by the first organic emission layer and a wavelength region of second light emitted by the second organic emission layer.02-28-2013
20130048985Metal-induced crystallization of continuous semiconductor thin films controlled by a diffusion barrier - A device and a method of forming a continuous polycrystalline Ge film having crystalline Ge islands is provided that includes depositing an amorphous Ge (a-Ge) layer on a substrate, oxidizing the top surface of the a-Ge layer to form a GeO02-28-2013
20090261327PROCESS FOR THE SIMULTANEOUS DEPOSITION OF CRYSTALLINE AND AMORPHOUS LAYERS WITH DOPING - One embodiment of the present invention relates to method for the concurrent deposition of multiple different crystalline structures on a semiconductor body utilizing in-situ differential epitaxy. In one embodiment of the present invention a preparation surface is formed, resulting in two distinct crystalline regions, a monocrystalline silicon substrate region and an isolating layer region. A monocrystalline silicon layer and an amorphous silicon layer are concurrently formed directly onto the preparation surface in the monocrystalline silicon substrate region and the isolating layer region, respectively. Deposition comprises the formation of two or more sub-layers. The process parameters can be varied for each individual sub-layer to optimize deposition characteristics.10-22-2009
20130161619SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A silicon carbide substrate includes: an n type drift layer having a first surface and a second surface opposite to each other; a p type body region provided in the first surface of the n type drift layer; and an n type emitter region provided on the p type body region and separated from the n type drift layer by the p type body region. A gate insulating film is provided on the p type body region so as to connect the n type drift layer and the n type emitter region to each other. A p type Si collector layer is directly provided on the silicon carbide substrate to face the second surface of the n type drift layer.06-27-2013
20120168753NITRIDE SEMICONDUCTOR LIGHT EMITTING DIODE - In a nitride semiconductor light emitting diode including a substrate made of a nitride semiconductor, a first conductive-type nitride semiconductor layer formed on the substrate, an active layer made of a nitride semiconductor, and a second conductive-type nitride semiconductor layer, characterized in that light emitted is extracted from the under surface side of the substrate or the upper surface side of the second conductive-type nitride semiconductor layer, an intermediate layer is formed between the substrate and the active layer, and dislocations is allowed to generates from the dislocation generating layer as the origin and to distribute in a light emitting region of the active layer.07-05-2012
20110121296THIN FILM TRANSISTOR COMPOSITIONS, AND METHODS RELATING THERETO - A process for forming at least one transistor on a substrate is described. The substrate comprises a polyimide and a nanoscopic filler. The polyimide is derived substantially or wholly from rigid rod monomers and the nanoscopic filler has an aspect ratio of at least 3:1. The substrates of the present disclosure are particularly well suited for thin film transistor applications, due at least in part to high resistance to hygroscopic expansion and relatively high levels of thermal and dimensional stability.05-26-2011
20100090219METHOD FOR FABRICATION OF SEMICONDUCTOR DEVICE - A method of fabrication of a semiconductor device having low resistance in an interconnection line and the same coefficient of thermal expansion as a semiconductor substrate is disclosed. The method includes forming a nitride film over a semiconductor substrate including a bottom metal line and a top metal line connected to each other through a plurality of vias, forming a trench at a through-silicon via (TSV) region of the semiconductor substrate, filling the trench with a predetermined material to form a silicon film, exposing the silicon film using a photoresist pattern, ion-implanting a dopant into the exposed silicon film, and selectively performing laser annealing to the silicon film to diffuse only the dopant implanted into the silicon film.04-15-2010
20110204362SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - It is an object to provide a semiconductor device including an oxide semiconductor, in which miniaturization of a transistor is achieved and the concentration of an electric field is relieved. The width of a gate electrode is reduced and a space between a source electrode layer and a drain electrode layer is shortened. By adding a rare gas in a self-alignment manner with the use of a gate electrode as a mask, a low-resistance region in contact with a channel formation region can be provided in an oxide semiconductor layer. Accordingly, even when the width of the gate electrode, that is, the line width of a gate wiring is small, the low-resistance region can be provided with high positional accuracy, so that miniaturization of a transistor can be realized.08-25-2011
20090014720METHOD OF TREATING INTERFACE DEFECTS IN A SUBSTRATE - The present invention relates to a method of treating a structure produced from semiconductor materials, wherein the structure includes a first and second substrates defining a common interface that has defects. The method includes forming a layer, called the disorganized layer, which includes the interface, in which at least a part of the crystal lattice is disorganized; and reorganizing the crystal lattice of the disorganized layer in order to force the defects back deeper into the first substrate.01-15-2009
20090065776Print Processing for Patterned Conductor, Semiconductor and Dielectric Materials - Embodiments relate to printing features from an ink containing a material precursor. In some embodiments, the material includes an electrically active material, such as a semiconductor, a metal, or a combination thereof. In another embodiment, the material includes a dielectric. The embodiments provide improved printing process conditions that allow for more precise control of the shape, profile and dimensions of a printed line or other feature. The composition(s) and/or method(s) improve control of pinning by increasing the viscosity and mass loading of components in the ink. An exemplary method thus includes printing an ink comprising a material precursor and a solvent in a pattern on the substrate; precipitating the precursor in the pattern to form a pinning line; substantially evaporating the solvent to form a feature of the material precursor defined by the pinning line; and converting the material precursor to the patterned material.03-12-2009
20100258800Semiconductor stacking layer and fabricating method thereof - A fabricating method of a semiconductor stacking layer includes following steps. First, an amorphous silicon (a-Si) layer is formed on a substrate. Surface treatment is then performed on a surface of the a-Si layer. After that, a doped microcrystalline silicon (μc-Si) layer is formed on the treated surface of the a-Si layer, wherein interface defects existing between the a-Si layer and the doped μc-Si layer occupy an area in a cross-sectional region having a width of 1.5 micrometers and a thickness of 40 nanometers, and a ratio of the occupied area in the cross-sectional region is equal to or less than 10%. The method of fabricating the semiconductor stacking layer can be applied to a fabrication process of a semiconductor device to effectively reduce the interface defects of the semiconductor stacking layer.10-14-2010
20120228612COMPOSITE BASE INCLUDING SINTERED BASE AND BASE SURFACE FLATTENING LAYER, AND COMPOSITE SUBSTRATE INCLUDING THAT COMPOSITE BASE AND SEMICONDUCTOR CRYSTALLINE LAYER - A composite base of the present invention includes a sintered base and a base surface flattening layer disposed on the sintered base, and the base surface flattening layer has a surface RMS roughness of not more than 09-13-2012
20090294766Process for Eliminating Delamination between Amorphous Silicon Layers - A circuit structure includes a substrate; a first amorphous silicon layer over the substrate; a first glue layer over and adjoining the first amorphous silicon layer; and a second amorphous silicon layer over and adjoining the first glue layer.12-03-2009
20100230674METHOD FOR FORMING NON-ALIGNED MICROCAVITIES OF DIFFERENT DEPTHS - The invention relates to a method for forming microcavities (09-16-2010
20120241742THINNED SEMICONDUCTOR COMPONENTS HAVING LASERED FEATURES AND METHOD OF FABRICATION - A semiconductor component includes a thinned semiconductor substrate having a back side and a circuit side containing integrated circuits and associated circuitry. The semiconductor component also includes at least one lasered feature on the back side configured to provide selected electrical or physical characteristics for the substrate. The lasered feature can cover the entire back side or only selected areas of the back side, and can be configured to change electrical properties, mechanical properties or gettering properties of the substrate.09-27-2012
20090114915SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A separation layer containing a halogen element is formed over a glass substrate by a plasma CVD method; a semiconductor element is formed over the separation layer; and separation is then performed inside the separation layer or at its interface, so that the large-area glass substrate and the semiconductor element are detached from each other. In order to perform detachment at the interface between the glass substrate and the separation layer, the separation layer may have concentration gradient of the halogen element, and the halogen element is contained more near the interface between the separation layer and the glass substrate than in the other areas.05-07-2009
20110024747METHODS FOR IMPROVING THE QUALITY OF GROUP III-NITRIDE MATERIALS AND STRUCTURES PRODUCED BY THE METHODS - The invention provides methods which can be applied during the epitaxial growth of two or more layers of Group III-nitride semiconductor materials so that the qualities of successive layer are successively improved. In preferred embodiments, surface defects interact with a protective layer of a protective material to form amorphous complex regions capable of preventing the further propagation of defects and dislocations. The invention also includes semiconductor structures fabricated by these methods.02-03-2011
20110114952MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A manufacturing method of a highly reliable semiconductor with a waterproof property. The method includes the steps of: sequentially forming a peeling layer, an inorganic insulating layer, and an element formation layer including an organic compound layer, over a substrate; separating the peeling layer and the inorganic insulating layer from each other, or separating the substrate and the inorganic insulating layer from each other; removing a part of the inorganic insulating layer or a part of the inorganic insulating layer and the element formation layer, thereby isolating at least the inorganic insulating layer into a plurality of sections so that at least two layers among the organic compound layer, a flexible substrate, and an adhesive agent are stacked at outer edges of the isolated inorganic insulating layers; and cutting a region where at least two layers among the organic compound layer, the flexible substrate, and the adhesive agent are stacked.05-19-2011
20090032815PIXEL WELL ELECTRODES - A multi-level mandrel is used to locate an electrode in a pixel well. A display includes an electrode recessed in a floor of a pixel well.02-05-2009
20100224876Two-Sided Semiconductor Structure - Deep via trenches and deep marker trenches are formed in a bulk substrate and filled with a conductive material to form deep conductive vias and deep marker vias. At least one first semiconductor device is formed on the first surface of the bulk substrate. A disposable dielectric capping layer and a disposable material layer are formed over the first surface of the bulk substrate. The second surface, located on the opposite side of the first surface, of the bulk substrate is polished to expose and planarize the deep conductive vias and deep marker vias, which become through-substrate vias and through-substrate alignment markers, respectively. At least one second semiconductor device and second metal interconnect structures are formed on the second surface of the bulk substrate. The disposable material layer and the disposable dielectric capping layer are removed and first metal interconnect structures are formed on the first surface.09-09-2010
20110210330LIGHT EMITTING DIODE AND METHOD OF MAKING THE SAME - A light emitting diode (LED) and a method of making the same are disclosed. The present invention uses a metal layer of high conductivity and high reflectivity to prevent the substrate from absorbing the light emitted. This invention also uses the bonding technology of dielectric material thin film to replace the substrate of epitaxial growth with high thermal conductivity substrate to enhance the heat dissipation of the chip, thereby increasing the performance stability of the LED, and making the LED applicable under higher current.09-01-2011
20090032816PIXEL WELL ELECTRODE - Various apparatus and methods relating to pixel wells and electrodes that are at least partially concurrently formed are disclosed.02-05-2009
20100264415INTERCONNECTING STRUCTURE PRODUCTION METHOD, AND INTERCONNECTING STRUCTURE - An interconnecting structure production method includes providing a substrate, forming a semiconductor layer on the substrate, forming a doped semiconductor layer on the semiconductor layer, the doped semiconductor layer containing a dopant, forming an oxide layer in a surface of the doped semiconductor layer by heating the surface of the doped semiconductor layer in atmosphere of an oxidizing gas with a water molecule contained therein, forming an alloy layer on the oxide layer, and forming an interconnecting layer on the alloy layer.10-21-2010
20120199832PROCESS FOR PRODUCING DOPED SILICON LAYERS, SILICON LAYERS OBTAINABLE BY THE PROCESS AND USE THEREOF - The present invention relates to a process for producing a doped silicon layer on a substrate, comprising the steps of (a) providing a liquid silane formulation and a substrate, (b) applying the liquid silane formulation to the substrate, (c) introducing electromagnetic and/or thermal energy to obtain an at least partly polymorphic silicon layer, (d) providing a liquid formulation which comprises at least one aluminium-containing metal complex, (e) applying this formulation to the silicon layer obtained after step (c) and then (f) heating the coating obtained after step (e) by introducing electromagnetic and/or thermal energy, which decomposes the formulation obtained after step (d) at least to metal and hydrogen, and then (g) cooling the coating obtained after step (f) to obtain an Al-doped or Al- and metal-doped silicon layer, to doped silicon layers obtainable by the process and to the use thereof for production of light-sensitive elements and electronic components.08-09-2012
20100025685Method and apparatus for forming contact hole - A method of forming a contact hole in an insulating film coating amorphous Si having an irregular surface formed on an insulating substrate, for connecting the amorphous Si to a conductor film formed on the insulating film includes etching the insulating film using reactive ion etching to a depth whereat the irregularity does not disappear, and sputter-etching by physically colliding Ar radicals produced by Ar gas plasma discharge onto the surface of the amorphous Si.02-04-2010
20120146024METHOD OF FORMING A GETTERING STRUCTURE AND THE STRUCTURE THEREFOR - At least one exemplary embodiment is directed to a method of forming a multilayered Bettering structure that can be used to control wafer warpage.06-14-2012
20090032817Back-To-Back Metal/Semiconductor/Metal (MSM) Schottky Diode - A method is provided for forming a metal/semiconductor/metal (MSM) back-to-back Schottky diode from a silicon (Si) semiconductor. The method deposits a Si semiconductor layer between a bottom electrode and a top electrode, and forms a MSM diode having a threshold voltage, breakdown voltage, and on/off current ratio. The method is able to modify the threshold voltage, breakdown voltage, and on/off current ratio of the MSM diode in response to controlling the Si semiconductor layer thickness. Generally, both the threshold and breakdown voltage are increased in response to increasing the Si thickness. With respect to the on/off current ratio, there is an optimal thickness. The method is able to form an amorphous Si (a-Si) and polycrystalline Si (polySi) semiconductor layer using either chemical vapor deposition (CVD) or DC sputtering. The Si semiconductor can be doped with a Group V donor material, which decreases the threshold voltage and increases the breakdown voltage.02-05-2009
20110095291Lateral Growth Semiconductor Method and Devices - A method of growing high quality crystalline films on lattice-mismatched or amorphous layers is presented allowing semiconductor materials that would normally be subject to high stress and cracking to be employed allowing cost reductions and/or performance improvements in devices to be obtained. Catalysis of the growth of these films is based upon utilizing particular combinations of metals, materials, and structures to establish growth of the crystalline film from a predetermined location. The subsequent film growth occurring in one or two dimensions to cover a predetermined area of the amorphous or lattice-mismatched substrate. Accordingly the technique can be used to either cover a large area or provide tiles of crystalline material with or without crystalline film interconnections.04-28-2011
20110315988PASSIVATED UPSTANDING NANOSTRUCTURES AND METHODS OF MAKING THE SAME - Described herein is a device comprising: a substrate; one or more of a nanostructure extending essentially perpendicularly from the substrate; wherein the nanostructure comprises a core of a doped semiconductor, an first layer disposed on the core, and a second layer of an opposite type from the core and disposed on the first layer.12-29-2011
20120043541SEMICONDUCTOR DEVICE - An object is to provide a transistor in which light deterioration is suppressed as much as possible and electrical characteristics are stable, and a semiconductor device including the transistor. The attention focuses on the fact that light is reflected by a film used for forming a transistor and multiple interaction occurs. When the optical thickness of the film which causes the reflection is roughly an odd multiple of λ02-23-2012
20120007077SILICON DEVICE STRUCTURE, AND SPUTTERING TARGET USED FOR FORMING THE SAME - There is provided a silicon device structure, comprising: a P-doped n01-12-2012
20120007078SEMICONDUCTOR DEVICE - It is an object to provide a method of manufacturing a crystalline silicon device and a semiconductor device in which formation of cracks in a substrate, a base protective film, and a crystalline silicon film can be suppressed. First, a layer including a semiconductor film is formed over a substrate, and is heated. A thermal expansion coefficient of the substrate is 6×1001-12-2012
20090166626PRODUCING METHOD FOR CRYSTALLINE THIN FILM - A method for producing a crystalline film by melting and resolidifying a film, characterized in preparing a film having a specific region and obtained either by (A) a step of forming a film in which a “specific region” and an “region continuous to a periphery of the specific region and different in thickness from the specific region” co-exist, or by (B) a step of irradiating a film with an electromagnetic wave or particles having a mass in mutually different conditions between a specific region and a peripheral region thereof, and melting and resolidifying at least a part of the film. As the spatial position of the specific region can be exactly and easily controlled, it is possible to obtain a crystalline film in which a crystal grain is formed in a desired position.07-02-2009
20120153283Display Panel Structure of Electrophoretic Display Device, Display Device Structure, and Method for Manufacturing Display Device - A display device structure includes a substrate having an active region and an electrostatic protection circuit region. The first metal layer, the first insulation layer, and an amorphous silicon layer are sequentially disposed on the substrate; the first opening passes through the first insulation layer for exposing part of the first metal layer. The second metal layer, disposed on the first insulation layer or the amorphous silicon layer, fills the first opening to contact with the first metal layer; the second insulation layer and the flat layer are disposed on the second metal layer, in which the region of the flat layer is overlapped the electrostatic protection circuit region. The second opening passes through the second insulation layer and the flat layer for exposing the second metal layer, in which the third metal layer fills the second opening to contact with the second metal layer.06-21-2012
20120211748Method of Dicing a Wafer - A method of dicing a semiconductor wafer includes forming a layer stack on a first main surface of a substrate. The layer stack and a portion of the substrate are etched according to a pattern defining an intended dicing location to obtain a trench structure. The substrate is irradiated with a laser beam to locally modify the substrate between a bottom of the trench structure and a second main surface of the substrate opposite to the first main surface.08-23-2012
20100244029SEMICONDUCTOR DEVICE - The threshold voltage is shifted in a negative or positive direction in some cases by an unspecified factor in a manufacturing process of the thin film transistor. If the amount of shift from 0 V is large, driving voltage is increased, which results in an increase in power consumption of a semiconductor device. Thus, a resin layer having good flatness is formed as a first protective insulating film covering the oxide semiconductor layer, and then a second protective insulating film is formed by a sputtering method or a plasma CVD method under a low power condition over the resin layer. Further, in order to adjust the threshold voltage to a desired value, gate electrodes are provided over and below an oxide semiconductor layer.09-30-2010
20100006841DUAL METAL GATE TRANSISTOR WITH RESISTOR HAVING DIELECTRIC LAYER BETWEEN METAL AND POLYSILICON - Structures are presented including a high-k and metal gate transistor and a resistor where the resistor includes a dielectric layer between a metal and a polysilicon. The resistor provides typical polysilicon resistor performance with less cost and higher throughput.01-14-2010
20120228613METHOD OF MANUFACTURING SEMICONDUCTOR WAFER, AND COMPOSITE BASE AND COMPOSITE SUBSTRATE FOR USE IN THAT METHOD - A method of manufacturing a semiconductor wafer of the present invention includes the steps of: obtaining a composite base by forming a base surface flattening layer having a surface RMS roughness of not more than 1.0 nm on a base; obtaining a composite substrate by attaching a semiconductor crystal layer to a side of the composite base where the base surface flattening layer is located; growing at least one semiconductor layer on the semiconductor crystal layer of the composite substrate; and obtaining the semiconductor wafer including the semiconductor crystal layer and the semiconductor layer by removing the base surface flattening layer by wet etching and thereby separating the semiconductor crystal layer from the base. Thus, a method of manufacturing a semiconductor wafer capable of efficiently manufacturing the semiconductor wafer regardless of the type of a base, and a composite base and a composite substrate suitably used in that manufacturing method are provided to efficiently manufacture a semiconductor device.09-13-2012
20120228614SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - According to one embodiment, a semiconductor device is disclosed. The device includes a semiconductor substrate, and an interconnection above the semiconductor substrate. The interconnection includes a co-catalyst layer, a catalyst layer on the co-catalyst layer, and a graphene layer on the catalyst layer. The co-catalyst layer includes a portion contacting the catalyst layer. The portion has a face-centered cubic structure with a (111) plane oriented parallel to a surface of the semiconductor substrate. The catalyst layer has a face-centered cubic structure with a (111) plane oriented parallel to the surface of the semiconductor substrate.09-13-2012
20110121297WIRING STRUCTURE, THIN FILM TRANSISTOR SUBSTRATE, METHOD FOR MANUFACTURING THIN FILM TRANSISTOR SUBSTRATE, AND DISPLAY DEVICE - Provided is a direct contact technology by which a barrier metal layer between a Cu alloy wiring composed of pure Cu or a Cu alloy and a semiconductor layer can be eliminated, and the Cu alloy wiring can be directly and surely connected to the semiconductor layer within a wide process margin. The wiring structure is provided with the semiconductor layer and the Cu alloy film composed of pure Cu or the Cu alloy on a substrate in this order from the substrate side. A laminated structure is included between the semiconductor layer and the Cu alloy film. The laminated structure is composed of an (N, C, F) layer, which contains at least one element selected from among a group composed of nitrogen, carbon and fluorine, and a Cu—Si diffusion layer, which contains Cu and Si, in this order from the substrate side. Furthermore, at least the one element selected from among the group composed of nitrogen, carbon and fluorine is bonded to Si contained in the semiconductor layer.05-26-2011
20110227070GETTERING MEMBERS, METHODS OF FORMING THE SAME, AND METHODS OF PERFORMING IMMERSION LITHOGRAPHY USING THE SAME - Provided herein are gettering members that include a monitor substrate and a conditioning layer thereon. Also provided herein are methods of forming gettering layers and methods of performing immersion lithography processes using the same.09-22-2011
20120091457SEMICONDUCTOR COMPONENT INCLUDING A LATERAL TRANSISTOR COMPONENT - A semiconductor arrangement is disclosed. One embodiment includes a first semiconductor layer including a first and second component zone that form a pn-junction or a Schottky-junction. A second semiconductor layer includes a drift control zone adjacent to the second component zone. A dielectric layer separates the first semiconductor layer from the second semiconductor layer. A rectifying element is coupled between the drift control zone and the second component zone.04-19-2012
20130015442BONDED SEMICONDUCTOR STRUCTURES AND METHOD OF FORMING SAME - Methods of forming semiconductor structures include transferring a portion (01-17-2013
20080237593Semiconductor Device, Method of Fabricating the Same, and Apparatus for Fabricating the Same - There is provided a semiconductor device including a substrate and a semiconductor film deposited on the substrate, characterized in that the semiconductor film has a laterally grown crystal having an end with a surface projection height smaller than the thickness of the semiconductor film. There are also provided a semiconductor device fabrication method and apparatus utilizing a method and apparatus for fabricating the semiconductor device, that is capable of reducing a surface projection height or a ridge formed in a last region in repeating laser exposure in the SLS method, and a semiconductor device fabricated thereby.10-02-2008
20080230781Method of forming an oxygen- or nitrogen-terminated silicon nanocrystalline structure and an oxygen- or nitrogen-terminated silicon nanocrystalline structure formed by the method - A substrate is set at a predetermined temperature in a plasma treatment chamber, then the inside of the plasma treatment chamber is regulated at a reduced pressure containing at least a silicon hydride gas and a hydrogen gas, a high-frequency electric field is applied to form a silicon film of nanometer scale thickness composed of fine silicon crystals and amorphous silicon on the substrate. Thereafter, application of the high-frequency electric field is terminated, then the inside of the plasma treatment chamber is replaced by an oxidizing or nitriding gas, and a high-frequency electric field is applied again for plasma oxidizing treatment or plasma nitriding treatment of the silicon film formed on the substrate.09-25-2008
20130140567SILICON SUBSTRATE, EPITAXIAL STRUCTURE INCLUDING THE SAME, AND METHOD OF MANUFACTURING THE SILICON SUBSTRATE - Crack formation and propagation in a silicon substrate may be reduced by forming a crack reducing portion. The silicon substrate includes a silicon main portion and a silicon edge portion formed around the silicon main portion. The crack reducing portion is formed on the silicon edge portion of the silicon substrate such that the directions of crystal faces in the crack reducing portion are randomly oriented.06-06-2013
20090283766Methods for increasing film thickness during the deposition of silicon films using liquid silane materials - Embodiments in accordance with the present invention relate to the fabrication of thin (>1 μm) polycrystalline, nanocrystalline, or amorphous silicon films on a substrate. Particular embodiments utilize liquid sources of silane, including but not limited to cyclohexasilane (CHS), cyclopentasilane (CPS) or related derivatives of these compounds. In one embodiment, the silane is applied in liquid form contained by the use of a series of raised walls. Subsequent polymerization results in the material being a solid form. In other embodiments, the silane is applied as a liquid which is then frozen, with subsequent localized melting allowing polymerization to convert the material into a stable solid form. Embodiments of the present invention are particularly suited for forming thick (>10 μm) silicon films needed to achieve light absorption efficiencies deemed acceptable for thin film photovoltaic devices.11-19-2009
20090218567CONDUCTIVE BRIDGE RANDOM ACCESS MEMORY DEVICE AND METHOD OF MAKING THE SAME - A method for making a semiconductor device (09-03-2009
20130092940SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - To provide a miniaturized transistor having high electric characteristics. A conductive film to be a source electrode layer and a drain electrode layer is formed to cover an oxide semiconductor layer and a channel protection layer, and then a region of the conductive film, which overlaps with the oxide semiconductor layer and the channel protection layer, is removed by chemical mechanical polishing treatment. Precise processing can be performed accurately because an etching step using a resist mask is not performed in the step of removing part of the conductive film to be the source electrode layer and the drain electrode layer. With the channel protection layer, damage to the oxide semiconductor layer or a reduction in film thickness due to the chemical mechanical polishing treatment on the conductive film can be suppressed.04-18-2013
20130146875SPLIT ELECTRODE FOR ORGANIC DEVICES - A device is provided. The device includes a first electrode, an organic layer disposed over the first electrode and a second electrode disposed over the organic layer. The second electrode further includes a first conductive layer having an extinction coefficient and an index of refraction, a first separation layer disposed over the first conductive layer, and a second conductive layer disposed over the first separation layer. The first separation layer has an extinction coefficient that is at least 10% different from the extinction coefficient of the first conductive layer at 500 nm, or an index of refraction that is at least 10% different from the index of refraction of the first conductive layer at 500 nm. The device also includes a barrier layer disposed over the second conductive layer.06-13-2013
20120273784FABRICATION OF ELECTRONIC AND PHOTONIC SYSTEMS ON FLEXIBLE SUBSTRATES BY LAYER TRANSFER METHOD - A transfer layer includes a transparent substrate. A buffer layer is formed on the transparent substrate that comprises PbO, GaN, PbTiO11-01-2012
20130126867HIGH YIELD SUBSTRATE ASSEMBLY - High yield substrate assembly. In accordance with a first method embodiment, a plurality of piggyback substrates are attached to a carrier substrate. The edges of the plurality of the piggyback substrates are bonded to one another. The plurality of piggyback substrates are removed from the carrier substrate to form a substrate assembly. The substrate assembly is processed to produce a plurality of integrated circuit devices on the substrate assembly. The processing may use manufacturing equipment designed to process wafers larger than individual instances of the plurality of piggyback substrates.05-23-2013
20110309360PROCESS FOR FORMING AN ELECTROACTIVE LAYER - There is provided a process for forming a layer of electroactive material having a substantially flat profile. The process includes: providing a workpiece having at least one active area; depositing a liquid composition including the electroactive material onto the workpiece in the active area, to form a wet layer; treating the wet layer on the workpiece at a controlled temperature in the range of −25 to 80° C. and under a vacuum in the range of 1012-22-2011
20130187159INTEGRATED CIRCUIT AND METHOD OF FORMING AN INTEGRATED CIRCUIT - An integrated circuit includes a first trench disposed in a semiconductor material, wherein a width of the first trench in an upper portion of the first trench adjacent to a surface of the semiconductor material is smaller than a width of the first trench in a lower portion of the first trench, the lower portion being disposed within the semiconductor material, each width being measured in a plane parallel to a surface of the semiconductor material, each width denoting a distance between inner faces of remaining semiconductor material portions or between outer faces of a filling disposed in the first trench, or between an inner face of a remaining semiconductor material portion and an outer face of a filling disposed in the first trench.07-25-2013

Patent applications in class Amorphous semiconductor material

Patent applications in all subclasses Amorphous semiconductor material