Inventors list

Assignees list

Classification tree browser

Top 100 Inventors

Top 100 Assignees


NON-SINGLE CRYSTAL, OR RECRYSTALLIZED, SEMICONDUCTOR MATERIAL FORMS PART OF ACTIVE JUNCTION (INCLUDING FIELD-INDUCED ACTIVE JUNCTION)

Subclass of:

257 - Active solid-state devices (e.g., transistors, solid-state diodes)

Patent class list (only not empty are listed)

Deeper subclasses:

Class / Patent application numberDescriptionNumber of patent applications / Date published
257052000 Amorphous semiconductor material 1709
257066000 Field effect device in non-single crystal, or recrystallized, Semiconductor material 766
257051000 Non-single crystal, or recrystallized, material forms active junction with single crystal material (e.g., monocrystal to polycrystal pn junction or heterojunction) 61
257075000 Recrystallized semiconductor material 34
257064000 Non-single crystal, or recrystallized, material with specified crystal structure (e.g., specified crystal size or orientation) 25
257065000 Non-single crystal, or recrystallized, material containing non-dopant additive, or alloy of semiconductor materials (e.g., Ge x Si 1- x, polycrystalline silicon with dangling bond modifier) 9
257073000 Schottky barrier to polycrystalline semiconductor material 4
20130032809Semiconductor Devices with Non-Implanted Barrier Regions and Methods of Fabricating Same - An electronic device includes a silicon carbide layer including an n-type drift region therein, a contact forming a Schottky junction with the drift region, and a p-type junction barrier region on the silicon carbide layer. The p-type junction barrier region includes a p-type polysilicon region forming a P-N heterojunction with the drift region, and the p-type junction barrier region is electrically connected to the contact.02-07-2013
20100308337Schottky Diodes Including Polysilicon Having Low Barrier Heights and Methods of Fabricating the Same - Hybrid semiconductor devices including a PIN diode portion and a Schottky diode portion are provided. The PIN diode portion is provided on a semiconductor substrate and has an anode contact on a first surface of the semiconductor substrate. The Schottky diode portion is also provided on the semiconductor substrate and includes a polysilicon layer on the semiconductor substrate and a ohmic contact on the polysilicon layer. Related Schottky diodes are also provided herein.12-09-2010
20110215338SEMICONDUCTOR DEVICES WITH HETEROJUNCTION BARRIER REGIONS AND METHODS OF FABRICATING SAME - An electronic device includes a silicon carbide layer including an n-type drift region therein, a contact forming a junction, such as a Schottky junction, with the drift region, and a p-type junction barrier region on the silicon carbide layer. The p-type junction barrier region includes a p-type polysilicon region forming a P-N heterojunction with the drift region, and the p-type junction barrier region is electrically connected to the contact. Related methods are also disclosed.09-08-2011
20130153916Semiconductor Device Including a Diode - One embodiment of an integrated circuit includes a semiconductor body. In the semiconductor body a first trench region extends into the semiconductor body from a first surface. The integrated circuit further includes a diode including an anode region and a cathode region. One of the anode region and the cathode region is at least partly arranged in the first trench region. The other one of the anode region and the cathode region includes a first semiconductor region adjoining the one of the anode region and the cathode region from outside of the first trench region.06-20-2013
257074000 Plural recrystallized semiconductor layers (e.g., "3-dimensional integrated circuit") 3
20080303031VENTED DIE AND PACKAGE - A die that includes a substrate having a first and second major surface is disclosed. The die has at least one unfilled through via passing through the major surfaces of the substrate. The unfilled through via serves as a vent to release pressure generated during assembly.12-11-2008
20090261343HIGH-DENSITY NONVOLATILE MEMORY AND METHODS OF MAKING THE SAME - Nonvolatile memory cells and methods of forming the same are provided, the methods including forming a first conductor at a first height above a substrate; forming a first pillar-shaped semiconductor element above the first conductor, wherein the first pillar-shaped semiconductor element comprises a first heavily doped layer of a first conductivity type, a second lightly doped layer above and in contact with the first heavily doped layer, and a third heavily doped layer of a second conductivity type above and in contact with the second lightly doped layer, the second conductivity type opposite the first conductivity type; forming a first dielectric antifuse above the third heavily doped layer of the first pillar-shaped semiconductor element; and forming a second conductor above the first dielectric antifuse.10-22-2009
20130168684BACK CONTACT TO FILM SILICON ON METAL FOR PHOTOVOLTAIC CELLS - A crystal oriented metal back contact for solar cells is disclosed herein. In one embodiment, a photovoltaic device and methods for making the photovoltaic device are disclosed. The photovoltaic device includes a metal substrate with a crystalline orientation and a heteroepitaxial crystal silicon layer having the same crystal orientation of the metal substrate. A heteroepitaxial buffer layer having the crystal orientation of the metal substrate is positioned between the substrate and the crystal silicon layer to reduce diffusion of metal from the metal foil into the crystal silicon layer and provide chemical compatibility with the heteroepitaxial crystal silicon layer. Additionally, the buffer layer includes one or more electrically conductive pathways to electrically couple the crystal silicon layer and the metal substrate.07-04-2013
257050000 Non-single crystal, or recrystallized, active junction adapted to be electrically shorted (e.g., "anti-fuse" element) 3
20090152549MEMORY DEVICE - A memory device is provided, which includes a memory element including a first electrode, a second electrode, and a silicon layer disposed between the first electrode and the second electrode. The memory element is capable of being in a first state, a second state, and a third state. A first data is written to the memory element being in the first state so that a potential of the first electrode is higher than a potential of the second electrode, whereby the memory element being in the second state is obtained. A second data is written to the memory element being in the first state so that a potential of the second electrode is higher than a potential of the first electrode, whereby the memory element being in the third state is obtained.06-18-2009
20090179201Laser Chalcogenide Phase Change Device - A laser activated phase change device for use in an integrated circuit comprises a chalcogenide fuse configured to connect a first patterned metal line and a second patterned metal line and positioned between an inter layer dielectric and an over fuse dielectric. The fuse interconnects active semiconductor elements manufactured on a substrate. A method for activating the laser activated phase change device includes selecting a laser condition of a laser based on characteristics of the fuse and programming a phase-change of the fuse with the laser by direct photon absorption until a threshold transition temperature is met.07-16-2009
20090321735Electrical Antifuse and Method of Programming - An antifuse having a link including a region of unsilicided semiconductor material may be programmed at reduced voltage and current and with reduced generation of heat by electromigration of metal or silicide from a cathode into the region of unsilicided semiconductor material to form an alloy having reduced bulk resistance. The cathode and anode are preferably shaped to control regions from which and to which material is electrically migrated. After programming, additional electromigration of material can return the antifuse to a high resistance state. The process by which the antifuse is fabricated is completely compatible with fabrication of field effect transistors and the antifuse may be advantageously formed on isolation structures.12-31-2009
Entries
DocumentTitleDate
20100051946POLY-EMITTER TYPE BIPOLAR JUNCTION TRANSISTOR, BIPOLAR CMOS DMOS DEVICE, AND MANUFACTURING METHODS OF POLY-EMITTER TYPE BIPOLAR JUNCTION TRANSISTOR AND BIPOLAR CMOS DMOS DEVICE - A poly-emitter type bipolar transistor includes a buried layer formed over an upper portion of a semiconductor substrate, an epitaxial layer formed on the semiconductor substrate, a collector area formed on the epitaxial layer and connected to the buried layer, a base area formed at a part of an upper portion of the epitaxial layer, and a poly-emitter area formed on a surface of the semiconductor substrate in the base area and including a polysilicon material. A BCD device includes a poly-emitter type bipolar transistor having a poly-emitter area including a polysilicon material and at least one of a CMOS and a DMOS formed on a single wafer together with the poly-emitter type bipolar transistor.03-04-2010
20130075728ARRAY SUBSTRATE AND DISPLAY APPARATUS USING THE SAME - An array substrate includes scan lines and data lines defining pixel structures. Each pixel structure includes a first TFT, a second TFT and a pixel electrode. The first TFT includes a first gate connected to the scan line, a first source disposed above and partially overlapping the first gate, and a first drain disposed above the first gate. An end of the first source is connected to the data line. The first drain has at least one first concavity in which the first source is disposed partially. The second TFT includes a second gate connected to the scan line, a second source disposed above the second gate and connected to the first drain, and a second drain disposed above and partially overlapping the second gate. The second source has at least one second concavity in which the second drain is disposed partially. The pixel electrode connects to the second drain.03-28-2013
20130037805VERTICAL SEMICONDUCTOR DEVICE - A technology for a vertical semiconductor device having a RESURF structure, which is capable of preventing the drop of the withstand voltage when the adhesion of external electric charges occurs is provided. The vertical semiconductor device disclosed in the present specification has a cell region and a non-cell region disposed outside the cell region. This vertical semiconductor device has a diffusion layer disposed in at least part of the non-cell region. When the vertical semiconductor device is viewed in a plane, the diffusion layer has an impurity surface density higher than that satisfying a RESURF condition at an end part close to the cell region, and an impurity surface density lower than that satisfying the RESURF condition at an end part far from the cell region. When the vertical semiconductor device is viewed in a plane, a region in the diffusion layer that has the impurity surface density higher than that satisfying the RESURF condition has a greater mean gradient of the impurity surface density than a region in the diffusion layer that has the impurity surface density lower than that satisfying the RESURF condition.02-14-2013
20130037804DISPLAY DEVICE - A display device includes: a base film including plastic; an active layer on the base film, the active layer including a polysilicon layer formed by crystallizing an amorphous silicon layer using a laser; a barrier layer between the active layer and the base film; and a laser absorption layer between the barrier layer and the active layer.02-14-2013
20130032801ELECTRONIC DEVICE AND METHOD FOR MANUFACTURING SAME - The electronic device includes a substrate, a first electrode formed over a surface of the substrate, a second electrode located on an opposite side of the first electrode from the substrate so as to face the first electrode, and a functional layer interposed between the first electrode and second electrode and formed by means of anodizing a first polycrystalline semiconductor layer in an electrolysis solution so as to contain a plurality of semiconductor nanocrystals. The electronic device further includes a second polycrystalline semiconductor layer interposed between the first electrode and the functional layer so as to be in close contact with the functional layer. The second polycrystalline semiconductor layer has an anodic oxidization rate in the electrolysis solution lower than that of the first polycrystalline semiconductor layer so as to function as a stop layer for exclusively anodizing the first polycrystalline semiconductor layer.02-07-2013
20090121224DUAL GATE OF SEMICONDUCTOR DEVICE CAPABLE OF FORMING A LAYER DOPED IN HIGH CONCENTRATION OVER A RECESSED PORTION OF SUBSTRATE FOR FORMING DUAL GATE WITH RECESS CHANNEL STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A dual gate of a semiconductor device includes a semiconductor substrate divided into a cell region with a recessed gate forming area and a peripheral region with PMOS and NMOS forming areas; first and second conductive type SiGe layers, the first conductive type SiGe layer being formed over the cell region and the PMOS forming area of the peripheral region, and the second conductive type SiGe layer being formed over the NMOS forming area of the peripheral region; first and second conductive type polysilicon layers, the first conductive type polysilicon layer being formed over the first conductive type SiGe layer and the second conductive type polysilicon layer being formed over the second conductive type SiGe layer; and a metallic layer and a hard mask layer stacked over the first and second conductive type polysilicon layers.05-14-2009
20100044704VERTICAL THERMOELECTRIC STRUCTURES - A thermoelectric device is disclosed which includes metal thermal terminals protruding from a top surface of an IC, connected to vertical thermally conductive conduits made of interconnect elements of the IC. Lateral thermoelectric elements are connected to the vertical conduits at one end and heatsinked to the IC substrate at the other end. The lateral thermoelectric elements are thermally isolated by interconnect dielectric materials on the top side and field oxide on the bottom side. When operated in a generator mode, the metal thermal terminals are connected to a heat source and the IC substrate is connected to a heat sink. Thermal power flows through the vertical conduits to the lateral thermoelectric elements, which generate an electrical potential. The electrical potential may be applied to a component or circuit in the IC. The thermoelectric device may be integrated into an IC without adding fabrication cost or complexity.02-25-2010
20130026469SILICON WAFERS AND INGOTS WITH REDUCED OXYGEN CONTENT AND METHODS FOR PRODUCING THEM - Silicon nitride coated crucibles for holding melted semiconductor material and for use in preparing multicrystalline silicon ingots by a directional solidification process; methods for coating crucibles; methods for preparing silicon ingots and wafers; compositions for coating crucibles and silicon ingots and wafers with a low oxygen content.01-31-2013
20130026468RADIATION DETECTOR AND METHOD OF MANUFACTURING THE SAME - A graphite substrate is processed to have surface unevenness in a range of 1 μm to 8 μm. Thereby, a semiconductor film to be laminated on the graphite substrate has a stable film quality, and thus adhesion of the graphite substrate and the semiconductor layer can be enhanced. When an electron blocking layer is interposed between the graphite substrate and the semiconductor layer, the electron blocking layer is thin and thus the surface unevenness of the graphite substrate is transferred onto the electron blocking layer. Consequently, the electron blocking layer also has surface unevenness approximately in such range. Thus, almost the same effect as a configuration in which the semiconductor layer is directly connected to the graphite substrate can be produced.01-31-2013
20130082261SEMICONDUCTOR DEVICE - A semiconductor device comprising: a Metal Oxide Semiconductor Field Effect Transistor including: a semiconductor substrate including a first semiconductor layer of a first conductivity type; second semiconductor layers of a second conductivity type extending in a depth direction from one surface of the semiconductor substrate, and having space each other; a first diode including a fifth semiconductor layer of the second conductivity type contacting the second semiconductor layer in one surface side of the semiconductor substrate, the first semiconductor layer and the second semiconductor layers; and an anode of the second diode connected to an anode of the first diode.04-04-2013
20110006304SEMICONDUCTOR DEVICE WITH ALTERNATELY ARRANGED P-TYPE AND N-TYPE THIN SEMICONDUCTOR LAYERS AND METHOD FOR MANUFACTURING THE SAME - The invention is related to a semiconductor device with alternately arranged P-type and N-type thin semiconductor layers and method for manufacturing the same. For P-type device, the method includes trench formation, thermal oxide formation on trench sidewalls, N-type silicon formation in trenches, N-type impurity diffusion through thermal oxide into P-type epitaxial layer, oxidation of N-type silicon in trenches and oxide removal. In the semiconductor device, N-type thin semiconductor layers are formed by N-type impurity diffusion through oxide to P-type epitaxial layers, and trenches are filled with oxide. With this method, relatively low concentration impurity in high voltage device can be realized by current mass production process, and the device development cost and manufacturing cost are decreased.01-13-2011
20110012109METHOD OF FORMING A GROUP III-NITRIDE CRYSTALLINE FILM ON A PATTERNED SUBSTRATE BY HYDRIDE VAPOR PHASE EPITAXY (HVPE) - A method of depositing a high quality low defect single crystalline Group III-Nitride film. A patterned substrate having a plurality of features with inclined sidewalls separated by spaces is provided. A Group III-Nitride film is deposited by a hydride vapor phase epitaxy (HVPE) process over the patterned substrate. The HVPE deposition process forms a Group III-Nitride film having a first crystal orientation in the spaces between features and a second different crystal orientation on the inclined sidewalls. The first crystal orientation in the spaces subsequently overgrows the second crystal orientation on the sidewalls and in the process turns over and terminates treading dislocations formed in the first crystal orientation.01-20-2011
20130069064SEMICONDUCTOR DEVICE - A semiconductor device has a transistor in which a resistance is inserted between a gate electrode and a source electrode, and a diode inserted between the gate electrode and the source electrode in series in relation to the resistance.03-21-2013
20130161618SILICON-ON-INSULATOR (SOI) STRUCTURE CONFIGURED FOR REDUCED HARMONICS AND METHOD OF FORMING THE STRUCTURE - Disclosed is semiconductor structure with an insulator layer on a semiconductor substrate and a device layer is on the insulator layer. The substrate is doped with a relatively low dose of a dopant having a given conductivity type such that it has a relatively high resistivity. Additionally, a portion of the semiconductor substrate immediately adjacent to the insulator layer can be doped with a slightly higher dose of the same dopant, a different dopant having the same conductivity type or a combination thereof. Optionally, micro-cavities are created within this same portion so as to balance out any increase in conductivity due to increased doping with a corresponding increase in resistivity. Increasing the dopant concentration at the semiconductor substrate-insulator layer interface raises the threshold voltage (Vt) of any resulting parasitic capacitors and, thereby reduces harmonic behavior. Also disclosed herein are embodiments of a method for forming such a semiconductor structure.06-27-2013
20120068178TRENCH POLYSILICON DIODE - Embodiments of the present invention include a method of manufacturing a trench transistor. The method includes forming a substrate of a first conductivity type and implanting a dopant of a second conductivity type, forming a body region of the substrate. The method further includes forming a trench in the body region and depositing an insulating layer in the trench and over the body region wherein the insulating layer lines the trench. The method further includes filling the trench with polysilicon forming a top surface of the trench and forming a diode in the body region wherein a portion of the diode is lower than the top surface of the trench.03-22-2012
20090014719SEMICONDUCTOR DEVICE WITH LARGE BLOCKING VOLTAGE - A junction FET having a large gate noise margin is provided. The junction FET comprises an n01-15-2009
20120097945POLYCRYSTALLINE METAL-BASED LED HEAT DISSIPATING STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A polycrystalline metal-based LED heat dissipating structure includes a composite substrate, an insulated heat conducting layer, printed circuit layer, electric and heat conducting layer, and a polycrystalline metal-based LED. The composite substrate and the printed circuit layer are linked by the insulated heat conducting layer. The printed circuit layer and the polycrystalline metal-based LED are linked by the electric and heat conducting layer. Through the above structure, the life time of the polycrystalline metal-based LED will be prolonged and the light decadency will be prevented.04-26-2012
20090127554Semiconductor structure having multilayer of polysilicon and display panel applied with the same - A semiconductor structure includes a substrate, a first polysilicon (polysilicon) region, a second polysilicon region, an insulating layer and a third polysilicon region. The first and second polysilicon regions are formed on the substrate and spaced apart by a gap. The insulating layer formed on the substrate covers the first and second polysilicon regions. The third polysilicon region is formed on the insulating layer and disposed above the gap. When the semiconductor structure is applied to a display panel, a grain boundary of the third polysilicon region in a displaying region and a channel of an active layer intersect at an angle, and the grain boundary of the third polysilicon region in a circuit driving region is substantially parallel to the channel of the active layer.05-21-2009
20090166624CRYSTALLIZATION APPARATUS, CRYSTALLIZATION METHOD, PHASE MODULATION ELEMENT, DEVICE AND DISPLAY APPARATUS - A phase modulation element according to the present invention has a first area having a first phase value based on a phase modulation unit having a predetermined size and a second area having a second phase value based on the phase modulation unit having the predetermined size, and each phase distribution is defined by a change in area shares of the first area and the second area depending on each position.07-02-2009
20090218566LOCALIZED COMPRESSIVE STRAINED SEMICONDUCTOR - One aspect of the present subject matter relates to a method for forming strained semiconductor film. According to an embodiment of the method, a crystalline semiconductor bridge is formed over a substrate. The bridge has a first portion bonded to the substrate, a second portion bonded to the substrate, and a middle portion between the first and second portions separated from the substrate. The middle portion of the bridge is bonded to the substrate to provide a compressed crystalline semiconductor layer on the substrate. Other aspects are provided herein.09-03-2009
20110168996Polycrystalline heterostructure infrared detector - A midwave infrared lead salt photodetector manufactured by a process comprising the step of employing molecular beam epitaxy (MBE) to grow a heterostructure photoconductive detector with a wide-gap surface layer that creates a surface channel for minority carriers.07-14-2011
20090166622PLASMA PROCESSING APPARATUS AND SEMICONDUCTOR ELEMENT MANUFACTURED BY SUCH APPARATUS - When a flow rate of a diluent gas is larger than a flow rate of a reaction gas, a reaction gas introducing tube (07-02-2009
20100127259SEMICONDUCTOR DEVICE - A semiconductor device has a MOS transistor that has a gate connected to a first terminal, a source connected to a second terminal and a drain connected to a third terminal, a first polysilicon diode that has an anode connected to the first terminal, a first single-crystalline silicon diode that is connected to a cathode of the first polysilicon diode at a cathode thereof and to the second terminal at an anode thereof, has a reverse breakdown voltage lower than a reverse breakdown voltage of the first polysilicon diode, a second polysilicon diode that has a cathode connected to the first terminal and a second single-crystalline silicon diode that is connected to an anode of the second polysilicon diode at an anode thereof and to the third terminal at a cathode thereof, has a reverse breakdown voltage lower than a reverse breakdown voltage of the second polysilicon.05-27-2010
20130119383SEMICONDUCTOR DEVICE AND ELECTRONIC UNIT - Thin-film transistors and techniques for forming thin-film transistors (TFT). In some embodiments, there is provided a method of forming a TFT, comprising forming a body region of the TFT comprising an organic semiconducting material, and forming a protective layer comprising an organic insulating material. Forming the protective layer comprises contacting the body region of the TFT with a solution comprising the organic insulating material. The organic insulating material is a material that phase separates with the organic semiconducting material when the solution contacts the organic semiconducting material. In other embodiments, there is provided an apparatus comprising a TFT. The TFT comprises a body region comprising an organic semiconducting material and a protective layer contacting the body region and comprising an organic insulating material that, when a solution comprising the organic insulating material contacts the organic semiconducting material, causes the organic insulating material to phase separate with the organic semiconducting material.05-16-2013
20130119384PARASITIC LATERAL PNP TRANSISTOR AND MANUFACTURING METHOD THEREOF - A parasitic lateral PNP transistor is disclosed, in which, an N-type implanted region formed in each of two adjacent active regions forms a base region; a P-type doped polysilicon pseudo buried layer located under a shallow trench field oxide region between the two active regions serves as an emitter; and a P-type doped polysilicon pseudo buried layer located under each of the shallow trench field oxide regions on the outer side of the active regions serves as a collector region. The transistor has a C-B-E-B-C structure which alters the current path in the base region to a straight line, which can improve the current amplification capacity of the transistor and thus leads to a significant improvement of its current gain and frequency characteristics, and is further capable of reducing the area and increasing current intensity of the transistor. A manufacturing method of the parasitic lateral PNP transistor is also disclosed.05-16-2013
20100051945SILICON WAFER AND METHOD FOR PRODUCING THE SAME - A silicon wafer is produced through the steps of forming a silicon ingot by a CZ method with an interstitial oxygen concentration of not more than 7.0×1003-04-2010
20090179200Semiconductor device - A self emission silicon emission display is provided at a low price, which contains silicon and oxygen which exist in abundance on the earth as the main component and which can be easily formed by conventional silicon process. A light emission element includes a first electrode for injecting electrons, a second electrode for injecting holes, and a light emission part electrically connected to the first electrode and the second electrode, where the light emission part includes amorphous or polycrystalline silicon consisting of a single layer or plural layers and where the dimension of the silicon in at least one direction is controlled to be several nanometers.07-16-2009
20090184317ARRAY OF MUTUALLY INSULATED GEIGER-MODE AVALANCHE PHOTODIODES, AND CORRESPONDING MANUFACTURING PROCESS - An embodiment of an array of Geiger-mode avalanche photodiodes, wherein each photodiode is formed by a body of semiconductor material, having a first conductivity type, housing a first cathode region, of the second conductivity type, and facing a surface of the body, an anode region, having the first conductivity type and a higher doping level than the body, extending inside the body, and facing the surface laterally to the first cathode region and at a distance therefrom, and an insulation region extending through the body and insulating an active area from the rest of the body, the active area housing the first cathode region and the anode region. The insulation region is formed by a mirror region of metal material, a channel-stopper region having the second conductivity type, surrounding the mirror region, and a coating region, of dielectric material, arranged between the mirror region and the channel-stopper region.07-23-2009
20100200854Method for reclaiming a surface of a substrate - A method for reclaiming a surface of a substrate, wherein the surface, in particular a silicon surface, comprises a protruding residual topography, comprising at least the layer of a first material. By providing a filling material in the non-protruding areas of the surface of the substrate and the subsequent polishing, the reclaiming can be carried out such that the material consuming double-sided polishing step used in the prior art is no longer necessary.08-12-2010
20120138928Method of Manufacturing Low Resistivity Contacts on n-Type Germanium - Disclosed are methods for manufacturing semiconductor devices and the devices thus obtained. In one embodiment, the method comprises obtaining a semiconductor substrate comprising a germanium region doped with n-type dopants at a first doping level and forming an interfacial silicon layer overlying the germanium region, where the interfacial silicon layer is doped with n-type dopants at a second doping level and has a thickness higher than a critical thickness of silicon on germanium, such that the interfacial layer is at least partially relaxed. The method further includes forming over the interfacial silicon layer a layer of material having an electrical resistivity smaller than 1×1006-07-2012
20110220890Methods and Devices for Fabricating and Assembling Printable Semiconductor Elements - The invention provides methods and devices for fabricating printable semiconductor elements and assembling printable semiconductor elements onto substrate surfaces. Methods, devices and device components of the present invention are capable of generating a wide range of flexible electronic and optoelectronic devices and arrays of devices on substrates comprising polymeric materials. The present invention also provides stretchable semiconductor structures and stretchable electronic devices capable of good performance in stretched configurations.09-15-2011
20090200550METHOD FOR FORMING AN ELECTRONIC DEVICE ON A FLEXIBLE SUBSTRATE SUPPORTED BY A DETACHABLE CARRIER - A method for forming an electronic device provides a carrier formed from a composite material comprising a plastic binder and an embedded material. A substrate material is attached to the carrier. The substrate is processed to form the electronic device thereon. The substrate is then detached from the carrier to yield the resultant electronic device.08-13-2009
20120104390Germanium-Containing Release Layer For Transfer of a Silicon Layer to a Substrate - A germanium-containing layer is deposited on a single crystalline bulk silicon substrate in an ambient including a level of oxygen partial pressure sufficient to incorporate 1%-50% of oxygen in atomic concentration. The thickness of the germanium-containing layer is preferably limited to maintain some degree of epitaxial alignment with the underlying silicon substrate. Optionally, a graded germanium-containing layer can be grown on, or replace, the germanium-containing layer. An at least partially crystalline silicon layer is subsequently deposited on the germanium-containing layer. A handle substrate is bonded to the at least partially crystalline silicon layer. The assembly of the bulk silicon substrate, the germanium-containing layer, the at least partially crystalline silicon layer, and the handle substrate is cleaved within the germanium-containing layer to provide a composite substrate including the handle substrate and the at least partially crystalline silicon layer. Any remaining germanium-containing layer on the composite substrate is removed.05-03-2012
20090230393DIODE - In a pn junction diode having a conductivity modulating element provided on a first principal surface of a semiconductor substrate, when an impurity concentration of a p type impurity region is lowered to shorten a reverse recovery time, hole injection is suppressed, thereby causing a problem that a forward voltage value is increased at a certain current point. Moreover, introduction of a life time killer to shorten the reverse recovery time leads to a problem of increased leak current. On an n− type semiconductor layer that is a single crystal silicon layer, a p type polycrystalline silicon layer (p type polysilicon layer) is provided. Since the polysilicon layer has more grain boundaries than the single crystal silicon layer, an amount of holes injected into the n− type semiconductor layer from the p type polysilicon layer in forward voltage application can be suppressed. Moreover, a natural oxide film formed between the n− type semiconductor layer and the p type polysilicon layer in formation of the p type polysilicon layer can also reduce the amount of holes injected into the n− type semiconductor layer. Thus, a time to extract the holes in reverse voltage application, that is, a reverse recovery time can be shortened without using a life time killer.09-17-2009
20090095956SINGLE-CRYSTAL SILICON SUBSTRATE, SOI SUBSTRATE, SEMICONDUCTOR DEVICE, DISPLAY DEVICE, AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device of the present invention is arranged in such a manner that a MOS non-single-crystal silicon thin-film transistor including a non-single-crystal silicon thin film made of polycrystalline silicon, a MOS single-crystal silicon thin-film transistor including a single-crystal silicon thin film, and a metal wiring are provided on an insulating substrate. With this arrangement, (i) a semiconductor device in which a non-single-crystal silicon thin film and a single-crystal silicon thin-film device are formed and high-performance systems are integrated, (ii) a method of manufacturing the semiconductor device, and (iii) a single-crystal silicon substrate for forming the single-crystal silicon thin-film device of the semiconductor device are obtained.04-16-2009
20100155728EPITAXIAL WAFER AND METHOD FOR FABRICATING THE SAME - An epitaxial wafer and method for fabricating the same can prevent a bowing phenomenon of the epitaxial wafer. The epitaxial wafer includes a substrate configured to be doped in a first doping concentration; an epitaxial layer configured to be formed over a first side of the substrate and doped in a second doping concentration lower than the first doping concentration; and a back seal layer configured to be formed over a second side of the substrate and include a layer having a tensile stress, wherein the second side is opposite to the first side, of the substrate.06-24-2010
20100163872Bipolar Junction Transistor and Method of Manufacturing the Same - A bipolar junction transistor and a method of manufacturing a bipolar junction transistor are disclosed. An exemplary bipolar junction transistor includes a second conductivity type base region in a first conductivity type substrate, step-shaped recesses in the base region, a polysilicon layer doped with a first conductivity type impurity in the step-shaped recesses, and a step-shaped emitter region between the polysilicon layer and the base region.07-01-2010
20100176398ELECTRONIC DEVICE IMPROVED IN HEAT RADIATION PERFORMANCE FOR HEAT GENERATED FROM ACTIVE ELEMENT - An electronic device of the present invention includes a first substrate provided with a thin film active element, having a thickness of 200 μm or lower, and a second substrate formed with a high thermal conductivity portion. The second substrate is applied to one surface of the two surfaces of the first substrate, i.e., the surface being the side other than the side that formed with the thin film active element. The thin film active element has a maximum power consumption of 0.01 to 1 mW. The high thermal conductivity portion is a region that corresponds to the position of the thin film active element and whose thermal conductivity falls within the range from 0.1 to 4 W/cm·deg.07-15-2010
20100258799Bipolar transistor and method of manufacturing the same - A bipolar transistor at least includes a semiconductor substrate including an N10-14-2010
20100230673 Semiconductor Fuse Structure and a Method of Manufacturing a Semiconductor Fuse Structure - The invention relates to a semiconductor fuse structure comprising a substrate (09-16-2010
20100237346NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A rectifier is formed by forming a first electrode layer, a semiconductor layer and a second electrode layer. A third electrode layer is formed between the first electrode layer and the semiconductor layer, or between the second electrode layer and the semiconductor layer.09-23-2010
20100252831SQUARE PILLAR-SHAPED SWITCHING ELEMENT FOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A switching element for a memory device includes a base layer including a plurality of line-type trenches. First insulation patterns are formed on the base layer excluding the trenches. First diode portions are formed on the bottoms of the trenches in the form of a thin film. Second insulation patterns are formed on the first diode portions and are spaced apart from each other to form holes in the trenches having the first diode portions provided therein. Square pillar-shaped second diode portions are formed in the holes over the first diode portions.10-07-2010
20100127260Antireflection film, antireflection film manufacturing method, and semiconductor device using the antireflection film - To improve a transmission rate of an antireflection film, the antireflection film includes: a first silicon oxide film (2), which is formed on a silicon substrate (05-27-2010
20090166623SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - A first interconnection is formed along a groove of a substrate and on a bottom surface of the groove, and has a first thickness. A second interconnection is electrically connected to the first interconnection and has a second thickness larger than the first thickness. An acceleration sensing unit is electrically connected to the second interconnection. A sealing unit has a portion opposed to the substrate with the first interconnection therebetween, and surrounds the second interconnection and the acceleration sensing unit on the substrate. A cap is arranged on the sealing unit to form a cavity on a region of the substrate surrounded by the sealing unit. Thereby, airtightness of the cavity can be ensured and also an electric resistance of the interconnection connected to the acceleration sensing unit can be reduced.07-02-2009
20100308330Methods of Manufacturing Resistors and Structures Thereof - Methods of manufacturing resistors, methods of manufacturing semiconductor devices, and structures thereof are disclosed. In one embodiment, a method of fabricating a resistor includes forming a transistor material stack over a workpiece and patterning the transistor material stack, forming a gate of a transistor in a first region of the workpiece and leaving a portion of the transistor material stack in a second region of the workpiece. A top portion of the transistor material stack is removed in the second region, and a top portion of the workpiece is removed in the first region proximate the gate of the transistor, forming recessed regions in the workpiece in the first region. A semiconductive material is formed in the recessed regions of the workpiece in the first region and over a portion of the transistor material stack in the second region, forming a resistor in the second region.12-09-2010
20120032168PHOTONIC DEVICE AND METHOD OF MAKING THE SAME - A photonic device (02-09-2012
20110108838ELECTRO-MECHANICAL TRANSDUCER, AN ELECTRO-MECHANICAL CONVERTER, AND MANUFACTURING METHODS OF THE SAME - An electro-mechanical transducer contains a vibrating electrode (05-12-2011
20110127529SILICON-ON-INSULATOR (SOI) STRUCTURE CONFIGURED FOR REDUCED HARMONICS AND METHOD OF FORMING THE STRUCTURE - Disclosed is semiconductor structure with an insulator layer on a semiconductor substrate and a device layer is on the insulator layer. The substrate is doped with a relatively low dose of a dopant having a given conductivity type such that it has a relatively high resistivity. Additionally, a portion of the semiconductor substrate immediately adjacent to the insulator layer can be doped with a slightly higher dose of the same dopant, a different dopant having the same conductivity type or a combination thereof. Optionally, micro-cavities are created within this same portion so as to balance out any increase in conductivity due to increased doping with a corresponding increase in resistivity. Increasing the dopant concentration at the semiconductor substrate-insulator layer interface raises the threshold voltage (Vt) of any resulting parasitic capacitors and, thereby reduces harmonic behavior. Also disclosed herein are embodiments of a method for forming such a semiconductor structure.06-02-2011
20110240997Epitaxial Structures, Methods of Forming the Same, and Devices Including the Same - Epitaxial structures, methods of making epitaxial structures, and devices incorporating such epitaxial structures are disclosed. The methods and the structures employ a liquid-phase Group IVA semiconductor element precursor ink (e.g., including a cyclo- and/or polysilane) and have a relatively good film quality (e.g., texture, density and/or purity). The Group IVA semiconductor element precursor ink forms an epitaxial film or feature when deposited on a (poly)crystalline substrate surface and heated sufficiently for the Group IVA semiconductor precursor film or feature to adopt the (poly)crystalline structure of the substrate surface. Devices incorporating a selective emitter that includes the present epitaxial structure may exhibit improved power conversion efficiency relative to a device having a selective emitter made without such a structure due to the improved film quality and/or the perfect interface formed in regions between the epitaxial film and contacts formed on the film.10-06-2011
20100059748METHOD FOR MANUFACTURING THIN FILM INTEGRATED CIRCUIT, AND ELEMENT SUBSTRATE - Application form of and demand for an IC chip formed with a silicon wafer are expected to increase, and further reduction in cost is required. An object of the invention is to provide a structure of an IC chip and a process capable of producing at a lower cost. In view of the above described object, one feature of the invention is to provide the steps of forming a separation layer over an insulating substrate and forming a thin film integrated circuit having a semiconductor film as an active region over the separation layer, wherein the thin film integrated circuit is not separated. There is less limitation on the shape of a mother substrate in the case of using the insulating substrate, when compared with the case of taking a chip out of a circular silicon wafer. Accordingly, reduction in cost of an IC chip can be achieved.03-11-2010
20120241740METHOD OF FORMING A PHOTOSENSITIVE PATTERN, METHOD OF MANUFACTURING A DISPLAY SUBSTRATE, AND DISPLAY SUBSTRATE - A method of forming a photosensitive pattern on a substrate with a photosensitive layer disposed thereon may include moving at least one of the substrate and a set of micro-mirrors in a first direction, the set of micro-mirrors being disposed above the substrate and being arranged as an array, the array having a first edge extending in a second direction, the second direction being at an acute angle with respect to the first direction. The method may also include selectively turning on one or more micro-mirrors of the set of micro-mirrors according to a position of the set of micro-mirrors relative to the photosensitive layer, thereby irradiating one or more spot beams on the photosensitive layer. The photosensitive layer exposed by the spot beams is developed to form a photosensitive pattern having an edge portion extending in a third direction crossing the first and second directions.09-27-2012
20120267627POLYCRYSTALLINE TEXTURING COMPOSITION AND METHOD - An aqueous acidic composition which includes alkaline compounds, fluoride ions and oxidizing agents is provided for texturing polycrystalline semiconductors. Methods for texturing are also disclosed. The textured polycrystalline semiconductors have reduced reflectance of light incidence.10-25-2012
20080315197SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes: a substrate of single crystal silicon; a first device formed in a first region of a surface of the substrate; a first interlayer insulating film formed on the substrate; a polycrystalline silicon layer formed in a second region on the first interlayer insulating film; a second device formed in the polycrystalline silicon layer; a second interlayer insulating film formed on the first interlayer insulating film, the second interlayer insulating film covering the polycrystalline silicon layer; and a pad formed in a third region on the second interlayer insulating film. The second region includes at least part of a directly overlying zone of the first region. The third region includes at least part of a region which is the directly overlying zone of the first region and a directly overlying zone of the second region.12-25-2008
20100301335High Voltage Insulated Gate Bipolar Transistors with Minority Carrier Diverter - High power insulated gate bipolar junction transistors are provided that include a wide band gap semiconductor bipolar junction transistor (“BJT”) and a wide band gap semiconductor MOSFET that is configured to provide a current to the base of the BJT. These devices further include a minority carrier diversion semiconductor layer on the base of the BJT and coupled to the emitter of the BJT, the minority carrier diversion semiconductor layer having a conductivity type opposite the conductivity type of the base of the BJT and forming a heterojunction with the base of the BJT.12-02-2010
20120199831LIQUID CRYSTAL DISPLAY DEVICE - To provide a liquid crystal display device having high visibility and high image quality by relieving color phase irregularity. A light-shielding layer is selectively provided so as to overlap with a contact hole for electrical connection to a source region or a drain region of a thin film transistor. Alternatively, by providing an opening portion of a colored layer (color filter) with an opening so as to overlap with a contact hole, uneven alignment of liquid crystal molecules does not influence display, and a liquid crystal display having high image quality can be provided.08-09-2012
20080203389Semiconductor apparatus having temperature sensing diode - A semiconductor apparatus is provided. The semiconductor apparatus includes a semiconductor substrate and a temperature sensing diode that is disposed on a surface part of the semiconductor substrate. A relation between a forward current flowing through the temperature sensing diode and a corresponding voltage drop across the temperature sensing diode varies with temperature. The semiconductor apparatus further includes a capacitor that is coupled with the temperature sensing diode, configured to reduce noise to act on the temperature sensing diode, and disposed such that the capacitor and the temperature sensing diode have a layered structure in a thickness direction of the semiconductor substrate.08-28-2008
20100320462N-TYPE CONDUCTIVE ALUMINUM NITRIDE SEMICONDUCTOR CRYSTAL AND MANUFACTURING METHOD THEREOF - This invention provides a selfsupporting substrate which consists of a n-type conductive aluminum nitride semiconductor crystal and is useful for manufacturing the vertical conductive type AlN semiconductor device.12-23-2010
20100283053NONVOLATILE MEMORY ARRAY COMPRISING SILICON-BASED DIODES FABRICATED AT LOW TEMPERATURE - In embodiments of the invention, a method of forming a monolithic three-dimensional memory array is provided, the method including forming a first memory level that includes a plurality of memory cells, each memory cell comprising a plurality of conductors comprising aluminum or copper, and forming a silicon diode in each memory cell, wherein the silicon diode is formed at temperatures compatible with the conductors. The silicon diode may be formed using a hot wire chemical vapor deposition technique, for example. Other aspects are also described.11-11-2010
20110254002DISPLAY SUBSTRATE AND METHOD OF FABRICATING THE SAME - A display substrate is provided that can prevent the opening of an upper conduction layer. The display substrate comprises a semiconductor layer pattern formed on a substrate, a data interconnection pattern formed on the semiconductor layer pattern, a protection layer formed on the substrate and the data interconnection pattern, contact holes formed on the substrate to expose at least a portion of an upper surface of the semiconductor pattern and at least a portion of an upper surface of the data interconnection pattern, and contact electrodes formed in the contact holes to be in contact with the exposed upper surfaces of the data interconnection pattern and the semiconductor layer pattern.10-20-2011
20120146022DISPLAY PANEL, DISPLAY DEVICE, AND METHOD MANUFACTURING SAME - The invention provides a display panel and display device enabling easy connection to an external connection component depending on the type of a mounted component, and provides a display device manufacturing method allowing a simple manufacturing process. The display panel of the present invention is a display panel in which a thin film transistor array substrate and an opposed substrate are disposed opposing each other. The thin film transistor array substrate has a first routing wiring that is routed at the outer edge of the substrate, a common transfer section that is formed at a position overlapping with the first routing wiring when the substrate surface is viewed from a normal direction, and a first terminal region, having a plurality of terminals formed thereon including a terminal that is joined to the first routing wiring, at an end portion of the substrate. The opposed substrate has a second routing wiring, and a second terminal region, having a plurality of terminals formed thereon including a terminal that is joined to the second routing wiring, at an end portion of the substrate. The first routing wiring and the second routing wiring conduct with each other via the common transfer section.06-14-2012
20110186840DIAMOND SOI WITH THIN SILICON NITRIDE LAYER - A method and structure for a semiconductor device including a thin nitride layer formed between a diamond SOI layer and device silicon layer to block diffusion of ions and improve lifetime of the device silicon.08-04-2011
20100025684METHOD FOR PRODUCING GROUP III NITRIDE SEMICONDUCTOR LAYER, GROUP III NITRIDE SEMICONDUCTOR LIGHT-EMITTING DEVICE, AND LAMP - The present invention is a method for producing a group III nitride semiconductor layer in which a single crystal group III nitride semiconductor layer (02-04-2010
20110215321POLYSILICON RESISTOR AND E-FUSE FOR INTEGRATION WITH METAL GATE AND HIGH-K DIELECTRIC - A method is provided for making a resistive polycrystalline semiconductor device, e.g., a poly resistor of a microelectronic element such as a semiconductor integrated circuit. The method can include: (a) forming a layered stack including a dielectric layer contacting a surface of a monocrystalline semiconductor region of a substrate, a metal gate layer overlying the dielectric layer, a first polycrystalline semiconductor region adjacent the metal gate layer having a predominant dopant type of either n or p, and a second polycrystalline semiconductor region spaced from the metal gate layer by the first polycrystalline semiconductor region and adjoining the first polycrystalline semiconductor region; and (b) forming first and second contacts in conductive communication with the second polycrystalline semiconductor region, the first and second contacts being spaced apart so as to achieve a desired resistance. In a variation thereof, an electrical fuse is formed which includes a continuous silicide region through which a current can be passed to blow the fuse. Some of the steps of fabricating the poly resistor or the electrical fuse can be employed simultaneously in fabricating metal gate field effect transistors (FETs) on the same substrate.09-08-2011
20110215320MEMORY CELL THAT INCLUDES A CARBON-BASED MEMORY ELEMENT AND METHODS OF FORMING THE SAME - In a first aspect, a method of forming a memory cell is provided that includes: (a) forming a layer of dielectric material above a substrate; (b) forming an opening in the dielectric layer; (c) depositing a solution that includes a carbon-based switching material on the substrate; (d) rotating the substrate to cause the solution to flow into the opening and to form a carbon-based switching material layer within the opening; and (e) forming a memory element using the carbon-based switching material layer. Numerous other aspects are provided.09-08-2011
20090173939Hybrid Wafers - A hybrid wafer comprises a single-crystal Si07-09-2009
20120305918PEROVSKITE SEMICONDUCTOR THIN FILM AND METHOD OF MAKING THEREOF - Perovskite semiconductor thin films and the method of making Perovskite semiconductor thin films are disclosed. Perovskite semiconductor thin films were deposited on inexpensive substrates such as glass and ceramics. CsSnI12-06-2012
20120037903Method For Manufacturing Semiconductor Device, Semiconductor Device And Electronic Appliance - A non-single-crystal semiconductor layer is formed over a substrate, and then a single crystal semiconductor layer is formed over part of the non-single-crystal semiconductor layer. Thus, a semiconductor element of a region which requires a large area (e.g. a pixel region in a display device) can be formed using the non-single-crystal semiconductor layer, and a semiconductor element of a region which requires high speed operation (e.g. a driver circuit region in a display device) can be formed using the single crystal semiconductor layer.02-16-2012
20100025683REDUCTION OF EDGE EFFECTS FROM ASPECT RATION TRAPPING - A device includes a crystalline material within an area confined by an insulator. In one embodiment, the area confined by the insulator is an opening in the insulator having an aspect ratio sufficient to trap defects using an ART technique. Method and apparatus embodiments of the invention can reduce edge effects in semiconductor devices. Embodiments of the invention can provide a planar surface over a buffer layer between a plurality of uncoalesced ART structures.02-04-2010
20120043540Semiconductor device, method for manufacturing same, and display device - The present invention provides a semiconductor device capable of suppressing a contact failure due to an increase in contact resistance, a production method of the semiconductor device, and a display device. The present invention provides a semiconductor device which includes a thin-film diode including a crystalline semiconductor layer which includes a cathode region and an anode region, a cathode electrode connected to the cathode region, and an anode electrode connected to the anode region, the thin-film diode, the cathode electrode, and the anode electrode being disposed on a substrate, and which is featured in that the crystalline semiconductor layer includes a first low-impurity-concentration region having an impurity concentration lower than the impurity concentration of the cathode region, in that the first low-impurity-concentration region is arranged adjacent to the cathode region, and in that the cathode electrode is in contact with an area of the cathode region, the area being within 3 μm from the boundary at which the cathode region is in contact with the first low-impurity-concentration region.02-23-2012
20120205653PRESSURE SENSOR AND METHOD FOR MANUFACTURING PRESSURE SENSOR - A pressure sensor 08-16-2012
20100176397METHOD FOR PRODUCING PARTIAL SOI STRUCTURES COMPRISING ZONES CONNECTING A SUPERFICIAL LAYER AND A SUBSTRATE - The invention relates to a method for producing a semiconductor structure comprising a superficial layer, at least one embedded layer, and a support, which method comprises: 07-15-2010
20090278125CRYSTALLINE SEMICONDUCTOR FILMS, GROWTH OF SUCH FILMS AND DEVICES INCLUDING SUCH FILMS - The present invention describes an approach to grow highly crystalline semiconductor films, multilayers of semiconductor thin films on foreign substrate such as glass, quartz. Specifically, The film were grown by first forming crystalline seeds, and transferring the seeds onto the substrate, and growing continuous semiconductor film through epitaxial growth on the seeds.11-12-2009
20130015441IC CARD AND BOOKING-ACCOUNT SYSTEM USING THE IC CARD - It is an object of the present invention to provide a highly sophisticated functional IC card that can ensure security by preventing forgery such as changing a picture of a face, and display other images as well as the picture of a face. An IC card comprising a display device and a plurality of thin film integrated circuits; wherein driving of the display device is controlled by the plurality of thin film integrated circuits; a semiconductor element used for the plurality of thin film integrated circuits and the display device is formed by using a polycrystalline semiconductor film; the plurality of thin film integrated circuits are laminated; the display device and the plurality of thin film integrated circuits are equipped for the same printed wiring board; and the IC card has a thickness of from 0.05 mm to 1 mm.01-17-2013
20120211747PN JUNCTIONS AND METHODS - A PN junction includes first and second areas of silicon, wherein one of the first and second areas is n-type silicon and the other of the first and second areas is p-type silicon. The first area has one or more projections which at least partially overlap with the second area, so as to form at least one cross-over point, the cross-over point being a point at which an edge of the first area crosses over an edge of the second area.08-23-2012
20120132912SEMICONDUCTOR DEVICE - A MOSFET cell of a semiconductor device includes a polysilicon gate electrode and an n05-31-2012
20120248442METHOD OF FORMING A FINE PATTERN, DISPLAY SUBSTRATE, AND METHOD OF MANUFACTURING THE SAME USING THE METHOD OF FORMING A FINE PATTERN - A method is provided for forming a fine pattern. In the method, a first fine pattern and a first metal pattern are formed by respectively patterning a first fine pattern layer on a base substrate and a first metal layer on the first fine pattern layer. A second fine pattern layer and a second metal layer are sequentially formed over the first fine pattern and the first metal pattern. The second metal layer is patterned, so that a second metal pattern between adjacent portions of the first fine pattern. The second fine pattern layer is patterned using the second metal pattern as a mask, so that a second fine pattern is formed between adjacent portions of the first fine pattern.10-04-2012
20110198590SINGLE CRYSTAL GROUP III NITRIDE ARTICLES AND METHOD OF PRODUCING SAME BY HVPE METHOD INCORPORATING A POLYCRYSTALLINE LAYER FOR YIELD ENHANCEMENT - In a method for making a GaN article, an epitaxial nitride layer is deposited on a single-crystal substrate. A 3D nucleation GaN layer is grown on the epitaxial nitride layer by HVPE under a substantially 3D growth mode. A GaN transitional layer is grown on the 3D nucleation layer by HVPE under a condition that changes the growth mode from the substantially 3D growth mode to a substantially 2D growth mode. A bulk GaN layer is grown on the transitional layer by HVPE under the substantially 2D growth mode. A polycrystalline GaN layer is grown on the bulk GaN layer to form a GaN/substrate bi-layer. The GaN/substrate bi-layer may be cooled from the growth temperature to an ambient temperature, wherein GaN material cracks laterally and separates from the substrate, forming a free-standing article.08-18-2011
20120175613POLYCRYSTALLINE SILICON MASS AND PROCESS FOR PRODUCING POLYCRYSTALLINE SILICON MASS - The present invention provides a clean and high-purity polycrystalline silicon mass having a small content of chromium, iron, nickel, copper, and cobalt in total, which are heavy metal impurities that reduce the quality of single-crystal silicon. In the vicinity of an electrode side end of a polycrystalline silicon rod obtained by the Siemens method, the total of the chromium, iron, nickel, copper, and cobalt concentrations is high. Accordingly, before a crushing step of a polycrystalline silicon rod 07-12-2012
20120313095ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT EMPLOYING POLYSILICON DIODE - An electrostatic discharge (ESD) protection circuit includes a polysilicon diode, a switch element, and a load element. The poly silicon diode has a first terminal and a second terminal. The switch element has a control terminal coupled to the first terminal of the polysilicon diode, a first terminal coupled to the second terminal of the polysilicon diode, and a second terminal. The load element is coupled to the control terminal of the switch element and the second terminal of the switch element.12-13-2012
20120074403METHOD FOR GROWING GaN CRYSTAL AND GaN CRYSTAL SUBSTRATE - The present invention is to provide GaN crystal growing method for growing a GaN crystal with few stacking faults on a GaN seed crystal substrate having a main surface inclined at an angle of 20° to 90° from the (0001) plane, and also to provide a GaN crystal substrate with few stacking faults. A method for growing a GaN crystal includes the steps of preparing a GaN seed crystal substrate 03-29-2012
20100006840MEMS/NEMS STRUCTURE COMPRISING A PARTIALLY MONOCRYSTALLINE ANCHOR AND METHOD FOR MANUFACTURING SAME - The invention relates to a method for producing a MEMS/NEMS structure from a substrate made in a monocrystalline semiconductor material, the structure comprising a flexible mechanical element connected to the substrate by at least one anchoring zone, the method comprising the following steps: 01-14-2010
20120326148THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF - A thin film transistor array panel and a manufacturing method therefor. A shorting bar for connecting a thin film transistor with data lines is formed separate from the data lines, and then the data lines and the shorting bar are connected through a connecting member. As a result, all the data lines are floated during manufacture, so that variation in etching speed between data lines does not occur. Since variation in etching speed between the data lines can be prevented, performance deterioration of the transistor caused by a thickness difference in the lower layer of the data line can be prevented, as can resulting deterioration in display quality. Also, the influence of static electricity can be reduced or eliminated. Furthermore, since the data lines and the shorting bar are connected to each other, the generation of static electricity can be prevented or reduced, and quality testing is more readily performed.12-27-2012
20120091456CONFORMAL ELECTROMAGNETIC SENSOR (FOR DETECTION OF NON-DESTRUCTIVE IMAGING AND INVESTIGATION) - A conformal electro-magnetic (EM) detector and a method of applying such a detector are provided herein as well as variations thereof Variations include, but are not limited to, single-element, area detectors; an array of multiple active elements.04-19-2012
20100140618Sensor and method for the manufacture thereof - A sensor includes at least one micro-patterned diode pixel that has a diode implemented in, on, or under a diaphragm, and the diaphragm in turn being implemented above a cavity. The diode is contacted via supply leads that are implemented at least in part in, on, or under the diaphragm, and the diode is implemented in a polycrystalline semiconductor layer. The diode is implemented by way of two low-doped diode regions or at least one low-doped diode region. At least parts of the supply leads are implemented by way of highly doped supply lead regions of the shared polycrystalline semiconductor layer.06-10-2010
20080230779[100] Or [110] aligned, semiconductor-based, large-area, flexible, electronic devices - Novel articles and methods to fabricate the same resulting in flexible, large-area, [100] or [110] textured, semiconductor-based, electronic devices are disclosed. Potential applications of resulting articles are in areas of photovoltaic devices, flat-panel displays, thermophotovoltaic devices, ferroelectric devices, light emitting diode devices, computer hard disc drive devices, magnetoresistance based devices, photoluminescence based devices, non-volatile memory devices, dielectric devices, thermoelectric devices and quantum dot laser devices.09-25-2008
20130140566BIPOLAR JUNCTION TRANSISTOR WITH A SELF-ALIGNED EMITTER AND BASE - Methods for fabricating bipolar junction transistors with self-aligned emitter and extrinsic base, bipolar junction transistors made by the methods, and design structures for a BiCMOS integrated circuit. The bipolar junction transistor is fabricated using a sacrificial emitter pedestal that provides a sacrificial mandrel promoting self-alignment between the emitter and the extrinsic base. The sacrificial emitter pedestal is subsequently removed to open an emitter window extending to the intrinsic base. An emitter is formed in the emitter window that lands on the intrinsic base.06-06-2013
20130168676Super-Junction Structure of Semiconductor Device and Method of Forming the Same - A super-junction of a semiconductor device is formed by forming a polysilicon layer on a semiconductor substrate; patterning the polysilicon layer to form pillars for a super-junction structure; and growing an epitaxial layer between the pillars to form a continuous PN junction structure of the super-junction, which forms the super-junction structure more accurately. It is therefore possible to simplify the process for forming the super-junction without using a repetitive ion implantation process a trench process, thereby increasing productivity and device reliability.07-04-2013
20130153901BSI Image Sensor Chips and Methods for Forming the Same - A device includes semiconductor substrate having a front side and a backside. A polysilicon layer is disposed on the backside of the semiconductor substrate. The polysilicon layer includes a portion doped with a p-type impurity. A dielectric layer is disposed on the backside of the semiconductor substrate, wherein the polysilicon layer is between the semiconductor substrate and the polysilicon layer.06-20-2013
20130200372THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF - The present invention provides a structure of the TFT in which a current-voltage characteristic can be improved. The present invention refers to a thin film transistor comprising a lamination layer wherein a first conductive film, a first insulating film and a second conductive film are sequentially laminated, a semiconductor film formed so as to be in contact with the side surface of the lamination layer, and a third conductive film covering the semiconductor film through a second insulating film. The first conductive film and the second conductive film are a source electrode and a drain electrode, and a region which is in contact with the first insulating film and the third conductive film is a channel forming region in semiconductor film, and the third conductive film is a gate electrode.08-08-2013
20130207109SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes providing a substrate upon which the semiconductor device is to be disposed, heating the substrate to a first temperature that exceeds at least one of a softening point or glass transition temperature of the substrate, and depositing a polysilicon layer onto the substrate. A semiconductor device includes a substrate having at least one of a softening point, T08-15-2013

Patent applications in class NON-SINGLE CRYSTAL, OR RECRYSTALLIZED, SEMICONDUCTOR MATERIAL FORMS PART OF ACTIVE JUNCTION (INCLUDING FIELD-INDUCED ACTIVE JUNCTION)

Patent applications in all subclasses NON-SINGLE CRYSTAL, OR RECRYSTALLIZED, SEMICONDUCTOR MATERIAL FORMS PART OF ACTIVE JUNCTION (INCLUDING FIELD-INDUCED ACTIVE JUNCTION)