Class / Patent application number | Description | Number of patent applications / Date published |
257039000 | Three or more electrode device | 27 |
20090057654 | SPIN FET AND MAGNETORESISTIVE ELEMENT - A spin FET of an aspect of the present invention includes source/drain regions, a channel region between the source/drain regions, and a gate electrode above the channel region. Each of the source/drain regions includes a stack structure which is comprised of a low work function material and a ferromagnet. The low work function material is a non-oxide which is comprised of one of Mg, K, Ca and Sc, or an alloy which includes the non-oxide of 50 at % or more. | 03-05-2009 |
20090250689 | Nanowire - A method comprises applying a first electric field pulse to a nanowire comprising a channel and a charge trapping region configured to control conductivity of the channel, the first electric field pulse having a first polarity and a relatively large magnitude of integral of electric field during the pulse and, thereafter, applying at least one further electric field pulse to the nanowire, each further electric pulse having a second, opposite polarity and each respective further electric field pulse having a relatively small magnitude of integral of electric field during the pulse. | 10-08-2009 |
20100127243 | BI-LAYER PSEUDO-SPIN FIELD-EFFECT TRANSISTOR - A bi-layer pseudo-spin field-effect transistor (BiSFET) is disclosed. The BiSFET includes a first and second conduction layers separated by a tunnel dielectric. The BiSFET transistor also includes a first gate separated from the first conduction layer by an insulating dielectric layer, and a second gate separated from the second conduction layer by an insulating layer. These conduction layers may be composed of graphene. The voltages applied to the first and/or second gates can control the peak current and associated voltage value for current flow between top and bottom conduction channels, and interlayer current voltage characteristic exhibiting negative differential resistance. BiSFETs may be used to make a variety of logic gates. A clocked power supply scheme may be used to facilitate BiSFET-based logic. | 05-27-2010 |
20100258787 | FIELD EFFECT TRANSISTOR HAVING GRAPHENE CHANNEL LAYER - Provided is a field effect transistor including a graphene channel layer, and capable of increasing an on/off ratio of an operating current by using the graphene of the graphene channel layer. The field effect transistor includes: a substrate; the graphene channel layer which is disposed on a portion of the substrate and includes graphene; a first electrode disposed on a first region of the graphene channel layer and a portion of the substrate; an interlayer disposed on a second region of the graphene channel layer, which is apart from the first region, and a portion of the substrate; a second electrode disposed on the interlayer; a gate insulation layer disposed on a portion of the graphene channel layer, the first electrode, and the second electrode; and a gate electrode disposed on a portion of the gate insulation layer. | 10-14-2010 |
20110233524 | SPIN TRANSISTOR HAVING MULTIFERROIC GATE DIELECTRIC - A carrier-mediated magnetic phase change spin transistor is disclosed. In general, the spin transistor includes a Dilute Magnetic Semiconductor (DMS) channel and a gate stack formed on the DMS channel. The gate stack includes a multiferroic gate dielectric on the DMS channel, and a gate contact on a surface of the multiferroic gate dielectric opposite the DMS channel. The multiferroic gate dielectric is formed of a multiferroic material that exhibits a cross-coupling between magnetic and electric orders (i.e., magnetoelectric coupling), which in one embodiment is BiFeO | 09-29-2011 |
20120267609 | COMPLEMENTARY TUNNELING FIELD EFFECT TRANSISTOR AND METHOD FOR FORMING THE SAME - A complementary tunneling field effect transistor and a method for forming the same are provided. The complementary tunneling field effect transistor comprises: a substrate; an insulating layer, formed on the substrate; a first semiconductor layer, formed on the insulating layer and comprising first and second doped regions; a first type TFET vertical structure formed on a first part of the first doped region and a second type TFET vertical structure formed on a first part of the second doped region, in which a second part of the first doped region is connected with a second part of the second doped region and a connecting portion between the second part of the first doped region and the second part of the second doped region is used as a drain output; and a U-shaped gate structure, formed between the first type TFET vertical structure and the second type TFET vertical structure. | 10-25-2012 |
20120273763 | Topological Insulator-Based Field-Effect Transistor - A Topological INsulator-based field-effect transistor (TINFET) is disclosed. The TINFET includes a first and second gate dielectric layers separated by a topological insulator (TI) layer. A first gate contact is connected to the first gate dielectric layer on the surface that is opposite the TI layer. A second gate contact may be connected to the second gate dielectric layer on the surface that is opposite the TI layer. A first TI surface contact is connected to one surface of the TI layer, and a second TI surface contact is connected to the second surface of the TI layer. | 11-01-2012 |
20130087767 | PATTERNING CONTACTS IN CARBON NANOTUBE DEVICES - A structure includes a substrate having a carbon nanotube (CNT) disposed over a surface. The CNT is partially disposed within a protective electrically insulating layer. The structure further includes a gate stack disposed over the substrate. A first portion of a length of the CNT not covered by the protective electrically insulating layer passes through the gate stack. Source and drain contacts are disposed adjacent to the gate stack, where second and third portions of the length of CNT not covered by the protective electrically insulating layer are conductively electrically coupled to the source and drain contacts. The gate stack and the source and drain contacts are contained within the protective electrically insulating layer and within an electrically insulating organic planarization layer that is disposed over the protective electrically insulating layer. A method to fabricate a CNT-based transistor is also described. | 04-11-2013 |
20130168641 | NANO METAL PARTICLES BASED TUNNELING FIELD EFFECT TRANSISTOR AND NANO-SWITCH - A new devices structure of nano tunneling field effect transistor based on nano metal particles is introduced. The nano semiconductor device, comprising a source and a drain, wherein each of the source and drain comprise an implanted nano cluster of metal atoms, wherein the implanted nano cluster of metal atoms forming the source has an average radius in the range from about 1 to about 2 nanometers, and the implanted nano cluster of metal atoms forming the drain has an average radius in the range from about 2 to about 4 nanometers. Processes for producing the nano semiconductor device are detailed. | 07-04-2013 |
20130221330 | MULTIPLE QUANTUM DOT DEVICE AND A PRODUCTION METHOD FOR THE DEVICE - The present invention relates to a multi-quantum dot device and a method of manufacturing the multi-quantum dot device. Further specifically, present invention relates to a multi-quantum dot device including a channel configured by patterning the top silicon layer of an SOI wafer to have a P-type silicon region formed by connecting a transversal region and a longitudinal region and a plurality of N-type silicon regions; gates including a plurality of tunneling barrier gates, an end of each tunneling barrier gate is positioned on the top of a transversal side of an intersection of the transversal region and the longitudinal region of the P-type silicon region to locally control a potential in the channel; a plurality of coupling gates, an end of each coupling gate is positioned on the top of a point between the intersection and another intersection adjacent to the intersection to locally control the potential in the channel; and a plurality of sensor gates, an end of each sensor gate is positioned on the top of a center of the intersection to sense a state of a quantum dot formed at the intersection; and an inversion layer gate formed on the top of the P-type silicon region to control free electron density. | 08-29-2013 |
20130334500 | TUNNEL FIELD EFFECT TRANSISTOR DEVICE AND METHOD FOR MAKING THE DEVICE - A Tunnel Field Effect Transistor device (TFET) made of at least following layers: a highly doped drain layer, a highly doped source layer, a channel layer, a gate dielectric layer and a gate electrode layer, the gate dielectric layer extending along the source layer, and a highly doped pocket layer extending in between and along the gate dielectric layer and the source layer, characterized in that the pocket layer extends to between and along the source layer and the channel layer. | 12-19-2013 |
20140091281 | NON-VOLATILE MEMORY DEVICE EMPLOYING SEMICONDUCTOR NANOPARTICLES - Semiconductor nanoparticles are deposited on a top surface of a first insulator layer of a substrate. A second insulator layer is deposited over the semiconductor nanoparticles and the first insulator layer. A semiconductor layer is then bonded to the second insulator layer to provide a semiconductor-on-insulator substrate, which includes a buried insulator layer including the first and second insulator layers and embedded semiconductor nanoparticles therein. Back gate electrodes are formed underneath the buried insulator layer, and shallow trench isolation structures are formed to isolate the back gate electrodes. Field effect transistors are formed in a memory device region and a logic device region employing same processing steps. The embedded nanoparticles can be employed as a charge storage element of non-volatile memory devices, in which charge carriers tunnel through the second insulator layer into or out of the semiconductor nanoparticles during writing and erasing. | 04-03-2014 |
20140158990 | Tunneling Field Effect Transistor (TFET) With Ultra Shallow Pockets Formed By Asymmetric Ion Implantation and Method of Making Same - An embodiment integrated circuit device and a method of making the same. The embodiment integrated circuit includes a substrate supporting a source with a first doping type and a drain with a second doping type on opposing sides of a channel region in the substrate, and a pocket disposed in the channel region, the pocket having the second doping type and spaced apart from the drain between about 2 nm and about 15 nm. In an embodiment, the pocket has a depth of between about 1 nanometer to about 30 nanometers. | 06-12-2014 |
20140166984 | Graphene Resonant Tunneling Transistor - A graphene device having a ribbon structure with soft boundaries formed between two thin parallel transport barriers in a “railroad track” configuration. Such a structure permits transport along the ribbon, and also permits transport of electrons across the barriers by means of resonant tunneling through quasi-bound states within the railroad track confinement. The transport barriers can be of any form of so long as transport through the barriers leads to the formation of isolated resonant bands with a transport gap. In some embodiments, the transport barriers can be in the form of a pair of parallel line defects, wherein the line defects delineate the central ribbon section and the two lateral sections. In some such embodiments, the line defects are chemically decorated by the adsorption of diatomic gases. In other embodiments, the transport barriers can be formed by the application of large local potentials directly to the graphene sheet. | 06-19-2014 |
20140166985 | RECTIFYING DEVICE, TRANSISTOR, AND RECTIFYING METHOD - A rectifying device includes: a one-dimensional channel ( | 06-19-2014 |
20140175381 | TUNNELING TRANSISTOR - Devices and methods for forming a device are presented. The device includes a substrate and a fin type transistor disposed on the substrate. The transistor includes a fin structure which serves as a body of the transistor. The fin structure includes first and second end regions and an intermediate region in between the first and second end regions. A source region is disposed on the first end region, a drain region disposed in the second end region and a gate disposed on the intermediate region of the fin structure. The device includes a channel region disposed adjacent to the source region and a gate dielectric of the gate. A source tunneling junction is aligned to the gate with a controlled channel thickness T | 06-26-2014 |
20140175382 | ELECTRICAL DEVICE - An electrical device includes an insulating substrate and a magnetically doped TI quantum well film. The insulating substrate includes a first surface and a second surface. The magnetically doped topological insulator quantum well film is located on the first surface of the insulating substrate. A material of the magnetically doped topological insulator quantum well film is represented by a chemical formula of Cr | 06-26-2014 |
20140239258 | TFET with Nanowire Source - A tunnel field effect transistor (TFET) includes a source region, the source region comprising a first portion of a nanowire; a channel region, the channel region comprising a second portion of the nanowire; a drain region, the drain region comprising a portion of a silicon pad, the silicon pad being located adjacent to the channel region; and a gate configured such that the gate surrounds the channel region and at least a portion of the source region. | 08-28-2014 |
20140264289 | Structure and Method for Vertical Tunneling Field Effect Transistor with Leveled Source and Drain - The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first semiconductor mesa formed on the semiconductor substrate within the first region; a second semiconductor mesa formed on the semiconductor substrate within the second region; and a field effect transistor (FET) formed on the semiconductor substrate. The FET includes a first doped feature of a first conductivity type formed in a top portion of the first semiconductor mesa; a second doped feature of a second conductivity type formed in a bottom portion of the first semiconductor mesa, the second semiconductor mesa, and a portion of the semiconductor substrate between the first and second semiconductor mesas; a channel in a middle portion of the first semiconductor mesa and interposed between the source and drain; and a gate formed on sidewall of the first semiconductor mesa. | 09-18-2014 |
20140353593 | TUNNEL FIELD EFFECT TRANSISTOR AND METHOD FOR MAKING THEREOF - A vertical tunneling field effect transistor (TFET) and method for forming a vertical tunneling field effect transistor (TFET) is disclosed. The vertical tunneling field effect transistor TFET comprises a vertical core region, a vertical source region, a vertical drain region and a gate structure. The vertical core region is extending perpendicularly from a semiconductor substrate, having a top surface, consisting of a doped outer part and a middle part. The vertical source region of semiconducting core material comprises the doped outer part of the vertical core region. The vertical drain region of semiconducting drain material comprises along its longitudinal direction a first drain part and a second drain part, the first drain part either directly surrounding said vertical source region or directly sandwiching said vertical source region between two sub-parts of said first drain part, the second drain part located directly above and in contact with the first drain part. The gate structure comprises a gate dielectric layer directly aside of the first drain part of the vertical drain region and a gate layer directly aside of the gate dielectric layer. The second drain part is extending above the gate layer and gate dielectric layer. The vertical tunneling field effect transistor TFET further comprises a drain contact directly connected to a third drain part, the third drain part being an upper part of the second drain part of the vertical drain region. The vertical tunneling field effect transistor TFET further comprises a source contact electrically connected to the vertical source region. The vertical tunneling field effect transistor TFET further comprises a gate contact electrically connected to the gate layer | 12-04-2014 |
20150014633 | TUNNEL FIELD-EFFECT TRANSISTORS WITH A GATE-SWING BROKEN-GAP HETEROSTRUCTURE - Device structures, fabrication methods, and design structures for tunnel field-effect transistors. A drain comprised of a first semiconductor material having a first band gap and a source comprised of a second semiconductor material having a second band gap are formed. A tunnel barrier is formed between the source and the drain. The second semiconductor material exhibits a broken-gap energy band alignment with the first semiconductor material. The tunnel barrier is comprised of a third semiconductor material with a third band gap larger than the first band gap and larger than the second band gap. The third band gap is configured to bend under an external bias to assist in aligning a first energy band of the first semiconductor material with a second energy band of the second semiconductor material | 01-15-2015 |
20150034909 | ASYMMETRIC DENSE FLOATING GATE NONVOLATILE MEMORY WITH DECOUPLED CAPACITOR - A nonvolatile memory (“NVM”) bitcell includes a capacitor, an asymmetrically doped transistor, and a tunneling device. The capacitor, transistor, and tunneling device are each electrically coupled to different active regions and metal contacts. The three devices are coupled by a floating gate that traverses the three active regions. The tunneling device is formed in a native region to allow for greater dynamic range in the voltage used to induce tunneling. The FN tunneling device is used to erase the device, allowing for faster page erasure, and thus allows for rapid testing and verification of functionality. The asymmetric transistor, in conjunction with the capacitor, is used to both program and read the logical state of the floating gate. The capacitor and floating gate are capacitively coupled together, removing the need for a separate selection device to perform read and write operations. | 02-05-2015 |
20150048313 | STRIP-SHAPED GATE TUNNELING FIELD EFFECT TRANSISTOR WITH DOUBLE-DIFFUSION AND A PREPARATION METHOD THEREOF - The present invention discloses a strip-shaped gate-modulated tunneling field effect transistor with double-diffusion and a preparation method thereof, belonging to a field of CMOS field effect transistor logic device and the circuit. The tunneling field effect transistor includes a semiconductor substrate, a highly-doped source region, a highly-doped drain region, a double-diffusion source region, a gate dielectric layer, and a control gate, wherein the control gate has a strip-shaped structure with a gate length greater than a gate width, and at one side thereof is connected to the highly-doped drain region and at the other side thereof extends laterally into the highly-doped source region; a region located below the control gate is a channel region; the gate width of the control gate is less than twice width of a source depletion layer; the double-diffusion region has the same doping region as the highly-doped source region and the double-diffusion region has the same doping type as the highly-doped drain region; and the channel region located below a portion of the control gate portion in the highly-doped source region has double-diffusion source doped impurities. The TFET device according to the invention improves its performance, and the preparation method thereof is simple. | 02-19-2015 |
20150060772 | SEMICONDUCTOR DEVICE - According to one embodiment, the pair of semiconductor regions are provided respectively on a pair of side walls of the second semiconductor layer having the fin configuration to form tunnel junctions with the second semiconductor layer. The gate electrode is provided on two sides of the second semiconductor layer at the pair of side walls to oppose the tunnel junctions with the semiconductor regions interposed between the gate electrode and the tunnel junctions. The third semiconductor layer is separated from the second semiconductor layer and the semiconductor regions by the first semiconductor layer to be adjacent to the first semiconductor layer. | 03-05-2015 |
20150102289 | GATE TUNABLE TUNNEL DIODE - A gate tunable diode is provided. The gate tunable diode includes a gate dielectric formed on a gate electrode and a graphene electrode formed on the gate dielectric. Also, the gate tunable diode includes a tunnel dielectric formed on the graphene electrode and a tunnel electrode formed on the tunnel dielectric. | 04-16-2015 |
20150137079 | VERTICAL TUNNEL FIELD EFFECT TRANSISTOR (FET) - Among other things, one or more techniques for forming a vertical tunnel field effect transistor (FET), and a resulting vertical tunnel FET are provided herein. In an embodiment, the vertical tunnel FET is formed by forming a core over a first type substrate region, forming a second type channel shell around a circumference greater than a core circumference, forming a gate dielectric around a circumference greater than the core circumference, forming a gate electrode around a circumference greater than the core circumference, and forming a second type region over a portion of the second type channel shell, where the second type has a doping opposite a doping of the first type. In this manner, line tunneling is enabled, thus providing enhanced tunneling efficiency for a vertical tunnel FET. | 05-21-2015 |
20160020305 | THERMIONICALLY-OVERDRIVEN TUNNEL FETS AND METHODS OF FABRICATING THE SAME - A field effect transistor (FET) includes a nanosheet stack having first and second stacked semiconductor channel layers. The first channel layer defines a channel region of a tunnel FET, and the second channel layer defines a channel region of a thermionic FET. Source and drain regions are provided on opposite sides of the nanosheet stack such that the first and second channel layers extend therebetween. A first portion of the source region adjacent the first channel layer and a second portion of the source region adjacent the second channel layer have opposite semiconductor conductivity types. Related fabrication and operating methods are also discussed. | 01-21-2016 |