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Ballistic transport device (e.g., hot electron transistor)

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257 - Active solid-state devices (e.g., transistors, solid-state diodes)

257009000 - THIN ACTIVE PHYSICAL LAYER WHICH IS (1) AN ACTIVE POTENTIAL WELL LAYER THIN ENOUGH TO ESTABLISH DISCRETE QUANTUM ENERGY LEVELS OR (2) AN ACTIVE BARRIER LAYER THIN ENOUGH TO PERMIT QUANTUM MECHANICAL TUNNELING OR (3) AN ACTIVE LAYER THIN ENOUGH TO PERMIT CARRIER TRANSMISSION WITH SUBSTANTIALLY NO SCATTERING (E.G., SUPERLATTICE QUANTUM WELL, OR BALLISTIC TRANSPORT DEVICE)

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DocumentTitleDate
20110186818Doped graphene electronic materials - A graphene substrate is doped with one or more functional groups to form an electronic device.08-04-2011
20110186817Doped graphene electronic materials - A graphene substrate is doped with one or more functional groups to form an electronic device.08-04-2011
20130037781FIELD-EFFECT TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME - A field-effect transistor includes a semiconductor layer containing carbon nanomaterials; a first electrode and a second electrode formed in contact with the semiconductor layer; a third electrode for controlling current flowing between the first electrode and the second electrode; and an insulating layer formed between the semiconductor layer and the third electrode. The insulating layer contains an aromatic polyamide comprising a substituent containing 1 to 20 carbon atoms.02-14-2013
20130075703PEPTIDE NANOSTRUCTURES ENCAPSULATING A FOREIGN MATERIAL AND METHOD OF MANUFACTURING SAME - A composition comprising a material at least partially enclosed by a tubular, spherical or planar nanostructure composed of a plurality of peptides, wherein each of the plurality of peptides includes no more than 4 amino acids and whereas at least one of the 4 amino acids is an aromatic amino acid.03-28-2013
20130075702Tunable Hot-Electron Transfer Within a Nanostructure - Provided are multimaterial devices, such as coaxial nanowires, that effect hot photoexcited electron transfer across the interface of the materials. Modulation of the transfer rates, manifested as a large tunability of the voltage onset of negative differential resistance and of voltage-current phase, may be effected by modulating electrostatic gating, incident photon energy, and the incident photon intensity. Dynamic manipulation of this transfer rate permits the introduction and control of an adjustable phase delay within a device element.03-28-2013
20130075701PROGRAMMABLE ARRAY OF SILICON NANOWIRE FIELD EFFECT TRANSISTOR AND METHOD FOR FABRICATING THE SAME - The present invention discloses a hexagonal programmable array based on a silicon nanowire field effect transistor and a method for fabricating the same. The array includes a nanowire device, a nanowire device connection region and a gate connection region, wherein, the nanowire device has a cylinder shape, and includes a silicon nanowire channel, a gate dielectric layer, and a gate region, the nanowire channel being surrounded by the gate dielectric layer, and the gate dielectric layer being surrounded by the gate region; the nanowire devices are arranged in a hexagon shape to form programming unit, the nanowire device connection region is a connection node of three nanowire devices and secured to a silicon supporter. The present invention can achieve a complex control logic of interconnections and is suitable for a digital/analog and a mixed-signal circuit having a high integration degree and a high speed.03-28-2013
20130082243TRANSISTOR DEVICE WITH REDUCED GATE RESISTANCE - A device with reduced gate resistance includes a gate structure having a first conductive portion and a second conductive portion formed in electrical contact with the first conductive portion and extending laterally beyond the first conductive portion. The gate structure is embedded in a dielectric material and has a gate dielectric on the first conductive portion. A channel layer is provided over the first conductive portion. Source and drain electrodes are formed on opposite end portions of a channel region of the channel layer. Methods for forming a device with reduced gate resistance are also provided.04-04-2013
20130082242TRANSISTOR DEVICE WITH REDUCED GATE RESISTANCE - A device with reduced gate resistance includes a gate structure having a first conductive portion and a second conductive portion formed in electrical contact with the first conductive portion and extending laterally beyond the first conductive portion. The gate structure is embedded in a dielectric material and has a gate dielectric on the first conductive portion. A channel layer is provided over the first conductive portion. Source and drain electrodes are formed on opposite end portions of a channel region of the channel layer. Methods for forming a device with reduced gate resistance are also provided.04-04-2013
20120181510Graphene Devices and Semiconductor Field Effect Transistors in 3D Hybrid Integrated Circuits - A three-dimensional integrated circuit includes a semiconductor device, an insulator formed on the semiconductor device, an interconnect formed in the insulator, and a graphene device formed on the insulator.07-19-2012
20120181509GRAPHENE DEVICE AND METHOD FOR MANUFACTURING THE SAME - A graphene device structure and a method for manufacturing the same are provided. The graphene device structure comprises: a graphene layer; a gate region formed on the graphene layer; and a doped semiconductor region formed at one side of the gate region and connected with the graphene layer, wherein the doped semiconductor region is a drain region of the graphene device structure, and the graphene layer formed at one side of the gate region is a source region of the graphene device structure. The on/off ratio of the graphene device structure may be improved by the doped semiconductor region without increasing the band gaps of the graphene material, so that the applicability of the graphene material in CMOS devices may be enhanced without decreasing the carrier mobility of graphene materials and speed of the devices.07-19-2012
20120181508Graphene Devices and Silicon Field Effect Transistors in 3D Hybrid Integrated Circuits - A three dimensional integrated circuit includes a silicon substrate, a first source region disposed on the substrate, a first drain region disposed on the substrate, a first gate stack portion disposed on the substrate, a first dielectric layer disposed on the first source region, the first drain region, the first gate stack portion, and the substrate, a second dielectric layer formed on the first dielectric layer, a second source region disposed on the second dielectric layer, a second drain region disposed on the second dielectric layer, and a second gate stack portion disposed on the second dielectric layer, the second gate stack portion including a graphene layer.07-19-2012
20120181507SEMICONDUCTOR STRUCTURE AND CIRCUIT INCLUDING ORDERED ARRANGMENT OF GRAPHENE NANORIBBONS, AND METHODS OF FORMING SAME - A semiconductor structure including an ordered array of parallel graphene nanoribbons located on a surface of a semiconductor substrate is provided using a deterministically assembled parallel set of nanowires as an etch mask. The deterministically assembled parallel set of nanowires is formed across a gap present in a patterned graphene layer utilizing an electric field assisted assembly process. A semiconductor device, such as a field effect transistor, can be formed on the ordered array of parallel graphene nanoribbons.07-19-2012
20120181506High-Speed Graphene Transistor and Method of Fabrication by Patternable Hard Mask Materials - Graphene or carbon nanotube-based transistor devices and techniques for the fabrication thereof are provided. In one aspect, a transistor is provided. The transistor includes a substrate; a carbon-based material on the substrate, wherein a portion of the carbon-based material serves as a channel region of the transistor and other portions of the carbon-based material serve as source and drain regions of the transistor; a patterned organic buffer layer over the portion of the carbon-based material that serves as the channel region of the transistor; a conformal high-k gate dielectric layer disposed selectively on the patterned organic buffer layer; metal source and drain contacts formed on the portions of the carbon-based material that serve as the source and drain regions of the transistor; and a metal top-gate contact formed on the high-k gate dielectric layer.07-19-2012
20120181505Radiation Hardened Transistors Based on Graphene and Carbon Nanotubes - Graphene- and/or carbon nanotube-based radiation-hard transistor devices and techniques for the fabrication thereof are provided. In one aspect, a method of fabricating a radiation-hard transistor is provided. The method includes the following steps. A radiation-hard substrate is provided. A carbon-based material is formed on the substrate wherein a portion of the carbon-based material serves as a channel region of the transistor and other portions of the carbon-based material serve as source and drain regions of the transistor. Contacts are formed to the portions of the carbon-based material that serve as the source and drain regions of the transistor. A gate dielectric is deposited over the portion of the carbon-based material that serves as the channel region of the transistor. A top-gate contact is formed on the gate dielectric.07-19-2012
20130048952HOLE DOPING OF GRAPHENE - An article includes a layer of graphene having a first work function; and a metal oxide film disposed on the layer of graphene, the metal oxide film having a second work function greater than the first work function. Electrons are transferred from the layer of graphene to the metal oxide film, forming a hole accumulation layer in the layer of graphene.02-28-2013
20130048951GRAPHENE SWITCHING DEVICE HAVING TUNABLE BARRIER - According to example embodiments, a graphene switching devices has a tunable barrier. The graphene switching device may include a gate substrate, a gate dielectric on the gate substrate, a graphene layer on the gate dielectric, a semiconductor layer and a first electrode sequentially stacked on a first region of the graphene layer, and a second electrode on a second region of the graphene layer. The semiconductor layer may be doped with one of an n-type impurity and a p-type impurity. The semiconductor layer may face the gate substrate with the graphene layer being between the semiconductor layer and the gate substrate. The second region of the graphene layer may be separated from the first region on the graphene layer.02-28-2013
20130048950ON-DEMAND NANOELECTRONICS PLATFORM - A reconfigurable device includes a first insulating layer, a second insulating layer, and a nanoscale quasi one- or zero-dimensional electron gas region disposed at an interface between the first and second insulating layers. The device is reconfigurable by applying an external electrical field to the electron gas, thereby changing the conductivity of the electron gas region. A method for forming and erasing nanoscale-conducting structures employs tools, such as the tip of a conducting atomic force microscope (AFM), to form local electric fields. The method allows both isolated and continuous conducting features to be formed with a length well below 5 nm.02-28-2013
20130048949Carbonaceous Nanomaterial-Based Thin-Film Transistors - Disclosed are thin film transistor devices incorporating a thin film semiconductor derived from carbonaceous nanomaterials and a dielectric layer composed of an organic-inorganic hybrid self-assembled multilayer.02-28-2013
20120217481MOSFET with a Nanowire Channel and Fully Silicided (FUSI) Wrapped Around Gate - Nanowire-channel metal oxide semiconductor field effect transistors (MOSFETs) and techniques for the fabrication thereof are provided. In one aspect, a MOSFET includes a nanowire channel; a fully silicided gate surrounding the nanowire channel; and a raised source and drain connected by the nanowire channel. A method of fabricating a MOSFET is also provided.08-30-2012
20120217480METHOD FOR MANUFACTURING GRAPHENE ELECTRONICS - An electrical circuit structure employing graphene as a charge carrier transport layer. The structure includes a plurality of graphene layers. Electrical contact is made with one of the layer of the plurality of graphene layers, so that charge carriers travel only through that one layer. By constructing the active graphene layer within or on a plurality of graphene layers, the active graphene layer maintains the necessary planarity and crystalline integrity to ensure that the high charge carrier mobility properties of the active graphene layer remain intact.08-30-2012
20120112166GRAPHENE BASED SWITCHING DEVICE HAVING A TUNABLE BANDGAP - A method of implementing bandgap tuning of a graphene-based switching device includes subjecting a bi-layer graphene to an electric field while simultaneously subjecting the bi-layer graphene to an applied strain that reduces an interlayer spacing between the bi-layer graphene, thereby creating a bandgap in the bi-layer graphene.05-10-2012
20120305892ELECTRONIC DEVICE, METHOD OF MANUFACTURING A DEVICE AND APPARATUS FOR MANUFACTURING A DEVICE - An electronic device comprises an in-plane component formed in an organic semiconductor layer, desirably graphene, on a flexible substrate. The component is formed using imprint lithography to create a trench through the organic semiconductor layer in a roll-to-roll process. The number of process steps required is limited to allow manufacture of the device in a single integrated apparatus.12-06-2012
20090294759Stack structure comprising epitaxial graphene, method of forming the stack structure, and electronic device comprising the stack structure - Provided are a stack structure including an epitaxial graphene, a method of forming the stack structure, and an electronic device including the stack structure. The stack structure includes: a Si substrate; an under layer formed on the Si substrate; and at least one epitaxial graphene layer formed on the under layer.12-03-2009
20130062594METHOD OF ISOLATING NANOWIRES FROM A SUBSTRATE - A method is provided. The method includes forming a plurality of nanowires on a top surface of a substrate and forming an oxide layer adjacent to a bottom surface of each of the plurality of nanowires, wherein the oxide layer is to isolate each of the plurality of nanowires from the substrate.03-14-2013
20130161587GRAPHENE DEVICES AND METHODS OF MANUFACTURING THE SAME - A graphene device may include a channel layer including graphene, a first electrode and second electrode on a first region and second region of the channel layer, respectively, and a capping layer covering the channel layer and the first and second electrodes. A region of the channel layer between the first and second electrodes is exposed by an opening in the capping layer. A gate insulating layer may be on the capping layer to cover the region of the channel layer, and a gate may be on the gate insulating layer.06-27-2013
20130161588Implant Free Quantum Well Transistor, Method for Making Such an Implant Free Quantum Well Transistor and Use of Such an Implant Free Quantum Well Transistor - An implant free quantum well transistor wherein the doped region comprises an implant region having an increased concentration of dopants with respect to the concentration of dopants of adjacent regions of the substrate, the implant region being substantially positioned at a side of the quantum well region opposing the gate region.06-27-2013
20130214252CONTROLLED SYNTHESIS OF MONOLITHICALLY-INTEGRATED GRAPHENE STRUCTURE - In a method for fabricating a graphene structure, there is formed on a fabrication substrate a pattern of a plurality of distinct graphene catalyst materials. In one graphene synthesis step, different numbers of graphene layers are formed on the catalyst materials in the formed pattern. In a method for fabricating a graphene transistor, on a fabrication substrate at least one graphene catalyst material is provided at a substrate region specified for synthesizing a graphene transistor channel and at least one graphene catalyst material is provided at a substrate region specified for synthesizing a graphene transistor source, and at a substrate region specified for synthesizing a graphene transistor drain. Then in one graphene synthesis step, at least one layer of graphene is formed at the substrate region for the graphene transistor channel, and at the regions for the transistor source and drain there are formed a plurality of layers of graphene.08-22-2013
20130214253MANUFACTURING METHOD OF GRAPHENE SUBSTRATE AND GRAPHENE SUBSTRATE - The invention provides a manufacturing method of a graphene-on-insulator substrate which is mass productive, of high quality, and yet is directly usable for manufacture of semiconductor devices at a low manufacturing cost. According to the manufacturing method of a graphene substrate of the invention, a metal layer and a carbide layer are heated with the metal layer in contact with the carbide layer so that carbon in the carbide layer is dissolved into the metal layer, and then the metal layer and the carbide layer are cooled so that the carbon in the metal layer is segregated as graphene on the surface of the carbide layer.08-22-2013
20130069041METHOD FOR MANUFACTURING GRAPHENE NANO-RIBBON, MOSFET AND METHOD FOR MANUFACTURING THE SAME - A MOSFET with a graphene nano-ribbon, and a method for manufacturing the same are provided. The MOSFET comprises an insulating substrate; and an oxide protection layer on the insulating substrate. At least one graphene nano-ribbon is embedded in the oxide protection layer and has a surface which is exposed at a side surface of the oxide protection layer. A channel region is provided in each of the at least one graphene nano-ribbon. A source region and a drain regions are provided in each of the at least one graphene nano-ribbon. The channel region is located between the source region and the drain region. A gate dielectric is positioned on the at least one graphene nano-ribbon. A gate conductor on the gate dielectric. A source and drain contacts contact the source region and the drain region respectively on the side surface of the oxide protection layer.03-21-2013
20130119349GRAPHENE TRANSISTOR HAVING AIR GAP, HYBRID TRANSISTOR HAVING THE SAME, AND METHODS OF FABRICATING THE SAME - A graphene transistor includes: a gate electrode on a substrate; a gate insulating layer on the gate electrode; a graphene channel on the gate insulating layer; a source electrode and a drain electrode on the graphene channel, the source and drain electrode being separate from each other; and a cover that covers upper surfaces of the source electrode and the drain electrode and forms an air gap above the graphene channel between the source electrode and the drain electrode.05-16-2013
20110017979HIGH-PERFORMANCE GATE OXIDES SUCH AS FOR GRAPHENE FIELD-EFFECT TRANSISTORS OR CARBON NANOTUBES - An apparatus or method can include forming a graphene layer including a working surface, forming a polyvinyl alcohol (PVA) layer upon the working surface of the graphene layer, and forming a dielectric layer upon the PVA layer. In an example, the PVA layer can be activated and the dielectric layer can be deposited on an activated portion of the PVA layer. In an example, an electronic device can include such apparatus, such as included as a portion of graphene field-effect transistor (GFET), or one or more other devices.01-27-2011
20110278545Manufacture of Graphene-Based Apparatus - An apparatus including: a stacked structure including a first substrate having a flat surface; a flat first graphene layer adjacent the flat surface of the first substrate; a flat second graphene layer adjacent the flat first graphene layer; and a second substrate having a flat surface adjacent the flat second graphene layer. An apparatus including: a stacked structure including a substrate having a flat upper surface; a flat lower patterned layer overlying the flat upper surface of the substrate and including at least one patterned electrode; a flat lower graphene layer overlying the flat lower patterned layer; a flat upper graphene layer overlying the flat lower graphene layer; and a flat upper patterned layer overlying the flat upper graphene layer and including at least one patterned electrode.11-17-2011
20110140088PHASE COHERENT SOLID STATE ELECTRON GYROSCOPE ARRAY - An apparatus and method is disclosed which may comprise an electron gyroscope, which may comprise an interferometer array which may comprise interferometer rings formed from a sheet of graphene. Each interferometer ring in the interferometer array may have a half-circumference shorter in length than the ballistic length for an electron in graphene.06-16-2011
20110291075FIELD EFFECT TRANSISTOR, METHOD FOR MANUFACTURING THE SAME, AND BIOSENSOR - Disclosed is a carbon nanotube field effect transistor which stably exhibits excellent electrical conduction properties. Also disclosed are a method for manufacturing the carbon nanotube field effect transistor, and a biosensor comprising the carbon nanotube field effect transistor. First of all, an silicon oxide film is formed on a contact region of a silicon substrate by an LOCOS method. Next, an insulating film, which is thinner than the silicon oxide film on the contact region, is formed on a channel region of the silicon substrate. Then, after arranging a carbon nanotube, which forms a channel, on the silicon substrate, the carbon nanotube is covered with a protective film. Finally, a source electrode and a drain electrode are formed, and the source electrode and the drain electrode are electrically connected to the carbon nanotube, respectively. A field effect transistor manufactured by these processes stably exhibits excellent electrical conduction properties since the carbon nanotube, which serves as the channel, is not contaminated.12-01-2011
20110062422Systems And Methods For Forming Defects On Graphitic Materials And Curing Radiation-Damaged Graphitic Materials - Systems and methods are disclosed herein for forming defects on graphitic materials. The methods for forming defects include applying a radiation reactive material on a graphitic material, irradiating the applied radiation reactive material to produce a reactive species, and permitting the reactive species to react with the graphitic material to form defects. Additionally, disclosed are methods for removing defects on graphitic materials.03-17-2011
20110062421SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - First semiconductor layers are in source/drain regions on the semiconductor substrate. A second semiconductor layer comprises first portions on the first semiconductor layers and a second portion in a linear form in a channel region between the source/drain regions. A gate electrode is around the second portion of the second semiconductor layer via an insulating film. A film thickness of the second portion of the second semiconductor layer is smaller than a film thickness of the first portion of the second semiconductor layer.03-17-2011
20110168981NANOTUBE ARRAY BIPOLAR TRANSISTORS - Carbon nanotube (CNT)-based devices and technology for their fabrication are disclosed. The planar, multiple layer deposition technique and simple methods of change of the nanotube conductivity type during the device processing are utilized to provide a simple and cost effective technology for large scale circuit integration. Such devices as p-n diode, CMOS-like circuit, bipolar transistor, light emitting diode and laser are disclosed, all of them are expected to have superior performance then their semiconductor-based counterparts due to excellent CNT electrical and optical properties. When fabricated on semiconductor wafers, the CNT-based devices can be combined with the conventional semiconductor circuit elements, thus producing hybrid devices and circuits.07-14-2011
20120292597Self-Aligned Contacts in Carbon Devices - A semiconductor device includes a carbon layer disposed on a substrate, a gate stack disposed on a portion of the carbon layer, a first cavity defined by the carbon layer and the substrate, a second cavity defined by the carbon layer and the substrate, a source region including a first conductive contact disposed in the first cavity, a drain region including a second conductive contact disposed in the second cavity.11-22-2012
20120292598EPITAXIAL SOURCE/DRAIN CONTACTS SELF-ALIGNED TO GATES FOR DEPOSITED FET CHANNELS - A method of forming a self-aligned device is provided and includes depositing carbon nanotubes (CNTs) onto a crystalline dielectric substrate, isolating a portion of the crystalline dielectric substrate encompassing a location of the CNTs, forming gate dielectric and gate electrode gate stacks on the CNTs while maintaining a structural integrity thereof and forming epitaxial source and drain regions in contact with portions of the CNTs on the crystalline dielectric substrate that are exposed from the gate dielectric and gate electrode gate stacks.11-22-2012
20120292596Graphene Base Transistor Having Compositionally-Graded Collector Barrier Layer - A junction transistor, comprising, on a substrate an emitter layer, a collector layer, and a base layer that comprises a graphene layer, wherein an emitter barrier layer is arranged between the base layer and the emitter layer, and a collector barrier layer is arranged between the base and the collector layers and adjacent to the graphene layer, characterized in that the collector barrier layer is a compositionally graded material layer, which has an electron affinity that decreases in a direction pointing from the base layer to the collector layer.11-22-2012
20130119350SEMICONDUCTOR STRUCTURE AND CIRCUIT INCLUDING ORDERED ARRANGEMENT OF GRAPHENE NANORIBBONS, AND METHODS OF FORMING SAME - A semiconductor structure including an ordered array of parallel graphene nanoribbons located on a surface of a semiconductor substrate is provided using a deterministically assembled parallel set of nanowires as an etch mask. The deterministically assembled parallel set of nanowires is formed across a gap present in a patterned graphene layer utilizing an electric field assisted assembly process. A semiconductor device, such as a field effect transistor, can be formed on the ordered array of parallel graphene nanoribbons.05-16-2013
20100200840GRAPHENE-BASED TRANSISTOR - A graphene layer is formed on a surface of a silicon carbide substrate. A dummy gate structure is formed over the fin, in the trench, or on a portion of the planar graphene layer to implant dopants into source and drain regions. The dummy gate structure is thereafter removed to provide an opening over the channel of the transistor. Threshold voltage adjustment implantation may be performed to form a threshold voltage implant region directly beneath the channel, which comprises the graphene layer. A gate dielectric is deposited over a channel portion of the graphene layer. After an optional spacer formation, a gate conductor is formed by deposition and planarization. The resulting graphene-based field effect transistor has a high carrier mobility due to the graphene layer in the channel, low contact resistance to the source and drain region, and optimized threshold voltage and leakage due to the threshold voltage implant region.08-12-2010
20100200839GRAPHENE GROWN SUBSTRATE AND ELECTRONIC/PHOTONIC INTEGRATED CIRCUITS USING SAME - A graphene-on-oxide substrate according to the present invention includes: a substrate having a metal oxide layer formed on its surface; and, formed on the metal oxide layer, a graphene layer including at least one atomic layer of the graphene. The graphene layer is grown generally parallel to the surface of the metal oxide layer, and the inter-atomic-layer distance between the graphene atomic layer adjacent to the surface of the metal oxide layer and the surface atomic layer of the metal oxide layer is 0.34 nm or less. Preferably, the arithmetic mean surface roughness Ra of the metal oxide layer is 1 nm or less.08-12-2010
20120068161METHOD FOR FORMING GRAPHENE USING LASER BEAM, GRAPHENE SEMICONDUCTOR MANUFACTURED BY THE SAME, AND GRAPHENE TRANSISTOR HAVING GRAPHENE SEMICONDUCTOR - A method for forming graphene includes introducing a substrate and a carbon-containing reactant source into a chamber, and radiating a laser beam onto the substrate to decompose the carbon-containing reactant source and form graphene over the substrate using carbon atoms generated by decomposition of the carbon-containing reactant source. A carbon-containing gas (methane) decomposes upon radiation of a laser beam. The carbon-containing gas has a decomposition rate on the order of femtoseconds and the laser beam has a pulse on the order of nanoseconds or more. The graphene is grown in a single layer along the surface of the substrate. Then, the graphene is selectively patterned using a laser beam to form a desired pattern.03-22-2012
20120068159NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a nonvolatile semiconductor memory device includes a first memory portion. The first memory portion includes a first base semiconductor layer, a first electrode, a first channel semiconductor layer, a first base tunnel insulating film, a first channel tunnel insulating, a first charge retention layer and a first block insulating film. The first channel semiconductor layer is provided between the first base semiconductor layer and the first electrode, and includes a first channel portion. The first base tunnel insulating film is provided between the first base semiconductor layer and the first channel semiconductor layer. The first channel tunnel insulating film is provided between the first electrode and the first channel portion. The first charge retention layer is provided between the first electrode and the first channel tunnel insulating film. The first block insulating film is provided between the first electrode and the first charge retention layer.03-22-2012
20110227044TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME - In one embodiment, a transistor includes: a substrate; a source electrode formed on the substrate; a drain electrode formed on the substrate; a graphene film formed between the source electrode and the drain electrode, the graphene film having a semiconductor region including a source side end and a conductor region including a drain side end, a width of the source side end of the graphene film in a channel width direction being narrower than a width of the drain side end of the graphene film in the channel width direction; and a gate electrode formed via a gate insulating film on the semiconductor region of the graphene film and the conductor region of the graphene film. The source electrode is connected to the source side end of the graphene film with a Schottky contact, and the drain electrode is connected to the drain side end of the graphene film with an ohmic contact.09-22-2011
20100258786SELF-ASSEMBLED ORGANIC MONOLAYERS ON GRAPHENE AND METHODS OF MAKING AND USING - Self-assembled organic monolayers on epitaxial graphene are described. The organic molecules are perylene derivatives including 3,4,9,10-perylene-tetracarboxylic dianhydride (PTCDA) molecules arranged in a herringbone phase and/or molecules are of the following formula:10-14-2010
20120187377GRAPHENE-BASED DEVICE AND METHODS OF FORMING THE SAME - A graphene-based device can be characterized as including a first electrode comprising graphene, a second electrode comprising graphene, and a potential barrier. The first electrode is physically separated from the second electrode by the potential barrier. The first electrode, second electrode and potential barrier are configured such that the graphene-based device can exhibit non-linear I-V characteristics under application of a voltage bias between the first electrode and the second electrode.07-26-2012
20110108806Method to Modify the Conductivity of Graphene - A gated electrical device includes a non-conductive substrate and a graphene structure disposed on the non-conductive substrate. A metal gate is disposed directly on a portion of the graphene structure. The metal gate includes a first metal that has a high contact resistance with graphene. Two electrical contacts are each placed on the graphene structure so that the metal gate is disposed between the two electrical contacts. In a method of making a gated electrical device, a graphene structure is placed onto a non-conductive substrate. A metal gate is deposited directly on a portion of the graphene structure. Two electrical contacts are deposited on the graphene structure so that the metal gate is disposed between the two electrical contacts.05-12-2011
20120032150Semiconductor component, method of producing a semiconductor component, semiconductor device - Semiconductor component comprising:02-09-2012
20110114919SELF-ALIGNED GRAPHENE TRANSISTOR - A graphene field effect transistor includes a gate stack, the gate stack including a seed layer, a gate oxide formed over the seed layer, and a gate metal formed over the gate oxide; an insulating layer; and a graphene sheet displaced between the seed layer and the insulating layer.05-19-2011
20120068160SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device according to an embodiment, includes a catalytic metal film, a graphene film, a contact plug, and an adjustment film. The catalytic metal film is formed above a substrate. The graphene film is formed on the catalytic metal film. The contact plug is connected to the graphene film. The adjustment film is formed in a region other than a region connected to the contact plug of a surface of the graphene film to adjust a Dirac point position in a same direction as the region connected to the contact plug with respect to a Fermi level.03-22-2012
20110175060GRAPHENE GROWN SUBSTRATE AND ELECTRONIC/PHOTONIC INTEGRATED CIRCUITS USING SAME - A substrate having a graphene film grown thereon according to the present invention includes: a base substrate; a patterned aluminum oxide film formed on the base substrate, the patterned aluminum oxide film having an average composition of Al07-21-2011
20120145999SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - Provided are semiconductor devices and methods of manufacturing the same. The semiconductor device includes a substrate including a first top surface, a second top surface lower in level than the first top surface, and a first perpendicular surface disposed between the first and second top surfaces, a first source/drain region formed under the first top surface, a first nanowire extended from the first perpendicular surface in one direction and being spaced apart from the second top surface, a second nanowire extended from a side surface of the first nanowire in the one direction, being spaced apart from the second top surface, and including a second source/drain region, a gate electrode on the first nanowire, and a dielectric layer between the first nanowire and the gate electrode.06-14-2012
20110042650SINGLE AND FEW-LAYER GRAPHENE BASED PHOTODETECTING DEVICES - A photodetector which uses single or multi-layer graphene as the photon detecting layer is disclosed. Multiple embodiments are disclosed with different configurations of electrodes. In addition, a photodetector array comprising multiple photodetecting elements is disclosed for applications such as imaging and monitoring.02-24-2011
20110163298Graphene and Hexagonal Boron Nitride Devices - Graphene layers, hexagonal boron nitride (hBN) layers, as well as other materials made of primarily sp2 bonded atoms and associated methods are disclosed. In one aspect, the present invention provides graphene and hBN devices. In one aspect, for example, an electronic device is provided including a graphene layer and a planar hBN layer operably associated with the graphene layer and forming a functional interface therebetween. Numerous functional interfaces are contemplated, depending on the desired functionality of the device.07-07-2011
20120199815SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device including a graphene layer and a method of manufacturing the same are disclosed. A method in which graphene is grown on a catalyst metal by a chemical vapor deposition or the like is known. However, the graphene cannot be used as a channel, since the graphene is in contact with the catalyst metal, which is conductive. There is disclosed a method in which a catalyst film (08-09-2012
20110089404Microfabrication of Carbon-based Devices Such as Gate-Controlled Graphene Devices - A graphene device includes a graphene layer and a back gate electrode connected to apply a global electrical bias to the graphene from a first surface of the graphene. At least two graphene device electrodes are each connected to a corresponding and distinct region of the graphene at a second graphene surface. A dielectric layer blanket-coats the second graphene surface and the device electrodes. At least one top gate electrode is disposed on the dielectric layer and extends over a distinct one of the device electrodes and at least a portion of a corresponding graphene region. Each top gate electrode is connected to apply an electrical charge carrier bias to the graphene region over which that top gate electrode extends to produce a selected charge carrier type in that graphene region. Such a carbon structure can be exposed to a beam of electrons to compensate for extrinsic doping of the carbon.04-21-2011
20120146000Omega Shaped Nanowire Field Effect Transistors - A method for forming a nanowire field effect transistor (FET) device includes forming a nanowire on a semiconductor substrate, forming a first gate structure on a first portion of the nanowire, forming a first protective spacer adjacent to sidewalls of the first gate structure and over portions of the nanowire extending from the first gate structure, removing exposed portions of the nanowire left unprotected by the first spacer, and epitaxially growing a doped semiconductor material on exposed cross sections of the nanowire to form a first source region and a first drain region.06-14-2012
20110095268TRANSISTOR AND FLAT PANEL DISPLAY INCLUDING THIN FILM TRANSISTOR - A transistor includes at least three terminals comprising a gate electrode, a source electrode and a drain electrode, an insulating layer disposed on a substrate, and a semiconductor layer disposed on the substrate, wherein a current which flows between the source electrode and the drain electrode is controlled by application of a voltage to the gate electrode, where the semiconductor layer includes a graphene layer and at least one of a metal atomic layer and a metal ion layer, and where the metal atomic layer or the metal ion layer is interposed between the graphene layer and the insulating layer.04-28-2011
20130009133A GRAPHENE TRANSISTOR WITH A SELF-ALIGNED GATE - A transistor structure is provided which includes a graphene layer located on an insulating layer, a first metal portion overlying a portion of the graphene layer, a second metal portion contacting and overhanging the first metal portion, a first electrode contacting a portion of the graphene layer and laterally offset from a first sidewall of the first metal portion by a lateral spacing, and a second electrode contacting another portion of the graphene layer and laterally offset from a second sidewall of the first metal portion by the lateral spacing.01-10-2013
20080217603Hot electron transistor and semiconductor device including the same - A hot electron transistor includes a collector layer, a base layer, an emitter layer, a collector barrier layer formed between the collector layer and the base layer, and an emitter barrier layer formed between the base layer and the emitter layer. An energy barrier between the emitter barrier layer and the emitter layer does not substantially exist and the height of an energy barrier of the collector barrier layer is lower than the height of an energy barrier of the emitter barrier layer.09-11-2008
20110215300GRAPHENE BASED THREE-DIMENSIONAL INTEGRATED CIRCUIT DEVICE - A three-dimensional (3D) integrated circuit (IC) structure includes a first layer of graphene formed over a substrate; a first level of one or more active devices formed using the first layer of graphene; an insulating layer formed over the first level of one or more active devices; a second layer of graphene formed over the insulating layer; and a second level of one or more active devices formed using the second layer of graphene, the second level of one or more active devices electrically interconnected with the first level of one or more active devices.09-08-2011
20120146001ULTRATHIN SPACER FORMATION FOR CARBON-BASED FET - A carbon-based field effect transistor (FET) includes a substrate; a carbon layer located on the substrate, the carbon layer comprising a channel region, and source and drain regions located on either side of the channel region; a gate electrode located on the channel region in the carbon layer, the gate electrode comprising a first dielectric layer, a gate metal layer located on the first dielectric layer, and a nitride layer located on the gate metal layer; and a spacer comprising a second dielectric layer located adjacent to the gate electrode, wherein the spacer is not located on the carbon layer.06-14-2012
20120305893TRANSISTOR DEVICE - The invention provides transistor device comprising a source, a drain and a connecting channel, the channel is a nano-structure device adapted to allow current flow between the source and drain. The channel comprises an ultra-high doping concentration and is of the same polarity as in the source and/or drain. Essentially the transistor device of the present invention acts as a junctionless, highly-doped gated resistor. In the context of optimal performance of the transistor high doping means equal to or exceeds 1×1012-06-2012
20110315962NANOSENSORS - Electrical devices comprised of nanowires are described, along with methods of their manufacture and use. The nanowires can be nanotubes and nanowires. The surface of the nanowires may be selectively functionalized Nanodetector devices are described.12-29-2011
20110101309GRAPHENE BASED SWITCHING DEVICE HAVING A TUNABLE BANDGAP - A method of implementing bandgap tuning of a graphene-based switching device includes subjecting a bi-layer graphene to an electric field while simultaneously subjecting the bi-layer graphene to an applied strain that reduces an interlayer spacing between the bi-layer graphene, thereby creating a bandgap in the bi-layer graphene.05-05-2011
20110156007COMPLEMENTARY LOGIC GATE DEVICE - Provided is a complementary logical gate device represented by a silicon CMOS logical circuit among semiconductor integrated logical circuits which can effectively solve the problem of the speed performance limit of an ultra-large scale integration and an ultra-low power consumption type logical circuit. The complementary logical gate includes an electron running layer formed by grapheme without using an n-channel FET or a p-channel FET, has the ambipolar characteristic, and uses only two FET having different threshold values, i.e., a first FET and a second FET. The first FET has a gate electrode short-circuited to a gate electrode of the second FET so as to constitute an input terminal. The first FET has a source electrode set to a low potential. The first FET has a drain electrode connected to a source electrode of the second FET so as to constitute an output terminal. The second FET has a drain electrode set to a high potential.06-30-2011
20120007054Self-Aligned Contacts in Carbon Devices - A method for forming a semiconductor device includes forming a carbon material on a substrate, forming a gate stack on the carbon material, removing a portion of the substrate to form at least one cavity defined by a portion of the carbon material and the substrate, and forming a conductive contact in the at least one cavity.01-12-2012
20120012817Semiconductor devices and methods of manufacturing an operating same - A semiconductor device and methods of manufacturing and operating the semiconductor device may be disclosed. The semiconductor device may comprise different nanostructures. The semiconductor device may have a first element formed of nanowires and a second element formed of nanoparticles. The nanowires may be ambipolar carbon nanotubes (CNTs). The first element may be a channel layer. The second element may be a charge trap layer. In this regard, the semiconductor device may be a transistor or a memory device.01-19-2012
20100038629Anisotropic Semiconductor Film and Method of Production Thereof - The present invention relates generally to the field of macro- and microelectronics with the potential for large-scale integration, optics, communications, and computer technology and particularly to the materials for these and other related fields. The present invention provides an anisotropic semiconductor film on a substrate, comprising at least one solid layer of material that comprises predominantly planar graphene-like carbon-based structures and possesses anisotropy of conductivity, and wherein the layer thickness is in a range from approximately 5 nm to 1000 nm.02-18-2010
20110089403Electronic device using a two-dimensional sheet material, transparent display and methods of fabricating the same - An electronic device, a transparent display and methods for fabricating the same are provided, the electronic device including a first, a second and a third element each formed of a two-dimensional (2D) sheet material. The first, second, and third elements are stacked in a sequential order or in a reverse order. The second element is positioned between the first element and the third element. The second element has an insulator property, the first and third elements have a metal property or a semiconductor property.04-21-2011
20120161106PHOTODETECTOR USING A GRAPHENE THIN FILM AND NANOPARTICLES, AND METHOD FOR PRODUCING THE SAME - Provided are a photodetector (PD) using a graphene thin film and nanoparticles and a method of fabricating the same. The PD includes a graphene thin film having a sheet shape formed by means of a graphene deposition process using a vapor-phase carbon (C) source and a nanoparticle layer formed on the graphene thin film and patterned to define an electrode region of the graphene thin film, the nanoparticle layer being formed of nanoparticles without a matrix material. The PD has a planar structure using the graphene thin film as a channel and an electrode and using nanoparticles as a photovoltaic material (capable of forming electron-hole pairs due to photoelectron-motive force caused by ultraviolet (UV) light). Since the PD has a very simple structure, the PD may be fabricated at low cost with high productivity. Also, the PD includes the graphene thin film to reduce power consumption.06-28-2012
20100289005AMORPHOUS MULTI-COMPONENT METALLIC THIN FILMS FOR ELECTRONIC DEVICES - An electronic structure comprising: (a) a first metal layer; (b) a second metal layer; (c) and at least one insulator layer located between the first metal layer and the second metal layer, wherein at least one of the metal layers comprises an amorphous multi-component metallic film. In certain embodiments, the construct is a metal-insulator-metal (MIM) diode.11-18-2010
20120168724TRANSFER-FREE BATCH FABRICATION OF SINGLE LAYER GRAPHENE DEVICES - A method of manufacturing one or more graphene devices is disclosed. A thin film growth substrate is formed directly on a device substrate. Graphene is formed on the thin film growth substrate. A transistor is also disclosed, having a device substrate and a source supported by the device substrate. The transistor also has a drain separated from the source and supported by the device substrate. The transistor further has a single layer graphene (SLG) channel grown partially on and coupling the source and the drain. The transistor also has a gate aligned with the SLG channel, and a gate insulator between the gate and the SLG channel. Integrated circuits and other apparati having a device substrate, a thin film growth substrate formed directly on at least a portion of the device substrate, and graphene formed directly on at least a portion of the thin film growth substrate are also disclosed.07-05-2012
20120168722Graphene Electronic Device Including A Plurality Of Graphene Channel Layers - Graphene electronic devices may include a gate electrode on a substrate, a first gate insulating film covering the gate electrode, a plurality of graphene channel layers on the substrate, a second gate insulating film between the plurality of graphene channel layers, and a source electrode and a drain electrode connected to both edges of each of the plurality of graphene channel layers.07-05-2012
20120168723ELECTRONIC DEVICES INCLUDING GRAPHENE AND METHODS OF FORMING THE SAME - Methods of forming a graphene layer are provided. The method includes sequentially forming a seed layer and a protection layer on a substrate, patterning the protection layer and the seed layer to form a protection pattern and a seed pattern having a first length in a first direction and a second length in a second direction perpendicular to the first direction, and forming a graphene material on at least one of both sidewalls of the seed pattern. The second length is greater than the first length. Related devices are also provided.07-05-2012
20120168721GRAPHENE FORMATION ON DIELECTRICS AND ELECTRONIC DEVICES FORMED THEREFROM - Methods of forming a graphene-based device are provided. According to an embodiment, a graphene-based device can be formed by subjecting a substrate having a dielectric formed thereon to a chemical vapor deposition (CVD) process using a cracked hydrocarbon or a physical vapor deposition (PVD) process using a graphite source; and performing an annealing process. The annealing process can be performed to temperatures of 1000 K or more. The cracked hydrocarbon of the CVD process can be cracked ethylene. In accordance with one embodiment, the application of the cracked ethylene to a MgO(111) surface followed by an annealing under ultra high vacuum conditions can result in a structure on the MgO(111) surface of an ordered graphene film with an oxidized carbon-containing interfacial layer therebetween. In another embodiment, the PVD process can be used to form single or multiple monolayers of graphene.07-05-2012
20120211727Method of Producing Precision Vertical and Horizontal Layers in a Vertical Semiconductor Structure - The present invention relates to providing layers of different thickness on vertical and horizontal surfaces (08-23-2012
20120132893Graphene Electronic Devices - A graphene electronic device includes a gate electrode, a gate oxide disposed on the gate electrode, a graphene channel layer formed on the gate oxide, and a source electrode and a drain electrode respectively disposed on both ends of the graphene channel layer. In the graphene channel layer, a plurality of nanoholes are arranged in a single line in a width direction of the graphene channel layer.05-31-2012
20120313079GRAPHENE ELECTRONIC DEVICES HAVING MULTI-LAYERED GATE INSULATING LAYER - A graphene electronic device includes a multi-layered gate insulating layer between a graphene channel layer and a gate electrode. The multi-layered gate insulating layer includes an organic insulating layer and an inorganic insulating layer on the organic insulating layer.12-13-2012
20120248414Semiconductor Device, Method Of Manufacturing The Same, And Electronic Device Including The Semiconductor Device - An example embodiment relates to a semiconductor device including a semiconductor element. The semiconductor element may include a plurality of unit layers spaced apart from each other in a vertical direction. Each unit layer may include a patterned graphene layer. The patterned graphene layer may be a layer patterned in a nanoscale. The patterned graphene layer may have a nanomesh or nanoribbon structure. The semiconductor device may be a transistor or a diode. An example embodiment relates to a method of making a semiconductor device including a semiconductor element.10-04-2012
20120248417DOUBLE GATE NANOSTRUCTURE FET - A Field Effect Transistor (FET) semiconductor device comprising at least one nanostructure, comprises at least a uniformly doped beam-shaped nanostructure having two major surfaces, a gate electrode provided at either major surface of the nanostructure, and an insulating layer between each of the major surfaces of the nanostructure and the gate electrodes to form a double gate nanostructure pinch-off FET. It is an advantage of such FET that pinch-off voltage and current of the FET can be independently tuned.10-04-2012
20100051907Devices including graphene layers epitaxially grown on single crystal substrates - An electronic device comprises a body including a single crystal region on a major surface of the body. The single crystal region has a hexagonal crystal lattice that is substantially lattice-matched to graphene, and a at least one epitaxial layer of graphene is disposed on the single crystal region. In a currently preferred embodiment, the single crystal region comprises multilayered hexagonal BN. A method of making such an electronic device comprises the steps of: (a) providing a body including a single crystal region on a major surface of the body. The single crystal region has a hexagonal crystal lattice that is substantially lattice-matched to graphene, and (b) epitaxially forming a at least one graphene layer on that region. In a currently preferred embodiment, step (a) further includes the steps of (a1) providing a single crystal substrate of graphite and (a2) epitaxially forming multilayered single crystal hexagonal BN on the substrate. The hexagonal BN layer has a surface region substantially lattice-matched to graphene, and step (b) includes epitaxially forming at least one graphene layer on the surface region of the hexagonal BN layer. Applications to FETs are described.03-04-2010
20120175595Graphene Electronic Device And Method Of Fabricating The Same - A graphene electronic device includes a graphene channel layer on a substrate, a source electrode on an end portion of the graphene channel layer and a drain electrode on another end portion of the graphene channel layer, a gate oxide on the graphene channel layer and between the source electrode and the drain electrode, and a gate electrode on the gate oxide. The gate oxide has substantially the same shape as the graphene channel layer between the source electrode and the drain electrode.07-12-2012
20120175594Graphene Devices with Local Dual Gates - An electronic device comprises an insulator, a local first gate embedded in the insulator with a top surface of the first gate being substantially coplanar with a surface of the insulator, a first dielectric layer formed over the first gate and insulator, and a channel. The channel comprises a bilayer graphene layer formed on the first dielectric layer. The first dielectric layer provides a substantially flat surface on which the channel is formed. A second dielectric layer formed over the bilayer graphene layer and a local second gate formed over the second dielectric layer. Each of the local first and second gates is capacitively coupled to the channel of the bilayer graphene layer. The local first and second gates form a first pair of gates to locally control a first portion of the bilayer graphene layer.07-12-2012
20120261644STRUCTURE AND METHOD OF MAKING GRAPHENE NANORIBBONS - Disclosed is a ribbon of graphene less than 3 nm wide, more preferably less than 1 nm wide. In a more preferred embodiment, there are multiple ribbons of graphene each with a width of one of the following dimensions: the length of 2 phenyl rings fused together, the length of 3 phenyl rings fused together, the length of 4 phenyl rings fused together, and the length of 5 phenyl rings fused together. In another preferred embodiment the edges of the ribbons are parallel to each other. In another preferred embodiment, the ribbons have at least one arm chair edge and may have wider widths.10-18-2012
20120261646Integrated Circuits Based on Aligned Nanotubes - Techniques, apparatus and systems are described for wafer-scale processing of aligned nanotube devices and integrated circuits one. In one aspect, a method can include growing aligned nanotubes on at least one of a wafer-scale quartz substrate or a wafer-scale sapphire substrate. The method can include transferring the grown aligned nanotubes onto a target substrate. Also, the method can include fabricating at least one device based on the transferred nanotubes.10-18-2012
20120261645Graphene Device Having Physical Gap - Disclosed herein is a graphene device having a structure in which a physical gap is provided so that the off-state current of the graphene device can be significantly reduced without having to form a band gap in graphene, and thus the on/off current ratio of the graphene device can be significantly increased while the high electron mobility of graphene is maintained.10-18-2012
20120261647METHODS OF FORMING STRUCTURES HAVING NANOTUBES EXTENDING BETWEEN OPPOSING ELECTRODES AND STRUCTURES INCLUDING SAME - A semiconductor structure including nanotubes forming an electrical connection between electrodes is disclosed. The semiconductor structure may include an open volume defined by a lower surface of an electrically insulative material and sidewalls of at least a portion of each of a dielectric material and opposing electrodes. The nanotubes may extend between the opposing electrodes, forming a physical and electrical connection therebetween. The nanotubes may be encapsulated within the open volume in the semiconductor structure. A semiconductor structure including nanotubes forming an electrical connection between source and drain regions is also disclosed. The semiconductor structure may include at least one semiconducting carbon nanotube electrically connected to a source and a drain, a dielectric material disposed over the at least one semiconducting carbon nanotube and a gate dielectric overlying a portion of the dielectric material. Methods of forming the semiconductor structures are also disclosed.10-18-2012
20120298965MULTIGATE STRUCTURE FORMED WITH ELECTROLESS METAL DEPOSITION - A multigate structure which comprises a semiconductor substrate; an ultra-thin silicon or carbon bodies of less than 20 nanometers thick located on the substrate; an electrolessly deposited metallic layer selectively located on the side surfaces and top surfaces of the ultra-thin silicon or carbon bodies and selectively located on top of the multigate structures to make electrical contact with the ultra-thin silicon or carbon bodies and to minimize parasitic resistance, and wherein the ultra-thin silicon or carbon bodies and metallic layer located thereon form source and drain regions is provided along with a process to fabricate the structure.11-29-2012
20120319083NANOROD SEMICONDUCTOR DEVICE HAVING A CONTACT STRUCTURE, AND METHOD FOR MANUFACTURING SAME - Disclosed is a nanorod semiconductor device having a contact structure, and a method for manufacturing the same. The nanorod semiconductor device having a contact structure according to one embodiment of the present disclosure includes: a transparent wafer; a transparent electrode layer formed on the transparent wafer; a nanorod layer including a plurality of semiconductor nanorods doped with dopants having a first polarity and grown on the transparent electrode layer; and a single crystal semiconductor layer doped with dopants having a second polarity and forming a certain physical contact with the ends of the semiconductor nanorods.12-20-2012
20120319084PLANAR AND NANOWIRE FIELD EFFECT TRANSISTORS - An integrated circuit includes a plurality of gate-all-around (GAA) nanowire field effect transistors (FETs), a plurality of omega-gate nanowire FETs, and a plurality of planar channel FETs, wherein the plurality of GAA FETs, the plurality of omega-gate nanowire FETs, and the plurality of planar channel FETs are disposed on a single wafer.12-20-2012
20110227045Voltage-Controlled Switches - A voltage-controlled switch (09-22-2011
20120080662GRAPHENE INTERCONNECTION AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a graphene interconnection includes a first insulating film, a first catalyst film, and a first graphene layer. A first insulating film includes an interconnection trench. A first catalyst film is formed on the first insulating film on both side surfaces of the interconnection trench. A first graphene layer is formed on the first catalyst film on the both side surfaces of the interconnection trench, and including graphene sheets stacked in a direction perpendicularly to the both side surfaces.04-05-2012
20120080661GRAPHENE INTERCONNECTION AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a graphene interconnection includes an insulating film, a catalyst film, and a graphene layer. An insulating film includes an interconnection trench. A catalyst film is formed in the interconnection trench and filling at least a portion of the interconnection trench. A graphene layer is formed on the catalyst film in the interconnection trench, and including graphene sheets stacked in a direction perpendicularly to a bottom surface of the interconnection trench.04-05-2012
20120280213Method of Fabricating Thin Film Transistor and Top-gate Type Thin Film Transistor - A method of fabricating a thin film transistor (TFT) and a top-gate type thin film transistor are disclosed, the method of fabricating a TFT of the present invention comprises steps: (A) providing a substrate; (B) forming a source electrode, a drain electrode, and SWCNT (singled-walled carbon nanotubes) layer on the substrate, in which the source electrode and the drain electrode are spaced in a distance and the SWCNT layer is located between the source electrode and the drain electrode; (C) forming a gate oxide layer on the SWCNT layer; (D) annealing the gate oxide layer with oxygen or nitrogen gas; and (E) forming a gate electrode on the gate oxide layer; wherein the temperature used in the step (D) for annealing is a 500° C. to 600° C.11-08-2012
20120326129METAL-FREE INTEGRATED CIRCUITS COMPRISING GRAPHENE AND CARBON NANOTUBES - An integrated circuit includes a graphene layer, the graphene layer comprising a region of undoped graphene, the undoped graphene comprising a channel of a transistor, and a region of doped graphene, the doped graphene comprising a contact of the transistor; and a gate of the transistor, the gate comprising a carbon nanotube film. A method of fabricating an integrated circuit comprising graphene and carbon nanotubes, includes forming a graphene layer; doping a portion of the graphene layer, resulting in doped graphene and undoped graphene; forming a carbon nanotube film; and etching the carbon nanotube film to form a gate of a transistor, wherein the transistor further comprises a channel comprising the undoped graphene and a contact comprising the doped graphene. A transistor includes a gate, the gate comprising a carbon nanotube film; a channel, the channel comprising undoped graphene; and a contact, the contact comprising doped graphene.12-27-2012
20120326126Graphene or Carbon Nanotube Devices with Localized Bottom Gates and Gate Dielectric - Transistor devices having nanoscale material-based channels (e.g., carbon nanotube or graphene channels) and techniques for the fabrication thereof are provided. In one aspect, a transistor device is provided. The transistor device includes a substrate; an insulator on the substrate; a local bottom gate embedded in the insulator, wherein a top surface of the gate is substantially coplanar with a surface of the insulator; a local gate dielectric on the bottom gate; a carbon-based nanostructure material over at least a portion of the local gate dielectric, wherein a portion of the carbon-based nanostructure material serves as a channel of the device; and conductive source and drain contacts to one or more portions of the carbon-based nanostructure material on opposing sides of the channel that serve as source and drain regions of the device.12-27-2012
20120326127COLLAPSABLE GATE FOR DEPOSITED NANOSTRUCTURES - A disposable material layer is first deposited on a graphene layer or a carbon nanotube (CNT). The disposable material layer includes a material that is less inert than graphene or CNT so that a contiguous dielectric material layer can be deposited at a target dielectric thickness without pinholes therein. A gate stack is formed by patterning the contiguous dielectric material layer and a gate conductor layer deposited thereupon. The disposable material layer shields and protects the graphene layer or the CNT during formation of the gate stack. The disposable material layer is then removed by a selective etch, releasing a free-standing gate structure. The free-standing gate structure is collapsed onto the graphene layer or the CNT below at the end of the selective etch so that the bottom surface of the contiguous dielectric material layer contacts an upper surface of the graphene layer or the CNT.12-27-2012
20120326128GRAPHENE-LAYERED STRUCTURE, METHOD OF PREPARING THE SAME, AND TRANSPARENT ELECTRODE AND TRANSISTOR INCLUDING GRAPHENE-LAYERED STRUCTURE - A method of directly growing graphene of a graphene-layered structure, the method including ion-implanting at least one ion of a nitrogen ion and an oxygen ion on a surface of a silicon carbide (SiC) thin film to form an ion implantation layer in the SiC thin film; and heat treating the SiC thin film with the ion implantation layer formed therein to graphenize a SiC surface layer existing on the ion implantation layer.12-27-2012
20120286242NANOWIRE PIN TUNNEL FIELD EFFECT DEVICES - A nanowire tunnel device includes a nanowire suspended above a semiconductor substrate by a first pad region and a second pad region, the nanowire having a channel portion surrounded by a gate structure disposed circumferentially around the nanowire, an n-type doped region including a first portion of the nanowire adjacent to the channel portion, and a p-type doped region including a second portion of the nanowire adjacent to the channel portion.11-15-2012
20120286243FIELD-EFFECT TRANSISTOR, SINGLE-ELECTRON TRANSISTOR AND SENSOR - A field-effect transistor or a single electron transistor is used as sensors for detecting a detection target such as a biological compound. A substrate has a first side and a second side, the second side being opposed to the first side. A source electrode is disposed on the first side of the substrate and a drain electrode disposed on the first side of the substrate, and a channel forms a current path between the source electrode and the drain electrode. An interaction-sensing gate is disposed on the second side of the substrate, the interaction-sensing gate having a specific substance that is capable of selectively interacting with the detection target. A gate for applying a gate voltage adjusts a characteristic of the transistor as the detection target changes the characteristic of the transistor when interacting with the specific substance.11-15-2012
20120138903Graphene Substrates And Methods Of Fabricating The Same - The graphene substrate may include a metal oxide film on a substrate, and a graphene layer on the metal oxide film. The concentration of oxygen in the metal oxide film may be gradually reduced from the substrate towards the graphene layer, and the graphene layer may be formed directly on the metal oxide film.06-07-2012
20120138902Edge-Contacted Vertical Carbon Nanotube Transistor - A vertical device geometry for a carbon-nanotube-based field effect transistor has one or multiple carbon nanotubes formed in a trench.06-07-2012
20120138901Color Selective Photodetector and Methods of Making - A photoelectric device, such as a photodetector, can include a semiconductor nanowire electrostatically associated with a J-aggregate. The J-aggregate can facilitate absorption of a desired wavelength of light, and the semiconductor nanowire can facilitate charge transport. The color of light detected by the device can be chosen by selecting a J-aggregate with a corresponding peak absorption wavelength.06-07-2012
20130015429ALL GRAPHENE FLASH MEMORY DEVICEAANM Hong; Augustin J.AACI Los AngelesAAST CAAACO USAAGP Hong; Augustin J. Los Angeles CA USAANM Kim; Ji-YoungAACI Los AngelesAAST CAAACO USAAGP Kim; Ji-Young Los Angeles CA USAANM Wang; Kang-LungAACI Santa MonicaAAST CAAACO USAAGP Wang; Kang-Lung Santa Monica CA US - A Graphene Flash Memory (GFM) device is disclosed. In general, the GFM device includes a number of memory cells, where each memory cell includes a graphene channel, a graphene storage layer, and a graphene electrode. In one embodiment, by using a graphene channel, graphene storage layer, and graphene electrode, the memory cells of the GFM device are enabled to be scaled down much more than memory cells of a conventional flash memory device. More specifically, in one embodiment, the GFM device has a feature size less than 25 nanometers, less than or equal to 20 nanometers, less than or equal to 15 nanometers, less than or equal to 10 nanometers, or less than or equal to 5 nanometers.01-17-2013
20130168640INVERTER DEVICE, NAND DEVICE, NOR DEVICE, AND LOGIC DEVICE INCLUDING THE SAME - An inverter device including a tunable diode device and a diode device that includes a control terminal connected to an input terminal of the inverter device, an anode terminal connected to a high-level voltage terminal, and a cathode terminal connected to an output terminal of the inverter device, wherein the diode device is configured to turn on or off according to a voltage applied to the control terminal.07-04-2013
20130175502Nanowire Field Effect Transistors - A method for forming a nanowire field effect transistor (FET) device includes forming a nanowire over a substrate, forming a liner material around a portion of the nanowire, forming a capping layer on the liner material, forming a first spacer adjacent to sidewalls of the capping layer and around portions of the nanowire, forming a hardmask layer on the capping layer and the first spacer, removing an exposed portion of the nanowire to form a first cavity partially defined by the gate material, epitaxially growing a semiconductor material on an exposed cross section of the nanowire in the first cavity, removing the hardmask layer and the capping layer, forming a second capping layer around the semiconductor material epitaxially grown in the first cavity to define a channel region, and forming a source region and a drain region contacting the channel region.07-11-2013
20130140526HEXAGONAL BORON NITRIDE SHEET, METHOD OF PREPARING THE HEXAGONAL BORON NITRIDE SHEET, AND ELECTRONIC DEVICE INCLUDING THE HEXAGONAL BORON NITRIDE SHEET - A hexagonal boron nitride sheet having: a two-dimensional planar structure with a sp06-06-2013
20130175504OXIDE-NITRIDE-OXIDE STACK HAVING MULTIPLE OXYNITRIDE LAYERS - An embodiment of a semiconductor memory device including a multi-layer charge storing layer and methods of forming the same are described. Generally, the device includes a channel formed from a semiconducting material overlying a surface on a substrate connecting a source and a drain of the memory device; a tunnel oxide layer overlying the channel; and a multi-layer charge storing layer including an oxygen-rich, first oxynitride layer on the tunnel oxide layer in which a stoichiometric composition of the first oxynitride layer results in it being substantially trap free, and an oxygen-lean, second oxynitride layer on the first oxynitride layer in which a stoichiometric composition of the second oxynitride layer results in it being trap dense. In one embodiment, the device comprises a non-planar transistor including a gate having multiple surfaces abutting the channel, and the gate comprises the tunnel oxide layer and the multi-layer charge storing layer.07-11-2013
20130175505THIN FILM TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - A thin film transistor (“TFT”) includes a gate electrode, a gate insulating layer, a source electrode, a drain electrode and a semiconductor layer. The gate insulating layer is disposed on the gate electrode. The source electrode is disposed on the gate insulating layer. The drain electrode is disposed on the gate insulating layer. The drain electrode is spaced apart from the source electrode. The semiconductor layer is disposed on the gate insulating layer. The semiconductor layer makes contact with a side surface of the source electrode and a side surface of the drain electrode.07-11-2013
20130175506THREE-DIMENSIONAL GRAPHENE SWITCHING DEVICE - A switching device includes a semiconductor layer, a graphene layer, a gate insulation layer, and a gate formed in a three-dimensional stacking structure between a first electrode and a second electrode formed on a substrate.07-11-2013
20120248416High Performance Field-Effect Transistors - A high performance field-effect transistor includes a substrate, a nanomaterial thin film disposed on the substrate, a source electrode and a drain electrode formed on the nanomaterial thin film, and a channel area defined between the source electrode and the drain electrode. A unitary self-aligned gate electrode extends from the nanomaterial thin film in the channel area between the source electrode and the drain electrode, the gate electrode having an outer dielectric layer and including a foot region and a head region, the foot region in contact with a portion of the nanomaterial thin film in the channel area. A metal layer is disposed over the source electrode, the drain electrode, the head region of the gate electrode, and portions of the nanomaterial thin film proximate the source electrode and the drain electrode in the channel area.10-04-2012
20120248415RESONANCE TUNNELING DEVICES AND METHODS OF MANUFACTURING THE SAME - Provided are a resonance tunneling device and a method of manufacturing the resonance tunneling device. The resonance tunneling device includes a substrate, a plurality of electrodes disposed on the substrate, and a nanoparticle layer disposed between the electrodes, and doped with an impurity. The nanoparticle layer uses the impurity to exhibit resonance tunneling where a current peak occurs at a target bias voltage applied between the electrodes.10-04-2012
20130134394Integrated Circuits Based on Aligned Nanotubes - Techniques, apparatus and systems are described for wafer-scale processing of aligned nanotube devices and integrated circuits. In one aspect, a method can include growing aligned nanotubes on at least one of a wafer-scale quartz substrate or a wafer-scale sapphire substrate. The method can include transferring the grown aligned nanotubes onto a target substrate. Also, the method can include fabricating at least one device based on the transferred nanotubes.05-30-2013
20130134393Nanotube Field Effect Devices and Methods of Making Same - Methods of making non-volatile field effect devices and arrays of same. Under one embodiment, a method of making a non-volatile field effect device includes providing a substrate with a field effect device formed therein. The field effect device includes a source, drain and gate with a field-modulatable channel between the source and drain. An electromechanically-deflectable, nanotube switching element is formed over the field effect device. Terminals and corresponding interconnect are provided to correspond to each of the source, drain and gate such that the nanotube switching element is electrically positioned between one of the source, drain and gate and its corresponding terminal, and such that the others of said source, drain and gate are directly connected to their corresponding terminals.05-30-2013
20130134392Doping Carbon Nanotubes and Graphene for Improving Electronic Mobility - A method and an apparatus for doping a graphene or nanotube thin-film field-effect transistor device to improve electronic mobility. The method includes selectively applying a dopant to a channel region of a graphene or nanotube thin-film field-effect transistor device to improve electronic mobility of the field-effect transistor device.05-30-2013
20130092902NANOWIRE TUNNELING FIELD EFFECT TRANSISTOR WITH VERTICAL STRUCTURE AND A MANUFACTURING METHOD THEREOF - The present invention belongs to the technical field of semiconductor devices and specifically relates to a method for manufacturing a nanowire tunneling field effect transistor (TFET). In the method, the ZnO nanowire required is developed in a water bath without the need for high temperatures and high pressure, featuring a simple solution preparation, convenient development and low cost, as well as constituting MOS devices of vertical structure with nanowire directly, thus omitting the nanowire treatment in the subsequent stage. The present invention has the advantages of simple structure, convenient manufacturing, and low cost, and control of the nanowire channel developed and the MOSFET array with vertical structure made of it though the gate, so as to facilitate the manufacturing of large-scale MOSFET array directly.04-18-2013
20130134391Reducing Contact Resistance for Field-Effect Transistor Devices - A method and an apparatus for doping a graphene and nanotube thin-film transistor field-effect transistor device to decrease contact resistance with a metal electrode. The method includes selectively applying a dopant to a metal contact region of a graphene and nanotube field-effect transistor device to decrease the contact resistance of the field-effect transistor device.05-30-2013
20110210314Graphene electronic device and method of fabricating the same - A graphene electronic device may include a silicon substrate, connecting lines on the silicon substrate, a first electrode and a second electrode on the silicon substrate, and an interlayer dielectric on the silicon substrate. The interlayer dielectric may be configured to cover the connecting lines and the first and second electrodes and the interlayer dielectric may be further configured to expose at least a portion of the first and second electrodes. The graphene electronic device may further include an insulating layer on the interlayer dielectric and a graphene layer on the insulating layer, the graphene layer having a first end and a second end. The first end of the graphene layer may be connected to the first electrode and the second end of the graphene layer may be connected to the second electrode.09-01-2011
20110248243Carbon nanotube field effect transistor for printed flexible/rigid electronics - Methods and devices for manufacturing carbon nanotube based field effect transistors are disclosed including providing a substrate; printing a gate electrode layer onto the substrate and sintering and/or UV curing; printing a gate isolation layer onto the gate electrode and air drying and/or UV curing; printing one or more carbon nanotube channel layers onto the gate isolation layer, wherein each carbon nanotube channel layer is air dried prior to subsequent printings; and printing a source and drain electrode layer onto the one or more carbon nanotube channel layers and sintering and/or UV curing. Other embodiments are described and claimed.10-13-2011
20130146847GRAPHENE FIELD EFFECT TRANSISTOR - Manufacturing a semiconductor structure including: forming a seed material on an insulator layer; forming a graphene field effect transistor (FET) on the seed material; and forming an air gap under the graphene FET by removing the seed material.06-13-2013
20130175503Compressive (PFET) and Tensile (NFET) Channel Strain in Nanowire FETs Fabricated with a Replacement Gate Process - A method of fabricating a FET device is provided which includes the following steps. Nanowires/pads are formed in a SOI layer over a BOX layer, wherein the nanowires are suspended over the BOX. A HSQ layer is deposited that surrounds the nanowires. A portion(s) of the HSQ layer that surround the nanowires are cross-linked, wherein the cross-linking causes the portion(s) of the HSQ layer to shrink thereby inducing strain in the nanowires. One or more gates are formed that retain the strain induced in the nanowires. A FET device is also provided wherein each of the nanowires has a first region(s) that is deformed such that a lattice constant in the first region(s) is less than a relaxed lattice constant of the nanowires and a second region(s) that is deformed such that a lattice constant in the second region(s) is greater than the relaxed lattice constant of the nanowires.07-11-2013
20120273762ELECTRONIC ARRANGEMENTS FOR PASSIVATED SILICON NANOWIRES - Methods for fabricating passivated silicon nanowires and an electronic arrangement thus obtained are described. Such arrangements may comprise a metal-oxide-semiconductor (MOS) structure such that the arrangements may be utilized for MOS field-effect transistors (MOSFETs) or opto-electronic switches.11-01-2012
20130181189Logic Elements Comprising Carbon Nanotube Field Effect Transistor (CNTFET) Devices and Methods of Making Same - Inverter circuits and NAND circuits comprising nanotube based FETs and methods of making the same are described. Such circuits can be fabricating using field effect transistors comprising a source, a drain, a channel region, and a gate, wherein the first channel region includes a fabric of semiconducting nanotubes of a given conductivity type. Such FETs can be arranged to provide inverter circuits in either two-dimension or three-dimensional (stacked) layouts. Design equations based upon consideration of the electrical characteristics of the nanotubes are described which permit optimization of circuit design layout based upon constants that are indicative of the current carrying capacity of the nanotube fabrics of different FETs.07-18-2013
20130119348Radio Frequency Devices Based on Carbon Nanomaterials - RF transistors are fabricated at complete wafer scale using a nanotube deposition technique capable of forming high-density, uniform semiconducting nanotube thin films at complete wafer scale, and electrical characterization reveals that such devices exhibit gigahertz operation, linearity, and large transconductance and current drive.05-16-2013
20110303899GRAPHENE DEPOSITION - Embodiments of the invention are directed toward the deposition of Graphene on a semiconductor substrate. In some embodiments, these processes can occur at low temperature levels during a back end of the line process. For example, Graphene can be deposited in a CVD reactor at a processing temperature that is below 600° C. to protect previously deposited layers that may be susceptible to sustained higher temperatures. Graphene deposition can include the deposition of an underlayer (e.g., cobalt) followed by the flow of a carbon precursor (e.g., acetylene) at the processing temperature. Graphene can then be synthesized with during cooling, an RTP cure, and/or a UV cure.12-15-2011
20110309336SEMICONDUCTING GRAPHENE COMPOSITION, AND ELECTRICAL DEVICE INCLUDING THE SAME - A graphene composition including a graphene monolayer and an alkali metal disposed on the graphene monolayer.12-22-2011
20110315961Ultrathin Spacer Formation for Carbon-Based FET - A method for formation of a carbon-based field effect transistor (FET) includes depositing a first dielectric layer on a carbon layer located on a substrate; forming a gate electrode on the first dielectric layer; etching an exposed portion of the first dielectric layer to expose a portion of the carbon layer; depositing a second dielectric layer over the gate electrode to form a spacer, wherein the second dielectric layer is deposited by atomic layer deposition (ALD), and wherein the second dielectric layer does not form on the exposed portion of the carbon layer; forming source and drain contacts on the carbon layer and forming a gate contact on the gate electrode to form the carbon-based FET.12-29-2011
20130193412TRANSISTORS AND METHODS OF MANUFACTURING THE SAME - Transistors and methods of manufacturing the same may include a gate on a substrate, a channel layer having a three-dimensional (3D) channel region covering at least a portion of a gate, a source electrode over a first region of the channel layer, and a drain electrode over a second region of the channel layer.08-01-2013
20130193410NANO-DEVICES FORMED WITH SUSPENDED GRAPHENE MEMBRANE - Semiconductor nano-devices, such as nano-probe and nano-knife devices, which are constructed using graphene films that are suspended between open cavities of a semiconductor structure. The suspended graphene films serve as electro-mechanical membranes that can be made very thin, from one or few atoms in thickness, to greatly improve the sensitivity and reliability of semiconductor nano-probe and nano-knife devices.08-01-2013
20130193411GRAPHENE DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a graphene device may include forming a device portion including a graphene layer on the first substrate; attaching a second substrate on the device portion of the first substrate; and removing the first substrate. The removing of the first substrate may include etching a sacrificial layer between the first substrate and the graphene layer. After removing the first substrate, a third substrate may be attached on the device portion. After attaching the third substrate, the second substrate may be removed.08-01-2013
20120074387MICROELECTRONIC TRANSISTOR HAVING AN EPITAXIAL GRAPHENE CHANNEL LAYER - The present disclosure relates to the field of microelectronic transistor fabrication and, more particularly, to forming a graphene layer as a channel layer for a microelectronic transistor.03-29-2012

Patent applications in class Ballistic transport device (e.g., hot electron transistor)