Class / Patent application number | Description | Number of patent applications / Date published |
257018000 | Strained layer superlattice | 55 |
20080203382 | SEMICONDUCTOR WAFER, DEVICES MADE THEREFROM, AND METHOD OF FABRICATION - A main semiconductor region of semiconducting nitrides is formed on a silicon substrate via a buffer region of semiconducting nitrides to provide devices such as HEMTs, MESFETs and LEDs. In order to render the wafer proof against warping, the buffer region is divided into a first and a second multilayered buffer subregion. The first buffer subregion comprises multiple alterations of a multi-sublayered first buffer layer and a non-sublayered second buffer layer. Each multi-sublayered first buffer layer of the first buffer subregion comprises multiple alternations of a first and a second buffer sublayer. The second buffer sublayers of each multi-sublayered first buffer layer either do not contain aluminum or do contain it in a higher proportion than do the first buffer sublayers. The second multilayered buffer subregion comprises multiple alternations of a first and a second buffer layer. The first buffer layers of the second multilayered buffer subregion are less in aluminum proportion than the fourth buffer layers of the second multilayered buffer subregion. | 08-28-2008 |
20080265241 | SEMICONDUCTOR DEVICE AND A METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor device is disclosed. In one embodiment, the semiconductor device includes a channel formation region formed on a side wall, having a mixture of a first semiconductor material with a first lattice constant, a second semiconductor material and carbon, the second semiconductor material having a second lattice constant differing from the first lattice constant. | 10-30-2008 |
20080283823 | Gallium Nitride-Based Semiconductor Stacked Structure - A gallium-nitride-based semiconductor stacked structure includes a sapphire substrate; a low temperature-deposited buffer layer which is composed of a Group III nitride material of Al | 11-20-2008 |
20080308788 | QUANTUM DOT SEMICONDUCTOR DEVICE - A quantum dot semiconductor device includes an active layer having a plurality of quantum dot layers each including a composite quantum dot formed by stacking a plurality of quantum dots and a side barrier layer formed in contact with a side face of the composite quantum dot. The stack number of the quantum dots and the magnitude of strain of the side barrier layer from which each of the quantum dot layers is formed are set so that a gain spectrum of the active layer has a flat gain bandwidth corresponding to a shift amount of the gain spectrum within a desired operation temperature range. | 12-18-2008 |
20090045395 | Strained-Layer Superlattice Focal Plane Array Having a Planar Structure - An infrared focal plane array (FPA) is disclosed which utilizes a strained-layer superlattice (SLS) formed of alternating layers of InAs and In | 02-19-2009 |
20090114902 | TENSILE STRAINED GE FOR ELECTRONIC AND OPTOELECTRONIC APPLICATIONS - A semiconductor structure is provided. The semiconductor structure includes one or more III-IV material-based semiconductor layers. A tensile-strained Ge layer is formed on the one or more a III-IV material-based semiconductor layers. The tensile-strained Ge layer is produced through lattice-mismatched heteroepitaxy on the one or more a III-IV material-based semiconductor layers. | 05-07-2009 |
20110017978 | STRAIN-INDUCING SEMICONDUCTOR REGIONS - A method to form a strain-inducing semiconductor region is described. In one embodiment, formation of a strain-inducing semiconductor region laterally adjacent to a crystalline substrate results in a uniaxial strain imparted to the crystalline substrate, providing a strained crystalline substrate. In another embodiment, a semiconductor region with a crystalline lattice of one or more species of charge-neutral lattice-forming atoms imparts a strain to a crystalline substrate, wherein the lattice constant of the semiconductor region is different from that of the crystalline substrate, and wherein all species of charge-neutral lattice-forming atoms of the semiconductor region are contained in the crystalline substrate. | 01-27-2011 |
20110101305 | MOS Devices with Partial Stressor Channel - A semiconductor structure includes a semiconductor substrate having a first lattice constant; a gate dielectric on the semiconductor substrate; a gate electrode on the semiconductor substrate; and a stressor having at least a portion in the semiconductor substrate and adjacent the gate electrode. The stressor has a tilted sidewall on a side adjacent the gate electrode. The stressor includes a first stressor layer having a second lattice constant substantially different from the first lattice constant; and a second stressor layer on the first stressor layer, wherein the second stressor has a third lattice constant substantially different from the first and the second lattice constants. | 05-05-2011 |
20110147706 | TECHNIQUES AND CONFIGURATIONS TO IMPART STRAIN TO INTEGRATED CIRCUIT DEVICES - Embodiments of the present disclosure describe techniques and configurations to impart strain to integrated circuit devices such as horizontal field effect transistors. An integrated circuit device includes a semiconductor substrate, a first barrier layer coupled with the semiconductor substrate, a quantum well channel coupled to the first barrier layer, the quantum well channel comprising a first material having a first lattice constant, and a source structure coupled to the quantum well channel, the source structure comprising a second material having a second lattice constant, wherein the second lattice constant is different than the first lattice constant to impart a strain on the quantum well channel. Other embodiments may be described and/or claimed. | 06-23-2011 |
20110168979 | Superlattice Structure - A superlattice layer including a plurality of periods, each of which is formed from a plurality of sub-layers is provided. Each sub-layer comprises a different composition than the adjacent sub-layer(s) and comprises a polarization that is opposite a polarization of the adjacent sub-layer(s). In this manner, the polarizations of the respective adjacent sub-layers compensate for one another. | 07-14-2011 |
20120025168 | STRAIN CONTROL IN SEMICONDUCTOR DEVICES - A semiconductor device comprises the following elements: an active layer comprising a quantum well structure and a buffer layer beneath the active layer adapted to form a confinement layer for charge carriers in the active layer. The buffer layer is adapted so as not to increase an overall strain in the active layer. The active layer is already strained as a result of a lattice mismatch between the active layer and the buffer layer. Strain in the buffer layer may be controlled by use of a strain control buffer layer and by appropriate choices of material and composition for the buffer layer and for a substrate on which the buffer layer is grown. | 02-02-2012 |
20120104360 | STRAIN COMPENSATED SHORT-PERIOD SUPERLATTICES ON SEMIPOLAR OR NONPOLAR GAN FOR DEFECT REDUCTION AND STRESS ENGINEERING - An (AlInGaN) based semiconductor device, comprising a first layer that is a semipolar or nonpolar nitride (AlInGaN) layer having a lattice constant that is partially or fully relaxed, deposited on a substrate or a template, wherein there are one or more dislocations at a heterointerface between the first layer and the substrate or the template; one or more strain compensated layers on the first layer, for defect reduction and stress engineering in the device, that is lattice matched to a larger lattice constant of the first layer; and one or more nonpolar or semipolar (AlInGaN) device layers on the strain compensated layers. | 05-03-2012 |
20120153261 | Semiconductor Device And Method Of Manufacturing The Same - Example embodiments relate to a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device may include a pre-seeding layer and a nucleation layer. The pre-seeding layer may include a first material for pre-seeding and a second material for masking so as to reduce tensile stress. | 06-21-2012 |
20130032781 | EPITAXIAL SUBSTRATE AND METHOD FOR MANUFACTURING EPITAXIAL SUBSTRATE - Provided is a crack-free epitaxial substrate with reduced warping, in which a silicon substrate is used as a base substrate. The epitaxial substrate includes a (111) single crystal Si substrate, a superlattice layer group in which a plurality of superlattice layers are laminated, and a crystal layer. The superlattice layer is formed of a first unit layer and a second unit layer made of group-III nitrides having different compositions being alternately and repeatedly laminated. The crystal layer is made of a group-III nitride and formed above the base substrate so as to be positioned at an upper side of the superlattice layer group relative to the base substrate. The superlattice layer group has a compressive strain contained therein. In the superlattice layer group, the more distant the superlattice layer is from the base substrate, the greater the compressive strain becomes. | 02-07-2013 |
20130043458 | Long Wavelength Infrared Superlattice - An embodiment of the present invention improves the fabrication and operational characteristics of a type-II superlattice material. Layers of indium arsenide and gallium antimonide comprise the bulk of the superlattice structure. One or more layers of indium antimonide are added to unit cells of the superlattice to provide a further degree of freedom in the design for adjusting the effective bandgap energy of the superlattice. One or more layers of gallium arsenide antimonide are added to unit cells of the superlattice to counterbalance the crystal lattice strain forces introduced by the aforementioned indium antimonide layers. | 02-21-2013 |
20130221327 | THICK NITRIDE SEMICONDUCTOR STRUCTURES WITH INTERLAYER STRUCTURES AND METHODS OF FABRICATING THICK NITRIDE SEMICONDUCTOR STRUCTURES - A semiconductor structure includes a substrate, a nucleation layer on the substrate, a compositionally graded layer on the nucleation layer, and a layer of a nitride semiconductor material on the compositionally graded layer. The layer of nitride semiconductor material includes a plurality of substantially relaxed nitride interlayers spaced apart within the layer of nitride semiconductor material. The substantially relaxed nitride interlayers include aluminum and gallium and are conductively doped with an n-type dopant, and the layer of nitride semiconductor material including the plurality of nitride interlayers has a total thickness of at least about 2.0 μm. | 08-29-2013 |
20130234113 | QUANTUM WELL MOSFET CHANNELS HAVING LATTICE MISMATCH WITH METAL SOURCE/DRAINS, AND CONFORMAL REGROWTH SOURCE/DRAINS - Embodiments described include straining transistor quantum well (QW) channel regions with metal source/drains, and conformal regrowth source/drains to impart a uni-axial strain in a MOS channel region. Removed portions of a channel layer may be filled with a junction material having a lattice spacing different than that of the channel material to causes a uni-axial strain in the channel, in addition to a bi-axial strain caused in the channel layer by a top barrier layer and a bottom buffer layer of the quantum well. | 09-12-2013 |
20130334496 | SEMICONDUCTOR DEVICE, SUPERLATTICE LAYER USED IN THE SAME, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a silicon substrate; a nitride nucleation layer disposed on the silicon substrate; at least one superlattice layer disposed on the nitride nucleation layer; and at least one gallium nitride-based semiconductor layer disposed on the superlattice layer. The at least one superlattice layer includes a stack of complex layers, each complex layer including a first layer and a second layer such that each of the complex layers has a plurality of nitride semiconductor layers having different compositions, at least one of the plurality of nitride semiconductor layers having a different thickness based on a location of the at least one nitride semiconductor layer within the stack, and at least one stress control layer having a thickness greater than a critical thickness for pseudomorphic growth. | 12-19-2013 |
20140001438 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME | 01-02-2014 |
20140103294 | TECHNIQUES AND CONFIGURATIONS TO IMPART STRAIN TO INTEGRATED CIRCUIT DEVICES - Embodiments of the present disclosure describe techniques and configurations to impart strain to integrated circuit devices such as horizontal field effect transistors. An integrated circuit device includes a semiconductor substrate, a quantum well channel coupled with the semiconductor substrate, a source structure coupled with the quantum well channel, a drain structure coupled with the quantum well channel and a strain-inducing film disposed on and in direct contact with material of the source structure and the drain structure to reduce resistance of the quantum well channel by imparting a tensile or compressive strain on the quantum well channel, wherein the quantum well channel is disposed between the strain-inducing film and the semiconductor substrate. Other embodiments may be described and/or claimed. | 04-17-2014 |
20140319462 | BUFFER LAYER OMEGA GATE - A device comprises insulation regions disposed in a substrate and a semiconductor fin extending above top surfaces of the insulation regions. The semiconductor fin comprises a first material. A semiconductor region comprising a second material extends from a first side of the semiconductor fin over a top of the fin to a second side of the fin. A strain buffer layer is disposed between, and contacts, the semiconductor fin and the semiconductor region. The strain buffer layer comprises an oxide, and a bottommost surface of the strain buffer layer is vertically spaced apart from the top surfaces of the insulation regions. | 10-30-2014 |
20140326950 | Stress Relieving Semiconductor Layer - A semiconductor structure, such as a group III nitride-based semiconductor structure is provided. The semiconductor structure includes a cavity containing semiconductor layer. The cavity containing semiconductor layer can have a thickness greater than two monolayers and a multiple cavities. The cavities can have a characteristic size of at least one nanometer and a characteristic separation of at least five nanometers. | 11-06-2014 |
20140339505 | VIRTUAL SUBSTRATES BY HAVING THICK, HIGHLY RELAXED METAMORPHIC BUFFER LAYER STRUCTURES BY HYDRIDE VAPOR PHASE EPITAXY - Virtual substrates made by hydride vapor phase epitaxy are provided comprising a semiconductor growth substrate and a substantially strain-relaxed metamorphic buffer layer (MBL) structure comprising one or more layers of a semiconductor alloy on the growth substrate. The MBL structure is compositionally graded such that its lattice constant transitions from a lattice constant at the interface with the growth substrate that is substantially the same as the lattice constant of the growth substrate to a lattice constant at a surface opposite the interface that is different from the lattice constant of the growth substrate. The virtual substrates comprise relatively thick MBL structures (e.g., >20 μm) and relatively thick growth substrates (e.g., >0.5 mm) | 11-20-2014 |
20140374701 | Superlattice Structures and Infrared Detector Devices Incorporating the Same - Embodiments of strain-balanced superlattice infrared detector devices and their fabrication are disclosed. In one embodiment, an infrared detector device includes a first contact layer, and absorber superlattice region, a wider gap unipolar barrier region, and a second contact layer. The absorber superlattice region has a period defined by a first InAs layer, strain-balancing structure, a second InAs layer, and an InAsSb layer. The strain-balancing structure comprises an arbitrary alloy layer sequence containing at least one constituent element of aluminum or phosphor, e.g., InGaAs, AlInAs InAsP. In another embodiment, the absorber superlattice region has a period defined by a first InAs layer, first strain-balancing structure, a second InAs layer, a first GaSb layer, a second strain-balancing structure, and a second GaSb layer. The first strain-balancing structure includes at least one constituent element of aluminum or phosphor, e.g., InGaAs, AlInAs InAsP. The second strain-balancing structure includes GaInSb and GaSb. | 12-25-2014 |
20150108428 | Heterostructure Including a Composite Semiconductor Layer - A heterostructure for use in an electronic or optoelectronic device is provided. The heterostructure includes one or more composite semiconductor layers. The composite semiconductor layer can include sub-layers of varying morphology, at least one of which can be formed by a group of columnar structures (e.g., nanowires). Another sub-layer in the composite semiconductor layer can be porous, continuous, or partially continuous. | 04-23-2015 |
20150144876 | SEMICONDUCTOR ELEMENT AND METHOD FOR PRODUCING THE SAME - A method for producing a semiconductor element includes a step of forming a multiple quantum well in which a GaSb layer and an InAs layer are alternately stacked on a GaSb substrate by MOVPE, wherein, in the step of forming a multiple quantum well, an InSb film is formed on at least one of a lower-surface side and an upper-surface side of the InAs layer so as to be in contact with the InAs layer. | 05-28-2015 |
20160079408 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a silicon substrate, a multi-layered film formed on the silicon substrate, the multi-layered film including a first aluminum nitride containing layer, a second aluminum nitride containing layer, and a film stack having a super lattice structure in which, between the first aluminum nitride containing layer and the second aluminum nitride containing layer, at least two layers selected from a group of layers including an aluminum nitride containing layer, a gallium nitride containing layer and an aluminum gallium nitride containing layer are alternately disposed between the first aluminum nitride containing layer and the second aluminum nitride containing layer, and a first gallium nitride containing layer formed on the multi-layered film. | 03-17-2016 |
20160126315 | III-Nitride Semiconductor Structure with Intermediate and Transition Layers - The invention provides semiconductor materials including a gallium nitride material layer formed on a silicon substrate and methods to form the semiconductor materials. The semiconductor materials include a transition layer formed between the silicon substrate and the gallium nitride material layer. The transition layer is compositionally-graded to lower stresses in the gallium nitride material layer which can result from differences in thermal expansion rates between the gallium nitride material and the substrate. The lowering of stresses in the gallium nitride material layer reduces the tendency of cracks to form. Thus, the invention enables the production of semiconductor materials including gallium nitride material layers having few or no cracks. The semiconductor materials may be used in a number of microelectronic and optical applications. | 05-05-2016 |
20160149000 | SEMICONDUCTOR WAFER AND METHOD OF PRODUCING SEMICONDUCTOR WAFER - A semiconductor wafer includes first and second superlattice layers. The first superlattice layer includes first unit layers each of which includes first and second layers, the second superlattice layer includes second unit layers each of which includes third and fourth layers, the first layer is made of Al | 05-26-2016 |
257019000 | Si x Ge 1-x | 26 |
20080237575 | Silicon germanium and germanium multigate and nanowire structures for logic and multilevel memory applications - A method to provide a transistor or memory cell structure. The method comprises: providing a substrate including a lower Si substrate and an insulating layer on the substrate; providing a first projection extending above the insulating layer, the first projection including an Si material and a Si1-xGex material; and exposing the first projection to preferential oxidation to yield a second projection including a center region comprising Ge/Si1-yGey and a covering region comprising SiO2 and enclosing the center region. | 10-02-2008 |
20080246019 | DEFECT REDUCTION BY OXIDATION OF SILICON - A method of fabricating high-quality, substantially relaxed SiGe-on-insulator substrate materials which may be used as a template for strained Si is described. A silicon-on-insulator substrate with a very thin top Si layer is used as a template for compressively strained SiGe growth. Upon relaxation of the SiGe layer at a sufficient temperature, the nature of the dislocation motion is such that the strain-relieving defects move downward into the thin Si layer when the buried oxide behaves semi-viscously. The thin Si layer is consumed by oxidation of the buried oxide/thin Si interface. This can be accomplished by using internal oxidation at high temperatures. In this way the role of the original thin Si layer is to act as a sacrificial defect sink during relaxation of the SiGe alloy that can later be consumed using internal oxidation. | 10-09-2008 |
20080277647 | Materials and Optical Devices Based on Group IV Quantum Wells Grown on Si-Ge-Sn Buffered Silicon - A semiconductor structure including a single quantum well Ge | 11-13-2008 |
20090020748 | SI/SIGE INTERBAND TUNNELING DIODES WITH TENSILE STRAIN - Some disclosed interband tunneling diodes comprise a plurality of substantially coherently strained layers including layers selected from a group consisting of silicon, germanium, and alloys of silicon and germanium, wherein at least one of said substantially coherently strained layers is tensile strained. Some disclosed resonant interband tunneling diodes comprise a plurality of substantially coherently strained layers including layers selected from a group consisting of silicon, germanium, and alloys of silicon and germanium, wherein at least one of said substantially coherently strained layers defines a barrier to non-resonant tunnel current. Some disclosed interband tunneling diodes comprise a plurality of substantially coherently strained layers, wherein at least one of said substantially coherently strained layers is tensile strained. Some disclosed resonant interband tunneling diodes comprise a plurality of substantially coherently strained layers, wherein at least one of said substantially coherently strained layers defines a barrier to non-resonant tunnel current. | 01-22-2009 |
20090134381 | Semiconductor device and fabrication method thereof - A semiconductor device includes a gate electrode formed on a silicon substrate via a gate insulation film in correspondence to a channel region, source and drain regions of a p-type diffusion region formed in the silicon substrate at respective outer sides of sidewall insulation films of the gate electrode, and a pair of SiGe mixed crystal regions formed in the silicon substrate at respective outer sides of. the sidewall insulation films in epitaxial relationship to the silicon substrate, the SiGe mixed crystal regions being defined by respective sidewall surfaces facing with each other, wherein, in each of the SiGe mixed crystal regions, the sidewall surface is defined by a plurality of facets forming respective, mutually different angles with respect to a principal surface of the silicon substrate. | 05-28-2009 |
20090173933 | Thermal Sensor with a Silicon/Germanium Superlattice Structure - A silicon/germanium (SiGe) superlattice thermal sensor is provided with a corresponding fabrication method. The method forms an active CMOS device in a first Si substrate, and a SiGe superlattice structure on a second Si-on-insulator (SOI) substrate. The first substrate is bonded to the second substrate, forming a bonded substrate. An electrical connection is formed between the SiGe superlattice structure and the CMOS device, and a cavity is formed between the SiGe superlattice structure and the bonded substrate. | 07-09-2009 |
20090236587 | SEMICONDUCTOR DEVICE INCLUDING A PLURALITY OF DIFFERENT FUNCTIONAL ELEMENTS AND METHOD OF MANUFACTURING THE SAME - At least first and second Si | 09-24-2009 |
20090267052 | LAYER TRANSFER OF LOW DEFECT SiGe USING AN ETCH-BACK PROCESS - A method for forming strained Si or SiGe on relaxed SiGe on insulator (SGOI) or a SiGe on Si heterostructure is described incorporating growing epitaxial Si | 10-29-2009 |
20100117059 | LIGHT MODULATION COMPRISING SI-GE QUANTUM WELL LAYERS - Optical modulators include active quantum well structures coherent with pseudosubstrates comprising relaxed buffer layers on a silicon substrate. In a preferred method the active structures, consisting of Si | 05-13-2010 |
20100163842 | Multiple-Gate Transistors with Reverse T-Shaped Fins - A method of forming an integrated circuit structure includes forming a first insulation region and a second insulation region in a semiconductor substrate and facing each other; and forming an epitaxial semiconductor region having a reversed T-shape. The epitaxial semiconductor region includes a horizontal plate including a bottom portion between and adjoining the first insulation region and the second insulation region, and a fin over and adjoining the horizontal plate. The bottom of the horizontal plate contacts the semiconductor substrate. The method further includes forming a gate dielectric on a top surface and at least top portions of sidewalls of the fin; and forming a gate electrode over the gate dielectric. | 07-01-2010 |
20110108801 | SINGLE-CRYSTAL SEMICONDUCTOR LAYER WITH HETEROATOMIC MACRO-NETWORK - A single-crystal layer of a first semiconductor material including single-crystal nanostructures of a second semiconductor material, the nanostructures being distributed in a regular crystallographic network with a centered tetragonal prism. | 05-12-2011 |
20110186816 | SEMICONDUCTOR DEVICE WAFER, SEMICONDUCTOR DEVICE, DESIGN SYSTEM, MANUFACTURING METHOD AND DESIGN METHOD - A device forming thin film for forming a semiconductor device; an inhibition portion that surrounds the device forming thin film and inhibits growth of a precursor of the device forming thin film into a crystal; a sacrificial growth portion that is formed by causing the precursor to sacrificially grow into a crystal, and is positioned around the device forming thin film separated by the inhibition portion; and a protection film that covers a top portion of the sacrificial growth portion and exposes a top portion of the device forming thin film are included. The protection film may be made of polyimide. | 08-04-2011 |
20110227042 | METHOD FOR PRODUCING SEMICONDUCTOR SUBSTRATE, SEMICONDUCTOR SUBSTRATE, METHOD FOR MANUFACTURING ELECTRONIC DEVICE, AND REACTION APPARATUS - There is provided a method of producing a semiconductor wafer by thermally processing a base water having a portion to be thermally processed that is to be thermally processed. The method comprises a step of providing, on the base wafer, a portion to be heated that generates heat through absorption of an electromagnetic wave and selectively heats the portion to be thermally processed, a step of applying an electromagnetic wave to the base wafer, and a step of lowering the lattice defect density of the portion to he thermally processed, by means of the heat generated by the portion to be heated through the absorption of the electromagnetic wave. | 09-22-2011 |
20120138897 | SOURCE/DRAIN STRESSOR HAVING ENHANCED CARRIER MOBILITY AND METHOD FOR MANUFACTURING SAME - Various source/drain stressors that can enhance carrier mobility, and methods for manufacturing the same, are disclosed. An exemplary source/drain stressor includes a seed layer of a first material disposed over a substrate of a second material, the first material being different than the second material; a relaxed epitaxial layer disposed over the seed layer; and an epitaxial layer disposed over the relaxed epitaxial layer. | 06-07-2012 |
20120161105 | UNIAXIALLY STRAINED QUANTUM WELL DEVICE AND METHOD OF MAKING SAME - A planar or non-planar quantum well device and a method of forming the quantum well device. The device includes: a buffer region comprising a large band gap material; a uniaxially strained quantum well channel region on the buffer region; an upper barrier region comprising a large band gap material on the quantum well channel region; a gate dielectric on the quantum well channel region; a gate electrode on the gate dielectric; and recessed source and drain regions at respective sides of the gate electrode, the source and drain regions including a junction material having a lattice constant different from a lattice constant of a material of the buffer region. Preferably, the buffer region comprises a Si | 06-28-2012 |
20120241722 | FIELD EFFECT TRANSISTOR - A field effect transistor according to an embodiment includes: a semiconductor layer; a source region and a drain region formed at a distance from each other in the semiconductor layer; a gate insulating film formed on a portion of the semiconductor layer, the portion being located between the source region and the drain region; a gate electrode formed on the gate insulating film; and a gate sidewall formed on at least one of side faces of the gate electrode, the side faces being located on a side of the source region and on a side of the drain region, the gate sidewall being made of a high dielectric material. The source region and the drain region are separately-placed from the corresponding side faces of the gate electrode. | 09-27-2012 |
20130240836 | FinFET Having Superlattice Stressor - A fin field effect transistor (FinFET) device is provided. The FinFET includes a superlattice layer and a strained layer. The superlattice layer is supported by a substrate. The strained layer is disposed on the superlattice layer and provides a gate channel. The gate channel is stressed by the superlattice layer. In an embodiment, the superlattice layer is formed by stacking different silicon germanium alloys or stacking other III-V semiconductor materials. | 09-19-2013 |
20130306935 | DOUBLE GATE PLANAR FIELD EFFECT TRANSISTORS - A transistor device includes multiple planar layers of channel material connecting a source region and a drain region, where the planar layers are formed in a stack of layers of a channel material; and a gate conductor formed around and between the planar layers of channel material. | 11-21-2013 |
20140097402 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises: a substrate ( | 04-10-2014 |
20140197375 | SEMICONDUCTOR COMPONENT COMPRISING MICRO-BRIDGES FOR ADJUSTING A TENSILE STRAIN STATE AND METHOD FOR THE PRODUCTION THEREOF - A tensile strain state in semiconductor components is adjusted. A pretensioned (tensile strain) layer is applied to a substrate (FIG. | 07-17-2014 |
20150069327 | FIN FIELD-EFFECT TRANSISTORS WITH SUPERLATTICE CHANNELS - FinFET structures may be formed including superlattice fins. The structure may include a superlattice fin of alternating layers of silicon-germanium with a germanium concentration of approximately 10% to 80% and a second semiconductor material. In some embodiments, the second semiconductor material may include either silicon or carbon-doped silicon. Where the second semiconductor material is carbon-doped silicon, the carbon concentration may range from approximately 0.2% to approximately 4%. The superlattice fin may have a height ranging from approximately 5 nm to approximately 100 nm and include between 5 and 30 alternating layers of silicon-germanium and the second semiconductor material. A gate may be formed over the superlattice fin and a source/drain region may be formed over an end of the superlattice fin. | 03-12-2015 |
20150311327 | ITC-IGBT AND MANUFACTURING METHOD THEREFOR - An ITC-IGBT and a manufacturing method therefor. The method comprises: providing a heavily doped substrate, forming a Ge | 10-29-2015 |
20160099317 | VERTICAL SEMICONDUCTOR DEVICES INCLUDING SUPERLATTICE PUNCH THROUGH STOP LAYER AND RELATED METHODS - A semiconductor device may include a substrate, and a plurality of fins spaced apart on the substrate. Each of the fins may include a lower semiconductor fin portion extending vertically upward from the substrate, and at least one superlattice punch-through layer on the lower fin portion. The superlattice punch-through layer may include a plurality of stacked groups of layers, with each group of layers of the superlattice punch-through layer comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Each fin may also include an upper semiconductor fin portion on the at least one superlattice punch-through layer and extending vertically upward therefrom. The semiconductor device may also include source and drain regions at opposing ends of the fins, and a gate overlying the fins. | 04-07-2016 |
20160133735 | COMMON-SUBSTRATE SEMICONDUCTOR DEVICES HAVING NANOWIRES OR SEMICONDUCTOR BODIES WITH DIFFERING MATERIAL ORIENTATION OR COMPOSITION - Common-substrate semiconductor devices having nanowires or semiconductor bodies with differing material orientation or composition and methods to form such common-substrate devices are described. For example, a semiconductor structure includes a first semiconductor device having a first nanowire or semiconductor body disposed above a crystalline substrate. The first nanowire or semiconductor body is composed of a semiconductor material having a first global crystal orientation. The semiconductor structure also includes a second semiconductor device having a second nanowire or semiconductor body disposed above the crystalline substrate. The second nanowire or semiconductor body is composed of a semiconductor material having a second global crystal orientation different from the first global orientation. The second nanowire or semiconductor body is isolated from the crystalline substrate by an isolation pedestal disposed between the second nanowire or semiconductor body and the crystalline substrate. | 05-12-2016 |
20160172472 | TECHNIQUES FOR FORMING NON-PLANAR GERMANIUM QUANTUM WELL DEVICES | 06-16-2016 |
20160190345 | STRAIN COMPENSATION IN TRANSISTORS - Transistor structures having channel regions comprising alternating layers of compressively and tensilely strained epitaxial materials are provided. The alternating epitaxial layers can form channel regions in single and multigate transistor structures. In alternate embodiments, one of the two alternating layers is selectively etched away to form nanoribbons or nanowires of the remaining material. The resulting strained nanoribbons or nanowires form the channel regions of transistor structures. Also provided are computing devices comprising transistors comprising channel regions comprised of alternating compressively and tensilely strained epitaxial layers and computing devices comprising transistors comprising channel regions comprised of strained nanoribbons or nanowires. | 06-30-2016 |