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Quantum well

Subclass of:

257 - Active solid-state devices (e.g., transistors, solid-state diodes)

257009000 - THIN ACTIVE PHYSICAL LAYER WHICH IS (1) AN ACTIVE POTENTIAL WELL LAYER THIN ENOUGH TO ESTABLISH DISCRETE QUANTUM ENERGY LEVELS OR (2) AN ACTIVE BARRIER LAYER THIN ENOUGH TO PERMIT QUANTUM MECHANICAL TUNNELING OR (3) AN ACTIVE LAYER THIN ENOUGH TO PERMIT CARRIER TRANSMISSION WITH SUBSTANTIALLY NO SCATTERING (E.G., SUPERLATTICE QUANTUM WELL, OR BALLISTIC TRANSPORT DEVICE)

257012000 - Heterojunction

Patent class list (only not empty are listed)

Deeper subclasses:

Class / Patent application numberDescriptionNumber of patent applications / Date published
257024000 Field effect device 255
257015000 Superlattice 179
257025000 Employing resonant tunneling 13
257023000 Current flow across well 4
20080258135SEMICONDUCTOR STRUCTURE HAVING PLURAL BACK-BARRIER LAYERS FOR IMPROVED CARRIER CONFINEMENT - A semiconductor structure having: a channel layer having a conductive channel therein; a pair of polarization generating layers; a spacer layer disposed between the pair of polarization generating layers. The polarization generating layers create polarization fields along a common, predetermined direction. Each one of the pair of polarizations layers may be InGaN; InAlGaN; or quaternary In10-23-2008
20110084251ATOMISTIC QUANTUM DOT - A quantum device is provided that includes controllably quantum mechanically coupled dangling bonds extending from a surface of a semiconductor material. Each of the controllably quantum mechanically coupled dangling bonds has a separation of at least one atom of the semiconductor material. At least one electrode is provided for selectively modifying an electronic state of the controllably quantum mechanically coupled dangling bonds. By providing at least one additional electron within the controllably quantum mechanically coupled dangling bonds with the proviso that there exists at least one unoccupied dangling bond for each one additional electron present, the inventive device is operable at least to 293 degrees Kelvin and is largely immune to stray electrostatic perturbations. Room temperature operable quantum cellular automata and qubits are constructed therefrom.04-14-2011
20080224123Methods for nanowire alignment and deposition - The present invention provides methods and systems for nanowire alignment and deposition. Energizing (e.g., an alternating current electric field) is used to align and associate nanowires with electrodes. By modulating the energizing, the nanowires are coupled to the electrodes such that they remain in place during subsequent wash and drying steps. The invention also provides methods for transferring nanowires from one substrate to another in order to prepare various device substrates. The present invention also provides methods for monitoring and controlling the number of nanowires deposited at a particular electrode pair, as well as methods for manipulating nanowires in solution.09-18-2008
20110248242Practical electrically pumped photonic crystal nanocavity - Electrical pumping of photonic crystal (PC) nanocavities using a lateral p-i-n junction is described. Ion implantation doping can be used to form the junction, which under forward bias pumps a gallium arsenide photonic crystal nanocavity with indium arsenide quantum dots. Efficient cavity-coupled electroluminescence is demonstrated in a first experimental device. Electrically pumped lasing is demonstrated in a second experimental device. This approach provides several significant advantages. Ease of fabrication is improved because difficult timed etch steps are not required. Any kind of PC design can be employed. Current flow can be lithographically controlled to focus current flow to the active region of the device, thereby improving efficiency, reducing resistance, improving speed, and reducing threshold. Insulating substrates can be employed, which facilitates inclusion of these devices in photonic integrated circuits.10-13-2011
Entries
DocumentTitleDate
20100155697Interfering excitations in FQHE fluids - An apparatus includes a substrate with a planar surface, a multilayer of semiconductor layers located on the planar surface, a plurality of electrodes located over the multilayer, and a dielectric layer located between the electrodes and the multilayer. The multilayer includes a 2D quantum well. A first set of the electrodes is located to substantially surround a lateral area of the 2D quantum well. A second set of the electrodes is controllable to vary a lateral width of a non-depleted channel between the substantially surrounded lateral area of the 2D quantum well and another area of the 2D quantum well. A third set of the electrodes is controllable to vary an area of a non-depleted portion of the lateral area.06-24-2010
20080258132QUANTUM DOT OPTOELECTRONIC DEVICE HAVING AN SB-CONTAINING OVERGROWN LAYER - A quantum dot optoelectronic device has an overgrown layer containing antimony (Sb). The optical characteristics and thermal stability of the optoelectronic device are thus greatly enhanced due to the improved crystal quality and carrier confinement of the quantum dot structure.10-23-2008
20110193062Growth of and Defect Reduction in Nanoscale Materials - Methods by which the growth of a nanostructure may be precisely controlled by an electrical current are described here. In one embodiment, an interior nanostructure is grown to a predetermined geometry inside another nanostructure, which serves as a reaction chamber. The growth is effected by a catalytic agent loaded with feedstock for the interior nanostructure. Another embodiment allows a preexisting marginal quality nanostructure to be zone refined into a higher-quality nanostructure by driving a catalytic agent down a controlled length of the nanostructure with an electric current. In both embodiments, the speed of nanostructure formation is adjustable, and the growth may be stopped and restarted at will. The catalytic agent may be doped or undoped to produce semiconductor effects, and the bead may be removed via acid etching.08-11-2011
20100117058MULTI-STRUCTURE NANOWIRE AND METHOD OF MANUFACTURING THE SAME - Provided is a multi-structure nanowire in which silicon nanowires are formed at both ends of a compound semi-conductor nanorod, and a method of manufacturing the multi-structure nanowire. The method includes providing a compound semiconductor nanorod; forming metal catalyst tips on both ends of the compound semiconductor nanorod; and growing silicon nanowires on both ends of the compound semiconductor nanorod where the metal catalyst tips are formed.05-13-2010
20130075698SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor layer provided over a substrate; an electron transit layer contacting a top of the first semiconductor layer; and a second semiconductor layer contacting a top of the electron transit layer, wherein the electron transit layer has a dual quantum well layer having a structure where a first well layer, an intermediate barrier layer, and a second well layer are sequentially stacked, an energy of a conduction band of the intermediate barrier layer is lower than an energy of conduction band of the first semiconductor layer and the second semiconductor layer, and a ground level is generated in the first and second well layers, and a first excitation level is generated in the dual quantum well layer.03-28-2013
20130032780PHOTODIODE, OPTICAL SENSOR DEVICE, AND PHOTODIODE MANUFACTURING METHOD - A photodiode and the like capable of preventing the responsivity on the short wavelength side from deteriorating while totally improving the responsivity in a type II MQW structure, is provided. The photodiode is formed on a group III-V compound semiconductor substrate 02-07-2013
20100051904Dual-Level Self-Assembled Patterning Method and Apparatus Fabricated Using the Method - A method of fabricating a device includes: providing a substrate having a patterned surface, depositing a first-level self-assembled material on at least a portion of the patterned surface, wherein the position and/or orientation of the first-level self-assembled material is directed by the patterned surface, to form a first nanostructure pattern, and depositing a second-level self-assembled material on at least a portion of the first nanostructure pattern to form an array of nanostructures of the second-level self-assembled material. An apparatus fabricated using the method is also provided.03-04-2010
20100044675Photovoltaic Device With an Up-Converting Quantum Dot Layer - A photovoltaic apparatus includes an absorber layer, and an up-converter layer positioned adjacent to the absorber layer, the up-converter layer including a plurality of quantum dots of first material in a matrix of a second material. In one example, the first material has a lower bandgap than the absorber layer, and the second material comprises a semiconductive material or an insulator.02-25-2010
20100102297GALLIUM NITRIDE-BASED EPITAXIAL WAFER AND METHOD OF PRODUCING GALLIUM NITRIDE-BASED SEMICONDUCTOR LIGHT-EMITTING DEVICE - A source gas flows through a flow channel 04-29-2010
20100140586QUANTUM DOTS HAVING COMPOSITION GRADIENT SHELL STRUCTURE AND MANUFACTURING METHOD THEREOF - Provided are quantum dots having a gradual composition gradient shell structure which have an improvedluminous efficiency and optical stability, and a method of manufacturing the quantum dots in a short amount of time at low cost. In the method, the quantum dots can be manufactured in a short amount of time at low cost using a reactivity difference between semiconductor precursors, unlike in uneconomical and inefficient conventional methods where shells areformed after forming cores and performing cleaning and redispersion processes. Also, formation of the cores is followed by formation of shells having a composition gradient. Thus, even if the shells are formed to a large thickness, the lattice mismatch between cores and shells is relieved. Furthermore, on the basis of the funneling concept, electrons and holes generated in the shells are transferred to the cores to emit light, thereby obtaining a high luminous efficiency of 80% or more. The quantum dot structure is not limited to Group II-IV semiconductor quantum dots but can be applied to other semiconductors quantum dots, such as Group III-V semiconductors quantum dots and Group IV-IV semiconductors quantum dots. Also, the manufacturing method can be utilized in the development of semiconductor quantum dots having different physical properties, and in various other fields.06-10-2010
20100108986METHOD FOR THE PRODUCTION OF QUANTUM DOTS EMBEDDED IN A MATRIX, AND QUANTUM DOTS EMBEDDED IN A MATRIX PRODUCED USING THE METHOD - A method for producing quantum dots embedded in a matrix on a substrate includes the steps of: depositing a precursor on the substrate, the precursor including at least one first metal or a metal compound; contacting the deposited precursor and uncovered areas of the substrate with a gas-phase reagent including at least one second metal and/or a chalcogen; and initiating a chemical reaction between the precursor and the reagent by raising a temperature thereof simultaneously with or subsequent to the contacting so that the matrix consists exclusively of elements of the reagent.05-06-2010
20100065818Layers and patterns of nanowire or carbon nanotube using chemical self assembly and fabricating method in liquid crystal display device thereby - Disclosed are layers and patterns of nanowire or nanotube using a chemical self assembly for forming a semiconductor layer and a conductive layer of a thin film transistor by using a nanowire and/or nanotube solution and an diamine-based self-assembled monolayer (SAM) material. The Layers and patterns including layers and patterns of nanowire or nanotube using a chemical self assembly include: a substrate having a surface terminated with amine group (—NH03-18-2010
20100065817Memory device and method of fabricating the same - A memory device includes a first electrode, a second electrode spaced apart from the first electrode and a nanotube or nanowire network disposed between the first electrode and the second electrode, having a heterojunction structure of a P-type network and an N-type network, and having a diode characteristic. Since the nanotube or nanowire network has the heterojunction structure of the P-type network and the N-type network, and has the diode characteristic, it is possible to enhance a degree of integration of the memory device and simplify the fabrication processes without separately requiring a selection device.03-18-2010
20100327258METHOD FOR PRODUCING CORE-SHELL NANOWIRES, NANOWIRES PRODUCED BY THE METHOD AND NANOWIRE DEVICE COMPRISING THE NANOWIRES - Disclosed is a method for producing core-shell nanowires in which an insulating film is previously patterned to block the contacts between nanowire cores and nanowire shells. According to the method, core-shell nanowires whose density and position is controllable can be produced in a simple manner. Further disclosed are nanowires produced by the method and a nanowire device comprising the nanowires. The use of the nanowires leads to an increase in the light emitting/receiving area of the device. Therefore, the device exhibits high luminance/efficiency characteristics.12-30-2010
20120217475Optoelectronic Devices Including Compound Valence-Band Quantum Well Structures - Semiconductor optoelectronic devices based on type-II band alignments comprising a compound valence-band quantum well structure, known as an H-layer, are disclosed. The use of the H-layer structure allows simultaneous optimization of optical properties of the semiconductor structures as well as lattice matching of the various layers of the device. The use of H-layer valence-band quantum wells enables improvements to several optical device applications including semiconductor lasers, optical modulators, photon detectors and the like.08-30-2012
20110006284PHOTONIC STRUCTURE - A photonic structure includes a plurality of annealed, substantially smooth-surfaced ellipsoids arranged in a matrix. Additionally, a method of producing a photonic structure is provided. The method includes providing a semiconductor material, providing an etch mask comprising a two-dimensional hole array, and disposing the etch mask on at least one surface of the semiconductor material. The semiconductor material is then etched through the hole array of the etch mask to produce holes in the semiconductor material and thereafter applying a passivation layer to surfaces of the holes. Additionally, the method includes repeating the etching and passivation-layer application to produce a photonic crystal structure that contains ellipsoids within the semiconductor material and annealing the photonic crystal structure to smooth the surfaces of the ellipsoids.01-13-2011
20130056707NITRIDE SEMICONDUCTOR DEVICE - In the nitride semiconductor device of the present invention, an active layer 03-07-2013
20090032801Approach to contacting nanowire arrays using nanoparticles - An in situ approach toward connecting and electrically contacting vertically aligned nanowire arrays using conductive nanoparticles is provided. The utility of the approach is demonstrated by development of a gas sensing device employing the nanowire assembly. Well-aligned, single-crystalline zinc oxide nanowires were grown through a direct thermal evaporation process at 550° C. on gold catalyst layers. Electrical contact to the top of the nanowire array was established by creating a contiguous nanoparticle film through electrostatic attachment of conductive gold nanoparticles exclusively onto the tips of nanowires. A gas sensing device was constructed using such an arrangement and the nanowire assembly was found to be sensitive to both reducing (methanol) and oxidizing (nitrous oxides) gases. This assembly approach is amenable to any nanowire array for which a top contact electrode is needed.02-05-2009
20120112164FORMATION OF A GRAPHENE LAYER ON A LARGE SUBSTRATE - A single crystalline silicon carbide layer can be grown on a single crystalline sapphire substrate. Subsequently, a graphene layer can be formed by conversion of a surface layer of the single crystalline silicon layer during an anneal at an elevated temperature in an ultrahigh vacuum environment. Alternately, a graphene layer can be deposited on an exposed surface of the single crystalline silicon carbide layer. A graphene layer can also be formed directly on a surface of a sapphire substrate or directly on a surface of a silicon carbide substrate. Still alternately, a graphene layer can be formed on a silicon carbide layer on a semiconductor substrate. The commercial availability of sapphire substrates and semiconductor substrates with a diameter of six inches or more allows formation of a graphene layer on a commercially scalable substrate for low cost manufacturing of devices employing a graphene layer.05-10-2012
20090078930Quantum device, manufacturing method of the same and controlling method of the same - By bringing a tip of an AFM into contact with the surface of a GaAs substrate or an AlGaAs substrate, for example, applying a negative bias to the tip, and applying a positive bias to the GaAs substrate or the AlGaAs substrate, a donut-shaped oxide film is formed. Then, the oxide film is removed. As a result, a ring-shaped groove is formed in the surface of the GaAs substrate or the AlGaAs substrate. The oxide film can be removed by chemical etching, ultrasonic cleaning with water, a treatment with atomic hydrogen in a vacuum, or the like. Thereafter, a semiconductor film (InAs film or InGaAs film, for example) is epitaxially grown in the groove. Then, a capping layer which covers the semiconductor film and the GaAs substrate or the AlGaAs substrate is formed.03-26-2009
20090065764Methods and devices for forming nanostructure monolayers and devices including such monolayers - Methods for forming or patterning nanostructure arrays are provided. The methods involve formation of arrays on coatings comprising nanostructure association groups, patterning using resist, and/or use of devices that facilitate array formation. Related devices for forming nanostructure arrays are also provided, as are devices including nanostructure arrays (e.g., memory devices).03-12-2009
20090267051Method of preparing quantum dot-inorganic matrix composites - A method for preparing a quantum dot-inorganic matrix composite includes preparing an inorganic matrix precursor solution containing one or more quantum dot precursors, spin-coating the precursor solution on a substrate to form an inorganic matrix thin film, and heating the inorganic matrix thin film to form an inorganic matrix, while growing the quantum dot precursors into quantum dots in the inorganic matrix, thereby yielding a quantum dot-inorganic matrix composite. The quantum dot-inorganic matrix composite thus obtained has a structure in which the quantum dots have a high efficiency and are densely filled in an inorganic matrix. The quantum dot-inorganic matrix composites can be prepared using a low temperature process, and can be used for various displays and electronic device material applications.10-29-2009
20090236585NITRIDE SEMICONDUCTOR LIGHT-EMITTING DEVICE, METHOD OF FABRICATING IT, AND SEMICONDUCTOR OPTICAL APPARATUS - A nitride semiconductor laser device has a nitride semiconductor substrate that includes a dislocation-concentrated region 09-24-2009
20130069039Ge QUANTUM DOTS FOR DISLOCATION ENGINEERING OF III-N ON SILICON - A virtual substrate structure includes a crystalline silicon substrate with a first layer of III-N grown on the silicon substrate. Ge clusters or quantum dots are grown on the first layer of III-N and a second layer of III-N is grown on the Ge clusters or quantum dots and any portions of the first layer of III-N exposed between the Ge clusters or quantum dots. Additional alternating Ge clusters or quantum dots and layers of III-N are grown on the second layer of III-N forming an upper surface of III-N. Generally, the additional alternating layers of Ge clusters or quantum dots and layers of III-N are continued until dislocations in the III-N adjacent the upper surface are substantially eliminated.03-21-2013
20090127541REDUCING DEFECTS IN SEMICONDUCTOR QUANTUM WELL HETEROSTRUCTURES - Reducing defects in semiconductor quantum well structures is generally described. In one example, an apparatus includes a semiconductor substrate including silicon, a buffer film epitaxially grown on the semiconductor substrate, the buffer film comprising silicon, germanium, and an impurity, and a first semiconductor film epitaxially grown on the buffer film wherein a lattice mismatch exists between the semiconductor substrate and the first semiconductor film and wherein the impurity disrupts lattice structure dislocation gliding in at least the first semiconductor film.05-21-2009
20110278539GENERATION OF MULTIPLE DIAMETER NANOWIRE FIELD EFFECT TRANSISTORS - A method of modifying a wafer having a semiconductor disposed on an insulator is provided and includes forming first and second nanowire channels connected at each end to semiconductor pads at first and second wafer regions, respectively, with second nanowire channel sidewalls being misaligned relative to a crystallographic plane of the semiconductor more than first nanowire channel sidewalls and displacing the semiconductor toward an alignment condition between the sidewalls and the crystallographic plane such that thickness differences between the first and second nanowire channels reflect the greater misalignment of the second nanowire channel sidewalls.11-17-2011
20110140082LIGHT-RECEIVING ELEMENT AND LIGHT-RECEIVING ELEMENT ARRAY - Provided are a light-receiving element which has sensitivity in the near-infrared region and in which a good crystal quality is easily obtained, a one-dimensional or two-dimensional array of the light-receiving elements is easily formed with a high accuracy, and a dark current can be reduced; a light-receiving element array; and methods for producing the same.06-16-2011
20100171096Segmented Nanowires Displaying Locally Controllable Properties - Vapor-liquid-solid growth of nanowires is tailored to achieve complex one-dimensional material geometries using phase diagrams determined for nanoscale materials. Segmented one-dimensional nanowires having constant composition display locally variable electronic band structures that are determined by the diameter of the nanowires. The unique electrical and optical properties of the segmented nanowires are exploited to form electronic and optoelectronic devices. Using gold-germanium as a model system, in situ transmission electron microscopy establishes, for nanometer-sized Au—Ge alloy drops at the tips of Ge nanowires (NWs), the parts of the phase diagram that determine their temperature-dependent equilibrium composition. The nanoscale phase diagram is then used to determine the exchange of material between the NW and the drop. The phase diagram for the nanoscale drop deviates significantly from that of the bulk alloy.07-08-2010
20100171095Super Sensitive UV Detector Using Polymer Functionalized Nanobelts - An ultraviolet light sensor includes an elongated metal oxide nanostructure, a layer of an ultraviolet light-absorbing polymer, a current source and a current detector. The elongated metal oxide nanostructure has a first end and an opposite second end. The layer of an ultraviolet light-absorbing polymer is disposed about at least a portion of the metal oxide nanostructure. The current source is configured to provide electrons to the first end of the metal oxide nanostructure. The current detector is configured to detect an amount of current flowing through the metal oxide nanostructure. The amount of current flowing through the metal oxide nanostructure corresponds to an amount of ultraviolet light impinging on the metal oxide nanostructure.07-08-2010
20100148152ELECTRICALLY CONTROLLED CATALYTIC NANOWIRE GROWTH - A population of nanowires can be prepared by a method involving electric field catalyzed growth and alteration based on surface charge density.06-17-2010
20100059736Heterostructure Nanotube Devices - Heterostructure devices incorporate carbon nanotube technology to implement rectifying devices including diodes, rectifiers, silicon-controlled rectifiers, varistors, and thyristors. In a specific implementation, a rectifying device includes carbon nanotube and nanowire elements. The carbon nanotubes may be single-walled carbon nanotubes. The devices may be formed using parallel pores of a porous structure. The porous structure may be anodized aluminum oxide or another material. A device of the invention may be especially suited for high power applications.03-11-2010
20120025167Vertical Light Emitting Diode (VLED) Die Having Electrode Frame And Method Of Fabrication - A vertical light emitting diode (VLED) die includes a metal base; a mirror on the metal base; a p-type semiconductor layer on the reflector layer; a multiple quantum well (MQW) layer on the p-type semiconductor layer configured to emit light; and an n-type semiconductor layer on the multiple quantum well (MQW) layer. The vertical light emitting diode (VLED) die also includes an electrode and an electrode frame on the n-type semiconductor layer, and an organic or inorganic material contained within the electrode frame. The electrode and the electrode frame are configured to provide a high current capacity and to spread current from the outer periphery to the center of the n-type semiconductor layer. The vertical light emitting diode (VLED) die can also include a passivation layer formed on the metal base surrounding and electrically insulating the electrode frame, the edges of the mirror, the edges of the p-type semiconductor layer, the edges of the multiple quantum well (MQW) layer and the edges of the n-type semiconductor layer.02-02-2012
20090189145Photodetectors, Photovoltaic Devices And Methods Of Making The Same - A photodetector includes a first layer, a second layer and a plurality of nanowires established between the first and second layers. At least some of the plurality of nanowires have a bandgap that is different from a bandgap of at least some other of the plurality of nanowires.07-30-2009
20110266521POROUS AND NON-POROUS NANOSTRUCTURES - Disclosed are a variety of porous and non-porous wire-like structures of microscopic and nanoscopic scale. For instance, disclosed are structures that comprise a porous object that comprises: (i) a first region; and (ii) a second region adjacent to the first region along an axis of the object, where the first region has at least one porous property different from that of the second region. Also disclosed are structures that include: (i) a high resistivity silicon; and (ii) a cross-section that is substantially perpendicular to an axis of the object. Also disclosed are methods of making and using such structures. For instance, the present invention provides methods of making a porous object by: (i) obtaining an etchable substrate; (ii) forming on a surface of the substrate a patterned porosification assisting metal layer that has at least one opening; and (iii) subsequently exposing the substrate to a first etching solution and a second etching solution to form respectively a first region and a second region of a porous object.11-03-2011
20110062416NANOWIRE-BASED PHOTODIODE - A nanowire-based photodiode and an interdigital p-i-n photodiode use an i-type semiconductor nanowire in an i-region of the photodiode. The nanowire-based photodiode includes a first sidewall of a first semiconductor doped with a p-type dopant, a second sidewall of the first semiconductor doped with an n-type dopant, and an intrinsic semiconductor nanowire that spans a trench between the first and second sidewalls. The trench is wider at a top than at a bottom adjacent to a substrate. The first semiconductor of one or both of the first sidewall and the second sidewall is single crystalline and together the first sidewall, the nanowire and the second sidewall form a p-i-n semiconductor junction of the photodiode.03-17-2011
20110062415ANISOTROPIC STRAIN CONTROL IN SEMIPOLAR NITRIDE QUANTUM WELLS BY PARTIALLY OR FULLY RELAXED ALUMINUM INDIUM GALLIUM NITRIDE LAYERS WITH MISFIT DISLOCATIONS - An epitaxial structure for a III-Nitride based optical device, comprising an active layer with anisotropic strain on an underlying layer, where a lattice constant and strain in the underlying layer are partially or fully relaxed in at least one direction due to a presence of misfit dislocations, so that the anisotropic strain in the active layer is modulated by the underlying layer.03-17-2011
20100090196Optical semiconductor device and manufacturing method of the same - A side barrier is provided between columnar dots each constituted by directly stacking respective quantum dots in seven or more layers. Out of respective side barrier layers composing the side barrier, each of the lower side barrier layers (four layers of the undermost layer to the fourth layer from the bottom) is formed as a first side barrier layer into which a tensile strain is introduced, and each of the upper side barrier layers (three layers of the fifth Layer to the uppermost layer from the bottom) is formed as a second side barrier layer which has no strain.04-15-2010
20090090902OPTICAL DEVICES USING A PENTERNARY III-V MATERIAL SYSTEM - The invention relates to the design and processing of a semiconductor optical device. The device is formed of at least four layers of III-V compounds in which one consists of the penternary AlGalnAsSb material. The structure is wet etched in order to form optical ridge waveguides. One such device has incorporated two waveguides which are connected through a new junction design which can be made by wet etching. In one design the junction and waveguides consists of wet etched AlO .90GaO .10AsSb cladding around a core of AlO .28GaO .72AsSb in which an active layer composed of AlO.22InO.22GaO.55AsSb/InO.29GaO.71AsSb quantum wells is embedded. The resulting device is a erdge junction laser which has single mode emission and emits a narrow line width. We made and tested a device in the 2.34 müm to 2.375 müm wavelength area and found it to have an emission line width of around 0, 5 nm.04-09-2009
20090283748SEMICONDUCTOR FOR USE IN HARSH ENVIRONMENTS - A gallium-nitride semiconductor apparatus may include an active region having one or more nitride-based barrier layers that are modulation-doped using a nitride-based doped layer. An active region may have at least two nitride-based barrier layers, and a nitride-based blocking layer may be disposed between the at least two barrier layers.11-19-2009
20090283750SUBSTRATE-FREE LIGHT EMITTING DIODE - A substrate-free light emitting diode (LED) including an epitaxy layer, a conductive supporting layer, and a first contact pad is provided. The epitaxy layer includes a first type doped semiconductor layer, a light emitting layer, and a second type doped semiconductor layer. The light emitting layer is disposed on the first type doped semiconductor layer, and a portion of the first type doped semiconductor layer is exposed. The second type doped semiconductor layer and the conductive supporting layer are sequentially disposed on the second type doped semiconductor layer. The first contact pad is disposed on the exposed first type doped semiconductor layer and electrically connected thereto. The first contact pad and the conductive supporting layer serving as an electrode are disposed on the same side of the epitaxy layer to avoid the light shielding effects of the electrode to improve the front light emitting efficiency of the LED.11-19-2009
20090283749QUANTUM-WELL PHOTOELECTRIC DEVICE ASSEMBLED FROM NANOMEMBRANES - A quantum-well photoelectric device, such as a quantum cascade laser, is constructed of monocrystalline nanoscale membranes physically removed from a substrate and mechanically assembled into a stack.11-19-2009
20090294757Semiconductor Nanowire Vertical Device Architecture - The present invention relates to nanoscaled electronic devices with a vertical nanowire as a functional part. Contacts are arranged on the nanowire at different parts of the nanowire, for example drain and source contacts. In connection to the nanowire contacts are external electrodes, that connect at different levels, as seen from the substrate, of the device. The external electrodes are elongated, and typically and preferably stripe-like. According to the invention a first external electrode, or contacts, associated with contact(s) at a first part of the nanowire, and a second external electrode, associated with contact(s) at a second part of the nanowire are arranged in a cross-bar configuration. The cross-bar configuration minimizes the overlay of the external electrodes, hence, parasitic capacitances and current leakage can be reduced, and the performance of the device improved.12-03-2009
20110204329NON-POLAR (Al,B,In,Ga)N QUANTUM WELL AND HETEROSTRUCTURE MATERIALS AND DEVICES - A method for forming non-polar (Al,B,In,Ga)N quantum well and heterostructure materials and devices. Non-polar (11 08-25-2011
20090242872DOUBLE QUANTUM WELL STRUCTURES FOR TRANSISTORS - Double quantum well structures for transistors are generally described. In one example, an apparatus includes a semiconductor substrate, one or more buffer layers coupled to the semiconductor substrate, a first barrier layer coupled to the one or more buffer layers, a first quantum well channel coupled with the first barrier layer wherein the first quantum well channel includes a group III-V semiconductor material or a group II-VI semiconductor material, or combinations thereof, a second barrier layer coupled to the first quantum well channel, and a second quantum well channel coupled to the barrier layer wherein the second quantum well channel includes a group III-V semiconductor material or a group II-VI semiconductor material, or combinations thereof.10-01-2009
20080296555LAMP WITH CONTROLLABLE SPECTRUM - An area illumination inorganic electro-luminescent device including a substrate; and an array of one or more commonly addressed, light-emitting elements. Each commonly-addressed, light-emitting element includes a first electrode layer formed over the substrate, one or more light-emitting layers formed over the first electrode layer and a second electrode layer formed over the light-emitting layer. The light-emitting layers include multiple core/shell quantum dot emitters formed in a common polycrystalline semiconductor matrix, and a number of different core/shell quantum dot emitters emit light with a spectral power distribution having a peak and a FWHM bandwidth, such that the peak wavelengths differ by an amount less than or equal to the average FWHM bandwidth of the different core/shell quantum dot emitters within the range of 460 to 670 nm.12-04-2008
20110204328NITRIDE BASED DEVICES INCLUDING A SYMMETRICAL QUANTUM WELL ACTIVE LAYER HAVING A CENTRAL LOW BANDGAP DELTA-LAYER - A symmetrical quantum well active layer provides enhanced internal quantum efficiency. The quantum well active layer includes an inner (central) layer and a pair of outer layers sandwiching the inner layer. The inner and outer layers have different thicknesses and bandgap characteristics. The outer layers are relatively thick and include a relatively low bandgap material, such as InGaN. The inner layer has a relatively lower bandgap material and is sufficiently thin to act as a quantum well delta layer, e.g., comprising approximately 6 Å or less of InN. Such a quantum well structure advantageously extends the emission wavelength into the yellow/red spectral regime, and enhances spontaneous emission. The multi-layer quantum well active layer is sandwiched by barrier layers of high bandgap materials, such as GaN.08-25-2011
20080258133Semiconductor Device and Method of Fabricating the Same - Disclosed is a semiconductor device. The semiconductor device includes a first type nitride-based cladding layer formed on a growth substrate having an insulating property, a multi quantum well nitride-based active layer formed on the first type nitride-based cladding layer and a second type nitride-based cladding layer, which is different from the first type nitride-based cladding layer and is formed on the multi quantum well nitride-based active layer. A tunnel junction layer is formed between the undoped buffering nitride-based layer and the first type nitride-based cladding layer or/and formed on the second type nitride-based cladding layer.10-23-2008
20100155699NITRIDE SEMICONDUCTOR DEVICE - A nitride semiconductor device includes n-type and p-type nitride semiconductor layers, an active layer, the active layer having a lamination of quantum barrier layers and quantum well layers, a thermal stress control layer disposed between the n-type nitride semiconductor layer and the active layer, and formed of a material having a smaller thermal expansion coefficient than the n-type and p-type nitride semiconductor layers, and a lattice stress control layer disposed between the thermal stress control layer and the active layer, and including a first layer and a second layer.06-24-2010
20080277646Vertical Type Nanotube Semiconductor Device - A vertical type nanotuhe semiconductor device including a nanotube bit line, disposed on a substrate and in parallel with the substrate and composed of a nanotube with a conductive property, and a nanotube pole connected to the bit line vertically to the substrate and provides a channel through which carriers migrate. By manufacturing the semiconductor device using the bit line composed of the nanotube, cutoff of an electrical connection of the bit line is prevented and an integration density of the semiconductor device can be improved.11-13-2008
20080315182Optical semiconductor device and method for manufacturing the same - There is provided an optical semiconductor device having a first optical semiconductor element including an InP substrate, a lower cladding layer formed on the InP substrate, a lower optical guide layer which is formed on the lower cladding layer and is composed of AlGaInAs, an active layer which is formed on the lower optical guide layer and has a multiple quantum well structure where a well layer and a barrier layer that is formed of AlGaInAs are alternately stacked, an upper optical guide layer which is formed on the active layer and is composed of InGaAsP, and an upper cladding layer formed on the upper optical guide layer.12-25-2008
20080237574Metal-Base Nanowire Transistor - A metal-base transistor is suggested. The transistor comprises a first and a second electrode (10-02-2008
20080272364INSULATING FILM AND ELECTRONIC DEVICE - An insulating film comprising: a first barrier layer; a well layer provided; and a second barrier layer is proposed. The first barrier layer consists of a material having a first bandgap and a first relative permittivity. The well layer is provided on the first barrier layer, and consists of a material having a second bandgap smaller than the first bandgap and having a second relative permittivity larger than first relative permittivity. Discrete energy levels are formed in the well layer by a quantum effect. The second barrier layer is provided on the well layer, and consists of a material having a third bandgap larger than the second bandgap and having a third relative permittivity smaller than second relative permittivity. Alternatively, an insulating film comprising: n (n being an integer larger than 2) layers of barrier layer consisting of a material having a bandgap larger than a first bandgap and having a relative permittivity smaller than a first relative permittivity; and (n−1) layers of well layers consisting of a material having a bandgap smaller than the first bandgap and having a relative permittivity larger than the first relative permittivity, discrete energy levels being formed in the well layer by a quantum effect, each of the barrier layers and each of the well layers being stacked by turns, and discrete energy levels being formed in each of the well layers by a quantum effect, is provided. Alternatively, an insulating film having a lattice mismatch within a range of plus-or-minus 1.5% to the substrate, and further having a high barrier and a large permittivity is provided.11-06-2008
20080277645Ferromagneic Influence on Quantum Dots - A semiconductor magnetic body comprises a layer (11-13-2008
20080272363Selectively Conducting Devices, Diode Constructions, Constructions, and Diode Forming Methods - Some embodiments include selectively conducting devices having a first electrode, a second electrode, and dielectric material between the first and second electrodes. The dielectric material may be configured to conduct current from the first electrode to the second electrode when a first voltage is applied across the first electrode and the second electrode. Furthermore, the dielectric material may be configured to inhibit current from flowing from the second electrode to the first electrode when a second voltage having a polarity opposite that of a polarity of the first voltage is applied across the first electrode and the second electrode. The diode material may comprise a plurality of layers of different dielectric materials arranged in order of increasing barrier height. Quantum wells may form at junctions of layers of the plurality responsive to the first voltage. Some embodiments include diode forming methods.11-06-2008
20090001351Insb Thin Film Magnetic Sensor and Fabrication Method Thereof - The present invention relates to a thin film lamination to be used in a micro InSb thin film magnetic sensor which can directly detect a magnetic flux density with high sensitivity and has small power consumption and consumption current, and the InSb thin film magnetic sensor. The InSb thin film magnetic sensor uses an InSb thin film as a magnetic sensor section or a magnetic detecting section. The sensor includes an InSb layer that is an InSb thin film formed on a substrate, and an Al01-01-2009
20120068156InN Nanowire Based Multifunctional Nanocantilever Sensors - Sensor are generally provided that include a layer of silicon oxide on a portion of a n+ layer to form an uneven surface where the layer of silicon oxide defines a thicker region than an exposed portion of the n+ layer. First and second metal contacts can be on the layer of silicon oxide, with first and second nanowires extending respectively from a first base on the first metal contact and a second base on the second metal contact. The first nanowire and the second nanowire are connected together at an apex to form a v-shaped nanocantilever, wherein the apex is positioned over the exposed n+ layer, and wherein the nanowires comprise indium and nitrogen. Methods of fabricating such sensors, along with methods of their use, are also generally provided.03-22-2012
20090206324DISLOCATION REMOVAL FROM A GROUP III-V FILM GROWN ON A SEMICONDUCTOR SUBSTRATE - Dislocation removal from a group III-V film grown on a semiconductor substrate is generally described. In one example, an apparatus includes a semiconductor substrate, a buffer film including a group III-V semiconductor material epitaxially coupled to the semiconductor substrate wherein the buffer film includes material melted by laser pulse irradiation and recrystallized to substantially remove dislocations or defects from the buffer film, and a first semiconductor film epitaxially grown on the buffer film wherein a lattice mismatch exists between the semiconductor substrate and the first semiconductor film.08-20-2009
20080315181Nanotube schottky diodes for high-frequency applications - Described is a Schottky diode using semi-conducting single-walled nanotubes (s-SWNTs) with titanium Schottky and platinum Ohmic contacts for high-frequency applications. The diodes are fabricated using angled evaporation of dissimilar metal contacts over an s-SWNT. The devices demonstrate rectifying behavior with large reverse-bias breakdown voltages of greater than −15 V. In order to decrease the series resistance, multiple SWNTs are grown in parallel in a single device, and the metallic tubes are burnt-out selectively. At low biases, these diodes showed ideality factors in the range of 1.5 to 1.9. Modeling of these diodes as direct detectors at room temperature at 2.5 terahertz (THz) frequency indicates noise equivalent powers (NEP) comparable to that of the state-of-the-art gallium arsenide sold-state Schottky diodes, in the range of 10-13 W/square-root (√) Hz.12-25-2008
20090101888METHOD OF MANUFACTURING IN (As) Sb SEMICONDUCTOR ON LATTICE-MISMATCHED SUBSTRATE AND SEMICONDUCTOR DEVICE USING THE SAME - Disclosed is a method of manufacturing a semiconductor device whereby InAs04-23-2009
20090078929NANOWIRE DEVICE AND METHOD OF MAKING A NANOWIRE DEVICE - A method of making nanowires includes providing a silicon substrate having a silicon dioxide insulation on the surface thereof. The silicon dioxide is etched to form one or more pillars, each having a plurality of sidewalls. A thin film of gold is deposited on a sidewall and is subjected to an annealing process. The annealing process causes the gold film to form a globular catalyst particle. The structure is placed in an LPCVD furnace into which is introduced silane gas. Silicon from the gas migrates through the catalyst particle and grows a nanowire from the sidewall of the pillar to a desired length. Electrical contacts are provided at each end of the nanowire to create an active component useable in an electronic circuit.03-26-2009
20090101887SILICON GERMANIUM HETEROSTRUCTURE BARRIER VARACTOR - Methods and heterostructure barrier varactor (HBV) diodes optimized for application with frequency multipliers at providing outputs at submillimeter wave frequencies and above. The HBV diodes include a silicon-containing substrate, an electrode over the silicon-containing substrate, and one or more heterojunction quantum wells of alternating layers of Si and SiGe of one or more electrodes of the diode. Each SiGe quantum well preferably has a floating SiGe layer between adjacent SiGe gradients followed by adjacent Si layers, such that, a single homogeneous structure is provided characterized by having no distinct separations. The plurality of Si/SiGe heterojunction quantum wells may be symmetric or asymmetric.04-23-2009
20110227040TEMPERATURE SENSOR AND MANUFACTURING METHOD OF TEMPERATURE SENSOR - A temperature sensor includes a semiconductor substrate and a quantum well structural part disposed on the semiconductor substrate. The semiconductor substrate is made of a plurality of elements. The quantum well structural part has a resistance value that changes with temperature. The quantum well structural part includes a plurality of semiconductor layers made of the elements. The semiconductor layers include a plurality of quantum barrier layers and a quantum well layer disposed between the quantum barrier layers. When the semiconductor substrate has a lattice constant “a,” each of the quantum barrier layers has a lattice constant “b,” and the quantum well layer has a lattice constant “c,” the semiconductor substrate, the quantum barrier layers, and the quantum well layer satisfy a relationship of b09-22-2011
20090200539Composite Nanorod-Based Structures for Generating Electricity - Composite nanorod-based structures for generating electricity are disclosed. One embodiment is an article of manufacture that includes a first layer with an array of nanowires and a dielectric material. The nanowires include: a core semiconducting region with a first type of doping; a shell semiconducting region with a second type of doping; and a junction region between the core semiconducting region and the shell semiconducting region. The first type of doping is different from the second type of doping. The shell region length is less than the core region length. The shell semiconducting region surrounds a portion of the core semiconducting region over a length of the core semiconducting region corresponding to the junction region length. A second layer comprising a conducting material contacts the top surface of the first layer. A third layer comprising a conducting material contacts the bottom surface of the first layer.08-13-2009
20090200538Group lll-V compound semiconductor and a method for producing the same - A Group III-V compound semiconductor includes an n-type layer, a p-type layer, a p-type layer represented by a formula In08-13-2009
20090230382III-V semiconductor core-heteroshell nanocrystals - The present invention provides a core/multishell semiconductor nanocrystal comprising a core and multiple shells, which exhibits a type-I band offset and high photoluminescence quantum yield providing bright tunable emission covering the visible range from about 400 nm to NIR over 1600 nm.09-17-2009
20120104359Method of Fabricating Optical Devices Using Laser Treatment of Contact Regions of Gallium and Nitrogen Containing Material - A method for forming optical devices includes providing a gallium nitride substrate having a crystalline surface region and a backside region. The backside is subjected to a laser scribing process to form scribe regions. Metal contacts overly the scribe regions.05-03-2012
20120104358SEMICONDUCTOR CHIP CARRIERS WITH MONOLITHICALLY INTEGRATED QUANTUM DOT DEVICES AND METHOD OF MANUFACTURE THEREOF - A three-dimensional polycrystalline semiconductor material provides a major ingredient forming individual crystalline grains having a nominal maximum grain diameter less than or equal to 50 nm, and a minor ingredient forming boundaries between the individual crystalline grains.05-03-2012
20120193608FRONTSIDE-ILLUMINATED INVERTED QUANTUM WELL INFRARED PHOTODETECTOR DEVICES AND METHODS OF FABRICATING THE SAME - A method of fabricating a frontside-illuminated inverted quantum well infrared photodetector may include providing a quantum well wafer having a bulk substrate layer and a quantum material layer, wherein the quantum material layer includes a plurality of alternating quantum well layers and barrier layers epitaxially grown on the bulk substrate layer. The method further includes applying at least one frontside common electrical contact to a frontside of the quantum well wafer, bonding a transparent substrate to the frontside of the quantum well wafer, thinning the bulk substrate layer of the quantum well wafer, and etching the quantum material layer to form quantum well facets that define at least one pyramidal quantum well stack. A backside electrical contact may be applied to the pyramidal quantum well stack. In one embodiment, a plurality of quantum well stacks is bonded to a read-out integrated circuit of a focal plane array.08-02-2012
20100155698Nanoscale wires and related devices - The present invention relates generally to sub-microelectronic circuitry, and more particularly to nanometer-scale articles, including nanoscale wires which can be selectively doped at various locations and at various levels. In some cases, the articles may be single crystals. The nanoscale wires can be doped, for example, differentially along their length, or radially, and either in terms of identity of dopant, concentration of dopant, or both. This may be used to provide both n-type and p-type conductivity in a single item, or in different items in close proximity to each other, such as in a crossbar array. The fabrication and growth of such articles is described, and the arrangement of such articles to fabricate electronic, optoelectronic, or spintronic devices and components. For example, semiconductor materials can be doped to form n-type and p-type semiconductor regions for making a variety of devices such as field effect transistors, bipolar transistors, complementary inverters, tunnel diodes, light emitting diodes, sensors, and the like.06-24-2010
20100155696Large-Area Nanoenabled Macroelectronic Substrates and Uses Therefor - A method and apparatus for an electronic substrate having a plurality of semiconductor devices is described. A thin film of nanowires is formed on a substrate. The thin film of nanowires is formed to have a sufficient density of nanowires to achieve an operational current level. A plurality of semiconductor regions are defined in the thin film of nanowires. Contacts are formed at the semiconductor device regions to thereby provide electrical connectivity to the plurality of semiconductor devices. Furthermore, various materials for fabricating nanowires, thin films including p-doped nanowires and n-doped nanowires, nanowire heterostructures, light emitting nanowire heterostructures, flow masks for positioning nanowires on substrates, nanowire spraying techniques for depositing nanowires, techniques for reducing or eliminating phonon scattering of electrons in nanowires, and techniques for reducing surface states in nanowires are described.06-24-2010
20100187499METHOD FOR EPITAXIAL GROWTH AND EPITAXIAL LAYER STRUCTURE USING THE METHOD - There are provided a method for epitaxial growth capable of securing stable optical and electrical characteristics by minimizing defects produced in a second epitaxial layer when growing the second epitaxial layer on a first epitaxial layer having defects formed therein, and an epitaxial layer structure using the method. The method includes preparing a first epitaxial layer having a defect formed therein, forming a metal quantum dot on the first epitaxial layer, allowing the metal quantum dot to be moved onto a step of the first epitaxial layer due to a difference of surface energy, converting the metal quantum dot into a metal quantum-dot semiconductor crystal having a lattice constant corresponding to that of the first epitaxial layer, and growing a second epitaxial layer on the first epitaxial layer.07-29-2010
20100187500CARBON STRUCTURES BONDED TO LAYERS WITHIN AN ELECTRONIC DEVICE - An OLED electronic device contains a fullerene chemically bonded to a hole transport layer. The bonding of the fullerene to the hole transport layer improves device lifetime and prevents migration of the fullerene to adjacent layers where deleterious effects may result.07-29-2010
20100176375Diode-Based Devices and Methods for Making the Same - In accordance with an embodiment, a diode comprises a substrate, a dielectric material including an opening that exposes a portion of the substrate, the opening having an aspect ratio of at least 1, a bottom diode material including a lower region disposed at least partly in the opening and an upper region extending above the opening, the bottom diode material comprising a semiconductor material that is lattice mismatched to the substrate, a top diode material proximate the upper region of the bottom diode material, and an active diode region between the top and bottom diode materials, the active diode region including a surface extending away from the top surface of the substrate.07-15-2010
20110175059II-VI CORE-SHELL SEMICONDUCTOR NANOWIRES - A plurality of core-shell semiconductor nanowires each being fixed to a support includes II-VI materials for both the cores and the shells. Each nanowire terminates in a free end and a metal alloy nanoparticle is fixed to each nanowire at its free end.07-21-2011
20100219396Mechanism for Forming a Remote Delta Doping Layer of a Quantum Well Structure - A method of fabricating a quantum well device includes forming a diffusion barrier on sides of a delta layer of a quantum well to confine dopants to the quantum well.09-02-2010
20100252810GATE PATTERNING OF NANO-CHANNEL DEVICES - Methodologies and gate etching processes are presented to enable the fabrication of gate conductors of semiconductor devices, such as NFETs and/or PFETs, which are equipped with nano-channels. In one embodiment, a sacrificial spacer of equivalent thickness to the diameter of the gate nano-channel is employed and is deposited after patterning the gate conductor down to the gate dielectric. The residue gate material that is beneath the nano-channel is removed utilizing a medium to high density, bias-free, fluorine-containing or fluorine- and chlorine-containing isotropic etch process without compromising the integrity of the gate. In another embodiment, an encapsulation/passivation layer is utilized. In yet further embodiment, no sacrificial spacer or encapsulation/passivation layer is used and gate etching is performed in an oxygen and nitrogen-free ambient.10-07-2010
20120187373Stepwise Surface Assembly of Quantum Dot-Fullerene Heterodimers - The present invention relates to high-purity quantum dot-fullerene dimers with controllable linker length and the process of fabricating the same. More particularly, this invention relates to the design, synthesis, and application of high-purity quantum dot-fullerene dimers by applying a novel stepwise surface assembly procedure that ensures the formation of conjugates due to steric repulsion effects between the quantum dots.07-26-2012
20100140587High-Injection Heterojunction Bipolar Transistor - A method for manufacturing high-injection heterojunction bipolar transistor capable of being used as a photonic device is disclosed. A sub-collector layer is formed on a substrate. A collector layer is then deposited on top of the sub-collector layer. After a base layer has been deposited on top of the collector layer, a quantum well layer is deposited on top of the base layer. An emitter is subsequently formed on top of the quantum well layer.06-10-2010
20100127240Carbon nanotube fabrication from crystallography oriented catalyst - A device and method associated with carbon nanowires, such as single walled carbon nanowires having a high degree of alignment are set forth herein. A catalyst layer is deposited having a predetermined crystallographic configuration so as to control a growth parameter, such as an alignment direction, a diameter, a crystallinity and the like of the carbon nanowire. The catalyst layer is etched to expose a sidewall portion. The carbon nanowire is nucleated from the exposed sidewall portion. An electrical circuit device can include a single crystal substrate, such as Silicon, and a crystallographically oriented catalyst layer on the substrate having an exposed sidewall portion. In the device, carbon nanowires are disposed on the single crystal substrate aligned in a direction associated with the crystallographic properties of the catalyst layer.05-27-2010
20090114901Room Temperature Carbon Nanotubes Integrated on CMOS - Embodiments of the invention integrate carbon nanotubes on a CMOS substrate using localized heating. An embodiment can allow the CMOS substrate to be in a room-temperature environment during the carbon nanotube growth process. Specific embodiments utilize a maskless post-CMOS microelectromechanical systems (MEMS) process. The post-CMOS MEMS process according to an embodiment of the present invention provides a carbon nanotube growth process that is foundry CMOS compatible. The maskless process, according to an embodiment, eliminates the need for photomasks after the CMOS fabrication and can preserve whatever feature sizes are available in the foundry CMOS process. Embodiments integrate single-walled carbon nanotube devices into a CMOS platform.05-07-2009
20110108800SILICON BASED SOLID STATE LIGHTING - A semiconductor device includes a substrate comprising a first surface having a first orientation and a second surface having a second orientation and a plurality of III-V nitride layers on the substrate, wherein the plurality of III-V nitride layers are configured to emit light when an electric current is produced in one or more of the plurality of III-V nitride layers.05-12-2011
20090072221NITRIDE SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A nitride semiconductor device comprises: a well layer of nitride semiconductor containing In and Ga; barrier layers of nitride semiconductor sandwiching the well layer, containing Al and Ga, and having a larger band gap energy than the well layer; and a thin film layer provided between the well layer and the barrier layer. The thin film layer is formed during lowering of the substrate temperature after formation of the barrier layer or during elevation of the substrate temperature after formation of the well layer.03-19-2009
20080272365INSULATING FILM AND ELECTRONIC DEVICE - An insulating film comprising: a first barrier layer; a well layer provided; and a second barrier layer is proposed. The first barrier layer consists of a material having a first bandgap and a first relative permittivity. The well layer is provided on the first barrier layer, and consists of a material having a second bandgap smaller than the first bandgap and having a second relative permittivity larger than first relative permittivity. Discrete energy levels are formed in the well layer by a quantum effect. The second barrier layer is provided on the well layer, and consists of a material having a third bandgap larger than the second bandgap and having a third relative permittivity smaller than second relative permittivity. Alternatively, an insulating film comprising: n (n being an integer larger than 2) layers of barrier layer consisting of a material having a bandgap larger than a first bandgap and having a relative permittivity smaller than a first relative permittivity; and (n−1) layers of well layers consisting of a material having a bandgap smaller than the first bandgap and having a relative permittivity larger than the first relative permittivity, discrete energy levels being formed in the well layer by a quantum effect, each of the barrier layers and each of the well layers being stacked by turns, and discrete energy levels being formed in each of the well layers by a quantum effect, is provided. Alternatively, an insulating film having a lattice mismatch within a range of plus-or-minus 1.5% to the substrate, and further having a high barrier and a large permittivity is provided.11-06-2008
20090108252Lateral two-terminal nanotube devices and method for their formation - An apparatus, system, and method are provided for a lateral two-terminal nanotube device configured to capture and generate energy, to store electrical energy, and to integrate these functions with power management circuitry. The lateral nanotube device can include a substrate, an anodic oxide material disposed on the substrate, and a column disposed in the anodic oxide material extending from one distal end of the anodic oxide material to another end of the anodic oxide material. The lateral nanotube device further can include a first material disposed within the column, and a second material disposed within the column. The first material fills a distal end of the column and gradiently decreases towards another distal end of the column along inner walls of the column. The second material fills the another distal end of the column and gradiently decreases towards the distal end of the column within the first material.04-30-2009
20090108251CONTROLLED GROWTH OF A NANOSTRUCTURE ON A SUBSTRATE - The present invention provides for nanostructures grown on a conducting substrate, and a method of making the same. The nanostructures grown according to the claimed method are suitable for manufacturing electronic devices such as an electron beam writer, and a field emission display.04-30-2009
20100295018NANOSTRUCTURES AND METHODS OF MAKING THE SAME - A nanostructure includes a highly conductive microcrystalline layer, a bipolar nanowire, and another layer (11-25-2010
20100301308PHOTODETECTORS - Implementations of quantum well photodetectors are provided. In one embodiment, a quantum structure includes a first barrier layer, a well layer located on the first barrier layer, and a second barrier layer located on the well layer. A metal layer is located adjacent to the quantum structure.12-02-2010
20110001125PHOTODETECTOR CAPABLE OF DETECTING LONG WAVELENGTH RADIATION - Apparatuses capable of and techniques for detecting long wavelength radiation are provided.01-06-2011
20110001124PHOTODETECTOR CAPABLE OF DETECTING THE VISIBLE LIGHT SPECTRUM - Apparatuses capable of and techniques for detecting the visible light spectrum are provided.01-06-2011
20110024723Nanoparticle synthesis - A noble metal nanoparticle can be grown on a semiconductor substrate by contacting a predetermined region of the substrate with a solution including noble metal ions. The predetermined region of the semiconductor substrate can be exposed by applying a polymeric layer over the substrate selectively removing a portion of the polymeric layer. The nanoparticles can be prepared in a predetermined pattern. The nanoparticle can be formed with a barrier separating it from another nanoparticle on the substrate; for example, nanoparticle can be located in a pit etched in the substrate. The size and location of the nanoparticle can be stable at elevated temperatures.02-03-2011
20110108799NANOPARTICLES - Method for producing a nanoparticle comprised of core, first shell and second shell semiconductor materials. Effecting conversion of a core precursor composition comprising separate first and second precursor species to the core material and then depositing said first and second shells. The conversion is effected in the presence of a molecular cluster compound under conditions permitting seeding and growth of the nanoparticle core. Core/multishell nanoparticles in which at least two of the core, first shell and second shell materials incorporate ions from groups 12 and 15, 14 and 16, or 11, 13 and 16 of the periodic table. Core/multishell nanoparticles in which the second shell material incorporates at least two different group 12 ions and group 16 ions. Core/multishell nanoparticles in which at least one of the core, first and second semiconductor materials incorporates group 11, 13 and 16 ions and the other semiconductor material does not incorporate group 11, 13 and 16 ions.05-12-2011
20130153860METHOD OF FORMING HYBRID NANOSTRUCTURE ON GRAPHENE, HYBRID NANOSTRUCTURE, AND DEVICE INCLUDING THE HYBRID NANOSTRUCTURE - A method of forming a hybrid nanostructure on graphene, the method including providing a graphene layer on a substrate; forming a metal layer on the graphene layer; and chemically depositing a nanomaterial on the graphene layer on which the metal layer is formed to form the hybrid nanostructure.06-20-2013
20110121264COMPOSITE STRUCTURE OF GRAPHENE AND NANOSTRUCTURE AND METHOD OF MANUFACTURING THE SAME - A composite structure includes; graphene and at least one substantially one-dimensional nanostructure disposed on the graphene.05-26-2011
20100163841NANO-HETERO STRUCTURE AND METHOD OF FABRICATING THE SAME - A nano-hetero structure is provided. The nano-hetero structure includes at least one nano-semiconductor base and a plurality of metal nanoparticles attached on the surface of nano-semiconductor base.07-01-2010
20100012922METHODS OF FORMING STRUCTURES INCLUDING NANOTUBES AND STRUCTURES INCLUDING SAME - A semiconductor structure including nanotubes forming an electrical connection between electrodes is disclosed. The semiconductor structure may include an open volume defined by a lower surface of an electrically insulative material and sidewalls of at least a portion of each of a dielectric material and opposing electrodes. The nanotubes may extend between the opposing electrodes, forming a physical and electrical connection therebetween. The nanotubes may be encapsulated within the open volume in the semiconductor structure. A semiconductor structure including nanotubes forming an electrical connection between source and drain regions is also disclosed. The semiconductor structure may include at least one semiconducting carbon nanotube electrically connected to a source and a drain, a dielectric material disposed over the at least one semiconducting carbon nanotube and a gate dielectric overlying a portion of the dielectric material. Methods of forming the semiconductor structures are also disclosed.01-21-2010
20090321715HETERO-CRYSTALLINE STRUCTURE AND METHOD OF MAKING SAME - A hetero-crystalline device structure and a method of making the same include a first layer and a nanostructure integral to a crystallite in the first layer. The first layer is a non-single crystalline material. The nanostructure is a single crystalline material. The nanostructure is grown on the first layer integral to the crystallite using epitaxial growth.12-31-2009
20110084250NANOPARTICLE COMPLEX, METHOD OF MANUFACTURING THE SAME, AND DEVICE INCLUDING THE NANOPARTICLE COMPLEX - A nanoparticle complex, including a semiconductor nanocrystal; and a metal complex ligand on the surface of the semiconductor nanocrystal. The nanoparticle complex may further include a polymer shell contacting the metal complex ligand.04-14-2011
20100252811Nitride semiconductor device - In the nitride semiconductor device of the present invention, an active layer 10-07-2010
20100006820SILICA NANOWIRE COMPRISING SILICON NANODOTS AND METHOD OF PREPARING THE SAME - Provided are a silica nanowire that includes silicon nanodots and a method of preparing the same. The silica nanowire has excellent capacitance characteristics and improved light absorption ability, and thus can be effectively used in a variety of fields, such as various semiconductor devices including CTF memory, image sensors, photodetectors, light emitting diodes, laser diodes, and the like.01-14-2010
20090001350High hole mobility semiconductor device - One embodiment of the invention includes a high hole mobility p-channel GaAs01-01-2009
20110001126Nitride semiconductor chip, method of fabrication thereof, and semiconductor device - A nitride semiconductor chip is provided that offers enhanced luminous efficacy and an increased yield as a result of an improved EL emission pattern and improved surface morphology (flatness). This nitride semiconductor laser chip (nitride semiconductor chip) includes a GaN substrate having a principal growth plane and individual nitride semiconductor layers formed on the principal growth plane of the GaN substrate. The principal growth plane is a plane having an off angle in the a-axis direction relative to the m plane, and the individual nitride semiconductor layers include a lower clad layer of AlGaN. This lower clad layer is formed in contact with the principal growth plane of the GaN substrate.01-06-2011
20090127540Systems and Methods for Nanowire Growth - The present invention is directed to systems and methods for nanowire growth. In an embodiment, methods for nanowire growth and doping are provided, including methods for epitaxial vertically oriented nanowire growth including providing a substrate material having one or more nucleating particles deposited thereon in a reaction chamber, introducing an etchant gas into the reaction chamber at a first temperature which gas aids in cleaning the surface of the substrate material, contacting the nucleating particles with at least a first precursor gas to initiate nanowire growth, and heating the alloy droplet to a second temperature, whereby nanowires are grown at the site of the nucleating particles. The etchant gas may also be introduced into the reaction chamber during growth of the wires to provide nanowires with low taper.05-21-2009
20080203381Forming arsenide-based complementary logic on a single substrate - In one embodiment, the present invention includes a method for forming a logic device, including forming an n-type semiconductor device over a silicon (Si) substrate that includes an indium gallium arsenide (InGaAs)-based stack including a first buffer layer, a second buffer layer formed over the first buffer layer, a first device layer formed over the second buffer layer. Further, the method may include forming a p-type semiconductor device over the Si substrate from the InGaAs-based stack and forming an isolation between the n-type semiconductor device and the p-type semiconductor device. Other embodiments are described and claimed.08-28-2008
20100320443ER Doped III-Nitride Materials And Devices Synthesized by MOCVD - This disclosure relates to the synthesis of Er doped GaN epilayers by in-situ doping by metal-organic chemical vapor deposition (MOCVD). In an embodiment, both above and below bandgap excitation results in a sharp PL emission peak at 1.54 μm. Contrary with other growth methods, MOCVD grown Er-doped GaN epilayers exhibit virtually no visible emission lines, an present a small thermal quenching effect. The Er incorporation has very little effect on the electrical conductivity of the GaN epilayers and Er doped layers retain similar electrical properties as those of undoped GaN.12-23-2010
20110133160NANOWIRE STRUCTURED PHOTODIODE WITH A SURROUNDING EPITAXIALLY GROWN P OR N LAYER - An embodiment relates to a device comprising a substrate, a nanowire and a doped epitaxial layer surrounding the nanowire, wherein the nanowire is configured to be both a channel to transmit wavelengths up to a selective wavelength and an active element to detect the wavelengths up to the selective wavelength transmitted through the nanowire. Another embodiment relates to a device comprising a substrate, a nanowire and one or more photogates surrounding the nanowire, wherein the nanowire is configured to be both a channel to transmit wavelengths up to a selective wavelength and an active element to detect the wavelengths up to the selective wavelength transmitted through the nanowire, and wherein the one or more photogates comprise an epitaxial layer.06-09-2011
20110073839II-VI SEMICONDUCTOR NANOWIRES - A high quality II-VI semiconductor nanowire is disclosed. A plurality of II-VI semiconductor nanowires is provided, with each being fixed to a support. Each nanowire terminates in a free end and a metal alloy nanoparticle is fixed to each nanowire at its free end.03-31-2011
20100176374NITRIDE SEMICONDUCTOR DEVICE - A nitride semiconductor device according to an aspect of the invention may include: first and second conductive nitride semiconductor layers; and an active layer having a DH structure located between the first and second conductive nitride semiconductor layers, and including a single quantum well structure active layer having the single quantum well structure includes at least one polarization relaxation layer formed of a nitride single crystal having a higher energy band gap than the quantum well.07-15-2010
20100264402USE OF SACK GEOMETRY TO IMPLEMENT A SINGLE QUBIT PHASE GATE - An implementation of a single qubit phase gate for use in a quantum information processing scheme based on the υ=5/2 fractional quantum Hall (FQH) state is disclosed. Using sack geometry, a qubit consisting of two σ-quasiparticles. which may be isolated on respective antidots, may be separated by a constriction from the bulk of a two-dimensional electron gas in the υ=5/2 FQH state. An edge quasiparticle may induce a phase gate on the qubit. The number of quasiparticles that are allowed to traverse the edge path defines which gate is induced. For example, if a certain number of quasiparticles are allowed to traverse the path, then a π/8 gate may be effected.10-21-2010
20110186815NITRIDE SEMICONDUCTOR DEVICE - There is provided a nitride semiconductor device including: an n-type nitride semiconductor layer; a p-type nitride semiconductor layer; and an active layer formed between the n-type and p-type nitride semiconductor layers, the active layer including a plurality of quantum well layers and at least one quantum barrier layer deposited alternately with each other, wherein the active layer includes a first quantum well layer, a second quantum well layer formed adjacent to the first quantum well layer toward the p-type nitride semiconductor layer and having a quantum level higher than a quantum level of the first quantum well layer, and a tunneling quantum barrier layer formed between the first and second quantum well layers and having a thickness enabling a carrier to be tunneled therethrough.08-04-2011
20110215297Formation of Nanowhiskers on a Substrate of Dissimilar Material - A method for forming a nanowhisker of, e.g., a III-V semiconductor material on a silicon substrate, comprises: preparing a surface of the silicon substrate with measures including passivating the substrate surface by HF etching, so that the substrate surface is essentially atomically flat. Catalytic particles on the substrate surface are deposited from an aerosol; the substrate is annealed; and gases for a MOVPE process are introduced into the atmosphere surrounding the substrate, so that nanowhiskers are grown by the VLS mechanism. In the grown nanowhisker, the crystal directions of the substrate are transferred to the epitaxial crystal planes at the base of the nanowhisker and adjacent the substrate surface. A segment of an optically active material may be formed within the nanowhisker and bounded by heterojunctions so as to create a quantum well wherein the height of the quantum well is much greater than the thermal energy at room temperature, whereby the luminescence properties of the segment remain constant without quenching from cryogenic temperatures up to room temperature.09-08-2011
20090173931Methods of Making, Positioning and Orienting Nanostructures, Nanostructure Arrays and Nanostructure Devices - Nanostructure manufacturing methods and methods for assembling nanostructures into functional elements such as junctions, arrays and devices are provided. Systems for practicing the methods are also provided. In one embodiment, a substrate is disclosed which comprises a first substrate region and a nanowire element attached to the first substrate region at a first position, the nanowire element comprising a first semiconductive region and a second region disposed between the first semiconductive region and the first position, wherein the second region comprises a material that is etchable under conditions that do not substantially etch the first semiconductive region.07-09-2009
20110315958HIGH OPERATING TEMPERATURE SPLIT-OFF BAND INFRARED DETECTOR WITH DOUBLE AND/OR GRADED BARRIER - A high operating temperature split-off band infrared (SPIP) detector having a double and/or graded barrier on either side of the emitter is provided. The photodetector may include a first and second barrier and an emitter disposed between the first and second barriers so as to form a heterojunction at each interface between the emitter and the first and second barriers, respectively. The emitter may be of a first semiconductor material having a split-off response to optical signals, while one of the first or the second barriers may include a double barrier having a light-hole energy band level that is aligned with the split-off band energy level of the emitter. In addition, the remaining barrier may be graded.12-29-2011
20120061647INFRARED LIGHT DETECTOR - Provided is an infrared light detector 03-15-2012
20110156003Systems and Methods for Nanowire Growth - The present invention is directed to systems and methods for nanowire growth. In an embodiment, methods for nanowire growth and doping are provided, including methods for epitaxial vertically oriented nanowire growth including providing a substrate material having one or more nucleating particles deposited thereon in a reaction chamber, introducing an etchant gas into the reaction chamber at a first temperature which gas aids in cleaning the surface of the substrate material, contacting the nucleating particles with at least a first precursor gas to initiate nanowire growth, and heating the alloy droplet to a second temperature, whereby nanowires are grown at the site of the nucleating particles. The etchant gas may also be introduced into the reaction chamber during growth of the wires to provide nanowires with low taper.06-30-2011
20120056159CONTROLLED QUANTUM DOT GROWTH - The present disclosure generally relates to techniques for controlled quantum dot growth as well as a quantum dot structures. In some examples, a method is described that includes one or more of providing a substrate, forming a defect on the substrate, depositing a layer on the substrate and forming quantum dots along the defect.03-08-2012
20120007046CARBON NANOTUBE HYBRID PHOTOVOLTAICS - Systems, methods and devices for the efficient photocurrent generation in single- or multi-walled carbon nanotubes, which includes (SWNTs)/poly [3-hexylthiophene-2,5-diyl] (P3HT) hybrid photovoltaics, and exhibit the following features: photocurrent measurement at individual SWNT/P3HT heterojunctions indicate that both semiconducting (s-) and metallic (m-) SWNTs function as excellent hole acceptors; electrical transport and gate voltage dependent photocurrent indicate that P3HT p-dopes both s-SWNT and m-SWNT, and exciton dissociation is driven by a built-in voltage at the heterojunction. Some embodiments include a mm01-12-2012
20120007045P-TYPE SEMICONDUCTOR DEVICE COMPRISING TYPE-2 QUANTUM WELL AND FABRICATION METHOD THEREOF - Disclosed herein are a method of generating a two-dimensional hole gas (2DHG) using a type-2 quantum well formed using semiconductors with different electron affinities or band gap, and a high-speed p-type semiconductor device using the 2DHG. To this end, the method includes providing a semiconductor substrate; growing a first semiconductor layer on the semiconductor substrate, growing a second semiconductor layer with a different electron affinity or band gap from the first semiconductor layer on the first semiconductor layer, and growing a third semiconductor layer with a different electron affinity or band gap from the second semiconductor layer, thereby forming a type-2 quantum well; and forming a p-type doping layer in the vicinity of the type-2 quantum well, thereby generating the 2DHG.01-12-2012
20120007047SEMICONDUCTOR LIGHT-EMITTING DEVICE - A semiconductor light-emitting device including a substrate, an n-type semiconductor layer formed on the substrate, an active layer laminated on the n-type semiconductor layer and capable of emitting a light, a p-type semiconductor layer laminated on the active layer, an n-electrode which is disposed on a lower surface of the semiconductor substrate or on the n-type semiconductor layer and spaced away from the active layer and p-type semiconductor layer, and a p-electrode which is disposed on the p-type semiconductor layer and includes a reflective ohmic metal layer formed on the dot-like metallic layer, wherein the light emitted from the active layer is extracted externally from the substrate side.01-12-2012
20120012816PHOTODETECTORS USING RESONANCE AND METHOD OF MAKING - An infrared photodetector comprising: a thin contact layer substantially transparent to infrared light; an absorption layer positioned such that light admitted through the substantially transparent thin contact area passes through the absorption layer; the absorption layer being configured to utilize resonance to increase absorption efficiency; at least one reflective side wall adjacent to the absorption layer being substantially non-parallel to the incident light operating to reflect light into the absorption layer for absorption of infrared radiation; and a top contact layer positioned adjacent to the active layer. A method of designing a photodetector comprising selecting a type of material based upon the wavelength range to be detected; determining a configuration geometry; calculating the electromagnetic field distributions using a computer simulated design of the configuration geometry, and determining a quantum efficiency spectrum at the desired wavelength or wavelength range; whereby the effectiveness of the photodetector is simulated prior to fabrication.01-19-2012
20100096618DOPING OF NANOSTRUCTURES - A catalyst particle for use in growth of elongated nanostructures, such as e.g. nanowires, is provided. The catalyst particle comprises a catalyst compound for catalyzing growth of an elongated nanostructure comprising a nanostructure material without substantially dissolving in the nanostructure material and at least one dopant element for doping the elongated nanostructure during growth by substantially completely dissolving in the nanostructure material. A method for forming an elongated nanostructure, e.g. nanowire, on a substrate using the catalyst particle is also provided. The method allows controlling dopant concentration in the elongated nanostructures, e.g. nanowires, and allows elongated nanostructures with a low dopant concentration of lower than 1004-22-2010
20120153260CHEMICALLY-ETCHED NANOSTRUCTURES AND RELATED DEVICES - A method of etching active quantum nanostructures provides the step of laterally etching of an intermediate active quantum nanostructure layer interposed between cladding layers. The lateral etching can be carried out on at least one side of the intermediate active quantum nanostructure layer selectively, with respect to the cladding layers to define at least one lateral recess or spacing in the intermediate active quantum nanostructure layer and respective lateral protrusions of cladding layers protruding with respect to the intermediate active quantum nanostructure layer. This method can be applied to create devices including active quantum nanostructures such as, for example, three-dimensional photonic crystals, a photonic crystal double-slab and a photonic crystal laser.06-21-2012
20100289003MAKING COLLOIDAL TERNARY NANOCRYSTALS - A method of making a colloidal solution of ternary semiconductor nanocrystals, includes providing binary semiconductor cores; forming first shells on the binary semiconductor cores containing one of the components of the binary semiconductor cores and another component which when combined with the binary semiconductor will form a ternary semiconductor, thereby providing core/shell nanocrystals; and annealing the core/shell nanocrystals to form ternary semiconductor nanocrystals containing a gradient in alloy composition.11-18-2010
20120313078SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - Disclosed is a semiconductor device (12-13-2012
20090057648High Hole Mobility P-Channel Ge Transistor Structure on Si Substrate - The present disclosure provides an apparatus and method for implementing a high hole mobility p-channel Germanium (“Ge”) transistor structure on a Silicon (“Si”) substrate. One exemplary apparatus may include a buffer layer including a GaAs nucleation layer, a first GaAs buffer layer, and a second GaAs buffer layer. The exemplary apparatus may further include a bottom barrier on the second GaAs buffer layer and having a band gap greater than 1.1 eV, a Ge active channel layer on the bottom barrier and having a valence band offset relative to the bottom barrier that is greater than 0.3 eV, and an AlAs top barrier on the Ge active channel layer wherein the AlAs top barrier has a band gap greater than 1.1 eV. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.03-05-2009
20100051905MOISTURE DETECTOR, BIOLOGICAL BODY MOISTURE DETECTOR, NATURAL PRODUCT MOISTURE DETECTOR, AND PRODUCT/MATERIAL MOISTURE DETECTOR - A moisture detector includes a light-receiving element including an absorption layer having a pn-junction, or an array of the light-receiving elements, wherein the absorption layer has a multiquantum well structure composed of a Group III-V semiconductor, the pn-junction is formed by selectively diffusing an impurity element into the absorption layer, and the concentration of the impurity in the absorption layer is 5×1003-04-2010
20100051903METHOD OF ALIGNING NANORODS AND RELATED COMPOSITIONS - A method of forming an array of nanorods on a crystalline substrate includes heating a composition that includes the crystalline substrate, a nanorod precursor, and a surfactant. The surfactant is capable of associating with the surface of the nanorods. The resulting nanostructures formed from the methods may be used in a variety of devices, including dye-sensitizing solar cell devices.03-04-2010
20100270534ELECTRONIC DEVICE USING QUANTUM DOT - An electronic device using quantum dots, which comprises a ferromagnetic micro magnet and performs individual ESR control on each multi-quantum bit in a power saving way.10-28-2010
20100270533ZnO-BASED SEMICONDUCTOR ELEMENT - Provided is a ZnO-based semiconductor device capable of achieving easier conversion into p-type by alleviating the self-compensation effect and by preventing donor impurities from mixing in. The ZnO-based semiconductor device includes a Mg10-28-2010
20120256165SINGLE-QUANTUM DOT DEVICE AND METHOD OF MANUFACTURING THE SAME - The present disclosure provides a single-quantum dot device and a method of manufacturing the same. A transparent dielectric thin film is formed on a cover layer and an energy band of quantum dots is adjusted based on compressive stress due to difference in coefficient of thermal expansion therebetween. Specifically, the dielectric thin film has a lower coefficient of thermal expansion than the cover layer and compressive stress is applied to the cover layer by radiation of laser beams. Then, the quantum dots undergo compressive stress and the energy band of the quantum dots increases with increasing intensity of the laser beams.10-11-2012
20110121265GROUP III NITRIDE SEMICONDUCTOR OPTICAL DEVICE - A group III nitride semiconductor optical device 05-26-2011
20110121263Coupled Asymmetric Quantum Confinement Structures - Implementations and techniques for coupled asymmetric quantum confinement structures are generally disclosed.05-26-2011
20110017977MEMRISTORS WITH INSULATION ELEMENTS AND METHODS FOR FABRICATING THE SAME - Embodiments of the present invention are directed to nanoscale memristor devices that provide nonvolatile memristive switching. In one embodiment, a memristor device comprises an active region disposed between a first electrode and a second electrode. The device includes a first insulation element disposed between the first electrode and an outer portion of a first surface of the active region. The first insulation element is configured with one or more opening through which the first electrode makes physical contact with the active region. The device also includes a second insulation element disposed between the second electrode and an outer portion of a second surface of the active region. The second insulation element is configured with one or more opening through which the second electrode makes physical contact with the second surface.01-27-2011
20110042646Nitride semiconductor wafer, nitride semiconductor chip, method of manufacture thereof, and semiconductor device - A nitride semiconductor chip allows enhancement of luminous efficacy. The nitride semiconductor laser chip (nitride semiconductor chip) has a GaN substrate, which has a principal growth plane, and an active layer, which is formed on the principal growth plane of the GaN substrate and which has a quantum well structure including a well layer and a barrier layer. The principal growth plane is a plane having an off angle in the a-axis direction relative to the m plane. The barrier layer is formed of AlGaN, which is a nitride semiconductor containing Al.02-24-2011
20110227041Electronic Devices and Thermal Image Sensors that Utilize Embedded Quantum Dots - Integrated circuit devices include thermal image sensors that utilize quantum dots therein to provide negative resistance characteristics to at least portions of the sensors. The thermal image sensor may include a sensing unit configured to absorb radiation incident on a first surface thereof and first and second electrodes electrically coupled to the sensing unit. The sensing unit includes a plurality of quantum dots therein, which may extend between the first and second electrodes. These quantum dots may be configured to impart a negative resistance characteristic to the sensing unit. In particular, the sensing unit may include a sensing layer having first and second opposing ends, which are electrically coupled to the first and second electrodes, respectively, and the plurality of quantum dots may be distributed within the sensing layer.09-22-2011
20100230658Apparatus and methods for improving parallel conduction in a quantum well device - Embodiments of an apparatus and methods of providing a quantum well device for improved parallel conduction are generally described herein. Other embodiments may be described and claimed.09-16-2010
20120326122EPITAXIAL WAFER, PHOTODIODE, OPTICAL SENSOR DEVICE, AND METHODS FOR PRODUCING EPITAXIAL WAFER AND PHOTODIODE - Provided are an epitaxial wafer, a photodiode, and the like that include an antimony-containing layer and can be efficiently produced such that protruding surface defects causing a decrease in the yield can be reduced and impurity contamination causing degradation of the performance can be suppressed.12-27-2012
20120286241SUPPRESSION OF INCLINED DEFECT FORMATION AND INCREASE IN CRITICAL THICKNESS BY SILICON DOPING ON NON-C-PLANE (Al,Ga,In)N - A method for fabricating a III-nitride based semiconductor device, including (a) growing one or more buffer layers on or above a semi-polar or non-polar GaN substrate, wherein the buffer layers are semi-polar or non-polar III-nitride buffer layers; and (b) doping the buffer layers so that a number of crystal defects in III-nitride device layers formed on or above the doped buffer layers is not higher than a number of crystal defects in III-nitride device layers formed on or above one or more undoped buffer layers. The doping can reduce or prevent formation of misfit dislocation lines and additional threading dislocations. The thickness and/or composition of the buffer layers can be such that the buffer layers have a thickness near or greater than their critical thickness for relaxation. In addition, one or more (AlInGaN) or III-nitride device layers can be formed on or above the buffer layers.11-15-2012
20080237573Mechanism for forming a remote delta doping layer of a quantum well structure - A method of fabricating a quantum well device includes forming a diffusion barrier on sides of a delta layer of a quantum well to confine dopants to the quantum well.10-02-2008
20080237572FORMING A TYPE I HETEROSTRUCTURE IN A GROUP IV SEMICONDUCTOR - In one embodiment, the present invention includes a method for forming a transistor that includes forming a first buffer layer of silicon germanium tin (SiGe(Sn)) on a silicon (Si) substrate, forming a barrier layer on the first buffer layer, the barrier layer comprising silicon germanium (Si10-02-2008
20130140523Quantum Well Device With Lateral Electrodes - An apparatus includes a substrate, a sequence of crystalline semiconductor layers on a planar surface of the substrate, and first and second sets of electrodes over the sequence. The sequence has a 2D quantum well therein. The first set of electrodes border opposite sides of a lateral region of the sequence and are controllable to vary a width of a non-depleted portion of the quantum well along the top surface. The second set of electrodes border channels between the lateral region and first and second adjacent lateral areas of the sequence and are controllable to vary widths of non-depleted segments of the quantum well in the channels. The electrodes are such that straight lines connecting the lateral areas via the channels either pass between one of the electrodes and the substrate or are misaligned to an effective [1 06-06-2013
20080224122Semiconductor Nanowire and Semiconductor Device Including the Nanowire - A nanowire (09-18-2008
20130099202SUPPRESSION OF RELAXATION BY LIMITED AREA EPITAXY ON NON-C-PLANE (In,Al,B,Ga)N - An (AlInGaN) based semiconductor device, including one or more (In,Al)GaN layers overlying a semi-polar or non-polar III-nitride substrate or buffer layer, wherein the substrate or buffer employs patterning to influence or control extended defect morphology in layers deposited on the substrate; and one or more (AlInGaN) device layers above and/or below the (In,Al)GaN layers.04-25-2013
20130140524Nanoparticle Synthesis - A noble metal nanoparticle can be grown on a semiconductor substrate by contacting a predetermined region of the substrate with a solution including noble metal ions. The predetermined region of the semiconductor substrate can be exposed by applying a polymeric layer over the substrate selectively removing a portion of the polymeric layer. The nanoparticles can be prepared in a predetermined pattern. The nanoparticle can be formed with a barrier separating it from another nanoparticle on the substrate; for example, nanoparticle can be located in a pit etched in the substrate. The size and location of the nanoparticle can be stable at elevated temperatures.06-06-2013
20080210927Buffer architecture formed on a semiconductor wafer - In one embodiment, the present invention includes an apparatus for forming a transistor that includes a silicon (Si) substrate, a dislocation filtering buffer formed over the Si substrate having a first buffer layer including gallium arsenide (GaAs) nucleation and buffer layers and a second buffer layer including a graded indium aluminium arsenide (InAlAs) buffer layer, a lower barrier layer formed on the second buffer layer formed of InAlAs, and a strained quantum well (QW) layer formed on the lower barrier layer of indium gallium arsenide (InGaAs). Other embodiments are described and claimed.09-04-2008
20130146843Segmented Nanowires Displaying Locally Controllable Properties - Vapor-liquid-solid growth of nanowires is tailored to achieve complex one-dimensional material geometries using phase diagrams determined for nanoscale materials. Segmented one-dimensional nanowires having constant composition display locally variable electronic band structures that are determined by the diameter of the nanowires. The unique electrical and optical properties of the segmented nanowires are exploited to form electronic and optoelectronic devices. Using gold-germanium as a model system, in situ transmission electron microscopy establishes, for nanometer-sized Au—Ge alloy drops at the tips of Ge nanowires (NWs), the parts of the phase diagram that determine their temperature-dependent equilibrium composition. The nanoscale phase diagram is then used to determine the exchange of material between the NW and the drop. The phase diagram for the nanoscale drop deviates significantly from that of the bulk alloy.06-13-2013
20100308302Quantum Well Device - An apparatus includes a primary planar quantum well and a planar distribution of dopant atoms. The primary planar quantum well is formed by a lower barrier layer, a central well layer on the lower barrier layer, and an upper barrier layer on the central well layer. Each of the layers is a semiconductor layer. One of the barrier layers has a secondary planar quantum well and is located between the planar distribution of dopant atoms and the central well layer. The primary planar quantum well may be undoped or substantially undoped, e.g., intrinsic semiconductor.12-09-2010
20100314608PHOTODETECTORS - Implementations of quantum well photodetectors are provided.12-16-2010
20110272671SEMICONDUCTOR DEVICE AND A METHOD OF FABRICATING A SEMICONDUCTOR DEVICE - A semiconductor device comprising a quantum dot and a plurality of layers, wherein said plurality of layers comprises: a first layer; a stressor layer; and a patterned layer wherein said stressor layer overlies said first layer and said patterned layer overlies said stressor layer; wherein said stressor layer has a substantially different lattice constant to said first layer and said patterned layer and has a pit provided in said layer; said quantum dot lying above said patterned layer aligned with said pit.11-10-2011
20120018703OPTOELECTRONIC SEMICONDUCTOR COMPONENT AND METHOD FOR THE MANUFACTURE THEREOF - Manufacturing semiconductor heterostructures by way of molecular beam epitaxy, including placing a substrate into a first vacuum chamber, heating the substrate to a first temperature, depositing from at least one molecular beam a first epitaxial layer of a first material containing a binary, ternary or quaternary compound of elements of main group III and V, cooling the substrate to a second temperature, interrupting the molecular beam by elements of main group III and V, heating the substrate to a third temperature and depositing from at least one molecular beam a second epitaxial layer of a second material containing a binary, ternary, or quaternary compound of elements of main group III and V and that is deposited from at least one molecular beam; and semiconductor components produced thereby.01-26-2012
20120018702SURFACE AND GAS PHASE DOPING OF III-V SEMICONDUCTORS - Compound semiconductor devices and methods of doping compound semiconductors are provided. Embodiments of the invention provide post-deposition (or post-growth) doping of compound semiconductors, enabling nanoscale compound semiconductor devices including diodes and transistors. In one method, a self-limiting monolayer technique with an annealing step is used to form shallow junctions. By forming a sulfur monolayer on a surface of an InAs substrate and performing a thermal annealing to drive the sulfur into the InAs substrate, n-type doping for InAs-based devices can be achieved. The monolayer can be formed by surface chemistry reactions or a gas phase deposition of the dopant. In another method, a gas-phase technique with surface diffusion is used to form doped regions. By performing gas-phase surface diffusion of Zn into InAs, p-type doping for InAs-based devices can be achieved. Both bulk and nanowire devices using compound semiconductors can be fabricated using these surface and gas-phase doping processes.01-26-2012
20120032145DETECTION DEVICE, LIGHT-RECEIVING ELEMENT ARRAY, SEMICONDUCTOR CHIP, METHOD FOR MANUFACTURING THE SAME, AND OPTICAL SENSOR APPARATUS - A detection device includes a light-receiving element array and a read-out integrated circuit (CMOS), bumps of the light-receiving element array being bonded to bumps of the read-out integrated circuit, and at least one of the light-receiving element array and the read-out integrated circuit having a concaved surface which faces the other. The bonded bumps positioned in a region near the periphery of the arrangement region of the bonded bumps have a larger diameter and a lower height than those of the bumps positioned in a central region. Therefore, it is possible to prevent bonding failure and insulation failure in the bumps from occurring due to a difference in coefficient of thermal expansion, while securing a small size and low cost.02-09-2012

Patent applications in class Quantum well

Patent applications in all subclasses Quantum well