Entries |
Document | Title | Date |
20080230764 | Composite Quantum Dot Structures - A composite quantum dot structure ( | 09-25-2008 |
20080315175 | ALIGNMENT, TRANSPORTATION AND INTEGRATION OF NANOWIRES USING OPTICAL TRAPPING - Individually trapping, transferring, and assembling high-aspect-ratio semiconductor nanowires into arbitrary structures in a fluid environment. Nanowires with diameters as small as 20 nm and aspect ratios of above 100 can be trapped and transported in three dimensions, enabling the construction of nanowire architectures which may function as active photonic devices. Moreover, nanowire structures can now be assembled in physiological environments. In one aspect, nanowires are positioned to direct light to remote samples, reducing exposure of the overall sample to intense source illumination. A tunable nanowire probe for subwavelength imaging is also described utilizing efficient second harmonic generation (SHG) whose optical frequency conversion allows implementing subwavelength microscopes. | 12-25-2008 |
20090085026 | STRUCTURE AND METHOD FOR MANIPULATING SPIN QUANTUM STATE THROUGH DIPOLE POLARIZATION SWITCHING - Disclosed herein is a structure and method for manipulating a spin state, regarded as important in the field of spintronics, by which the distribution of spin-up and spin-down states of carriers in a hybrid double quantum disk structure, composed of a diluted magnetic semiconductor and a ferroelectric compound semiconductor, is manipulated through dipole polarization switching of the ferroelectric compound semiconductor without a change in bias. Giant Zeeman splitting properties of the diluted magnetic semiconductor and polarization properties of the ferroelectric compound semiconductor are applied in conjunction with the Pauli exclusion principle, thus enabling the combination or separation of carriers in spin-up and spin-down states in the hybrid double quantum disk structure. The spin relaxation time in the structure is on the order of microseconds, during which the spin state is well-defined, and therefore, the structure can be applied to microprocessors having gigahertz clock speeds. | 04-02-2009 |
20090189143 | Nanotube array electronic and opto-electronic devices - Carbon nanotube (CNT)-based devices and technology for their fabrication are disclosed. The discussed electronic and photonic devices and circuits rely on the nanotube arrays grown on a variety of substrates, such as glass or Si wafer. The planar, multiple layer deposition technique and simple methods of change of the nanotube conductivity type during the device processing are utilized to provide a simple and cost effective technology for a large scale circuit integration. Such devices as p-n diode, CMOS-like circuit, bipolar transistor, light emitting diode and laser are disclosed, all of them are expected to have superior performance then their semiconductor-based counterparts due to excellent CNT electrical and optical properties. When fabricated on Si-wafers, the CNT-based devices can be combined with the Si circuit elements, thus producing hybrid Si-CNT devices and circuits. | 07-30-2009 |
20090189144 | Device For Absorbing Or Emitting Light And Methods Of Making The Same - A device disclosed herein includes a first layer, a second layer, and a first plurality of nanowires established between the first layer and the second layer. The first plurality of nanowires is formed of a first semiconductor material. The device further includes a third layer, and a second plurality of nanowires established between the second and third layers. The second plurality of nanowires is formed of a second semiconductor material having a bandgap that is the same as or different from a bandgap of the first semiconductor material. | 07-30-2009 |
20090302306 | Nano Electronic Device and Fabricating Method of The Same - Disclosed herein are a nano electronic device and a method of fabricating the same. The nano electronic device includes a ferroelectric nano-structure and a semiconducting nano-wire. Polarization formed on the ferroelectric nano-structure is utilized. | 12-10-2009 |
20110193055 | NANOWHISKERS WITH PN JUNCTIONS, DOPED NANOWHISKERS, AND METHODS FOR PREPARING THEM - Nano-engineered structures are disclosed, incorporating nanowhiskers of high mobility conductivity and incorporating pn junctions. In one embodiment, a nanowhisker of a first semiconducting material has a first band gap, and an enclosure comprising at least one second material with a second band gap encloses said nanoelement along at least part of its length, the second material being doped to provide opposite conductivity type charge carriers in respective first and second regions along the length of the of the nanowhisker, whereby to create in the nanowhisker by transfer of charge carriers into the nanowhisker, corresponding first and second regions of opposite conductivity type charge carriers with a region depleted of free carriers therebetween. The doping of the enclosure material may be degenerate so as to create within the nanowhisker adjacent segments having very heavy modulation doping of opposite conductivity type analogous to the heavily doped regions of an Esaki diode. In another embodiment, a nanowhisker is surrounded by polymer material containing dopant material. A step of rapid thermal annealing causes the dopant material to diffuse into the nanowhisker. In a further embodiment, a nanowhisker has a heterojunction between two different intrinsic materials, and Fermi level pinning creates a pn junction at the interface without doping. | 08-11-2011 |
20110220865 | TRANSISTOR AND MANUFACTURING METHOD THEREOF - According to an embodiment of the present invention, a transistor includes a source electrode, a drain electrode, a graphene film formed between the source electrode and the drain electrode and having a first region and a second region, and a gate electrode formed on the first region and the second region of the graphene film via a gate insulating film. The graphene film functions as a channel. A Schottky junction is formed at a junction between the first region and the second region. The first region has a conductor property, and the second region is adjacent to the drain electrode side of the first region and has a semiconductor property. | 09-15-2011 |
20110272665 | Nitride semiconductor device - An inventive nitride semiconductor device includes: a substrate; a first buffer layer provided on the substrate, and having a superlattice structure which includes two types of Group III nitride semiconductor sublayers having different compositions and alternately stacked in pairs; a second buffer layer provided on the first buffer layer in contact with the first buffer layer, and having a superlattice structure which includes two types of Group III nitride semiconductor sublayers having different compositions and alternately stacked in pairs; and a device operation layer of a Group III nitride semiconductor provided on the second buffer layer; wherein an average lattice constant LC | 11-10-2011 |
20120097917 | Aligned, Coated Nanowire Arrays for Gas Sensing - Aligned nanowire arrays were coated with semiconductor shell layers, and optionally with noble metal nanoparticles for use as three dimensional gas sensors. The sensors show room-temperature responses to low concentrations of various gases. Arrays containing different sensor types can discriminate among different gases, based upon changes in conductivity and response times. | 04-26-2012 |
20120126200 | Nanowhiskers with PN Junctions, Doped Nanowhiskers, and Methods for Preparing Them - Nano-engineered structures are disclosed, incorporating nanowhiskers of high mobility conductivity and incorporating pn junctions. In one embodiment, a nanowhisker of a first semiconducting material has a first band gap, and an enclosure comprising at least one second material with a second band gap encloses said nanoelement along at least part of its length, the second material being doped to provide opposite conductivity type charge carriers in respective first and second regions along the length of the of the nanowhisker, whereby to create in the nanowhisker by transfer of charge carriers into the nanowhisker, corresponding first and second regions of opposite conductivity type charge carriers with a region depleted of free carriers therebetween. | 05-24-2012 |
20120175584 | STRUCTURES FOR RADIATION DETECTION AND ENERGY CONVERSION USING QUANTUM DOTS - Inorganic semiconducting materials such as silicon are used as a host matrix in which quantum dots reside to provide a radiation detector or energy converter. The quantum dot material may be disposed by incorporating materials sensitive to neutron detection such as boron-containing compounds, or the use of methods such as chemical vapor deposition or atomic layer deposition to insert the quantum dot material. Electrodes may be extended deep into the host matrix material to improve efficiency. Likewise, the host matrix may be machined to create pores in the matrix material. Further, amplification and signal-processing structures may be used in close proximity to the radiation-sensitive region of the device. | 07-12-2012 |
20120175585 | CAGE NANOSTRUCTURES AND PREPARTION THEREOF - A unique family of nanoparticles characterized by their nanometric size and cage-like shapes (hollow structures), capable of holding in their hollow cavity a variety of materials is disclosed herein. | 07-12-2012 |
20120241717 | Organic Photosensitive Optoelectronic Devices - A photosensitive optoelectronic device ( | 09-27-2012 |
20120248403 | LAYER ASSEMBLY - The invention inter alia relates to a method of fabricating a layer assembly comprising the steps of: arranging a first layer on top of a carrier; arranging a second layer on top of the first layer; locally modifying the material of the buried first layer and providing at least one modified section in the first layer, wherein the modified material changes or induces mechanical strain in a portion of the second layer which is arranged above the at least one modified section; after locally modifying the material of the buried first layer, depositing a third material on top of the second layer, at least one characteristic of the third material being sensitive to the local mechanical strain in the second layer. | 10-04-2012 |
20120256160 | Piezo-phototronic Effect Devices - A semiconducting device includes a piezoelectric structure that has a first end and an opposite second end. A first conductor is in electrical communication with the first end and a second conductor is in electrical communication with the second end so as to form an interface therebetween. A force applying structure is configured to maintain an amount of strain in the piezoelectric member sufficient to generate a desired electrical characteristic in the semiconducting device. | 10-11-2012 |
20120267605 | Methods for the Production of Nanoscale Heterostructures - The present invention is directed to a novel synthetic method for producing nanoscale heterostructures, and particularly nanoscale heterostructure particles, rods and sheets, that comprise a metal core and a monocrystalline semiconductor shell with substantial lattice mismatches between them. More specifically, the invention concerns the use of controlled soft acid-base coordination reactions between molecular complexes and colloidal nanostructures to drive the nanoscale monocrystalline growth of the semiconductor shell with a lattice structure incommensurate with that of the core. The invention also relates to more complex hybrid core-shell structures that exhibit azimuthal and radial nano-tailoring of structures. The invention is additionally directed to the use of such compositions in semiconductor devices. | 10-25-2012 |
20130140518 | QUANTUM DOT GATE FETS AND CIRCUITS CONFIGURED AS BIOSENSORS AND GENE SEQUENCERS - Quantum dot (QD) gate FETs and the use of quantum dot (QD) gate FETs for the purpose of sensing analytes and proteins is disclosed and described. Analytes, proteins, miRNAs, and DNAs functionalized to the QDs change the charge density in the gate and hence the current-voltage characteristics. In one embodiment, QD-FETs, such as | 06-06-2013 |
20130181185 | TUNNELING FIELD EFFECT TRANSISTOR AND METHOD FOR FABRICATING THE SAME - A tunneling field effect transistor and a method for fabricating the same are provided. The tunneling field effect transistor comprises: a semiconductor substrate and a drain layer formed in the semiconductor substrate, in which the drain layer is first type heavily doped; an epitaxial layer formed on the drain layer, with an isolation region formed in the epitaxial layer; a buried layer formed in the epitaxial layer, in which the buried layer is second type lightly doped; a source formed in the buried layer, in which the source is second type heavily doped; a gate dielectric layer formed on the epitaxial layer, and a gate formed on the gate dielectric layer; and a source metal contact layer formed on the source, and a drain metal contact layer formed under the drain layer. | 07-18-2013 |
20130256628 | EPITAXIAL STRUCTURE - An epitaxial structure is provided. The epitaxial structure comprises a substrate, a carbon nanotube layer and an epitaxial layer stacked in that order. The substrate has an epitaxial growth surface and defines a plurality of first grooves and first bulges on the epitaxial growth surface. The carbon nanotube layer covers the epitaxial growth surface, wherein a first part of the carbon nanotube layer is attached on top surface of the first bulges, and a second part of the carbon nanotube layer is attached on bottom surface and side surface of the first grooves. The epitaxial layer is formed on the epitaxial growth surface, and the carbon nanotube layer is sandwiched between the epitaxial layer and the substrate. | 10-03-2013 |
20130306934 | BIOSENSOR COMPRISING REDUCED GRAPHENE OXIDE LAYER - The present invention relates to a horizontal biosensor, comprising a reduced graphene oxide layer formed on a substrate; a molecular linker formed on the reduced graphene oxide layer; and a metal nanoparticle layer formed on the molecular linker. | 11-21-2013 |
20140048765 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - The present invention discloses a semiconductor device, comprising: a substrate, a gate stack structure on the substrate, source and drain regions in the substrate on both sides of the gate stack structure, and a channel region between the source and drain regions in the substrate, characterized in that the source region in the source and drain regions comprises GeSn alloy, and a tunnel dielectric layer is optionally comprised between the GeSn alloy of the source region and the channel region. In accordance with the semiconductor device and method for manufacturing the same of the present invention, GeSn alloy having a narrow band gap is formed by implanting precursors and performing a laser rapid annealing, the on-state current of TFET is effectively enhanced, accordingly it has an important application prospect in a high performance low power consumption application. | 02-20-2014 |
20140077151 | Optoelectric device with semiconductor microwires or nanowires and method for manufacturing the same - An optoelectric device including microwires or nanowires on a support, each microwire or nanowire including at least one portion mainly containing a III-V compound in contact with the support, wherein the III-V compound is based on a first group-V element and on a second group-III element, wherein a surface of the support includes first areas of a first material promoting the growth of the III-V compound according to the polarity of the first element distributed in a second area of a second material promoting the growth of the compound according to the polarity of the second element, the microwires or nanowires being located on the first areas. | 03-20-2014 |
20140084239 | NON-PLANAR SEMICONDUCTOR DEVICE HAVING CHANNEL REGION WITH LOW BAND-GAP CLADDING LAYER - Non-planar semiconductor devices having channel regions with low band-gap cladding layers are described. For example, a semiconductor device includes a vertical arrangement of a plurality of nanowires disposed above a substrate. Each nanowire includes an inner region having a first band gap and an outer cladding layer surrounding the inner region. The cladding layer has a second, lower band gap. A gate stack is disposed on and completely surrounds the channel region of each of the nanowires. The gate stack includes a gate dielectric layer disposed on and surrounding the cladding layer and a gate electrode disposed on the gate dielectric layer. Source and drain regions are disposed on either side of the channel regions of the nanowires. | 03-27-2014 |
20140110662 | GRAPHENE-BASED COMPOSITE STRUCTURE AND METHOD FOR MAKING THE SAME - A graphene-based composite structure is disclosed. The graphene-based composite structure includes a graphene layer, a transition metal layer, and a substrate. The graphene layer, transition metal layer, and substrate are stacked together in series to form a sandwich structure. The graphene layer and the transition metal layer are coupled by d-p orbitals hybridization. The transition metal layer and the substrate are also coupled by d-p orbitals hybridization. A method for making graphene-based composite structure is also disclosed. | 04-24-2014 |
20140158976 | III-N SEMICONDUCTOR-ON-SILICON STRUCTURES AND TECHNIQUES - III-N semiconductor-on-silicon integrated circuit structures and techniques are disclosed. In some cases, the structure includes a first semiconductor layer formed on a nucleation layer, the first semiconductor layer including a 3-D GaN layer on the nucleation layer and having a plurality of 3-D semiconductor structures, and a 2-D GaN layer on the 3-D GaN layer. The structure also may include a second semiconductor layer formed on or within the first semiconductor layer, wherein the second semiconductor layer includes AlGaN on the 2-D GaN layer and a GaN layer on the AlGaN layer. Another structure includes a first semiconductor layer formed on a nucleation layer, the first semiconductor layer comprising a 2-D GaN layer on the nucleation layer, and a second semiconductor layer formed on or within the first semiconductor layer, wherein the second semiconductor layer includes AlGaN on the 2-D GaN layer and a GaN layer on the AlGaN layer. | 06-12-2014 |
20140175376 | Reduced Scale Resonant Tunneling Field Effect Transistor - An embodiment includes a heterojunction tunneling field effect transistor including a source, a channel, and a drain; wherein (a) the channel includes a major axis, corresponding to channel length, and a minor axis that corresponds to channel width and is orthogonal to the major axis; (b) the channel length is less than 10 nm long; (c) the source is doped with a first polarity and has a first conduction band; (d) the drain is doped with a second polarity, which is opposite the first polarity, and the drain has a second conduction band with higher energy than the first conduction band. Other embodiments are described herein. | 06-26-2014 |
20140332753 | NANO FIELD-EFFECT VACUUM TUBE AND FABRICATION METHOD THEREOF - A method is provided for fabricating a nano field-effect vacuum tube. The method includes providing a substrate having an insulating layer and a sacrificial layer; and forming a sacrificial line, a source sacrificial layer and a drain sacrificial layer. The method also includes forming a trench in the insulating layer; and forming a dielectric layer on the surface of the sacrificial line. Further, the method includes forming a metal layer on the dielectric layer to fill up the trench, cover the sacrificial line and expose the source sacrificial layer and the drain sacrificial layer; and removing the source sacrificial layer and the drain sacrificial layer. Further, the method also includes removing the sacrificial line to form a through channel; forming an isolation layer on the metal layer; and forming a source region and a drain region on the insulating layer at both ends of the metal layer. | 11-13-2014 |
20150108423 | APPARATUS, METHOD AND COMPUTER PROGRAM PRODUCT PROVIDING RADIAL ADDRESSING OF NANOWIRES - Disclosed is a method to construct a device that includes a plurality of nanowires (NWs) each having a core and at least one shell. The method includes providing a plurality of radially encoded NWs where each shell contains one of a plurality of different shell materials; and differentiating individual ones of the NWs from one another by selectively removing or not removing shell material within areas to be electrically coupled to individual ones of a plurality of mesowires (MWs). Also disclosed is a nanowire array that contains radially encoded NWs, and a computer program product useful in forming a nanowire array. | 04-23-2015 |
20150123073 | High Temperature Sensor Selective for Propane and Other Reducing Gases - Exemplary embodiments of the present disclosure relate to sensor technology for gases, and more specifically, to nanofiber based gas sensors capable of operating at high temperatures (e.g., hundreds, thousands of degrees Celsius). In exemplary embodiments, a combination of p-type and n-type nanofiber materials can be combined to create gas sensors that can be used to detect reducing gases with enhanced selectivity/sensitivity. | 05-07-2015 |
20150300980 | SENSOR INCLUDING CORE-SHELL NANOSTRUCTURE, AND METHOD FOR PRODUCING SAME - The present invention relates to a sensor including a core-shell nanostructure, and more particularly, to a sensor including: a base material; a sensing part including a core-shell nanostructure that has a core including a first metal oxide and a shell including a second metal oxide formed on the core; and two electrode layers spaced from each other on the sensing part. | 10-22-2015 |
20150311460 | CARBON NANOTUBE COMPOSITE LAYER - A carbon nanotube composite layer includes a number of semiconductor particles and a number of carbon nanotubes. The number of semiconductor particles are dispersed into the number of carbon nanotubes, the number of carbon nanotubes and the number of semiconductor particles are electrically connected with each other, each of the number of semiconductor particles includes a semiconductor fragment, the semiconductor fragment includes a number of semiconductor molecular layers stacked together, a number of the number of semiconductor molecular layers ranges from about 1 to about 20, an area of the semiconductor fragment ranges from about 0.1 square micrometers to about 5 square micrometers, and a thickness of the semiconductor fragment range from about 2 nanometers to about 20 nanometers. | 10-29-2015 |
20150333282 | METHODS AND DEVICES FOR SILICON INTEGRATED VERTICALLY ALIGNED FIELD EFFECT TRANSISTORS - Embodiments of the present disclosure provide for vertically aligned CNTFET, methods of making vertically aligned CNTFET, methods of using vertically aligned CNTFET, and the like. | 11-19-2015 |
20150364582 | SEMICONDUCTOR DEVICE - A semiconductor device includes a gate dielectric film on a semiconductor layer. A gate electrode is above the semiconductor layer via the gate dielectric film. A first conductivity-type drain is in the semiconductor layer on one end side of the gate electrode. A second conductivity-type source is in the semiconductor layer on the other end side of the gate electrode and below the gate electrode. A channel is between the gate dielectric film and the source. A drain side end of the source is below a bottom surface of the gate electrode. A region of the drain side end of a surface region of the source is formed using a first material. A region of the surface region of the source other than the drain side end is formed using a second material. An energy band gap of the first material is larger than that of the second material. | 12-17-2015 |
20150364583 | ALL-ELECTRIC SPIN FIELD EFFECT TRANSISTOR - An all-electric spin field effect transistor is disclosed, which includes an injection node, injecting an electron in a first spin direction; a detection node, detecting the electron in the first spin direction; and a gate, disposed between the injection node and the detection node such that the electron changes from the first spin direction to a second spin direction by carrying out precession; if the second spin direction is parallel to the first spin direction, the electron is able to pass through the detection node; if the second spin direction is antiparallel to the first spin direction, the electron is unable to pass through the detection node. | 12-17-2015 |
20150372141 | SILICON-CONTAINING, TUNNELING FIELD-EFFECT TRANSISTOR INCLUDING III-N SOURCE - Tunneling field-effect transistors including silicon, germanium or silicon germanium channels and III-N source regions are provided for low power operations. A broken-band heterojunction is formed by the source and channel regions of the transistors. Fabrication methods include selective anisotropic wet-etching of a silicon substrate followed by epitaxial deposition of III-N material and/or germanium implantation of the substrate followed by the epitaxial deposition of the III-N material. | 12-24-2015 |
20160005895 | INTERBAND CASCADE DEVICES - Photovoltaic (PV) and photodetector (PD) devices, comprising a plurality of interband cascade (IC) stages, wherein the IC stages comprise an absorption region with a type-I superlattice and/or a bulk semiconductor material having a band gap, the absorption region configured to absorb photons, an intraband transport region configured to act as a hole barrier, and an interband tunneling region configured to act as an electron barrier, wherein the absorption region, the intraband transport region, and the interband tunneling region are positioned such that electrons will flow from the absorption region to the intraband transport region to the interband tunneling region. | 01-07-2016 |
20160056278 | TUNNELING FIELD EFFECT TRANSISTORS (TFETS) WITH UNDOPED DRAIN UNDERLAP WRAP-AROUND REGIONS - Tunneling field effect transistors (TFETs) with undoped drain underlap wrap-around regions are described. For example, a tunneling field effect transistor (TFET) includes a homojunction active region formed above a substrate. The homojunction active region includes a doped source region, an undoped channel region, a wrapped-around region, and a doped drain region. A gate electrode and gate dielectric layer are formed on the undoped channel region, between the source and wrapped-around regions. | 02-25-2016 |
20160064535 | HETEROSECTION TUNNEL FIELD-EFFECT TRANSISTOR (TFET) - A Tunnel Field-Effect Transistor (TFET) device is provided comprising at least one heterosection between the source region and the channel region. The at least one heterosection has a low dielectric constant and thickness below 10 nm. Additionally a pocket region and another heterosection may be added in between the at least one heterosection and the channel region. | 03-03-2016 |
20160071965 | LEAKAGE CURRENT SUPPRESSION METHODS AND RELATED STRUCTURES - A method and structure for suppressing band-to-band tunneling current in a semiconductor device having a high-mobility channel material includes forming a channel region adjacent to and in contact with one of a source region and a drain region. A tunnel barrier layer may be formed such that the tunnel barrier layer is interposed between, and in contact with, the channel region and one of the source region and the drain region. In some embodiments, a gate stack is then formed over at least the channel region. In various examples, the tunnel barrier layer includes a first material, and the channel region includes a second material different than the first material. In some embodiments, the semiconductor device may be oriented in one of a horizontal or vertical direction, and the semiconductor device may include one of a single-gate or multi-gate device. | 03-10-2016 |
20160087047 | QUANTUM ROD AND METHOD OF FABRICATING THE SAME - A quantum rod includes a core of ZnS semiconductor particle having a rod shape; and a transition metal with which the core is doped and which is biased at one side of a length direction of the core. | 03-24-2016 |
20160087086 | SEMICONDUCTOR DEVICES - Semiconductor devices include an intrinsic semiconductor region on a substrate, a source region adjacent to a first side surface of the semiconductor region and doped with a p-type dopant, a drain region adjacent to a second side surface of the semiconductor region, a gate electrode on the semiconductor region, a source gate electrode on the source region, and a drain gate electrode on the drain region. The second side surface is a reverse side of the first side surface. The drain region is doped with a p-type dopant. | 03-24-2016 |
20160099343 | TUNNELING FIELD EFFECT TRANSISTOR AND METHODS OF MAKING SUCH A TRANSISTOR - One illustrative method of forming a TFET device includes forming a first semiconductor material that extends for a full length of a drain region, a gate region and a source region of the device, masking the drain region while exposing at least a portion of the gate region and exposing the source region, forming a second semiconductor material above the gate region and above the source region, forming a third semiconductor material above the second semiconductor material and above the gate region and above the source region, the third semiconductor material being doped with an opposite type of dopant material than in the first semiconductor material, masking the drain region, and forming a gate structure above at least a portion of the exposed gate region. | 04-07-2016 |
20160133699 | Reduced Scale Resonant Tunneling Field Effect Transistor - An embodiment includes a heterojunction tunneling field effect transistor including a source, a channel, and a drain; wherein (a) the channel includes a major axis, corresponding to channel length, and a minor axis that corresponds to channel width and is orthogonal to the major axis; (b) the channel length is less than 10 nm long; (c) the source is doped with a first polarity and has a first conduction band; (d) the drain is doped with a second polarity, which is opposite the first polarity, and the drain has a second conduction band with higher energy than the first conduction band. Other embodiments are described herein. | 05-12-2016 |
20160197184 | TUNNEL FIELD EFFECT TRANSISTORS HAVING LOW TURN-ON VOLTAGE | 07-07-2016 |