Entries |
Document | Title | Date |
20080197339 | Nanocrystal powered nanomotor - A nanoscale nanocrystal which may be used as a reciprocating motor is provided, comprising a substrate having an energy differential across it, e.g. an electrical connection to a voltage source at a proximal end; an atom reservoir on the substrate distal to the electrical connection; a nanoparticle ram on the substrate distal to the atom reservoir; a nanolever contacting the nanoparticle ram and having an electrical connection to a voltage source, whereby a voltage applied between the electrical connections on the substrate and the nanolever causes movement of atoms between the reservoir and the ram. Movement of the ram causes movement of the nanolever relative to the substrate. The substrate and nanolever preferably comprise multiwalled carbon nanotubes (MWNTs) and the atom reservoir and nanoparticle ram are preferably metal (e.g. indium) deposited as small particles on the MWNTs. The substrate may comprise a silicon chip that has been fabricated to provide the necessary electrodes and other electromechanical structures, and further supports an atomic track, which may comprise an MWNT. | 08-21-2008 |
20080203380 | CNT devices, low-temperature fabrication of CTN and CNT photo-resists - A method is provided for growth of carbon nanotube (CNT) synthesis at a low temperature. The method includes preparing a catalyst by placing the catalyst between two metal layers of high chemical potential on a substrate, depositing such placed catalyst on a surface of a wafer, and reactivating the catalyst in a high vacuum at a room temperature in a catalyst preparation chamber to prevent a deactivation of the catalyst. The method also includes growing carbon nanotubes on the substrate in the high vacuum in a CNT growth chamber after preparing the catalyst. | 08-28-2008 |
20080230763 | Metallic Nanospheres Embedded in Nanowires Initiated on Nanostructures and Methods for Synthesis Thereof - A nanostructure includes a nanowire having metallic spheres formed therein, the spheres being characterized as having at least one of about a uniform diameter and about a uniform spacing there between. A nanostructure in another embodiment includes a substrate having an area with a nanofeature; and a nanowire extending from the nanofeature, the nanowire having metallic spheres formed therein, the spheres being characterized as having at least one of about a uniform diameter and about a uniform spacing there between. A method for forming a nanostructure is also presented. A method for reading and writing data is also presented. A method for preparing nanoparticles is also presented. | 09-25-2008 |
20080237568 | Methods of making nano-scale structures having controlled size, nanowire structures and methods of making the nanowire structures - Methods of making nanometer-scale semiconductor structures with controlled size are disclosed. Semiconductor structures that include one or more nanowires are also disclosed. The nanowires can include a passivation layer or have a hollow tube structure. | 10-02-2008 |
20080272361 | High Density Nanotube Devices - Carbon-nanotube-based devices or nanowire-based devices are formed in multiple layers to obtain higher density of such devices. The layers may be all similar such as all carbon-nanotube-based transistors. Or they may be different, such as one layer with nanowire devices and another layer with nanotube devices. Or some layers such as the bottom layer may be based on silicon devices and another layer with nanotube devices. Traditional interconnects and vias may be used to connect layers and electrodes, or nanoscale materials such as nanotubes or nanowires may be used as interconnects or vias. | 11-06-2008 |
20080308786 | Manufacturing Method for the Integration of Nanostructures Into Microchips - State-of-the-art synthesis of carbon nanostructures ( | 12-18-2008 |
20090001349 | LIGHT-EMITTING NANOCOMPOSITE PARTICLES - A method of making an inorganic light emitting layer includes combining a solvent for semiconductor nanoparticle growth, a solution of core/shell quantum dots, and semiconductor nanoparticle precursor(s); growing semiconductor nanoparticles to form a crude solution of core/shell quantum dots, semiconductor nanoparticles, and semiconductor nanoparticles that are connected to the core/shell quantum dots; forming a single colloidal dispersion of core/shell quantum dots, semiconductor nanoparticles, and semiconductor nanoparticles that are connected to the core/shell quantum dots; depositing the colloidal dispersion to form a film; and annealing the film to form the inorganic light emitting layer. | 01-01-2009 |
20090014711 | Nanowhiskers with PN junctions, doped nanowhiskers, and methods for preparing them - Nano-engineered structures are disclosed, incorporating nanowhiskers of high mobility conductivity and incorporating pn junctions. In one embodiment, a nanowhisker of a first semiconducting material has a first band gap, and an enclosure comprising at least one second material with a second band gap encloses said nanoelement along at least part of its length, the second material being doped to provide opposite conductivity type charge carriers in respective first and second regions along the length of the of the nanowhisker, whereby to create in the nanowhisker by transfer of charge carriers into the nanowhisker, corresponding first and second regions of opposite conductivity type charge carriers with a region depleted of free carriers therebetween. The doping of the enclosure material may be degenerate so as to create within the nanowhisker adjacent segments having very heavy modulation doping of opposite conductivity type analogous to the heavily doped regions of an Esaki diode. In another embodiment, a nanowhisker is surrounded by polymer material containing dopant material. A step of rapid thermal annealing causes the dopant material to diffuse into the nanowhisker. In a further embodiment, a nanowhisker has a heterojunction between two different intrinsic materials, and Fermi level pinning creates a pn junction at the interface without doping. | 01-15-2009 |
20090020747 | METHOD FOR REALIZING A HOSTING STRUCTURE OF NANOMETRIC ELEMENTS - A nanometric device comprising a substrate; a plurality of conductive spacers of a conductive material, each conductive spacer being arranged on top of and transverse to the substrate, the conductive spacers including respective pairs of conductive spacers defining respective hosting seats each of less than 30 nm wide; and a plurality of nanometric elements respectively accommodated in the hosting seats. | 01-22-2009 |
20090045391 | Switch Device and Method of Fabricating the Same - Provided is a switch device that can be reliably turned on or off using a nanostructure that includes a nanotube and/or a nanowire. The switch device includes a lower conductive film formed on a substrate, a first insulating film formed on the lower conductive film and having a first hole that exposes at least a portion of the first lower conductive film, and a conductive film spacer formed on an inner wall of the first hole of the first insulating film. A switch device may include a nanostructure having an end electrically connected to the lower conductive film, including a nanotube and/or a nanowire, extending substantially vertically from the lower conductive film and penetrating through the first hole, and separated from the conductive film spacer with a working gap interposed therebetween. | 02-19-2009 |
20090072219 | MOS transistor on the basis of quantum interferance effect - A new type of Metal Oxide Semiconductor (MOS) transistor that works on the basis of the Quantum Interference Depression (QID) effect is disclosed. QID occurs inside an n-type semiconductor source-drain electrode of special geometry. Due to QID the Fermi level of said semiconductor increases locally inside the source drain electrode, thereby creating a localised potential energy barrier in the path of electrons moving from source to drain regions. The height of the barrier depends on the degree of QID. QID is in turn regulated by the gate voltage via the charge depletion and hence change in effective dimensions of the special geometry of the semiconductor electrode. A gate voltage modulated potential energy barrier and is thus formed whereby current in said MOS transistor is controlled. | 03-19-2009 |
20090078927 | Composite hard mask for the etching of nanometer size magnetic multilayer based device - A composite hard mask is disclosed that enables sub-100 nm sized MTJ cells to be formed for advanced devices such as spin torque MRAMs. The hard mask has a lower non-magnetic metallic layer such as Ru to magnetically isolate an overlying middle metallic spacer such as MnPt from an underlying free layer. The middle metallic spacer provides a height margin during subsequent processing to avoid shorting between a bit line and the MTJ cell in the final device. An upper conductive layer may be made of Ta and is thin enough to allow a MTJ pattern in a thin overlying photoresist layer to be transferred through the Ta during a fluorocarbon etch without consuming all of the photoresist. The MTJ pattern is transferred through the remaining hard mask layers and underlying MTJ stack of layers with a second etch step using a C, H, and O etch gas composition. | 03-26-2009 |
20090152527 | METHOD FOR PRODUCING CATALYST-FREE SINGLE CRYSTAL SILICON NANOWIRES, NANOWIRES PRODUCED BY THE METHOD AND NANODEVICE COMPRISING THE NANOWIRES - Disclosed herein is a method for producing catalyst-free single crystal silicon nanowires. According to the method, nanowires can be produced in a simple and economical manner without the use of any metal catalyst. In addition, impurities contained in a metal catalyst can be prevented from being introduced into the nanowires, contributing to an improvement in the electrical and optical properties of the nanowires. Also disclosed herein are nanowires produced by the method and nanodevice comprising the nanowires. | 06-18-2009 |
20090184311 | Nanowire placement by electrodeposition - Electrodeposition is used to deposit nanowires in a controlled fashion with accurate placement and orientation. A substrate is provided with a mesa having electrically conductive sidewalls. The substrate is immersed in an electroplating solution having a dispersion of nanowires, and metal is electroplated onto the sidewalls of the mesa. During electrodeposition, nanowires are incorporated and partially embedded in the deposited metal film. The nanowires will tend to be parallel with the substrate. Additionally electrodes can be deposited to provide electrical contact with the free ends of the nanowires. In this way, electrical connections can be provided to nanowires in a controlled, reproducible manner. The deposited nanowires can be used in a multitude of devices. | 07-23-2009 |
20090212275 | NANO/MICRO-SIZED DIODE AND METHOD OF PREPARING THE SAME - A nano/micro-sized diode and a method of preparing the same, the diode including: a first electrode; a second electrode; and a diode layer that is disposed between the first electrode and the second electrode. The diode layer includes a first layer and a second layer. The first layer is disposed on the first electrode and has a first surface that is electrically connected to the first electrode, and an opposing second surface that has a protrusion. The second layer is disposed between the first layer and the second electrode and has a first surface having a recess that corresponds to the protrusion, and an opposing second surface that is electrically connected to the second electrode. | 08-27-2009 |
20090218560 | METHOD FOR REVERSIBLY MOUNTING A DEVICE WAFER TO A CARRIER SUBSTRATE - New temporary bonding methods and articles formed from those methods are provided. The methods comprise bonding a device wafer to a carrier wafer or substrate only at their outer perimeters in order to assist in protecting the device wafer and its device sites during subsequent processing and handling. The edge bonds formed by this method are chemically and thermally resistant, but can also be softened, dissolved, or mechanically disrupted to allow the wafers to be easily separated with very low forces and at or near room temperature at the appropriate stage in the fabrication process. | 09-03-2009 |
20090230380 | Methods for Formation of Substrate Elements - The present invention relates to methods of forming substrate elements, including semiconductor elements such as nanowires, transistors and other structures, as well as the elements formed by such methods. | 09-17-2009 |
20090256134 | Process for Fabricating Nanowire Arrays - A process is provided for etching a silicon-containing substrate to form nanowire arrays. In this process, one deposits nanoparticles and a metal film onto the substrate in such a way that the metal is present and touches silicon where etching is desired and is blocked from touching silicon or not present elsewhere. One submerges the metallized substrate into an etchant aqueous solution comprising HF and an oxidizing agent. In this way arrays of nanowires with controlled diameter and length are produced. | 10-15-2009 |
20090278112 | METHODS FOR ETCHING CARBON NANO-TUBE FILMS FOR USE IN NON-VOLATILE MEMORIES - Memory cells, and methods of forming such memory cells are provided that include a steering element coupled to a carbon-based reversible resistivity-switching material. In particular embodiments, methods in accordance with this invention etch a carbon nano-tube (“CNT”) film formed over a substrate, the methods including coating the substrate with a masking layer, patterning the masking layer, and etching the CNT film through the patterned masking layer using a non-oxygen based chemistry. Other aspects are also described. | 11-12-2009 |
20090283742 | Methods and articles including nanomaterial - A method of depositing a nanomaterial onto a donor surface comprises depositing a composition comprising nanomaterial onto a donor surface from a micro-dispenser. In another aspect of the invention there is provided a method of depositing a nanomaterial onto a substrate. Methods of making a device including nanomaterial are disclosed. An article of manufacture comprising nanomaterial and a material capable of transporting charge disposed on a backing member is disclosed. | 11-19-2009 |
20090283743 | Composite including nanoparticles, methods, and products including a composite - A composite comprising a first layer comprising a first material including nanoparticles dispersed therein, wherein the first material comprises a material capable of transporting charge, a second layer comprising a second material, and a backing element that is removably attached to the uppermost layer of the composite or the lowermost layer of the composite. In certain preferred embodiments, a least a portion of the nanoparticles include a ligand attached to a surface thereof. Methods are also disclosed. Products including a composite is further provided. Composite materials can be particularly well-suited for use, for example, in products useful in various optical, electronic, optoelectronic, magnetic, or catalytic devices. | 11-19-2009 |
20090283744 | Thin film transistor - A thin film transistor includes a source electrode, a drain electrode, a semiconducting layer, and a gate electrode. The drain electrode is spaced from the source electrode. The semiconducting layer is electrically connected to the source electrode and the drain electrode. The gate electrode is insulated from the source electrode, the drain electrode, and the semiconducting layer by an insulating layer. The at least one of the source electrode, drain electrode, and the gate electrode includes a metallic carbon nanotube layer. The metallic carbon nanotube layer includes a plurality of metallic carbon nanotubes. | 11-19-2009 |
20090283745 | METHODS OF MAKING CARBON NANOTUBE FILMS, LAYERS, FABRICS, RIBBONS, ELEMENTS AND ARTICLES - Methods of making carbon nanotube films, layers, fabrics, ribbons, elements and articles are disclosed. Carbon nanotube growth catalyst is applied on to a surface of a substrate. The substrate is subjected to a chemical vapor deposition of a carbon-containing gas to grow a non-woven fabric of carbon nanotubes. Portions of the non-woven fabric are selectively removed according to a defined pattern to create the article. A non-woven fabric of carbon nanotubes may be made by applying carbon nanotube growth catalyst on to a surface of a wafer substrate to create a dispersed monolayer of catalyst. The substrate is subjected to a chemical vapor deposition of a carbon-containing gas to grow a non-woven fabric of carbon nanotubes in contact and covering the surface of the wafer and in which the fabric is substantially uniform density. | 11-19-2009 |
20090294753 | CARBON NANOTUBE DIAMETER SELECTION BY PRETREATMENT OF METAL CATALYSTS ON SURFACES - A new and useful nanotube growth substrate conditioning processes is herein disclosed that allows the growth of vertical arrays of carbon nanotubes where the average diameter of the nanotubes can be selected and/or controlled as compared to the prior art. | 12-03-2009 |
20090294754 | NOVEL TECHNIQUES FOR PRECISION PATTERN TRANSFER OF CARBON NANOTUBES FROM PHOTO MASK TO WAFERS - A method for patterning CNTs on a wafer wherein a CNT layer is provided on a substrate, a hard mask film is deposited on the CNT layer, a BARC layer (optional) is coated on the hard mask film, and a resist is patterned on the BARC layer (or directly on the hard mask film if the BARC layer is not included). Then, the resist pattern is effectively transferred to the hard mask film by etching the BARC layer (if provided) and etching partly into, but not entirely through, the hard mask film (i.e., etching is stopped before reaching the CNT layer). Then, the resist and the BARC layer (if provided) is stripped, and the hard mask pattern is effectively transferred to the CNTs by etching away (preferably by using C1, F plasma) the portions of the hard mask which have been already partially etched away. | 12-03-2009 |
20090294755 | Fabricating Arrays Of Metallic Nanostructures - A patterned array of metallic nanostructures and fabrication thereof is described. A device comprises a patterned array of metallic columns vertically extending from a substrate. Each metallic column is formed by metallically coating one of an array of non-metallic nanowires catalytically grown from the substrate upon a predetermined lateral pattern of seed points placed thereon according to a nanoimprinting process. An apparatus for fabricating a patterned array of metallic nanostructures is also described. | 12-03-2009 |
20090294756 | LIGHT EMITTING DIODE STRUCTURE AND METHOD FOR FABRICATING THE SAME - The present invention discloses a light emitting diode structure and a method for fabricating the same. In the present invention, a substrate is placed in a solution to form a chemical reaction layer. Next, the substrate is etched to form a plurality of concave zones and a plurality of convex zones with the chemical reaction layer overhead. Next, the chemical reaction layer is removed to form an irregular geometry of the concave zones and convex zones on the surface of the substrate. Then, a semiconductor light emitting structure is epitaxially formed on the surface of the substrate. Thereby, the present invention can achieve a light emitting diode structure having improved internal and external quantum efficiencies. | 12-03-2009 |
20090302304 | DOPED SEMICONDUCTOR NANOCRYSTALS AND METHODS OF MAKING SAME - A method of synthesizing doped semiconductor nanocrystals. In one embodiment, the method includes the steps of combining a metal oxide or metal salt precursor, a ligand, and a solvent to form a metal complex in a reaction vessel; admixing an anionic precursor with the metal complex at a first temperature, T | 12-10-2009 |
20090302305 | SELF-CONSTRAINED ANISOTROPIC GERMANIUM NANOSTRUCTURE FROM ELECTROPLATING - A nanostructure comprising germanium, including wires of less than 1 micron in diameter and walls of less than 1 micron in width, in contact with the substrate and extending outward from the substrate is provided along with a method of preparation. | 12-10-2009 |
20090309090 | Nanostructures and a Method for the Manufacture of the Same - A nanostructure comprising a first structure comprising conductive material, which is attached to a second structure comprising one or more portions of conductive material separated by insulator material, which is attached to a third structure comprising a material in which a change can be effected. The third structure may comprise a dielectric or ferroelectric material, and the change effected in the material may be polarization of the material. The nanostructure may comprise one or more nanocapacitors, each of which comprises a part of the third structure in which a change comprising polarization may be effected. The nanocapacitors may be used to store data. | 12-17-2009 |
20090315011 | NANOTUBE DEVICE STRUCTURE AND METHODS OF FABRICATION - Nanotube device structures and methods of fabrication. A method of making a nanotube switching element includes forming a first structure having at a first output electrode; forming second structure having a second output electrode; forming a conductive article having at least one nanotube, the article having first and second ends; positioning the conductive article between said first and second structures such that the first structure clamps the first and second ends of the article to the second structure, and such that the first and second output electrodes are opposite each other with the article positioned therebetween; providing at least one signal electrode in electrical communication with the conductive article; and providing at least one control electrode in spaced relation to the conductive article such that the control electrode may control the conductive article to form a conductive pathway between the signal electrode and the first output electrode. | 12-24-2009 |
20090321712 | PLASMONIC COUPLING DEVICES - A plasmonic coupling device ( | 12-31-2009 |
20100001255 | SELECTIVE NANOTUBE FORMATION AND RELATED DEVICES - Nanotube electronic devices exhibit selective affinity to disparate nanotube types. According to an example embodiment, a semiconductor device exhibits a treated substrate that selectively interacts (e.g., chemically) with nanotubes of a first type, relative to nanotubes of a second type, the respective types including semiconducting-type and metallic-type nanotubes. The selective interaction is used to set device configuration characteristics based upon the nanotube type. This selective-interaction approach can be used to set the type, and/or characteristics of nanotubes in the device. | 01-07-2010 |
20100012919 | GAS SENSOR HAVING ZINC OXIDE NANO-STRUCTURES AND METHOD OF FABRICATING THE SAME - Provided are a gas sensor using a plurality of zinc oxide nano-structures on which metal islands are formed, and a method of fabricating the same. The gas sensor comprises zinc oxide nano-structures formed on a substrate, a plurality of metal islands coated on a surface of each zinc oxide nano-structure and separated from one another, a first electrode electrically connected to one end of each zinc oxide nano-structure through the substrate, a second electrode electrically connected to the other end of each zinc oxide nano-structure, and a current variation-measuring unit electrically connected to each of the first electrode and the second electrode so as to measure a variation in the amount of current flowing between the first electrode and the second electrode. In order to form the plurality of metal islands separated from one another on the surface of each zinc oxide nano-structure using a wet process, metal components of a metal material are coated on the surface of each zinc oxide nano-structure using the solution in which the metal material is solved. | 01-21-2010 |
20100038625 | NONVOLATILE NANOTUBE PROGRAMMABLE LOGIC DEVICES AND A NONVOLATILE NANOTUBE FIELD PROGRAMMABLE GATE ARRAY USING SAME - Field programmable device (FPD) chips with large logic capacity and field programmability that are in-circuit programmable are described. FPDs use small versatile nonvolatile nanotube switches that enable efficient architectures for dense low power and high performance chip implementations and are compatible with low cost CMOS technologies and simple to integrate. | 02-18-2010 |
20100051897 | DEVICE AND PROCESS OF FORMING DEVICE WITH DEVICE STRUCTURE FORMED IN TRENCH AND GRAPHENE LAYER FORMED THEREOVER - A graphene-based device is formed with a substrate having a trench therein, a device structure on the substrate and within the trench, a graphene layer over the device structure, and a protective layer over the graphene layer. Fabrication techniques include forming a trench in a substrate, forming a device structure within the trench, forming a graphene layer over the device structure, and forming a protective layer over the graphene layer. | 03-04-2010 |
20100051898 | QUANTUM DOT-WAVELENGTH CONVERTER, MANUFACTURING METHOD OF THE SAME AND LIGHT EMITTING DEVICE INCLUDING THE SAME - There is provided a quantum dot wavelength converter including a quantum dot, which is optically stable without any change in an emission wavelength and improved in emission capability. The quantum dot wavelength converter includes: a wavelength converting part including a quantum dot wavelength-converting excitation light and generating a wavelength-converted light and a dispersive medium dispersing the quantum dot; and a sealer sealing the wavelength converting part. | 03-04-2010 |
20100051899 | Method of manufacturing nanowire, method of manufacturing a semiconductor apparatus including nanowire and semiconductor apparatus formed from the same - A method of manufacturing a nanowire, a method of manufacturing a semiconductor apparatus including a nanowire and a semiconductor apparatus formed from the same are provided. The method of manufacturing a semiconductor apparatus may include forming a material layer pattern on a substrate, forming a first insulating layer on the material layer pattern, a first nanowire forming layer and a top insulating layer on the substrate, wherein a total depth of the first insulating layer and the first nanowire forming layer may be formed to be smaller than a depth of the material layer pattern, sequentially polishing the top insulating layer, the first nanowire forming layer and the first insulating layer so that the material layer pattern is exposed, exposing part of the first nanowire forming layer to form an exposed region and forming a single crystalline nanowire on an exposed region of the first nanowire forming layer. | 03-04-2010 |
20100065809 | NANOWIRE COMPRISING SILICON RICH OXIDE AND METHOD FOR PRODUCING THE SAME - Disclosed herein is a nanowire including silicon rich oxide and a method for producing the same. The nanowire exhibits excellent electrically conducting properties and optical characteristics, and therefore is effectively used in a variety of applications including, for example, solar cells, sensors, photodetectors, light emitting diodes, laser diodes, EL devices, PL devices, CL devices, FETs, CTFs, surface plasmon waveguides, MOS capacitors and the like. | 03-18-2010 |
20100065810 | Method Of Synthesizing Semiconductor Nanostructures And Nanostructures Synthesized By The Method - A method of synthesizing semiconductor nanostructures of at least one semiconductor material (e.g. nanowires, nanorods, nanoribbons, nanodots, quantumdots, etc.) is described which includes the steps of placing a solid catalyst particle on a substrate, placing the combination of the said substrate and the said solid catalyst in a chamber of low oxygen partial pressure, below I×10 | 03-18-2010 |
20100072455 | Well-Structure Anti-Punch-through Microwire Device - A well-structure anti-punch-through microwire device and associated fabrication method are provided. The method initially forms a microwire with alternating highly and lightly doped cylindrical regions. A channel ring is formed external to the microwire outer shell and surrounding a first dopant well-structure region in the microwire, between source and drain (S/D) regions of the microwire. The S/D regions are doped with a second dopant, opposite to the first dopant. A gate dielectric ring is formed surrounding the channel ring, and a gate electrode ring is formed surrounding the gate dielectric ring. The well-structure, in contrast to conventional micro or nanowire transistors, helps prevent the punch-through phenomena. | 03-25-2010 |
20100084628 | BRANCHED NANOWIRE AND METHOD FOR FABRICATION OF THE SAME - Disclosed herein are a branched nanowire having parasitic nanowires grown at a surface of the branched nanowire, and a method for fabricating the same. The branched nanowire may be fabricated in a fractal form and seeds of the parasitic nanowires may be formed by thermal energy irradiation and/or a wet-etching process. The branched nanowire may effectively be used in a wide variety of applications such as, for example, sensors, photodetectors, light emitting elements, light receiving elements, and the like. | 04-08-2010 |
20100102292 | SEMICONDUCTOR DEVICE USING GRAPHENE AND METHOD OF MANUFACTURING THE SAME - A semiconductor graphene is used for a channel layer, and a metal graphene is used for electrode layers for a source, a drain, and a gate which serve as interconnections as well. An oxide is used for a gate insulating layer. The channel layer and the electrode layers are located on the same plane. | 04-29-2010 |
20100140584 | METHOD FOR PRODUCING CATALYST-FREE SINGLE CRYSTAL SILICON NANOWIRES, NANOWIRES PRODUCED BY THE METHOD AND NANODEVICE COMPRISING THE NANOWIRES - Disclosed herein is a method for producing catalyst-free single crystal silicon nanowires. According to the method, nanowires can be produced in a simple and economical manner without the use of any metal catalyst. In addition, impurities contained in a metal catalyst can be prevented from being introduced into the nanowires, contributing to an improvement in the electrical and optical properties of the nanowires. Also disclosed herein are nanowires produced by the method and nanodevice comprising the nanowires. | 06-10-2010 |
20100148144 | SEMICONDUCTING NANOPARTICLES WITH SURFACE MODIFICATION - The invention relates to semiconducting nanoparticles. The nanoparticles of the invention comprise a single element or a compound of elements in one or more of groups II, III, IV, V, VI. The nanoparticles have a size in the range of 1 nm to 500 nm, and comprise from 0.1 to 20 atomic percent of oxygen or hydrogen. The nanoparticles are typically formed by comminution of bulk high purity silicon. One application of the nanoparticles is in the preparation of inks which can be used to define active layers or structures of semiconductor devices by simple printing methods. | 06-17-2010 |
20100155691 | METHOD OF FABRICATING SEMICONDUCTOR OXIDE NANOFIBERS FOR SENSOR AND GAS SENSOR USING THE SAME - A gas sensor for detecting environmentally harmful gases is provided. The sensor includes an insulating substrate, a metal electrode formed on the insulating substrate, and a sensing layer formed on the metal electrode and including a semiconductor oxide (La | 06-24-2010 |
20100155692 | NANO MEMORY, LIGHT, ENERGY, ANTENNA AND STRAND-BASED SYSTEMS AND METHODS - An apparatus includes a first array of transistor elements; a second array of carbon nano-elements formed above or below the first array of transistor elements; and a circuit coupled to the first array to access the carbon nano elements. | 06-24-2010 |
20100163838 | METHOD OF ISOLATING NANOWIRES FROM A SUBSTRATE - A method is provided. The method includes forming a plurality of nanowires on a top surface of a substrate and forming an oxide layer adjacent to a bottom surface of each of the plurality of nanowires, wherein the oxide layer is to isolate each of the plurality of nanowires from the substrate. | 07-01-2010 |
20100163839 | SEMICONDUCTOR SUBSTRATE FOR GROWTH OF AN EPITAXIAL SEMICONDUCTOR DEVICE - A semiconductor substrate includes: a base layer; a sacrificial layer that is formed on a base layer and that includes a plurality of spaced apart sacrificial film regions and a plurality of first passages each of which is defined between two adjacent ones of the sacrificial film regions. Each sacrificial film region has a plurality of nanostructures and a plurality of second passages defined among the nanostructures. The second passages communicate spatially with the first passages and have a width less than that of the first passages. An epitaxial layer is disposed on the sacrificial layer. | 07-01-2010 |
20100171092 | METHOD FOR CONTROLLING OPTIC INTERBAND TRANSITION OF CARBON NANOTUBES, THE CARBON NANOTUBES RESULTING THEREFROM AND DEVICES THAT COMPRISE THE CARBON NANOTUBES - A new single optical interband transition occurs at the corresponding p-doping state of the carbon nanotubes in the VIS-NIR region when the degree of p-doping of carbon nanotubes is increased beyond a certain degree. P-doped carbon nanotubes to exhibit the new single optical interband transition in the VIS-NIR region may be used for devices so as to improve sensitivity and selectivity of the devices. | 07-08-2010 |
20100193766 | Process for Producing a PN Homojunction in a Nanostructure - The invention relates to a process for producing a p-n junction in a nanostructure, in which the nanostructure has one or more nanoconstituents made of a semiconductor material with a single type of doping having one conductivity type, characterized in that it includes a step consisting in forming a dielectric element ( | 08-05-2010 |
20100193767 | ENCAPSULATED NANOPARTICLES - A nanoparticle composition including a semiconductor nanoparticle encapsulated within a self-assembled layer including an amphiphilic cross-linkable multi-unsaturated fatty acid based compound or derivative thereof. In other embodiments, a nanoparticle composition includes a semiconductor nanoparticle encapsulated within a self-assembled layer including an amphiphilic cross-linkable C | 08-05-2010 |
20100193768 | SEMICONDUCTING NANOWIRE ARRAYS FOR PHOTOVOLTAIC APPLICATIONS - This invention relates to the fabrication of nanowires for electrical and electronic applications. A method of growing silicon nanowires using an alumina template is disclosed whereby the aluminum forming the alumina is also used as the catalyst for growing the silicon nanowires in a VLS (CVD) process and as the semiconductor dopant. In addition, various techniques for masking off parts of the aluminum and alumina in order to maintain electrical isolation between device layers is disclosed. | 08-05-2010 |
20100200834 | Crystalline nanowire substrate, method of manufacturing the same, and method of manufacturing thin film transistor using the same - Example embodiments relate to a crystalline nanowire substrate having a structure in which a crystalline nanowire film having a relatively fine line-width may be formed on a substrate, a method of manufacturing the same, and a method of manufacturing a thin film transistor using the same. The method of manufacturing the crystalline nanowire substrate may include preparing a substrate, forming an insulating film on the substrate, forming a silicon film on the insulating film, patterning the insulating film and the silicon film into a strip shape, reducing the line-width of the insulating film by undercut etching at least one lateral side of the insulating film, and forming a self-aligned silicon nanowire film on an upper surface of the insulating film by melting and crystallizing the silicon film. | 08-12-2010 |
20100200835 | FABRICATION OF GERMANIUM NANOWIRE TRANSISTORS - In general, in one aspect, a method includes using the Germanium nanowire as building block for high performance logic, memory and low dimensional quantum effect devices. The Germanium nanowire channel and the SiGe anchoring regions are formed simultaneously through preferential Si oxidation of epitaxial Silicon Germanium epi layer. The placement of the germanium nanowires is accomplished using a Si fin as a template and the germanium nanowire is held on Si substrate through SiGe anchors created by masking the two ends of the fins. High dielectric constant gate oxide and work function metals wrap around the Germanium nanowire for gate-all-around electrostatic channel on/off control, while the Germanium nanowire provides high carrier mobility in the transistor channel region. The germanium nanowire transistors enable high performance, low voltage (low power consumption) operation of logic and memory devices. | 08-12-2010 |
20100200836 | NANOPARTICLE POSITIONING TECHNIQUE - Embodiments of the present invention are generally directed to a method for disposing nanoparticles on a substrate. In one embodiment, a substrate having a plurality of recesses is provided. In this embodiment, a plurality of nanoparticles is also provided. The nanoparticles include a catalyst material coupled to one or more ligands, and these nanoparticles are disposed within respective recesses of the substrate. In some embodiments, the substrate is processed to form nanostructures, such as nanotubes or nanowires, within the recesses. Devices and systems having such nanostructures are also disclosed. | 08-12-2010 |
20100213434 | METHOD OF SYNTHESIZING NANOWIRES - A method of synthesizing a nanowire. The method includes disposing a first oxide layer including germanium (Ge) on a substrate, forming a second oxide layer including a nucleus by annealing the first oxide layer, and growing a nanowire including Ge from the nucleus by a chemical vapor deposition (“CVD”) method. | 08-26-2010 |
20100213435 | SWITCHING DEVICE AND NONVOLATILE MEMORY DEVICE - A switching device includes: a first layer including a carbon material having a six-member ring network structure; a first electrode electrically connected to a first portion of the first layer; a second electrode electrically connected to a second portion of the first layer and provided apart from the first electrode; a third electrode including a fourth portion provided opposing a third portion between the first portion and the second portion of the first layer; and a second layer provided between the third portion of the first layer and the fourth portion of the third electrode. The second layer includes: a base portion; and a functional group portion. The functional group portion is provided between the base portion and the first layer. The functional group portion is bonded to the base portion. A ratio of sp | 08-26-2010 |
20100224851 | SYNTHESIZING GRAPHENE FROM METAL-CARBON SOLUTIONS USING ION IMPLANTATION - A method and semiconductor device for synthesizing graphene using ion implantation of carbon. Carbon is implanted in a metal using ion implantation. After the carbon is distributed in the metal, the metal is annealed and cooled in order to precipitate the carbon from the metal to form a layer of graphene on the surface of the metal. The metal/graphene surface is then transferred to a dielectric layer in such a manner that the graphene layer is placed on top of the dielectric layer. The metal layer is then removed. Alternatively, recessed regions are patterned and etched in a dielectric layer located on a substrate. Metal is later formed in these recessed regions. Carbon is then implanted into the metal using ion implantation. The metal may then be annealed and cooled in order to precipitate the carbon from the metal to form a layer of graphene on the metal's surface. | 09-09-2010 |
20100243984 | Live bioelectronic cell gated nanodevice - This invention is directed toward a bioelectronic cell gated nanodevice. The bioelectronic cell gated nanodevice comprises a plurality of bioelectric cells deposited on a fiber of a nanodevice. The bioelectronic cells of the nanodevice act as a gate, allowing current to be transmitted when the bioelectronic cells are exposed to an actuating chemical. The present invention also provides methods for constructing such a device. | 09-30-2010 |
20100252800 | NANOWIRE DEVICES FOR ENHANCING MOBILITY THROUGH STRESS ENGINEERING - A p-type semiconductor nanowire transistor is formed on the first semiconductor nanowire and an n-type semiconductor nanowire transistor is formed on the second semiconductor nanowire. The first and second semiconductor nanowires have a rectangular cross-sectional area with different width-to-height ratios. The type of semiconductor nanowires for each semiconductor nanowire transistor is selected such that top and bottom surfaces provide a greater on-current per unit width than sidewall surfaces in a semiconductor nanowire having a greater width-to-height ratio, while sidewall surfaces provide a greater on-current per unit width than top and bottom surfaces in the other semiconductor nanowire having a lesser width-to-height ratio. Different types of stress-generating material layers may be formed on the first and second semiconductor nanowire transistors to provide opposite types of stress, which may be employed to enhance the on-current of the first and second semiconductor nanowire transistors. | 10-07-2010 |
20100252801 | SEMICONDUCTOR NANOWIRE WITH BUILT-IN STRESS - A semiconductor nanowire having two semiconductor pads on both ends is suspended over a substrate. Stress-generating liner portions are formed over the two semiconductor pads, while a middle portion of the semiconductor nanowire is exposed. A gate dielectric and a gate electrode are formed over the middle portion of the semiconductor nanowire while the semiconductor nanowire is under longitudinal stress due to the stress-generating liner portions. The middle portion of the semiconductor nanowire is under a built-in inherent longitudinal stress after removal of the stress-generating liners because the formation of the gate dielectric and the gate electrode locks in the strained state of the semiconductor nanowire. Source and drain regions are formed in the semiconductor pads to provide a semiconductor nanowire transistor. A middle-of-line (MOL) dielectric layer may be formed directly on the source and drain pads. | 10-07-2010 |
20100252802 | SEMICONDUCTOR ELEMENT - This invention provides a semiconductor element which uses a plurality of carbon nanotubes as a current path, can reduce contact resistance of its electrode contact part, and has excellent electrical characteristics. This semiconductor element is characterized in that the semiconductor element includes a current path ( | 10-07-2010 |
20100252803 | THIN FILM TRANSISTOR HAVING A NANO SEMICONDUCTOR SHEET AND METHOD OF MANUFACTURING THE SAME - Provided are a nano semiconductor sheet, a thin film transistor (TFT) using the nano semiconductor sheet, and a flat panel display using nano semiconductor sheet. The nano semiconductor sheet has excellent characteristics, can be manufactured at room temperature, and has good flexibility. The nano semiconductor sheet includes: a first film and a second film disposed on at least one side of or inside of the first film, and includes a plurality of nano particles arranged substantially in parallel to each other. In addition, provided are a method of manufacturing a nano semiconductor sheet and methods of manufacturing a TFT and a flat panel display using the nano semiconductor sheet. The method of manufacturing a nano semiconductor sheet, includes: forming first polymer micro-fibers having a plurality of nano particles arranged substantially in parallel; preparing a first film; and arranging a plurality of the first micro-fibers on at least one side of or inside of the first film. | 10-07-2010 |
20100264399 | METHOD OF FABRICATING NANOSIZED FILAMENTARY CARBON DEVICES OVER A RELATIVELY LARGE-AREA - Nanosized filamentary carbon structures (CNTs) nucleating over a catalyzed surface may be grown in an up-right direction reaching a second surface, spaced from the first surface, without the need of applying any external voltage source bias. The growth process may be inherently self-stopping, upon reaching a significant population of grown CNTs on the second surface. A gap between the two surfaces may be defined for CNT devices being simultaneously fabricated by common integrated circuit integration techniques. The process includes finding that for separation gaps of up to a hundred or more nanometers, a difference between the respective work functions of the materials delimiting the gap space, for example, different metallic materials or a doped semiconductor of different dopant concentration or type, may produce an electric field intensity orienting the growth of nucleated CNTs from the surface of one of the materials toward the surface of the other material. | 10-21-2010 |
20100270530 | SEMICONDUCTOR NANOWIRE SENSOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a biosensor device is provided. The method involves forming a silicon nanowire channel with a line width of several nanometers to several tens of nanometers using a typical photolithography process, and using the channel to manufacture a semiconductor nanowire sensor device. The method includes etching a first conductivity-type single crystalline silicon layer which is a top layer of a Silicon-On-Insulator (SOI) substrate to form a first conductivity-type single crystalline silicon line pattern, doping both sidewalls of the first conductivity-type single crystalline silicon line pattern with impurities of a second conductivity-type opposite to the first conductivity-type to form a second conductivity-type channel, forming second conductivity-type pads for forming electrodes at both ends of the first conductivity-type single crystalline silicon line pattern, forming, in an undoped region of the first conductivity-type single crystalline silicon line pattern, a first electrode for applying a reverse-bias voltage to insulate the first conductivity-type single crystalline silicon line pattern and the second conductivity-type channel from each other, and forming second electrodes for applying a bias voltage across the second conductivity-type channel on the second conductivity-type pad. | 10-28-2010 |
20100276661 | POLARITON MODE OPTICAL SWITCH - Devices, methods, and techniques for frequency-dependent optical switching are provided. In one embodiment, a device includes a substrate, a first and a second optical-field confining structures located on the substrate, and a quantum structure disposed between the first and the second optical-field confining structures. The first optical-field confining structure may include a surface to receive photons. The second optical-field confining structure may be spaced apart from the first optical-field confining structure. The first and the second optical-field confining structures may be configured to substantially confine therebetween an optical field of the photons. | 11-04-2010 |
20100276662 | JUNCTIONLESS METAL-OXIDE-SEMICONDUCTOR TRANSISTOR - A junctionless metal-oxide-semiconductor transistor is described. In one aspect, a transistor device comprises a semiconductor material. The semiconductor material comprises first, second, and third portions. The second portion is located between the first and third portions. The first, second, and third portions are doped with dopants of the same polarity and the same concentration. The transistor device further comprises an electrode connected to the second portion. A current flows between the first and third portions when a voltage is applied to the electrode. | 11-04-2010 |
20100283031 | BIOSENSOR USING NANODOT AND METHOD OF MANUFACTURING THE SAME - A biosensor using a nanodot and a method of manufacturing the same are provided. A silicon nanowire can be formed by a CMOS process to reduce manufacturing costs. In addition, an electrically charged nanodot is coupled to a target molecule to be detected, in order to readily change conductivity of the silicon nanowire, thereby making it possible to implement a biosensor capable of providing good sensitivity and being manufactured at a low cost. | 11-11-2010 |
20100283032 | METHOD FOR FORMING A SEMIDCONDUCTOR STRUCTURE - Method for Forming a Semiconductor Structure A method and apparatus for applying a carrier fluid ( | 11-11-2010 |
20100308299 | ELECTRONIC COMPONENT, METHODS FOR THE PRODUCTION THEREOF, AND USE THEREOF - An electronic component includes a first and a second electrode. A layer of nanoparticles is disposed between the first and second electrodes. The layer of nanoparticles includes an electrically conducting compound of a metal and an element of Main Group VI of the Periodic Table. A dimension of a majority of the nanoparticles ranges from 0.1 to 10 times a screening length of the electrically conductive compound. A dielectric layer has at least one common interface with at least a part of the nanoparticles. | 12-09-2010 |
20100314603 | ELECTRONIC AND OPTOELECTRONIC DEVICES WITH QUANTUM DOT FILMS - Optical and optoelectronic devices and methods of making same. Under one aspect, an optical device includes an integrated circuit an array of conductive regions; and an optically sensitive material over at least a portion of the integrated circuit and in electrical communication with at least one conductive region of the array of conductive regions. Under another aspect, a method of forming a nanocrystalline film includes fabricating a plurality of nanocrystals having a plurality of first ligands attached to their outer surfaces; exchanging the first ligands for second ligands of different chemical composition than the first ligands; forming a film of the ligand-exchanged nanocrystals; removing the second ligands; and fusing the cores of adjacent nanocrystals in the film to form an electrical network of fused nanocrystals. Under another aspect, a film includes a network of fused nanocrystals, the nanocrystals having a core and an outer surface, wherein the core of at least a portion of the fused nanocrystals is in direct physical contact and electrical communication with the core of at least one adjacent fused nanocrystal, and wherein the film has substantially no defect states in the regions where the cores of the nanocrystals are fused. | 12-16-2010 |
20100314604 | Gate-all-around type semiconductor device and method of manufacturing the same - The gate-all-around (GAA) type semiconductor device may include source/drain layers, a nanowire channel, a gate electrode and an insulation layer pattern. The source/drain layers may be disposed at a distance in a first direction on a semiconductor substrate. The nanowire channel may connect the source/drain layers. The gate electrode may extend in a second direction substantially perpendicular to the first direction. The gate electrode may have a height in a third direction substantially perpendicular to the first and second directions and may partially surround the nanowire channel. The insulation layer pattern may be formed between and around the source/drain layers on the semiconductor substrate and may cover the nanowire channel and a portion of the gate electrode. Thus, a size of the gate electrode may be reduced, and/or a gate induced drain leakage (GIDL) and/or a gate leakage current may be reduced. | 12-16-2010 |
20100320437 | Gas-phase functionalization of surfaces including carbon-based surfaces - The invention provides methods functionalizing a planar surface of a graphene layer, a graphite surface, or microelectronic structure. The graphene layer, graphite surface, or planar microelectronic structure surface is exposed to at least one vapor including at least one functionalization species that non-covalently bonds to the graphene layer, a graphite surface, or planar microelectronic surface while providing a functionalization layer of chemically functional groups, to produce a functionalized graphene layer, graphite surface, or planar microelectronic surface. | 12-23-2010 |
20100320438 | COMPLEXES OF CARBON NANOTUBES AND FULLERENES WITH MOLECULAR-CLIPS AND USE THEREOF - Separation of carbon nanotubes or fullerenes according to diameter through non-covalent pi-pi interaction with molecular clips is provided. Molecular clips are prepared by Diels-Alder reaction of polyacenes with a variety of dienophiles. The pi-pi complexes of carbon nanotubes with molecular clips are also used for selective placement of carbon nanotubes and fullerenes on substrates. | 12-23-2010 |
20100327255 | NANOFLUDIC FIELD EFFECT TRANSISTOR BASED ON SURFACE CHARGE MODULATED NANOCHANNEL - A field effect transistor device includes: a reservoir bifurcated by a membrane of three layers: two electrically insulating layers; and an electrically conductive gate between the two insulating layers. The gate has a surface charge polarity different from at least one of the insulating layers. A nanochannel runs through the membrane, connecting both parts of the reservoir. The device further includes: an ionic solution filling the reservoir and the nanochannel; a drain electrode; a source electrode; and voltages applied to the electrodes (a voltage between the source and drain electrodes and a voltage on the gate) for turning on an ionic current through the ionic channel wherein the voltage on the gate gates the transportation of ions through the ionic channel. | 12-30-2010 |
20110001117 | NANOSCALE WIRE-BASED MEMORY DEVICES - The present invention generally relates to nanotechnology and sub-microelectronic devices that can be used in circuitry, and, in particular, to nanoscale wires and other nanostructures able to encode data. One aspect of the present invention is directed to a device comprising an electrical crossbar array comprising at least two crossed wires at a cross point. In some cases, at least one of the crossed wires is a nanoscale wire, and in certain instances, at least one of the crossed wires is a nanoscale wire comprising a core and at least one shell surrounding the core. For instance, the core may comprise a crystal (e.g., crystalline silicon) and the shell may be at least partially amorphous (e.g., amorphous silicon). In certain embodiments, the cross point may exhibit intrinsic current rectification, or other electrical behaviors, and the cross point can be used as a memory device. For example, in one embodiment, the cross point may exhibit a first conductance at a positive voltage, and the cross point may exhibit a second conductance at a negative voltage. Accordingly, by applying suitable voltages to the cross point, data may be stored at the cross point. Other aspects of the present invention are directed to systems and methods for making or using such devices, kits involving such devices, or the like. | 01-06-2011 |
20110001118 | PATTERNING OF NANOSTRUCTURES - A method of patterning nanostructures comprising printing an ink comprising the nanostructures onto a solvent-extracting first surface such that a pattern of nanostructures is formed on the first surface. | 01-06-2011 |
20110001119 | METHOD FOR THE SYNTHESIS OF AN ARRAY OF METAL NANOWIRE CAPABLE OF SUPPORTING LOCALIZED PLASMON RESONANCES AND PHOTONIC DEVICE COMPRISING SAID ARRAY - A method is for the synthesis of an array of metal nanowires (w) capable of supporting localized plasmon resonances. A metal film (M) deposited on a planar substrate (D) is irradiated with a defocused beam of noble gas ions (IB) under high vacuum, so that, with increasing ion doses a corrugation is produced on the metal film surface, formed by a mutually parallel nanoscale self-organized corrugations (r). Subsequently, the height of the self-organized corrugations peaks is increased relative to the valleys (t) interposed therebetween. Then the whole the metal film is eroded so as to expose the substrate at the valleys, and to mutually disconnect the self-organized corrugations, thereby generating the array of metal nanowires. Finally, the transversal cross-section of the nanowires is reduced in a controlled manner so as to adjust the localized plasmon resonances wavelength which can be associated thereto. The nanowires array constitutes an electrode of an improved photonic device. | 01-06-2011 |
20110006280 | QUANTUM-DOT DEVICE AND POSITION-CONTROLLED QUANTUM-DOT-FABRICATION METHOD - The present invention relates to a method for position-controlled fabrication of a semiconductor quantum dot, the method comprising: providing a substrate ( | 01-13-2011 |
20110012085 | METHODS OF MANUFACTURE OF VERTICAL NANOWIRE FET DEVICES - A vertical Field Effect Transistor (FET) comprising a vertical semiconductor nanowire is formed by the following steps. Create a columnar pore in a bottom dielectric layer formed on a bottom electrode. Fill the columnar pore by plating a vertical semiconductor nanowire having a bottom end contacting the bottom electrode. The semiconductor nanowire forms an FET device with a FET channel region between a source region and a drain region formed in distal ends of the vertical semiconductor nanowire. Form a gate dielectric layer around the channel region of the vertical semiconductor nanowire and then form a gate electrode around the gate dielectric layer. Form a top electrode contacting a top end of the vertical semiconductor nanowire. | 01-20-2011 |
20110012086 | NANOSTRUCTURED FUNCTIONAL COATINGS AND DEVICES - In one aspect of the present invention, an article including a nanostructured functional coating disposed on a substrate is described. The functional coating is characterized by both anti-reflection properties and down-converting properties. Related optoelectronic devices are also described. | 01-20-2011 |
20110024717 | METHOD FOR PREFERENTIAL GROWTH OF SEMICONDUCTING VERTICALLY ALIGNED SINGLE WALLED CARBON NANOTUBES - A method and system for the preferential growth of semiconducting vertically-aligned single-walled carbon nanotubes (VA-SWNTs) is provided. The method combines the use of plasma-enhanced chemical vapor deposition at low pressure with rapid heating. The method provides a high yield of up to approximately 96% semiconducting SWNTs in the VA-SWNT array. The as-synthesized semiconducting SWNTs can be used directly for fabricating field effect transistor (FET) devices without the need for any post-synthesis purification or separation. | 02-03-2011 |
20110024718 | Nanowire Synthesis - A noble metal nanoparticle can be grown on a semiconductor substrate by contacting a predetermined region of the substrate with a solution including noble metal ions. The predetermined region of the semiconductor substrate can be exposed by applying a polymeric layer over the substrate selectively removing a portion of the polymeric layer. The nanoparticles can be prepared in a predetermined pattern. Nanowires having a predetermined diameter and a predetermined position can be grown from the nanoparticles. | 02-03-2011 |
20110024719 | LARGE SCALE NANOELEMENT ASSEMBLY METHOD FOR MAKING NANOSCALE CIRCUIT INTERCONNECTS AND DIODES - Nanoelements such as single walled carbon nanotubes are assembled in three dimensions into a nanoscale template on a substrate by means of electrophoresis and dielectrophoresis at ambient temperature. The current-voltage relation indicates that strong substrate-nanotube interconnects carrying mA currents are established inside the template pores. The method is suitable for large-scale, rapid, three-dimensional assembly of 1,000,000 nanotubes per square centimeter area using mild conditions. Circuit interconnects made by the method can be used for nanoscale electronics applications. | 02-03-2011 |
20110031470 | METHODS FOR FABRICATING PASSIVATED SILICON NANOWIRES AND DEVICES THUS OBTAINED - Methods for fabricating passivated silicon nanowires and an electronic arrangement thus obtained are described. Such arrangements may comprise a metal-oxide-semiconductor (MOS) structure such that the arrangements may be utilized for MOS field-effect transistors (MOSFETs) or opto-electronic switches. | 02-10-2011 |
20110031471 | Laser-Induced Structuring of Substrate Surfaces - In one aspect, the present invention provides a method of processing a substrate, e.g., a semiconductor substrate, by irradiating a surface of the substrate (or at least a portion of the surface) with a first set of polarized short laser pulses while exposing the surface to a fluid to generate a plurality of structures on the surface, e.g., within a top layer of the surface. Subsequently, the structured surface can be irradiated with another set of polarized short laser pulses having a different polarization than that of the initial set while exposing the structured surface to a fluid, e.g., the same fluid initially utilized to form the structured surface or a different fluid. In many embodiments, the second set of polarized laser pulses cause the surface structures formed by the first set to break up into smaller-sized structures, e.g., nano-sized features such as nano-sized rods. | 02-10-2011 |
20110037048 | Composition Comprising Rare-earth Dielectric - Compositions comprising a single-phase rare-earth dielectric disposed on a substrate. Embodiments of the present invention provide the basis for high-K gate dielectrics in conventional integrated circuits and high-K buried dielectrics as part of a semiconductor-on-insulator wafer structure. | 02-17-2011 |
20110042641 | BRANCHED NANOSCALE WIRES - The present invention generally relates to nanotechnology and, in particular, to branched nanoscale wires cases, the branched nanoscale wires may be produced using vapor-phase and/or solution-phase synthesis. Branched nanoscale wires may be grown by depositing nanoparticles onto a nanoscale wire, and segments or “branches” can then be grown from the nanoparticles. The nanoscale wire may be any nanoscale wire, for example, a semiconductor nanoscale wire, a nanoscale wire having a core and a shell. The segments may be of the same, or of different materials, than the nanoscale wire, for example, semiconductor/metal, semiconductor/semiconductor. The junction between the segment and the nanoscale wire, in some cases, is epitaxial. In one embodiment, the nanoparticles are adsorbed onto the nanoscale wire by immobilizing a positively-charged entity, such as polylysine, to the nanoscale wire, and exposing it to the nanoparticles. In another embodiment, nanoparticles are deposited onto a nanoscale wire by etching the nanoscale wire to produce an H-terminated surface, then exposing the surface to a solution comprising a metal ion, which be reduced by the surface to form nanoparticles. Segments or branches can then be grown from the deposited nanoparticles to the branched nanoscale wire. | 02-24-2011 |
20110042642 | METHOD FOR PRODUCING NANOSTRUCTURES ON METAL OXIDE SUBSTRATE, METHOD FOR DEPOSITING THIN FILM ON SAME, AND THIN FILM DEVICE - A method for producing nanostructures ( | 02-24-2011 |
20110057163 | NANO-WIRE FIELD EFFECT TRANSISTOR, METHOD FOR MANUFACTURING THE TRANSISTOR, AND INTEGRATED CIRCUIT INCLUDING THE TRANSISTOR - Provided is a method for fabricating a nano-wire field effect transistor including steps of: preparing a nano-wire field effect transistor including two columnar members made of a silicon crystal configuring a nano-wire on a substrate are arranged on a substrate in parallel and one above the other, and an SOI substrate having a (100) surface orientation; processing a silicon crystal layer configuring the SOI substrate into a standing plate-shaped member having a rectangular cross-section; processing the silicon crystal by orientation dependent wet etching and thermal oxidation into a shape where two triangular columnar members are arranged one above the other with a spacing from each other as to face along the ridge lines of the triangular columnar members; and processing the triangular columnar member into a circular columnar member configuring a nano-wire by hydrogen-annealing or a thermal oxidation; and an integrated circuit including the transistor. | 03-10-2011 |
20110062410 | METHOD FOR MORPHOLOGICAL CONTROL AND ENCAPSULATION OF MATERIALS FOR ELECTRONICS AND ENERGY APPLICATIONS - An electronic device comprises a drawn glass tube having opposing ends, a semiconductive material disposed inside of the drawn glass tube, and a first electrode and a second electrode disposed at the opposing ends of the drawn glass tube. A method of making an electrical device comprises disposing a semiconductive material inside of a glass tube, and drawing the glass tube with the semiconductive material disposed therein to form a drawn glass tube. The method of making an electrical device also comprises disposing a first electrode and a second electrode on the opposing ends of the drawn glass tube to form an electric device. | 03-17-2011 |
20110062411 | MOSFET with a Nanowire Channel and Fully Silicided (FUSI) Wrapped Around Gate - Nanowire-channel metal oxide semiconductor field effect transistors (MOSFETs) and techniques for the fabrication thereof are provided. In one aspect, a MOSFET includes a nanowire channel; a fully silicided gate surrounding the nanowire channel; and a raised source and drain connected by the nanowire channel. A method of fabricating a MOSFET is also provided. | 03-17-2011 |
20110068320 | QUANTUM WELL GRAPHENE STRUCTURE - An electronic device employing a graphene layer as a charge carrier layer. The graphene layer is sandwiched between layers that are constructed of a material having a highly ordered crystalline structure and a high dielectric constant. The highly ordered crystalline structure of the layers surrounding the graphene layer has low density of charged defects that can lead to scattering of charge carriers in the graphene layer. The high dielectric constant of the layers surrounding the graphene layer also prevents charge carrier scattering by minimizing interaction between the charge carriers and the charged defects in the surrounding layers. An interracial layer constructed of a thin, non-polar, dielectric material can also be provided between the graphene layer and each of the highly ordered crystalline high dielectric constant layers to minimize charge carrier scattering in the graphene layer through remote interfacial phonons. | 03-24-2011 |
20110073834 | ACTIVATION OF GRAPHENE BUFFER LAYERS ON SILICON CARBIDE BY ULTRA LOW TEMPERATURE OXIDATION - A method of electrically activating a structure having one or more graphene layers formed on a silicon carbide layer includes subjecting the structure to an oxidation process so as to form a silicon oxide layer disposed between the silicon carbide layer and a bottommost of the one or more graphene layers, thereby electrically activating the bottommost graphene layer. | 03-31-2011 |
20110073835 | SEMICONDUCTOR NANOCRYSTAL FILM - A film comprised of semiconductor nanocrystals having an aspect ratio less than 3:1 and a diameter greater than 10 nanometers, wherein the film has less than 5% by volume of organic material. | 03-31-2011 |
20110073836 | High Power Density Photo-electronic and Photo-voltaic Materials and Methods of Making - A high power density photo-electronic and photo-voltaic material comprising a bio-inorganic nanophotoelectronic material with a photosynthetic reaction center protein encapsulated inside a multi-wall carbon nanotube or nanotube array. The array can be on an electrode. The photosynthetic reaction center protein can be immobilized on the electrode surface and the protein molecules can have the same orientation. A method of making a high power density photo-electronic and photo-voltaic material comprising the steps of immobilizing a bio-inorganic nanophotoelectronic material with a photosynthetic reaction center protein inside a carbon nanotube, wherein the immobilizing is by passive diffusion, wherein the immobilizing can include using an organic linker. | 03-31-2011 |
20110108795 | Molecular devices and methods of manufacturing the same - Molecular devices and methods of manufacturing the molecular device are provided. The molecular device may include a lower electrode on a substrate and a self-assembled monolayer on the lower electrode. After an upper electrode is formed on the self-assembled monolayer, the self-assembled monolayer may be removed to form a gap between the lower electrode and the upper electrode. A functional molecule having a functional group may be injected into the gap. | 05-12-2011 |
20110114914 | FIELD EFFECT TRANSISTOR AND CIRCUIT DEVICE - An end portion ( | 05-19-2011 |
20110121257 | Growth of Single Crystal Nanowires - A diode is provided which comprises a cathode, an anode, and at least one crystalline nanowire in electrical communication with said cathode and said anode. The crystalline nanowire comprises a group IV metal which is substantially straight and substantially free of nanoparticles. | 05-26-2011 |
20110121258 | RECTIFYING ANTENNA DEVICE WITH NANOSTRUCTURE DIODE - A rectifying antenna device is disclosed. The device comprises a pair of electrode structures, and at least one nanostructure diode contacting at least a first electrode structure of the pair and being at least in proximity to a second electrode structure of the pair. At least one electrode structure of the pair receives AC radiation, and the nanostructure diode(s) at least partially rectifies a current generated by the AC radiation. | 05-26-2011 |
20110127488 | USES OF A CARBON NANOBUD MOLECULE AND DEVICES COMPRISING THE SAME - A carbon nanobud molecule ( | 06-02-2011 |
20110133153 | POROUS NANOSTRUCTURE AND METHOD OF MANUFACTURING THE SAME - Provided are a porous nanostructure and a method of manufacturing the same. The porous nanostructure includes a plurality of pores disposed on an exterior surface of a nanostructure, wherein at least a portion of the plurality of pores extend inside the nanostructure. | 06-09-2011 |
20110140071 | NANO-SPHERICAL GROUP III-NITRIDE MATERIALS - Nano-spherical group III-nitride materials and methods of forming nano-spherical group III-nitride materials are described. Also described is a 1-dimensional LED or similar device formed from a single nano-rod of a nano-spherical group III-nitride material. | 06-16-2011 |
20110140072 | DEFECT-FREE GROUP III - NITRIDE NANOSTRUCTURES AND DEVICES USING PULSED AND NON-PULSED GROWTH TECHNIQUES - Exemplary embodiments provide semiconductor devices including high-quality (i.e., defect free) Group III—Nitride nanostructures and uniform Group III—Nitride nanostructure arrays as well as their scalable processes for manufacturing, where the position, orientation, cross-sectional features, length and the crystallinity of each nanostructure can be precisely controlled. A pulsed growth mode can be used to fabricate the disclosed Group III—Nitride nanostructures and/or nanostructure arrays providing a uniform length of about 0.01-20 micrometers (μm) with constant cross-sectional features including an exemplary diameter of about 10 nanometers (nm)-500 micrometers (μm). Furthermore, core-shell nanostructure/MQW active structures can be formed by a core-shell growth on the non-polar sidewalls of each nanostructure and can be configured in nanoscale photoelectronic devices such as nanostructure LEDs and/or nanostructure lasers to provide tremendously-high efficiencies. Additional growth mode transitions from the pulsed to the non-pulsed growth mode and subsequent transitions from non-pulsed to pulsed growth mode are employed in order to incorporate certain group III—Nitride compounds more efficiently into the nanostructures and form devices of the designed shape, morphology and stochiometric composition. In addition, high-quality group III—Nitride substrate structures can be formed by coalescing the plurality of group III—Nitride nanostructures and/or nanostructure arrays to facilitate the fabrication of visible LEDs and lasers. | 06-16-2011 |
20110147697 | Isolation for nanowire devices - The present disclosure relates to the field of fabricating microelectronic devices. In at least one embodiment, the present disclosure relates to forming an isolated nanowire, wherein isolation structure adjacent the nanowire provides a substantially level surface for the formation of microelectronic structures thereon. | 06-23-2011 |
20110155995 | Vertically Oriented Nanostructure and Fabricating Method Thereof - A vertically oriented nanometer-wires structure is disclosed. The vertically oriented nanometer-wires structure includes a non-crystalline base and many straight nanometer-wires. The straight nanometer-wires are uniformly distributed on the non-crystalline base, and the angle between each of the straight nanometer-wire and the non-crystalline base is 80-90 degrees. The straight nanometer-wires structure can be widely applied in semiconductor, optoelectronic, biological and energy field. What is worth to be noticed is that the non-crystalline base can be glass, ceramics, synthetic, resin, rubber or even metal foil, and the straight nanometer-wires and the non-crystalline base are still orthogonal to each other. | 06-30-2011 |
20110155996 | BISTABLE CARBAZOLE COMPOUNDS - Bistable carbazole compounds of formula (I) | 06-30-2011 |
20110163289 | STRUCTURE AND METHOD OF FORMING BURIED-CHANNEL GRAPHENE FIELD EFFECT DEVICE - A novel buried-channel graphene device structure and method for manufacture. The new structure includes a two level channel layer comprised of a buried-channel graphene layer with an amorphous silicon top channel layer. The method for making such structure includes the steps of depositing a graphene layer on a substrate, depositing an amorphous silicon layer on the graphene layer, converting the upper layer of the amorphous silicon layer to a gate dielectric by nitridation, oxidation or oxynitridation, while keeping the lower layer of the amorphous silicon layer to serve as part of the channel to form the buried-channel graphene device. | 07-07-2011 |
20110163290 | METHODS FOR PASSIVATING A CARBONIC NANOLAYER - Methods for passivating a carbonic nanolayer (that is, material layers comprised of low dimensional carbon structures with delocalized electrons such as carbon nanotubes and nano-scopic graphene flecks) to prevent or otherwise limit the encroachment of another material layer are disclosed. In some embodiments, a sacrificial material is implanted within a porous carbonic nanolayer to fill in the voids within the porous carbonic nanolayer while one or more other material layers are applied over or alongside the carbonic nanolayer. Once the other material layers are in place, the sacrificial material is removed. In other embodiments, a non-sacrificial filler material (selected and deposited in such a way as to not impair the switching function of the carbonic nanolayer) is used to form a barrier layer within a carbonic nanolayer. In other embodiments, carbon structures are combined with and nanoscopic particles to limit the porosity of a carbonic nanolayer. | 07-07-2011 |
20110163291 | SOLID STATE MATERIAL - A solid state system comprising a host material and a quantum spin defect, wherein the quantum spin defect has a T | 07-07-2011 |
20110168968 | FLUIDIC NANOTUBES AND DEVICES - Fluidic nanotube devices are described in which a hydrophilic, non-carbon nanotube, has its ends fluidly coupled to reservoirs. Source and drain contacts are connected to opposing ends of the nanotube, or within each reservoir near the opening of the nanotube. The passage of molecular species can be sensed by measuring current flow (source-drain, ionic, or combination). The tube interior can be functionalized by joining binding molecules so that different molecular species can be sensed by detecting current changes. The nanotube may be a semiconductor, wherein a tubular transistor is formed. A gate electrode can be attached between source and drain to control current flow and ionic flow. By way of example an electrophoretic array embodiment is described, integrating MEMs switches. A variety of applications are described, such as: nanopores, nanocapillary devices, nanoelectrophoretic, DNA sequence detectors, immunosensors, thermoelectric devices, photonic devices, nanoscale fluidic bioseparators, imaging devices, and so forth. | 07-14-2011 |
20110180776 | OPTOELECTRONIC DEVICE BASED ON NANOWIRES AND CORRESPONDING PROCESSES - The invention relates to a method for making optoelectronic devices comprising nanowire semiconductors, in which: the nanowires ( | 07-28-2011 |
20110180777 | METHOD OF PLACING A SEMICONDUCTING NANOSTRUCTURE AND SEMICONDUCTOR DEVICE INCLUDING THE SEMICONDUCTING NANOSTRUCTURE - A semiconductor device includes a bonding surface, a semiconducting nanostructure including one of a nanowire and a nanocrystal, which is formed on the bonding surface, and a source electrode and a drain electrode which are formed on the nanostructure such that the nanostructure is electrically connected to the source and drain electrodes. | 07-28-2011 |
20110186804 | NANOSCALE CHEMICAL TEMPLATING WITH OXYGEN REACTIVE MATERIALS - A method of fabricating templated semiconductor nanowires on a surface of a semiconductor substrate for use in semiconductor device applications is provided. The method includes controlling the spatial placement of the semiconductor nanowires by using an oxygen reactive seed material. The present invention also provides semiconductor structures including semiconductor nanowires. In yet another embodiment, patterning of a compound semiconductor substrate or other like substrate which is capable of forming a compound semiconductor alloy with an oxygen reactive element during a subsequent annealing step is provided. This embodiment provides a patterned substrate that can be used in various applications including, for example, in semiconductor device manufacturing, optoelectronic device manufacturing and solar cell device manufacturing. | 08-04-2011 |
20110186805 | Doped graphene electronic materials - A graphene substrate is doped with one or more functional groups to form an electronic device. | 08-04-2011 |
20110186806 | Doped graphene electronic materials - A graphene substrate is doped with one or more functional groups to form an electronic device. | 08-04-2011 |
20110186807 | Doped graphene electronic materials - A graphene substrate is doped with one or more functional groups to form an electronic device. | 08-04-2011 |
20110186808 | METHODS OF FORMING CATALYTIC NANOPADS - Carbon nanotube (CNT)-based devices and technology for their fabrication are disclosed. The planar, multiple layer deposition technique and simple methods of change of the nanotube conductivity type during the device processing are utilized to provide a simple and cost effective technology for large scale circuit integration. Such devices as p-n diode, CMOS-like circuit, bipolar transistor, light emitting diode and laser are disclosed, all of them are expected to have superior performance then their semiconductor-based counterparts due to excellent CNT electrical and optical properties. When fabricated on semiconductor wafers, the CNT-based devices can be combined with the conventional semiconductor circuit elements, thus producing hybrid devices and circuits. | 08-04-2011 |
20110186809 | NANOTUBE ARRAY LIGHT EMITTING DIODES AND LASERS - Carbon nanotube (CNT)-based devices and technology for their fabrication are disclosed. The planar, multiple layer deposition technique and simple methods of change of the nanotube conductivity type during the device processing are utilized to provide a simple and cost effective technology for large scale circuit integration. Such devices as p-n diode, CMOS-like circuit, bipolar transistor, light emitting diode and laser are disclosed, all of them are expected to have superior performance then their semiconductor-based counterparts due to excellent CNT electrical and optical properties. When fabricated on semiconductor wafers, the CNT-based devices can be combined with the conventional semiconductor circuit elements, thus producing hybrid devices and circuits. | 08-04-2011 |
20110193052 | THREE-DIMENSIONAL NANODEVICES INCLUDING NANOSTRUCTURES - Provided are three-dimensional (3D) nanodevices including 3D nanostructures. The 3D nanodevice includes at least one nanostructure, each nanostructure including an oscillation portion floating over a substrate and support portions for supporting both lengthwise end portions of the oscillation portion, supports disposed on the substrate to support the support portions of each of the nanostructures, at least one controller disposed at an upper portion of the substrate, a lower portion of the substrate, or both the upper and lower portions of the substrate to control each of the nanostructures, and a sensing unit disposed on each of the oscillation portions to sense an externally supplied adsorption material. Thus, unlike in a typical planar device, generation of impurities between a nanodevice and a substrate can be reduced, and mechanical vibration can be caused. In particular, since 3D nanostructures have mechanical and electrical characteristics, 3D nanodevices including new 3D nanostructures can be provided using nano-electro-mechanical systems (NEMS). Also, a single electron device, a spin device, or a single electron transistor (SET)-field effect transistor (FET) hybrid device can be formed using a simple process unlike in planar devices. | 08-11-2011 |
20110193053 | METHOD FOR MAKING SIDE GROWTH SEMICONDUCTOR NANOWIRES AND TRANSISTORS OBTAINED BY SAID METHOD - A method of fabricating semiconductor nanowires ( | 08-11-2011 |
20110193054 | DEPOSITION OF MATERIALS - The method utilises a conducting trench base with non-conducting trench walls to corral charged particles precisely into the trenches. The nanoparticles are close packed in the channels and highly ordered. This approach utilises the charge on the particles to selectively deposit them within the trenches, as all nanoparticles in solution can be charged, and this can be extended to any nanoparticle system beyond gold. Also, this method results in the layer-by-layer growth of the gold nanoparticles. Therefore the depth of the nanoparticle layers within the trenches is controllable. This allows the possibility of heterolayered structures of different nanoparticle layers. Further this method ensures that assembly occurs to fill the void space available provided the back-contacting electrode is more conducting than the trench walls. This allows nanoparticle assemblies to be corralled into any lithographically defined shape, which makes this approach highly adaptable to a range of applications | 08-11-2011 |
20110198558 | GRAPHENE CIRCUIT BOARD HAVING IMPROVED ELECTRICAL CONTACT BETWEEN GRAPHENE AND METAL ELECTRODE, AND DEVICE INCLUDING SAME - A circuit board having a graphene circuit according to the present invention includes: a base substrate; a patterned aluminum oxide film formed on the base substrate, the patterned aluminum oxide film having an average composition of Al | 08-18-2011 |
20110198559 | CNT DEVICES, LOW-TEMPERATURE FABRICATION OF CTN AND CNT PHOTO-RESISTS - A method is provided for growth of carbon nanotube (CNT) synthesis at a low temperature. The method includes preparing a catalyst by placing the catalyst between two metal layers of high chemical potential on a substrate, depositing such placed catalyst on a surface of a wafer, and reactivating the catalyst in a high vacuum at a room temperature in a catalyst preparation chamber to prevent a deactivation of the catalyst. The method also includes growing carbon nanotubes on the substrate in the high vacuum in a CNT growth chamber after preparing the catalyst. | 08-18-2011 |
20110204317 | Electric energy generator - An electric energy generator may include a semiconductor layer and a plurality of nanowires having piezoelectric characteristics. The electric energy generator may convert optical energy into electric energy if external light is applied and may generate piezoelectric energy if external pressure (e.g., sound or vibration) is applied. | 08-25-2011 |
20110204318 | FORMATION OF CARBON AND SEMICONDUCTOR NANOMATERIALS USING MOLECULAR ASSEMBLIES - The invention is directed to a method of forming carbon nanomaterials or semiconductor nanomaterials. The method comprises providing a substrate and attaching a molecular precursor to the substrate. The molecular precursor includes a surface binding group for attachment to the substrate and a binding group for attachment of metal-containing species. The metal-containing species is selected from a metal cation, metal compound, or metal or metal-oxide nanoparticle to form a metallized molecular precursor. The metallized molecular precursor is then subjected to a heat treatment to provide a catalytic site from which the carbon nanomaterials or semiconductor nanomaterials form. The heating of the metallized molecular precursor is conducted under conditions suitable for chemical vapor deposition of the carbon nanomaterials or semiconductor nanomaterials. | 08-25-2011 |
20110204319 | FULLERENE-DOPED NANOSTRUCTURES AND METHODS THEREFOR - Nanostructures are doped to set conductivity characteristics. In accordance with various example embodiments, nanostructures such as carbon nanotubes are doped with a halogenated fullerene type of dopant material. In some implementations, the dopant material is deposited from solution or by vapor deposition, and used to dope the nanotubes to increase the thermal and/or electrical conductivity of the nanotubes. | 08-25-2011 |
20110204320 | METHODS OF FORMING SEMICONDUCTOR DEVICES AND DEVICES FORMED USING SUCH METHODS - Single source precursors are subjected to carbon dioxide to form particles of material. The carbon dioxide may be in a supercritical state. Single source precursors also may be subjected to supercritical fluids other than supercritical carbon dioxide to form particles of material. The methods may be used to form nanoparticles. In some embodiments, the methods are used to form chalcopyrite materials. Devices such as, for example, semiconductor devices may be fabricated that include such particles. Methods of forming semiconductor devices include subjecting single source precursors to carbon dioxide to form particles of semiconductor material, and establishing electrical contact between the particles and an electrode. | 08-25-2011 |
20110204321 | METHOD FOR PRODUCING NANOWIRES USING A POROUS TEMPLATE - Disclosed herein is a method for producing nanowires. The method comprises the steps of providing a porous template with a plurality of holes in the form of tubes, filling the tubes with nanoparticles or nanoparticle precursors, and forming the filled nanoparticles or nanoparticle precursors into nanowires. According to the method, highly rectilinear and well-ordered nanowires can be produced in a simple manner. | 08-25-2011 |
20110210308 | LAYERS AND PATTERNS OF NANOWIRE OR CARBON NANOTUBE USING CHEMICAL SELF ASSEMBLY AND FABRICATING METHOD IN LIQUID CRYSTAL DISPLAY DEVICE THEREBY - Disclosed are layers and patterns of nanowire or nanotube using a chemical self assembly for forming a semiconductor layer and a conductive layer of a thin film transistor by using a nanowire and/or nanotube solution and an diamine-based self-assembled monolayer (SAM) material. The Layers and patterns including layers and patterns of nanowire or nanotube using a chemical self assembly include: a substrate having a surface terminated with amine group (—NH | 09-01-2011 |
20110210309 | TUBULAR NANOSTRUCTURES, PROCESSES OF PREPARING SAME AND DEVICES MADE THEREFROM - Novel methods of producing single-walled and multi-walled, single-crystalline, tubular nanostructures, made of an inorganic substance (e.g., silicon), and single-walled and multi-walled, single-crystalline, tubular nanostructures produced thereby, are disclosed. Also disclosed are devices into which the nanostructures are integrated. The methods described herein are used to reproducibly and controllably producing single-crystalline nanostructures with well-defined shape, diameter and/or interwall distance, chemical composition and morphology. | 09-01-2011 |
20110215289 | ULTRAHIGH DENSITY PATTERNING OF CONDUCTING MEDIA - A reconfigurable device and a method of creating, erasing, or reconfiguring the device are provided. At an interface between a first insulating layer and a second insulating layer, an electrically conductive, quasi one- or zero-dimensional electron gas is present such that the interface presents an electrically conductive region that is non-volatile. The second insulating layer is of a thickness to allow metal-insulator transitions upon the application of a first external electric field. The electrically conductive region is subject to erasing upon application of a second external electric field. | 09-08-2011 |
20110233512 | VERTICAL INTEGRATED SILICON NANOWIRE FIELD EFFECT TRANSISTORS AND METHODS OF FABRICATION - Vertical integrated field effect transistor circuits and methods are described which are fabricated from Silicon, Germanium, or a combination Silicon and Germanium based on nanowires grown in place on the substrate. By way of example, vertical integrated transistors are formed from one or more nanowires which have been insulated, had a gate deposited thereon, and to which a drain is coupled to the exposed tips of one or more of the nanowires. The nanowires are preferably grown over a surface or according to a desired pattern in response to dispersing metal nanoclusters over the desired portions of the substrate. In one preferred implementation, SiCl | 09-29-2011 |
20110233513 | ENHANCED BONDING INTERFACES ON CARBON-BASED MATERIALS FOR NANOELECTRONIC DEVICES - Semiconductor structures and electronic devices are provided that includes at least one layer of an interfacial dielectric material located on an upper surface of a carbon-based material. The at least one layer of interfacial dielectric material has a short-range crystallographic bonding structure, typically hexagonal, that is the same as that of the carbon-based material and, as such, the at least one layer of interfacial dielectric material does not change the electronic structure of the carbon-based material. The presence of the at least one layer of interfacial dielectric material having the same short-range crystallographic bonding structure as that of the carbon-based material improves the interfacial bonding between the carbon-based material and any overlying material layer, including a dielectric material, a conductive material or a combination of a dielectric material and a conductive material. The improved interfacial bonding in turn facilitates formation of devices including a carbon-based material. | 09-29-2011 |
20110240953 | INTEGRATED SEMICONDUCTOR NANOWIRE DEVICE - A method of making a semiconductor nanowire device includes providing a plurality of spaced semiconductor nanowires on a growth substrate; applying a dielectric material so that it is disposed between the semiconductor nanowires producing a layer of embedded semiconductor nanowires having a top surface opposed to a bottom surface, wherein the bottom surface is defined by the interface with the growth substrate; depositing a first electrode over the top surface of the layer of embedded semiconductor nanowires so that it is in electrical contact with the semiconductor nanowires; joining the first electrode to a device substrate; removing the growth substrate and exposing the bottom surface of the layer of embedded semiconductor nanowires; and depositing a second electrode on the bottom surface of the layer of embedded semiconductor nanowires so that it is in electrical contact with the semiconductor nanowires. | 10-06-2011 |
20110240954 | SILICON NANOWIRE COMPRISING HIGH DENSITY METAL NANOCLUSTERS AND METHOD OF PREPARING THE SAME - A silicon nanowire includes metal nanoclusters formed on a surface thereof at a high density. The metal nanoclusters improve electrical and optical characteristics of the silicon nanowire, and thus can be usefully used in various electrical devices such as a lithium battery, a solar cell, a bio sensor, a memory device, or the like. | 10-06-2011 |
20110253969 | Narrow Graphene Nanoribbons from Carbon Nanotubes - Disclosed is a method for making graphene nanoribbons (GNRs) by controlled unzipping of structures such as carbon nanotubes (CNTs) by etching (e.g., argon plasma etching) of nanotubes partly embedded in a polymer film. The GNRs have smooth edges and a narrow width distribution (2-20 nm). Raman spectroscopy and electrical transport measurements reveal the high quality of the GNRs. Such a method of unzipping CNTs with well-defined structures in an array will allow the production of GNRs with controlled widths, edge structures, placement and alignment in a scalable fashion for device integration. GNRs may be formed from nanostructures in a controlled array to form arrays of parallel or overlapping structures. Also disclosed is a method in which the CNTs are in a predetermined pattern that is carried over and transferred to a substrate for forming into a semiconductor device. | 10-20-2011 |
20110253970 | Transparent nanowire transistors and methods for fabricating same - Disclosed are fully transparent nanowire transistors having high field-effect mobilities. The fully transparent nanowire transistors disclosed herein include one or more nanowires, a gate dielectric prepared from a transparent inorganic or organic material, and transparent source, drain, and gate contacts fabricated on a transparent substrate. The fully transparent nanowire transistors disclosed herein also can be mechanically flexible. | 10-20-2011 |
20110253971 | Photo-Receptor for Electro-Magnetic Radiation Collection - An underwater data transmission system including arrays of nano-meter scaled photon emitters and sensors on an outer surface of an underwater platform. For the emitters, a laser is pulsed to correlate with data packets, providing a beam of photons at a prescribed frequency. Nano-scaled collecting lenses channel the incoming photons to photo-receptors located at a focal plane for the frequency at the base of each lens. A coating on the lenses absorbs photons at the frequency that are not aligned with the longitudinal axes of the lenses or tubes. Nano-wires connect the photo-receptors to a light intensity integrator. The integrator integrates the intensity over a surface area. The output of the integrator is fed to a signal processor to track and process the arriving digital packets. | 10-20-2011 |
20110260136 | Semiconductor Devices Including a Transistor With Elastic Channel - A semiconductor device that may control a formation of a channel is disclosed. The semiconductor device includes a gate region including a first area, an insulating layer disposed on portions of a top surface of the gate region corresponding to both ends portions of the first area, first and second electrodes formed on the insulating layer to be spaced apart from each other, an elastic conductive layer disposed between the first and second electrodes and the insulating layer and having a shape that varies according to an electrostatic force based on voltages applied to the first electrode, the second electrode, and the gate region, and a gate insulating region disposed between the elastic conductive layer and the first area of the gate region. | 10-27-2011 |
20110266517 | PEPTIDE NANOSTRUCTURES ENCAPSULATING A FOREIGN MATERIAL AND METHOD OF MANUFACTURING SAME - A composition comprising a material at least partially enclosed by a tubular, spherical or planar nanostructure composed of a plurality of peptides, wherein each of the plurality of peptides includes no more than 4 amino acids and whereas at least one of the 4 amino acids is an aromatic amino acid. | 11-03-2011 |
20110278533 | DOUBLE GYROID STRUCTURE NANOPOROUS FILMS AND NANOWIRE NETWORKS - A method of forming a nanoporous film is disclosed. The method comprises forming a coating solution including clusters, surfactant molecules, a solvent, and one of an acid catalyst and a base catalyst. The clusters comprise inorganic groups. The method further comprises aging the coating solution for a time period to select a predetermined phase that will self-assemble and applying the coating solution on a substrate. The method further comprises evaporating the solvent from the coating solution and removing the surfactant molecules to yield the nanoporous film. | 11-17-2011 |
20110278534 | OPTOELECTRONIC DEVICES UTILIZING MATERIALS HAVING ENHANCED ELECTRONIC TRANSITIONS - An optoelectronic device that includes a material having enhanced electronic transitions. The electronic transitions are enhanced by mixing electronic states at an interface. The interface may be formed by a nano-well, a nano-dot, or a nano-wire. | 11-17-2011 |
20110278535 | Incorporation of Functionalizing Molecules in Nano-Patterned Epitaxial Graphene Electronics - In a method of making graphite devices, a thin-film graphitic layer disposed against a preselected face of a substrate is created on the preselected face of the substrate. A preselected pattern is generated on the thin-film graphitic layer. At least one functionalizing molecule is attached to a portion of the graphitic layer. The molecule is capable of interacting with π bands in the graphitic layer. | 11-17-2011 |
20110284818 | Graphene Channel-Based Devices and Methods for Fabrication Thereof - Graphene-channel based devices and techniques for the fabrication thereof are provided. In one aspect, a semiconductor device includes a first wafer having at least one graphene channel formed on a first substrate, a first oxide layer surrounding the graphene channel and source and drain contacts to the graphene channel that extend through the first oxide layer; and a second wafer having a CMOS device layer formed in a second substrate, a second oxide layer surrounding the CMOS device layer and a plurality of contacts to the CMOS device layer that extend through the second oxide layer, the wafers being bonded together by way of an oxide-to-oxide bond between the oxide layers. One or more of the contacts to the CMOS device layer are in contact with the source and drain contacts. One or more other of the contacts to the CMOS device layer are gate contacts for the graphene channel. | 11-24-2011 |
20110284819 | QUANTUM DOT LIGHT EMITTING ELEMENT AND METHOD FOR MANUFACTURING THE SAME - The present invention relates to a quantum dot light emitting element which can form a quantum light emitting layer configured of charge transporting particles and quantum dots and a charge transporting layer in a solution process, to reduce process expense, and a method for manufacturing the same. The quantum dot light emitting element includes a substrate, an anode formed on the substrate, a quantum light emitting layer formed on the anode, the quantum light emitting layer having charge transporting particles and quantum dots mixed therein, and a cathode formed on the quantum light emitting layer. | 11-24-2011 |
20110284820 | NANOWIRES ON SUBSTRATE SURFACES, METHOD FOR PRODUCING SAME AND USE THEREOF - The invention relates to a method for producing anchored nanowires on substrate surfaces. A method for producing anchored nanowires on a substrate which comprises no deposition steps from the gas phase with the steps:
| 11-24-2011 |
20110291068 | FIELD EFFECT TRANSISTOR MANUFACTURING METHOD, FIELD EFFECT TRANSISTOR, AND SEMICONDUCTOR GRAPHENE OXIDE MANUFACTURING METHOD - A semiconductor device is provided and includes a conductive substrate, an insulating film formed on the conductive substrate, a base layer including amino groups, and a reduced graphene oxide layer formed on the base layer. | 12-01-2011 |
20110297913 | NANOSTRUCTURE OPTOELECTRONIC DEVICE HAVING SIDEWALL ELECTRICAL CONTACT - Nanostructure array optoelectronic devices are disclosed. The optoelectronic device may have a top electrical contact that is physically and electrically connected to sidewalls of the array of nanostructures (e.g., nanocolumns). The top electrical contact may be located such that light can enter or leave the nanostructures without passing through the top electrical contact. Therefore, the top electrical contact can be opaque to light having wavelengths that are absorbed or generated by active regions in the nanostructures. The top electrical contact can be made from a material that is highly conductive, as no tradeoff needs to be made between optical transparency and electrical conductivity. The device could be a solar cell, LED, photo-detector, etc. | 12-08-2011 |
20110309323 | METHOD OF MANUFACTURING NANO DEVICE BY ARBITRARILY PRINTING NANOWIRE DEVICES THEREON AND INTERMEDIATE BUILDING BLOCK USEFUL FOR THE METHOD - A method of manufacturing a nano device by directly printing a plurality of NW devices in a desired shape on a predesigned gate substrate. The method includes preparing an NW solution, preparing a building block for performing decaling onto the substrate by carrying an NW device, forming the NW device by connecting electrodes of each of building block units of the building block using NWs by dropping the NW solution between the electrodes and then through dielectrophoresis, visually inspecting the numbers of NW bridges that are formed between the electrodes of each of the building block units through the dielectrophoresis, grouping the building block units according to the numbers, and decaling the NW device formed on each of the building block units onto the gate substrate by bringing the grouped building block units into contact with the predesigned gate substrate and then detaching the grouped building block units. | 12-22-2011 |
20110315949 | APPARATUS AND METHOD FOR SENSING PHOTONS - In accordance with an example embodiment of the present invention, an apparatus is provided, including a plurality of photon sensing layers arranged on top of each other, and an intermediate layer between each two adjacent sensing layers, the sensing layers being of graphene, and each intermediate layer being configured to prevent a respective color component of light from proceeding into the photon sensing layer next to it. | 12-29-2011 |
20110315950 | NANOWIRE FET WITH TRAPEZOID GATE STRUCTURE - In one embodiment, a method of providing a nanowire semiconductor device is provided, in which the gate structure to the nanowire semiconductor device has a trapezoid shape. The method may include forming a trapezoid gate structure surrounding at least a portion of a circumference of a nanowire. The first portion of the trapezoid gate structure that is in direct contact with an upper surface of the nanowire has a first width and a second portion of the trapezoid gate structure that is in direct contact with a lower surface of the nanowire has a second width. The second width of the trapezoid gate structure is greater than the first width of the trapezoid gate structure. The exposed portions of the nanowire that are adjacent to the portion of the nanowire that the trapezoid gate structure is surrounding are then doped to provide source and drain regions. | 12-29-2011 |
20110315951 | METHOD FOR FORMING A CATALYST SUITABLE FOR GROWTH OF CARBON NANOTUBES - The present disclosure is related to a method for forming a catalyst nanoparticle on a metal surface, the nanoparticle being suitable for growing a single nanostructure, in particular a carbon nanotube, the method comprising at least the steps of: providing a substrate, having a metal layer on at least a portion of the substrate surface, depositing a sacrificial layer at least on the metal layer, producing a small hole in the sacrificial layer, thereby exposing the metal layer, providing a single catalyst nanoparticle into the hole, removing the sacrificial layer. The disclosure is further related to growing a carbon nanotube from the catalyst nanoparticle. | 12-29-2011 |
20120001149 | FLEXIBLE MICROCAVITIES THROUGH SPIN COATING - A mechanically flexible array of optically pumped vertical cavity surface emitting lasers, fabricated using spin coating. The array uses InGaP colloidal quantum dots as an active medium and alternating polymer layers of different refractive indices as Bragg mirrors. Enhanced spontaneous emission is produced. The flexible array can be peeled off a substrate, producing a flexible structure that can conform to a wide variety of shapes, and having an emission spectrum that can be mechanically tuned. The flexible array can be used to create a flexible infrared light bandage. | 01-05-2012 |
20120001150 | MEMORY CELL THAT EMPLOYS A SELECTIVELY FABRICATED CARBON NANO-TUBE REVERSIBLE RESISTANCE-SWITCHING ELEMENT AND METHODS OF FORMING THE SAME - In some aspects, a method of fabricating a memory cell is provided that includes fabricating a steering element above a substrate, and fabricating a reversible-resistance switching element coupled to the steering element by selectively fabricating carbon nano-tube (“CNT”) material above the substrate, wherein the CNT material comprises a single CNT. Numerous other aspects are provided. | 01-05-2012 |
20120025165 | FLEXIBLE NANOSTRUCTURE ELECTRONIC DEVICES - A flexible electronic device is made up of nanostructures. Specifically, the device includes a flexible substrate, a film of nanostructures in contact with the flexible substrate, a first conducting element in contact with the film of nanostructures, and a second conducting element in contact with the film of nanostructures. The nanostructures may comprise nanotubes, such as carbon nanotubes disposed along the flexible substrate, such as an organic or polymer substrate. The first and second conductive elements may serve as electrical terminals, or as a source and drain. In addition, the electronic device may include a gate electrode that is in proximity to the nanotubes and not in electrical contact with the nanotubes. In this configuration, the device can operate as a transistor or a FET. The device may also be operated in a resistive mode as a chemical sensor (e.g., for sensing NH | 02-02-2012 |
20120025166 | METHOD OF FABRICATING NANOSIZED FILAMENTARY CARBON DEVICES OVER A RELATIVELY LARGE-AREA - Nanosized filamentary carbon structures (CNTs) nucleating over a catalyzed surface may be grown in an up-right direction reaching a second surface, spaced from the first surface, without the need of applying any external voltage source bias. The growth process may be inherently self-stopping, upon reaching a significant population of grown CNTs on the second surface. A gap between the two surfaces may be defined for CNT devices being simultaneously fabricated by common integrated circuit integration techniques. The process includes finding that for separation gaps of up to a hundred or more nanometers, a difference between the respective work functions of the materials delimiting the gap space, for example, different metallic materials or a doped semiconductor of different dopant concentration or type, may produce an electric field intensity orienting the growth of nucleated CNTs from the surface of one of the materials toward the surface of the other material. | 02-02-2012 |
20120037880 | Contacts for Nanowire Field Effect Transistors - A method for forming a nanowire field effect transistor (FET) device includes forming a nanowire over a semiconductor substrate, forming a gate stack around a portion of the nanowire, forming a capping layer on the gate stack, forming a spacer adjacent to sidewalls of the gate stack and around portions of nanowire extending from the gate stack, forming a hardmask layer on the capping layer and the first spacer, forming a metallic layer over the exposed portions of the device, depositing a conductive material over the metallic layer, removing the hardmask layer from the gate stack, and removing portions of the conductive material to define a source region contact and a drain region contact. | 02-16-2012 |
20120056149 | METHODS FOR ADJUSTING THE CONDUCTIVITY RANGE OF A NANOTUBE FABRIC LAYER - Methods for adjusting and/or limiting the conductivity range of a nanotube fabric layer are disclosed. In some aspects, the conductivity of a nanotube fabric layer is adjusted by functionalizing the nanotube elements within the fabric layer via wet chemistry techniques. In some aspects, the conductivity of a nanotube fabric layer is adjusted by functionalizing the nanotube elements within the fabric layer via plasma treatment. In some aspects, the conductivity of a nanotube fabric layer is adjusted by functionalizing the nanotube elements within the fabric layer via CVD treatment. In some aspects, the conductivity of a nanotube fabric layer is adjusted by functionalizing the nanotube elements within the fabric layer via an inert ion gas implant. | 03-08-2012 |
20120056150 | NITRIDE SEMICONDUCTOR LIGHT-EMITTING DEVICE WITH ELECTRODE PATTERN - A nitride semiconductor light-emitting device with an electron pattern that applies current uniformly to an active layer to improve light emission efficiency is provided. The nitride semiconductor light-emitting device includes multiple layers of a substrate, an n-type nitride layer, an active layer of a multi-quantum-well structure, and a p-type nitride layer. The nitride semiconductor light-emitting device further includes a p-electrode pattern and an n-electrode pattern. The p-electrode pattern includes one or more p-pads disposed on the p-type nitride layer, and one or more p-fingers extending from the p-pads. The n-electrode pattern includes one or more n-pads disposed on an exposed region of the n-type nitride layer to correspond to the p-pads, and one or more n-fingers extending from the n-pads. The n-fingers have identical resistance, and the p-fingers have identical resistance to improve current spreading to the active layer. | 03-08-2012 |
20120056151 | Memory Devices, Memory Device Constructions, Constructions, Memory Device Forming Methods, Current Conducting Devices, and Memory Cell Programming Methods - Some embodiments include memory devices having a wordline, a bitline, a memory element selectively configurable in one of three or more different resistive states, and a diode configured to allow a current to flow from the wordline through the memory element to the bitline responsive to a voltage being applied across the wordline and the bitline and to decrease the current if the voltage is increased or decreased. Some embodiments include memory devices having a wordline, a bitline, memory element selectively configurable in one of two or more different resistive states, a first diode configured to inhibit a first current from flowing from the bitline to the wordline responsive to a first voltage, and a second diode comprising a dielectric material and configured to allow a second current to flow from the wordline to the bitline responsive to a second voltage. | 03-08-2012 |
20120068150 | Nanowire Field Effect Transistors - A method for forming a nanowire field effect transistor (FET) device including forming a first silicon on insulator (SOI) pad region, a second SOI pad region, a third SOI pad region, a first SOI portion connecting the first SOI pad region to the second SOI pad region, and a second SOI portion connecting the second SOI pad region to the third SOI pad region on a substrate, patterning a first hardmask layer over the second SOI portion, forming a first suspended nanowire over the semiconductor substrate, forming a first gate structure around a portion of the first suspended nanowire, patterning a second hardmask layer over the first gate structure and the first suspended nanowire, removing the first hardmask layer, forming a second suspended nanowire over the semiconductor substrate, forming a second gate structure around a portion of the second suspended nanowire, and removing the second hardmask layer. | 03-22-2012 |
20120068151 | Light emitting and lasing semiconductor methods and devices - The invention is applicable for use in conjunction with a light-emitting semiconductor structure that includes a semiconductor active region of a first conductivity type containing a quantum size region and having a first surface adjacent a semiconductor input region of a second conductivity type that is operative, upon application of electrical potentials with respect to the active and input regions, to produce light emission from the active region. A method is provided that includes the following steps: providing a semiconductor output region that includes a semiconductor auxiliary layer of the first conductivity type adjacent a second surface, which opposes the first surface of the active region, and providing the auxiliary layer as a semiconductor material having a diffusion length for minority carriers of the first conductivity type material that is substantially shorter than the diffusion length for minority carriers of the semiconductor material of the active region. | 03-22-2012 |
20120068152 | GRAPHENE LIGHT-EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - A graphene light-emitting device and a method of manufacturing the same are provided. The graphene light-emitting device includes a p-type graphene doped with a p-type dopant; an n-type graphene doped with an n-type dopant; and an active graphene that is disposed between the type graphene and the n-type graphene and emits light, wherein the p-type graphene, the n-type graphene, and the active graphene are horizontally disposed. | 03-22-2012 |
20120080658 | Graphene electronic device and method of fabricating the same - A graphene electronic device and a method of fabricating the graphene electronic device are provided. The graphene electronic device may include a graphene channel layer formed on a hydrophobic polymer layer, and a passivation layer formed on the graphene channel layer. The hydrophobic polymer layer may prevent or reduce adsorption of impurities to transferred graphene, and a passivation layer may also prevent or reduce adsorption of impurities to a heat-treated graphene channel layer. | 04-05-2012 |
20120085985 | ELECTRICALLY ACTUATED DEVICE - An electrically actuated device includes a reactive metal layer, a first electrode established in contact with the reactive metal layer, an insulating material layer established in contact with the first electrode or the reactive metal layer, an active region established on the insulating material layer, and a second electrode established on the active region. A conductive nano-channel is formed through a thickness of the insulating material layer. | 04-12-2012 |
20120085986 | GALLIUM NITRIDE-BASED COMPOUND SEMICONDUCTOR LIGHT-EMITTING DIODE - The light-emitting diode element of this invention includes: an n-type GaN substrate ( | 04-12-2012 |
20120091430 | NANOELECTROMECHANICAL SYSTEMS AND METHODS FOR MAKING THE SAME - Nanoelectromechanical systems are disclosed that utilize vertically grown or placed nanometer-scale beams. The beams may be configured and arranged for use in a variety of applications, such as batteries, generators, transistors, switching assemblies, and sensors. In some generator applications, nanometer-scale beams may be fixed to a base and grown to a desired height. The beams may produce an electric potential as the beams vibrate, and may provide the electric potential to an electrical contact located at a suitable height above the base. In other embodiments, vertical beams may be grown or placed on side-by-side traces, and an electrical connection may be formed between the side-by-side traces when beams on separate traces vibrate and contact one another. | 04-19-2012 |
20120091431 | Low Temperature Synthesis of Nanowires in Solution - Methods synthesizing nanowires in solution at low temperatures (e.g., about 400° C. or lower) are provided. In the present methods, the nanowires are synthesized by exposing nanowire precursors to metal nanocrystals in a nanowire growth solution comprising a solvent. The metal nanocrystals serve as seed particles that catalyze the growth of the semiconductor nanowires. The metal nanocrystals may be formed in situ in the growth solution from metal nanocrystal precursors. Alternatively, the nanowires may be pre-formed and added to the growth solution. | 04-19-2012 |
20120091432 | NANOWIRES - An apparatus and a method of manufacturing the apparatus. The apparatus includes a main nanowire and branch nanowires emanating from the main nanowire. The main nanowire may have a first portion and a second portion. The first portion may have a first carrier concentration and the second portion may have a second carrier concentration, different to the first carrier concentration. Each branch nanowire may emanate from the first portion of the main nanowire. Each branch nanowire may emanate from the main nanowire at a substantially fixed distance along a length of the main nanowire. | 04-19-2012 |
20120104354 | LIGHT-EMITTING DIODE - A light-emitting diode includes an n-type nitride semiconductor layer, a multiple quantum well, a p-type nitride semiconductor layer, a window electrode layer, a p-side electrode, and an n-side electrode, which are stacked in this order. The window electrode layer comprises an n-type single-crystalline ITO transparent film and an n-type single-crystalline ZnO transparent film. The p-type nitride semiconductor layer is in contact with the n-type single-crystalline ITO transparent film, the n-type single-crystalline ITO transparent film is in contact with the n-type single-crystalline ZnO transparent film, and the p-side electrode is in connected with the n-type single-crystalline ZnO transparent film. The n-type single-crystalline ITO transparent film contains Ga, a molar ratio of Ga/(In+Ga) being not less than 0.08 and not more than 0.5. Thickness of the n-type single-crystalline ITO transparent film is not less than 1.1 nm and not more than 55 nm. | 05-03-2012 |
20120112157 | NANOWIRE SENSOR WITH ANGLED SEGMENTS THAT ARE DIFFERENTLY FUNCTIONALIZED - A nanowire device includes a nanowire | 05-10-2012 |
20120119182 | SEMICONDUCTOR LIGHT EMITTING DEVICE - Provided is a semiconductor light emitting device. The semiconductor light emitting device comprises a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer. The active layer comprises a first active layer, a second active layer, an electron barrier layer on the first conductive type semiconductor layer. The first active layer and the second active layer comprise a quantum well layer and a quantum barrier layer. The electron barrier layer is formed between the first active layer and the second active layer. The second conductive type semiconductor layer is formed on the active layer. | 05-17-2012 |
20120126197 | Structure and process of basic complementary logic gate made by junctionless transistors - The present invention discloses a structure and process of basic complementary logic gate made by junctionless transistors. Junctionless N-channel transistor(s) and junctionless P-channel transistor(s) are formed on a semiconductor wafer, a conducting contact structure is used to connect the transistors to form a basic complementary logic gate(s) such as inverter, NAND, NOR, etc. | 05-24-2012 |
20120126198 | LIGHT EMITTING DIODE FOR DROOP IMPROVEMENT - A light emitting diode (LED) device structure with a reduced Droop effect, and a method for fabricating the LED device structure. The LED is a III-nitride-based LED having an active layer or emitting layer comprised of a multi-quantum-well (MQW) structure, wherein there are eight or more quantum wells (QWs) in the MQW structure, and more preferably, at least nine QWs in the MQW structure. Moreover, the QWs in the MQW structure are grown at temperatures different from barrier layers in the MQW structure, wherein the barrier layers in the MQW structure are grown a temperatures at least 40° C. higher than the QWs in the MQW structure. | 05-24-2012 |
20120126199 | PREPARING NANOPARTICLES AND CARBON NANOTUBES - Apparatus and methods for forming the apparatus include nanoparticles, catalyst nanoparticles, carbon nanotubes generated from catalyst nanoparticles, and methods of fabrication of such nanoparticles and carbon nanotubes. | 05-24-2012 |
20120132885 | Fabrication of Graphene Electronic Devices Using Step Surface Contour - A method for fabricating an electronic component, comprising providing a substrate; and depositing a graphene layer; wherein the substrate is either provided with a van-der-Waals functional layer or a van-der-Waals functional layer is deposited on the substrate before depositing the graphene layer; a surface step contour is formed; and growth of the graphene layer is seeded at the step contour. | 05-31-2012 |
20120132886 | NANOFLUDIC FIELD EFFECT TRANSISTOR BASED ON SURFACE CHARGE MODULATED NANOCHANNEL - A field effect transistor device includes: a reservoir bifurcated by a membrane of three layers: two electrically insulating layers; and an electrically conductive gate between the two insulating layers. The gate has a surface charge polarity different from at least one of the insulating layers. A nanochannel runs through the membrane, connecting both parts of the reservoir. The device further includes: an ionic solution filling the reservoir and the nanochannel; a drain electrode; a source electrode; and voltages applied to the electrodes (a voltage between the source and drain electrodes and a voltage on the gate) for turning on an ionic current through the ionic channel wherein the voltage on the gate gates the transportation of ions through the ionic channel. | 05-31-2012 |
20120138886 | SILICON AND SILICON GERMANIUM NANOWIRE STRUCTURES - Methods of forming microelectronic structures are described. Embodiments of those methods include forming a nanowire device comprising a substrate comprising source/drain structures adjacent to spacers, and nanowire channel structures disposed between the spacers, wherein the nanowire channel structures are vertically stacked above each other. | 06-07-2012 |
20120138887 | Electrical and Optical Devices Incorporating Topological Materials Including Topological Insulators - An electrical device includes a current transport layer formed using a layer of a topological material selected from the group of a topological insulator, a quantum anomalous hall (QAH) insulator, a topological insulator variant, and a topological magnetic insulator. In one embodiment, the current transport layer forms a conductive wire on an integrated circuit where the conductive wire includes two spatially separated edge channels, each edge channel carrying charge carriers propagating in one direction only. In other embodiments, an optical device includes an optical layer formed using a layer of the topological material. The optical layer can be a light absorbing layer, a light emitting layer, a light transport layer, or a light modulation layer. | 06-07-2012 |
20120138888 | Single Gate Inverter Nanowire Mesh - A FET inverter is provided that includes a plurality of device layers oriented vertically in a stack, each device layer having a source region, a drain region and a plurality of nanowire channels, wherein the source and drain regions of one or more of the device layers are doped with an n-type dopant and the source and drain regions of one or more other of the device layers are doped with a p-type dopant; a gate common to each of the device layers surrounding the nanowire channels; a first contact to the source regions of the one or more device layers doped with an n-type dopant; a second contact to the source regions of the one or more device layers doped with a p-type dopant; and a third contact common to the drain regions of each of the device layers. Techniques for fabricating a FET inverter are also provided. | 06-07-2012 |
20120145988 | Nanoscale Apparatus and Sensor With Nanoshell and Method of Making Same - A nanoscale apparatus ( | 06-14-2012 |
20120145989 | LASER-INDUCED STRUCTURING OF SUBSTRATE SURFACES - In one aspect, the present invention provides a method of processing a substrate, e.g., a semiconductor substrate, by irradiating a surface of the substrate (or at least a portion of the surface) with a first set of polarized short laser pulses while exposing the surface to a fluid to generate a plurality of structures on the surface, e.g., within a top layer of the surface. Subsequently, the structured surface can be irradiated with another set of polarized short laser pulses having a different polarization than that of the initial set while exposing the structured surface to a fluid, e.g., the same fluid initially utilized to form the structured surface or a different fluid. In many embodiments, the second set of polarized laser pulses cause the surface structures formed by the first set to break up into smaller-sized structures, e.g., nano-sized features such as nano-sized rods. | 06-14-2012 |
20120153250 | Nanowire Device with Alumina Passivation Layer and Methods of Making Same - In one aspect, the present disclosure relates to a device including a silicon substrate, wherein at least a portion of the substrate surface can be a silicon nanowire array; and a layer of alumina covering the silicon nanowire array. In some embodiments, the device can be a solar cell. In some embodiments, the device can be a p-n junction. In some embodiments, the p-n junction can be located below the bottom surface the nanowire array. | 06-21-2012 |
20120153251 | SELECTIVE EMITTER NANOWIRE ARRAY AND METHODS OF MAKING SAME - Another aspect of the present disclosure relates to a device including a substrate, having a top surface and a bottom surface; an array of nanowires having a base and a top surface, the base contacting the top surface of the substrate; a contacting structure including the same material as the substrate having a non-nanostructured surface of a dimension suitable for forming an electrical contact, located on the same side of the substrate as the array of silicon nanowires; wherein the contacting structure is doped with a greater impurity concentration than the nanowire array, thereby forming a selective emitter. | 06-21-2012 |
20120161098 | SUBSTRATE, MANUFACTURING METHOD OF SUBSTRATE, SEMICONDUCTOR ELEMENT, AND MANUFACTURING METHOD OF SEMICONDUCTOR ELEMENT - A semiconductor device is provided which is produced from a high-quality and large-area graphene substrate and is capable of fully exhibiting superior electronic properties that graphene inherently has. The semiconductor device is capable of realizing increased operation speed, reduced power consumption, and higher degree of integration, and thus is capable of improving the reliability and productivity. Electrical short circuit between a graphene layer ( | 06-28-2012 |
20120168710 | Growth and Transfer of Monolithic Horizontal Nanowire Superstructures onto Flexible Substrates - In a method of making a monolithic elongated nanowire, a mask polymer layer is applied to a selected crystal surface of a seed crystal. A plurality of spaced apart elongated openings is defined through the mask polymer layer, thereby exposing a corresponding plurality of portions of the crystal surface. The openings are disposed so as to be aligned with and parallel to a selected crystal axis of the seed crystal. The portions of the crystal surface are subjected to a chemical nutrient environment that causes crystalline material to grow from the plurality of portions for at least a period of time so that monocrystalline members grow from the elongated openings and until the monocrystalline members laterally expand so that each monocrystalline member grows into and merges with an adjacent one of the monocrystalline members, thereby forming a monolithic elongated nanowire. | 07-05-2012 |
20120168711 | Narrow-Waist Nanowire Transistor with Wide Aspect Ratio Ends - A method is provided for forming narrow-waist nanowire (NW) transistors with wide aspect ratio ends. The method provides a semiconductor-on-insulator wafer. The top semiconductor layer is etched to form a first pad, a second pad, and a plurality of narrow-waist semiconductor bridges. Each semiconductor bridge has two ends, each with a first width, attached to the first and second pads, and a mid-section less than the first width. A channel is formed in a center portion of each mid-section, a drain interposed between the channel and the first end, a source interposed between the channel and the second end, and a gate dielectric surrounding the channel and adjacent portions of the source and drain. A gate electrode is formed surrounding the gate dielectric. The semiconductor bridge ends are etched from the first and second pads, forming a plurality of narrow-waist semiconductor NW transistors. | 07-05-2012 |
20120168712 | HIGH BRIGHT LIGHT EMITTING DIODE - A high bright LED comprises a substrate, a conductive layer, a first semiconductor layer, a luminous layer, a second semiconductor layer, a first electrode, a second electrode and an insulation structure. The conductive layer, the first semiconductor layer, the luminous layer and the second semiconductor layer are disposed upwards from an upper solder layer of the substrate in order. The first electrode is electrically connected to the conductive layer The second electrode penetrates through the conductive layer, the first semiconductor layer and the luminous layer to make the upper solder and the second semiconductor layer electrically connected. The insulation structure comprises at least two passivation layers peripherally wrapping the second electrode. The thicknesses of the at least two passivation layers are conformed to the distributed Bragg reflection technique to make the passivation layers jointly used as a reflector with high reflectance. | 07-05-2012 |
20120168713 | METHOD FOR MANUFACTURING A SILICON NANOWIRE ARRAY USING A POROUS METAL FILM - The present invention is to provide a method for manufacturing a silicon nanowire array comprising (a) preparing a porous metal film; (b) placing the porous metal film in contact with a silicon substrate; and (c) etching the silicon substrate with a silicon etching solution. The present invention allows manufacturing vertically aligned large-area silicon nanowires by using the porous metal film as a catalyst and manufacturing nanowires having a porous structure, a porous nodular structure, an inclined structure and a zig-zag structure, which are distinguishable from nanowires of the prior art in their shape and crystallographic orientation, by adjusting etching conditions such as the composition of the silicon etching solution and the etching temperature in the step in which the silicon substrate is subjected to wet etching. | 07-05-2012 |
20120181501 | Graphene on Diamond Devices and Associated Methods - Graphene layers and associated methods are disclosed. In one aspect, for example, a method of making graphene on a diamond substrate is provided. Such a method can include applying a layer of a metal to a crystallographic face of the diamond substrate, and heating the diamond substrate under vacuum to convert a portion of the diamond substrate at the crystallographic face into graphene. In another aspect, the layer of metal is applied only on diamond substrate faces having a same crystallographic orientation. In yet another aspect, the layer of metal is applied to only a single crystallographic face of the diamond substrate. Additionally, in one aspect, converting the portion of the diamond substrate at the crystallographic face into graphene includes converting the portion of the diamond substrate by a martensitic transformation. | 07-19-2012 |
20120181502 | METHOD OF ELECTRICALLY CONTACTING NANOWIRE ARRAYS - In one aspect, the present disclosure relates to a device including a substrate, having a top surface and a bottom surface; an array of nanowires having a base and a top surface, the base contacting the top surface of the substrate; a contacting structure having a non-nanostructured surface, having a top surface and a bottom surface, located on the same side of the substrate as the array of silicon nanowires; and an electrical contact in contact with the top surface of the contacting structure. In some embodiments, the device includes an aluminum oxide passivation layer over the array of nanowires. In some embodiments, the layer of aluminum oxide is deposited via atomic layer deposition. | 07-19-2012 |
20120187365 | LIGHT EMITTING DEVICE - Provided are a light emitting device, a method of fabricating the light emitting device, a light emitting device package, and a lighting system. The light emitting device comprises a first conductive type semiconductor layer, a light emitting layer over the first conductive type semiconductor layer, an electron blocking layer over the light emitting layer, and a second conductive type semiconductor layer over the electron blocking layer. The electron blocking layer comprises a pattern having a height difference. | 07-26-2012 |
20120193603 | GRAPHENE GROWTH ON A CARBON-CONTAINING SEMICONDUCTOR LAYER - A semiconductor-carbon alloy layer is formed on the surface of a semiconductor substrate, which may be a commercially available semiconductor substrate such as a silicon substrate. The semiconductor-carbon alloy layer is converted into at least one graphene layer during a high temperature anneal, during which the semiconductor material on the surface of the semiconductor-carbon alloy layer is evaporated selective to the carbon atoms. As the semiconductor atoms are selectively removed and the carbon concentration on the surface of the semiconductor-carbon alloy layer increases, the remaining carbon atoms in the top layers of the semiconductor-carbon alloy layer coalesce to form a graphene layer having at least one graphene monolayer. Thus, a graphene layer may be provided on a commercially available semiconductor substrate having a diameter of 200 mm or 300 mm. | 08-02-2012 |
20120193604 | WAVELENGTH CONVERSION PLATE AND LIGHT EMITTING DEVICE USING THE SAME - Provided is a wavelength conversion plate having excellent luminous efficiency of a wavelength-converted light. The wavelength conversion plate includes a dielectric layer with nano pattern, a metal layer formed inside the nano pattern, and a wavelength conversion layer formed on the metal layer and having quantum dot or phosphor which wavelength-converts an excitation light to generate a wavelength-converted light. | 08-02-2012 |
20120199807 | SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR DEVICE INCLUDING A DIODE STRUCTURE AND METHODS OF FORMING SAME - Methods of forming diode structures for use in memory cells and memory arrays, such as resistive random access memory (RRAM). The methods include forming a first electrode by chemisorbing a graphite material (e.g., graphene) on a conductive material. A low-k dielectric material may be formed over surfaces of the first electrode exposed through an opening in a dielectric material overlying the first electrode, followed by formation of a high-k dielectric material over the low-k dielectric material. A remaining portion of the opening may be filled with another conductive material to form a second electrode. The first and second electrodes of the resulting diode structure have different work functions and, thus, provide a low thermal budget, a low contact resistance, a high forward-bias current and a low reverse-bias current. A memory cell and a memory array including such a diode structure are also disclosed. | 08-09-2012 |
20120199808 | HIGH VOLTAGE-RESISTANT LATERAL DOUBLE-DIFFUSED TRANSISTOR BASED ON NANOWIRE DEVICE - The present invention provides a high voltage-resistant lateral double-diffused transistor based on a nanowire device, which relates to the field of microelectronics semiconductor devices. The lateral double-diffused MOS transistor includes a channel region, a gate dielectric, a gate region, a source region, a drain region, a source end extension region and a drain end S-shaped drifting region, wherein the channel region has a lateral cylindrical silicon nanowire structure, on which a layer of gate dielectric is uniformly covered, the gate region is on the gate dielectric, the gate region and the gate dielectric completely surround the channel region, the source end extension region lies between the source region and the channel region, the drain end S-shaped drifting region lies between the drain region and the channel region, the plan view of the drain end S-shaped drifting region is in the form of single or multiple S-shaped structure(s), and an insulating material with a relative dielectric constant of 1-4 is filled within the S-shaped structure(s). The invention can improve the high voltage-resistant capability of a lateral double-diffused transistor based on a silicon nanowire MOS transistor. | 08-09-2012 |
20120199809 | METALORGANIC CHEMICAL VAPOR DEPOSITION (MOCVD) GROWTH OF HIGH PERFORMANCE NON-POLAR III-NITRIDE OPTICAL DEVICES - A method of device growth and p-contact processing that produces improved performance for non-polar III-nitride light emitting diodes and laser diodes. Key components using a low defect density substrate or template, thick quantum wells, a low temperature p-type III-nitride growth technique, and a transparent conducting oxide for the electrodes. | 08-09-2012 |
20120205613 | High Efficiency Broadband Semiconductor Nanowire Devices and Methods of Fabricating without Foreign Catalysis - Amongst the candidates for very high efficiency solid state light sources and full solar spectrum solar cells are devices based upon InGaN nanowires. Additionally these nanowires typically require heterostructures, quantum dots, etc which all place requirements for these structures to be grown with relatively few defects and in a controllable reproducible manner. Additionally flexibility according to the device design requires that the nanowire at the substrate may be either InN or GaN. According to the invention a method of growing relatively defect free nanowires and associated structures for group IIIA-nitrides is presented without the requirement for foreign metal catalysts and overcoming the non-uniform growth of prior art non-catalyst growth techniques. According to other embodiments of the invention self-organizing dot-within-a-dot nanowire and dot-within-a-dot-within-a-well nanowire structures are presented. | 08-16-2012 |
20120205614 | METHOD FOR MANUFACTURING A VERY-HIGH-RESOLUTION SCREEN USING A NANOWIRE-BASED EMITTING ANISOTROPIC CONDUCTIVE FILM - A method for producing an emissive pixel screen includes forming an active pixel matrix along which an electrode forming layer runs and having pixels arranged according to a distribution, forming an anisotropic substrate that includes a set of light emitting diodes constituted by parallel nanowires and arranged in an insulating matrix transversely with respect to a substrate thickness and having a density higher than a density of the pixels irrespective of the pixel distribution, connecting the substrate to the active pixel matrix by connecting only sub-groups of the parallel nanowires by a first end to separate pixel electrodes defined in the electrode forming layer according to the distribution of the pixels in the matrix, and connecting the sub-groups, by another end, to a common electrode, and delimiting the sub-groups by rendering the nanowires of the substrate that are arranged between the sub-groups emissively inactive. | 08-16-2012 |
20120205615 | ORGANIC PHOTOVOLTAIC CELL - An organic photovoltaic cell ( | 08-16-2012 |
20120211723 | GRAPHENE-CONTAINING SEMICONDUCTOR STRUCTURES AND DEVICES ON A SILICON CARBIDE SUBSTRATE HAVING A DEFINED MISCUT ANGLE - A semiconductor structure having a high Hall mobility is provided that includes a SiC substrate having a miscut angle of 0.1° or less and a graphene layer located on an upper surface of the SiC substrate. Also, provided are semiconductor devices that include a SiC substrate having a miscut angle of 0.1° or less and at least one graphene-containing semiconductor device located atop the SiC substrate. The at least one graphene-containing semiconductor device includes a graphene layer overlying and in contact with an upper surface of the SiC substrate. | 08-23-2012 |
20120217467 | BURIED CHANNEL FINFET SONOS WITH IMPROVED P/E CYCLING ENDURANCE - A Fin FET SONOS device is formed with a full buried channel. Embodiments include forming p-type silicon fins protruding from a first oxide layer, an n-type silicon layer over exposed surfaces of the fins, a second oxide layer, a nitride layer, and a third oxide layer sequentially on the n-type silicon layer, and a polysilicon layer on the third oxide layer. Embodiments include etching a silicon layer to form the fins and forming the oxide on the silicon layer. Different embodiments include: etching a silicon layer on a BOX layer to form the fins; forming the fins with a rounded top surface; and forming nano-wires surrounded by an n-type silicon layer, a first oxide layer, a nitride layer, a second oxide layer, and a polysilicon layer over a BOX layer. | 08-30-2012 |
20120217468 | Silicon Nanotube MOSFET - A nanotubular MOSFET device and a method of fabricating the same are used to extend device scaling roadmap while maintaining good short channel effects and providing competitive drive current. The nanotubular MOSFET device includes a concentric tubular inner and outer gate separated from each other by a tubular shaped epitaxially grown silicon layer, and a source and drain respectively separated by spacers surrounding the tubular inner and outer gates. The method of forming the nanotubular MOSFET device includes: forming on a substrate a cylindrical shaped Si layer; forming an outer gate surrounding the cylindrical Si layer and positioned between a bottom spacer and a top spacer; growing a silicon epitaxial layer on the top spacer adjacent to a portion of the cylindrical shaped Si layer; etching an inner portion of the cylindrical shaped Si forming a hollow cylinder; forming an inner spacer at the bottom of the inner cylinder; forming an inner gate by filling a portion of the hollow cylinder; forming a sidewall spacer adjacent to the inner gate; and etching a deep trench for accessing and contacting the outer gate and drain. | 08-30-2012 |
20120223288 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC DEVICE INCLUDING THE SEMICONDUCTOR DEVICE - An example embodiment relates to a transistor including a channel layer. A channel layer of the transistor may include a plurality of unit layers spaced apart from each other in a vertical direction. Each of the unit layers may include a plurality of unit channels spaced apart from each other in a horizontal direction. The unit channels in each unit layer may form a stripe pattern. Each of the unit channels may include a plurality of nanostructures. Each nanostructure may have a nanotube or nanowire structure, for example a carbon nanotube (CNT). | 09-06-2012 |
20120248401 | 3-DIMENSIONAL GRAPHENE STRUCTURE AND PROCESS FOR PREPARING AND TRANSFERRING THE SAME - A three-dimensional graphene structure, and methods of manufacturing and transferring the same including forming at least one layer of graphene having a periodically repeated three-dimensional shape. The three-dimensional graphene structure is formed by forming a pattern having a three-dimensional shape on a surface of a substrate, and forming the three-dimensional graphene structure having the three-dimensional shape of the pattern by growing graphene on the substrate on which the pattern is formed. The three-dimensional graphene structure is transferred by injecting a gas between the three-dimensional graphene structure and the substrate, separating the three-dimensional graphene structure from the substrate by bonding the three-dimensional graphene structure to an adhesive support, combining the three-dimensional graphene structure with an insulating substrate, and removing the adhesive support. | 10-04-2012 |
20120256158 | Al(x)Ga(1-x)N-CLADDING-FREE NONPOLAR III-NITRIDE BASED LASER DIODES AND LIGHT EMITTING DIODES - A method for fabricating Al | 10-11-2012 |
20120256159 | LED Device Architecture Employing Novel Optical Coating and Method of Manufacture - An improved LED device is disclosed and includes at least one active layer in communication with an energy source and configured to emit a first electromagnetic signal within a first wavelength range and at least a second electromagnetic signal within at least a second wavelength range, a substrate configured to support the active layer, at least one coating layer formed from alternating layers of silicon carbide and alumina applied to a surface of the substrate, the coating layer configured to reflect at least 95% of the first electromagnetic signal at the first wavelength range and transmit at least 95% of the second electromagnetic signal at the second wavelength range, at least one metal layer applied to the coating layer and configured to transmit the second electromagnetic signal at the second wavelength range therethrough, and an encapsulation device positioned to encapsulate the active layer. | 10-11-2012 |
20120261639 | STRUCTURES FOR RADIATION DETECTION AND ENERGY CONVERSION USING QUANTUM DOTS - Inorganic semiconducting materials such as silicon are used as a host matrix in which quantum dots reside to provide an energy conversion device that may be used to convert various types of radiation to electricity. | 10-18-2012 |
20120261640 | QUANTUM WELL GRAPHENE STRUCTURE FORMED ON A DIELECTRIC LAYER HAVING A FLAT SURFACE - An electronic device employing a graphene layer as a charge carrier layer. The graphene layer is sandwiched between layers that are constructed of a material having a highly ordered crystalline structure and a high dielectric constant. The highly ordered crystalline structure of the layers surrounding the graphene layer has low density of charged defects that can lead to scattering of charge carriers in the graphene layer. The high dielectric constant of the layers surrounding the graphene layer also prevents charge carrier scattering by minimizing interaction between the charge carriers and the changed defects in the surrounding layers. An interracial layer constructed of a thin, non-polar, dielectric material can also be provided between the graphene layer and each of the highly ordered crystalline high dielectric constant layers to minimize charge carrier scattering in the graphene layer through remote interfacial phonons. | 10-18-2012 |
20120267602 | CONTROL METHOD FOR DEVICE USING DOPED CARBON-NANOSTRUCTURE AND DEVICE COMPRISING DOPED CARBON-NANOSTRUCTURE - Provided is a method for controlling a device using a doped carbon-nanostructure, and a device including the doped carbon-nanostructure, in which the method for controlling the device selectively controls the mobility of electrons or holes using N-type or P-type doped carbon-nanostructure; the N-type or P-type impurities-doped carbon-nanostructure can selectively control the transport of electrons or holes according to a doped material; and also since the doped carbon-nanostructure limits the transport of charge that is the opposite charge to the transport facilitating charge, it can improve the efficiency of device by adding to a functional layer of device or using as a separate layer in the electrons or holes-only transporting device. | 10-25-2012 |
20120267603 | METHOD FOR FABRICATING QUANTUM DOT AND SEMICONDUCTOR STRUCTURE CONTAINING QUANTUM DOT - Disclosed are a method for fabricating a quantum dot. The method includes the steps of (a) preparing a compound semiconductor layer including a quantum well structure formed by sequentially stacking a first barrier layer, a well layer and a second barrier layer; (b) forming a dielectric thin film pattern including a first dielectric thin film having a thermal expansion coefficient higher than a thermal expansion coefficient of the second barrier layer and a second dielectric thin film having a thermal expansion coefficient lower than the thermal expansion coefficient of the second barrier layer on the second barrier layer; and (c) heat-treating the compound semiconductor layer formed thereon with the dielectric thin film pattern to cause an intermixing between elements of the well layer and elements of the barrier layers at a region of the compound semiconductor layer under the second dielectric thin film. | 10-25-2012 |
20120267604 | BENT NANOWIRES AND RELATED PROBING OF SPECIES - Kinked nanowires are used for measuring electrical potentials inside simple cells. An improved intracellular entrance is achieved by modifying the kinked nanowires with phospholipids. | 10-25-2012 |
20120280203 | TRANSPARENT PHOTODETECTOR - A transparent photodetector. The transparent photodetector includes a substrate; a waveguide on the substrate; a displaceable structure that can be displaced with respect to the substrate, the displaceable structure in proximity to the waveguide; and a silicon nanowire array suspended with respect to the substrate and mechanically linked to the displaceable structure, the silicon nanowire array comprising a plurality of silicon nanowires having piezoresistance. In operation, a light source propagating through the waveguide results in an optical force on the displaceable structure which further results in a strain on the nanowires to cause,a change in electrical resistance of the nanowires. The substrate may be a semiconductor on insulator substrate. | 11-08-2012 |
20120280204 | DIRECTIONALLY ETCHED NANOWIRE FIELD EFFECT TRANSISTORS - A nanowire field effect transistor (FET) device, includes a source region comprising a first semiconductor layer disposed on a second semiconductor layer, the source region having a surface parallel to {110} crystalline planes and opposing sidewall surfaces parallel to the {110} crystalline planes, a drain region comprising the first semiconductor layer disposed on the second semiconductor layer, the source region having a face parallel to the {110} crystalline planes and opposing sidewall surfaces parallel to the {110} crystalline planes, and a nanowire channel member suspended by the source region and the drain region, wherein nanowire channel includes the first semiconductor layer, and opposing sidewall surfaces parallel to {100} crystalline planes and opposing faces parallel to the {110} crystalline planes. | 11-08-2012 |
20120280205 | Contacts for Nanowire Field Effect Transistors - A nanowire field effect transistor (FET) device includes a channel region including a silicon nanowire portion having a first distal end extending from the channel region and a second distal end extending from the channel region, the silicon portion is partially surrounded by a gate stack disposed circumferentially around the silicon portion, a source region including the first distal end of the silicon nanowire portion, a drain region including the second distal end of the silicon nanowire portion, a metallic layer disposed on the source region and the drain region, a first conductive member contacting the metallic layer of the source region, and a second conductive member contacting the metallic layer of the drain region. | 11-08-2012 |
20120280206 | Nanowire Circuits in Matched Devices - A memory device includes a first nanowire connected to a first bit line node and a ground node, a first field effect transistor (FET) having a gate disposed on the first nanowire, a second FET having a gate disposed on the first nanowire, a second nanowire connected to a voltage source node and a first input node, a third FET having a gate disposed on the second nanowire, a third nanowire connected to the voltage source node and a second input node, a fourth FET having a gate disposed on the third nanowire, a fourth nanowire connected to a second bit line node and the ground node, a fifth FET having a gate disposed on the fourth nanowire, and a sixth FET having a gate disposed on the fourth nanowire. | 11-08-2012 |
20120286234 | Directionally Recrystallized Graphene Growth Substrates - Implementations and techniques for producing substrates suitable for growing graphene monolayers are generally disclosed. | 11-15-2012 |
20120286235 | NANOSCALE CHEMICAL TEMPLATING WITH OXYGEN REACTIVE MATERIALS - A method of fabricating templated semiconductor nanowires on a surface of a semiconductor substrate for use in semiconductor device applications is provided. The method includes controlling the spatial placement of the semiconductor nanowires by using an oxygen reactive seed material. The present invention also provides semiconductor structures including semiconductor nanowires. In yet another embodiment, patterning of a compound semiconductor substrate or other like substrate which is capable of forming a compound semiconductor alloy with an oxygen reactive element during a subsequent annealing step is provided. This embodiment provides a patterned substrate that can be used in various applications including, for example, in semiconductor device manufacturing, optoelectronic device manufacturing and solar cell device manufacturing. | 11-15-2012 |
20120286236 | SUPER LATTICE/QUANTUM WELL NANOWIRES - Segmented semiconductor nanowires are manufactured by removal of material from a layered structure of two or more semiconductor materials in the absence of a template. The removal takes place at some locations on the surface of the layered structure and continues preferentially along the direction of a crystallographic axis, such that nanowires with a segmented structure remain at locations where little or no removal occurs. The interface between different segments can be perpendicular to or at angle with the longitudinal direction of the nanowire. | 11-15-2012 |
20120298948 | NANOWIRE FET HAVING INDUCED RADIAL STRAIN - An intermediate process device is provided and includes a nanowire connecting first and second silicon-on-insulator (SOI) pads, a gate including a gate conductor surrounding the nanowire and poly-Si surrounding the gate conductor and silicide forming metal disposed to react with the poly-Si to form a fully silicided (FUSI) material to induce radial strain in the nanowire. | 11-29-2012 |
20120298949 | Graphene/Nanostructure FET with Self-Aligned Contact and Gate - A field effect transistor (FET) includes a substrate; a channel material located on the substrate, the channel material comprising one of graphene or a nanostructure; a gate located on a first portion of the channel material; and a contact aligned to the gate, the contact comprising one of a metal silicide, a metal carbide, and a metal, the contact being located over a source region and a drain region of the FET, the source region and the drain region comprising a second portion of the channel material. | 11-29-2012 |
20120305886 | NANOWIRE FET WITH TRAPEZOID GATE STRUCTURE - In one embodiment, a method of providing a nanowire semiconductor device is provided, in which the gate structure to the nanowire semiconductor device has a trapezoid shape. The method may include forming a trapezoid gate structure surrounding at least a portion of a circumference of a nanowire. The first portion of the trapezoid gate structure that is in direct contact with an upper surface of the nanowire has a first width and a second portion of the trapezoid gate structure that is in direct contact with a lower surface of the nanowire has a second width. The second width of the trapezoid gate structure is greater than the first width of the trapezoid gate structure. The exposed portions of the nanowire that are adjacent to the portion of the nanowire that the trapezoid gate structure is surrounding are then doped to provide source and drain regions. | 12-06-2012 |
20120319078 | GRAPHENE GROWTH ON A NON-HEXAGONAL LATTICE - A graphene layer is formed on a crystallographic surface having a non-hexagonal symmetry. The crystallographic surface can be a surface of a single crystalline semiconductor carbide layer. The non-hexagonal symmetry surface of the single crystalline semiconductor carbide layer is annealed at an elevated temperature in ultra-high vacuum environment to form the graphene layer. During the anneal, the semiconductor atoms on the non-hexagonal surface of the single crystalline semiconductor carbide layer are evaporated selective to the carbon atoms. As the semiconductor atoms are selectively removed, the carbon concentration on the surface of the semiconductor-carbon alloy layer increases. Despite the non-hexagonal symmetry of the surface of the semiconductor-carbon alloy layer, the remaining carbon atoms can coalesce to form a graphene layer having hexagonal symmetry. | 12-20-2012 |
20120326115 | GRAPHENE STRUCTURE AND METHOD OF MANUFACTURING THE GRAPHENE STRUCTURE, AND GRAPHENE DEVICE AND METHOD OF MANUFACTURING THE GRAPHENE DEVICE - A graphene structure and a method of manufacturing the graphene structure, and a graphene device and a method of manufacturing the graphene device. The graphene structure includes a substrate; a growth layer disposed on the substrate and having exposed side surfaces; and a graphene layer disposed on the side surfaces of the growth layer. | 12-27-2012 |
20120326116 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor structure with a waveguide, the semiconductor structure has a plurality of layers, at least one of which being partially laterally oxidised, said laterally oxidised material modifying the lateral effective refractive index with said structure in order to form a waveguide within the structure, the structure also has a quantum dot, said quantum dot being configured to emit photons into said waveguide, the waveguide being configured such that it guides the output from a single quantum dot. | 12-27-2012 |
20130001507 | SEMICONDUCTOR DEVICE AND METHOD - A semiconductor device and a method of manufacturing the device is disclosed. In one aspect, a method includes providing a substrate, providing a first epitaxial semiconducting layer on top of the substrate, and forming a one- or two-dimensional repetitive pattern, each part of the pattern having an aspect ratio in the range of about 0.1 to 50. | 01-03-2013 |
20130009128 | NANOSCALE SWITCHING DEVICE - A nanoscale switching device has an active region containing a switching material. The switching device has a first electrode and a second electrode with nanoscale widths, and the active region is disposed between the first and second electrodes. A protective cladding layer surrounds the active region. The protective cladding layer is formed of a cladding material unreactive to the switching material. An interlayer isolation layer formed of a dielectric material is disposed between the first and second electrodes and outside the protective cladding layer. | 01-10-2013 |
20130009129 | QUANTUM DOT OPTICAL DEVICES WITH ENHANCED GAIN AND SENSITIVITY AND METHODS OF MAKING SAME - Various embodiment include optical and optoelectronic devices and methods of making same. Under one aspect, an optical device includes an integrated circuit having an array of conductive regions, and an optically sensitive material over at least a portion of the integrated circuit and in electrical communication with at least one conductive region of the array of conductive regions. Under another aspect, a film includes a network of fused nanocrystals, the nanocrystals having a core and an outer surface, wherein the core of at least a portion of the fused nanocrystals is in direct physical contact and electrical communication with the core of at least one adjacent fused nanocrystal, and wherein the film has substantially no defect states in the regions where the cores of the nanocrystals are fused. Additional devices and methods are described. | 01-10-2013 |
20130015424 | OPTOELECTRONIC DEVICESAANM CHUNG; Dae-youngAACI Yongin-siAACO KRAAGP CHUNG; Dae-young Yongin-si KRAANM CHO; Kyung-sangAACI Gwacheon-siAACO KRAAGP CHO; Kyung-sang Gwacheon-si KRAANM KIM; Tae-hoAACI Suwon-siAACO KRAAGP KIM; Tae-ho Suwon-si KRAANM CHOI; Byoung-lyongAACI SeoulAACO KRAAGP CHOI; Byoung-lyong Seoul KR - An optoelectronic device is provided including an element that forms a dipole moment between an active layer and a charge transport layer. The optoelectronic device may include an active layer between a first electrode and a second electrode, a first charge transport layer between the first electrode and the active layer, and a dipole layer between the active layer and the first charge transport layer. A second charge transport layer may be further provided between the second electrode and the active layer. The second dipole layer may be further provided between the second charge transport layer and the active layer. | 01-17-2013 |
20130020549 | SYSTEMS AND METHODS FOR FABRICATING LONGITUDINALLY-SHAPED STRUCTURES - The present invention relates, in some aspects, to systems and methods for fabricating longitudinally-shaped structures such as nanobelt semiconductor structures. In some embodiments, the method comprises:
| 01-24-2013 |
20130026441 | Apparatus and Associated Methods Related to Detection of Electromagnetic Signalling - In one or more embodiments described herein, there is provided an apparatus including a first layer for detecting electromagnetic signalling, and a second layer positioned proximate to the first layer. The first layer includes graphene, and the second layer is configured to undergo plasmonic resonance in response to receiving electromagnetic signalling. This plasmonic resonance that the second layer undergoes thereby sensitizes the graphene of the first layer to detection of particular spectral characteristics of received electromagnetic signalling corresponding to the particular plasmonic resonance of the second layer. | 01-31-2013 |
20130026442 | PHOTODETECTOR - A photodetector includes: a substrate; a first dielectric material positioned on the substrate; an optical waveguide positioned on the first dielectric material; a second dielectric material positioned on the optical waveguide; a graphene layer positioned on the second dielectric material; and a first electrode and a second electrode that are positioned on the graphene layer. | 01-31-2013 |
20130026443 | SILICON NANOWIRE COMPRISING HIGH DENSITY METAL NANOCLUSTERS AND METHOD OF PREPARING THE SAME - A silicon nanowire including metal nanoclusters formed on a surface thereof at a high density. The metal nanocluster improves electrical and optical characteristics of the silicon nanowire, and thus can be usefully used in various electrical devices such as a lithium battery, a solar cell, a bio sensor, a memory device, or the like. | 01-31-2013 |
20130026444 | SYNTHESIZING GRAPHENE FROM METAL-CARBON SOLUTIONS USING ION IMPLANTATION - A method and semiconductor device for synthesizing graphene using ion implantation of carbon. Carbon is implanted in a metal using ion implantation. After the carbon is distributed in the metal, the metal is annealed and cooled in order to precipitate the carbon from the metal to form a layer of graphene on the surface of the metal. The metal/graphene surface is then transferred to a dielectric layer in such a manner that the graphene layer is placed on top of the dielectric layer. The metal layer is then removed. Alternatively, recessed regions are patterned and etched in a dielectric layer located on a substrate. Metal is later formed in these recessed regions. Carbon is then implanted into the metal using ion implantation. The metal may then be annealed and cooled in order to precipitate the carbon from the metal to form a layer of graphene on the metal's surface. | 01-31-2013 |
20130032776 | LIGHT EMITTING DIODE STRUCTURE AND MANUFACTURING METHOD THEREOF - A light emitting diode structure and a manufacturing method thereof are disclosed. The structure includes a substrate, an N type semiconductor layer, and active layer, a P type semiconductor layer, a current diffusion layer, and a metal electrode. The metal ions of the P type semiconductor layer may bond with hydrogen after process thermal annealing, and metal hydride may be generated. The metal hydride may be directly formed on the surface of the P type semiconductor layer and may be used as the current blocking layer. Since the metal hydride may be directly formed on the surface of the P type semiconductor layer, its structure is flat, which resolve the problem having the electrodes peeled off from the solder wire. | 02-07-2013 |
20130032777 | Semiconductor Device and Manufacturing Method thereof - The present invention discloses a semiconductor device and a manufacturing method thereof. The method comprises the steps of providing a substrate on which a graphene layer or carbon nanotube layer is formed; exposing part of the graphene layer or carbon nanotube layer after forming a gate structure on the graphene layer or carbon nanotube layer, wherein the gate structure comprises a gate stack, a spacer and a cap layer, the cap layer is located on the gate stack, and the spacer surrounds the gate stack and the cap layer; epitaxially growing a semiconductor layer on the exposed graphene layer or carbon nanotube layer; and forming a metal contact layer on the semiconductor layer. In the present invention, the semiconductor layer is formed on the graphene layer or carbon nanotube layer, and then the metal contact layer is formed on the semiconductor layer, instead of forming the metal contact layer directly from the graphene layer or carbon nanotube layer. This facilitates to form the self-aligned source and drain contact plugs. | 02-07-2013 |
20130037778 | DEVICE INCLUDING QUANTUM DOTS - A method of making a device comprises forming a layer comprising quantum dots over a substrate including a first electrode, fixing the layer comprising quantum dots formed over the substrate, and exposing at least a portion of, and preferably all, exposed surfaces of the fixed layer comprising quantum dots to small molecules. Also disclosed is a method of making a device, the method comprising forming a layer comprising quantum dots over a substrate including a first electrode, exposing the layer comprising quantum dots to small molecules and light flux. A method of making a film including a layer comprising quantum dots, and a method of preparing a device component including a layer comprising quantum dots are also disclosed. Devices, device components, and films are also disclosed. | 02-14-2013 |
20130056703 | Sensor Device and Method - A graphene layer is generated on a substrate. A plastic material is deposited on the graphene layer to at least partially cover the graphene layer. The substrate is separated into at least two substrate pieces. | 03-07-2013 |
20130062591 | CASE INCLUDING SEMICONDUCTOR NANOCRYSTALS, AND OPTOELECTRONIC DEVICE INCLUDING THE SAME - A case including a case main body, a matrix including a semiconductor nanocrystal, the matrix disposed in the case main body, and a sealant disposed on the case main body, wherein the sealant has a gas permeability of about 1 cubic centimeter at standard temperature and pressure per centimeter per meter squared per day per atmosphere or less and a tensile strength of about 5 megaPascals or more, and wherein the semiconductor nanocrystal is a Group II-VI compound, a Group III-V compound, a Group IV-VI compound, a Group IV element, a Group IV element, a Group IV compound, or a combination thereof. | 03-14-2013 |
20130075690 | Ammonia Nanosensors, and Environmental Control System - Embodiments of nanoelectronic sensors are described, including sensors for detecting analytes such ammonia. An environmental control system employing nanoelectronic sensors is described. A personnel safety system configured as a disposable badge employing nanoelectronic sensors is described. A method of dynamic sampling and exposure of a sensor providing a number of operational advantages is described. | 03-28-2013 |
20130082233 | SELECTIVE PLACEMENT OF CARBON NANOTUBES VIA COULOMBIC ATTRACTION OF OPPOSITELY CHARGED CARBON NANOTUBES AND SELF-ASSEMBLED MONOLAYERS - A method of forming a structure having selectively placed carbon nanotubes, a method of making charged carbon nanotubes, a bi-functional precursor, and a structure having a high density carbon nanotube layer with minimal bundling. Carbon nanotubes are selectively placed on a substrate having two regions. The first region has an isoelectric point exceeding the second region's isoelectric point. The substrate is immersed in a solution of a bi-functional precursor having anchoring and charged ends. The anchoring end bonds to the first region to form a self-assembled monolayer having a charged end. The substrate with charged monolayer is immersed in a solution of carbon nanotubes having an opposite charge to form a carbon nanotube layer on the self-assembled monolayer. The charged carbon nanotubes are made by functionalization or coating with an ionic surfactant. | 04-04-2013 |
20130082234 | Carbon-based semiconductors - All-carbon-based semiconductor devices are provided. In accordance with an example embodiment, an apparatus includes n-type and p-type carbon-based semiconductor material that form a p-n junction, which are respectively coupled to electrodes having a carbon allotrope. A first one of electrodes is connected to the n-type material and a second one of the electrodes is connected to the p-type material, and collect charge presented at the p-n junction. | 04-04-2013 |
20130082235 | MONOLITHIC 3-D INTEGRATION USING GRAPHENE - A monolithic three dimensional integrated circuit device includes a first layer having first active devices. The monolithic three dimensional integrated circuit device also includes a second layer having second active devices that each include a graphene portion. The second layer can be fabricated on the first layer to form a stack of active devices. A base substrate may support the stack of active devices. | 04-04-2013 |
20130087758 | CARBON NANOTUBE LIGHT EMITTING DEVICE, LIGHT SOURCE, AND PHOTO COUPLER - A plurality of electrodes, and carbon nanotubes disposed between the electrodes, at least part of the carbon nanotubes including a metal carbon nanotube are provided. The metal carbon nanotube generates heat upon passing of current to the electrodes and emits light by blackbody radiation, so that the emitted light has a wide emission wavelength region and can be modulated at high speed. This makes it possible to implement a continuum spectrum light source that can be modulated at high speed, which is suitable for use in information communication, electrical and electronic fields. | 04-11-2013 |
20130099194 | Method Of Making Graphene Layers, And Articles Made Thereby - There is provided a method for forming a graphene layer. The method includes forming an article that comprises a carbon-containing self-assembled monolayer (SAM). A layer of nickel is deposited on the SAM. The article is heated in a reducing atmosphere and coolded. The heating and cooling steps are carried out so as to convert the SAM to a graphene layer. | 04-25-2013 |
20130099195 | Direct Formation of Graphene on Semiconductor Substrates - The invention generally related to a method for preparing a layer of graphene directly on the surface of a semiconductor substrate. The method includes forming a carbon-containing layer on a front surface of a semiconductor substrate and depositing a metal film on the carbon layer. A thermal cycle degrades the carbon-containing layer, which forms graphene directly upon the semiconductor substrate upon cooling. In some embodiments, the carbon source is a carbon-containing gas, and the thermal cycle causes diffusion of carbon atoms into the metal film, which, upon cooling, segregate and precipitate into a layer of graphene directly on the semiconductor substrate. | 04-25-2013 |
20130099196 | Semiconductor-Graphene Hybrids Formed Using Solution Growth - A novel method for fabrication of hybrid semiconductor-graphene nanostructures in large scale by floating graphene sheets on the surface of a solution is provided. Using this approach, crystalline ZnO nano/micro-rod bundles on graphene fabricated using chemical vapor deposition were prepared. UV detectors fabricated using the as-prepared hybrid ZnO-graphene nano-structure with graphene being one of the two electrodes show high sensitivity to ultraviolet light, suggesting the graphene remained intact during the ZnO growth. This growth process provides a low-cost and robust scheme for large-scale fabrication of semiconductor nanostructures on graphene and may be applied for synthesis of a variety of hybrid semiconductor-graphene nano-structures demanded for optoelectronic applications including photovoltaics, photodetection, and photocatalysis. | 04-25-2013 |
20130099197 | DOPED GRAPHENE ELECTRONIC MATERIALS - A graphene substrate is doped with one or more functional groups to form an electronic device. | 04-25-2013 |
20130112937 | Nanowire Field Effect Transistor Device - A method for forming a field effect transistor device includes forming a nanowire suspended above a substrate, forming a dummy gate stack on a portion of the substrate and around a portion of the nanowire, removing exposed portions of the nanowire, epitaxially growing nanowire extension portions from exposed portions of the nanowire, depositing a layer of semiconductor material over exposed portions of the substrate, the dummy gate stack and the nanowire extension portions, and removing portions of the semiconductor material to form sidewall contact regions arranged adjacent to the dummy gate stack and contacting the nanowire extension portions. | 05-09-2013 |
20130112938 | Nanowire Field Effect Transistor Device - A field effect transistor device includes a nanowire, a gate stack comprising a gate dielectric layer disposed on the nanowire, a gate conductor layer disposed on the dielectric layer and a substrate, and an active region including a sidewall contact portion disposed on the substrate adjacent to the gate stack, the side wall contact portion is electrically in contact with the nanowire. | 05-09-2013 |
20130126824 | SEMICONDUCTIVE NANOWIRE SOLID STATE OPTICAL DEVICE AND CONTROL METHOD THEREOF - Disclosed are a semiconductor nanowire solid state optical device and a control method thereof. The device comprises a nanowire, a first electrode, a second electrode, an electrical circuit and a mechanical micro device. The nanowire has a first end and a second end. The first electrode is coupled to the first end. The second electrode is coupled to the second end. The electrical circuit is coupled to the first electrode and the second electrode. The mechanical micro device is conjuncted with the nanowire for applying an external force to the nanowire to form highest occupied molecular orbital (HOMO) and lowest unoccupied molecular orbital (LUMO) in the nanowire. The HOMO and LUMO are employed as an n-type semiconductor and a p-type semiconductor, respectively. The nanowire is a semiconductor when an external force is applied thereto. | 05-23-2013 |
20130134384 | METHOD OF POST TREATING GRAPHENE AND METHOD OF MANUFACTURING GRAPHENE USING THE SAME - Provided is a method of post treating graphene including providing graphene on a metal thin film, providing a carrier on the graphene, hardening the carrier, and removing the metal thin film from the graphene. | 05-30-2013 |
20130140517 | Thin and Flexible Gallium Nitride and Method of Making the Same - A material for use in electronic circuits. The material includes a thin layer of gallium nitride (GaN), the thin layer of GaN produced in a high-volume production setting without mechanical planarization having a thickness of as low as 10 nm and a defect density as low as 10 | 06-06-2013 |
20130146834 | QUANTUM DOT-MATRIX THIN FILM AND METHOD OF PRODUCING THE SAME - A quantum dot-matrix thin film and a method of preparing a quantum dot-matrix thin film are provided. The thin film includes quantum dots; an inorganic matrix in which the quantum dots are imbedded; and an interface layer disposed between the quantum dots and the inorganic matrix to surround surfaces of the quantum dots. The method includes preparing a quantum dot solution in which quantum dots with inorganic ligands are dispersed; adding a matrix precursor to the quantum dot solution; coating the quantum dot solution comprising the matrix precursor on a substrate; and annealing the substrate coated with the quantum dot solution. | 06-13-2013 |
20130153855 | Chemical Oxidation of Graphene and Carbon Nanotubes Using Cerium (IV) Ammonium Nitrate - A process comprises combining a Ce (IV) salt with a carbon material comprising CNT or graphene wherein the Ce (IV) salt is selected from a Ce (IV) ammonium salt of a nitrogen oxide acid and is dissolved in a solvent comprising water. The process is conducted under conditions to substantially oxidize the carbon material to produce an oxidized material that is substantially non-conducting. After the oxidation, the Ce (IV) is substantially removed from the oxidized material. This produces a product made by the process. An article of manufacture comprises the product on a substrate. The oxidized material can be formed as a pattern on the substrate. In another embodiment the substrate comprises an electronic device with the oxidized material patterning non-conductive areas separate from conductive areas of the non-oxidized carbon material, where the conductive areas are operatively associated with the device. | 06-20-2013 |
20130161584 | Light Emitting Diode (LED) Using Three-Dimensional Gallium Nitride (GaN) Pillar Structures with Planar Surfaces - A method is provided for fabricating a light emitting diode (LED) using three-dimensional gallium nitride (GaN) pillar structures with planar surfaces. The method forms a plurality of GaN pillar structures, each with an n-doped GaN (n-GaN) pillar and planar sidewalls perpendicular to the c-plane, formed in either an m-plane or a-plane family. A multiple quantum well (MQW) layer is formed overlying the n-GaN pillar sidewalls, and a layer of p-doped GaN (p-GaN) is formed overlying the MQW layer. The plurality of GaN pillar structures are deposited on a first substrate, with the n-doped GaN pillar sidewalls aligned parallel to a top surface of the first substrate. A first end of each GaN pillar structure is connected to a first metal layer. The second end of each GaN pillar structure is etched to expose the n-GaN pillar second end and connected to a second metal layer. | 06-27-2013 |
20130187122 | PHOTONIC DEVICE HAVING EMBEDDED NANO-SCALE STRUCTURES - The present disclosure involves a method of fabricating a lighting apparatus. The method includes forming a first III-V group compound layer over a substrate. The first III-V group compound layer has a first type of conductivity. A multiple quantum well (MQW) layer is formed over the first III-V group compound layer. A second III-V group compound layer is then formed over the MQW layer. The second III-V group compound layer has a second type of conductivity different from the first type of conductivity. Thereafter, a plurality of conductive components is formed over the second III-V group compound layer. A light-reflective layer is then formed over the second III-V group compound layer and over the conductive components. The conductive components each have better adhesive and electrical conduction properties than the light-reflective layer. | 07-25-2013 |
20130193404 | PHOTOCONVERSION DEVICE WITH ENHANCED PHOTON ABSORPTION - An infrared photoconversion device comprising a collector with at least an active layer made of a single sheet of doped single-layer, bilayer, or multilayer graphene patterned as nanodisks or nanoribbons. The single sheet of doped graphene presents high absorbance and thus, the efficiency of devices such as photovoltaic cells, photodetectors, and light emission devices can be improved by using graphene as the central absorbing or emitting element. These devices become tunable because their peak absorption or emission wavelength is changed via electrostatic doping of the graphene. | 08-01-2013 |
20130193405 | Imprinted Semiconductor Multiplex Detection Array - An array of sensor devices, each sensor including a set of semiconducting nanotraces having a width less than about 100 nm is provided. Method for fabricating the arrays is disclosed, providing a top-down approach for large arrays with multiple copies of the detection device in a single processing step. Nanodimensional sensing elements with precise dimensions and spacing to avoid the influence of electrodes are provided. The arrays may be used for multiplex detection of chemical and biomolecular species. The regular arrays may be combined with parallel synthesis of anchor probe libraries to provide a multiplex diagnostic device. Applications for gas phase sensing, chemical sensing and solution phase biomolecular sensing are disclosed. | 08-01-2013 |
20130200332 | TRANSISTOR ARRANGEMENT AND A METHOD OF FORMING A TRANSISTOR ARRANGEMENT - In an embodiment, a transistor arrangement is provided. The transistor arrangement comprises a nanowire including a first nanowire region and a second nanowire region; a first gate contact disposed over the first nanowire region; an insulating region disposed over the second nanowire region; a second gate contact disposed over the insulating region; wherein the first nanowire region and the first gate contact forms a part of an enhancement mode transistor and the second nanowire region, the insulating region and the second gate contact forms a part of a depletion mode transistor. A method of forming a transistor arrangement may also be provided. Also contemplated is a transistor and a method for forming said transistor, where the transistor comprises a nanowire and a gate contact, where the gate contact is formed by directly writing the gate contact onto a region of the nanowire. | 08-08-2013 |
20130200333 | SEMICONDUCTOR LIGHT-EMITTING ELEMENT WITH CORTEX-LIKE NANOSTRUCTURES - The present invention is to provide a semiconductor light-emitting element. The element comprises a substrate and a nanostructural layer. The nanostructural layer is formed on the substrate and comprises a plurality of void-embedded cortex-like nanostructures, wherein the volumetric porosity of the nanostructural layer is ranged from 30% to 59%. Compared with the prior art, the present invention can not only improve the crystalline quality of epitaxial layers but also enhance the external quantum efficiency (EQE) of the semiconductor light-emitting element. | 08-08-2013 |
20130207070 | Nanocomposite Material And Its Use In Optoelectronics - Material comprising a matrix made of semiconducting or insulating, transparent material in which core/shell type nanoparticles are dispersed, the core of which consists of a semiconductor and the shell of which is formed from a material chosen from the oxides TiO | 08-15-2013 |
20130214242 | Integrated Circuitry Components, Switches, And Memory Cells - A switch includes a graphene structure extending longitudinally between a pair of electrodes and being conductively connected to both electrodes of said pair. First and second electrically conductive structures are laterally outward of the graphene structure and on opposing sides of the graphene structure from one another. Ferroelectric material is laterally between the graphene structure and at least one of the first and second electrically conductive structures. The first and second electrically conductive structures are configured to provide the switch into “on” and “off” states by application of an electric field across the graphene structure and the ferroelectric material. Other embodiments are disclosed, including components of integrated circuitry which may not be switches. | 08-22-2013 |
20130214243 | NANOWIRES MADE OF NOVEL PRECURSORS AND METHOD FOR THE PRODUCTION THEREOF - The invention relates to nanowires which consist of or comprise semiconductor materials and are used for applications in photovoltaics and electronics and to a method for the production thereof. The nanowires are characterized in that they are obtained by a novel method using novel precursors. The precursors represent compounds, or mixtures of compounds, each having at least one direct Si—Si and/or Ge—Si and/or Ge—Ge bond, the substituents of which consist of halogen and/or hydrogen, and in the composition of which the atomic ratio of substituent:metalloid atoms is at least 1:1. | 08-22-2013 |
20130221319 | Gate-All Around Semiconductor Nanowire FET's On Bulk Semicoductor Wafers - Non-planar semiconductor devices are provided that include at least one semiconductor nanowire suspended above a semiconductor oxide layer that is present on a first portion of a bulk semiconductor substrate. An end segment of the at least one semiconductor nanowire is attached to a first semiconductor pad region and another end segment of the at least one semiconductor nanowire is attached to a second semiconductor pad region. The first and second pad regions are located above and are in direct contact with a second portion of the bulk semiconductor substrate which is vertically offsets from the first portion. The structure further includes a gate surrounding a central portion of the at least one semiconductor nanowire, a source region located on a first side of the gate, and a drain region located on a second side of the gate which is opposite the first side of the gate. | 08-29-2013 |
20130221320 | LED WITH EMBEDDED DOPED CURRENT BLOCKING LAYER - The present disclosure involves an apparatus. The apparatus includes a photonic die structure that includes a plurality of layers. A current blocking layer is embedded in one of the plurality of layers. The current blocking layer is a doped layer. The present disclosure also involves a method of fabricating a light-emitting diode (LED). As a part of the method, an LED is provided. The LED includes a plurality of layers. A patterned mask is then formed over the LED. The patterned mask contains an opening. A dopant is introduced through the opening to a layer of the LED through either an ion implantation process or a thermal diffusion process. As a result of the dopant being introduced, a doped current blocking component is formed to be embedded within the layer of the LED. | 08-29-2013 |
20130234105 | Bond type flip-chip light-emitting structure and method of manufacturing the same - A bond type flip-chip light-emitting structure and method of manufacturing the same. Firstly, form a positive electrode and a negative electrode on an epitaxy layer. Next, deposit an insulation layer on parts of the positive electrode and negative electrode, to expose respectively a positive electrode via hole and a negative electrode via hole. Then, form a bonded metal layer on the insulation layer, the positive electrode via hole, and the negative electrode via hole, so that the positive electrode and the negative electrode are on a same plane by means of the bonded metal layer. Finally, on a substrate, bond the first metal layer and the second metal layer onto the corresponding first bonded metal unit and the second bonded metal unit of the bonded metal layer, to form into shape, thus realizing a bond type flip-chip light-emitting structure. | 09-12-2013 |
20130240828 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device according to embodiments includes a semiconductor substrate, a buried insulating layer which is formed on the semiconductor substrate, a semiconductor layer which is formed on the buried insulating layer and includes a narrow portion and two wide portions which are larger than the narrow portion in width and are respectively connected to one end and the other end of the narrow portion, a gate insulating film which is formed on a side surface of the narrow portion, and a gate electrode formed on the gate insulating film. The impurity concentration of the semiconductor substrate directly below the narrow portion is higher than the impurity concentration of the narrow portion, and the impurity concentration of the semiconductor substrate directly below the narrow portion is higher than the impurity concentration of the semiconductor substrate directly below the wide portion. | 09-19-2013 |
20130240829 | QUANTUM DOT STRUCTURE, METHOD FOR FORMING QUANTUM DOT STRUCTURE, WAVELENGTH CONVERSION ELEMENT, LIGHT-LIGHT CONVERSION DEVICE, AND PHOTOELECTRIC CONVERSION DEVICE - This quantum dot structure has a matrix layer and a plurality of crystalline quantum dots provided spaced within the matrix layer. The quantum dots are provided at positions that differ in the direction of thickness of the matrix layer. | 09-19-2013 |
20130240830 | DIRECT AND SEQUENTIAL FORMATION OF MONOLAYERS OF BORON NITRIDE AND GRAPHENE ON SUBSTRATES - The invention generally related to a method for preparing a layer of graphene directly on the surface of a substrate, such as a semiconductor substrate. The layer of graphene may be formed in direct contact with the surface of the substrate, or an intervening layer of a material may be formed between the substrate surface and the graphene layer. | 09-19-2013 |
20130256627 | Sensors Incorporating Freestanding Carbon NanoStructures - Sensors for detecting IR radiation, UV radiation, X-Rays, light, gas, and chemicals. The sensors herein incorporate freestanding carbon nanostructures, such as single-walled carbon nanotubes (“SWCNT”), atomically thin carbon sheets having a thickness of about between 1 atom and about 5 atoms (“graphene”), and combinations thereof. The freestanding carbon nanostructures are suspended above a substrate by a plurality of conductors, each conductor electrically connected to the carbon nanostructure. In one method of manufacture, a resonance chamber is formed under the carbon nanostructure by etching of the substrate, yielding a sensor wherein the resonance chamber is bounded by at least the substrate and the carbon nanostructure. | 10-03-2013 |
20130270511 | GRAPHENE PRESSURE SENSORS - Semiconductor nano pressure sensor devices having graphene membrane suspended over cavities formed in a semiconductor substrate. A suspended graphene membrane serves as an active electro-mechanical membrane for sensing pressure, which can be made very thin, from about one atomic layer to about 10 atomic layers in thickness, to improve the sensitivity and reliability of a semiconductor pressure sensor device. | 10-17-2013 |
20130270512 | CMOS IMPLEMENTATION OF GERMANIUM AND III-V NANOWIRES AND NANORIBBONS IN GATE-ALL-AROUND ARCHITECTURE - Architectures and techniques for co-integration of heterogeneous materials, such as group III-V semiconductor materials and group IV semiconductors (e.g., Ge) on a same substrate (e.g. silicon). In embodiments, multi-layer heterogeneous semiconductor material stacks having alternating nanowire and sacrificial layers are employed to release nanowires and permit formation of a coaxial gate structure that completely surrounds a channel region of the nanowire transistor. In embodiments, individual PMOS and NMOS channel semiconductor materials are co-integrated with a starting substrate having a blanket layers of alternating Ge/III-V layers. In embodiments, vertical integration of a plurality of stacked nanowires within an individual PMOS and individual NMOS device enable significant drive current for a given layout area. | 10-17-2013 |
20130270513 | ELECTROPOSITIVE METAL CONTAINING LAYERS FOR SEMICONDUCTOR APPLICATIONS - Embodiments of the present invention provide methods for forming layers that comprise electropositive metals through ALD (atomic layer deposition) and or CVD (chemical vapor deposition) processes, layers comprising one or more electropositive metals, and semiconductor devices comprising layers comprising one or more electropositive metals. In embodiments of the invention, the layers are thin or ultrathin (films that are less than 100 {acute over (Å)} thick) and or conformal films. Additionally provided are transistor devices, metal interconnects, and computing devices comprising metal layers comprising one or more electropositive metals. | 10-17-2013 |
20130285007 | SILICON NANOCRYSTAL INKS, FILMS, AND METHODS - Silicon nanocrystal inks and films, and methods of making and using silicon nanocrystal inks and films, are disclosed herein. In certain embodiments the nanocrystal inks and films include halide-terminated (e.g., chloride-terminated) and/or halide and hydrogen-terminated nanocrystals of silicon or alloys thereof. Silicon nanocrystal inks and films can be used, for example, to prepare semiconductor devices. | 10-31-2013 |
20130285008 | NANOWIRES, METHOD OF FABRICATION THE SAME AND USES THEREOF - A method of forming a nanowire structure is disclosed. The method comprises applying on a surface of carrier liquid a layer of a liquid composition which comprises a surfactant and a plurality of nanostructures each having a core and a shell, and heating at least one of the carrier liquid and the liquid composition to a temperature selected such that the nanostructures are segregated from the surfactant and assemble into a nanowire structure on the surface. | 10-31-2013 |
20130299771 | Semiconductor Device Including Transistor - A semiconductor device has a semiconductor body including a source region, a channel region, and a drain region, which are sequentially arranged in a longitudinal direction and are doped with the same type of impurity, a gate electrode including metal, and a gate dielectric layer interposed between the semiconductor body and the gate electrode. | 11-14-2013 |
20130299772 | HEAVILY DOPED SEMICONDUCTOR NANOPARTICLES - Herein, provided are heavily doped colloidal semiconductor nanocrystals and a process for introducing an impurity to semiconductor nanoparticles, providing control of band gap, Fermi energy and presence of charge carriers. The method is demonstrated using InAs colloidal nanocrystals, which are initially undoped, and are metal-doped (Cu, Ag, Au) by adding a metal salt solution. | 11-14-2013 |
20130313512 | GRAPHENE ELECTRONIC DEVICE AND METHOD OF FABRICATING THE SAME - A graphene electronic device and a method of fabricating the graphene electronic device are provided. The graphene electronic device may include a graphene channel layer formed on a hydrophobic polymer layer, and a passivation layer formed on the graphene channel layer. The hydrophobic polymer layer may prevent or reduce adsorption of impurities to transferred graphene, and a passivation layer may also prevent or reduce adsorption of impurities to a heat-treated graphene channel layer. | 11-28-2013 |
20130313513 | SEMICONDUCTOR DEVICES HAVING MODULATED NANOWIRE COUNTS - Semiconductor devices having modulated nanowire counts and methods to form such devices are described. For example, a semiconductor structure includes a first semiconductor device having a plurality of nanowires disposed above a substrate and stacked in a first vertical plane with a first uppermost nanowire. A second semiconductor device has one or more nanowires disposed above the substrate and stacked in a second vertical plane with a second uppermost nanowire. The second semiconductor device includes one or more fewer nanowires than the first semiconductor device. The first and second uppermost nanowires are disposed in a same plane orthogonal to the first and second vertical planes. | 11-28-2013 |
20130320293 | SEMICONDUCTOR LIGHT EMITTING DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor light emitting device package includes a base unit including a main body having electrical insulation properties and at least one pair of first and second through electrodes formed in the main body in a thickness direction thereof and formed of a semiconductor material, and a light emitting structure disposed on the base unit and including first and second conductivity type semiconductor layers and an active layer interposed there between. The manufacturing process thereof may be simplified, whereby a reduction in manufacturing costs and time may be achieved. | 12-05-2013 |
20130320294 | COMMON-SUBSTRATE SEMICONDUCTOR DEVICES HAVING NANOWIRES OR SEMICONDUCTOR BODIES WITH DIFFERING MATERIAL ORIENTATION OR COMPOSITION - Common-substrate semiconductor devices having nanowires or semiconductor bodies with differing material orientation or composition and methods to form such common-substrate devices are described. For example, a semiconductor structure includes a first semiconductor device having a first nanowire or semiconductor body disposed above a crystalline substrate. The first nanowire or semiconductor body is composed of a semiconductor material having a first global crystal orientation. The semiconductor structure also includes a second semiconductor device having a second nanowire or semiconductor body disposed above the crystalline substrate. The second nanowire or semiconductor body is composed of a semiconductor material having a second global crystal orientation different from the first global orientation. The second nanowire or semiconductor body is isolated from the crystalline substrate by an isolation pedestal disposed between the second nanowire or semiconductor body and the crystalline substrate. | 12-05-2013 |
20140001432 | APPLICATIONS FOR NANOPILLAR STRUCTURES | 01-02-2014 |
20140001433 | METHODS FOR PASSIVATING A CARBONIC NANOLAYER | 01-02-2014 |
20140027708 | PHOTONIC INTEGRATED CIRCUITS BASED ON QUANTUM CASCADE STRUCTURES - Photonic integrated circuits (PICs) are based on quantum cascade (QC) structures. In embodiment methods and corresponding devices, a QC layer in a wave confinement region of an integrated multi-layer semiconductor structure capable of producing optical gain is depleted of free charge carriers to create a low-loss optical wave confinement region in a portion of the structure. Ion implantation may be used to create energetically deep trap levels to trap free charge carriers. Other embodiments include modifying a region of a passive, depleted QC structure to produce an active region capable of optical gain. Gain or loss may also be modified by partially depleting or enhancing free charge carrier density. QC lasers and amplifiers may be integrated monolithically with each other or with passive waveguides and other passive devices in a self-aligned manner. Embodiments overcome challenges of high cost, complex fabrication, and coupling loss involved with material re-growth methods. | 01-30-2014 |
20140034899 | GRAPHENE SEMICONDUCTOR AND ELECTRICAL DEVICE INCLUDING THE SAME - A graphene semiconductor including graphene and a metal atomic layer disposed on the graphene, wherein the metal atomic layer includes a metal, which is capable of charge transfer with the graphene. | 02-06-2014 |
20140042385 | CONTACTS-FIRST SELF-ALIGNED CARBON NANOTUBE TRANSISTOR WITH GATE-ALL-AROUND - A method of fabricating a semiconducting device is disclosed. A carbon nanotube is deposited on a substrate of the semiconducting device. A first contact on the substrate over the carbon nanotube. A second contact on the substrate over the carbon nanotube, wherein the second contact is separated from the first contact by a gap. A portion of the substrate in the gap between the first contact and the second contact is removed. | 02-13-2014 |
20140042386 | NANOWIRE STRUCTURES HAVING NON-DISCRETE SOURCE AND DRAIN REGIONS - Nanowire structures having non-discrete source and drain regions are described. For example, a semiconductor device includes a plurality of vertically stacked nanowires disposed above a substrate. Each of the nanowires includes a discrete channel region disposed in the nanowire. A gate electrode stack surrounds the plurality of vertically stacked nanowires. A pair of non-discrete source and drain regions is disposed on either side of, and adjoining, the discrete channel regions of the plurality of vertically stacked nanowires. | 02-13-2014 |
20140048764 | SUB-10 NM GRAPHENE NANORIBBON LATTICES - A graphene lattice comprising an ordered array of graphene nanoribbons is provided in which each graphene nanoribbon in the ordered array has a width that is less than 10 nm. The graphene lattice including the ordered array of graphene nanoribbons is formed by utilizing a layer of porous anodized alumina as a template which includes dense alumina portions and adjacent amorphous alumina portions. The amorphous alumina portions are removed and the remaining dense alumina portions which have an ordered lattice arrangement are employed as an etch mask. After removing the amorphous alumina portions, each dense alumina portion has a width which is also less than 10 nm. | 02-20-2014 |
20140054540 | DEVICE INCLUDING SEMICONDUCTOR NANOCRYSTALS & METHOD - A method of making a device comprising semiconductor nanocrystals comprises forming a first layer capable of transporting charge over a first electrode, wherein forming the first layer comprises disposing a metal layer over the first electrode and oxidizing at least the surface of the metal layer opposite the first electrode to form a metal oxide, disposing a layer comprising semiconductor nanocrystals over the oxidized metal surface, and disposing a second electrode over the layer comprising semiconductor nanocrystals. A device comprises a layer comprising semiconductor nanocrystals disposed between a first electrode and a second electrode, and a first layer capable of transporting charge disposed between the layer comprising semiconductor nanocrystals one of the electrodes, wherein the first layer capable of transporting charge comprises a metal layer wherein at least the surface of the metal layer facing the layer comprising semiconductor nanocrystals is oxidized prior to disposing semiconductor nanocrystals thereover. | 02-27-2014 |
20140061582 | SUSPENDED NANOWIRE STRUCTURE - A mandrel having vertical planar surfaces is formed on a single crystalline semiconductor layer. An epitaxial semiconductor layer is formed on the single crystalline semiconductor layer by selective epitaxy. A first spacer is formed around an upper portion of the mandrel. The epitaxial semiconductor layer is vertically recessed employing the first spacers as an etch mask. A second spacer is formed on sidewalls of the first spacer and vertical portions of the epitaxial semiconductor layer. Horizontal bottom portions of the epitaxial semiconductor layer are etched from underneath the vertical portions of the epitaxial semiconductor layer to form a suspended ring-shaped semiconductor fin that is attached to the mandrel. A center portion of the mandrel is etched employing a patterned mask layer that covers two end portions of the mandrel. A suspended semiconductor fin is provided, which is suspended by a pair of support structures. | 03-06-2014 |
20140061583 | SILICON NANOTUBE MOSFET - A nanotubular MOSFET device extends a scaling roadmap while maintaining good short channel effects and providing competitive drive current. The nanotubular MOSFET device includes a concentric tubular inner and outer gate separated from each other by a tubular shaped epitaxially grown silicon layer, and a source and drain respectively separated by spacers surrounding the tubular inner and outer gates. | 03-06-2014 |
20140084238 | NANO-PATTERNED SUBSTRATE AND EPITAXIAL STRUCTURE CROSS-REFERENCE TO RELATED APPLICATION - A nano-patterned substrate includes a substrate and a plurality of nano-structures. The substrate has an upper surface and each of the plurality of nano-structures comprises a semiconductor buffer region and a buffer region formed on the upper surface of the substrate, wherein one of the pluralities of nano-structures has a ratio of height to diameter greater than 1, and an arc-shaped top surface. | 03-27-2014 |
20140138610 | MAGNETIC DOMAIN WALL SHIFT REGISTER MEMORY DEVICE READOUT - A memory device includes a first nanowire, a second nanowire and a magnetic tunnel junction device coupling the first and second nanowires. | 05-22-2014 |
20140138611 | IN NANOWIRE, DEVICE USING THE SAME AND METHOD OF MANUFACTURING In NANOWIRE - There is provided an In nanowire including a substrate, an indium thin film formed on the substrate, an insulating film formed on the indium thin film and having at least one through hole through formation of a pattern, and an In nanowire vertically protruded from the indium thin film through the at least one through hole. | 05-22-2014 |
20140138612 | FULLERENE-DOPED NANOSTRUCTURES AND METHODS THEREFOR - Nanostructures are doped to set conductivity characteristics. In accordance with various example embodiments, nanostructures such as carbon nanotubes are doped with a halogenated fullerene type of dopant material. In some implementations, the dopant material is deposited from solution or by vapor deposition, and used to dope the nanotubes to increase the thermal and/or electrical conductivity of the nanotubes. | 05-22-2014 |
20140145143 | Carbon Nanotube Transistor Voltage Converter Circuit - A voltage converter circuit includes one or more single-walled carbon nanotube transistors, capable of handling relatively high amounts of current. The transistors are formed using a porous structure which has a number of single-walled carbon nanotubes. The porous structure may be anodized aluminum oxide or another porous material. The circuit will be especially suited for power applications, including use in portable electronic devices such as notebook computers, MP3 players, mobile phones, digital cameras, personal digital assistants, and other battery-operated devices. | 05-29-2014 |
20140151630 | PROTECTION FOR THE EPITAXIAL STRUCTURE OF METAL DEVICES - Techniques for fabricating metal devices, such as vertical light-emitting diode (VLED) devices, power devices, laser diodes, and vertical cavity surface emitting laser devices, are provided. Devices produced accordingly may benefit from greater yields and enhanced performance over conventional metal devices, such as higher brightness of the light-emitting diode and increased thermal conductivity. Moreover, the invention discloses techniques in the fabrication arts that are applicable to GaN-based electronic devices in cases where there is a high heat dissipation rate of the metal devices that have an original non-(or low) thermally conductive and/or non-(or low) electrically conductive carrier substrate that has been removed. | 06-05-2014 |
20140151631 | ASYMMETRIC BOTTOM CONTACTED DEVICE - The invention provides a Bottom Contacted 2D-layer Device (BCD) for the determination of graphene doping and chemical sensing. The device can be made by transfer of high quality CVD grown graphene films onto n- or p-doped silicon substrates yielding Schottky barrier diodes. Exposure to liquids and gases change the charge carrier density in the graphene and as a result the electrical transport of the device is modulated. The changes can be easily detected and interpreted in the doping power of the adsorbent. This principle allows one to create a new type of chemical sensor platform exploiting the monolayer nature of graphene or other carbon material. The device benefits from facile fabrication and the result is a robust device which can investigate surface chemistry on monolayer materials. | 06-05-2014 |
20140175372 | Recessed Contact to Semiconductor Nanowires - A semiconductor nanowire device includes at least one semiconductor nanowire having a bottom surface and a top surface, an insulating material which surrounds the semiconductor nanowire, and an electrode ohmically contacting the top surface of the semiconductor nanowire. A contact of the electrode to the semiconductor material of the semiconductor nanowire is dominated by the contact to the top surface of the semiconductor nanowire. | 06-26-2014 |
20140175373 | TOPOLOGICAL INSULATOR STRUCTURE - A topological insulator structure includes an insulating substrate and a magnetically doped TI quantum well film located on the insulating substrate. A material of the magnetically doped TI quantum well film is represented by a chemical formula of Cr | 06-26-2014 |
20140175374 | HYBRID CMOS NANOWIRE MESH DEVICE AND FINFET DEVICE - A semiconductor hybrid structure on an SOI substrate. A first portion of the SOI substrate containing a nanowire mesh device and a second portion of the SOI substrate containing a FINFET device. The nanowire mesh device including stacked and spaced apart semiconductor nanowires located on the substrate, each semiconductor nanowire having two end segments in which one of the end segments is connected to a source region and the other end segment is connected to a drain region; and a gate region over at least a portion of the stacked and spaced apart semiconductor nanowires, wherein each source region and each drain region is self-aligned with the gate region. The FINFET device including spaced apart fins on a top semiconductor layer on the second portion of the substrate; and a gate region over at least a portion of the fins. | 06-26-2014 |
20140175375 | HYBRID CMOS NANOWIRE MESH DEVICE AND PDSOI DEVICE - A semiconductor hybrid structure on an SOI substrate. A first portion of the SOI substrate contains a nanowire mesh device and a second portion of the SOI substrate contains a partially depleted semiconductor on insulator (PDSOI) device. The nanowire mesh device includes stacked and spaced apart semiconductor nanowires located on the SOI substrate with each semiconductor nanowire having two end segments in which one of the end segments is connected to a source region and the other end segment is connected to a drain region. The nanowire mesh device further includes a gate region over at least a portion of the stacked and spaced apart semiconductor nanowires. The PDSOI device includes a partially depleted semiconductor layer on the substrate, and a gate region over at least a portion of the partially depleted semiconductor layer. | 06-26-2014 |
20140183441 | APPARATUS FOR GENERATING/DETECTING TERAHERTZ WAVE USING GRAPHENE AND MANUFACTURING METHOD OF THE SAME - Provided is a terahertz wave generating/detecting apparatus and a method for manufacturing the same. The terahertz wave generating/detecting apparatus includes; a substrate having an active region and a transmitting region; a lower metal layer extending in a first direction on the active region and the transmitting region of the substrate; a graphene layer disposed on the lower metal layer on the active region; and upper metal layers extending in the first direction on the graphene layer of the active region and the substrate in the transmission region, wherein a terahertz wave is generated or amplified by a surface plasmon polariton that is induced on a boundary surface between the graphene layer and the lower metal layer by beated laser light applied to the graphene layer and the metal layer. | 07-03-2014 |
20140191185 | APPARATUS AND METHOD FOR FABRICATING NANO RESONATOR USING LASER INTERFERENCE LITHOGRAPHY - A method of fabricating a nano resonator, includes forming a line pattern in a first substrate, and transferring the line pattern to a second substrate including a gate electrode. The method further includes forming a source electrode and a drain electrode on the transferred line pattern. | 07-10-2014 |
20140191186 | Regenerative Nanosensor Devices - The present invention provides a regenerative nanosensor device for the detection of one or more analytes of interest. In certain embodiments, the device comprises a nanostructure having a reversible functionalized coating comprising a supramolecular assembly. Controllable and selective disruption of the assembly promotes desorption of at least part of the reversible functionalized coating thereby allowing for reuse of the regenerative device. | 07-10-2014 |
20140197370 | OVERLAP CAPACITANCE NANOWIRE - A device and method for fabricating a nanowire include patterning a first set of structures on a substrate. A dummy structure is formed over portions of the substrate and the first set of structures. Exposed portions of the substrate are etched to provide an unetched raised portion. First spacers are formed about a periphery of the dummy structure and the unetched raised portion. The substrate is etched to form controlled undercut etched portions around a portion of the substrate below the dummy structure. Second spacers are formed in the controlled undercut etched portions. Source/drain regions are formed with interlayer dielectric regions formed thereon. The dummy structure is removed. The substrate is etched to release the first set of structures. Gate structures are formed including a top gate formed above the first set of structures and a bottom gate formed below the first set of structures to provide a nanowire. | 07-17-2014 |
20140197371 | OVERLAP CAPACITANCE NANOWIRE - A device and method for fabricating a nanowire include patterning a first set of structures on a substrate. A dummy structure is formed over portions of the substrate and the first set of structures. Exposed portions of the substrate are etched to provide an unetched raised portion. First spacers are formed about a periphery of the dummy structure and the unetched raised portion. The substrate is etched to form controlled undercut etched portions around a portion of the substrate below the dummy structure. Second spacers are formed in the controlled undercut etched portions. Source/drain regions are formed with interlayer dielectic regions formed thereon. The dummy structure is removed. The substrate is etched to release the first set of structures. Gate structures are formed including a top gate formed above the first set of structures and a bottom gate formed below the first set of structures to provide a nanowire. | 07-17-2014 |
20140203238 | Wire-Last Integration Method and Structure for III-V Nanowire Devices - In one aspect, a method of fabricating a nanowire FET device includes the following steps. A layer of III-V semiconductor material is formed on an SOI layer of an SOI wafer. Fins are etched into the III-V material and SOI layer. One or more dummy gates are formed over a portion of the fins that serves as a channel region of the device. A gap filler material is deposited onto the wafer. The dummy gates are removed selective to the gap filler material, forming trenches in the gap filler material. The SOI layer is removed from portions of the fins within the trenches thereby forming suspended nanowire channels in the channel regions of the device. The trenches are filled with at least one gate material to form one or more replacement gates surrounding the nanowire channels in a gate-all-around configuration. | 07-24-2014 |
20140209854 | Nanowire Capacitor for Bidirectional Operation - A method of fabricating an electronic device includes the following steps. At least one first set and at least one second set of nanowires and pads are etched in an SOI layer of an SOI wafer. A first gate stack is formed that surrounds at least a portion of each of the first set of nanowires that serves as a channel region of a capacitor device. A second gate stack is formed that surrounds at least a portion of each of the second set of nanowires that serves as a channel region of a FET device. Source and drain regions of the FET device are selectively doped. A first silicide is formed on the source and drain regions of the capacitor device that extends at least to an edge of the first gate stack. A second silicide is formed on the source and drain regions of the FET device. | 07-31-2014 |
20140209855 | NANOWIRE STRUCTURES HAVING WRAP-AROUND CONTACTS - Nanowire structures having wrap-around contacts are described. For example, a nanowire semiconductor device includes a nanowire disposed above a substrate. A channel region is disposed in the nanowire. The channel region has a length and a perimeter orthogonal to the length. A gate electrode stack surrounds the entire perimeter of the channel region. A pair of source and drain regions is disposed in the nanowire, on either side of the channel region. Each of the source and drain regions has a perimeter orthogonal to the length of the channel region. A first contact completely surrounds the perimeter of the source region. A second contact completely surrounds the perimeter of the drain region. | 07-31-2014 |
20140239249 | RAPID BIOLOGICAL SYNTHESIS PROCESS TO PRODUCE SEMICONDUCTING CHALCOGENIDE NANOSTRUCTURES FOR TRANSISTOR OR SOLAR CELL APPLICATIONS - The process disclosed herein produces macroscopic quantities of semiconducting arsenic sulfide nanofibers within one to three days. The process is biotically influenced by the bacteria | 08-28-2014 |
20140246647 | NANOSTRUCTURE LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - A nanostructure semiconductor light emitting device includes a base layer, an insulating layer, and a plurality of light emitting nanostructures. The base layer includes a first conductivity type semiconductor. The insulating layer is disposed on the base layer and has a plurality of openings through which regions of the base layer are exposed. The light emitting nanostructures are respectively disposed on the exposed regions of the base layer and include a plurality of nanocores having a first conductivity type semiconductor and having side surfaces provided as the same crystal planes. The light emitting nanostructures include an active layer and a second conductivity type semiconductor layer sequentially disposed on surfaces of the nanocores. Upper surfaces of the nanocores are provided as portions of upper surfaces of the light emitting nanostructures, and the upper surfaces of the light emitting nanostructures are substantially planar with each other. | 09-04-2014 |
20140252305 | Enhanced Photo-Thermal Energy Conversion - Semiconducting quantum dots are applied to a fluid. The quantum dots are configured to absorb visible or near infrared light and re-radiate infrared energy that excites a fundamental vibration frequency of the fluid. | 09-11-2014 |
20140252306 | MONOLITHIC THREE DIMENSIONAL INTEGRATION OF SEMICONDUCTOR INTEGRATED CIRCUITS - A three-dimensional integrated circuit comprising top tier nanowire transistors formed on a bottom tier of CMOS transistors, with inter-tier vias, intra-tier vias, and metal layers to connect together the various CMOS transistors and nanowire transistors. The top tier first begins as lightly doped regions on a first wafer, with an oxide layer formed over the regions. Hydrogen ion implantation forms a cleavage interface. The first wafer is flipped and oxide bonded to a second wafer having CMOS devices, and the cleavage interface is thermally activated so that a portion of the lightly doped regions remains bonded to the bottom tier. Nanowire transistors are formed in the top tier layer. The sources and drains for the top tier nanowire transistors are formed by in-situ doping during epitaxial growth. After oxide bonding, the remaining process steps are performed at low temperatures so as not to damage the metal interconnects. | 09-11-2014 |
20140252307 | SINGLE ELECTRON TRANSISTOR AND METHOD FOR FABRICATING THE SAME - A transistor and a fabrication method thereof. A transistor includes a channel region including linkers, formed on a substrate, and a metallic nanoparticle grown from metal ions bonded to the linkers, a source region disposed at one end of the channel region, a drain region disposed at the other end of the channel region opposite of the source region, and a gate coupled to the channel region and serving to control migration of at least one charges in the channel region. | 09-11-2014 |
20140264253 | LEAKAGE REDUCTION STRUCTURES FOR NANOWIRE TRANSISTORS - A nanowire device of the present description may include a highly doped underlayer formed between at least one nanowire transistor and the microelectronic substrate on which the nanowire transistors are formed, wherein the highly doped underlayer may reduce or substantially eliminate leakage and high gate capacitance which can occur at a bottom portion of a gate structure of the nanowire transistors. As the formation of the highly doped underlayer may result in gate inducted drain leakage at an interface between source structures and drain structures of the nanowire transistors, a thin layer of undoped or low doped material may be formed between the highly doped underlayer and the nanowire transistors. | 09-18-2014 |
20140264254 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND ILLUMINATION APPARATUS INCLUDING THE SAME - There is provided a light emitting device including a plurality of nanoscale light emitting structures spaced apart from one another on a first conductivity-type semiconductor base layer, the plurality of nanoscale light emitting structures each including a first conductivity-type semiconductor core, an active layer and a second conductivity-type semiconductor layer, and an electrode connected to the second conductivity-type semiconductor layer. The electrode is disposed between a first nanoscale light emitting structure and a second nanoscale light emitting structure among the plurality of nanoscale light emitting structures, and the electrode has a height lower than a height of the plurality of nanoscale light emitting structures. | 09-18-2014 |
20140264255 | Method for Making a Sensor Device Using a Graphene Layer - A graphene layer is generated on a substrate. A plastic material is deposited on the graphene layer to at least partially cover the graphene layer. The substrate is separated into at least two substrate pieces. | 09-18-2014 |
20140284547 | SELF-FORMATION OF HIGH-DENSITY ARRAYS OF NANOSTRUCTURES - A method for forming nanostructures includes bonding a flexible substrate to a crystalline semiconductor layer having a two-dimensional material formed on a side opposite the flexible substrate. The crystalline semiconductor layer is stressed in a first direction to initiate first cracks in the crystalline semiconductor layer. The first cracks are propagated through the crystalline semiconductor layer and through the two-dimensional material. The stress of the crystalline semiconductor layer is released to provide parallel structures including the two-dimensional material on the crystalline semiconductor layer. | 09-25-2014 |
20140291606 | SOLUTION-ASSISTED CARBON NANOTUBE PLACEMENT WITH GRAPHENE ELECTRODES - A semiconductor device includes a substrate having at least one electrically insulating portion. A first graphene electrode is formed on a surface of the substrate such that the electrically insulating portion is interposed between a bulk portion of the substrate and the first graphene electrode. A second graphene electrode formed on the surface of the substrate. The electrically insulating portion of the substrate is interposed between the bulk portion of the substrate and the second graphene electrode. The second graphene electrode is disposed opposite the first graphene electrode to define an exposed substrate area therebetween. | 10-02-2014 |
20140291607 | INSULATING SHEET HAVING HETEROGENEOUS LAMINATED STRUCTURE, METHOD OF MANUFACTURING THE SAME, AND TRANSISTOR INCLUDING THE INSULATING SHEET - An insulating sheet has a heterogeneous laminated structure, and includes a graphene sheet and a hexagonal boron nitride sheet on the graphene sheet, the hexagonal boron nitride sheet having a root mean square (RMS) surface roughness of about 0.5 nm or less in a region having an area of about 200 nm×200 nm or less, and one or more of longitudinal and transverse lengths of about 1 mm or more. | 10-02-2014 |
20140291608 | QUANTUM DOT OPTICAL DEVICES WITH ENHANCED GAIN AND SENSITIVITY AND METHODS OF MAKING SAME - Various embodiment include optical and optoelectronic devices and methods of making same. Under one aspect, an optical device includes an integrated circuit having an array of conductive regions, and an optically sensitive material over at least a portion of the integrated circuit and in electrical communication with at least one conductive region of the array of conductive regions. Under another aspect, a film includes a network of fused nanocrystals, the nanocrystals having a core and an outer surface, wherein the core of at least a portion of the fused nanocrystals is in direct physical contact and electrical communication with the core of at least one adjacent fused nanocrystal, and wherein the film has substantially no defect states in the regions where the cores of the nanocrystals are fused. Additional devices and methods are described. | 10-02-2014 |
20140299835 | RAM MEMORY POINT WITH A TRANSISTOR - A memory cell formed of a semiconductor nanorod having its ends heavily doped to form source and drain regions and having its central portion comprising, between the source and drain regions, an N-type region surrounded on a majority of its periphery with a quasi-intrinsic P-type region, and wherein the P-type region itself is surrounded with an insulated gate. | 10-09-2014 |
20140306175 | THIN FILM TRANSISTOR - A thin film transistor includes a source electrode, a drain electrode, a semiconducting layer, a first conductive layer, a second conductive layer, an insulating layer and a gate electrode. The drain electrode is spaced apart from the source electrode. The first conductive layer is sandwiched between the source electrode and the semiconductor layer. The second conductive layer is sandwiched between the drain electrode and the semiconductor layer. The gate electrode is insulated from the source electrode, the drain electrode, the first conductive layer, the second conductive layer, and the semiconductor layer by the insulating layer. A first work-function of a first material of the first conductive layer and the second conductive layer is same as a second work-function of a second material of the semiconductor layer. | 10-16-2014 |
20140312298 | Graphene and Nanotube/Nanowire Transistor with a Self-Aligned Gate Structure on Transparent Substrates and Method of Making Same - Transistor devices having a self-aligned gate structure on transparent substrates and techniques for fabrication thereof are provided. In one aspect, a method of fabricating a transistor device includes the following steps. A channel material is formed on a transparent substrate. Source and drain electrodes are formed in contact with the channel material. A dielectric layer is deposited on the channel material. A photoresist is deposited on the dielectric layer and developed using UV light exposure through the transparent substrate. A gate metal(s) is deposited on the exposed portions of the dielectric layer and the undeveloped portions of the photoresist. The undeveloped portions of the photoresist are removed along with portions of the gate metal over the source and drain regions to form a gate of the device on the dielectric layer over the channel material which is self-aligned to the source and drain electrodes. | 10-23-2014 |
20140319452 | SINGLE TRANSISTOR RANDOM ACCESS MEMORY USING ION STORAGE IN TWO-DIMENSIONAL CRYSTALS - A single-transistor random access memory (RAM) cell may be used as universal memory. The single-transistor RAM cell generally includes a first gate, a 2D-crystal channel, a source, a drain, an ion conductor, and a second (back) gate. The single-transistor RAM cell is capable of drifting ions towards the graphene channel. The ions in turn induce charge carriers from the source into the graphene channel. The closer the ions are to the graphene channel, the higher the conductivity of the graphene channel. As the ions are spaced from the graphene channel, the conductivity of the graphene channel is reduced. Thus the presence of the charged ions adjacent to the channel is used to modify the channel's conductivity, which is sensed to indicate the state of the memory. | 10-30-2014 |
20140346436 | PRINTABLE INKS WITH SILICON/GERMANIUM BASED NANOPARTICLES WITH HIGH VISCOSITY ALCOHOL SOLVENTS - Silicon based nanoparticle inks are formulated with viscous polycyclic alcohols to control the rheology of the inks. The inks can be formulated into pastes with non-Newtonian rheology and good screen printing properties. The inks can have low metal contamination such that they are suitable for forming semiconductor structures. The silicon based nanoparticles can be elemental silicon particles with or without dopant. | 11-27-2014 |
20140353574 | FIELD EFFECT TRANSISTOR STRUCTURE COMPRISING A STACK OF VERTICALLY SEPARATED CHANNEL NANOWIRES - A field effect transistor structure comprises a source and a drain on a substrate, and a stack of n vertically separated channel nanowires isolated from the substrate and connecting the source and the drain, where n is an integer and 2≦n≦20. The channel nanowires collectively comprise at least two different thicknesses and/or at least two different dopant concentrations and/or at least two different semiconductor materials. | 12-04-2014 |
20140353575 | DETERMINATION OF OPTIMAL DIAMETERS FOR NANOWIRES - Methods of optimizing the diameters of nanowire photodiode light sensors. The method includes comparing the response of nanowire photodiode pixels having predetermined diameters with standard spectral response curves and determining the difference between the spectral response of the photodiode pixels and the standard spectral response curves. Also included are nanowire photodiode light sensors with optimized nanowire diameters and methods of scene reconstruction. | 12-04-2014 |
20140367632 | FABRICATING METHOD OF CARBON NANOTUBE-BASED FIELD EFFECT TRANSISTOR AND CARBON NANOTUBE-BASED FIELD EFFECT TRANSISTOR FABRICATED THEREBY - There are provided a fabricating method of a carbon nanotube-based field effect transistor having an improved binding force with a substrate and a carbon nanotube-based field effect transistor fabricated by the fabricating method. The method includes forming an oxide film on a substrate, forming a photoresist pattern on the oxide film, forming a metal film on the entire surface of the oxide film having the photoresist pattern, removing the photoresist by lifting off, adsorbing carbon nanotubes on the substrate from which the photoresist is removed, performing an annealing process to the substrate to which the carbon nanotubes are adsorbed, and removing the metal film. Since an adhesive strength between a substrate and carbon nanotubes increases, stability and reliability of a field effect transistor can be improved. If the field effect transistor is applied to a liquid sensor or the like, a lifespan of the sensor can be extended and reliability of a measurement result obtained by the sensor can be improved. | 12-18-2014 |
20140374694 | MANUFACTURABLE SUB-3 NANOMETER PALLADIUM GAP DEVICES FOR FIXED ELECTRODE TUNNELING RECOGNITION - A technique is provided for manufacturing a nanogap in a nanodevice. An oxide is disposed on a wafer. A nanowire is disposed on the oxide. A helium ion beam is applied to cut the nanowire into a first nanowire part and a second nanowire part which forms the nanogap in the nanodevice. Applying the helium ion beam to cut the nanogap forms a signature of nanowire material in proximity to at least one opening of the nanogap. | 12-25-2014 |
20140374695 | NANOGAP DEVICE WITH CAPPED NANOWIRE STRUCTURES - An anti-retraction capping material is formed on a surface of a nanowire that is located upon a dielectric membrane. A gap is then formed into the anti-retraction capping material and nanowire forming first and second capped nanowire structures of a nanodevice. The nanodevice can be used for recognition tunneling measurements including, for example DNA sequencing. The anti-retraction capping material serves as a mobility barrier to pin, i.e., confine, a nanowire portion of each of the first and second capped nanowire structures in place, allowing long-term structural stability. In some embodiments, interelectrode leakage through solution during recognition tunneling measurements can be minimized. | 12-25-2014 |
20150014624 | NANODEVICE AND METHOD FOR FABRICATING THE SAME - This invention is to provide a nanodevice, which is combined with an electronic device such as a diode, tunnel device and MOS transistor, integrated circuit and manufacturing method of the nanodevice. A nanodevice includes: a first insulating layer | 01-15-2015 |
20150028285 | SEMICONDUCTOR NANO LAYER STRUCTURE AND MANUFACTURING METHOD THEREOF - A method for manufacturing a semiconductor nano layer structure includes: two substrates are provided; a plurality of semiconductor nanowires are formed on one of the substrates; an absorption surface is formed on the other substrate; one of the substrates is fixed on a cylindrical roller, the cylindrical roller is brought into contact with a surface of the substrate which is stationary and is not fixed on the cylindrical roller, and rolled with a constant velocity and pressure so that the semiconductor nanowires are break, detached, transferred and absorbed, and a semiconductor nano layer structure is formed on the stationary substrate; a de-laminating process is performed to separate the semiconductor nano layer structure from the second substrate; an electric Joule heat welding process is locally performed to bond each of the semiconductor nanowires of the semiconductor nano layer structure or each semiconductor nano layer structure. | 01-29-2015 |
20150034899 | Semiconductor Device and Fabricating the Same - The present disclosure provides a method for fabricating an integrated circuit (IC) device. The method includes providing a precursor including a substrate having first and second metal-oxide-semiconductor (MOS) regions. The first and second MOS regions include first and second gate regions, semiconductor layer stacks, source/drain regions and isolation regions. The method includes exposing and oxidizing the first semiconductor layer stack to form a first outer oxide layer and a first inner nanowire, and removing the first outer oxide layer to expose the first inner nanowire in the first gate region. A first high-k/metal gate (HK/MG) stack wraps around the first inner nanowire. The method includes exposing and oxidizing the second semiconductor layer stack to form second outer oxide layer and inner nanowire, and removing the second outer oxide layer to expose the second inner nanowire in the second gate region. A second HK/MG stack wraps around the second inner nanowire. | 02-05-2015 |
20150048300 | MATERIALS, FABRICATION EQUIPMENT, AND METHODS FOR STABLE, SENSITIVE PHOTODETECTORS AND IMAGE SENSORS MADE THEREFROM - Optically sensitive devices include a device comprising a first contact and a second contact, each having a work function, and an optically sensitive material between the first contact and the second contact. The optically sensitive material comprises a p-type semiconductor, and the optically sensitive material has a work function. Circuitry applies a bias voltage between the first contact and the second contact. The optically sensitive material has an electron lifetime that is greater than the electron transit time from the first contact to the second contact when the bias is applied between the first contact and the second contact. The first contact provides injection of electrons and blocking the extraction of holes. The interface between the first contact and the optically sensitive material provides a surface recombination velocity less than 1 cm/s. | 02-19-2015 |
20150053912 | Integrate Circuit With Nanowires - The present disclosure provides an integrated circuit (IC). The IC includes a substrate having a metal-oxide-semiconductor (MOS) region. The IC further includes first gate, source and drain regions, having a first length, and second gate, source and drain regions, having a second length. A first nanowire set is disposed in the first gate region, the first nanowire set including a nanowire having a first diameter and connecting to a feature in the first source region and a feature in the first drain region. A second nanowire set is disposed in the second gate region, the second nanowire set including a nanowire having a second diameter and connecting to a feature in the second source region and a feature in the second drain region. The diameters are such that if the first length is greater than the second length, the first diameter is less than the second diameter, and vice versa. | 02-26-2015 |
20150053913 | SUSPENDED NANOWIRE STRUCTURE - A mandrel having vertical planar surfaces is formed on a single crystalline semiconductor layer. An epitaxial semiconductor layer is formed on the single crystalline semiconductor layer by selective epitaxy. A first spacer is formed around an upper portion of the mandrel. The epitaxial semiconductor layer is vertically recessed employing the first spacers as an etch mask. A second spacer is formed on sidewalls of the first spacer and vertical portions of the epitaxial semiconductor layer. Horizontal bottom portions of the epitaxial semiconductor layer are etched from underneath the vertical portions of the epitaxial semiconductor layer to form a suspended ring-shaped semiconductor fin that is attached to the mandrel. A center portion of the mandrel is etched employing a patterned mask layer that covers two end portions of the mandrel. A suspended semiconductor fin is provided, which is suspended by a pair of support structures. | 02-26-2015 |
20150060756 | OPTICAL-MICROWAVE-QUANTUM TRANSDUCER - An optical-microwave-quantum transducer can include a tapered optical fiber configured to transmit and receive optical signals. The optical-microwave-quantum transducer can also include a cantilever that can include an optical cavity that includes a nanophotonic crystal. The optical cavity can be configured to provide mechanical excitation in response to electromagnetic excitation induced by photons emitted from the tapered optical fiber. The cantilever can also include a mechanical coupler that is configured to induce electrical modulation onto a superconducting cavity in response to the mechanical excitation. The mechanical coupler can also be configured to provide mechanical excitation in response to electromagnetic excitation induced by photons from the superconducting cavity. The optical cavity can further be configured to provide electromagnetic excitation that induces optical modulation on the tapered optical fiber in response to the mechanical excitation. | 03-05-2015 |
20150097156 | PHOTODETECTOR - A photodetector | 04-09-2015 |
20150102283 | FIELD-EFFECT TRANSISTOR, SINGLE-ELECTRON TRANSISTOR AND SENSOR USING THE SAME - A sensor capable of detecting detection targets that are necessary to be detected with high sensitivity is provided. | 04-16-2015 |
20150102284 | METHODS OF NANOWIRE FUNCTIONALIZATION, DISPERSION AND ATTACHMENT - A nanowire device and a method of making a nanowire device are provided. The device includes a plurality of nanowires functionalized with different functionalizing compounds. The method includes functionalizing the nanowires with a functionalizing compound, dispersing the nanowires in a polar or semi-polar solvent, aligning the nanowires on a substrate such that longitudinal axes of the nanowires are oriented about perpendicular to a major surface of the substrate, and fixing the nanowires to the substrate. | 04-16-2015 |
20150115216 | CONVERSION OF THIN TRANSISTOR ELEMENTS FROM SILICON TO SILICON GERMANIUM - Embodiments of the present disclosure provide techniques and configurations associated with conversion of thin transistor elements from silicon (Si) to silicon germanium (SiGe). In one embodiment, a method includes providing a semiconductor substrate having a channel body of a transistor device disposed on the semiconductor substrate, the channel body comprising silicon, forming a cladding layer comprising germanium on the channel body, and annealing the channel body to cause the germanium to diffuse into the channel body. Other embodiments may be described and/or claimed. | 04-30-2015 |
20150129830 | NANOWIRE TRANSISTOR FABRICATION WITH HARDMASK LAYERS - A nanowire device of the present description may be produced with the incorporation of at least one hardmask during the fabrication of at least one nanowire transistor in order to assist in protecting an uppermost channel nanowire from damage that may result from fabrication processes, such as those used in a replacement metal gate process and/or the nanowire release process. The use of at least one hardmask may result in a substantially damage free uppermost channel nanowire in a multi-stacked nanowire transistor, which may improve the uniformity of the channel nanowires and the reliability of the overall multi-stacked nanowire transistor. | 05-14-2015 |
20150129831 | INDUCING LOCALIZED STRAIN IN VERTICAL NANOWIRE TRANSISTORS - A device includes a semiconductor substrate and a vertical nano-wire over the semiconductor substrate. The vertical nano-wire includes a bottom source/drain region, a channel region over the bottom source/drain region, and a top source/drain region over the channel region. A top Inter-Layer Dielectric (ILD) encircles the top source/drain region. The device further includes a bottom ILD encircling the bottom source/drain region, a gate electrode encircling the channel region, and a strain-applying layer having vertical portions on opposite sides of, and contacting opposite sidewalls of, the top ILD, the bottom ILD, and the gate electrode. | 05-14-2015 |
20150137067 | NANOWIRE MOSFET WITH DIFFERENT SILICIDES ON SOURCE AND DRAIN - A nanowire field effect transistor (FET) device and method for forming a nanowire FET device are provided. A nanowire FET including a source region and a drain region is formed. The nanowire FET further includes a nanowire that connects the source region and the drain region. A source silicide is formed on the source region, and a drain silicide is formed on the drain region. The source silicide is comprised of a first material that is different from a second material comprising the drain silicide. | 05-21-2015 |
20150137068 | JUNCTIONLESS NANO-ELECTRO-MECHANICAL RESONANT TRANSISTOR - A junctionless Nano-Electro-Mechanical (NEM) resonator, comprising a highly doped conductive channel connecting a drain region and a source region; the conduction channel region is movable and the overall structure is fixed at least at these two ends placed on acting the source and drain regions, respectively; at least one fixed gate electrode arranged to control a depletion charge in the highly doped conductive channel thereby modulating dimensions of a cross-section of the highly doped conductive channel. A dimension of the cross-section in the direction of an electrical field that is oriented from the fixed gate electrode to the highly doped conductive channel, is designed in such a way that it can be reduced under the effect of the depletion charge such that a full depletion in the highly doped conductive channel is achievable with the control of the fixed gate electrode. | 05-21-2015 |
20150137069 | NANOGAP DEVICE WITH CAPPED NANOWIRE STRUCTURES - An anti-retraction capping material is formed on a surface of a nanowire that is located upon a dielectric membrane. A gap is then formed into the anti-retraction capping material and nanowire forming first and second capped nanowire structures of a nanodevice. The nanodevice can be used for recognition tunneling measurements including, for example DNA sequencing. The anti-retraction capping material serves as a mobility barrier to pin, i.e., confine, a nanowire portion of each of the first and second capped nanowire structures in place, allowing long-term structural stability. In some embodiments, interelectrode leakage through solution during recognition tunneling measurements can be minimized. | 05-21-2015 |
20150144867 | SEMICONDUCTOR PHOSPHOR NANOPARTICLE AND LIGHT-EMITTING DEVICE INCLUDING THE SAME - A semiconductor phosphor nanoparticle includes a semiconductor nanoparticle and a first organic compound. An end of the first organic compound is bonded to a surface of the semiconductor nanoparticle, and the other end of the first organic compound is polymerized to form a first inorganic layer. | 05-28-2015 |
20150295036 | NANOWIRE DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a nanowire device is disclosed. The method includes providing a substrate, wherein the substrate comprises a pair of support pads, a recess disposed between the support pads, a second insulating layer disposed on the support pads, a third insulating layer disposed on a bottom of the recess, and at least one nanowire suspended between the support pads at a top portion of the recess; forming a first insulating layer on the nanowire; depositing a dummy gate material over the substrate on the first insulating layer, and patterning the dummy gate material to form a dummy gate structure surrounding a channel region; forming a first oxide layer on laterally opposite sidewalls of the dummy gate; and extending the nanowire on laterally opposite ends of the channel region to the respective support pads, so as to form a source region and a drain region. | 10-15-2015 |
20150303197 | Semiconductor Device and Fabricating the Same - An integrated circuit (IC) device comprises a substrate having a metal-oxide-semiconductor (MOS) region; a gate region disposed over the substrate and in the MOS region; and source/drain features in the MOS region and separated by the gate region. The gate region includes a fin structure and a nanowire over the fin structure. The nanowire extends from the source feature to the drain feature. | 10-22-2015 |
20150303256 | ELECTRONIC DEVICE COMPRISING NANOGAP ELECTRODES AND NANOPARTICLE - An electronic device includes a substrate and at least two electrodes spaced by a nanogap, wherein the at least two electrodes are bridged by at least one nanoparticle and wherein the at least one nanoparticle has an overlap area with the at least two electrodes higher than 2% of the area of the at least one nanoparticle. A method of manufacturing of the electronic device and the use of the electronic device in photodetector, transistor, phototransistor, optical modulator, electrical diode, photovoltaic cell or electroluminescent component are also described. | 10-22-2015 |
20150303259 | CIRCUITS USING GATE-ALL-AROUND TECHNOLOGY - A semiconductor structure includes a first gate-all-around (GAA) structure configured to form a first circuit and a second GAA structure configured to form a second circuit similar to the first circuit. The first GAA structure and the second GAA structure have a same of at least one of the following exemplary features: a number of GAA devices in which current flows from a first oxide definition (OD) region to a second OD region; a number of GAA devices in which current flows from the second OD region to the first OD region; a number of first OD region contact elements; a number of second OD region contact elements. | 10-22-2015 |
20150303270 | CONNECTION STRUCTURE FOR VERTICAL GATE ALL AROUND (VGAA) DEVICES ON SEMICONDUCTOR ON INSULATOR (SOI) SUBSTRATE - A vertical gate all around (VGAA) nanowire device circuit routing structure is disclosed. The circuit routing structure comprises a plurality of VGAA nanowire devices including a NMOS and a PMOS device. The devices are formed on a semiconductor-on-insulator substrate. Each device comprises a bottom plate and a top plate wherein one of the bottom and top plates serves as a drain node and the other serves as a source node. Each device further comprises a gate layer. The gate layer fully surrounds a vertical channel in the device. In one example, a CMOS circuit is formed with an oxide (OD) block layer that serves as a common bottom plate for the NMOS and PMOS devices. In another example, a CMOS circuit is formed with a top plate that serves as a common top plate for the NMOS device and the PMOS devices. In another example, a SRAM circuit is formed. | 10-22-2015 |
20150303350 | NANO-STRUCTURE SEMICONDUCTOR LIGHT EMITTING DEVICE - A method of manufacturing a light emitting device having a plurality of nano-light emitting structures is provided. The method comprises depositing a first conductivity-type semiconductor material on a substrate to form a base layer. A mask having a plurality of openings is formed on the base layer. The first conductivity-type nitride semiconductor material is deposited in the openings of the mask to form a plurality of nanocores having a main portion bounded by the mask and an exposed tip portion. A current blocking layer is deposited on the tip portion of the nanocores. A portion of the mask is removed to expose the main portion of the nanocore. An active material layer is deposited on the plurality of nanocores. A second conductivity-type nitride semiconductor layer is deposited on the active material layer. | 10-22-2015 |
20150307348 | MEMS DEVICE AND METHOD OF FORMING THE SAME - According to an exemplary embodiment, a method of forming a MEMS device is provided. The method includes the following operations: providing a substrate; forming a catalyst layer over the substrate; patterning the catalyst layer; forming a carbon nanotube based on the catalyst layer; forming a getter layer over the carbon nanotube and the substrate; and etching back the getter layer to expose the carbon nanotube. According to an exemplary embodiment, a method of forming a MEMS device is provided. The method includes the following operations: providing a substrate; forming a catalyst island over the substrate; heating the substrate and the catalyst island; contacting the catalyst island with a carbon-containing gas to form a carbon nanotube; forming a getter layer over the carbon nanotube and the substrate; and etching back the getter layer to expose the carbon nanotube. | 10-29-2015 |
20150318213 | TUNNEL FIELD-EFFECT TRANSISTOR AND METHOD FOR FABRICATING THE SAME - A tunnel field-effect transistor and method fabricating the same are provided. The tunnel field-effect transistor includes a drain region, a source region with opposite conductive type to the drain region, a channel region disposed between the drain region and the source region, a metal gate layer disposed around the channel region, and a high-k dielectric layer disposed between the metal gate layer and the channel region. | 11-05-2015 |
20150318214 | TUNNEL FIELD-EFFECT TRANSISTOR AND METHOD FOR FABRICTAING THE SAME - The tunnel field-effect transistor includes a drain layer, a source layer, a channel layer, a metal gate layer, and a high-k dielectric layer. The drain and source layers are of opposite conductive types. The channel layer is disposed between the drain layer and the source layer. At least one of the drain layer, the channel layer, and the source layer has a substantially constant doping concentration. The metal gate layer is disposed around the channel layer. The high-k dielectric layer is disposed between the metal gate layer and the channel layer. | 11-05-2015 |
20150318503 | FIELD EFFECT TRANSISTOR AND MANUFACTURING METHOD THEREOF - A field effect transistor is disclosed. The field effect transistor includes a substrate, a carbon nanotube formed above the substrate, a gate electrode formed on the substrate, wherein the gate electrode is formed surrounding a center portion of the carbon nanotube, and a source electrode and a drain electrode formed on the substrate, wherein the source electrode and the drain electrode are formed surrounding respective end portions of the carbon nanotube. | 11-05-2015 |
20150318504 | TUNNELING NANOTUBE FIELD EFFECT TRANSISTOR AND MANUFACTURING METHOD THEREOF - A tunneling nanotube field effect transistor includes: an insulating layer disposed on a substrate; a gate electrode disposed on the insulating layer; a source electrode and a drain electrode disposed on the insulating layer on respective adjacent sides of the gate electrode; and a carbon nanotube extending through the gate electrode, wherein the carbon nanotube is supported by the source electrode, the gate electrode, and the drain electrode, wherein the carbon nanotube includes a first portion adjacent to the source electrode and a second portion adjacent to the drain electrode, and wherein the source electrode and the gate electrode are spaced apart by an exposed section of the first portion, and the drain electrode and the gate electrode are spaced apart by an exposed section of the second portion. | 11-05-2015 |
20150325649 | Nanowires and Methods of Forming - An array of out-of-plane, nanowires may be formed spontaneously when a material is deposited over a freshly sputter-deposited porous film under high vacuum. The nanowires may be formed without an apparent catalyst. It is the nanoporous structure of the sputter-deposited porous film that confines the size of permeated material domains during its vapor deposition, which may cause a certain surface-to-volume ratio and subsequent melting point reduction, rendering the domains of the material molten or partially molten at room temperature. The release of surface energy provides a force for the domains to diffuse and to eventually erupt from the porous thin film and may form nanowires. Due to the universality of higher surface energy for nanoparticles, the present nanowires may be applicable for scalable growth of one-dimensional nanostructures of various other materials with moderate melting points. Furthermore, the absence of a catalyst in this method may eliminate the unwanted but inevitable diffusion of catalyst atoms into the nanostructures, thus allowing a route for the growth of nanostructure of higher purity and better controlled properties. | 11-12-2015 |
20150333024 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - In order to achieve both a reduction in thermal resistance and an improvement in thermal deformation absorbing property of a semiconductor device having a packaging structure in which a semiconductor chip | 11-19-2015 |
20150348969 | Methods and Apparatus for Quantum Point Contacts in CMOS Processes - Methods and apparatus for quantum point contacts. In an arrangement, a quantum point contact device includes at least one well region in a portion of a semiconductor substrate and doped to a first conductivity type; a gate structure disposed on a surface of the semiconductor substrate; the gate structure further comprising a quantum point contact formed in a constricted area, the constricted area having a width and a length arranged so that a maximum dimension is less than a predetermined distance equal to about 35 nanometers; a drain/source region in the well region doped to a second conductivity type opposite the first conductivity type; a source/drain region in the well region doped to the second conductivity type; a first and second lightly doped drain region in the at least one well region. Additional methods and apparatus are disclosed. | 12-03-2015 |
20150349216 | LIGHT EMITTING DIODE PACKAGE STRUCTURE - A light emitting diode package structure includes an encapsulation case, a phosphor layer, a substrate, and a light emitting diode chip. The encapsulation case has an accommodating space. The phosphor layer is coated on a side of the encapsulation case. The substrate is disposed in the accommodating space. The light emitting diode chip is disposed on a first surface of the substrate. A surface of the light emitting diode chip is devoid of being directly covered by a colloid, and the light emitting diode chip and the package housing are separated from each other by a distance. | 12-03-2015 |
20150357411 | P-FET WITH STRAINED SILICON-GERMANIUM CHANNEL - A method of forming a semiconductor structure includes forming a dummy gate above a semiconductor substrate. The dummy gate defines a source-drain region adjacent to the dummy gate and a channel region below the dummy gate. A silicon-germanium layer is epitaxially grown above the source-drain region with a target concentration of germanium atoms. The semiconductor structure is annealed to diffuse the germanium atoms from the silicon-germanium layer into the channel region to form a silicon-germanium channel region. | 12-10-2015 |
20150364546 | NANOSHEET FETS WITH STACKED NANOSHEETS HAVING SMALLER HORIZONTAL SPACING THAN VERTICAL SPACING FOR LARGE EFFECTIVE WIDTH - A device including a stacked nanosheet field effect transistor (FET) may include a substrate, a first channel pattern on the substrate, a second channel pattern on the first channel pattern, a gate that is configured to surround portions of the first channel pattern and portions of the second channel pattern, and source/drain regions on opposing ends of the first channel pattern and second channel pattern. The first and second channel patterns may each include a respective plurality of nanosheets arranged in a respective horizontal plane that is parallel to a surface of the substrate. The nanosheets may be spaced apart from each other at a horizontal spacing distance between adjacent ones of the nanosheets. The second channel pattern may be spaced apart from the first channel pattern at a vertical spacing distance from the first channel pattern to the second channel pattern that is greater than the horizontal spacing distance. | 12-17-2015 |
20150372082 | SEMICONDUCTOR DEVICE INCLUDING A SEMICONDUCTOR SHEET UNIT INTERCONNECTING A SOURCE AND A DRAIN - A semiconductor device includes a substrate, a first source/drain (S/D), a second S/D, and a semiconductor sheet unit. The substrate extends in a substantially horizontal direction. The first S/D is formed on the substrate. The second S/D is disposed above the first S/D. The semiconductor sheet unit extends in a substantially vertical direction and interconnects the first S/D and the second S/D. A method for fabricating the semiconductor device is also disclosed. | 12-24-2015 |
20150372083 | SEMICONDUCTOR DEVICE INCLUDING A SEMICONDUCTOR SHEET INTERCONNECTING A SOURCE REGION AND A DRAIN REGION - A semiconductor device includes a substrate, a first source/drain (S/D) region, a second S/D region, and a semiconductor sheet. The first S/D region is disposed on the substrate. The second S/D region is disposed above the first S/D region. The semiconductor sheet interconnects the first and second S/D regions and includes a plurality of turns. A method for fabricating the semiconductor device is also disclosed. | 12-24-2015 |
20150372194 | NANO-STRUCTURED SEMICONDUCTOR LIGHT-EMITTING ELEMENT - There is provided a nanostructure semiconductor light emitting device including a base layer formed of a first conductivity-type semiconductor, a first insulating layer disposed on the base layer and having a plurality of first openings exposing partial regions of the base layer, a plurality of nanocores disposed in the exposed regions of the base layer and formed of the first conductivity-type semiconductor, an active layer disposed on surfaces of the plurality of nanocores positioned to be higher than the first insulating layer, a second insulating layer disposed on the first insulating layer and having a plurality of second openings surrounding the plurality of nanocores and the active layer disposed on the surfaces of the plurality of nanocores, and a second conductivity-type semiconductor layer disposed on the surface of the active layer positioned to be higher than the second insulating layer. | 12-24-2015 |
20150380539 | Metal Gate of Gate-All-Around Transistor - The disclosure relates to a semiconductor device. An exemplary structure for a semiconductor device comprises a nanowire structure comprising a channel region between a source region and a drain region; and a metal gate surrounding a portion the channel region, wherein the metal gate comprising a first gate portion adjacent to the source region having a first thickness and a second gate portion adjacent to the drain region having a second thickness less than the first thickness. | 12-31-2015 |
20150380603 | LIGHT-EMITTING ELEMENT SUBSTRATE AND LIGHT-EMITTING ELEMENT USING THE SAME - A light-emitting element substrate and a light-emitting element using the same are disclosed. The light-emitting element substrate includes a transparent substrate and an intermediate layer. The transparent substrate has a plurality of microstructures on a surface thereof, top portion of each microstructure is a plane structure, and an adjacent interval between the plane structures is between 0.5 μm and 2.5 μm, the plurality of microstructures have gaps therebetween, and the intermediate layer is covered on the plane structures for facilitating production of epitaxial layer. In an embodiment, the gaps of the plurality of microstructures are still reserved when the epitaxial layer is grown on the plurality of microstructures so as to improve light extraction efficiency of the light-emitting element using the light-emitting element substrate. | 12-31-2015 |
20160020311 | ELECTRONIC ELEMENT - Provided is an electronic element that functions as a switch or memory without using metal nanoparticle. The electronic element comprises: one electrode | 01-21-2016 |
20160020364 | TWO STEP TRANSPARENT CONDUCTIVE FILM DEPOSITION METHOD AND GAN NANOWIRE DEVICES MADE BY THE METHOD - A method of making a semiconductor device includes depositing a first transparent conductive film (TCF) contact layer on a sidewall of a III-nitride semiconductor nanostructure by evaporation, and depositing a second TCF contact layer over the first TCF contact layer by sputtering or chemical vapor deposition (CVD). | 01-21-2016 |
20160027929 | PERFECTLY SYMMETRIC GATE-ALL-AROUND FET ON SUSPENDED NANOWIRE - A semiconductor device including a plurality of suspended nanowires and a gate structure that is present on a channel region portion of the plurality of suspended nanowires. The gate structure includes a uniform length extending from an upper surface of the gate structure to the base of the gate structure. A dielectric spacer having a graded composition is present in direct contact with the gate structure. The dielectric spacer having a uniform length extending from an upper surface of the gate structure to the base of the gate structure. Source and drain regions are present on source and drain region portions of the plurality of suspended nanowires. | 01-28-2016 |
20160035457 | FIELD EFFECT TRANSISTOR - There is provided a field effect transistor which comprises a gate insulating layer, a gate electrode, a semiconductor layer, a source electrode and a drain electrode. The gate insulating layer contains an organic compound that contains a silicon-carbon bond and a metal compound that contains a bond between a metal atom and an oxygen atom; and the metal atoms are contained in the gate insulating layer in an amount of 10 to 180 parts by weight with respect to 100 parts by weight of the total of carbon atoms and silicon atoms. This field effect transistor (FET) has high mobility and a low voltage of the threshold value, while being suppressed in leak current. | 02-04-2016 |
20160035829 | ULTRA-LONG SILICON NANOSTRUCTURES, AND METHODS OF FORMING AND TRANSFERRING THE SAME - Under one aspect, a plurality of silicon nanostructures is provided. Each of the silicon nanostructures includes a length and a cross-section, the cross-section being substantially constant along the length, the length being at least 100 microns. Under another aspect, a method of making nanostructures is provided that includes providing a silicon wafer including a thickness and first and second surfaces separated from one another by the thickness; forming a patterned layer of metal on the first surface of the silicon wafer; generating a current through the thickness of the silicon wafer, the metal oxidizing the silicon wafer in a region beneath the patterned layer of the metal; and exposing the silicon wafer to an etchant in the presence of the current, the etchant removing the oxidized region of the silicon wafer so as to define a plurality of nanostructures. Methods of transferring nanowires also are provided. | 02-04-2016 |
20160035838 | NANO-STRUCTURE ASSEMBLY AND NANO-DEVICE COMPRISING SAME - Provided are a nano-structure assembly including an insulating substrate; and a nano-structure formed on the insulating substrate, and a nano-device including the same. | 02-04-2016 |
20160043173 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor structure, a semiconductor device, and a method for forming the semiconductor device are provided. In various embodiments, the method for forming the semiconductor device includes forming transistors on a substrate. Forming each transistor includes forming a doped region on the substrate. A nanowire is formed protruding from the doped region. An interlayer dielectric layer is deposited over the doped region. A dielectric layer is deposited over the interlayer dielectric layer and surrounding each of the nanowires. A first gate layer is deposited over the dielectric layer. The dielectric layer and first gate layer are etched to expose portions of the nanowires and the interlayer dielectric layer. A second gate layer is formed over the exposed interlayer dielectric layer and surrounding the first gate layer. Then, the second gate layer was patterned to remove the second gate layer on the interlayer dielectric layer between the transistors. | 02-11-2016 |
20160043220 | TUNNELING FIELD EFFECT TRANSISTOR HAVING A THREE-SIDE SOURCE AND FABRICATION METHOD THEREOF - The present invention discloses a tunneling field effect transistor having a three-side source and a fabrication method thereof, referring to field effect transistor logic devices and circuits in CMOS ultra large scale integrated circuits (ULSI). By means of the strong depletion effect of the three-side source, the transistor can equivalently achieve a steep doping concentration gradient for the source junction, significantly optimizing the sub-threshold slope of the TFET. Meanwhile, the turn-on current of the transistor is boosted. Furthermore, due to a region uncovered by the gate between the gate and the drain, the bipolar conduction effect of the transistor is effectively inhibited, and on the other hand, in the small-size transistor a parasitic tunneling current at the corner of the source junction is inhibited. The fabrication method is simple and can be accurately controlled. By forming the channel region using an epitaxy method subsequent to etching, it facilitates to form a steeper doping concentration gradient for the source region or form a hetero-junction. Moreover, the fabrication flow of the post-gate process facilitates to integrate a high-k gate dielectric/a metal gate having good quality, further improving the performance of the transistor. | 02-11-2016 |
20160043264 | PHOTON-EFFECT TRANSISTOR - A two-terminal photon-effect transistor (PET) is described that simplifies the photo sensing pixel by combing photodiode and field effect transistor dual functions into one simple but effective unit. Photons excite electrons from the valance band of semiconducting material as the electrode-free gate to modulate resistivity between source and drain, which directly results in current amplification of photo signal without traditional photo-electrical conversion and electrical amplification dual processes. PET possesses significance in both structural simplification and functional enhancement. As an implementing example of PET, a nanowire camera (NC) with large sensing area and extremely high resolution is fabricated by integrating millions of vertically aligned nanowire arrays in-between of orthogonal top and bottom nano-stripe electrodes. Each nanowire works as independent three-dimensional (3D) PET pixel, enabling the NC an ultra-high resolution and much simplified architecture. NC has pixel size of 50 nm which is two orders higher than existing CCD and CMOS image sensors. | 02-11-2016 |
20160056336 | SEMICONDUCTOR LIGHT-EMITTING DEVICE - A semiconductor light-emitting device includes a substrate, a first reflective layer disposed on the substrate and including first openings, a first conductivity-type semiconductor layer grown in and extending from the first openings and connected on the first reflective layer, a second reflective layer disposed on the first conductivity-type semiconductor layer and including second openings having lower surfaces disposed to be spaced apart from upper surfaces of the first openings, and a plurality of light-emitting nanostructures including nanocores extending from the second openings and formed of a first conductivity-type semiconductor material, and active layers and second conductivity-type semiconductor layers sequentially disposed on the nanocores. | 02-25-2016 |
20160064482 | NANOWIRE TRANSISTOR STRUCTURES WITH MERGED SOURCE/DRAIN REGIONS USING AUXILIARY PILLARS - A nanowire transistor structure is fabricated by using auxiliary epitaxial nucleation source/drain fin structures. The fin structures include semiconductor layers integral with nanowires that extend between the fin structures. Gate structures are formed between the fin structures such that the nanowires extend through the gate conductors. Following spacer formation and nanowire chop, source/drain regions are grown epitaxially between the gate structures. | 03-03-2016 |
20160064531 | METHOD TO FORM A CYLINDRICAL GERMANIUM NANOWIRE DEVICE ON BULK SILICON SUBSTRATE - A method for manufacturing a semiconductor device includes providing a substrate structure having a substrate and a cavity in the substrate, epitaxially growing a SiGe nanowire in the cavity, and removing a portion of the substrate surrounding the SiGe nanowire to substantially expose a surface of the SiGe nanowire. The method further includes oxidizing the exposed surface of the SiGe nanowire to form an oxide layer, removing the oxide layer by etching, and repeating the oxidizing and removing steps to form a suspended germanium nanowire in the cavity. | 03-03-2016 |
20160079358 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor structure, and methods for forming the semiconductor device are provided. In various embodiments, the semiconductor device includes a substrate, source/drain regions over the substrate, a plurality of nanowires over the substrate and sandwiched by the source/drain regions, a gate dielectric layer surrounding the plurality of nanowires, and a gate layer surrounding the gate dielectric layer. | 03-17-2016 |
20160079361 | Silicide Region of Gate-All-Around Transistor - The disclosure relates to a semiconductor device. An exemplary structure for a semiconductor device comprises a substrate; a nanowire structure protruding from the substrate comprising a channel region between a source region and a drain region; a pair of silicide regions extending into opposite sides of the source region, wherein each of the pair of silicide regions comprising a vertical portion adjacent to the source region and a horizontal portion adjacent to the substrate; and a metal gate surrounding a portion the channel region. | 03-17-2016 |
20160104769 | LAYERED STRUCTURE OF A P-TFET - A p-type Tunnel Field-Effect Transistor comprises a drain p-type semiconductor region, a source n-type semiconductor region, and at least one gate stack. The source n-type semiconductor region comprises a lowly doped section with a length of at least 10 nm and with a doping level of n-type dopant elements below 5×10 | 04-14-2016 |
20160111553 | LOCALIZED FIN WIDTH SCALING USING A HYDROGEN ANNEAL - Transistors including one or more semiconductor fins formed on a substrate. The one or more semiconductor fins are thinner in a channel region than in source and drain regions and have rounded corners formed by an anneal in a gaseous environment. A gate dielectric layer is on the channel region of the one or more semiconductor fins, conforming to the contours of the one or more semiconductor fins. A gate structure is on the gate dielectric layer. | 04-21-2016 |
20160118460 | SEMICONDUCTOR DEVICE - A semiconductor device comprises: a substrate; a multilayer semiconductor layer located on the substrate; a source located on the multilayer semiconductor layer, the source including a first source portion inside an active region and a second source portion inside a passive region; a drain located on the multilayer semiconductor layer, the drain including a first drain portion inside the active region and a second drain region inside the passive region; a gate located on the multilayer semiconductor layer, the gate including a first gate portion inside the active region and a second gate portion inside the passive region, and the first gate portion being in a form of interdigital among the first source portion and the first drain portion; and a heat dissipating layer disposed at one or more of the first source portion, the first drain portion, the first gate portion, the second source portion, the second drain portion and the second gate portion. | 04-28-2016 |
20160126310 | S/D CONNECTION TO INDIVIDUAL CHANNEL LAYERS IN A NANOSHEET FET - A field effect transistor (FET) and a method to form the FET are disclosed. The FET comprises a channel region comprising a nanosheet layer/sacrificial layer stack. The stack comprises at least one nanosheet layer/sacrificial layer pair. Each nanosheet layer/sacrificial layer pair comprises an end surface. A conductive material layer is formed on the end surface of the pairs, and a source/drain contact is formed on the conductive material layer. In one embodiment, the sacrificial layer of at least one pair further may comprise a low-k dielectric material proximate to the end surface of the pair. A surface of the low-k dielectric material proximate to the end surface of the pair is in substantial alignment with the end surface of the nanosheet layer. Alternatively, the surface of the low-k dielectric material proximate to the end surface of the pair is recessed with respect to the end surface of the nanosheet layer. | 05-05-2016 |
20160133648 | JUNCTIONLESS TUNNEL FET WITH METAL-INSULATOR TRANSITION MATERIAL - Embodiments of the present disclosure provide an integrated circuit (IC) structure, which can include: a doped semiconductor layer having a substantially uniform doping profile; a first gate structure positioned on the doped semiconductor layer; and a second gate structure positioned on the doped semiconductor layer, the second gate structure including a metal-insulator transition material and a gate dielectric layer separating the metal-insulator transition material from the doped semiconductor layer. | 05-12-2016 |
20160133695 | A METHOD OF INHIBITING LEAKAGE CURRENT OF TUNNELING TRANSISTOR, AND THE CORRESPONDING DEVICE AND A PREPARATION METHOD THEREOF - Provided are a method for suppressing a leakage current of a tunnel field-effect transistor (TFET), a corresponding device, and a manufacturing method, related to the field of field-effect transistor logic devices and circuits in CMOS ultra large-scale integration (ULSI). By inserting an insulating layer ( | 05-12-2016 |
20160133843 | PURIFICATION OF CARBON NANOTUBES VIA SELECTIVE HEATING - The present invention provides methods for purifying a layer of carbon nanotubes comprising providing a precursor layer of substantially aligned carbon nanotubes supported by a substrate, wherein the precursor layer comprises a mixture of first carbon nanotubes and second carbon nanotubes; selectively heating the first carbon nanotubes; and separating the first carbon nanotubes from the second carbon nanotubes, thereby generating a purified layer of carbon nanotubes. Devices benefiting from enhanced electrical properties enabled by the purified layer of carbon nanotubes are also described. | 05-12-2016 |
20160141361 | NANOWIRE MOSFET WITH SUPPORT STRUCTURES FOR SOURCE AND DRAIN - Transistor devices and methods for forming transistor devices are provided. A transistor device includes a semiconductor substrate and a device layer. The device layer includes a source region and a drain region connected by a suspended nanowire channel. First and second etch stop layers are respectively arranged beneath the source region and the drain region. Each of the etch stop layers forms a support structure interposed between the semiconductor substrate and the respective source and drain regions. | 05-19-2016 |
20160141366 | Field Effect Transistors and Methods of Forming Same - Semiconductor devices and methods of forming the same are provided. A first gate stack is formed over a substrate, wherein the first gate stack comprises a first ferroelectric layer. A source/channel/drain stack is formed over the first gate stack, wherein the source/channel/drain stack comprises one or more 2D material layers. A second gate stack is formed over the source/channel/drain stack, wherein the second gate stack comprises a second ferroelectric layer. | 05-19-2016 |
20160163796 | SEMICONDUCTOR DEVICES WITH STRUCTURES FOR SUPPRESSION OF PARASITIC BIPOLAR EFFECT IN STACKED NANOSHEET FETS AND METHODS OF FABRICATING THE SAME - A device may include a nanosheet field effect transistor (FET) that may include a substrate, a well that is doped with impurities at a surface of the substrate, a channel including a plurality of stacked nanosheets, a gate, a conductive material, and an isolation layer. Ones of the plurality of stacked nanosheets may include a semiconductor material that may be doped with impurities of the same conductivity type as the impurities of the well. The conductive material may be adjacent the plurality of nanosheets and may electrically connect ones of the plurality of nanosheets to the well. The isolation layer may electrically insulate the well from the workfunction metal. | 06-09-2016 |
20160163801 | GROUP III NITRIDE SUBSTRATES AND THEIR FABRICATION METHOD - Group III nitride substrate having a first side of nonpolar or semipolar plane and a second side has more than one stripe of metal buried, wherein the stripes are perpendicular to group III nitride's c-axis. More than 90% of stacking faults exist over metal stripes. Second side may expose a nonpolar or semipolar plane. Also disclosed is a group III nitride substrate having a first side of nonpolar or semipolar plane and a second side with exposed nonpolar or semipolar plane. The substrate contains bundles of stacking faults with spacing larger than 1 mm. The invention also provides methods of fabricating the group III nitride substrates above. | 06-09-2016 |
20160163842 | FORMATION OF CMOS DEVICE USING CARBON NANOTUBES - A method, and the resulting structure, of making a CMOS device from carbon nanotube substrate, where a carbide contact is formed in a source drain region. The carbide is formed prior to the gate structure by reacting a glassy carbon and a metal. | 06-09-2016 |
20160172442 | CIRCUITS USING GATE-ALL-AROUND TECHNOLOGY | 06-16-2016 |
20160172596 | Photolithography Based Fabrication of 3D Structures | 06-16-2016 |
20160181557 | COBALT-CARBON EUTECTIC METAL ALLOY OHMIC CONTACT FOR CARBON NANOTUBE FIELD EFFECT TRANSISTORS | 06-23-2016 |
20160197145 | TUNNELLING FIELD EFFECT TRANSISTOR | 07-07-2016 |
20160197172 | ELECTRODE PAIR, METHOD FOR FABRICATING THE SAME, SUBSTRATE FOR DEVICE, AND DEVICE | 07-07-2016 |
20160380098 | DOUBLE EXPONENTIAL MECHANISM CONTROLLED TRANSISTOR - The present disclosure relates to a tunnel FET device with a steep sub-threshold slope, and a corresponding method of formation. In some embodiments, the tunnel FET device has a dielectric layer arranged over a substrate. A conductive gate electrode and a conductive drain electrode are arranged over the dielectric layer. A conductive source electrode contacts the substrate at a first position located along a first side of the conductive gate electrode. The conductive drain electrode is arranged at a second position located along the first side of the conductive gate electrode. By arranging the conductive gate electrode over the dielectric layer at a position laterally offset from the conductive drain electrode, the conductive gate electrode is able to generate an electric field that controls tunneling of minority carriers, which can change the effective barrier height of the tunnel barrier, and thereby improving a sub-threshold slope of the tunnel FET device. | 12-29-2016 |
20180025200 | LUMINESCENT FILM WITH QUANTUM DOTS | 01-25-2018 |
20190148143 | A METHOD OF FORMING AN APPARATUS COMPRISING QUANTUM DOTS | 05-16-2019 |
20190148545 | PRECISE JUNCTION PLACEMENT IN VERTICAL SEMICONDUCTOR DEVICES USING ETCH STOP LAYERS | 05-16-2019 |