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257 - Active solid-state devices (e.g., transistors, solid-state diodes)

257001000 - BULK EFFECT DEVICE

257002000 - Bulk effect switching in amorphous material

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DocumentTitleDate
20110175053NONVOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a nonvolatile memory device includes a substrate, first electrodes, a first and a second interelectrode insulating layer, second electrodes, a memory portion and a first protrusion. The first electrodes are provided on the substrate and extend in a first direction. The first interelectrode insulating layer is provided between the first electrodes. The second electrodes are opposed to the first electrodes and extend in a second direction crossing the first direction. The second interelectrode insulating layer is provided between the second electrodes. The memory portion is provided between the first electrode and the second electrode. The first protrusion is conductive and provided at least one of between the first electrode and the memory portion and between the first interelectrode insulating layer and the memory portion, and between the second electrode and the memory portion and between the second interelectrode insulating layer and the memory portion.07-21-2011
20130043456NONVOLATILE MEMORY CELL, NONVOLATILE MEMORY DEVICE AND METHOD FOR DRIVING THE SAME - A nonvolatile memory cell is able to reduce the size per the unit area by employing a dual gate structure where the chalcogenide compound is used for a channel. The nonvolatile memory cell includes a phase-change layer, a first and a second gate that are in contact with sides of the phase-change layer to face each other across the phase-in change layer and control a current flowing through the phase-change layer by each gate being arranged to induce the phase transition of the phase-change layer independently of the other.02-21-2013
20130043455Vertical Cross Point Arrays For Ultra High Density Memory Applications - An ultra-high-density vertical cross-point array comprises a plurality of horizontal line layers having horizontal lines interleaved with a plurality of vertical lines arranged in rows and columns. The vertical lines are interleaved with the horizontal lines such that a row of vertical lines is positioned between each consecutive pair of horizontal lines in each horizontal line layer. Each vertical line comprises a center conductor surrounded by a single or multi-layered memory film. Accordingly, when interleaved with the horizontal lines, two-terminal memory cells are integrally formed between the center conductor of each vertical line and each crossing horizontal line. By configuring the vertical and horizontal lines so that a row of vertical lines is positioned between each consecutive pair of horizontal lines, a unit memory cell footprint of just 2F02-21-2013
20100155689Quad memory cell and method of making same - A non-volatile memory device includes a first electrode, a diode steering element, at least three resistivity switching storage elements, and a second electrode. The diode steering element electrically contacts the first electrode and the at least three resistivity switching storage elements. The second electrode electrically contacts only one of the at least three resistivity switching storage elements.06-24-2010
20120161096PHASE CHANGE MEMORY DEVICE WITH VOLTAGE CONTROL ELEMENTS - A phase change memory device with reduced programming disturbance and its operation are described. The phase change memory includes an array with word lines and bit lines and voltage controlling elements coupled to bit lines adjacent to an addressed bit line to maintain the voltage of the adjacent bit lines within an allowed range.06-28-2012
20130134383NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A non-volatile memory device and a method of manufacturing the same are provided. A first portion stack having a first circuit element including at least one layer selected from at least one diode layer, at least one variable resistive layer, and interconnection layer is formed on a first substrate. A second portion stack having a second circuit element including at least the other layer selected from the at least one diode layer, the at least variable resistive layer, and the at least interconnection layer is formed on a second substrate. The first circuit element and the second circuit element are bonded together and the second substrate is removed.05-30-2013
20080258129Phase-Change Memory Device - A phase-change memory device has a plurality of first wiring lines WL extending in parallel to each other, a plurality of second wiring lines BL which are disposed to cross the first wiring lines WL while being separated or isolated therefrom, and memory cells MC which are disposed at respective cross points of the first wiring lines WL and the second wiring lines BL and each of which has one end connected to a first wiring line WL and the other end connected to a second wiring line BL. The memory cell MC has a variable resistive element VR which stores as information a resistance value determined due to phase change between crystalline and amorphous states thereof, and a Schottky diode SD which is connected in series to the variable resistive element VR.10-23-2008
20100163835CONTROLLING THE CIRCUITRY AND MEMORY ARRAY RELATIVE HEIGHT IN A PHASE CHANGE MEMORY FEOL PROCESS FLOW - A CMOS logic portion embedded with a PCM portion is recessed by a gate structure height as measured by a thickness of a gate oxide and a polysilicon gate to provide planarity of the CMOS logic portion with the PCM portion is described.07-01-2010
20100163836LOW-VOLUME PHASE-CHANGE MATERIAL MEMORY CELL - A memory device includes a memory array comprising a plurality of storage locations disposed above a plurality of generally parallel lines, where each storage location comprises a programmable material disposed on a sidewall of a conductive element.07-01-2010
20100072454EXPOSURE METHOD, AND SEMICONDUCTOR DEVICE - An exposure method includes an exposure process for exposing a substrate through a halftone mask with quadrupole illumination to form plural columnar portions that are disposed into a matrix shape in a first direction and a second direction orthogonal to the first direction. The halftone mask includes a first pattern that is extended in the first direction and disposed at predetermined pitches in the second direction; and a second pattern that is extended in the second direction and disposed at predetermined pitches in the first direction such that an intersection portion intersecting the first pattern is formed. The pitches and widths of the patterns on the halftone mask are configured such that zero-order diffracted light intensity and first-order diffracted light intensity, diffracted by the halftone mask, are substantially matched with each other and such that a first-order diffracted light phase is inverted with respect to a zero-order diffracted light phase.03-25-2010
20100072453Phase-Changeable Fuse Elements and Memory Devices Containing Phase-Changeable Fuse Elements and Memory Cells Therein - Non-volatile memory devices include an array of phase-changeable memory cells, which have first phase-changeable material patterns therein, and at least one phase-changeable fuse element. This phase-changeable fuse element includes a second phase-changeable material pattern therein with a higher crystallization temperature relative to the first phase-changeable material patterns in the array of phase-changeable memory cells. This higher crystallization temperature may be greater than about 300° C. According to additional embodiments of the present invention, the at least one phase-changeable fuse element includes a composite of the second phase-changeable material pattern and a third phase-changeable material pattern, which is formed of the same material at the first phase-changeable material patterns.03-25-2010
20130075689STACKABLE NON-VOLATILE RESISTIVE SWITCHING MEMORY DEVICE AND METHOD - A memory device includes a first plurality of memory cells arranged in a first crossbar array, a first thickness of dielectric material overlying the first plurality of memory cells, and a second plurality of memory cells arranged in a second crossbar array overlying the first thickness of dielectric material. The memory device further includes a second thickness of dielectric material overlying the second plurality of memory cells. In a specific embodiment, the memory device further includes a Nth thickness of dielectric material overlying an Nth plurality of memory cells, where N is an integer ranging from 3 to 8.03-28-2013
20100108982ELECTRONIC DEVICES INCLUDING CARBON NANO-TUBE FILMS HAVING CARBON-BASED LINERS, AND METHODS OF FORMING THE SAME - Methods in accordance with this invention form a microelectronic structure by forming a carbon nano-tube (“CNT”) layer, and forming a carbon layer (“carbon liner”) above the CNT layer, wherein the carbon liner comprises: (1) a first portion disposed above and in contact with the CNT layer; and/or (2) a second portion disposed in and/or around one or more carbon nano-tubes in the CNT layer. Numerous other aspects are provided.05-06-2010
20100108981ELECTRONIC DEVICES INCLUDING CARBON NANO-TUBE FILMS HAVING BORON NITRIDE-BASED LINERS, AND METHODS OF FORMING THE SAME - Methods in accordance with this invention form a microelectronic structure by forming a carbon nano-tube (“CNT”) layer, and forming a boron nitride layer (“BN liner”) above the CNT layer, wherein the BN liner comprises: (1) a first portion disposed above and in contact with the CNT layer; and/or (2) a second portion disposed in and/or around one or more carbon nano-tubes in the CNT layer. Numerous other aspects are provided.05-06-2010
20100108980RESISTIVE MEMORY ARRAY - The invention is directed to a resistive memory cell on a substrate. The resistive memory cell comprises a first gate, a second gate, a common doped region, a contact plug, a bit line and a resistive memory element. The first gate and the second gate are separately disposed on the substrate. Notably, the first length of the first gate is different from the second length of the second gate. Furthermore, the common doped region of the first gate and the second gate is disposed in the substrate. The contact plug is electrically connected to the common doped region and the bit line is disposed over the substrate. Moreover, the resistive memory element is connected between the contact plug and the bit line.05-06-2010
20130082232Multi Layered Conductive Metal Oxide Structures And Methods For Facilitating Enhanced Performance Characteristics Of Two Terminal Memory Cells - A memory cell including a two-terminal re-writeable non-volatile memory element having at least two layers of conductive metal oxide (CMO), which, in turn, can include a first layer of CMO including mobile oxygen ions, and a second layer of CMO formed in contact with the first layer of CMO to cooperate with the first layer of CMO to form an ion obstruction barrier. The ion obstruction barrier is configured to inhibit transport or diffusion of a subset of mobile ion to enhance, among other things, memory effects and cycling endurance of memory cells. At least one layer of an insulating metal oxide that is an electrolyte to the mobile oxygen ions and configured as a tunnel barrier is formed in contact with the second layer of CMO.04-04-2013
20100327254Methods to improve electrode diffusions in two-terminal non-volatile memory devices - A non-volatile memory device includes a plurality of pillars, where each of the plurality of pillars contains a non-volatile memory cell containing a steering element and a storage element and at least one of a top corner or a bottom corner of each of the plurality of pillars is rounded. A method of making non-volatile memory device includes forming a stack of device layers, and patterning the stack to form a plurality of pillars, where each of the plurality of pillars contains a non-volatile memory cell that contains a steering element and a storage element, and where at least one of top corner or bottom corner of each of the plurality of pillars is rounded.12-30-2010
20090302303Thin film memory system - An electronic system includes at least one reduced-complexity integrated circuit memory coupled to a memory controller. By reducing the complexity of each integrated circuit memory and concentrating the complexity within the memory controller, overall system costs may be greatly reduced and reliability improved.12-10-2009
20120217466Digital Potentiometer Using Third Dimensional Memory - A digital potentiometer using third dimensional memory includes a switch configured to electrically couple one or more resistive elements with a first pin and a second pin, and a non-volatile register configured to control the switch. In one example, the non-volatile register can include a BEOL non-volatile memory element, such as a third dimensional memory element. The non-volatile register can include a FEOL active circuitry portion that is electrically coupled with the BEOL non-volatile memory element to implement the non-volatile register. The resistive elements can be BEOL resistive elements that can be fabricated on the same plane or a different plane than the BEOL non-volatile memory elements. The BEOL non-volatile memory elements and the BEOL resistive elements can retain stored data in the absence of power and the stored data can be non-destructively determined by application of a read voltage.08-30-2012
20120112156Non-Volatile Memory Devices Having Resistance Changeable Elements And Related Systems And Methods - A non-volatile memory device may include a first wordline on a substrate, an insulating layer on the first wordline, and a second wordline on the insulating layer so that the insulating layer is between the first and second wordlines. A bit pillar may extend adjacent the first wordline, the insulating layer, and the second wordline in a direction perpendicular with respect to a surface of the substrate, and the bit pillar may be electrically conductive. In addition, a first memory cell may include a first resistance changeable element electrically coupled between the first wordline and the bit pillar, and a second memory cell may include a second resistance changeable element electrically coupled between the second wordline and the bit pillar. Related methods and systems are also discussed.05-10-2012
20120112155INTERCONNECTS FOR STACKED NON-VOLATILE MEMORY DEVICE AND METHOD - A method of forming a vertical interconnect for a memory device. The method includes providing a substrate having a surface region and defining a cell region, a first peripheral region, and a second peripheral region. A first thickness of dielectric material is formed overlying the surface region. A first bottom wiring structure spatially configured to extend in a first direction is formed overlying the first dielectric material for a first array of devices. A second thickness of a dielectric material is formed overlying the first wiring structure. The method includes forming an opening region in the first peripheral region. The opening region is configured to extend in a portion of at least the first thickness of dielectric material and the second thickness of dielectric material to expose a portion of the first wiring structure and to expose a portion of the substrate. A second bottom wiring material is formed overlying the second thickness of dielectric material and filling the opening region to form a vertical interconnect structure in the first peripheral region. A second bottom wiring structure is formed from the second wiring material for a second array of devices. The second bottom wiring structure is separated from the first bottom wiring structure by at least the second thickness of dielectric material and spatially configured to extend in the first direction. The first wiring structure and the second wiring structure are electrically connected by the vertical interconnect structure in the first peripheral region to a control circuitry on the substrate.05-10-2012
20130062590METHOD FOR MANUFACTURING NONVOLATILE STORAGE DEVICE AND NONVOLATILE STORAGE DEVICE - According to one embodiment, a method for manufacturing a nonvolatile storage device. The device includes a plurality of first conductive layers each extending in a first direction, a plurality of second conductive layers each extending in a second direction and spaced from the first layers, and memory cells each provided between the first layers and the second layers and including a rectifying element including a semiconductor layer, and a variable resistance element stacked with the rectifying element. The method includes a film formation step, a heating step and a patterning step. The film formation step is configured to form a rectifying element material film including an amorphous semiconductor film. The heating step is configured to heat the rectifying element material film. The patterning step is configured to form the rectifying element including the semiconductor layer by patterning the rectifying element material film after the heating step.03-14-2013
20120223286ELECTROFORMING-FREE NANOSCALE SWITCHING DEVICE - A nanoscale switching device is constructed such that an electroforming process is not needed to condition the device for normal switching operations. The switching device has an active region disposed between two electrodes. The active region has at least one switching layer formed of a switching material capable of transporting dopants under an electric field, and at least one conductive layer formed of a dopant source material containing dopants that can drift into the switching layer under an electric field. The switching layer has a thickness about 6 nm or less.09-06-2012
20110012084RESISTOR RANDOM ACCESS MEMORY CELL WITH REDUCED ACTIVE AREA AND REDUCED CONTACT AREAS - A memory device has a sidewall insulating member with a sidewall insulating member length according to a first spacer layer thickness. A first electrode formed from a second spacer layer having a first electrode length according to a thickness of a second spacer layer and a second electrode formed from the second spacer layer having a second electrode length according to the thickness of the second spacer layer are formed on sidewalls of the sidewall insulating member. A bridge of memory material having a bridge width extends from a top surface of the first electrode to a top surface of the second electrode across a top surface of the sidewall insulating member, wherein the bridge comprises memory material.01-20-2011
20130161583Stacked RRAM Array With Integrated Transistor Selector - The present invention provides a resistive memory array arranged in a 3D stack comprising a plurality of resistivity switching memory elements laid out in an array in a first and second direction, and stacked in a third direction, a plurality of first electrodes and a plurality of second electrodes extending in the first direction, each first electrode and each second electrode being associated with the at least one resistivity switching memory element, and a plurality of transistor devices, each transistor device being electrically coupled to one of the resistivity switching memory elements, an inversion or accumulation channel of a transistor device being adapted for forming a switchable resistivity path in the third direction, between the electrically coupled resistivity switching memory element and the associated second electrode, wherein the memory array furthermore comprises at least one third electrode provided in a trench through the stack.06-27-2013
20100123117NON VOLATILE MEMORY CELLS INCLUDING A FILAMENT GROWTH LAYER AND METHODS OF FORMING THE SAME - A non volatile memory cell that includes a first electrode; a variable resistive layer disposed on the first electrode; a filament growth layer disposed on the variable resistive layer, the filament growth layer including dielectric material and metal atoms; and a second electrode. In other embodiments, a memory array is disclosed that includes a plurality of non volatile memory cells, each non volatile memory cell including a first electrode; a variable resistive layer disposed on the first electrode; a filament growth layer disposed on the variable resistive layer, the filament growth layer including clusters of a first electrically conductive atomic component interspersed in an oxidized second atomic component; and a second electrode; at least one word line; and at least one bit line, wherein the word line is orthogonal to the bit line and each of the plurality of non volatile memory cells are operatively coupled to a word line and a bit line. In still other embodiments, methods are disclosed that include forming a non volatile memory cell include forming a first electrode; forming a variable resistive layer on the first electrode; depositing a two phase alloy layer on the variable resistive layer; converting the two phase alloy layer to a filament growth layer; and depositing a second electrode on the filament growth layer, thereby forming a non volatile memory cell.05-20-2010
20130214241DISTURB-RESISTANT NON-VOLATILE MEMORY DEVICE AND METHOD - A method of forming a disturb-resistant non volatile memory device. The method includes providing a semiconductor substrate having a surface region and forming a first dielectric material overlying the surface region. A first wiring material overlies the first dielectric material, a doped polysilicon material overlies the first wiring material, and an amorphous silicon switching material overlies the said polysilicon material. The switching material is subjected to a first patterning and etching process to separating a first strip of switching material from a second strip of switching spatially oriented in a first direction. The first strip of switching material, the second strip of switching material, the contact material, and the first wiring material are subjected to a second patterning and etching process to form at least a first switching element from the first strip of switching material and at least a second switching element from the second strip of switching material, and a first wiring structure comprising at least the first wiring material and the contact material. The first wiring structure being is in a second direction at an angle to the first direction.08-22-2013
20130207068MEMORY CELLS AND MEMORY CELL FORMATION METHODS USING SEALING MATERIAL - Memory cells, arrays of memory cells, and methods of forming the same with sealing material on sidewalls thereof are disclosed herein. One example of forming a memory cell includes forming a stack of materials, forming a trench to a first depth in the stack of materials such that a portion of at least one of the active storage element material and the active select device material is exposed on sidewalls of the trench. A sealing material is formed on the exposed portion of the at least one of the active storage element material and the active select device material and the trench is deepened such that a portion of the other of the at least one of the active storage element material and the active select device material is exposed on the sidewalls of the trench.08-15-2013
20110278532TRI LAYER METAL OXIDE REWRITABLE NON VOLATILE TWO TERMINAL MEMORY ELEMENT - A memory using a tunnel barrier that has a variable effective width is disclosed. A memory element includes a tunneling barrier and a conductive material. The conductive material typically has mobile ions that either move towards or away from the tunneling barrier in response to a voltage across the memory element. A low conductivity region is either formed or destroyed. It can be formed by either the depletion or excess ions around the tunneling barrier, or by the mobile ions combining with complementary ions. It may be destroyed by either reversing the forming process or by reducing the tunneling barrier and injecting ions into the conductive material. The low conductivity region increases the effective width of the tunnel barrier, making electrons tunnel a greater distance, which reduces the memory element's conductivity. By varying conductivity multiple states can be created in the memory cell.11-17-2011
20110127487ELECTRONIC DEVICE FOR A RECONFIGURABLE LOGIC CIRCUIT - The invention relates to an electronic device, comprising a field effect transistor and a resistive switch electrically coupled with each other, wherein the resistive switch is configured to be switched between a state of low resistance and a state of high resistance.06-02-2011
20100171091Memory array for increased bit density and method of forming the same - A memory array having a plurality of resistance variable memory units and method for forming the same are provided. Each memory unit includes a first electrode, a resistance variable material over the first electrode, and a first second-electrode over the resistance variable material. The first second-electrode is associated with the first electrode to define a first memory element. Each memory unit further includes a second second-electrode over the resistance variable material. The second-second electrode is associated with the first electrode to define a second memory element.07-08-2010
20110284817NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - In a nonvolatile semiconductor memory device, there is provided a technique which promotes microfabrication by reducing a thickness of the device as suppressing an OFF current of a polysilicon diode which is a selective element. A polysilicon layer to which an impurity is doped at low concentration and which becomes an electric-field relaxation layer of the polysilicon diode which is a selective element of a resistance variable memory is formed so as to be divided into two or more layers such as polysilicon layers. In this manner, it is suppressed to form the crystal grain boundaries thoroughly penetrating between an n-type polysilicon layer and a p-type polysilicon layer in the electric-field relaxation layer, and therefore, it is prevented to generate a leakage current flowing through the crystal grain boundaries in application of a reverse-bias voltage without increasing a height of the polysilicon diode.11-24-2011
20090166605PHASE CHANGE MEMORY ELEMENTS USING SELF-ALIGNED PHASE CHANGE MATERIAL LAYERS AND METHOS OF MAKING AND USING SAME - A phase change memory element and method of forming the same. The memory element includes a substrate supporting a first electrode. An insulating material element is positioned over the first electrode, and a phase change material layer is formed over the first electrode and surrounding the insulating material element such that the phase change material layer has a lower surface that is in electrical communication with the first electrode. The memory element also has a second electrode in electrical communication with an upper surface of the phase change material layer.07-02-2009
20120025164VARIABLE RESISTANCE MEMORY WITH A SELECT DEVICE - According to various embodiments, a variable resistance memory element and memory element array that uses variable resistance changes includes a select device, such as an ovonic threshold switch. The memory elements are able to switch during the very brief period when a transient pulse voltage is visible to the memory element.02-02-2012
20120187364ON/OFF RATIO FOR NON-VOLATILE MEMORY DEVICE AND METHOD - A switching device includes a first dielectric material formed overlying a substrate. A bottom wiring material and a switching material are sequentially formed overlying the first dielectric material. The bottom wiring material and the switching material are patterned and etched to form a first structure having a top surface region and a side region. The first structure includes a bottom wiring structure and a switching element having the top surface region including an exposed region. A second dielectric material is formed overlying the first structure. A first opening region is formed in a portion of the second dielectric layer to expose a portion of the top surface region. A dielectric side wall structure is formed overlying a side region of the first opening region. A top wiring material including a conductive material is formed overlying the top surface region to be directly contact with the switching element.07-26-2012
20090146131Integrated Circuit, and Method for Manufacturing an Integrated Circuit - According to one embodiment of the present invention, a method of manufacturing an integrated circuit including a plurality of memory cells is provided, including: forming a first isolation layer including a plurality of contact elements, each contact element extending from the top surface of the first isolation layer to the bottom surface of the first isolation layer; forming a second isolation layer on the first isolation layer, wherein the material of the first isolation layer is different from the material of the second isolation layer; forming trenches within the second isolation layer above the contact elements, wherein the trenches are formed using an etching substance which selectively etches the material of the second isolation layer over the material of the first isolation layer; and filling the trenches with resistivity changing material.06-11-2009
20120187363Arrays Of Nonvolatile Memory Cells And Methods Of Forming Arrays Of Nonvolatile Memory Cells - A nonvolatile memory cell includes first and second electrodes. Programmable material and a select device are received in series between and with the first and second electrodes. Current conductive material is in series between and with the programmable material and the select device. An array of vertically stacked tiers of such nonvolatile memory cells is disclosed. Methods of forming arrays of nonvolatile memory cells are disclosed.07-26-2012
20120193602NANOSCOPIC WIRE-BASED DEVICES AND ARRAYS - Electrical devices comprised of nanoscopic wires are described, along with methods of their manufacture and use. The nanoscopic wires can be nanotubes, preferably single-walled carbon nanotubes. They can be arranged in crossbar arrays using chemically patterned surfaces for direction, via chemical vapor deposition. Chemical vapor deposition also can be used to form nanotubes in arrays in the presence of directing electric fields, optionally in combination with self-assembled monolayer patterns. Bistable devices are described.08-02-2012
20110062409PHASE CHANGE MEMORY STRUCTURE WITH MULTIPLE RESISTANCE STATES AND METHODS OF PROGRAMMING AND SENSING - A phase change memory structure with multiple resistance states and methods of forming, programming, and sensing the same. The memory structure includes two or more phrase change elements provided between electrodes. Each phase change element has a respective resistance curve as a function of programming voltage which is shifted relative to the resistance curves of other phase change elements. In one example structure using two phase change elements, the memory structure is capable of switching among four resistance states.03-17-2011
20090014709PROCESS FOR MANUFACTURING AN ARRAY OF CELLS INCLUDING SELECTION BIPOLAR JUNCTION TRANSISTORS WITH PROJECTING CONDUCTION REGIONS - A process manufactures an array of cells in a body of semiconductor material wherein a common conduction region of a first conductivity type and a plurality of shared control regions, of a second conductivity type, are formed in the body. The shared control regions extend on the common conduction region and are laterally delimited by insulating regions. Then, a grid-like layer is formed on the body to delimit a first plurality of empty regions directly overlying the body and conductive regions of semiconductor material and the first conductivity type are formed by filling the first plurality of empty regions, each conductive region forming, together with the common conduction region and an own shared control region, a bipolar junction transistor.01-15-2009
20090294752HIGHLY INTEGRATED PHASE CHANGE MEMORY DEVICE HAVING MICRO-SIZED DIODES AND METHOD FOR MANUFACTURING THE SAME - A highly integrated phase change memory device and a method for manufacturing the same is disclosed. The highly integrated phase change memory device includes a semiconductor substrate having a cell area and a peripheral area with impurity regions formed in the cell area and extending in parallel to each other in a first direction to form a striped pattern. A gate electrode is formed in the peripheral area and dummy gate electrodes are formed in the cell area and extending in a second direction perpendicular to the first direction of the impurity regions. An interlayer dielectric layer pattern exposes portions of the cell area and the peripheral area and a PN diode is formed in a space defined by a pair of dummy gate electrodes and a pair of interlayer dielectric layer patterns.12-03-2009
20090261316ENHANCED MEMORY DENSITY RESISTANCE VARIABLE MEMORY CELLS, ARRAYS, DEVICES AND SYSTEMS INCLUDING THE SAME, AND METHODS OF FABRICATION - A resistance variable memory cell and method of forming the same. The memory cell includes a first electrode and at least one layer of resistance variable material in contact with the first electrode. A first, second electrode is in contact with a first portion of the at least one layer of resistance variable material and a second, second electrode is in contact with a second portion of the at least one layer of resistance variable material.10-22-2009
20090261315SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor integrated circuit device including: a semiconductor substrate on which a circuit is formed; a plurality of functional device arrays stacked on the semiconductor substrate; and vertical wirings so disposed outside of the functional device arrays as to couple the signal lines of the functional device arrays to the circuit, wherein the vertical wirings include multi-layered metal pieces, each layer of which has a plurality of the metal pieces dispersedly arranged in a stripe-shaped contact trench formed on an interlayer insulating film in the elongated direction.10-22-2009
20110266516PHASE CHANGE MEMORY DEVICE CAPABLE OF REDUCING DISTURBANCE AND METHOD OF MANUFACTURING THE SAME - A phase change memory device includes a plurality of word lines, a plurality of bit lines disposed to be crossed with the plurality of word lines, switching devices disposed at intersections of the plurality of word lines and the plurality of bit lines, heating electrodes connected to the switching devices respectively, heat absorbing layers disposed between adjacent heating electrodes, and phase change layers formed on the heating electrodes and the heat absorbing layers and extended in the same direction of the bit line.11-03-2011
20080277644SWITCH ARRAY CIRCUIT AND SYSTEM USING PROGRAMMABLE VIA STRUCTURES WITH PHASE CHANGE MATERIALS - The present invention provides at least one programmable via structure that includes at least two phase change material vias that are both directly contacting a heating element, the programmable via structure further including a first terminal in contact with a first portion of the heating element, a second terminal in contact with a second portion of the heating element, a third terminal in contact with one of the at least two programmable vias, and a fourth terminal in contact with another one of the at least two programmable vias; a first circuit block in contact with one of the third and fourth terminals; a second circuit block in contact with the third or fourth terminal not contacting the first circuit block; a source region of a first field effect transistor in contact with one of the first and second terminals; and a drain region of a second field effect transistor in contact with the first or second terminal that is not contacting the source region of the first field effect transistor. A method of operating the at least one programmable via structure is also provided.11-13-2008
20080303016PHASE CHANGE MEMORY DEVICES EMPLOYING CELL DIODES AND METHODS OF FABRICATING THE SAME - Phase change memory devices having cell diodes and related methods are provided, where the phase change memory devices include a semiconductor substrate of a first conductivity type and a plurality of parallel word lines disposed on the semiconductor substrate, the word lines have a second conductivity type different from the first conductivity type and have substantially flat top surfaces, a plurality of first semiconductor patterns are one-dimensionally arrayed on each word line along a length direction of the word line, the first semiconductor patterns have the first conductivity type or the second conductivity type, second semiconductor patterns having the first conductivity type are stacked on the first semiconductor patterns, an insulating layer is provided on the substrate having the second semiconductor patterns, the insulating layer fills gap regions between the word lines, gap regions between the first semiconductor patterns and gap regions between the second semiconductor patterns, a plurality of phase change material patterns are two-dimensionally arrayed on the insulating layer, and the phase change material patterns are electrically connected to the second semiconductor patterns, respectively.12-11-2008
20110204316Structure And Fabrication Method For Resistance-Change Memory Cell In 3-D Memory - A memory device in a 3-D read and write memory includes a resistance-changing layer, and a local contact resistance in series with, and local to, the resistance-changing layer. The local contact resistance is established by a junction between a semiconductor layer and a metal layer. Further, the local contact resistance has a specified level of resistance according to a doping concentration of the semiconductor and a barrier height of the junction. A method for fabricating such a memory device is also presented.08-25-2011
20090032796PHASE CHANGE MEMORY BRIDGE CELL - Memory devices are described along with manufacturing methods. An embodiment of a memory device as described herein includes a conductive bit line and a plurality of first electrodes. The memory device includes a plurality of insulating members, the insulating members having a thickness between a corresponding first electrode and a portion of the bit line acting as a second electrode. The memory device further includes an array of bridges of memory material having at least two solid phases, the bridges contacting respective first electrodes and extending across the corresponding insulating member to the bit line. The bridges define an inter-electrode path between the corresponding first electrode and the bit line defined by the thickness of the insulating member.02-05-2009
20090014710NONVOLATILE MEMORY ELEMENT, NONVOLATILE MEMORY APPARATUS, AND METHOD OF MANUFACTURE THEREOF - A lower electrode layer 01-15-2009
20080251779APPARATUS OF MEMORY ARRAY USING FINFETS - A memory cell includes a FinFET select device and a memory element. In some embodiments a memory cell has a contact element coupled between a surface of the fin and the memory element.10-16-2008
20110006279PHASE CHANGE MEMORY - A phase change memory (PCM) is provided which includes a substrate, a plurality of bottom electrodes, a plurality of top electrodes, a plurality of phase change materials, and a plurality of thermal disturbance-preventing parts. The bottom electrodes are disposed in the substrate, and the top electrodes are disposed on the substrate. The phase change (PC) materials are disposed between the top and bottom electrodes, and each of the PC materials is conducted with one of the top electrodes and one of the bottom electrodes. The thermal disturbance-preventing parts are utilized to reduce the effect of thermal disturbance upon the PCM.01-13-2011
20110266515MEMRISTIVE SWITCH DEVICE - A memristive switch device can comprise a switch formed between a first electrode and a second electrode, where the switch includes a memristive layer and a select layer directly adjacent the memristive layer. The select layer blocks current to the memristive layer over a symmetric bipolar range of subthreshold voltages applied between the first and second electrodes.11-03-2011
20100006816Self-aligned vertical bipolar junction transistor for phase change memories - A phase change memory may include self-aligned polysilicon vertical bipolar junction transistors used as select devices. The bipolar junction transistors may be formed with double shallow trench isolation. For example, the emitters of each bipolar transistor may be defined by a first set of parallel trenches in one direction and a second set of parallel trenches in the opposite direction. In some embodiments, the formation of parasitic PNP transistors between adjacent emitters may be avoided.01-14-2010
20100200833SEMICONDUCTOR DEVICE INCLUDING UNIFORM CONTACT PLUGS AND A METHOD OF MANUFACTURING THE SAME - A semiconductor device, a semiconductor module, an electronic apparatus and methods of fabricating and manufacturing the same are provided. The semiconductor device includes a lower interconnection formed on a substrate, a plurality of control patterns formed on the lower interconnection, a plurality of lower contact plug patterns formed on the control patterns, a plurality of storage patterns formed on the lower contact plug patterns, a plurality of upper electrodes formed on the storage patterns, and a plurality of upper interconnections formed on the upper electrodes. The lower contact plug patterns each include at least two contact holes having different sizes, a plurality of sidewall patterns formed on inner sidewalls of the two contact holes and wherein the sidewall patterns have different thicknesses from one another. The semiconductor device further includes a plurality of electrode patterns conformably formed on the inside of the sidewall patterns and having size errors less than 10%, and a plurality of filling patterns formed inside the electrode patterns and completely filling the inside of the contact holes.08-12-2010
20120068149APPARATUS OF MEMORY ARRAY USING FINFETS - In one or more embodiments, a semiconductor device a FinFET device and a second device. In one or more embodiments, the semiconductor device has a contact element coupled between a surface of the fin and the second device.03-22-2012
20090321711NONVOLATILE MEMORY ELEMENT AND MANUFACTURING METHOD THEREOF - A nonvolatile memory element (12-31-2009
20110140070THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND METHODS OF FABRICATING AND OPERATING THE SAME - Provided are three-dimensional semiconductor devices and methods of fabricating and operating the same. A device includes a connection node interposed between first and second nodes, a semiconductor pattern connected to the connection node, a plurality of memory elements connected to the semiconductor pattern, word lines connected to the memory elements, and a control electrode disposed opposite the semiconductor pattern. The control electrode selectively controls an electrical connection between the connection node and the memory element, thereby preventing an un-intended current path in a cross-point 3D memory device.06-16-2011
20110140069NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR PRODUCING THE SAME - A first opening and a second opening are formed at the same time over a first metal wiring and a second metal wiring, respectively which are provided as the same layer on a substrate on which a transistor for selecting a memory cell is formed. Then, a variable resistor and an upper electrode are deposited on a whole surface so as to completely fill the first opening with the upper electrode but not to completely fill the second opening with it. Thereafter, a variable resistive element is formed in the first opening and a via hole to connect to the third metal wiring (bit line), in the second opening, at the same time, by performing back-etching until a surface of the second metal wiring is exposed at a bottom of the second opening.06-16-2011
20090101885Method of producing phase change memory device - An area where a lower electrode is in contact with a variable resistance material needs to be reduced in order to lower the power consumption of a variable resistance memory device. The present invention provides a method of producing a variable resistance memory element whereby the lower electrode can be more finely formed. The method of producing a semiconductor device according to the present invention includes forming a small opening by utilizing cubical expansion due to the oxidation of silicon. Thereby forming the lower electrode smaller than that can be formed by lithography techniques.04-23-2009
20090212274PHASE CHANGE MEMORY RANDOM ACCESS DEVICE USING SINGLE-ELEMENT PHASE CHANGE MATERIAL - A phase change memory cell with a single element phase change thin film layer; and a first electrode and a second electrode coupled to the single element phase change thin film layer. A current flows from the first electrode to the single element phase change thin film layer, and through to the second electrode. The single element phase change thin film layer includes a single element phase change material. The single element phase change thin film layer can be less than 5 nanometers thick. The temperature of crystallization of the single element phase change material can be controlled by its thickness. In one embodiment, the single element phase change thin film layer is configured to be amorphous at room temperature (25 degrees Celsius). In one embodiment, the single element phase change thin film layer is comprised of Antimony (Sb).08-27-2009
20090230379Integrated Circuit, Method of Manufacturing an Integrated Circuit, and Memory Module - According to one embodiment of the present invention, an integrated circuit including a plurality of memory cells is provided. Each memory cell includes a resistivity changing memory element which includes a top electrode, a bottom electrode, and resistivity changing material being disposed between the top electrode and the bottom electrode. Each resistivity changing memory element is at least partially surrounded by a thermal insulating structure. The thermal insulating structures are arranged such that the dissipation of heat generated within the resistivity changing memory elements into the environment of the resistivity changing memory elements is lowered.09-17-2009
20120104353CROSS POINT MEMORY ARRAYS, METHODS OF MANUFACTURING THE SAME, MASTERS FOR IMPRINT PROCESSES, AND METHODS OF MANUFACTURING MASTERS - A cross point memory array includes a structure in which holes are formed in an insulating layer and a storage node is formed in each of the holes. The storage node may include a memory resistor and a switching structure. The master for an imprint process used to form the cross-point memory array includes various pattern shapes, and the method of manufacturing the master uses various etching methods.05-03-2012
20090256133Multiple layer resistive memory - A resistive memory cell may be composed of four stacked layers. Each layer may be sandwiched by electrodes. Connections may be formed from each of four directions around the stack, for example, aligned with each of four edges where the resistive layers are rectangular.10-15-2009
20100176368METHOD OF MANUFACTURING SEMICONDUCTOR MEMORY DEVICE, AND SEMICONDUCTOR MEMORY DEVICE - A method of manufacturing semiconductor memory device comprises forming a first wiring layer and a memory cell layer above a semiconductor substrate; forming a plurality of first trenches extending in a first direction in the first wiring layer and the memory cell layer, thereby forming first wirings and separating the memory cell layer; burying a first interlayer film in the first trenches to form a stacked body; forming a second wiring layer above the stacked body; forming a plurality of second trenches, extending in a second direction intersecting the first direction and reaching an upper surface of the first interlayer film in depth, in the first stacked body with the second wiring layer formed thereabove, thereby forming second wirings; removing the first interlayer film isotropically; and digging the second trenches down to an upper surface of the first wirings, thereby forming memory cells.07-15-2010
20100258783SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor memory device includes a plurality of memory cell arrays each includes a plurality of memory cells, the plurality of memory cell arrays being stacked on a semiconductor substrate to form a three-dimensional structure, a first well formed in the semiconductor substrate and having a first conductivity type, an element isolation insulating film including a bottom surface shallower than a bottom surface of the first well in the first well, and buried in the semiconductor substrate, a second well including a bottom surface shallower than the bottom surface of the first well in the first well, formed along a bottom surface of at least a portion of the element isolation insulating film, and made of an impurity having a second conductivity type, and a contact line electrically connected to the first well.10-14-2010
20120241716NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, in a nonvolatile semiconductor memory device, a first line is disposed on a semiconductor substrate. A first memory cell is disposed on a side opposite to the semiconductor substrate with respect to the first line. A second line intersects with the first line via the first memory cell. A second memory cell is disposed on a side opposite to the semiconductor substrate with respect to the second line. A third line intersects with the second line via the second memory cell. The first memory cell has a first resistance change layer and a first rectification layer. The second memory cell has a second resistance change layer and a second rectification layer. A composition of the first resistance change layer is different from a composition of the second resistance change layer.09-27-2012
20100148143NONVOLATILE MEMORY ELEMENT, MANUFACTURING METHOD THEREOF, AND NONVOLATILE SEMICONDUCTOR APPARATUS USING NONVOLATILE MEMORY ELEMENT - A nonvolatile semiconductor apparatus of the present invention comprises (06-17-2010
20100276659Three-Dimensional Phase-Change Memory Array - A three-dimensional phase-change memory array. In one embodiment of the invention, the memory array includes a first plurality of diodes, a second plurality of diodes disposed above the first plurality of diodes, a first plurality phase-change memory elements disposed above the first and second plurality of diodes and a second plurality of memory elements disposed above the first plurality of memory elements.11-04-2010
20100276660MEMORY WITH HIGH DIELECTRIC CONSTANT ANTIFUSES ADAPTED FOR USE AT LOW VOLTAGE - A memory cell is provided that includes a diode and a resistance-switching material layer coupled in series with the diode. The resistance-switching material layer: (a) has a dielectric constant in the range of about 5 to about 27, and (b) includes a material from the family consisting of X11-04-2010
20100237320NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A nonvolatile semiconductor memory device includes a memory cell array where a plurality of memory cell layers having a plurality of first and second wires which cross each other and a memory cell provided at each intersection of these first and second wires are laminated on top of each other, wherein the memory cells have a variable resistance element and a non-ohmic element laminated in the direction in which the memory cell layers are laminated and tapered in such a manner that the area in a cross section gradually becomes smaller from the bottom memory cell layer towards the top memory cell layer, and the variable resistance element and the non-ohmic element in the memory cells in a certain memory cell layer are laminated in the same order as the variable resistance element and the non-ohmic element of the memory cells in another memory cell layer.09-23-2010
20080210925THREE-TERMINAL CASCADE SWITCH FOR CONTROLLING STATIC POWER CONSUMPTION IN INTEGRATED CIRCUITS - A switching circuit configured for controlling static power consumption in integrated circuits includes a plurality of three-terminal, phase change material (PCM) switching devices connected between a voltage supply terminal and a corresponding sub-block of integrated circuit logic. Each of the PCM switching devices further includes a PCM disposed in contact between a first terminal and a second terminal, a heating device disposed in contact between the second terminal and a third terminal, the heating device positioned proximate the PCM, and configured to switch the conductivity of a transformable portion of the PCM between a lower resistance crystalline state and a higher resistance amorphous state; and an insulating layer configured to electrically isolate the heater from said PCM material, and the heater from the first terminal. The third terminal of a first of the PCM switching devices is coupled to a set/reset switch, and the third terminal of the remaining PCM switching devices is coupled to the second terminal of an adjacent PCM switching device in a cascade configuration.09-04-2008
20100237321SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes the first transistor having first and second source/drain diffusion regions positioned below a second bit line to sandwich the first word line therebetween, and the second source/drain diffusion region positioned between the first and second word lines and connected to a first bit line, a second transistor having second and third source/drain diffusion regions positioned below the second bit line to sandwich the second word line therebetween, a first resistive memory element formed below the second bit line above the first source/drain diffusion region, and having terminals connected to the second bit line and the first source/drain diffusion region, and a second resistive memory element formed below the second bit line above the third source/drain diffusion region, and having terminals connected to the second bit line and the third source/drain diffusion region.09-23-2010
20100252799APPARATUS OF MEMORY ARRAY USING FINFETS - A memory cell includes a FinFET select device and a memory element. In some embodiments a memory cell has a contact element coupled between a surface of the fin and the memory element.10-07-2010
20100127235INFORMATION RECORDING/REPRODUCING DEVICE - An information recording/reproducing device includes a recording layer, and a recording circuit which records data to the recording layer by generating a phase change in the recording layer. The recording layer includes a first chemical compound having a spinel structure. The recording layer is A05-27-2010
20090309089Non-Volatile Memory Arrays Comprising Rail Stacks with a Shared Diode Component Portion for Diodes of Electrically Isolated Pillars - An integrated circuit including vertically oriented diode structures between conductors and methods of fabricating the same are provided. Two-terminal devices such as passive element memory cells can include a diode steering element in series with an antifuse and/or other state change element. The devices are formed using pillar structures at the intersections of upper and lower sets of conductors. The height of the pillar structures are reduced by forming part of the diode for each pillar in a rail stack with one of the conductors. A diode in one embodiment can include a first diode component of a first conductivity type and a second diode component of a second conductivity type. A portion of one of the diode components is divided into first and second portions with one on the portions being formed in the rail stack where it is shared with other diodes formed using pillars at the rail stack.12-17-2009
20120193601SEMICONDUCTOR DEVICE - The semiconductor device includes a memory cell including a plurality of magnetoresistive elements disposed therein, and a peripheral circuit region disposed around the memory cell region. The magnetoresistive element includes a magnetization fixed layer, a magnetization free layer, and a tunneling insulation layer. The semiconductor device includes, above the magnetoresistive elements, a plurality of first wires extending in the direction along the main surface. In the peripheral circuit region, there is disposed a multilayer structure of lamination of a layer equal in material to the magnetization free layer, a layer equal in material to the tunneling insulation layer, and a layer equal in material to the magnetization fixed layer so as to overlap a second wire formed of the same layer as the first wire in plan view. The multilayer structure does not overlap both of a pair of adjacent second wires in plan view in the peripheral circuit region.08-02-2012
20080303015MEMORY HAVING SHARED STORAGE MATERIAL - An integrated circuit includes a bit line and a plurality of access devices coupled to the bit line. The integrated circuit includes a plate of phase change material and a plurality of contacts. Each contact is coupled to an access device and contacting the plate of phase change material. A phase change element is formed at each intersection of a contact and the plate of phase change material.12-11-2008
20090108249Phase Change Memory with Diodes Embedded in Substrate - An integrated circuit structure includes a semiconductor substrate; a diode; and a phase change element over and electrically connected to the diode. The diode includes a first doped semiconductor region of a first conductivity type, wherein the first doped semiconductor region is embedded in the semiconductor substrate; and a second doped semiconductor region over and adjoining the first doped semiconductor region, wherein the second doped semiconductor region is of a second conductivity type opposite the first conductivity type.04-30-2009
20130181184NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a nonvolatile semiconductor memory device includes fin-type stacked layer structures. Each of the structures includes semiconductor layers stacked in a perpendicular direction. Assist gate electrodes are disposed in an in-plane direction and divided on a surface in the perpendicular direction of the structures.07-18-2013
20100301305PHASE CHANGE MEMORY DEVICE WITH ALTERNATING ADJACENT CONDUCTION CONTACTS AND FABRICATION METHOD THEREOF - A phase change memory device and an associated method of making same are presented. The phase change memory device, includes first wiring lines, second wiring lines, memory cells, and conduction contacts. The first wiring lines are arranged substantially in parallel to each other so that the first wiring lines are grouped into odd and even numbered first wiring lines. The memory cells are coupled to the first and second wiring lines. The conduction contacts coupled to the first wiring lines so that only one conduction contact is coupled to a center of a corresponding odd numbered first wiring line. Also only two corresponding conduction contacts are coupled to opposing edges of a corresponding even numbered first wiring line. Accordingly, the conduction contacts are arranged on the first wiring lines so that conduction contacts are not adjacent to each other with respect to immediately adjacent first wiring lines.12-02-2010
20100155690CROSS-POINT CELL NANOARRAY WITH ANISOTROPIC ACTIVE ORGANIC LAYER - A cross-point cell nanoarray comprises a mechanical support substrate, first and second orders of uniformly spaced parallel electrodes separated by an electrically active organic film and orthogonally arranged to form an array of cross-point cells, individually addressable by biasing the respective opposite electrodes, by selecting them among those of the respective orders, over a planar area of the substrate. The active organic resin layer includes a block copolymer of a major component resin and of at least one different minor component resin, configured to promote formation of large-scale ordered nanostructures through phase segregation, due to block incompatibility and self-assembly properties of the blocks. Polymeric bocks of the ordered nanostructures configured to sequester conductive nanoparticles and/or conductive nanoparticle clusters originally dispersed in the component organic resins, subtracting them from the surrounding matrix copolymer. Preferential electric current paths across the thickness of the active organic layer at cross-over points are thus created.06-24-2010
20100308297Heterojunction diode, method of manufacturing the same, and electronic device including the heterojunction diode - Example embodiments relate to a heterojunction diode, a method of manufacturing the heterojunction diode, and an electronic device including the heterojunction diode. The heterojunction diode may include a first conductive type non-oxide layer and a second conductive type oxide layer bonded to the non-oxide layer. The non-oxide layer may be a Si layer. The Si layer may be a p++ Si layer or an n++ Si layer. A difference in work functions of the non-oxide layer and the oxide layer may be about 0.8-1.2 eV. Accordingly, when a forward voltage is applied to the heterojunction diode, rectification may occur. The heterojunction diode may be applied to an electronic device, e.g., a memory device.12-09-2010
20100308298NONVOLATILE MEMORY ELEMENT AND NONVOLATILE MEMORY DEVICE INCORPORATING NONVOLATILE MEMORY ELEMENT - A nonvolatile memory element includes a first electrode (12-09-2010
20100301304BURIED SILICIDE STRUCTURE AND METHOD FOR MAKING - Methods for manufacturing buried silicide lines are described herein, along with high density stacked memory structures. A method for manufacturing an integrated circuit as described herein includes forming a semiconductor body comprising silicon. A plurality of trenches are formed in the semiconductor body to define semiconductor lines comprising silicon between adjacent trenches, the semiconductor lines having sidewalls. A silicide precursor is deposited within the trenches to contact the sidewalls of the semiconductor lines, and a portion of the silicide precursor is removed to expose upper portions of the sidewalls and leave remaining strips of silicide precursor along the sidewalls. Silicide conductors are then formed by inducing reaction of the strips of silicide with the silicon of the semiconductor lines.12-02-2010
20100308296PHASE CHANGE MEMORY CELL WITH SELF-ALIGNED VERTICAL HEATER - A self-aligned vertical heater element is deposited directly on the silicide of a selection device, and a phase change chalcogenide material is deposited directly on the vertical heater element. The fabrication process allows for self-alignment between the chalcogenide line and vertical heater element. In an embodiment, the vertical heater element is L-shaped, having a vertical wall along the wordline direction and a horizontal base. The vertical wall and the horizontal base may have the same thickness.12-09-2010
20100133503PHASE CHANGE MEMORY - A phase change memory is provided, which includes a semiconductor substrate having a first conductive type, buried word lines having a second conductive type, doped semiconductor layers having the first conductive type, memory cells, metal silicide layers, and bit lines. The buried word lines are disposed in the semiconductor substrate. Each buried word line includes a line-shaped main portion extended along a first direction and protrusion portions. Each protrusion portion is connected to one long side of the line-shaped main portion. Each doped semiconductor layer is disposed on one protrusion portion. Each memory cell includes a phase change material layer and is disposed on and electrically connected to one of the doped semiconductor layers. Each metal silicide layer is disposed on one of the line-shaped main portions. Each bit line is connected to memory cells disposed on the word lines in a second direction substantially perpendicular to the first direction.06-03-2010
20110240951MEMRISTIVE DEVICE - A memristive device includes a first electrode and a second electrode crossing the first electrode at a non-zero angle. An active region is disposed between the first and second electrodes. The active region has defects therein. Graphene or graphite is disposed between the active region and the first electrode and/or between the active region and the second electrode.10-06-2011
20110017971INTEGRATED CIRCUIT DEVICES INCLUDING LOW-RESISTIVITY CONDUCTIVE PATTERNS IN RECESSED REGIONS - An integrated circuit device includes a device isolation pattern on a semiconductor substrate to define an active area therein. The active area includes a doped region therein. A conductive pattern extends on the active area and electrically contacts the doped region. The conductive pattern has a lower resistivity than the doped region. The conductive pattern may be disposed in a recessed region having a bottom surface lower than a top surface of the active area. A channel pillar electrically contacts to the doped region and extends therefrom in a direction away from the substrate. A conductive gate electrode is disposed on a sidewall of the channel pillar, and a gate dielectric layer is disposed between the gate electrode and the sidewall of the channel pillar.01-27-2011
20110024716MEMRISTOR HAVING A NANOSTRUCTURE IN THE SWITCHING MATERIAL - A memristor includes a first electrode having a first surface, at least one electrically conductive nanostructure provided on the first surface, in which the at least one electrically conductive nanostructure is relatively smaller than a width of the first electrode, a switching material positioned upon said first surface, in which the switching material covers the at least one electrically conductive nanostructure, and a second electrode positioned upon the switching material substantially in line with the at least one electrically conductive nanostructure, in which an active region in the switching material is formed substantially between the at least one electrically conductive nanostructure and the first electrode.02-03-2011
20090065761PROGRAMMABLE FUSE/NON-VOLATILE MEMORY STRUCTURES IN BEOL REGIONS USING EXTERNALLY HEATED PHASE CHANGE MATERIAL - A programmable phase change material (PCM) structure includes a heater element formed at a BEOL level of a semiconductor device, the BEOL level including a low-K dielectric material therein; a first via in electrical contact with a first end of the heater element and a second via in electrical contact with a second end of the heater element, thereby defining a programming current path which passes through the first via, the heater element, and the second via; a PCM element disposed above the heater element, the PCM element configured to be programmed between a lower resistance crystalline state and a higher resistance amorphous state through the use of programming currents through the heater element; and a third via in electrical contact with the PCM element, thereby defining a sense current path which passes through the third via, the PCM element, the heater element, and the second via.03-12-2009
20110031469SEMICONDUCTOR DEVICE - The invention provides a semiconductor device which is non-volatile, easily manufactured, and can be additionally written. A semiconductor device of the invention includes a plurality of transistors, a conductive layer which functions as a source wiring or a drain wiring of the transistors, and a memory element which overlaps one of the plurality of transistors, and a conductive layer which functions as an antenna. The memory element includes a first conductive layer, an organic compound layer and a phase change layer, and a second conductive layer stacked in this order. The conductive layer which functions as an antenna and a conductive layer which functions as a source wiring or a drain wiring of the plurality of transistors are provided on the same layer.02-10-2011
20110031466SEMICONDUCTOR MEMORY DEVICE AND A METHOD OF MANUFACTURING THE SAME - Disclosed herein is a semiconductor memory device, including: a first electrode formed on a substrate; an ion source layer formed on an upper layer of the first electrode; and a second electrode formed on an upper layer of the ion source layer. Resistance change type memory cells in each of which either a surface of the first electrode or a surface of the ion source layer is oxidized to form a resistance change type memory layer in an interface between the first electrode and the ion source interface are arranged in a array.02-10-2011
20110031467INFORMATION RECORDING AND REPRODUCING APPARATUS - An information recording and reproducing apparatus according to an embodiment has a memory cell including a recording layer operative to change in a reversible manner between a first state having a certain resistance value upon application of a voltage pulse and a second state having a resistance value higher than that of the first state. The recording layer includes a first compound layer represented by a composition formula of A02-10-2011
20110031468NONVOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a nonvolatile memory device includes a substrate, a first electrode, a second electrode, a third electrode, a first memory portion and a second memory portion. The first electrode extends in a first direction and is provided on the substrate. The second electrode extends in a second direction crossing the first direction and is provided on the first electrode. The third electrode extends in a third direction crossing the second direction and is provided on the second electrode. The first memory portion is provided between the first and the second electrodes and has a first oxygen composition ratio and a first layer thickness. The second memory portion is provided between the second and the third electrodes and has at least one of a second oxygen composition ratio different from the first oxygen composition ratio and a second layer thickness different from the first layer thickness.02-10-2011
20110114913HETEROJUNCTION DEVICE COMPRISING A SEMICONDUCTOR AND A RESISTIVITY-SWITCHING OXIDE OR NITRIDE - In the present invention, a metal oxide or nitride compound which is a wide-band-gap semiconductor abuts a silicon, germanium, or alloy of silicon and/or germanium of the opposite conductivity type to form a p-n heterojunction. This p-n heterojunction can be used to advantage in various devices. In preferred embodiments, one terminal of a vertically oriented p-i-n heterojunction diode is a metal oxide or nitride layer, while the rest of the diode is formed of a silicon or silicon-germanium resistor. For example, a diode may include a heavily doped n-type silicon region, an intrinsic silicon region, and a nickel oxide layer serving as the p-type terminal. Many of these metal oxides and nitrides exhibit resistivity-switching behavior, and such a heterojunction diode can be used in a nonvolatile memory cell, for example in a monolithic three dimensional memory array.05-19-2011
20090127538Phase-Changeable Memory Devices Having Reduced Susceptibility to Thermal Interference - A non-volatile memory array includes an array of phase-changeable memory elements that are electrically insulated from each other by at least a first electrically insulating region extending between the array of phase-changeable memory elements. The first electrically insulating region includes a plurality of voids therein. Each of these voids extends between a corresponding pair of phase-changeable memory cells in the non-volatile memory array and, collectively, the voids form an array of voids in the first electrically insulating region.05-21-2009
20100012918Write-Once Memory Array including Phase-Change Elements and Threshold Switch Isolation - A three-dimensional memory array formed of one or more two-dimensional memory arrays of one-time programmable memory elements arranged in horizontal layers and stacked vertically upon one another; and a two-dimensional memory array of reprogrammable phase change memory elements stacked on the one or more two-dimensional memory arrays as the top layer of the three-dimensional memory array.01-21-2010
20090218559Integrated Circuit, Memory Cell Array, Memory Module, and Method of Manufacturing an Integrated Circuit - According to one embodiment of the present invention, an integrated circuit is provided including a plurality of magneto-resistive memory cells. Each memory cell includes a magnetic tunneling junction stack, wherein the top surfaces of the magnetic tunneling junctions stacks are electrically connected to a common continuous conductive plate.09-03-2009
20100065808PHASE CHANGE MEMORY CELL IN VIA ARRAY WITH SELF-ALIGNED, SELF-CONVERGED BOTTOM ELECTRODE AND METHOD FOR MANUFACTURING - An array of “mushroom” style phase change memory cells is manufactured by forming a separation layer over an array of contacts, forming an isolation layer on the separation layer and forming an array of memory element openings in the isolation layer using a lithographic process. Etch masks are formed within the memory element openings by a process that compensates for variation in the size of the memory element openings that results from the lithographic process. The etch masks are used to etch through the separation layer to define an array of electrode openings. Electrode material is deposited within the electrode openings; and memory elements are formed within the memory element openings. The memory elements and bottom electrodes are self-aligned.03-18-2010
20110068318SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a semiconductor memory device includes a substrate, an upper-layer wire provided on the substrate, a lower-layer wire provided on the substrate, a memory cell located at an intersection of the upper-layer wire and the lower-layer wire and includes a diode and a storage layer, a conductive layer located between the upper-layer wire and the memory cell in a direction perpendicular to the substrate surface, and an interlayer insulating film provided between memory cells. The position of an interface between the upper-layer wire and the interlayer insulating film is lower than a top surface of the conductive layer.03-24-2011
20110068319INFORMATION RECORDING AND REPRODUCING DEVICE - According to one embodiment, an information recording and reproducing device includes a stacked body. The stacked body includes a first layer, a second layer and a recording layer provided between the first layer and the second layer. The recording layer includes a phase-change material and a crystal nucleus. The phase-change material is capable of reversely changing between a crystal state and an amorphous state by a current supplied via the first layer and the second layer. The crystal nucleus is provided in contact with the phase-change material and includes a crystal nucleus material having a crystal structure identical to a crystal structure of the crystal state of the phase-change material, and a crystal nucleus coating provided on a surface of the crystal nucleus material and having a composition different from a composition of the crystal nucleus material.03-24-2011
20130187121CROSS-POINT MEMORY UTILIZING RU/SI DIODE - Memory devices utilizing memory cells including a resistive element and a diode coupled in series between two conductors. The diodes include a ruthenium material and a silicon material. The diodes further include an interface on the silicon material of ruthenium or ruthenium silicide. A ruthenium silicide interface may be a polycrystalline ruthenium silicide.07-25-2013
20100295013SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device according to an embodiment includes: a semiconductor substrate; a resistance element of a first conductivity type formed in one region of the semiconductor substrate; a field effect transistor of a second conductivity type formed in another region of the semiconductor substrate; and a field effect transistor of the first conductivity type formed in still another region of the semiconductor substrate. The resistance element includes: an insulating film formed in an upper layer portion of the semiconductor substrate; and a well of the first conductivity type formed immediately below the insulating film, an impurity concentration at an arbitrary depth position in the well of the first conductivity is lower than an impurity concentration at the same depth position in a channel region of the field effect transistor of the second conductivity type.11-25-2010
20120273747SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a fin type stacked layer structure which has first to third semiconductor layers, and first to third layer select transistors to select one of the first to third semiconductor layers. The second layer select transistor is normally on in the second semiconductor layer, and is controlled to be on or off in the first and third semiconductor layers. A channel region of the second semiconductor layer which is covered with a gate electrode of the second layer select transistor has a metal silicide.11-01-2012
20120273748INTERCONNECTS FOR STACKED NON-VOLATILE MEMORY DEVICE AND METHOD - A method of forming a memory device includes providing a substrate having a surface region, defining a cell region and first and second peripheral regions, sequentially forming a first dielectric material, a first wiring structure for a first array of devices, and a second dielectric material over the surface region, forming an opening region in the first peripheral region, the opening region extending in a portion of at least the first and second dielectric materials to expose portions of the first wiring structure and the substrate, forming a second wiring material that is overlying the second dielectric material and fills the opening region to form a vertical interconnect structure in the first peripheral region, and forming a second wiring structure from the second wiring material for a second array of devices, the first and second wiring structures being separated from each other and electrically connected by the vertical interconnect structure.11-01-2012
20120267601PHASE CHANGE MEMORY CELLS WITH SURFACTANT LAYERS - An example embodiment is a phase change memory cell including a bottom electrode and phase change material carried within a via above the bottom electrode. A surfactant layer is deposited above the bottom electrode. The surfactant layer includes a surfactant configured to lower an interfacial force between the phase change material and the via surface.10-25-2012
20110253968RESISTIVE MEMORY ARRAY USING P-I-N DIODE SELECT DEVICE AND METHODS OF FABRICATION THEREOF - An electronic structure includes a resistive memory device, and a P-I-N diode in operative association with the resistive memory device. A plurality of such electronic structures are used in a resistive memory array, with the P-I-N diodes functioning as select devices in the array. Methods are provided for fabricating such resistive memory device—P-I-N diode structures.10-20-2011
20080203378SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A phase change memory device including plural memory cells is disclosed. Each of the memory cells includes memory transistors and phase change film portions formed above or below the memory transistors. The phase change film portions correspond to the respective memory transistors respectively. Vias are provided in order to connect each of the memory transistor in parallel to each of the phase change film portions in each of the memory cells. The vias connect the memory cells in series to one another.08-28-2008
20080203379ARRAY OF VERTICAL BIPOLAR JUNCTION TRANSISTORS, IN PARTICULAR SELECTORS IN A PHASE CHANGE MEMORY DEVICE - A process for manufacturing an array of bipolar transistors, wherein deep field insulation regions of dielectric material are formed in a semiconductor body, thereby defining a plurality of active areas, insulated from each other and a plurality of bipolar transistors are formed in each active area. In particular, in each active area, a first conduction region is formed at a distance from the surface of the semiconductor body; a control region is formed on the first conduction region; and, in each control region, at least two second conduction regions and at least one control contact region are formed. The control contact region is interposed between the second conduction regions and at least two surface field insulation regions are thermally grown in each active area between the control contact region and the second conduction regions.08-28-2008
20100320436ENCAPSULATED PHASE CHANGE CELL STRUCTURES AND METHODS - Methods and devices associated with phase change cell structures are described herein. In one or more embodiments, a method of forming a phase change cell structure includes forming a substrate protrusion that includes a bottom electrode, forming a phase change material on the substrate protrusion, forming a conductive material on the phase change material, and removing a portion of the conductive material and a portion of the phase change material to form an encapsulated stack structure.12-23-2010
20120145987MEMORY ELEMENT AND METHOD OF MANUFACTURING THE SAME, AND MEMORY DEVICE - A memory element with reduced degradation of memory characteristics that is caused by deterioration of a memory layer, a method of manufacturing the memory element, and a memory device are provided. The memory element includes a first electrode, a memory layer, and a second electrode in this order. The memory layer includes a resistance change layer containing fluoride, and an ion source layer disposed between the resistance change layer and the second electrode.06-14-2012
20110260135Method for Doping an Electrically Actuated Device - An electrically actuated device (10-27-2011
20100065807NONVOLATILE MEMORY ELEMENT, NONVOLATILE MEMORY ELEMENT ARRAY, AND METHOD FOR MANUFACTURING NONVOLATILE MEMORY ELEMENT - The present invention is configured such that a resistance variable element (03-18-2010
20110186803Multi-resistive state memory device with conductive oxide electrodes - A memory cell including conductive oxide electrodes is disclosed. The memory cell includes a memory element operative to store data as a plurality of resistive states. The memory element includes a layer of a conductive metal oxide (CMO) (e.g., a perovskite) in contact with an electrode that may comprise one or more layers of material. At least one of those layers of material can be a conductive oxide (e.g., a perovskite such as LaSrCoO08-04-2011
20100019221FULLY SELF-ALIGNED PORE-TYPE MEMORY CELL HAVING DIODE ACCESS DEVICE - Memory devices are described along with methods for manufacturing. A memory device as described herein includes a plurality of memory cells. Each memory cell in the plurality of memory cells comprises a diode comprising doped semiconductor material and a dielectric spacer on the diode and defining an opening, the dielectric spacer having sides self-aligned with sides of the diode. Each memory cell further comprises a memory element on the dielectric spacer and including a portion within the opening contacting a top surface of the diode.01-28-2010
20120032136Forming Resistive Random Access Memories Together With Fuse Arrays - A resistive random access memory array may be formed on the same substrate with a fuse array. The random access memory and the fuse array may use the same active material. For example, both the fuse array and the memory array may use a chalcogenide material as the active switching material. The main array may use a pattern of perpendicular sets of trench isolations and the fuse array may only use one set of parallel trench isolations. As a result, the fuse array may have a conductive line extending continuously between adjacent trench isolations. In some embodiments, this continuous line may reduce the resistance of the conductive path through the fuses.02-09-2012
20120037879NON VOLATILE MEMORY DEVICE ION BARRIER - An ion barrier layer made from a dielectric material in contact with an electronically insulating layer is operative to prevent mobile ions transported into the electronically insulating layer from passing through the ion barrier layer and into adjacent layers during data operations on a non-volatile memory cell. A conductive oxide layer in contact with the electronically insulating layer is the source of the mobile ions. A programming data operation is operative to transport a portion of the mobile ions into the electronically insulating layer and an erase data operation is operative to transport the mobile ions back into the conductive oxide layer. When the portion is positioned in the electronically insulating layer the memory cell stores data as a programmed conductivity profile and when a substantial majority of the mobile ions are positioned in the conductive oxide layer the memory cell stores data as an erased conductivity profile.02-16-2012
20110315948Memory Device Using Ion Implant Isolated Conductive Metal Oxide - Memory cell formation using ion implant isolated conductive metal oxide is disclosed, including forming a bottom electrode below unetched conductive metal oxide layer(s), forming the unetched conductive metal oxide layer(s) including depositing at least one layer of a conductive metal oxide (CMO) material (e.g., PrCaMnO12-29-2011
20110101298METHODS, STRUCTURES AND DEVICES FOR INCREASING MEMORY DENSITY - Non-volatile memory devices comprising a memory string including a plurality of vertically superimposed diodes. Each of the diodes may be arranged at different locations along a length of the electrode and may be spaced apart from adjacent diodes by a dielectric material. The electrode may electrically couple the diodes of the memory strings to one another and to another memory device, such as, a MOSFET device. Methods of forming the non-volatile memory devices as well as intermediate structures are also disclosed.05-05-2011
20110155994STRUCTURES FOR RESISTANCE RANDOM ACCESS MEMORY AND METHODS OF FORMING THE SAME - Memory cells and methods of forming the same and devices including the same. The memory cells have first and second electrodes. An amorphous semiconductor material capable of electronic switching and having a first band gap is between the first and second electrodes. A material is in contact with the semiconductor material and having a second band gap, the second band gap greater than the first band gap.06-30-2011
20120205612NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A nonvolatile semiconductor memory device comprises a semiconductor substrate; a cell array block formed on the semiconductor substrate and including plural stacked cell array layers each with a plurality of first lines, a plurality of second lines crossing the plurality of first lines, and memory cells connected at intersections of the first and second lines between both lines; and a plurality of via-holes extending in the stacked direction of the cell array layers to individually connect the first or second line in the each cell array layer to the semiconductor substrate. The via-holes are formed continuously through the plural cell array layers, and multiple via-holes having equal lower end positions and upper end positions are connected to the first or second lines in different cell array layers.08-16-2012
20120007037CROSS-POINT MEMORY UTILIZING Ru/Si DIODE - Memory devices utilizing memory cells including a resistive element and a diode coupled in series between two conductors. The diodes include a ruthenium material and a silicon material. The diodes further include an interface on the silicon material of ruthenium or ruthenium silicide. A ruthenium silicide interface may be a polycrystalline ruthenium silicide.01-12-2012
20120007038Reconfigurable Multilayer Circuit - A reconfigurable multilayer circuit (01-12-2012
20120104352MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a memory device includes a nanomaterial assembly layer, a first electrode layer and a second electrode layer. The nanomaterial assembly layer is formed of an assembly of a plurality of micro conductors via gaps between the micro conductors. The first electrode layer is provided on the nanomaterial assembly layer. The second electrode layer is provided on the first electrode layer.05-03-2012
20110049466LARGE ARRAY OF UPWARD POINTING P-I-N DIODES HAVING LARGE AND UNIFORM CURRENT - A memory is provided that includes a first memory level having a plurality of memory cells. Each memory cell includes a vertically oriented p-i-n diode including a bottom heavily doped p-type region, a middle intrinsic or lightly doped region, and a top heavily doped n-type region. When a voltage between about 1.5 volts and about 3.0 volts is applied across each p-i-n diode, a current of at least 1.5 microamps flows through 99 percent of the p-i-n diodes. Numerous other aspects are also provided.03-03-2011
20110049465SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor integrated circuit device including: multiple wiring layers stacked on a semiconductor substrate with interlayer insulating films interposed therebetween; wiring hook-up portions extended from the corresponding wirings in the respective wiring layers; and contact conductors so buried in interlayer insulating films as to pass through the hook-up portions for vertically leading wirings of the respective wiring layers, wherein the hook-up portions have different sizes from each other between at least two layers in the wiring layers.03-03-2011
20100288996MEMORY ARRAYS INCLUDING MEMORY LEVELS THAT SHARE CONDUCTORS, AND METHODS OF FORMING SUCH MEMORY ARRAYS - A memory array is provided that includes a first memory level, a second memory level and a conductor shared between the first and second memory levels. The first memory level includes a first diode and a first resistivity-switching material layer coupled in series with the first diode. The second memory level includes a second diode and a second resistivity-switching material layer coupled in series with the second diode. The first and second resistivity-switching material layers each comprise one or more of Ni11-18-2010
20120161097PHASE CHANGE MEMORY AND METHOD FOR FABRICATING THE SAME - The invention provides a phase change memory and a method for forming the phase change memory. The phase change memory includes a storage region and a peripheral circuit region. The peripheral circuit region has a peripheral substrate, peripheral shallow trench isolation (STI) units in the peripheral substrate, and MOS transistors on the peripheral substrate and between the peripheral STI units. The storage region has a storage substrate, an N-type ion buried layer on the storage substrate, vertical LEDs on the on the N-type ion buried layer, storage shallow trench isolation (STI) units between the vertical LEDs, and phase change layers on the vertical LEDs and between the storage STI units. The storage STI units have thickness equal to thickness of the vertical LEDs. Each vertical LED comprises an N-type conductive region on the N-type ion buried layer, and a P-type conductive region on the N-type conductive region. The P-type conductive region contains SiGe. The peripheral STI units have thickness equal to thickness of the storage STI units. A top of P-type conductive region is flush with a top of the peripheral substrate. The P-type conductive region containing SiGe reduces drain current through the vertical LED and raises current efficiency of the vertical LED. The peripheral circuit region can work normally without adverse influence on performance of the phase change memory.06-28-2012
20080203377METHODS OF MANUFACTURING NON-VOLATILE MEMORY DEVICES BY IMPLANTING METAL IONS INTO GRAIN BOUNDARIES OF VARIABLE RESISTANCE LAYERS, AND RELATED DEVICES - Integrated circuit nonvolatile memory devices are manufactured by forming a variable resistance layer on an integrated circuit substrate. The variable resistance layer includes grains that define grain boundaries between the grains. Conductive filaments are formed along at least some of the grain boundaries. Electrodes are formed on the variable resistance layer. The conductive filaments may be formed by implanting conductive ions into at least some of the grain boundaries. Moreover, the variable resistance layer may be a variable resistance oxide of a metal, and the conductive filaments may be the metal. Related devices are also disclosed.08-28-2008
20120175583MEMRISTOR APPARATUS - A memristor apparatus comprising a plurality of meta-stable switching elements.07-12-2012
20120074378MEMORY ELEMENT HAVING ELASTICALLY DEFORMABLE ACTIVE REGION - A memory element is provided that includes a first electrode, a second electrode, and an active region disposed between the first electrode and the second electrode, wherein at least a portion of the active region comprises an elastically deformable material, and wherein deformation of the elastically deformable material causes said memory element to change from a lower conductive state to a higher conductive state. A multilayer structure also is provided that includes a base and a multilayer circuit disposed above the base, where the multilayer circuit includes at least of the memory elements including the elastically deformable material.03-29-2012
20120248400Integrated Circuit Semiconductor Devices Including Channel Trenches And Related Methods Of Manufacturing - An integrated circuit device may include a semiconductor substrate including an active region and a transistor in the active region. The transistor may include first and second spaced apart source/drain regions in the active region of the semiconductor substrate, and a semiconductor channel region between the first and second source/drain regions. The semiconductor channel region may include a plurality of channel trenches therein between the first and second source/drain regions. A gate insulating layer may be provided on the channel region including sidewalls of the plurality of channel trenches, and a gate electrode may be provided on the gate insulating layer so that the gate insulating layer is between the gate electrode and the semiconductor channel region including the plurality of channel trenches. Related methods are also discussed.10-04-2012
20120223287Diamond Type Quad-Resistor Cells of PRAM - A method of forming a phase-change random access memory (PRAM) cell, and a structure of a phase-change random access memory (PRAM) cell are disclosed. The PRAM cell includes a bottom electrode, a heater resistor coupled to the bottom electrode, a phase change material (PCM) thrilled over and coupled to the heater resistor, and a top electrode coupled to the phase change material. The phase change material contacts a portion of a vertical surface of the heater resistor and a portion of a horizontal surface of the heater resistor to form an active region between the heater resistor and the phase change material.09-06-2012
20120256157SEMICONDUCTOR DEVICE - For example, one memory cell is configured using two memory cell transistors and one phase change element by disposing a plurality of diffusion layers in parallel to a bit-line, disposing gates between the diffusion layers so as to cross the bit-line, disposing bit-line contacts and source contacts alternately to the plurality of diffusion layers arranged in a bit-line direction for each diffusion layer, and providing a phase change element on the source contact. Also, the phase change element can be provided on the bit-line contact instead of the source contact. By this means, for example, increase in drivability of the memory cell transistors and reduction in area can be realized.10-11-2012
201202285793D POLYSILICON DIODE WITH LOW CONTACT RESISTANCE AND METHOD FOR FORMING SAME - A semiconductor p-i-n diode and method for forming the same are described herein. In one aspect, a SiGe region is formed between a region doped to have one conductivity (either p+ or n+) and an electrical contact to the p-i-n diode. The SiGe region may serve to lower the contact resistance, which may increase the forward bias current. The doped region extends below the SiGe region such that it is between the SiGe region and an intrinsic region of the diode. The p-i-n diode may be formed from silicon. The doped region below the SiGe region may serve to keep the reverse bias current from increasing as result of the added SiGe region. In one embodiment, the SiGe is formed such that the forward bias current of an up-pointing p-i-n diode in a memory array substantially matches the forward bias current of a down-pointing p-i-n diode which may achieve better switching results when these diodes are used with the R/W material in a 3D memory array.09-13-2012
20100237319NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - This nonvolatile semiconductor memory device comprises a memory cell array including memory cells arranged therein. Each of the memory cells is located at respective intersections between first wirings and second wirings and includes a variable resistance element. The variable resistance element comprises a thin film including carbon (C). The thin film includes a side surface along a direction of a current flowing in the memory cell. The side surface includes carbon nitride (CN09-23-2010
20110121256PROGRAMMABLE RESISTIVE MEMORY CELL WITH FILAMENT PLACEMENT STRUCTURE - Programmable metallization memory cells having a first metal contact and a second metal contact with an ion conductor solid electrolyte material between the metal contacts. The first metal contact has a filament placement structure thereon extending into the ion conductor material. In some embodiments, the second metal contact also has a filament placement structure thereon extending into the ion conductor material toward the first filament placement structure. The filament placement structure may have a height of at least about 2 nm.05-26-2011
20110121255Integrated Memory Arrays, And Methods Of Forming Memory Arrays - Some embodiments include methods of forming memory arrays. A stack of semiconductor material plates may be patterned to subdivide the plates into pieces. Electrically conductive tiers may be formed along sidewall edges of the pieces. The pieces may then be patterned into an array of wires, with the array having vertical columns and horizontal rows. Individual wires may have first ends joining to the electrically conductive tiers, may have second ends in opposing relation to the first ends, and may have intermediate regions between the first and second ends. Gate material may be formed along the intermediate regions. Memory cell structures may be formed at the second ends of the wires. A plurality of vertically-extending electrical interconnects may be connected to the wires through the memory cell structures, with individual vertically-extending electrical interconnects being along individual columns of the array. Some embodiments include memory arrays incorporated into integrated circuitry.05-26-2011
20120319076MULTI-BIT MEMORY ELEMENTS, MEMORY DEVICES INCLUDING THE SAME, AND METHODS OF MANUFACTURING THE SAME - In one embodiment, the memory element may include a first electrode, a second electrode spaced apart from the first electrode, a memory layer between the first electrode and the second electrode, and an auxiliary layer between the memory layer and the second electrode. The auxiliary layer provides a multi-bit memory characteristic to the memory layer.12-20-2012
20120319077NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a nonvolatile semiconductor memory device includes a plurality of first interconnections arranged parallel, a plurality of second interconnections arranged parallel to intersect the first interconnections, and memory cell portions respectively arranged at intersecting portions between the first and second interconnections and each configured by laminating a variable-resistance element and a diode element. The diode element has a laminated structure having a first insulating film, a conductive fine grain layer and a second insulating film. The physical film thickness of the second insulating film is greater than the first insulating film and the dielectric constant of the second insulating film is greater than the first insulating film.12-20-2012
20120261638VERTICAL MEMORY CELL FOR HIGH-DENSITY MEMORY - This disclosure provides embodiments for the formation of vertical memory cell structures that may be implemented in RRAM devices. In one embodiment, memory cell area may be increased by varying word line height and/or word line interface surface characteristics to ensure the creation of a grain boundary that is suitable for formation of conductive pathways through an active layer of an RRAM memory cell. This may maintain continuum behavior while reducing random cell-to-cell variability that is often encountered at nanoscopic scales. In another embodiment, such vertical memory cell structures may be formed in multiple-tiers to define a three-dimensional RRAM memory array. Further embodiments also provide a spacer pitch-doubled RRAM memory array that integrates vertical memory cell structures.10-18-2012
20100230655VARIABLE RESISTANCE DEVICE, METHOD FOR MANUFACTURING VARIABLE RESISTANCE DEVICE, AND SEMICONDUCTOR STORAGE DEVICE USING VARIABLE RESISTANCE DEVICE - A variable resistance device includes a first electrode including a transition metal nitride film, a second electrode including a precious metal or a precious metal oxide, and a transition metal oxide film interposed between the first and second electrodes.09-16-2010
20120267600MEMORY CELL REPAIR - A repairable memory cell in accordance with one or more embodiments of the present disclosure includes a storage element positioned between a first and a second electrode, and a repair element positioned between the storage element and at least one of the first electrode and the second electrode.10-25-2012
20110227032Memristor with Nanostructure Electrodes - A memristor having an active region includes a first electrode. The first electrode comprises a nanostructure formed of at least one metallic single walled nanotube. The memristor also includes a second electrode formed of at least one metallic single walled nanotube. The second electrode is positioned in a crossed relationship with respect to the first electrode. The memristor further includes a switching material positioned between the first electrode and the second electrode, in which the active region is configured to form in the switching material at a cross point of the first electrode and the second electrode.09-22-2011
20120280202HETEROJUNCTION DEVICE COMPRISING A SEMICONDUCTOR AND A RESISTIVITY-SWITCHING OXIDE OR NITRIDE - A monolithic three dimensional memory array is provided that includes a first memory level formed above a substrate, and a second memory level monolithically formed above the first memory level. The first memory level includes a first plurality of substantially parallel, substantially coplanar conductors extending in a first direction, a second plurality of substantially parallel, substantially coplanar conductors extending in a second direction, the second direction different from the first direction, the second conductors above the first conductors, and a first plurality of devices. Each of the first plurality of devices is disposed between one of the first conductors and one of the second conductors, and includes a resistivity-switching binary metal oxide or nitride compound and a silicon, germanium, or silicon-germanium alloy resistor of a single conductivity type. Numerous other aspects are provided.11-08-2012
20110297912Non-Volatile Memory Having 3d Array of Read/Write Elements with Vertical Bit Lines and Laterally Aligned Active Elements and Methods Thereof - A three-dimensional array of memory elements is formed across multiple layers of planes positioned at different distances above a semiconductor substrate. The memory elements reversibly change a level of electrical conductance in response to a voltage difference being applied across them. The three-dimensional array includes a two-dimensional array of pillar lines from the substrate through the multiple layers of planes which together with arrays of word lines on each plane are used to access the memory elements. The memory elements of the multiple layers are formed simultaneously in an orientation parallel to the substrate thereby reducing processing cost. In another aspect, a diode is formed in series with each memory element to reduce current leakage. The diode is incorporated within a pillar line acting as a bit line without taking up additional space.12-08-2011
20120326114PHASE-CHANGE RANDOM ACCESS MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A phase-change random access memory device includes a semiconductor substrate, an interlayer dielectric layer formed over the semiconductor substrate and having contact holes defined therein, metal contacts formed in the contact holes, an ohmic contact layer formed over the metal contacts and having recesses defined therein, and switching elements formed over the recesses of the ohmic contact layer.12-27-2012
20120091429RESISTIVE MEMORY - A memory device memory device includes a first array of memory structures disposed in rows and columns and constructed over a substrate, each memory structure having a first signal electrode, a second signal electrode, and a resistive layer positioned between the first signal electrode and the second signal electrode.04-19-2012
20120091428MANUFACTURING METHOD OF MEMORY APPARATUS, MEMORY DEVICE AND MEMORY APPARATUS - A manufacturing method of a memory apparatus in which memory devices each having a memory layer whose resistance value reversibly varies by voltage application between bottom and upper electrodes are formed, includes: forming and shaping a bottom electrode material film into a first linear pattern extending in a first direction; forming a memory layer material film and an upper electrode material film in this order on the bottom electrode material film; forming the upper electrodes and the memory layers by shaping the upper electrode material film and the memory layer material film into a second linear pattern extending in a second direction intersecting with the first direction; and forming the bottom electrodes having a quadrangle plane shape at regions where the first linear pattern intersect with the second linear pattern by shaping the bottom electrode material film into the second linear pattern.04-19-2012
20120091427MULTI-LEVEL MEMORY ARRAYS WITH MEMORY CELLS THAT EMPLOY BIPOLAR STORAGE ELEMENTS AND METHODS OF FORMING THE SAME - In some embodiments, a memory array is provided that includes (1) a first memory cell having (a) a first conductive line; (b) a first bipolar storage element formed above the first conductive line; and (c) a second conductive line formed above the first bipolar storage element; and (2) a second memory cell formed above the first memory cell and having (a) a second bipolar storage element formed above the second conductive line; and (b) a third conductive line formed above the second bipolar storage element. The first and second memory cells share the second conductive line; the first bipolar storage element has a first storage element polarity orientation within the first memory cell; the second bipolar storage element has a second storage element polarity orientation within the second memory cell; and the second storage element polarity orientation is opposite the first storage element polarity orientation. Numerous other aspects are provided.04-19-2012
20120286232ARRAY OPERATION USING A SCHOTTKY DIODE AS A NON-OHMIC SELECTION DEVICE - A two-terminal memory cell including a Schottky metal-semiconductor contact as a selection device (SD) allows selection of two-terminal cross-point memory array operating voltages that eliminate “half-select leakage current” problems present when other types of non-ohmic devices are used. The SD structure can comprise a “metal/oxide semiconductor/metal” or a “metal/lightly-doped single layer polycrystalline silicon.” The memory cell can include a two-terminal memory element including at least one conductive oxide layer (e.g., a conductive metal oxide—CMO, such as a perovskite or a conductive binary oxide) and an electronically insulating layer (e.g., yttria-stabilized zirconia—YSZ) in contact with the CMO. The SD can be included in the memory cell and configured electrically in series with the memory element. The memory cell can be positioned in a two-terminal cross-point array between a pair of conductive array lines (e.g., a bit line and a word line) across which voltages for data operations are applied.11-15-2012
20120286233MEMORY CELL THAT EMPLOYS A SELECTIVELY DEPOSITED REVERSIBLE RESISTANCE-SWITCHING ELEMENT AND METHODS OF FORMING THE SAME - A memory cell is provided that includes a steering element, a reversible resistance-switching element coupled to the steering element and a silicide-forming metal layer disposed between the steering element and the reversible resistance-switching element. The reversible resistance-switching element includes tantalum, and is formed using a selective deposition process. Numerous other aspects are provided.11-15-2012
20120138885ELECTRICAL CIRCUIT COMPONENT - An electrical circuit component includes a first electrode, a plurality of second electrodes and a negative differential resistance (NDR) material. The first electrode and the plurality of second electrodes are connected to the NDR material and the NDR material is to electrically connect the first electrode to one of the plurality of second electrodes when a sufficient voltage is applied between the first electrode and the one of the plurality of second electrodes through the NDR material.06-07-2012
20080246016Device With Damaged Breakdown Layer - A device utilizing a breakdown layer in combination with a programmable resistance material, a phase-change material or a threshold switching material. The breakdown layer having damage.10-09-2008
20130140516PROTRUDING POST RESISTIVE MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - A resistive memory device may include a substrate, gate electrode structures, a first impurity region, a second impurity region, a first metal silicide pattern and a second metal silicide pattern. The substrate may have a first region where isolation patterns and first active patterns may be alternately arranged in a first direction, and a second region where linear second active patterns may be extended in the first direction. The gate electrode structures may be arranged between the first region and the second region of the substrate. The first and second impurity regions may be formed in the first and second impurity regions. The first metal silicide pattern may have an isolated shape configured to make contact with an upper surface of the first impurity region. The second metal silicide pattern may make contact with an upper surface of the second impurity region.06-06-2013
20080224120Phase change device with offset contact - A programmable resistance memory combines multiple cells into a block that includes one or more shared electrodes. The shared electrode configuration provides additional thermal isolation for the active region of each memory cell, thereby reducing the current required to program each memory cell.09-18-2008
20130175497DEVICE STRUCTURE FOR LONG ENDURANCE MEMRISTORS - A memristor includes a first electrode formed of a first metal, a second electrode formed of a second material, wherein the second material comprises a different material from the first metal, and a switching layer positioned between the first electrode and the second electrode. The switching layer is formed of a composition of a first material comprising the first metal and a second nonmetal material, in which the switching layer is in direct contact with the first electrode and in which at least one conduction channel is configured to be formed in the switching layer from an interaction between the first metal and the second nonmetal material.07-11-2013
20130175496SEMICONDUCTOR MEMORY DEVICE, MEMORY CHIP, MEMORY MODULE, MEMORY SYSTEM AND METHOD FOR FABRICATING THE SAME - A semiconductor memory device and a method for fabricating the same capable of easily controlling a contact area between a conductive line and a memory layer even at the high degree of integration. The semiconductor memory device includes a plurality of first conductive lines, a memory layer contacting with a first sidewall of each of the first conductive lines, and a plurality of second conductive lines crossing the first conductive lines and contacting with the memory layer.07-11-2013
20130134381SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A method of manufacturing a semiconductor device and a semiconductor device made by the method is disclosed. The method comprises forming a buried N+ layer in an upper portion of a P-type substrate; performing ion implantation on the buried N+ layer; annealing the buried N+ layer; forming an epitaxial semiconductor layer on the buried N+ layer through epitaxial deposition, wherein, an upper portion of said epitaxial semiconductor layer and a portion underlying said P+ region of said epitaxial semiconductor layer are doped to form a P+ region and an N− region, respectively. Increasing the ion implant dosage of the BNL layer, adjusting the method of annealing the BNL layer to increase the width of the BNL layer, or increasing the thickness of the EPI layer, reduces the vertical BJT current gain and suppressed the substrate leakage current.05-30-2013
20130092895SEMICONDUCTOR DEVICE AND OPERATION METHOD FOR SAME - A semiconductor device includes a first switching element, a second switching element, and at least one third switching element; wherein the third switching element includes a first terminal and a second terminal, wherein each of the first switching element and the second switching element includes an ion conductor, a first electrode which is disposed so as to have contact with the ion conductor and supplies metal ions to the ion conductor, and a second electrode which is disposed so as to have contact with the ion conductor and is less susceptible to ionization than the first electrode; and wherein 04-18-2013
20130099193Phase Change Memory and Manufacturing Method Therefor - The present invention discloses a phase change memory and a manufacturing method thereof. The phase change memory according to the present invention uses top electrodes provided on the top of storage nodes to heat the storage nodes such that a phase change layer in the storage nodes undergoes a phase change. In the phase change memory of embodiments of the present invention, the contact area between the top electrode and the storage node is relatively small, which is good for phase change. Moreover, each column of storage nodes is connected by the same linear top electrode, which can improve photo alignment shift margin.04-25-2013
20130134382Selector Device for Memory Applications - The present disclosure is related to a selector device for memory applications. The selector device for selecting a memory element in a memory array comprises an MIT element and a decoupled heater, thermally linked to the MIT element. The MIT element comprises a MIT material component and a barrier component and is switchable from a high to a low resistance state by heating the MIT element above a transition temperature with the decoupled heater. The barrier component is provided to increase the resistance of the MIT element in the high resistance state.05-30-2013
20080210926Three-dimensional phase-change memory array - A three-dimensional phase-change memory array. In one embodiment of the invention, the memory array includes a first plurality of diodes, a second plurality of diodes disposed above the first plurality of diodes, a first plurality phase-change memory elements disposed above the first and second plurality of diodes and a second plurality of memory elements disposed above the first plurality of memory elements.09-04-2008
20130181183RESISTIVE MEMORY CELL STRUCTURES AND METHODS - Resistive memory cell structures and methods are described herein. One or more memory cell structures comprise a first resistive memory cell comprising a first resistance variable material and a second resistive memory cell comprising a second resistance variable material that is different than the first resistance variable material.07-18-2013
20130146833MEMORY CELLS HAVING A PLURALITY OF HEATERS - Resistive memory cells having a plurality of heaters and methods of operating and forming the same are described herein. As an example, a resistive memory cell may include a resistance variable material located between a first electrode and a second electrode, a first heater coupled to a first portion of the resistance variable material, a second heater coupled to a second portion of the resistance variable material, a third heater coupled to a third portion of resistance variable material, and a conductive material coupled to the first, second, and third heaters.06-13-2013
20080197338Bottom electrode for memory device and method of forming the same - Contacts having use in an integrated circuit and exemplary methods of forming the contacts are disclosed. The methods involve forming a conductive cap over a metal plug. The invention can mitigate keyholes in the contacts by capping and encapsulating the conductive material used to form the contact. The exemplary cap may be made of a nitride material.08-21-2008
20110227031Memristor Devices Configured to Control Bubble Formation - Various embodiments of the present invention are direct to nanoscale, reconfigurable, two-terminal memristor devices. In one aspect, a device (09-22-2011
20110240952PROGRAMMABLE CROSSPOINT DEVICE WITH AN INTEGRAL DIODE - A programmable crosspoint device with an integral diode includes a first crossbar, a second crossbar, a metallic interlayer, and a switching oxide layer interposed between the first crossbar and the metallic interlayer. The switching oxide layer has a low resistance state and high resistance state. The programmable crosspoint device also includes an integral diode which is interposed between the second crossbar layer and the metallic interlayer, the integral diode being configured to limit the flow of leakage current through the programmable crosspoint device in one direction. A method for forming a programmable crosspoint device with an integrated diode is also provided.10-06-2011
20130126823MEMORY DEVICE INCLUDING TRANSISTOR ARRAY WITH SHARED PLATE CHANNEL AND METHOD FOR MAKING THE SAME - The present invention relates to memory devices incorporating therein a novel memory cell architecture which includes an array of selection transistors sharing a common channel and method for making the same. A memory device comprises a semiconductor substrate having a first type conductivity, a plurality of drain regions and a common source region separated by a common plate channel in the substrate, and a selection gate disposed on top of the plate channel with a gate dielectric layer interposed therebetween. The plurality of drain regions and the common source region have a second type conductivity opposite to the first type provided in the substrate.05-23-2013
20130126822Method Arrays and Methods of Forming Memory Cells - Some embodiments include methods of forming memory cells. A stack includes ovonic material over an electrically conductive region. The stack is patterned into rails that extend along a first direction. The rails are patterned into pillars. Electrically conductive lines are formed over the ovonic material. The electrically conductive lines extend along a second direction that intersects the first direction. The electrically conductive lines interconnect the pillars along the second direction. Some embodiments include a memory array having first electrically conductive lines extending along a first direction. The lines contain n-type doped regions of semiconductor material. Pillars are over the first conductive lines and contain mesas of the n-type doped regions together with p-type doped regions and ovonic material. Second electrically conductive lines are over the ovonic material and extend along a second direction that intersects the first direction. The second electrically conductive lines interconnect the pillars along the second direction.05-23-2013
20110303890Electrically Actuated Device - An electrically actuated device includes a first electrode and a second electrode crossing the first electrode at a non-zero angle, thereby forming a junction therebetween. A material is established on the first electrode and at the junction. At least a portion of the material is a matrix region. A current conduction channel extends substantially vertically between the first and second electrodes, and is defined in at least a portion of the material positioned at the junction. The current conduction channel has a controlled profile of dopants therein.12-15-2011
20110309322RESISTANCE CHANGE MEMORY DEVICE WITH THREE-DIMENSIONAL STRUCTURE, AND DEVICE ARRAY, ELECTRONIC PRODUCT AND MANUFACTURING METHOD THEREFOR - Provided are a resistance change memory device with a three-dimensional structure, a resistance change memory device array, an electronic product, and a manufacturing method therefor. The device array includes a plurality of first directional data lines which are arranged on a substrate in parallel. A conductive pillar is positioned between sidewalls of the first directional data lines, which face each other. A resistance change material film is positioned between the sidewall of the conductive pillar and the sidewall of the data lines that are adjacent to the sidewall of the conductive pillar.12-22-2011
20110309321MEMRISTORS WITH A SWITCHING LAYER COMPRISING A COMPOSITE OF MULTIPLE PHASES - A memristor with a switching layer that includes a composite of multiple phases is disclosed. The memristor comprises: a first electrode; a second electrode spaced from the first electrode; and a switching layer positioned between the first electrode and the second electrode, the switching layer comprising the multi-phase composite system that comprises a first majority phase comprising a relatively insulating matrix of a switching material and a second minority phase comprising a relatively conducting material for forming at least one conducting channel in the switching layer during a fabrication process of the memristor. A method of making the memristor and a crossbar employing the memristor are also disclosed.12-22-2011
20130187120MEMORY CELLS HAVING HEATERS WITH ANGLED SIDEWALLS - Memory cells having heaters with angled sidewalls and methods of forming the same are described herein. As an example, a method of forming an array of resistive memory cells can include forming a first resistive memory cell having a first heater element angled with respect to a vertical plane, forming a second resistive memory cell adjacent to the first resistive memory cell and having a second heater element angled with respect to the vertical plane and toward the first heater, and forming a third resistive memory cell adjacent to the first resistive memory cell and having a third heater element angled with respect to the vertical plane and away from the first heater element.07-25-2013
20130193398MEMORY ARRAYS AND METHODS OF FORMING SAME - Memory arrays and methods of forming the same are provided. One example method of forming a memory array can include forming a first conductive material having a looped feature using a self-aligning multiple patterning technique, and forming a first sealing material over the looped feature. A first chop mask material is formed over the first sealing material. The looped feature and the first sealing material are removed outside the first chop mask material.08-01-2013
201301933993D SOLID-STATE ARRANGEMENT FOR SOLID STATE MEMORY - The present invention generally relates to the three-dimensional arrangement of memory cells. This 3D arrangement and orientation is made with macro cells that enable the programming, reading and/or querying of any memory cell in the 3D array without the need for overhead wiring or by utilizing a minimal amount of overhead wiring. The individual macro cells are electrically coupled together such that a single transistor on the substrate can be utilized to address multiple macro cells. In such an arrangement, all the auxiliary circuits for addressing memory elements are simplified thereby diminishing their integrated circuit area.08-01-2013
20130193400Memory Cell Structures and Memory Arrays - Some embodiments include memory cell structures. The structures include a vertical transistor having a bottom source/drain region electrically coupled to a first access/sense line, and having a gate comprised by a second access/sense line. The structures also include programmable material over the vertical transistor and electrically coupled with a top source/drain region of the vertical transistor, with the programmable material having at least two compositionally different regions. The structures also include an electrically conductive material over and directly against the programmable material. Some embodiments include memory arrays.08-01-2013
20130193401SELF-ALIGNED PROCESS TO FABRICATE A MEMORY CELL ARRAY WITH A SURROUNDING-GATE ACCESS TRANSISTOR - A memory array including a plurality of memory cells. Each word line is electrically coupled to a set of memory cells, a gate contact and a pair of dielectric pillars positioned parallel to the word line. Dielectric pillars are placed on both sides of the gate contact. Also a method to prevent a gate contact from electrically connecting to a source contact for a plurality of memory cells on a substrate. The method includes formation of a pair of pillars made of an insulating material over the substrate, depositing an electrically conductive gate material between and over the pillars, etching the gate material such that it both partially fills a space between the pair of pillars and forms a word line for the memory cells, and depositing a gate contact between the dielectric pillars such that the gate contact is in electrical contact with the gate material.08-01-2013
20120018698LOW-POWER NANOSCALE SWITCHING DEVICE WITH AN AMORPHOUS SWITCHING MATERIAL - A nanoscale switching device exhibits multiple desired properties including a low switching current level, being electroforming-free, and cycling endurance. The switching device has an active region disposed between two electrodes. The active region contains a switching material capable of transporting dopants under an electric field. The switching material is in an amorphous state and formed by deposition at or below room temperature.01-26-2012
20120018697SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device in accordance with an embodiment comprises first lines, second lines, and a memory cell array including memory cells. Each of the memory cells is disposed at each of intersections of the first lines and the second lines and is configured by a rectifier element and a variable resistor connected in series. The rectifier element comprises a first semiconductor region of a first conductivity type including an impurity of a first impurity concentration, and a second semiconductor region of a second conductivity type including an impurity of a second impurity concentration lower than the first impurity concentration. The first semiconductor region and the second semiconductor region are formed by silicon. A junction interface of the first semiconductor region and the second semiconductor region is a pseudo-heterojunction formed by two layers that have different band gap widths and are formed of the same material.01-26-2012
20120018696VERTICAL PHASE CHANGE MEMORY CELL - A vertical phase change memory cell (01-26-2012
20130193402PHASE-CHANGE RANDOM ACCESS MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A phase-change random access memory (PCRAM) device and a method of manufacturing the same. The PCRAM device includes memory cells that each include a semiconductor substrate having a switching element, a lower electrode formed on the switching element, a phase-change layer formed on the lower electrode, and an upper electrode formed on the phase-change layer; and a porous insulating layer arranged to insulate one memory cell from another memory cell of the memory cells.08-01-2013
20130193403Memory Arrays and Methods of Forming Memory Cells - Some embodiments include methods of forming memory cells utilizing various arrangements of conductive lines, electrodes and programmable material; with the programmable material containing high k dielectric material directly against multivalent metal oxide. Some embodiments include arrays of memory cells, with the memory cells including programmable material containing high k dielectric material directly against multivalent metal oxide.08-01-2013
20130200330SELF-ALIGNED PROCESS TO FABRICATE A MEMORY CELL ARRAY WITH A SURROUNDING-GATE ACCESS TRANSISTOR - A memory array including a plurality of memory cells. Each word line is electrically coupled to a set of memory cells, a gate contact and a pair of dielectric pillars positioned parallel to the word line and placed on both sides of the gate contact over a layer of insulating material. Also a method to prevent a gate contact from electrically connecting to a source contact for a plurality of memory cells on a substrate. The method includes formation of a pair of pillars over an insulating material on the substrate, depositing an electrically conductive gate material between and over the pillars, etching the gate material such that it both partially fills a space between the pair of pillars and forms a word line for the memory cells, and depositing a gate contact between the dielectric pillars such that the gate contact is in electrical contact with the gate material.08-08-2013
20130200331SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - In a semiconductor storage device where a plurality of memory cells obtained by connecting a vertical transistor and a phase-change element in parallel is formed along a direction perpendicular to a main face of a semiconductor substrate, highly-reliable selection operation is made possible with a further low voltage. A plurality of through-holes extending through insulating films and polysilicon layers is formed in regions at which word lines and bit lines intersect with each other. A plurality of vertical chain memories composed of a gate insulating film 08-08-2013

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