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With means to localize region of conduction (e.g., "pore" structure)

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257 - Active solid-state devices (e.g., transistors, solid-state diodes)

257001000 - BULK EFFECT DEVICE

257002000 - Bulk effect switching in amorphous material

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DocumentTitleDate
20090194757PHASE CHANGE ELEMENT EXTENSION EMBEDDED IN AN ELECTRODE - The present invention in one embodiment provides a method of forming a memory device that includes providing an interlevel dielectric layer including a conductive stud having a first width; forming an stack comprising a metal layer and a first insulating layer; forming a second insulating layer atop portions of the interlevel dielectric layer adjacent each sidewall of the stack; removing the first insulating layer to provide a cavity; forming a conformal insulating layer atop the second insulating layer and the cavity; applying an anisotropic etch step to the conformal insulating layer to produce a opening having a second width exposing an upper surface of the metal layer, wherein the first width is greater than the second width; and forming a memory material layer in the opening.08-06-2009
20090194756Self-aligned eletrode phase change memory - A phase change memory may be formed with an upper electrode self-aligned to a phase change memory element. In some embodiments, patterning techniques may be used to form the elements of the memory. The memory element may be formed as a sidewall spacer formed on both opposed sides of an elongate strip of material. The resulting elongate strip of phase change memory element material may then be singulated in the same etching step that forms the upper electrodes extending in the column direction. Thus, the memory elements may be singulated in the row direction, while, at the same time, the top electrodes are defined to extend continuously in the column direction.08-06-2009
20130075685METHODS AND APPARATUS FOR INCLUDING AN AIR GAP IN CARBON-BASED MEMORY DEVICES - In some aspects, a reversible resistance-switching metal-insulator-metal stack is provided that includes a first conducting layer, a carbon nano-tube (“CNT”) material above the first conducting layer, a second conducting layer above the CNT material, and an air gap between the first conducting layer and the CNT material. Numerous other aspects are provided.03-28-2013
20110193048NON-VOLATILE MEMORY DEVICE HAVING BOTTOM ELECTRODE - Provided is a non-volatile memory device including a bottom electrode disposed on a substrate and having a lower part and an upper part. A conductive spacer is disposed on a sidewall of the lower part of the bottom electrode. A nitride spacer is disposed on a top surface of the conductive spacer and a sidewall of the upper part of the bottom electrode. A resistance changeable element is disposed on the upper part of the bottom electrode and the nitride spacer. The upper part of the bottom electrode contains nitrogen (N).08-11-2011
20130037776VARIABLE RESISTANCE MEMORY - A variable resistance memory according to an embodiment includes: a first wiring; a second wiring intersecting with the first wiring; a first electrode provided in an intersection region between the first wiring and the second wiring, the first electrode being connected to the first wiring; a second electrode connected to the second wiring, the second electrode facing to the first electrode; a variable resistance layer provided between the first electrode and the second electrode; and one of a first insulating layer and a first semiconductor layer formed at side portions of the second electrode. The one of the first insulating layer and the first semiconductor layer, and the second electrode form voids at the side portions of the second electrode.02-14-2013
20100163831DEPOSITED SEMICONDUCTOR STRUCTURE TO MINIMIZE N-TYPE DOPANT DIFFUSION AND METHOD OF MAKING - A microelectronic structure including a layerstack is provided, the layerstack including: (a) a first layer including semiconductor material that is very heavily n-doped before being annealed, having a first-layer before-anneal dopant concentration, the first layer being between about 50 and 200 angstroms thick, wherein the first layer is above a substrate, and wherein the first layer is heavily n-doped after being annealed, having a first-layer after-anneal dopant concentration, the first-layer before-anneal dopant concentration exceeding the first-layer after-anneal concentration; (b) a second layer including semiconductor material that is not heavily doped before being annealed, having a second-layer before-anneal dopant concentration, the second layer being about as thick as the first layer, wherein the second layer is above and in contact with the first layer, and wherein the second layer includes heavily n-doped semiconductor material after being annealed, having a second-layer after-anneal dopant concentration, the second-layer after-anneal dopant concentration exceeding the second-layer before-anneal concentration; and (c) a third layer including semiconductor material that is above and in contact with the second layer and that is not heavily n-doped before or after being annealed, the third layer having a third-layer dopant concentration.07-01-2010
20100163828PHASE CHANGE MEMORY DEVICES AND METHODS FOR FABRICATING THE SAME - A phase change memory device is provided, including a semiconductor substrate with a first conductive semiconductor layer disposed thereover, wherein the first conductive semiconductor layer has a first conductivity type. A first dielectric layer is disposed over the semiconductor substrate. A second conductive semiconductor layer having a second conductivity type opposite to the first conductivity type is disposed in the first dielectric layer. A heating electrode is disposed in the first dielectric layer and formed over the second conductive semiconductor layer, wherein the heating electrode has a tapered cross section and includes metal silicide. A second dielectric layer is disposed over the first dielectric layer. A phase change material layer is disposed in the second dielectric layer. An electrode is disposed over the second dielectric layer, covering the phase change material layer.07-01-2010
20100163830PHASE-CHANGE RANDOM ACCESS MEMORY CAPABLE OF REDUCING THERMAL BUDGET AND METHOD OF MANUFACTURING THE SAME - A phase-change random access memory (PRAM) is presented which can ensure the integrity of the electrical characteristics of driving transistors even when the PRAM is with a high temperature SEG fabrication process because the fabrication time is minimized. A method of manufacturing the PRAM includes the following steps. After preparing a semiconductor substrate having a cell area and a peripheral area, a junction area is formed in the cell area. Then, a transistor having a gate electrode with a single conductive layer is formed in the peripheral area. Subsequently, a first interlayer dielectric layer is formed at an upper portion of the semiconductor substrate, and then a contact hole is formed by etching the first interlayer dielectric layer to expose a predetermined portion of the junction area. Next, an epitaxial layer is grown in the contact hole.07-01-2010
20100163825FORMING PHASE CHANGE MEMORIES WITH A BREAKDOWN LAYER SANDWICHED BY PHASE CHANGE MEMORY MATERIAL - A phase change memory cell may be formed with a pair of chalcogenide phase change layers that are separated by a breakdown layer. The breakdown layer may be broken down prior to use of the memory so that a conductive breakdown point is defined within the breakdown layer. In some cases, the breakdown point may be well isolated from the surrounding atmosphere, reducing heat losses and decreasing current consumption. In addition, in some cases, the breakdown point may be well isolated from overlying and underlying electrodes, reducing issues related to contamination. The breakdown point may be placed between a pair of chalcogenide layers with the electrodes outbound of the two chalcogenide layers.07-01-2010
20100078619RESISTIVE MEMORY CELL AND METHOD FOR MANUFACTURING A RESISTIVE MEMORY CELL - A resistive memory cell includes a structural layer, a pore in the structural layer, a selector, having a coupling terminal accommodated in the pore, and a storage element of a resistive memory material, arranged in the pore and electrically coupled to the coupling terminal of the selector. The storage element has a tubular portion, extending transversely to an electrical coupling interface of the coupling terminal.04-01-2010
20100117047NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - A non-volatile semiconductor storage device includes a plurality of memory element groups, each of the memory element groups having a plurality of memory elements, each of the memory elements having a resistance-change element and a Schottky diode connected in series. Each of the memory element groups includes: a first columnar layer extending in a lamination direction; a first insulation layer formed on a side surface of the first columnar layer and functioning as the resistance-change element; and a first conductive layer formed to surround the first columnar layer via the first insulation layer. The first conductive layer is formed of metal. The first columnar layer is formed of a semiconductor having such a impurity concentration that the first conductive layer and the semiconductor configure the Schottky diode.05-13-2010
20100072447PHASE CHANGE MEMORY CELL HAVING INTERFACE STRUCTURES WITH ESSENTIALLY EQUAL THERMAL IMPEDANCES AND MANUFACTURING METHODS - A memory device as described herein includes a memory member contacting first and second interface structures. The first interface structure electrically and thermally couples the memory member to access circuitry and has a first thermal impedance therebetween. The second interface structure electrically and thermally couples the memory member to a bit line structure and has a second thermal impedance therebetween. The first and second thermal impedances are essentially equal such that applying a reset pulse results in a phase transition of an active region of the memory member spaced away from both the first and second interface structures.03-25-2010
20100108974PHASE CHANGE MEMORY DEVICE HAVING A DIODE THAT HAS AN ENLARGED PN INTERFACIAL JUNCTION AND METHOD FOR MANUFACTURING THE SAME - A phase change memory device that has a diode with an enlarged, i.e., bulging, PN interfacial junction and a corresponding fabrication method are presented. The phase change memory device includes a semiconductor substrate, an insulation layer, a diode, and a phase change memory cell. The insulation layer is placed on the semiconductor substrate and has a contact hole which is wider in a middle portion than the lower and upper portions of the contact hole. The diode is formed within the contact hole and PN interfacial junction at the wider middle portion of the diode within the contact hole. The phase change memory cell is formed on top of the diode.05-06-2010
20090140229Active material devices with containment layer - An active material electronic device is described with a containment layer. The device includes an active chalcogenide, pnictide, or phase-change material in electrical communication with an upper and lower electrode. The device includes a containment layer formed over the active material that prevents escape of volatilized matter from the active material when the device is exposed to high temperatures during fabrication or operation. The containment layer further prevents chemical contamination of the active material by protecting it from reactive species in the processing or ambient environment. The containment layer and intermediate layers formed between the active material and containment layer are formed at temperatures sufficiently low to prevent volatilization of the active material. Once the containment layer is formed, the device may be subjected to high temperature or chemically aggressive environments without impairing the compositional or structural integrity of the active material. Inclusion of the containment layer is shown to extend the cycle life of the device by over two orders of magnitude.06-04-2009
20090302297PHASE CHANGE MEMORY DEVICES AND THEIR METHODS OF FABRICATION - In an embodiment, a phase change memory device includes a semiconductor substrate of a first conductivity type and a first interlayer insulating layer disposed on the semiconductor substrate. A hole penetrates the first interlayer insulating layer. A first and a second semiconductor pattern are sequentially stacked in a lower region of the hole. A cell electrode is provided on the second semiconductor pattern. The cell electrode has a lower surface than a top surface of the first interlayer insulating layer. A confined phase change material pattern fills the hole on the cell electrode. An upper electrode is disposed on the phase change material pattern. The phase change material pattern in the hole is self-aligned with the first and second semiconductor patterns by the hole. A method of fabricating the phase change memory device is also provided.12-10-2009
20090236582PHASE-CHANGE RAM AND METHOD FOR FABRICATING THE SAME - A PRAM and a fabricating method thereof are provided. The PRAM includes a transistor and a data storage capability. The data storage capability is connected to the transistor. The data storage includes a top electrode, a bottom electrode, and a porous PCM layer. The porous PCM layer is interposed between the top electrode and the bottom electrode.09-24-2009
20120235108METHOD OF FORMING MEMORY CELL USING GAS CLUSTER ION BEAMS - A variable resistance memory cell structure and a method of forming it. The method includes forming a first electrode, forming an insulating material over the first electrode, forming a via in the insulating material to expose a surface of the first electrode, forming a heater material within the via using gas cluster ion beams, forming a variable resistance material within the via, and forming a second electrode such that the heater material and variable resistance material are provided between the first and second electrodes.09-20-2012
20090134379Phase-change nonvolatile memory and manufacturing method therefor - A phase-change nonvolatile memory (PRAM) is constituted of a semiconductor substrate, a lower electrode, a first interlayer insulating film having a first hole, an impurity diffusion layer embedded in the first hole, a second interlayer insulating film having a second hole whose diameter is smaller than the diameter of the first hole, a phase-change recording layer, and an upper electrode. The impurity diffusion layer is constituted of two semiconductor layers having different conductivity types, wherein one semiconductor layer is constituted of a base portion and a projecting portion having a heating spot in contact with the phase-change recording layer, while the other semiconductor layer is formed to surround the projecting portion. A depletion layer is formed in proximity to the junction surface so as to reduce the diameter of the heating spot, thus reducing the current value Ireset for writing data in to the phase-change recording layer.05-28-2009
20100163829CONDUCTIVE BRIDGING RANDOM ACCESS MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A conductive bridging random access memory (CBRAM) device and a method of manufacturing the same are provided. The CBRAM device includes a first electrode layer, a dielectric layer, a solid electrolyte layer, a second electrode layer and a metal layer. The solid electrolyte layer is located on the first electrode layer. The second electrode layer is located on the solid electrolyte layer. The metal layer is located near the solid electrolyte layer. The dielectric layer is located between the solid electrolyte layer and the metal layer. Since the metal layer is disposed near the solid electrolyte layer in the CBRAM device, it can generate a positive electric field during an erase operation, so as to accelerate a break of mutually connected metal filaments.07-01-2010
20110278530MEMORY DEVICE INCORPORATING A RESISTANCE VARIABLE CHALCOGENIDE ELEMENT - A memory device comprising a first electrode, a second electrode, metal-chalcogenide material between the first and second electrodes and chalcogenide glass between the first and second electrodes. The chalcogenide glass comprises a material with the chemical formula A11-17-2011
20110133150Phase Change Memory Cell with Filled Sidewall Memory Element and Method for Fabricating the Same - Memory cells are described along with methods for manufacturing. A memory cell described herein includes a bottom electrode, a top electrode overlying the bottom electrode, a via having a sidewall extending from a bottom electrode to a top electrode, and a memory element electrically coupling the bottom electrode to the top electrode. The memory element has an outer surface contacting a dielectric sidewall spacer that is on the sidewall of the via, and comprises a stem portion on the bottom electrode and a cup portion on the stem portion. A fill material is within an interior defined by an inner surface of the cup portion of the memory element.06-09-2011
20110127485KEYHOLE-FREE SLOPED HEATER FOR PHASE CHANGE MEMORY - Subject matter disclosed herein relates to a method of manufacturing a semiconductor integrated circuit device, and more particularly to a method of fabricating a phase change memory device.06-02-2011
20100090191Cross point memory arrays, methods of manufacturing the same, masters for imprint processes, and methods of manufacturing masters - A cross point memory array includes a structure in which holes are formed in an insulating layer and a storage node is formed in each of the holes. The storage node may include a memory resistor and a switching structure. The master for an imprint process used to form the cross-point memory array includes various pattern shapes, and the method of manufacturing the master uses various etching methods.04-15-2010
20090267046MEMORY STRUCTURE WITH A PROGRAMMABLE RESISTIVE ELEMENT AND ITS MANUFACTURING PROCESS - A memory structure has an access transistor connected in series with a programmable resistive element, wherein the programmable resistive element comprises on a semiconductor substrate; an insulated layer with a cavity comprising: a first layer lining the lateral surfaces and the bottom of the said cavity and impermeable to the diffusion of metal; a second layer made of porous material on the said first layer; a third layer of metallic material allowing to realize a contact electrode susceptible to spread within the said formed porous material of the second layer. Diffusion of metallic ions within the said second layer is controlled by the joint action of an electric field and temperature. A manufacturing process is also described.10-29-2009
20090267045PHASE CHANGE MEMORY DEVICE HAVING HEATERS AND METHOD FOR MANUFACTURING THE SAME - A phase change memory device includes switching elements formed on a substrate that includes a cell region and a peripheral region. Heat sinks are formed on the switching elements. Heaters are formed on the heat sink and a phase change layer is formed on the heaters.10-29-2009
20090267044PHASE CHANGE MEMORY DEVICE HAVING A BENT HEATER AND METHOD FOR MANUFACTURING THE SAME - A phase change memory device includes heaters which are formed in their respective memory cells and vertically positioned stack patterns having phase change layers and top electrodes which are formed to come into contact with the heaters. The heaters have horizontal cross-sectional bent shapes which can have any number of shapes such as a shape similar to that of a boomerang. The horizontal cross-sectional bent shapes of the heaters are for minimizing the contact area between the heaters and the phase change layer so that programming currents can be reduced or minimized.10-29-2009
20120097914MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a memory device includes a selection element layer, a nanomaterial aggregate layer, and a fine particle. The nanomaterial aggregate layer is stacked on the selection element layer. The nanomaterial aggregate layer has a plurality of micro conductive bodies aggregated with an interposed gap. The fine particle has at least a surface made of silicon oxynitride. The fine particle is dispersed between the micro conductive bodies in one portion of the nanomaterial aggregate layer piercing the nanomaterial aggregate layer in a thickness direction.04-26-2012
20120097913Integrated Circuitry Comprising Nonvolatile memory Cells And Methods Of Forming A Nonvolatile Memory Cell - An integrated circuit has a nonvolatile memory cell that includes a first electrode, a second electrode, and an ion conductive material there-between. At least one of the first and second electrodes has an electrochemically active surface received directly against the ion conductive material. The second electrode is elevationally outward of the first electrode. The first electrode extends laterally in a first direction and the ion conductive material extends in a second direction different from and intersecting the first direction. The first electrode is received directly against the ion conductive material only where the first and second directions intersect. Other embodiments, including method embodiments, are disclosed.04-26-2012
20090189138FILL-IN ETCHING FREE PORE DEVICE - A memory cell includes a memory cell layer with a first dielectric layer over a bottom electrode layer, a second dielectric layer over the first dielectric layer, and a top electrode over the second dielectric layer. The dielectric layers define a via having a first part bounded by the first electrode layer and the bottom electrode and a second part bounded by the second dielectric layer and the top electrode. A memory element is within the via and is in electrical contact with the top and bottom electrodes. The first and second parts of the via may comprise a constricted, energy-concentrating region and an enlarged region respectively. The constricted region may have a width smaller than the minimum feature size of the process used to form the enlarged region of the via. A method for manufacturing a memory cell is also disclosed.07-30-2009
20090189139PORE PHASE CHANGE MATERIAL CELL FABRICATED FROM RECESSED PILLAR - A method of manufacturing an electrode is provided that includes providing a pillar of a first phase change material atop a conductive structure of a dielectric layer; or the inverted structure; forming an insulating material atop dielectric layer and adjacent the pillar, wherein an upper surface of the first insulating material is coplanar with an upper surface of the pillar; recessing the upper surface of the pillar below the upper surface of the insulating material to provide a recessed cavity; and forming a second phase change material atop the recessed cavity and the upper surface of the insulating material, wherein the second phase change material has a greater phase resistivity than the first phase change material.07-30-2009
20110266511Phase Change Memory Device with Air Gap - A semiconductor device is provided which includes a bottom electrode contact formed on a substrate, and a dielectric layer formed on the bottom electrode contact. The device further includes a heating element formed in the dielectric layer, wherein the heating element is disposed between two air gaps separating the heating element from the dielectric layer, and a phase change element formed on the heating element, wherein the phase change element includes a substantially amorphous background and an active region, the active region capable of changing phase between amorphous and crystalline. A method of forming such a device is also provided.11-03-2011
20090146127PHASE CHANGE MEMORY - Phase change memories comprising a top electrode, a phase change element, a plurality of via holes allocated between the top electrode and the phase change element, at least four heaters aiming at different regions of the phase change element, and a plurality of bottom electrodes and transistors corresponding to the heaters. The bottom electrodes are respectively coupled to the heaters. Regarding the transistors, their first terminals are respectively coupled to the bottom electrodes, their control terminals are used for coupling to word lines, and their second terminals are used for coupling to bit lines. In an embodiment with four heaters, the regions the heaters aimed at the phase change element form a 2×2 storage array.06-11-2009
20100038619VARIABLE RESISTANCE ELEMENT, MANUFACTURING METHOD THEREOF, AND ELECTRONIC DEVICE - A variable resistance element includes a first conductive portion; an insulating film pattern provided on the first conductive portion; a level difference with respect to the upper surface of the first conductive portion, the level difference being formed of the insulating film pattern; a variable resistance film provided on a side surface of the level difference and having contact with the upper surface of the first conductive portion on the lower-end side of the side surface of the level difference; and a second conductive portion having contact with the variable resistance film on the upper-end side of the side surface of the level difference.02-18-2010
20080237563Diode/superionic conductor/polymer memory structure - A conjugated polymer layer with a built-in diode is formed by providing a first metal-chalcogenide layer over a bottom electrode. Subsequently, a second metal-chalcogenide layer is provided over and in contact with the first metal-chalcogenide layer. The first metal-chalcogenide layer has a first conductivity type and the second metal-chalcogenide layer has a second conductivity type. The plane of contact between the first and second metal-chalcogenide layers creates the p-n junction of the built-in diode. Then a polymer layer is selectively deposited on the second metal-chalcogenide layer. The second metal-chalcogenide layer provides ions to the polymer layer to change its resistivity. A top electrode is then provided over the polymer layer. An exemplary memory cell may have the following stacked structure: first electrode/n-type semiconductor/p-type semiconductor/conjugated polymer/second electrode.10-02-2008
20080237564Phase-Change Memory Device Using Sb-Se Metal Alloy and Method of Fabricating the Same - Provided are a phase-change memory device using a phase-change material having a low melting point and a high crystallization speed, and a method of fabricating the same. The phase-change memory device includes an antimony (Sb)-selenium (Se) chalcogenide Sb10-02-2008
20080265238PHASE CHANGE MEMORY DEVICES AND METHODS FOR MANUFACTURING THE SAME - Phase change memory devices and methods for manufacturing the same are provided. An exemplary embodiment of a phase change memory device includes a first electrode disposed in a first dielectric layer. A second dielectric layer is disposed over the first dielectric layer and the first electrode. A phase change material layer disposed in the second dielectric layer to electrically contact the first electrode. A third dielectric layer is disposed over the second dielectric layer. A second electrode is disposed in the third dielectric layer to electrically connect the phase change material layer and at least one gap disposed in the first dielectric layer or the second dielectric layer to thereby isolate portions of the phase change material layer and portions of the first or second dielectric layer adjacent thereto.10-30-2008
20080265236VARIABLE RESISTANCE NON-VOLATILE MEMORY CELLS AND METHODS OF FABRICATING SAME - Methods of fabricating integrated circuit memory cells and integrated circuit memory cells are disclosed. Formation of an integrated circuit memory cell include forming a first electrode on a substrate. An insulation layer is formed on the substrate with an opening that exposes at least a portion of a first electrode. An amorphous variable resistivity material is formed on the first electrode and extends away from the first electrode along sidewalls of the opening. A crystalline variable resistivity material is formed in the opening on the amorphous variable resistivity material. A second electrode is formed on the crystalline variable resistivity material.10-30-2008
20080265237Phase-Change Memory Cell Having Two Insulated Regions - A phase-change-memory cell is provided which comprises two insulated regions formed in a first phase-change material connected by a region formed in a second phase-change material. The crystallization temperature of the second phase-change material is below the crystallization temperature of the first phase-change material. By locally changing the material properties using a second PCM material, which switches phase at a lower temperature, a localized “hot spot” is obtained.10-30-2008
20100078618Self-assembly process for memory array - A method of making a device includes forming at least one anodizable metal layer over at least one of an electrode or a semiconductor device, forming a plurality of pores in the anodizable metal layer by anodization of the anodizable metal layer to expose a portion of the electrode or semiconductor device, and filling at least one pore with a rewritable material such that at least some of the rewritable material is in electrical contact with the electrode or semiconductor device.04-01-2010
20100078617METHOD TO REDUCE A VIA AREA IN A PHASE CHANGE MEMORY CELL - A memory cell structure and method to form such structure. The method partially comprised of forming a via within an oxidizing layer, over the center of a bottom electrode. The method includes depositing a via spacer along the sidewalls of the via and oxidizing the via spacer. The via spacer being comprised of a material having a Pilling-Bedworth ratio of at least one and one-half and is an insulator when oxidized. The via area is reduced by expansion of the via spacer during the oxidation. Alternatively, the method is partially comprised of forming a via within a first layer, over the center of the bottom electrode. The first layer has a Pilling-Bedworth ratio of at least one and one-half and is an insulator when oxidized. The method also includes oxidizing at least a portion of the sidewalls of the via in the first layer.04-01-2010
20090166600INTEGRATED CIRCUIT DEVICES HAVING A STRESS BUFFER SPACER AND METHODS OF FABRICATING THE SAME - Integrated circuit devices include an integrated circuit substrate and an insulating layer on the integrated circuit substrate. A contact hole penetrates the insulating layer. A vertical diode is in the contact hole and a stress buffer spacer is provided between the vertical diode and the insulating layer. Methods of forming the integrated circuit devices are also provided.07-02-2009
20110198555CHALCOGENIDE FILM AND MANUFACTURING METHOD THEREOF - A chalcogenide film of the present invention is deposited, by sputtering, in a contact hole formed in an insulating layer on a substrate. The chalcogenide film comprises an underlayer film formed at least on a bottom portion of the contact hole and a crystal layer made of a chalcogen compound, and formed onto the underlayer film and in the contact hole.08-18-2011
20100123115Interconnect And Method For Mounting An Electronic Device To A Substrate - An interconnect for mounting an electronic device to a substrate includes a base layer between the electronic device and the substrate in electrical communication with integrated circuits on the electronic device, a phase change layer on the base layer made of a material which is liquid at normal operating temperatures of the electronic device. and a retaining layer surrounding the phase change layer, and configured to retain the phase change layer in liquid form on the base layer.05-20-2010
20090008622Phase Change Memory Devices and Methods of Fabricating the Same - Phase change memory devices are provided including a selection element electrically connected to a phase change material pattern. The selection element includes a metallic conductor and a semiconductor that are in contact with each other. A depletion region in contact with a metallic pattern is generated in the semiconductor in an equilibrium state. The depletion region includes a high barrier region having an electric potential barrier higher than an interface electric potential barrier and a low barrier region having an electric potential barrier lower than the interface electric potential barrier. Related methods are also provided.01-08-2009
20100127233METHOD FOR CONTROLLED FORMATION OF THE RESISTIVE SWITCHING MATERIAL IN A RESISTIVE SWITCHING DEVICE AND DEVICE OBTAINED THEREOF - The present disclosure provides a method for controlled formation of the resistive switching layer in a resistive switching device. The method comprises providing a substrate (05-27-2010
20080296552PHASE CHANGE MEMORY CELL STRUCTURES AND METHODS FOR MANUFACTURING THE SAME - Phase change memory cell structures and methods for fabricating the same are provided. An exemplary embodiment of a phase change memory cell structure includes a first electrode formed over a first dielectric layer. A second dielectric layer is formed over the first electrode. A conductive member is formed through the second dielectric layer and electrically contacting the first electrode, wherein the conductive member comprises a lower element and an upper element sequentially stacking over the first electrode, and the lower and upper elements comprises different materials. A phase change material layer is formed over the second dielectric layer, electrically contacting the conductive member. A second electrode is formed over the phase change material layer.12-04-2008
20090050872PROCESS FOR MANUFACTURING A COPPER COMPATIBLE CHALCOGENIDE PHASE CHANGE MEMORY ELEMENT AND CORRESPONDING PHASE CHANGE MEMORY ELEMENT - A copper-diffusion plug 02-26-2009
20080303014Vertical Phase Change Memory Cell and Methods For Manufacturing Thereof - The present invention discloses a vertical phase-change-memory (PCM) cell, comprising a stack of a bottom electrode (12-11-2008
20080303013INTEGRATED CIRCUIT INCLUDING SPACER DEFINED ELECTRODE - An integrated circuit includes a contact, a first spacer, and a first electrode including a first portion and a second portion. The second portion contacts the contact and is defined by the first spacer. The integrated circuit includes a second electrode and resistivity changing material between the second electrode and the first portion of the first electrode.12-11-2008
20120032131PROGRAMMABLE RESISTIVE MEMORY CELL WITH OXIDE LAYER - Programmable metallization memory cells include an electrochemically active electrode and an inert electrode and an ion conductor solid electrolyte material between the electrochemically active electrode and the inert electrode. An electrically insulating oxide layer separates the ion conductor solid electrolyte material from the electrochemically active electrode.02-09-2012
20080210922Storage nodes and methods of manufacturing and operating the same, phase change memory devices and methods of manufacturing and operating the same - In various embodiments, the present disclosure may provide a storage node. In various implementations, the storage node may include a bottom electrode having a non-planar bottom surface that conforms with and is connected to a non-planar top surface of a diode electrode of a memory device. The storage node may further include a phase change layer on top of a bottom diode and a top electrode on a top surface of a phase change layer.09-04-2008
20090014705PHASE CHANGE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A phase change memory device is provided. The phase change memory device comprises a substrate. A first conductive layer is formed on the substrate. A heating electrode is formed on the first conductive layer, and electrically connected to the first conductive layer, wherein the heating electrode comprises a carbon nanotube (CNT). A phase change material layer covers the heating electrode. A second conductive layer is formed on the phase change material layer, and electrically connected to the phase change material layer.01-15-2009
20090014704CURRENT CONSTRICTING PHASE CHANGE MEMORY ELEMENT STRUCTURE - A layer of nanopaiticles having a dimension on the order of 10 nm is employed to form a current constricting layer or as a hardmask for forming a current constricting layer from an underlying insulator layer. The nanoparticles are preferably self-aligning and/or self-planarizing on the underlying surface. The current constricting layer may be formed within a bottom conductive plate, within a phase change material layer, within a top conductive plate, or within a tapered liner between a tapered via sidewall and a via plug contains either a phase change material or a top conductive material. The current density of the local structure around the current constricting layer is higher than the surrounding area, thus allowing local temperature to rise higher than surrounding material. The total current required to program the phase change memory device, and consequently the size of a programming transistor, is reduced due to the current constricting layer.01-15-2009
20080272357Phase Changeable Memory Device Structures - A phase-changeable memory device may include a substrate, an insulating layer on the substrate, first and second electrodes, and a pattern of a phase-changeable material between the first and second electrodes. More particularly, the insulating layer may have a hole therein, and the first electrode may be in the hole in the insulating layer. Moreover, portions of the second electrode may extend beyond an edge of the pattern of phase-changeable material. Related methods are also discussed.11-06-2008
20100140581BOTTOM ELECTRODE FOR MEMORY DEVICE AND METHOD OF FORMING THE SAME - Contacts having use in an integrated circuit and exemplary methods of forming the contacts are disclosed. The methods involve forming a conductive cap over a metal plug. The invention can mitigate keyholes in the contacts by capping and encapsulating the conductive material used to form the contact. The exemplary cap may be made of a nitride material.06-10-2010
20090159867Phase change memory with layered insulator - A phase change memory may be formed with an insulator made up of two different layers having significantly different thermal conductivities. Pores may be formed within the stack of insulating layers and the pores may be filled with heaters, chalcogenide layers, and electrodes in some embodiments. The use of the two different insulator layers enables embodiments where thermal losses may be reduced and an amorphous region may be maintained along the entire length of the phase change material layer.06-25-2009
20090184308Forming an Intermediate Electrode Between an Ovonic Threshold Switch and a Chalcogenide Memory Element - An intermediate electrode between an ovonic threshold switch and a memory element may be formed in the same pore with the memory element. This may have many advantages including, in some embodiments, reducing leakage.07-23-2009
20090166601Non-volatile programmable variable resistance element - A phase-change memory element exhibits a non-uniform temperature profile in the phase-change material, resulting in a non-uniform temperature profile. The non-uniform temperature profile causes non-uniform growth of a programmed volume, resulting in a gradual R-I characteristic. The phase-change material may be a chalcogenide material.07-02-2009
20090026436Phase change memory devices and methods of forming the same - A method of forming a phase change memory device includes forming a core pattern on a substrate, conformally forming a heat conductive layer on the substrate including the core pattern, anisotropically etching the heat conductive layer down to a top surface of the core pattern to form a heat electrode surrounding a sidewall of the core pattern, and forming a phase change memory pattern connected to a top surface of the heat electrode.01-29-2009
20100270528RESISTIVE RANDOM ACCESS MEMORY DEVICE AND METHOD OF SAME - Disclosed are a resistive random access memory device (ReRAM) and a method for manufacturing the same. The ReRAM includes a cell array including a metal oxide nanowire formed inside a micropore array of a porous template, a first electrode electrically connected to an upper protrusion of the metal oxide nanowire, the upper protrusion being exposed to an upper portion of the porous template, and located in an upper portion of the cell array, and a second electrode electrically connected to a lower protrusion of the metal oxide nanowire, the lower protrusion being exposed to a lower portion of the porous template, and located in a lower portion of the cell array.10-28-2010
20090184306PHASE CHANGE MEMORY CELL WITH FINFET AND METHOD THEREFOR - A phase change memory (PCM) cell includes a transistor, a PCM structure, and a heater. The transistor has a first current electrode and a second current electrode in a structure, and a channel region having a first portion along a first sidewall of the structure and having a second portion along a second sidewall of the structure. The second sidewall is opposite the first sidewall. The transistor has a control electrode that has a first portion adjacent to the first sidewall and a second portion adjacent to the second sidewall. The PCM structure exhibits first and second resistive values when in first and second phase states, respectively. The heater is on the structure and produces heat when current flows through the heater for changing the phase state of the phase change structure.07-23-2009
20090184307PHASE CHANGE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A phase change memory device and a method of fabricating the same are provided. A phase change material layer of the phase change memory device is formed of germanium (Ge)-antimony (Sb)-Tellurium (Te)-based Ge07-23-2009
20090140230Memory Cell Device With Circumferentially-Extending Memory Element - A memory device comprises a contact and a pillar-shaped structure on the contact. The pillar-shaped structure includes a conductive inner element surrounded by a memory outer layer. A transition region is located at the memory outer layer above said contact. The conductive element may directly contact said contact.06-04-2009
20100200829Semiconductor Phase Change Memory Using Multiple Phase Change Layers - In accordance with some embodiments, a phase change memory may be formed in which the thermal conductivity in the region outside the programmed volume of phase change material is reduced. This may reduce the power consumption of the resulting phase change memory. The reduction in power consumption may be achieved by forming distinct layers of phase change material that have little or no mixing between them outside the programmed volume. For example, in one embodiment, a diffusion barrier layer may be maintained between the two distinct phase change layers. In another embodiment, a face centered cubic chalcogenide structure may be utilized.08-12-2010
20090057641Phase Change Memory Cell With First and Second Transition Temperature Portions - A phase change memory cell includes first and second electrodes having generally coplanar surfaces spaced apart by a gap and a phase change bridge electrically coupling the first and second electrodes. The phase change bridge may extend over the generally coplanar surfaces and across the gap. The phase change bridge has a higher transition temperature bridge portion and a lower transition temperature portion. The lower transition temperature portion comprises a phase change region which can be transitioned from generally crystalline to generally amorphous states at a lower temperature than the higher transition temperature portion. A method for making a phase change memory cell is also disclosed.03-05-2009
20090045386Phase-change memory element - A phase-change memory element. The phase-change memory element comprises a first electrode and a second electrode. A first phase change layer is electrically coupled to the first electrode. A second phase change layer is electrically coupled to the second electrode. A conductive bridge is formed between and electrically coupled to the first and second phase change layers.02-19-2009
20090101883Method for manufacturing a resistor random access memory with a self-aligned air gap insulator - A memory device including a programmable resistive memory material is described along with methods for manufacturing the memory device. A memory device disclosed herein includes top and bottom electrodes and a multilayer stack disposed between the top and bottom electrodes. The multilayer stack includes a memory element comprising programmable resistive memory material and has a sidewall surface. An air gap is adjacent to the sidewall surface and self-aligned to the memory element.04-23-2009
20090085023PHASE CHANGE MEMORY STRUCTURES - A phase change memory cell has a first electrode, a heater, a phase change material, and a second electrode. The heater is over the first electrode, and the heater comprises a pillar. The phase change material is around the heater. The second electrode is electrically coupled to the phase change material. In some embodiments, a method includes forming a electrode layer over a substrate, depositing a first layer, providing nanoclusters over the first layer, and etching the first layer. The first layer comprises one of a group consisting of a heater material and a phase change material. The first layer may be etched using the nanocluster defined pattern to form pillars from the first layer.04-02-2009
20090101884PHASE CHANGE MEMORY DEVICES AND METHODS FOR FABRICATING THE SAME - Phase change memory devices and methods for fabricating the same are provided. A phase change memory device includes a first conductive electrode disposed in a first dielectric layer. A second dielectric layer is disposed over the first dielectric layer. A phase change material layer is disposed in the second dielectric layer and electrically connected to the first conductive electrode. A space is disposed in the second dielectric layer to at least isolate a sidewall of the phase change material layer and the second dielectric layer adjacent thereto. A second conductive electrode is disposed in the second dielectric layer and electrically connected to the phase change material layer.04-23-2009
20090101882Programmable Via Devices - A device comprises a heater, a dielectric layer, a phase-change element, and a capping layer. The dielectric layer is disposed at least partially on the heater and defines an opening having a lower portion and an upper portion. The phase-change element occupies the lower portion of the opening and is in thermal contact with the heater. The capping layer overlies the phase-change element and occupies the upper portion of the opening. At least a fraction of the phase-change element is operative to change between lower and higher electrical resistance states in response to an application of an electrical signal to the heater.04-23-2009
20110227022Memristor Having a Nanostructure Forming An Active Region - A memristor having an active region having a first electrode, a second electrode, and a nanostructure connecting the first electrode with the second electrode. The nanostructure includes a generally insulating material configured to have an electrically conductive channel formed in the material. The nanostructure forms the active region and has a length and a thickness, where the length is substantially equivalent to a distance extending from the first electrode to the second electrode along the nanostructure and the thickness is a distance across the nanostructure substantially perpendicular to the length of the nanostructure. The length of the nanostructure is substantially greater than the thickness of the nanostructure.09-22-2011
20090200534METHOD FOR FABRICATION OF POLYCRYSTALLINE DIODES FOR RESISTIVE MEMORIES - The present invention, in one embodiment, provides a method of producing a PN junction the method including at least the steps of providing a Si-containing substrate; forming an insulating layer on the Si-containing substrate; forming a via through the insulating layer to expose at least a portion of the Si-containing substrate; forming a seed layer of the exposed portion of the Si containing substrate; forming amorphous Si on at least the seed layer; converting at least a portion of the amorphous Si to provide crystalline Si; and forming a first dopant region abutting a second dopant region in the crystalline Si.08-13-2009
20090200535Non-Volatile Memory Element with Improved Temperature Stability - An integrated circuit including a memory element is described. The memory element includes a solid electrolyte layer that includes a matrix material having a metal dissolved therein, and a dopant distributed in the matrix material, the dopant competing with the metal to bind with elements of the matrix material at a crystallization temperature so that at least a portion of the metal in the matrix material remains unbound, to increase the temperature stability of the memory element.08-13-2009
20130214234Resistive Switching Devices and Methods of Formation Thereof - In accordance with an embodiment of the present invention, a resistive switching device includes an opening disposed within a first dielectric layer, a conductive barrier layer disposed on sidewalls of the opening, a fill material including an inert material filling the opening. A solid electrolyte layer is disposed over the opening. The solid electrolyte contacts the fill material but not the conductive barrier layer. A top electrode is disposed over the solid electrolyte.08-22-2013
20120104344SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor element. The semiconductor element comprises a first insulating film, a resistance changing layer, a first electrode, a buried layer, and a second electrode. The first electrode is formed within the opening so as to cover side and bottom surfaces of an inner wall of the opening and so as to include a recessed portion and is in contact with the resistance changing layer via the upper end thereof. The second electrode is formed on the resistance changing layer so as to interpose the resistance changing layer between the second electrode, and the upper end of the first electrode and the buried layer. The semiconductor element changes an electronic resistance between the first and second electrodes by reversibly forming a conductive bridge in the resistance changing layer between the upper end of the first electrode and the second electrode.05-03-2012
20120104343Nonvolatile Memory Cells and Methods Of Forming Nonvolatile Memory Cell - A method of forming a nonvolatile memory cell includes forming a first electrode having a first current conductive material and a circumferentially self-aligned second current conductive material projecting elevationally outward from the first current conductive material. The second current conductive material is different in composition from the first current conductive material. A programmable region is formed over the first current conductive material and over the projecting second current conductive material of the first electrode. A second electrode is formed over the programmable region. In one embodiment, the programmable region is ion conductive material, and at least one of the first and second electrodes has an electrochemically active surface directly against the ion conductive material. Other method and structural aspects are disclosed.05-03-2012
20090095949Low Area Contact Phase-Change Memory - A memory device includes a first electrode and a second electrode. A phase-change material is disposed between the first and second electrodes. The phase-change material is in electrical communication with the first and second electrodes at a first contact region and a second contact region respectively. The first and second contact regions are similar in contact area. The device enables scaling of reset current to smaller dimensions without encountering a limitation imposed by an offset current.04-16-2009
20100264396RING-SHAPED ELECTRODE AND MANUFACTURING METHOD FOR SAME - An electrode structure and a method for manufacturing an integrated circuit electrode includes forming a bottom electrode comprising a pipe-shaped member, filled with a conductive material such as n-doped silicon, and having a ring-shaped top surface. A disc-shaped insulating member is formed on the top of the pipe-shaped member by oxidizing the conductive fill. A layer of programmable resistance material, such as a phase change material, is deposited in contact with the top surface of the pipe-shaped member. A top electrode in contact with the layer of programmable resistance material.10-21-2010
20100155685ELECTRONIC COMPONENT, AND A METHOD OF MANUFACTURING AN ELECTRONIC COMPONENT - An electronic component (06-24-2010
20100012915PHASE-CHANGE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A phase-change memory device in which a phase-change material layer has a multilayered structure with different compositions and a method of fabricating the same are provided. The phase-change memory device includes a first electrode layer formed on a substrate, a heater electrode layer formed on the first electrode layer, an insulating layer formed on the heater electrode layer and having a pore partially exposing the heater electrode layer, a phase-change material layer formed to fill the pore and partially contacting the heater electrode layer, and a second electrode layer formed on the phase-change material layer. The main operating region functioning as a memory operating region is formed of a Ge01-21-2010
20100163827FORMING PHASE CHANGE MEMORY CELLS - Small phase change memory cells may be formed by forming a segmented heater over a substrate. A stop layer may be formed over the heater layer and segmented with the heater layer. Then, sidewall spacers may be formed over the segmented heater to define an aperture between the sidewall spacers that may act as a mask for etching the stop layer over the segmented heater. As a result of the etching using the sidewall spacers as a mask, sublithographic pore may be formed over the heater. Phase change material may be formed within the pore.07-01-2010
20130214235RESISTIVE MEMORY HAVING RECTIFYING CHARACTERISTICS OR AN OHMIC CONTACT LAYER - Disclosed is a resistive memory simultaneously having rectifying characteristics and resistive characteristics according to a bias direction, wherein a resistive diode is interposed between electrodes at the top and bottom thereof. The resistive diode has a form in which a p-type resistive semiconductor layer is bonded to an n-type resistive semiconductor layer. When a high reverse bias is applied to the resistive diode, the resistive diode forms a conductive filament. When a forward bias is applied thereafter, a reset that destroys a portion of the formed conductive filament occurs, and as a result, a high resistance state is formed. Additionally, when a reverse bias is applied again, a set operation regenerating a conductive filament occurs. Thus, a low resistance state is achieved. Moreover, in order to achieve a resistive semiconductor layer and ohmic contact, and suppress the formation of a Schottky barrier, an ohmic contact layer is formed on the resistive diode. The present invention enables each memory cell to read information without misreading said information, even at a low readout voltage, and reduces the driving power required for a memory structure, such that a high-capacity and high-density memory is produced, and complexity and high costs of manufacturing processes may be avoided.08-22-2013
20100193760CURRENT RESTRICTING ELEMENT, MEMORY APPARATUS INCORPORATING CURRENT RESTRICTING ELEMENT, AND FABRICATION METHOD THEREOF - In a current rectifying element (08-05-2010
20090078924Phase Change Memory with Various Grain Sizes - A memory device includes a phase change element, which further includes a first phase change layer having a first grain size; and a second phase change layer over the first phase change layer. The first and the second phase change layers are depth-wise regions of the phase change element. The second phase change layer has a second average grain size different from the first average grain size.03-26-2009
20090008621PHASE-CHANGE MEMORY ELEMENT - A phase-change memory element is provided. The phase-change memory element of an embodiment of the invention comprises a phase-change material layer with a concave, and a heater with an extended part, wherein the extended part of the heater is wedged in the concave of the phase-change material layer. Specifically, the extended part of the heater has a length of 10˜5000 Å.01-08-2009
20100176365RESISTANCE VARIABLE MEMORY DEVICES AND METHODS OF FABRICATING THE SAME - A resistance variable memory device includes at least one bottom electrode, a first insulating layer containing a trench which exposes the at least one bottom electrode, and a resistance variable material layer including respective first and second portions located on opposite sidewalls of the trench, respectively, where the first and second portions of the resistance variable material layer are electrically connected to the at least one bottom electrode. The device further includes a protective layer covering the resistance variable material layer within the trench, and a second insulating layer located within the trench and covering the protective layer within the trench07-15-2010
20100237315Diode structures and resistive random access memory devices having the same - A diode structure includes: a lower electrode and an insulating layer disposed on the lower electrode. The insulating layer includes aperture exposing a portion of the lower electrode. The diode structure further includes: a first layer and a second layer. The first layer is disposed in the aperture and having a depressed portion. The second layer is disposed in the depressed portion of the first layer. A resistive random access memory (RRAM) device includes the above-described diode structure.09-23-2010
20100243981Phase-change random access memory device - A phase-change random access memory device includes an isolation layer structure, an insulating interlayer, a spacer, a switching element and a phase-change material (PCM) layer. The isolation layer structure is in a trench on a substrate, defines an active region in the substrate, and has a recess at an upper portion thereof. The insulating interlayer has an opening partially exposing the active region and the isolation layer structure. The spacer is on a sidewall of the opening and fills the recess. The switching element is in the opening on the exposed active region. The PCM layer is electrically connected to the switching element.09-30-2010
20100237314RESISTANCE CHANGE TYPE MEMORY - A resistance change type memory of an aspect of the present invention including a first wiring configured to extend in a first direction, a second wiring configured to extend in a second direction crossing the first direction, a series circuit configured to connect to the first and second wirings, the series circuit including a non-ohmic element being more conductive in the first to second wiring direction than in the second to first direction and a resistance change type storage element in which data is stored according to a change of a resistance state, an energy supplying circuit configured to connect to the first wiring to supply energy to the first wiring, the energy being used to store the data in the resistance change type storage element, and a capacitance circuit configured to include a capacitive element and being connected to the second wiring.09-23-2010
20100243982VARIABLE RESISTANCE NON-VOLATILE MEMORY CELLS AND METHODS OF FABRICATING SAME - Methods of fabricating integrated circuit memory cells and integrated circuit memory cells are disclosed. An integrated circuit memory cell can be fabricated by forming an ohmic layer on an upper surface of a conductive structure and extending away from the structure along at least a portion of a sidewall of an opening in an insulation layer. An electrode layer is formed on the ohmic layer. A variable resistivity material is formed on the insulation layer and electrically connected to the electrode layer.09-30-2010
20100219392NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD FOR SAME - A three-dimensional memory cell array of memory cells with two terminals having a variable resistive element is formed such that: one ends of memory cells adjacent in Z direction are connected to one of middle selection lines extending in Z direction aligned in X and Y directions; the other ends of the memory cells located at the same point in Z direction are connected to one of third selection lines aligned in Z direction; a two-dimensional array where selection transistors are aligned in X and Y directions is adjacent to the memory cell array in Z direction; gates of selection transistors adjacent in X direction, drains of selection transistors adjacent in Y direction and sources of selection transistors are connected to same first selection line, second selection line, and different middle selection lines, respectively; and first, second and third selection lines are connected to X, Y and Z decoders, respectively.09-02-2010
20100140580Phase Change Memory - A phase change memory is provided. The method includes forming contact plugs in a first dielectric layer. A second dielectric layer is formed overlying the first dielectric layer and a trench formed therein exposing portions of the contact plugs. A metal layer is formed over surfaces of the trench. One or more heaters are formed from the metal layer such that each heater is formed along one or more sidewalls of the trench, wherein the portion of the heater along the sidewalls does not include a corner region of adjacent sidewalls. The trench is filled with a third dielectric layer, and a fourth dielectric layer is formed over the third dielectric layer. Trenches are formed in the fourth dielectric layer and filled with a phase change material. An electrode is formed over the phase change material.06-10-2010
20090114898Method and apparatus for reducing programmed volume of phase change memory - A phase change memory includes a volume of phase change material disposed between, and coupled to, two electrodes, with the composition of a region of at least one of the two electrodes or phase change material having been compositionally altered to reduce the programmed volume of the phase change material.05-07-2009
20110108792Single Crystal Phase Change Material - A method for fabricating a phase change memory (PCM) cell includes forming a dielectric layer over an electrode, the electrode comprising an electrode material; forming a via hole in the dielectric layer such that the via hole extends down to the electrode; and growing a single crystal of a phase change material on the electrode in the via hole. A phase change memory (PCM) cell includes an electrode comprising an electrode material; a dielectric layer over the electrode; a via hole in the dielectric layer; and a single crystal of a phase change material located in the via hole, the single crystal contacting the electrode at the bottom of the via hole.05-12-2011
20100301302PHASE CHANGE MEMORY DEVICE HAVING BURIED CONDUCTION LINES DIRECTLY UNDERNEATH PHASE CHANGE MEMORY CELLS AND FABRICATION METHOD THEREOF - A phase change memory device having buried conduction lines directly underneath phase change memory cells is presented. The phase change memory device includes buried conduction lines buried in a semiconductor substrate and phase change memory cells arranged on top of the buried conductive lines. By having the buried conduction lines directly underneath the phase change memory cells, the resultant device can realize a considerable reduction in size.12-02-2010
20120068142RESISTANCE RANDOM ACCESS MEMORY ELEMENT AND METHOD FOR MAKING THE SAME - A resistance random access memory element includes a first electrode, an insulating layer, a diffusing metal layer, and a second electrode superimposed in sequence. The insulating layer includes a plurality of pointed electrodes. A method for making a resistance random access memory element includes growing and forming an insulating layer on a surface of a first electrode. A diffusing metal layer is formed on a surface of the insulating layer. A second electrode is mounted on a surface of the diffusing metal layer. A negative pole and a positive pole of a driving voltage are connected with the first and second electrodes, respectively. The diffusing metal in the diffusing metal layer is oxidized into metal ions by the driving voltage. The metal ions are driven into the insulating layer and form a plurality of pointed electrodes after reduction.03-22-2012
20110240946Graphene Memristor Having Modulated Graphene Interlayer Conduction - A graphene memristor includes a first electrode, a second electrode electrically coupled to the first electrode, an active region interspersed between the first and second electrodes, a defective graphene structure that modulates a barrier height to migration of ions through the active region, fast diffusing ions that migrate under the influence an electric field to change a state of the graphene memristor, and a source that generates the electric field.10-06-2011
20110001113PHASE CHANGE MEMORY STRUCTURES - A phase change memory cell has a first electrode, a plurality of pillars, and a second electrode. The plurality of pillars are electrically coupled with the first electrode. Each of the pillars comprises a phase change material portion and a heater material portion. The second electrode is electrically coupled to each of the pillars. In some examples, the pillars have a width less than 20 nanometers.01-06-2011
20110001112NONVOLATILE MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A nonvolatile memory device according to an embodiment of the present invention includes a first wire that extends in a first direction, a second wire that is formed at a height different from the first wire and extends in a second direction, and a nonvolatile memory cell that is arranged to be sandwiched between the first wire and the second wire at a position at which the first wire and the second wire intersect with each other. The nonvolatile memory cell includes a structure in which a nonvolatile storage element is sandwiched by semiconductor layers having different polarities.01-06-2011
20110001111THERMALLY INSULATED PHASE CHANGE MATERIAL CELLS - A memory cell structure and method for forming the same. The method includes forming a pore within a dielectric layer. The pore is formed over the center of an electrically conducting bottom electrode. The method includes depositing a thermally insulating layer along at least one sidewall of the pore. The thermally insulating layer isolates heat from phase change current to the volume of the pore. In one embodiment phase change material is deposited within the pore and the volume of the thermally insulating layer. In another embodiment a pore electrode is formed within the pore and the volume of the thermally insulating layer, with the phase change material being deposited above the pore electrode. The method also includes forming an electrically conducting top electrode above the phase change material.01-06-2011
20100133500Memory Cell Having a Side Electrode Contact - Memory cells are described along with methods for manufacturing. A memory cell as described herein includes a bottom electrode, a memory element and a side electrode. The bottom electrode contacts the memory element at a first contact surface on the bottom of the memory element. The side electrode contacts the memory element at a second contact surface on the side of the memory element, where the second contact surface on the side faces laterally relative to the first contact surface on the bottom.06-03-2010
20110240947Defective Graphene-Based Memristor - A graphene-based memristor includes a first electrode, a defective graphene layer adjacent the first electrode, a memristive material that includes a number of ions adjacent the defective graphene layer, a second electrode adjacent the memristive material, and a voltage source that generates an electric field between the first and the second electrodes. Under the influence of the electric field, ions in the memristive material form an ion conducting channel between the second electrode and the defective graphene layer.10-06-2011
20120132880Memristors with Asymmetric Electrodes - Embodiments of the present invention are directed to nanoscale memristor devices that provide nonvolatile memristive switching. In one embodiment, a memristor device (05-31-2012
20110031461PHASE CHANGE MEMORY DEVICE - A method of fabricating a phase change memory device includes forming an opening in a first layer, forming a phase change material in the opening and on the first layer, heating the phase change material to a first temperature that is sufficient to reflow the phase change material in the opening, wherein the first temperature is less than a melting point of the phase change material, and, after heating the phase change material to the first temperature, patterning the phase change material to define a phase change element in the opening.02-10-2011
20110031460Self-Aligned Memory Cells and Method for Forming - The invention provides a memory cell based on variable resistance material memory element that includes an access device having a pillar structure that may also include a protective sidewall layer. The pillar access device selects and isolates the memory cell from other memory array cells and is adapted to both self-align any memory element formed thereon, and to deliver suitable programming current to the memory element. The pillar structure is formed from one or more access device layers stacked above a wordline and below the memory element. Optional resistive layers may be selectively formed within the pillar structure to minimize resistance in the access device layer and the memory element. The pillar access device may be a diode, transistor, Ovonic threshold switch or other device capable of regulating current flow to an overlying programmable memory material.02-10-2011
20110017970SELF-ALIGN PLANERIZED BOTTOM ELECTRODE PHASE CHANGE MEMORY AND MANUFACTURING METHOD - A method is described for self-aligning a bottom electrode in a phase change random access memory PCRAM device where a top electrode serves as a mask for self-aligning etching of the bottom electrode. The bottom electrode has a top surface that is planarized by chemical mechanical polishing. The top electrode also has a top surface that is planarized by chemical mechanical polishing. A bottom electrode layer like TiN is formed over a substrate and prior to the formation of a via during subsequent process steps. A first dielectric layer is formed over the bottom electrode layer, and a second dielectric layer is formed over the first dielectric layer. A via is formed at a selected section that extends through the first and second dielectric layers.01-27-2011
20110079764INFORMATION RECORDING MEDIUM, MANUFACTURING METHOD THEREFOR, AND SPUTTERING TARGET - The information recording medium of the present invention includes a recording layer whose phase can be changed by application of electrical energy. The recording layer contains, as a main component, a material consisting of Ge, Te, and Sb. The material has a composition within a region defined by point (a) (35, 35, 30), point (b) (32.5, 27.5, 40), point (c) (25, 25, 50), and point (d) (27.5, 32.5, 40) and including lines from point (a) to point (b), from point (b) to point (c), from point (c) to point (d), and from point (d) to point (a), respectively, when coordinates (Ge, Te, Sb)=(x, y, z) are plotted on a triangular coordinate system shown in FIG. 04-07-2011
20100163826METHOD FOR ACTIVE PINCH OFF OF AN OVONIC UNIFIED MEMORY ELEMENT - A method of manufacturing a phase change memory (PCM) includes forming a pinch plate layer transversely to a PCM layer that is insulated from the pinch plate layer by a dielectric layer. Biasing the pinch plate layer causes a depletion region to form in the PCM layer. During a read of the PCM in a reset or partial reset state the depletion region increases the resistance of the PCM layer significantly.07-01-2010
20100032641NONVOLATILE SEMICONDUCTOR MEMORY APPARATUS AND MANUFACTURING METHOD THEREOF - A nonvolatile semiconductor memory apparatus (02-11-2010
20110210307CHEMICAL MECHANICAL POLISHING STOP LAYER FOR FULLY AMORPHOUS PHASE CHANGE MEMORY PORE CELL - A method for fabricating a phase change memory pore cell that includes forming a bottom electrode, forming a dielectric layer on the bottom electrode, and forming a sacrificial layer on the dielectric layer. The method further includes selectively etching portions of the sacrificial layer and the dielectric layer to define a pore extending through the sacrificial layer and the dielectric layer, depositing phase change material on the sacrificial layer and into the pore and removing the phase change material formed outside the pore, removing the sacrificial layer to expose the pore, the pore being vertically aligned, and forming a top electrode over the pore.09-01-2011
20110210306MEMORY CELL THAT INCLUDES A CARBON-BASED MEMORY ELEMENT AND METHODS OF FORMING THE SAME - A method of forming a reversible resistance-switching metal-carbon-metal (“MCM”) device is provided, the device including a first conducting layer, a second conducting layer, and a reversible resistance-switching element disposed between the first and second conducting layers, wherein the reversible resistance-switching element includes thermal CVD graphitic material and includes a highly resistive region that favors crack formation. Other aspects are also provided.09-01-2011
20100187492Multi-bit memory device having reristive material layers as storage node and methods of manufacturing and operating the same - Provided are a multi-bit memory device having resistive material layers as a storage node, and methods of manufacturing and operating the same. The memory device includes a substrate, a transistor formed on the substrate, and a storage node coupled to the transistor, wherein the storage node includes: a lower electrode connected to the substrate; a first phase change layer formed on the lower electrode; a first barrier layer overlying the first phase change layer; a second phase change layer overlying the first barrier layer; and an upper electrode formed on the second phase change layer.07-29-2010
20100038620INTEGRATION METHODS FOR CARBON FILMS IN TWO- AND THREE-DIMENSIONAL MEMORIES AND MEMORIES FORMED THEREFROM - Methods of forming memory cells are disclosed which include forming a pillar above a substrate, the pillar including a steering element and a memory element, and performing one or more etches vertically through the pillar to form multiple memory cells. Memory cells formed from such methods, as well as numerous other aspects are also disclosed.02-18-2010
20090218557Phase change memory device and fabrication method thereof - A phase change memory device is provided in which the area of contact between phase change material and heater electrode is reduced to suppress current required for heating and a phase change region is formed directly on a contact to raise the degree of integration. The device comprises a heater electrode in which the lower part thereof is surrounded by a side wall of a first insulating material and the upper part thereof protruding from the side wall has a sharp configuration covered by a second insulating material except for a part of the tip end thereof, and the exposed tip end is coupled to the phase change material layer.09-03-2009
20090218556INTEGRATED CIRCUIT FABRICATED USING AN OXIDIZED POLYSILICON MASK - An integrated circuit includes a first electrode, a second electrode, and dielectric material including an opening. The opening is defined by etching the dielectric material based on an oxidized polysilicon mask formed using a keyhole process. The integrated circuit includes resistivity changing material deposited in the opening and coupled between the first electrode and the second electrode.09-03-2009
20100038621Four-Terminal Reconfigurable Devices - Reconfigurable devices and methods for the fabrication thereof are provided. In one aspect, a reconfigurable device is provided. The reconfigurable device comprises a substrate; a first dielectric layer on the substrate; a conductive layer recessed into at least a portion of a side of the first dielectric layer opposite the substrate; at least one second dielectric layer over the side of the first dielectric layer opposite the substrate, so as to cover the conductive layer; a heater within the second dielectric layer; at least one programmable via extending through the second dielectric layer, extending through and surrounded by the heater and in contact with the conductive layer, the programmable via comprising at least one phase change material; a capping layer over the programmable via; a first conductive via and a second conductive via, each extending through the second dielectric layer and in contact with the heater; and a third conductive via extending through the second dielectric layer and in contact with the conductive layer.02-18-2010
20100059731PHASE CHANGE MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A phase change memory device and a corresponding method of manufacturing the same is presented. The phase change memory device includes a silicon substrate, a first insulation layer, cell switching elements, heaters, a gate, a second insulation layer, a barrier layer, a phase change layer and top electrodes. The first insulation layer is in the cell region of the substrate and has a first holes. The cell switching elements are formed in the first holes. The heaters are formed on the cell switching elements. The gate is in the peripheral region of the substrate and is higher than the cell switching elements. The second insulation layer having second holes which expose the heaters, and is defined to expose a hard mask layer of the gate. The barrier layer is on sidewalls of the second holes and on the second insulation layer. The phase change layer is formed in and over the second holes in which the barrier layer is formed. The top electrodes are formed on the phase change layer.03-11-2010
20110175049MEMORY COMPONENT AND MEMORY DEVICE - A memory component includes: a first electrode; a memory layer; and a second electrode in this order, wherein the memory layer includes a high resistance layer which includes tellurium (Te) as the chief component among anion components and is formed on the first electrode side; and an ion source layer which includes at least one kind of metal element and at least one kind of chalcogen element among tellurium (Te), sulfur (S) and selenium (Se) and is formed on the second electrode side.07-21-2011
20110073827NANODEVICE ARRAYS FOR ELECTRICAL ENERGY STORAGE, CAPTURE AND MANAGEMENT AND METHOD FOR THEIR FORMATION - An apparatus, system, and method are provided for a vertical two-terminal nanotube device configured to capture and generate energy, to store electrical energy, and to integrate these functions with power management circuitry. The vertical nanotube device can include a column disposed in an anodic oxide material extending from a first distal end of the anodic oxide material to a second distal end of the anodic oxide material. Further, the vertical nanotube device can include a first material disposed within the column, a second material disposed within the column, and a third material disposed between the first material and the second material. The first material fills the first distal end of the column and extends to the second distal end of the column along inner walls of the column. The second material fills the first distal end of the column and extends to the second distal end of the column within the first material. Both the first material and the second material are exposed at the first distal end of the column.03-31-2011
20110073826PHASE CHANGE MEMORY DEVICE AND FABRICATION METHOD THEREOF - A phase change memory device is provided that includes a switching device, a bottom electrode contact in contact with the switching device and a porous spacer formed on the bottom electrode contact.03-31-2011
20110037045NONVOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a nonvolatile memory device includes a substrate, a first electrode, a second electrode, and a memory. The first electrode is provided on the substrate. The second electrode crosses on the first electrode. The memory portion is provided between the first electrode and the second electrode. At least one of an area of a first memory portion surface of the memory portion opposed to the first electrode and an area of a second memory portion surface of the memory portion opposed to the second electrode is smaller than an area of a cross surface of the first electrode and the second electrode opposed to each other by the crossing.02-17-2011
20100276656Devices Comprising Carbon Nanotubes, And Methods Of Forming Devices Comprising Carbon Nanotubes - Some embodiments include devices that contain bundles of CNTs. An undulating topography extends over the CNTs and within spaces between the CNTs. A global maximum lateral width is defined as the greatest lateral width of any of the spaces. A material is directly over the CNTs, with the material being a plurality of particles that have minimum cross-sectional equatorial widths exceeding the global maximum lateral width. Some embodiments include methods in which a plurality of crossed carbon nanotubes are formed over a semiconductor substrate. The CNTs form an undulating upper topography extending across the CNTs and within spaces between the CNTs. A global maximum lateral width is defined as the greatest lateral width of any of the spaces. A material is deposited over the CNTs, with the material being deposited as particles that have minimum cross-sectional equatorial widths exceeding the global maximum lateral width.11-04-2010
20090212272SELF-CONVERGING BOTTOM ELECTRODE RING - A method and memory cell including self-converged bottom electrode ring. The method includes forming a step spacer, a top insulating layer, an intermediate insulating layer, and a bottom insulating layer above a substrate. The method includes forming a step spacer within the top insulating layer and the intermediate insulating layer. The step spacer size is easily controlled. The method also includes forming a passage in the bottom insulating layer with the step spacer as a mask. The method includes forming bottom electrode ring within the passage comprising a cup-shaped outer conductive layer within the passage and forming an inner insulating layer within the cup-shaped outer conductive layer. The method including forming a phase change layer above the bottom electrode ring and a top electrode above the bottom electrode ring.08-27-2009
20080237562PHASE CHANGE MEMORY DEVICES AND FABRICATION METHODS THEREOF - Phase change memory devices and fabrication methods thereof. A phase change memory device comprises a stacked heating element with a conductive portion and a relatively high resistive portion, wherein the relatively high resistive portion includes a nitrogen-containing metal silicide part. The heating stacked element such as a highly resistive nitrogen-containing metal silicide (MSi10-02-2008
20080203376Phase change memories with improved programming characteristics - A phase change memory may be made with improved speed and stable characteristics over extended cycling. The alloy may be selected by looking at alloys that become stuck in either the set or the reset state and finding a median or intermediate composition that achieves better cycling performance. Such alloys may also experience faster programming and may have set and reset programming speeds that are substantially similar.08-28-2008
20080203375Memory Cell with Memory Element Contacting Ring-Shaped Upper End of Bottom Electrode - A memory cell includes a bottom electrode, a top electrode and a memory element switchable between electrical property states by the application of energy. The bottom element includes lower and upper parts. The upper part has a generally ring-shaped upper end surrounding a non-conductive central region. The lateral dimension of the lower part is longer, for example twice as long, than the lateral dimension of the ring-shaped upper end. The lower part is a non-perforated structure. The memory element is positioned between and in electrical contact with the top electrode and the ring-shaped upper end of the second part of the bottom electrode. In some examples the ring-shaped upper end has a wall thickness at the memory element of 2-10 nm. A manufacturing method is also discussed.08-28-2008
20110163288Manufacturing Method for Pipe-Shaped Electrode Phase Change Memory - A method for manufacturing a memory cell device includes forming a bottom electrode comprising a pipe-shaped member, a top, a bottom and sidewalls having thickness in a dimension orthogonal to the axis of the pipe-shaped member, and having a ring-shaped top surface. A disc shaped member is formed on the bottom of the pipe-shaped member having a thickness in a dimension coaxial with the pipe-shaped member that is not dependent on the thickness of the sidewalls of the pipe-shaped member. A layer of phase change material is deposited in contact with the top surface of the pipe-shaped member. A top electrode in contact with the layer of programmable resistive material. An integrated circuit including an array of such memory cells is described.07-07-2011
20100320434Method of manufacturing a variable resistance structure and method of manufacturing a phase-change memory device using the same - In methods of manufacturing a variable resistance structure and a phase-change memory device, after forming a first insulation layer on a substrate having a contact region, a contact hole exposing the contact region is formed through the first insulation layer. After forming a first conductive layer on the first insulation layer to fill up the contact hole, a first protection layer pattern is formed on the first conductive layer. The first conductive layer is partially etched to form a contact and to form a pad on the contact. A second protection layer is formed on the first protection layer pattern, and then an opening exposing the pad is formed through the second protection layer and the first protection layer pattern. After formation of a first electrode, a phase-change material layer pattern and a second electrode are formed on the first electrode and the second protection layer.12-23-2010
20100283029Programmable resistance memory and method of making same - A memory includes multiple layers of deposited memory material. An etch is performed on at least one layer of deposited memory material prior to the deposition of a subsequent layer of memory material.11-11-2010
20110133149RESISTANCE CHANGE MEMORY AND MANUFACTURING METHOD THEREOF - According to one embodiment, a resistance change memory includes a first interconnect line extending in a first direction, a second interconnect line extending in a second direction intersecting with the first direction, and a cell unit which is provided between the first interconnect line and the second interconnect line and which includes a non-ohmic element and a memory element, the non-ohmic element including a conductive layer provided on at least one of first and second ends of the cell unit and a silicon portion provided between the first and second ends, the memory element being connected to the non-ohmic element via the conductive layer and storing data in accordance with a reversible change in a resistance state, wherein the non-ohmic element includes a first silicon germanium region in the silicon portion.06-09-2011
20100181549Phase-Changeable Random Access Memory Devices Including Barrier Layers and Metal Silicide Layers - A PRAM device may include an insulating interlayer, a diode, a metal silicide layer, a barrier spacer, an outer spacer, a lower electrode, a phase-changeable layer and an upper electrode. The insulating interlayer may be formed on a substrate. The insulating interlayer may have a contact hole. The diode may be formed in the contact hole. The metal silicide layer may be formed on the diode. The barrier spacer may be formed on an upper surface of the metal silicide layer and a side surface of the contact hole. The outer spacer may be formed on the barrier spacer. The lower electrode may be formed on the barrier spacer. The phase-changeable layer may be formed on the lower electrode. The upper electrode may be formed on the phase-changeable layer.07-22-2010
20100117046PHASE CHANGE MEMORY DEVICE HAVING REDUCED PROGRAMMING CURRENT AND METHOD FOR MANUFACTURING THE SAME - A phase change memory device includes a semiconductor substrate having an active region. An insulation layer is formed on the semiconductor substrate grooves and holes are defined in the insulation layer, with the holes being defined under the grooves to expose portions of the active region. Cell switching are elements formed in the holes and lower portions of the grooves and a phase change layer formed in upper portions of the grooves over the cell switching elements and on portions of the insulation layer adjacent to the grooves such that the phase change layer has a pore structure. Top electrodes are formed on the phase change layer.05-13-2010
20110095257MEMORY CELL THAT INCLUDES A CARBON-BASED REVERSIBLE RESISTANCE SWITCHING ELEMENT COMPATIBLE WITH A STEERING ELEMENT, AND METHODS OF FORMING THE SAME - Memory cells, and methods of forming such memory cells, are provided that include a steering element coupled to a carbon-based reversible resistivity switching material that has an increased resistivity, and a switching current that is less than a maximum current capability of the steering element used to control current flow through the carbon-based reversible resistivity switching material. In particular embodiments, methods and apparatus in accordance with this invention form a steering element, such as a diode, having a first width, coupled to a reversible resistivity switching material, such as aC, having a second width smaller than the first width.04-28-2011
20110260133SWITCHING ELEMENT AND MANUFACTURING METHOD THEREOF - A switching element includes: a first electrode supplying metal ions; a second electrode less ionizable than the first electrode; and an ion conducting layer arranged between the first electrode and the second electrode and containing a metal oxide that can conduct the metal ions. The ion conducting layer includes two or more layers of different types, and one of the ion conducting layers that is closest to the first electrode has a larger diffusion coefficient for the metal ions than that of the other ion conducting layer(s).10-27-2011
20100059732PHASE CHANGE MEMORY DEVICE HAVING HEAT SINKS FORMED UNDER HEATERS AND METHOD FOR MANUFACTURING THE SAME - A phase change memory device includes a silicon substrate having a cell region and a peripheral region. A first insulation layer is formed in the cell region and includes a plurality of holes. Cell switching elements are formed in the holes of the first insulation layer and heat sinks are formed on the cell switching elements. The heaters are formed on the center of the heat sinks and spacers are formed on the sidewalls. A gate is formed in the peripheral region of the silicon substrate formed of a gate insulation layer, a first conductive layer, a second conductive layer, and a hard mask layer. A second insulation layer covers the entire surface of the resultant silicon substrate and exposes the spacers and the heaters and the hard mask layer. Finally, a stack pattern of a phase change layer and a top electrode is formed on the heaters.03-11-2010
20110186800PORE PHASE CHANGE MATERIAL CELL FABRICATED FROM RECESSED PILLAR - A method of manufacturing an electrode is provided that includes providing a pillar of a first phase change material atop a conductive structure of a dielectric layer; or the inverted structure; forming an insulating material atop dielectric layer and adjacent the pillar, wherein an upper surface of the first insulating material is coplanar with an upper surface of the pillar; recessing the upper surface of the pillar below the upper surface of the insulating material to provide a recessed cavity; and forming a second phase change material atop the recessed cavity and the upper surface of the insulating material, wherein the second phase change material has a greater phase resistivity than the first phase change material.08-04-2011
20110186799NON-VOLATILE MEMORY CELL CONTAINING NANODOTS AND METHOD OF MAKING THEREOF - A non-volatile memory cell includes a first electrode, a steering element, a storage element located in series with the steering element, a plurality of discrete conductive nano-features separated from each other by an insulating matrix, where the plurality of discrete nano-features are located in direct contact with the storage element, and a second electrode. An alternative non-volatile memory cell includes a first electrode, a steering element, a storage element located in series with the steering element, a plurality of discrete insulating nano-features separated from each other by a conductive matrix, where the plurality of discrete insulating nano-features are located in direct contact with the storage element, and a second electrode.08-04-2011
20110147694RESISTIVE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A resistive memory device includes a plurality of resistive units, each resistive unit including: a lower electrode formed over a substrate; a resistive layer formed over the lower electrode; and an upper electrode formed over the resistive layer, wherein edge parts of the lower and upper electrodes, which come in contact with the resistive layer, is formed with a rounding shape.06-23-2011
20100044669INTEGRATED CIRCUIT INCLUDING MEMORY CELL HAVING CUP-SHAPED ELECTRODE INTERFACE - An integrated circuit includes a first electrode and a cup-shaped electrode interface coupled to the first electrode. The integrated circuit includes a dielectric spacer at least partially laterally enclosed by the electrode interface and a resistance changing material laterally enclosed by the spacer and contacting the electrode interface. The integrated circuit includes a second electrode coupled to the resistance changing material.02-25-2010
20090173929DATA MEMORY, WRITABLE AND READABLE BY MICROTIPS, WHICH HAS A WELL STRUCTURE, AND MANUFACTURING METHOD - The invention relates to data storage memories, that can be written and read by using at least one write or read microtip which comes near to a point zone to be written or to be read on the surface of a substrate, either in order to change the physical state of this zone, when writing or erasing, or in order to determine the physical state of the zone, when reading, the data stored in the zone being defined by the physical state of the zone. The surface of the substrate is subdivided into a set of individual islands (07-09-2009
20090173928POLYSILICON EMITTER BJT ACCESS DEVICE FOR PCRAM - A resistive non-volatile memory cell with a bipolar junction transistor (BJT) access device formed in conjunction with the entire memory cell. The memory cell includes a substrate acting as a collector, a semiconductor base layer acting as a base, and a semiconductor emitter layer acting as an emitter. Additionally, metal plugs and the phase change memory element are formed above the BJT access device while the emitter, metal plugs, and phase change memory element are contained within an insulating region. In one embodiment of the invention, a spacer layer is formed and the emitter layer is contained within the protective spacer layer. The spacer layer is contained within the insulating region.07-09-2009
20090026435Phase change random access meomory and semiconductor device - A phase change random access memory comprises an under electrode; an interlayer insulating layer which is formed on the under electrode; an impurity diffusion layer which is embedded into a pore through the interlayer insulating layer; a phase change recording layer which is formed on the interlayer insulating layer; an upper electrode which is formed on the phase change recording layer; a side gate electrode which is located on an inner wall of the pore into which the impurity diffusion layer is embedded; and a side gate insulating layer which is located between the side gate electrode and the impurity diffusion layer, wherein the side gate electrode applies an electric field to the impurity diffusion layer via the side gate insulating lay, the impurity diffusion layer is depleted, and so that an effective diameter of the impurity diffusion layer can become smaller than the pore diameter.01-29-2009
20110168966DEPOSITION OF AMORPHOUS PHASE CHANGE MATERIAL - A method for formation of a phase change memory (PCM) cell includes depositing amorphous phase change material in a via hole, the via hole comprising a bottom and a top, such that the amorphous phase change material is grown on an electrode located at the bottom of the via hole; melt-annealing the amorphous phase change material; and crystallizing the phase change material starting at the electrode at the bottom of the via hole and ending at the top of the via hole.07-14-2011
20110155989VARIABLE RESISTANCE MEMORY DEVICE AND METHODS OF FORMING THE SAME - A semiconductor memory device includes a first electrode and a second electrode, a variable resistance material pattern including a first element disposed between the first and second electrode, and a first spacer including the first element, the first spacer disposed adjacent to the variable resistance material pattern.06-30-2011
20110155990Continuous plane of thin-film materials for a two-terminal cross-point memory - A structure for a memory device including a plurality of substantially planar thin-film layers or a plurality of conformal thin-film layers is disclosed. The thin-film layers form a memory element that is electrically in series with first and second cladded conductors and operative to store data as a plurality of conductivity profiles. A select voltage applied across the first and second cladded conductors is operative to perform data operations on the memory device. The memory device may optionally include a non-ohmic device electrically in series with the memory element and the first and second cladded conductors. Fabrication of the memory device does not require the plurality of thin-film layers be etched in order to form the memory element. The memory element can include a CMO layer having a selectively crystallized polycrystalline portion and an amorphous portion. The cladded conductors can include a core material made from copper.06-30-2011
20120205607PHASE-CHANGE RANDOM ACCESS MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - A PRAM device includes a lower electrode, a phase-change nanowire and an upper electrode. The phase-change nanowire may be electrically connected to the lower electrode and includes a single element. The upper electrode may be electrically connected to the phase-change nanowires.08-16-2012
20120012805NONVOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a nonvolatile memory device includes a first interconnect, a nanomaterial aggregate layer, and a second interconnect. The nanomaterial aggregate layer is provided on the first interconnect. The nanomaterial aggregate layer includes an aggregation of a plurality of micro conductive bodies. The second interconnect is provided on the nanomaterial aggregate layer. At least a lower portion of the nanomaterial aggregate layer is disposed inside the second interconnect as viewed from above.01-19-2012
20110049461CHEMICAL MECHANICAL POLISHING STOP LAYER FOR FULLY AMORPHOUS PHASE CHANGE MEMORY PORE CELL - A method for fabricating a phase change memory pore cell that includes forming a bottom electrode, forming a first dielectric layer on the bottom electrode, forming a sacrificial layer on the first dielectric layer, forming an isolation layer on the sacrificial layer, and forming a second dielectric layer on the isolation layer. The method further includes forming a via overlying the bottom electrode, the via extending to the sacrificial layer, etching through the sacrificial layer to the first dielectric layer to form a pore defined extending through the sacrificial layer and the first dielectric layer, depositing phase change material on the sacrificial layer and into the pore and removing the phase change material formed outside the pore, removing the sacrificial layer to expose the pore, the pore being vertically aligned, and forming a top electrode over the pore.03-03-2011
20110049460SINGLE MASK ADDER PHASE CHANGE MEMORY ELEMENT - A method of fabricating a phase change memory element within a semiconductor structure includes etching an opening to an upper surface of a bottom electrode, the opening being formed of a height equal to a height of a metal region at a same layer within the semiconductor structure, depositing phase change material within the opening, recessing the phase change material within the opening, and forming a top electrode on the recessed phase change material.03-03-2011
20120025162PHASE CHANGE RANDOM ACCESS MEMORY AND METHOD FOR FABRICATING THE SAME - A method for fabricating a PCRAM includes forming a switching element on a semiconductor substrate, forming an interlayer dielectric layer of a multilayer-structure by sequentially stacking a plurality of material layers having different etching properties on the semiconductor substrate having the switching element formed thereon, and by patterning the plurality of material layers to have different lengths or different side shapes, forming a heating electrode on sidewalls of the interlayer dielectric layer and an upper surface of the switching element, and forming a phase change material layer to fill a space inside of the heating electrode.02-02-2012
20110057162IN VIA FORMED PHASE CHANGE MEMORY CELL WITH RECESSED PILLAR HEATER - A method for fabricating a phase change memory device including a plurality of in via phase change memory cells includes forming pillar heaters formed of a conductive material along a contact surface of a substrate corresponding to each of an array of conductive contacts to be connected to access circuitry, forming a dielectric layer along exposed areas of the substrate surrounding the pillar heaters, forming an interlevel dielectric (ILD) layer above the dielectric layer, etching a via to the dielectric layer, each via corresponding to each of pillar heater such that an upper surface of each pillar heater is exposed within each via, recessing each pillar heater, depositing phase change material in each via on each recessed pillar heater, recessing the phase change material within each via, and forming a top electrode within the via on the phase change material.03-10-2011
20100288994METHOD OF FORMING MEMORY CELL USING GAS CLUSTER ION BEAMS - A variable resistance memory cell structure and a method of forming it. The method includes forming a first electrode, forming an insulating material over the first electrode, forming a via in the insulating material to expose a surface of the first electrode, forming a heater material within the via using gas cluster ion beams, forming a variable resistance material within the via, and forming a second electrode such that the heater material and variable resistance material are provided between the first and second electrodes.11-18-2010
20100090190PHASE CHANGE MEMORY DEVICE HAVING DIELECTRIC LAYER FOR ISOLATING CONTACT STRUCTURE FORMED BY GROWTH, SEMICONDUCTOR DEVICE HAVING THE SAME, AND METHODS FOR MANUFACTURING THE DEVICES - A phase change memory device includes a semiconductor substrate having an impurity region and an interlayer dielectric applying a tensile stress formed on the semiconductor substrate and having contact holes exposing the impurity region. Switching elements are formed in the contact holes; and sidewall spacers interposed between the switching elements and the interlayer dielectric and formed as a dielectric layer applying a compressive stress.04-15-2010
20100207092PHASE CHANGE MEMORY DEVICE SWITCHED BY SCHOTTKY DIODES AND METHOD FOR MANUFACTURING THE SAME - A phase change memory device and a method for manufacturing the same is presented. The phase change memory device includes a semiconductor substrate, a bit line, switching elements, bottom electrodes, a phase change layer, and top electrodes. The semiconductor substrate has a cell area and a peripheral area. The bit line is formed on the semiconductor substrate. The switching elements are formed on portions of the bit line in the cell area. The bottom electrodes are formed on the switching elements. The phase change layer is formed on the bottom electrodes. The top electrodes are formed on the phase change layer.08-19-2010
20090057640PHASE-CHANGE MEMORY ELEMENT - A phase-change memory element and fabrication method thereof is provided. The phase-change memory element comprises an electrode. A first dielectric layer is formed on the substrate. An opening passes through the first dielectric layer exposing the electrode. A heater with an extended part is formed in the opening, wherein the extended part protrudes the opening. A second dielectric layer surrounds the extended part of the heater exposing the top surface of the extended part. A phase-changed material layer is formed on the second dielectric layer to directly contact the top of the extended part.03-05-2009
20110095258MEMORY CELL THAT INCLUDES A CARBON-BASED REVERSIBLE RESISTANCE SWITCHING ELEMENT COMPATIBLE WITH A STEERING ELEMENT, AND METHODS OF FORMING THE SAME - Memory cells, and methods of forming such memory cells, are provided that include a steering element coupled to a carbon-based reversible resistivity switching material that has an increased resistivity, and a switching current that is less than a maximum current capability of the steering element used to control current flow through the carbon-based reversible resistivity switching material. In particular embodiments, methods and apparatus in accordance with this invention form a steering element, such as a diode, having a first cross-sectional area, coupled to a reversible resistivity switching material, such as aC, having a region that has a second cross-sectional area smaller than the first cross-sectional area.04-28-2011
20120074371RESISTANCE VARIABLE MEMORY DEVICE WITH NANOPARTICLE ELECTRODE AND METHOD OF FABRICATION - A chalcogenide-based programmable conductor memory device and method of forming the device, wherein a nanoparticle is provided between an electrode and a chalcogenide glass region. The method of forming the nanoparticle utilizes a template over the electrode or random deposition of the nanoparticle.03-29-2012
20120256154Semiconductor Phase Change Memory Using Multiple Phase Change Layers - In accordance with some embodiments, a phase change memory may be formed in which the thermal conductivity in the region outside the programmed volume of phase change material is reduced. This may reduce the power consumption of the resulting phase change memory. The reduction in power consumption may be achieved by forming distinct layers of phase change material that have little or no mixing between them outside the programmed volume. For example, in one embodiment, a diffusion barrier layer may be maintained between the two distinct phase change layers. In another embodiment, a face centered cubic chalcogenide structure may be utilized.10-11-2012
20090020741PHASE CHANGE MEMORY DEVICE WITH REINFORCED ADHESION FORCE - A phase change memory device includes a semiconductor substrate having a plurality of phase change cell regions. A bottom electrode is formed in each phase change cell region of the semiconductor substrate. An insulation layer is formed on the semiconductor substrate to cover the bottom electrode, and the insulation layer includes a contact hole exposing the bottom electrode. A contact plug is formed within the contact hole. A stacked pattern comprising a phase change layer and a top electrode is formed over the insulation layer. In the phase change memory device a buffer layer is interposed between the insulation layer and the phase change layer to reinforce the adhesion force between them. The buffer layer prevents the phase change material from peeling off due to an inconstant adhesion force between the phase change material and the insulation layer.01-22-2009
20100327252PHASE CHANGE MEMORY APPARATUS AND FABRICATION METHOD THEREOF - A phase change memory apparatus is provided that includes a first electrode of a bar type having a trench formed on an active region of a semiconductor substrate, a second electrode formed in a bottom portion of the trench, and a bottom electrode contact formed on the second electrode.12-30-2010
20120280199NONVOLATILE MEMORY ELEMENT, METHOD OF MANUFACTURING THE SAME, AND NONVOLATILE MEMORY DEVICE - Provided is a nonvolatile memory element achieving a stable resistance change and miniaturization, and a method of manufacturing the same. The nonvolatile memory element includes: a first electrode formed above a substrate; an interlayer insulating layer formed above the substrate including the first electrode and having a memory cell hole reaching the first electrode; a barrier layer formed in the memory cell hole and composed of a semiconductor layer or an insulating layer connected to the first electrode; a second electrode formed in the memory cell hole and connected to the barrier layer; a variable resistance layer formed on the second electrode and having a stacked structure whose resistance value changes based on electric signals; and a third electrode connected to the variable resistance layer and formed on the interlayer insulating layer to cover the memory cell hole.11-08-2012
20120286226Nonvolatile Memory Devices And Methods Of Fabricating The Same - Nonvolatile memory devices including a first interlayer insulating film and a second interlayer insulating film separated from each other and are stacked sequentially, a first electrode penetrating the first interlayer insulating film and the second interlayer insulating film, a resistance change film along a top surface of the first interlayer insulating film, side surfaces of the first electrode, and a bottom surface of the second interlayer insulating film, and a second electrode between the first interlayer insulating film and the second interlayer insulating film.11-15-2012
20130009123VARIABLE RESISTANCE ELEMENT, SEMICONDUCTOR DEVICE INCLUDING VARIABLE RESISTANCE ELEMENT, AND METHODS FOR MANUFACTURING VARIABLE RESISTANCE ELEMENT AND SEMICONDUCTOR DEVICE - A variable resistance element includes a first electrode, a second electrode and an ion conduction layer interposed between the first and second electrodes. The ion conduction layer contains an organic oxide containing at least oxygen and carbon. The carbon concentration distribution in the ion conduction layer is such that the carbon concentration in an area closer to the first electrode is greater than that in an area closer to the second electrode.01-10-2013
20130020548SEED LAYER FOR A P+ SILICON GERMANIUM MATERIAL FOR A NON-VOLATILE MEMORY DEVICE AND METHOD - A method of forming a non-volatile memory device includes providing a substrate having a surface, depositing a dielectric overlying the surface, forming a first wiring structure overlying the dielectric, depositing silicon material overlying the first wiring structure, the silicon layer having a thickness of less than about 100 Angstroms, depositing silicon germanium material at a temperature raging from about 400 to about 490 Degrees Celsius overlying the first wiring structure using the silicon layer as a seed layer, wherein the silicon germanium material is substantially free of voids and has polycrystalline characteristics, depositing resistive switching material (e.g. amorphous silicon material) overlying the silicon germanium material, depositing a conductive material overlying the resistive material, and forming a second wiring structure overlying the conductive material.01-24-2013
20130140511RESISTIVE-SWITCHING MEMORY ELEMENT - A resistive-switching memory element is described. The memory element includes a first electrode, a porous layer over the first electrode including a point defect embedded in a plurality of pores of the porous layer, and a second electrode over the porous layer, wherein the nonvolatile memory element is configured to switch between a high resistive state and a low resistive state.06-06-2013
20080224116Forming an intermediate electrode between an ovonic threshold switch and a chalcogenide memory element - An intermediate electrode between an ovonic threshold switch and a memory element may be formed in the same pore with the memory element. This may have many advantages including, in some embodiments, reducing leakage.09-18-2008
20130168629NANOSCALE SWITCHING DEVICE - A nanoscale switching device comprises a first electrode of a nanoscale width; a second electrode of a nanoscale width; an active region disposed between the first and second electrodes, the active region containing a switching material; an area within the active region that constrains current flow between the first electrode and the second electrode to a central portion of the active region; and an interlayer dielectric layer formed of a dielectric material and disposed between the first and second electrodes outside the active region. A nanoscale crossbar array and method of forming the nanoscale switching device are also disclosed.07-04-2013
20130175493PHASE CHANGE MEMORY STRUCTURE HAVING LOW-K DIELECTRIC HEAT-INSULATING MATERIAL AND FABRICATION METHOD THEREOF - The present invention discloses a phase change memory structure having low-k dielectric heat-insulating material and fabrication method thereof, wherein the phase change memory cell comprises diode, heating electrode, reversible phase change resistor, top electrode and etc; the heating electrode and reversible phase change resistor are surrounded by low-k dielectric heat-insulating layer; an anti-diffusion dielectric layer is designed between the reversible phase change resistor and the low-k dielectric heat-insulating layer surrounding thereof. The present invention utilizes low-k dielectric material as heat-insulating material, thereby avoiding thermal crosstalk and mutual influence during operation between phase change memory cells, enhancing the reliability of devices, and eliminating the influence of temperature, pressure and etc. on phase change random access memory (PCRAM) data retention during the change from amorphous to polycrystalline states. Furthermore, an anti-diffusion dielectric layer is prepared between the low-k dielectric material and the phase change material, which can be used to prevent the elements of the phase change material from diffusing to low-k dielectric material. The fabrication process of said phase change memory is compatible with standard complementary metal-oxide semiconductor (CMOS) process and the chemical mechanical polishing (CMP) process with low pressure and light corrosion is adopted in polishing.07-11-2013
20130112933GERMANIUM ANTIMONY TELLURIDE MATERIALS AND DEVICES INCORPORATING SAME - A chalcogenide alloy composition, having an atomic composition comprising from 34 to 45 Ge, from 2 to 16% Sb, from 48 to 55% Te, from 3 to 15% carbon and from 1 to 10% nitrogen, wherein all atomic percentages of all components of the film total to 100 atomic %. Material of such composition is useful to form phase change films, e.g., as conformally coated on a phase change memory device substrate to fabricate a phase change random access memory cell.05-09-2013
20120273745METHOD OF MANUFACTURING A PHASE CHANGE SEMICONDUCTOR DEVICE AND THE PHASE CHANGE SEMICONDUCTOR DEVICE - This disclosure is directed to a phase change semiconductor device and a manufacturing method thereof, comprising: forming an insulating layer on a substrate and a metal layer on the insulating layer; forming a via hole penetrating from the metal layer to the insulating layer; forming a phase change material layer on the metal layer and the via hole to at least fill up the via hole; and performing a planarization process, wherein after forming the metal layer and before forming the via hole, or after forming the via hole and before forming the phase change material layer, or after forming the phase change material layer and before the planarization process, subjecting the metal layer to an annealing treatment to form a metallic compound layer at an interface between the metal layer and the insulating layer. Adhesion between the phase change material layer and the insulating layer can be improved.11-01-2012
20110233505NONVOLATILE MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - According to the nonvolatile memory device in one embodiment, contact plugs connect between second wires and third wires in a memory layer and a first wire connected to a control element. Drawn wire portions connect the second wires and the third wires with the contact plug. The drawn wire portion connected to the second wires and the third wires of the memory layer is formed of a wire with a critical dimension same as the second wires and the third wires and is in contact with the contact plug on an upper surface and both side surfaces of the drawn wire portion.09-29-2011
20130126816Memory Arrays and Methods of Forming Memory Cells - Some embodiments include methods of forming memory cells. A series of rails is formed to include bottom electrode contact material. Sacrificial material is patterned into a series of lines that cross the series of rails. A pattern of the series of lines is transferred into the bottom electrode contact material. At least a portion of the sacrificial material is subsequently replaced with top electrode material. Some embodiments include memory arrays that contain a second series of electrically conductive lines crossing a first series of electrically conductive lines. Memory cells are at locations where the electrically conductive lines of the second series overlap the electrically conductive lines of the first series. First and second memory cell materials are within the memory cell locations. The first memory cell material is configured as planar sheets and the second memory cell material is configured as upwardly-opening containers.05-23-2013
20130153850NONVOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a nonvolatile memory device includes a first electrode, a second electrode, and a memory cell provided between the first electrode and the second electrode. The memory cell includes a retention unit, a resistance change unit, and an ion supply unit. The retention unit is provided on the first electrode and has an electron trap. The resistance change unit is provided on the retention unit. The ion supply unit is provided between the resistance change unit and the second electrode and includes a metal element.06-20-2013
20130187115PROGRAMMABLE METALLIZATION MEMORY CELLS VIA SELECTIVE CHANNEL FORMING - Programmable metallization memory cells include an electrochemically active electrode, an inert electrode and an internal layer between the electrochemically active electrode and the inert electrode. The internal layer having a fast ion conductor material and an apertured layer having a plurality of apertures defined by an electrically insulating material. Each aperture defines at least a portion of a column of fast ion conductor material having superionic clusters.07-25-2013
20130187114Non-Volatile Memory Cell Containing a Nano-Rail Electrode - A non-volatile memory device includes a plurality of non-volatile memory cells. Each of the non-volatile memory cells includes a first electrode, a diode steering element, a storage element located in series with the diode steering element, a second electrode, and a nano-rail electrode having a width of 15 nm or less.07-25-2013
20120018694REPRODUCIBLE RESISTANCE VARIABLE INSULATING MEMORY DEVICES AND METHODS FOR FORMING SAME - The present invention relates to the use of a shaped bottom electrode in a resistance variable memory device. The shaped bottom electrode ensures that the thickness of the insulating material at the tip of the bottom electrode is thinnest, creating the largest electric field at the tip of the bottom electrode. The arrangement of electrodes and the structure of the memory element makes it possible to create conduction paths with stable, consistent and reproducible switching and memory properties in the memory device.01-26-2012
20120037877ONE-MASK PHASE CHANGE MEMORY PROCESS INTEGRATION - An example embodiment disclosed is a method for fabricating a phase change memory cell. The method includes forming a non-sublithographic via within an insulating substrate. The insulating substrate is embedded on the same layer as a first metalization layer (Metal 02-16-2012

Patent applications in class With means to localize region of conduction (e.g., "pore" structure)