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Bulk effect switching in amorphous material

Subclass of:

257 - Active solid-state devices (e.g., transistors, solid-state diodes)

257001000 - BULK EFFECT DEVICE

Patent class list (only not empty are listed)

Deeper subclasses:

Class / Patent application numberDescriptionNumber of patent applications / Date published
257004000 With specified electrode composition or configuration 640
257005000 In array 185
257003000 With means to localize region of conduction (e.g., "pore" structure) 177
Entries
DocumentTitleDate
20090230376RESISTIVE MEMORY DEVICES - Provided is a resistive memory device that can be integrated with a high integration density and method of forming the same. In an embodiment, a bit line is formed of copper using a damascene technique, and when the copper bit line, a copper stud may be formed around the copper bit line09-17-2009
20130043451Nonvolatile Memory Elements And Memory Devices Including The Same - Nonvolatile memory elements and memory devices including the nonvolatile memory elements. A nonvolatile memory element may include a memory layer between two electrodes, and the memory layer may have a multi-layer structure. The memory layer may include a base layer and an ionic species exchange layer and may have a resistance change characteristic due to movement of ionic species between the base layer and the ionic species exchange layer. The ionic species exchange layer may have a multi-layer structure including at least two layers. The nonvolatile memory element may have a multi-bit memory characteristic due to the ionic species exchange layer having the multi-layer structure. The base layer may be an oxygen supplying layer, and the ionic species exchange layer may be an oxygen exchange layer.02-21-2013
20100090188SEMICONDUCTOR DEVICE - A semiconductor device is comprised of a semiconductor substrate, conductive layers stacked above the semiconductor substrate, which is comprised of a conductive polysilicon, and a metal layer provided above the conductive layers. Both ends of the conductive layers have stairsteps respectively. The conductive layers are connected in series by a metal layer which is provided on the stairsteps. The conductive layers connected in series comprise a resistance element.04-15-2010
20110204310ELECTRONIC DEVICE INCORPORATING MEMRISTOR MADE FROM METALLIC NANOWIRE - An electronic device includes a first electrode, a second electrode and a nanowire connected between the first and second electrodes to allow electric current flow. The nanowire is made from a conductive material exhibiting a variable resistance due to electromigration. The nanowire is repeatably switchable between two states. A voltage clamp operates through feedback control to maintain the voltage across the nanowire and prevent thermal runaway.08-25-2011
20090194755HIGH DENSITY CHALCOGENIDE MEMORY CELLS - A non-volatile memory cell is constructed from a chalcogenide alloy structure and an associated electrode side wall. The electrode is manufactured with a predetermined thickness and juxtaposed against a side wall of the chalcogenide alloy structure, wherein at least one of the side walls is substantially perpendicular to a planar surface of the substrate. The thickness of the electrode is used to control the size of the active region created within the chalcogenide alloy structure. Additional memory cells can be created along rows and columns to form a memory matrix. The individual memory cells are accessed through address lines and address circuitry created during the formation of the memory cells. A computer can thus read and write data to particular non-volatile memory cells within the memory matrix.08-06-2009
20130134374VARIABLE RESISTOR, NON-VOLATILE MEMORY DEVICE USING THE SAME, AND METHODS OF FABRICATING THE SAME - A variable resistor, a nonvolatile memory device and methods of fabricating the same are provided. The variable resistor includes an anode electrode and a cathode electrode, a variable resistive layer including CdS nanoscale particles provided between the anode electrode and the cathode electrode, and an initial metal atom diffusion layer within the variable resistive layer. The variable resistor is a bipolar switching element and configured to be in a reset state when a positive voltage relative to a cathode electrode is applied to the anode electrode, and configured to be in a set state when a negative voltage relative to the cathode electrode is applied to the anode electrode.05-30-2013
20130075684NON-VOLATILE MEMORY DEVICE - A non-volatile memory device includes: a first line extending along a main surface of a substrate; a stack provided above the first line; a second line formed above the stack; a select element provided where the first and second lines intersect, the select element adapted to pass current in a direction perpendicular to the main surface; a second insulator film provided along a side surface of the stack; a channel layer provided along the second insulator film; an adhesion layer provided along the channel layer; and a variable resistance material layer provided along the adhesion layer, wherein the first and second lines are electrically connected via the select element and channel layer, a contact resistance via the adhesion layer between the channel layer and variable resistance material layer is low, and a resistance of the adhesion layer is high with respect to an extending direction of the channel layer.03-28-2013
20130075683INTEGRATED NONVOLATILE RESISTIVE MEMORY ELEMENTS - A resistive memory apparatus provides resistive memory material between conductive traces on a substrate or in a film stack on a substrate. The resistive memory apparatus may provide a sealed cavity or may utilize material obviating the need for the cavity. Methods and materials utilized to form the resistive memory apparatus are compatible with current microelectronic fabrication techniques. The resistive memory apparatus is nonvolatile or requires no power to maintain a programmed state. The resistive memory device may also be directly integrated with other microelectronic components.03-28-2013
20130075682PHASE CHANGE RANDOM ACCESS MEMORY AND METHOD FOR MANUFACTURING THE SAME - A phase change random access memory includes a semiconductor substrate having a bottom electrode formed over the semiconductor substrate; and a phase change layer formed over the bottom electrode. The phase change layer a first phase change layer formed over the bottom electrode and including at least one of a first element, a second element, and a third element; and a second phase change layer formed over a surface of the first phase change layer and formed of the first element to prevent an area of the first phase change layer from increasing through diffusion.03-28-2013
20110193047PHASE CHANGE MEMORY - A method of fabricating a phase change memory includes forming a lower electrode on a semiconductor substrate, forming a phase change pattern, an upper electrode, and a hard mask pattern sequentially on the lower electrode, a width of a bottom surface of the hard mask pattern being greater than a width of a top surface of the hard mask pattern, the bottom surface of the hard mask pattern facing the upper electrode and being opposite the top surface of the hard mask pattern, and forming a capping layer to cover the top surface of the hard mask pattern and sidewalls of the hard mask pattern, phase change pattern, and upper electrode.08-11-2011
20110193046PHASE CHANGE MEMORY DEVICE, MANUFACTURING METHOD THEREOF AND OPERATING METHOD THEREOF - A phase change memory (PCM) device, a manufacturing technique of making the PCM device, and a way of operating the PCM device is presented. The PCM device is structured to have a silicon on insulator type substrate that provides an advantage of thermally insulating the active area of the PCM device without the need for an additional insulation layer. The PCM device has a phase change resistor PCR that has one terminal connected to a word line and the other terminal connected in common to the N-terminals of two PN diodes in which the P-terminals are connected in common to the bit line. As a result, a current flowing through the phase change resistor PCR is doubled which results in doubling the cell driving capacity.08-11-2011
20110193045POST DEPOSITION METHOD FOR REGROWTH OF CRYSTALLINE PHASE CHANGE MATERIAL - Techniques for forming a phase change memory cell. An example method includes forming a bottom electrode within a substrate. The method includes forming a phase change layer above the bottom electrode. The method includes forming a capping layer and an insulator layer. The method includes crystallizing the phase change material in the phase change layer so that the phase change layer is void free. The method further comprises heating the phase change material in the phase change layer from the bottom electrode and as a result the phase change layer is crystallized from the bottom to the top. In one embodiment, a rapid thermal anneal (RTA) is applied for crystallizing the phase change material.08-11-2011
20110193044RESISTIVE MEMORY AND METHODS OF PROCESSING RESISTIVE MEMORY - Resistive memory and methods of processing resistive memory are described herein. One or more method embodiments of processing resistive memory include conformally forming a cell material in an opening in an interlayer dielectric such that a seam is formed in the cell material, forming a conductive pathway by modifying the seam, and forming an electrode on the cell material and the seam.08-11-2011
20130037775NONVOLATILE MEMORY ELEMENT, MANUFACTURING METHOD THEREOF, AND NONVOLATILE SEMICONDUCTOR DEVICE INCORPORATING NONVOLATILE MEMORY ELEMENT - A nonvolatile memory element of the present invention comprises a first electrode (02-14-2013
20130037773IONIC DEVICES WITH INTERACTING SPECIES - An ionic device includes a layer (02-14-2013
20130037772Memory Cells - Some embodiments include memory cells. A memory cell may contain a switching region and an ion source region between a pair of electrodes. The switching region may be configured to reversibly retain a conductive bridge, with the memory cell being in a low resistive state when the conductive bridge is retained within the switching region and being in a high resistive state when the conductive bridge is not within the switching region. The memory cell may contain an ordered framework extending across the switching region to orient the conductive bridge within the switching region, with the framework remaining within the switching region in both the high resistive and low resistive states of the memory cell.02-14-2013
20130037774SEMICONDUCTOR DEVICE - A semiconductor device includes a first horizontal molding pattern, a horizontal electrode pattern disposed on the first horizontal molding pattern, and a second horizontal molding pattern disposed on the horizontal electrode pattern. A vertical structure extends through the horizontal patterns. The vertical structure includes a vertical electrode pattern, a data storage pattern interposed between the vertical electrode pattern and the horizontal patterns, a first buffer pattern interposed between the data storage pattern and the first molding pattern, and a second buffer pattern interposed between the data storage pattern and the second molding pattern and spaced apart from the first buffer pattern.02-14-2013
20100163823RESISTIVE RANDOM ACCESS MEMORY - A resistive memory device includes a first electrode, a resistive oxidation structure and a second electrode. The resistive oxidation structure has sets of oxidation layers stacked on the first electrode. Each set is made up of a first metal oxide layer and a second metal oxide layer which is disposed on and is thinner than the first metal oxide layer. The first metal oxidation layer of the first one of the sets of oxidation layers contacts an upper surface of the first electrode. The second electrode is formed on the resistive oxidation structure. The resistance of the oxidation structure can be changed by an electric field07-01-2010
20100117045Memory Array with a Selector Connected to Multiple Resistive Cells - An array includes a transistor comprising a first terminal, a second terminal and a third terminal; a first contact plug connected to the first terminal of the transistor; a second contact plug connected to the first terminal of the transistor; a first resistive memory cell having a first end and a second end, wherein the first end is connected to the first contact plug; and a second resistive memory cell having a third end and a fourth end, wherein the third end is connected to the second contact plug.05-13-2010
20100117044PHASE CHANGE MEMORY DEVICE CAPABLE OF SATISFYING RESET CURRENT CHARACTERISTIC AND CONTACT RESISTANCE CHARACTERISTIC - A phase change memory device is presented that has a lower electrode contact that has a gradient resistance profile ranging from a lower resistive lower end to a higher resistive upper end. The phase change memory device includes a semiconductor substrate, a lower electrode contact, and a phase change pattern. The semiconductor substrate has a switching device. The lower electrode contact is formed on the switching device and has a specific resistance which gradually increases from a lower part to an upper part of the lower electrode contact. The phase change pattern layer is formed on the lower electrode contact.05-13-2010
20100117042 HIGH LEVEL INTEGRATION PHASE CHANGE MEMORY DEVICE HAVING AN INCREASED DIODE JUNCTION AREA AND METHOD FOR MANUFACTURING THE SAME - A phase change memory device includes a semiconductor substrate active region, a plurality of first conductivity type silicon pillars, and a plurality of second conductivity type silicon patterns. The plurality of first conductivity type silicon pillars is formed on the semiconductor active region such that each first conductivity type silicon pillar is provided for two adjoining cells. The plurality of second conductivity type silicon patterns is formed on the plurality of first conductivity type silicon pillars such that two second conductivity type silicon patterns are formed on opposite sidewalls of each first conductivity type silicon pillars. Two adjoining cells together share only one first conductivity type silicon pillar and each adjoining cell is connected to only one second conductivity type silicon pattern which constitutes a PN diode which serves as a single switching element for each corresponding cell.05-13-2010
20100117043PHASE CHANGE MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A phase change memory device includes a semiconductor substrate having a first conductivity type well An isolation structure is formed in the semiconductor substrate having the first conductivity type well to define active regions. Second conductivity type high concentration areas are formed in surfaces of the active regions. Insulation patterns are formed under the second conductivity type high concentration areas to insulate the second conductivity type high concentration areas from the first conductivity type well. A plurality of vertical diodes are formed on the second conductivity type high concentration areas which are insulated from the first conductivity type well.05-13-2010
20100117040Optical Ovonic Threshold Switch - A method and device for accomplishing transformation of a switching material from a resistive state to a conductive state. The method utilizes a non-electrical source of energy to effect the switching transformation. The switching material may be a chalcogenide switching material, where the non-electrical source of energy initiates switching by liberating lone pair electrons from bound states of chalcogen atoms. The liberated lone pair electrons form a conductive filament having the characteristics of a solid state plasma to permit high current densities to pass through the switching material. The device includes a switching material with electrical contacts and may be interconnected with other elements in a circuit to regulate electrical communication therebetween.05-13-2010
20100072445MEMORY CELL THAT INCLUDES A CARBON NANO-TUBE REVERSIBLE RESISTANCE-SWITCHING ELEMENT AND METHODS OF FORMING THE SAME - Methods of forming planar carbon nanotube (“CNT”) resistivity-switching materials for use in memory cells are provided, that include depositing first dielectric material, patterning the first dielectric material, etching the first dielectric material to form a feature within the first dielectric material, depositing CNT resistivity-switching material over the first dielectric material to fill the feature at least partially with the CNT resistivity-switching material, depositing second dielectric material over the CNT resistivity-switching material, and planarizing the second dielectric material and the CNT resistivity-switching material so as to expose at least a portion of the CNT resistivity-switching material within the feature. Other aspects are also provided.03-25-2010
20100044668HYBRID MRAR ARRAY STRUCTURE AND OPERATION - This invention relates to MRAM technology and new variations on MRAM array architecture to incorporate certain advantages from both cross-point and 1T-1MTJ architectures. The fast read-time and higher signal-to-noise ratio of the 1T-1MTJ architecture and the higher packing density of the cross-point architecture are both exploited by combining certain characteristics of these layouts. A single access transistor 02-25-2010
20100044667SEMICONDUCTOR DEVICES HAVING A PLANARIZED INSULATING LAYER - A semiconductor device includes at least one phase-change pattern disposed on a semiconductor substrate. A planarized capping layer, a planarized protecting layer, and a planarized insulating layer are sequentially stacked to surround sidewalls of the at least one phase-change pattern. An interconnection layer pattern is disposed on the planarized capping layer, the planarized protecting layer, and the planarized insulating layer. The interconnection layer pattern is in contact with the phase-change pattern.02-25-2010
20100044666RESISTIVE MEMORY CELLS AND DEVICES HAVING ASYMMETRICAL CONTACTS - A memory cell includes a plug-type first electrode in a substrate, a magneto-resistive memory element disposed on the first electrode, and a second electrode disposed on the magneto-resistive memory element opposite the first electrode. The second electrode has an area of overlap with the magneto-resistive memory element that is greater than an area of overlap of the first electrode and the magneto-resistive memory element. The first surface may, for example, be substantially circular and have a diameter less than a minimum planar dimension (e.g., width) of the second surface. The magneto-resistive memory element may include a colossal magneto-resistive material, such as an insulating material with a perovskite phase and/or a transition metal oxide.02-25-2010
20100044664MEMORY DEVICES AND METHODS OF FORMING THE SAME - Memory devices having a plurality of memory cells, with each memory cell including a phase change material having a laterally constricted portion thereof. The laterally constricted portions of adjacent memory cells are vertically offset and positioned on opposite sides of the memory device. Also disclosed are memory devices having a plurality of memory cells, with each memory cell including first and second electrodes having different widths. Adjacent memory cells have the first and second electrodes offset on vertically opposing sides of the memory device Methods of forming the memory devices are also disclosed.02-25-2010
20100102289NONVOLATILE RESISTIVE MEMORY DEVICES - Nonvolatile resistive memory devices are disclosed. In some embodiments, the memory devices comprise multilayer structures including electrodes, one or more resistive storage layers, and separation layers. The separation layers insulate the resistive storage layers to prevent charge leakage from the storage layers and allow for the use of thin resistive storage layers. In some embodiments, the nonvolatile resistive memory device includes a metallic multilayer comprising two metallic layers about an interlayer. A dopant at an interface of the interlayer and metallic layers can provide a switchable electric field within the multilayer.04-29-2010
20090159866Integrated Circuits With Phase Change Devices - Embodiments include methods, apparatus, and systems with integrated circuits having phase change devices. One embodiment includes an integrated circuit die and a phase change die having a phase change material that changes phases when a temperature at the integrated circuit die exceeds a threshold for a predetermined amount of time.06-25-2009
20100108972NON-VOLATILE SEMICONDUCTOR MEMORY DEVICES - A non-volatile semiconductor memory device includes a lower electrode, an upper electrode, a resistive layer pattern between the lower electrode and the upper electrode, and a filament seed embedded in the resistive layer pattern. The filament seed includes at least one of a carbon nanotube, a nanowire and a nanoparticle.05-06-2010
20100108971Methods of Forming Integrated Circuit Devices Having Vertical Semiconductor Interconnects and Diodes Therein and Devices Formed Thereby - Methods of forming integrated circuit devices include forming an etch stop layer on a surface of a semiconductor substrate and forming a first interlayer insulating layer on the etch stop layer. The first interlayer insulating layer is patterned to define an opening therein that exposes a first portion of the etch stop layer. This first portion of the etch stop layer is then removed to thereby expose an underlying portion of the surface of the semiconductor substrate. This removal of the etch stop layer may be performed by wet etching the first portion of the etch stop layer using a phosphoric acid solution. A semiconductor region is then selectively grown into the opening, using the exposed portion of the surface of the semiconductor substrate as an epitaxial seed layer.05-06-2010
20100108973IMAGE SENSOR AND METHOD FOR MANUFACTURING THE SAME - An image sensor according to embodiments may include a semiconductor substrate, photodiodes disposed over the semiconductor substrate, a dielectric layer formed over the photodiodes, a color filter layer formed over the dielectric layer, a planarization layer formed over the color filter layer, a phase change material formed over the planarization layer, and a plurality of microlenses formed over the planarization layer, wherein the phase change material is positioned in the microlens. Further, a method for manufacturing an image sensor according to embodiments may include forming a dielectric layer over a semiconductor substrate with a plurality of photodiodes, sequentially forming a color filter layer and a planarization layer over the dielectric layer, forming a phase change material over the planarization layer, forming a patterned phase change material by partially etching the phase change material, and forming microlenses over the planarization layer and the phase change material.05-06-2010
20100108970Memory Devices and Formation Methods - A method includes forming an electrical insulator material over an integrated circuit having a metal-containing conductive interconnect and activating a dopant in a semiconductor material of a substrate to provide a doped region. The doped region provides a junction of opposite conductivity types. After activating the dopant, the substrate is bonded to the insulator material and at least some of the substrate is removed where bonded to the insulator material. After the removing, a memory cell is formed having a word line, an access diode, a state-changeable memory element containing chalcogenide phase change material, and a bit line all electrically connected in series, the access diode containing the junction as a p-n junction. A memory device includes an adhesion material over the insulator material and bonding the word line to the insulator material.05-06-2010
20130026435SWITCHING DEVICE AND RESISTANCE CHANGE MEMORY DEVICE USING THE SAME - A switching device that provides bipolar current paths and a resistance change memory device using the switching device. The switching device includes a first electrode, a second electrode, and an amorphous carbon layer interposed between the first electrode and the second electrode and configured to control a bipolar current to flow therethrough in response to a voltage applied between the first electrode and the second electrode.01-31-2013
20130087755ELECTRICALLY ACTUATED SWITCH - A method of manufacturing an electrically actuable switch and comprising: depositing a first electrode on a surface; depositing an active layer or layers on top of said first electrode; and depositing a second electrode on top of said active layer(s), wherein said step of depositing an active layer or layers is performed in an atmosphere into which a reactive gas is introduced, the partial pressure of the reactive gas being varied during the process so as to introduce dopants into the active layer in a concentration which varies across the active layer.04-11-2013
20120181499QUATERNARY GALLIUM TELLURIUM ANTIMONY (M-GaTeSb) BASED PHASE CHANGE MEMORY DEVICES - A phase change material comprising a quaternary GaTeSb material consisting essentially of M07-19-2012
20120181498VERTICAL NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - Provided are a vertical nonvolatile memory device and a method for fabricating the vertical nonvolatile memory device. The vertical nonvolatile memory device can be integrated more highly as compared with a nonvolatile memory device of the related art. In addition, since the vertical nonvolatile memory device includes a selective diode, reading errors can be prevented.07-19-2012
20100006810Memory device and method of manufacturing the same - Provided are a memory device formed using one or more source materials not containing hydrogen as a constituent element and a method of manufacturing the memory device.01-14-2010
20100327249PHASE CHANGE MEMORY DEVICE HAVING AN IMPROVED WORD LINE RESISTANCE, AND METHODS OF MAKING SAME - A phase change memory device having an improved word line resistance and a fabrication method of making the same are presented. The phase change memory device includes a semiconductor substrate, a word line, an interlayer insulation film, a strapping line, a plurality of current paths, a switching element, and a phase change variable resistor. The word line is formed in a cell area of the semiconductor substrate. The interlayer insulation film formed on the word line. The strapping line is formed on the interlayer insulation film such that the strapping line overlaps on top of the word line. The current paths electrically connect together the word line with the strapping line. The switching element is electrically connected to the strapping line. The phase change variable resistor is electrically connected to the switching element.12-30-2010
20130048935PHASE CHANGE MEMORY CELLS INCLUDING NITROGENATED CARBON MATERIALS, METHODS OF FORMING THE SAME, AND PHASE CHANGE MEMORY DEVICES INCLUDING NITROGENATED CARBON MATERIALS - A phase change memory cell comprising a first chalcogenide compound on a first electrode, a first nitrogenated carbon material directly on the first chalcogenide compound, a second chalcogenide compound directly on the first nitrogenated carbon material, and a second nitrogenated carbon material directly on the second chalcogenide compound and directly on a second electrode. Other phase change memory cells are described. A method of forming a phase change memory cell and a phase change memory device are also described.02-28-2013
20130048936PHASE CHANGE MEMORY AND METHOD OF FABRICATING SAME - A fine pitch phase change random access memory (“PCRAM”) design and method of fabricating same are disclosed. One embodiment is a phase change memory (“PCM”) cell comprising a spacer defining a rectangular reaction area and a phase change material layer disposed within the reaction area. The PCM cell further comprises a protection layer disposed over the GST film layer and within the area defined by the spacer; and a capping layer disposed over the protection layer and the spacer.02-28-2013
20110001108FRONT TO BACK RESISTIVE RANDOM ACCESS MEMORY CELLS - A resistive random access memory device formed on a semiconductor substrate comprises an interlayer dielectric having a via formed therethrough. A chemical-mechanical-polishing stop layer is formed over the interlayer dielectric. A barrier metal liner lines walls of the via. A conductive plug is formed in the via. A first barrier metal layer is formed over the chemical-mechanical-polishing stop layer and in electrical contact with the conductive plug. A dielectric layer is formed over the first barrier metal layer. An ion source layer is formed over the dielectric layer. A dielectric barrier layer is formed over the ion source layer, and includes a via formed therethrough communicating with the ion source layer. A second barrier metal layer is formed over the dielectric barrier layer and in electrical contact with the ion source layer. A metal interconnect layer is formed over the barrier metal layer.01-06-2011
20100001250VARIABLE RESISTANCE MEMORY DEVICE WITH AN INTERFACIAL ADHESION HEATING LAYER, SYSTEMS USING THE SAME AND METHODS FORMING THE SAME - A variable resistance memory element and method of forming the same. The memory element includes a first electrode, a resistivity interfacial layer having a first surface coupled to said first electrode; a resistance changing material, e.g. a phase change material, having a first surface coupled to a second surface of said resistivity interfacial layer, and a second electrode coupled to a second surface of said resistance changing material.01-07-2010
20100133497SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - The invention includes: multiple bit lines b06-03-2010
20100133495PHASE CHANGE MEMORY DEVICES AND METHODS FOR FABRICATING THE SAME - A phase change memory device is provided, including a substrate, a first dielectric layer disposed over the substrate, a first electrode disposed in the first dielectric layer, a second dielectric layer formed over the first dielectric layer, covering the first electrode, a heating electrode disposed in the second dielectric layer, contacting the first electrode, a phase change material layer disposed over the second dielectric layer, contacting the heating electrode, and a second electrode disposed over the phase change material layer. In one embodiment, the heating electrode includes a first portion contacting the first electrode and a second portion contacting the phase change material layer, and the second portion of the heating electrode includes metal silicides and the first portion of the heating electrode includes no metal silicides.06-03-2010
20100133494USE OF LACUNAR SPINELS WITH TETRAHEDRAL AGGREGATES OF A TRANSITION ELEMENT OF THE AM4X8 TYPE WITH AN ELECTRONIC DATA REWRITABLE NON VOLATILE MEMORY, AND CORRESPONDING MATERIAL - The invention relates to the use of a material that belongs to the class of lacunar spinels with tetrahedral aggregates of an AM4X8 transition element as the active material for an electronic data non-volatile memory, in which: A comprises at least one of the following elements: Ga, Ge, Zn; M comprises at least one of the following elements: V, Nb, Ta, Mo; and X comprises at least one of the following elements: S, Se.06-03-2010
20090108247Memory Device - A phase-change memory device including a memory cell having a memory element and a select transistor is improved in heat resistance so that it may be operable at 145° C. or higher.04-30-2009
20090302296ALD PROCESSING TECHNIQUES FOR FORMING NON-VOLATILE RESISTIVE-SWITCHING MEMORIES - ALD processing techniques for forming non-volatile resistive-switching memories are described. In one embodiment, a method includes forming a first electrode on a substrate, maintaining a pedestal temperature for an atomic layer deposition (ALD) process of less than 100° Celsius, forming at least one metal oxide layer over the first electrode, wherein the forming the at least one metal oxide layer is performed using the ALD process using a purge duration of less than 20 seconds, and forming a second electrode over the at least one metal oxide layer.12-10-2009
20090302295Structures & Methods for Combining Carbon Nanotube Array and Organic Materials as a Variable Gap Interposer for Removing Heat from Solid-State Devices - One embodiment involves an article of manufacture that includes: a copper substrate plate with a front surface and a back surface; a blocking (barrier) layer on top of a single surface of the copper substrate; and a thermal interface material (TIM) on top of the single surface of the copper substrate. The thermal interface material comprises: a layer of carbon nanotubes that contains catalyst nanoparticles and, a filler material between and in contact with the carbon nanotubes. The carbon nanotubes are oriented substantially perpendicular to the single surface of the copper substrate and strongly attached to a blocking (barrier) layer. The TIM made of CNT array plus the elastic filler material is interposed between copper plate and the hot surface of a solid-state device. The TIM composite material adjusts to variable gap thickness to make optimal thermal contact area between opposing surfaces. The sandwich structure may include a non-uniform, variable gap TIM that can change during thermal cycles of operation. In some embodiments, the copper substrate plate is configured to be incorporated in a peripheral structure of a heat spreader. In some embodiments, the thermal interface material is on top of both the top and bottom surfaces of the copper substrate plug.12-10-2009
20090302294MULTI-BIT PHASE-CHANGE MEMORY DEVICE - A multi-bit phase-change memory device includes a semiconductor substrate with a plurality of phase-change patterns sequentially stacked above the semiconductor substrate. Each phase-change pattern crosses another phase change pattern, and each phase change pattern includes a phase-change conductive line formed on a surface thereof. Bipolar transistors are installed between the semiconductor substrate and the lowermost phase-change pattern and also among the phase-change patterns, and the bipolar transistors selectively form electrical connections between the semiconductor substrate and the lowermost phase-change pattern and also among the phase-change patterns. Heating electrodes are aligned between the respective bipolar transistors and phase-change patterns. The semiconductor substrate includes an active area that extends in a direction that is perpendicular to the extension direction of the lowermost phase-change pattern.12-10-2009
20090302293SEMICONDUCTOR DEVICE - On the same semiconductor substrate 12-10-2009
20120217462MEMORY CELL THAT EMPLOYS A SELECTIVELY GROWN REVERSIBLE RESISTANCE-SWITCHING ELEMENT AND METHODS OF FORMING THE SAME - A method of forming a memory cell is provided that includes forming a steering element above a substrate, and forming a reversible resistance-switching element coupled to the steering element. The reversible resistance-switching element includes one or more of TiO08-30-2012
20120217461SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory device according to an embodiment includes: first lines provided on a substrate; second lines provided between the first lines and the substrate so as to intersect the first lines; and a first memory cell array including first memory cells, each of the first memory cells being provided at respective intersections of the first lines and the second lines and including a current rectifying element and a variable resistor connected in series. The variable resistor of the first memory cell includes a first recording layer and a second recording layer, the first recording layer being made of an oxide of a first metal material, the second recording layer being made of the first metal material and being formed so as to contact with the first recording layer. The second recording layer is closer to the first line than the first recording layer is.08-30-2012
20130056698RESISTIVE MEMORY DEVICE HAVING VERTICAL TRANSISTORS AND METHOD FOR MAKING THE SAME - The present invention relates to resistive memory devices incorporating therein vertical selection transistors and methods for making the same. A resistive memory device comprises a semiconductor substrate having a first type conductivity; a plurality of vertical selection transistors formed on the semiconductor substrate in an array, each of the plurality of vertical selection transistors including a semiconductor pillar protruded from the semiconductor substrate, top region of the semiconductor pillar having a second type conductivity opposite to the first type conductivity provided in the semiconductor substrate; and a gate electrode surrounding the semiconductor pillar with a gate dielectric layer interposed therebetween, the gate electrode being lower in height than the semiconductor pillar; a plurality of contact studs disposed on top of the vertical selection transistors; a plurality of resistive memory elements disposed on top of the contact studs; a plurality of parallel word lines connecting the vertical selection transistors by way of respective gate electrodes, the parallel word lines extending along a first direction; a plurality of parallel bit lines connecting the resistive memory elements, the parallel bit lines extending along a second direction different from the first direction provided in the parallel word lines; and a plurality of parallel source lines with the second type conductivity formed in top regions of the semiconductor substrate in between rows of the semiconductor pillars, wherein the source lines and the top regions of the semiconductor pillars function as source and drain, respectively.03-07-2013
20120112153NONVOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is a nonvolatile memory device which requires a lower initializing voltage such that the nonvolatile memory device can be operated at a low voltage. The nonvolatile memory device (05-10-2012
20120112152ELECTRONICALLY CONTROLLED SQUISHABLE COMPOSITE SWITCH - A method and apparatus for making analog and digital electronics which includes a composite including a squishable material doped with conductive particles. A microelectromechanical systems (MEMS) device has a channel made from the composite, where the channel forms a primary conduction path for the device. Upon applied voltage, capacitive actuators squeeze the composite, causing it to become conductive. The squishable device includes a control electrode, and a composite electrically and mechanically connected to two terminal electrodes. By applying a voltage to the control electrode relative to a first terminal electrode, an electric field is developed between the control electrode and the first terminal electrode. This electric field results in an attractive force between the control electrode and the first terminal electrode, which compresses the composite and enables electric control of the electron conduction from the first terminal electrode through the channel to the second terminal electrode.05-10-2012
20120112151METHODS OF FORMING A CRYSTALLINE Pr1-xCaxMnO3 (PCMO) MATERIAL AND METHODS OF FORMING SEMICONDUCTOR DEVICE STRUCTURES COMPRISING CRYSTALLINE PCMO - A method of forming a crystalline Pr05-10-2012
20120112150Post Deposition Adjustment of Chalcogenide Composition in Chalcogenide Containing Semiconductors - The concentration of a constituent within a chalcogenide film used to form a chalcogenide containing semiconductor may be adjusted post deposition by reacting the chalcogenide film with a material in contact with the chalcogenide film. For example, a chalcogenide film containing tellurium may be coated with a titanium layer. Upon the application of heat, the titanium may react with the tellurium to a controlled extent to reduce the concentration of tellurium in the chalcogenide film.05-10-2012
20130056699PHASE CHANGE MEMORY CELL HAVING VERTICAL CHANNEL ACCESS TRANSISTOR - A device includes a substrate having a first region and a second region. The first region comprises a first field effect transistor having a horizontal channel region within the substrate, a gate overlying the horizontal channel region, and a first dielectric covering the gate of the first field effect transistor. The second region of the substrate includes a second field effect transistor comprising a first terminal extending through the first dielectric to contact the substrate, a second terminal overlying the first terminal and having a top surface, and a vertical channel region separating the first and second terminals. The second field effect transistor also includes a gate on the first dielectric and adjacent the vertical channel region, the gate having a top surface that is co-planar with the top surface of the second terminal.03-07-2013
20090283736NONVOLATILE MEMORY ELEMENT, MANUFACTURING METHOD THEREOF, AND NONVOLATILE SEMICONDUCTOR APPARATUS USING THE NONVOLATILE MEMORY ELEMENT - A nonvolatile memory element comprises a first electrode layer (11-19-2009
20090267042Integrated Circuit and Method of Manufacturing an Integrated Circuit - According to one embodiment of the present invention, an integrated circuit including a plurality of resistance changing memory cells is provided. Each memory cell includes: a semiconductor substrate; a select device arranged within the semiconductor substrate; and a memory element being arranged above the semiconductor substrate. The select device is a diode comprising a first semiconductor area of a first conductive type and a second semiconductor area of a second conductive type which are arranged adjacent to each other such that a lateral pn-junction is formed. The first semiconductor area is connected to a word line arranged on or above the semiconductor substrate. The second semiconductor area is connected to the memory element via a conductive connection element.10-29-2009
20110012082ELECTRONIC COMPONENT COMPRISING A CONVERTIBLE STRUCTURE - An electronic component (01-20-2011
20110012081SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a first conductive line, a second conductive line crossing over the first conductive line, a resistance variation part disposed at a position in which the second conductive line intersects with the first conductive line and electrically connected to the first conductive line and the second conductive line and a mechanical switch disposed between the resistance variation part and the second conductive line. The mechanical switch includes a nanotube.01-20-2011
20110012080Arsenic-Containing Variable Resistance Materials - A variable resistance material for memory applications. The material includes a base Ge—Sb—Te composition and further includes As-doping. The materials were included in variable resistance memory devices. Incorporation of As in the variable resistance composition led to a significant increase in the operational life of the device and, unexpectedly, did not reduce the programming speed of the device. In one embodiment, the composition includes at atomic concentration of Ge in the range from 7%-13%, an atomic concentration of Sb in the range from 50%-70%, an atomic concentration of Te in the range from 20%-30%, and an atomic concentration of As in the range from 2%-15%.01-20-2011
20110012079THERMAL PROTECT PCRAM STRUCTURE AND METHODS FOR MAKING - A memory cell as described herein includes a conductive contact and a memory element comprising programmable resistance memory material overlying the conductive contact. An insulator element extends from the conductive contact into the memory element, the insulator element having proximal and distal ends and an inside surface defining an interior. The proximal end is adjacent the conductive contact. A bottom electrode contacts the conductive contact and extends upwardly within the interior from the proximal end. The memory element is within the interior extending downwardly from the distal end to contact a top surface of the bottom electrode at a first contact surface. A top electrode can be separated from the distal end of the insulator element by the memory element and contact the memory element at a second contact surface having a surface area greater than that of the first contact surface.01-20-2011
20090236581RESISTANCE MEMORY ELEMENT, METHOD OF MANUFACTURING RESISTANCE MEMORY ELEMENT AND SEMICONDUCTOR MEMORY DEVICE - A resistance memory element which memorizes a high resistance state and a low resistance state and is switched between the high resistance state and the low resistance state by an application of a voltage includes a first electrode layer of titanium nitride film, a resistance memory layer formed on the first electrode layer and formed of titanium oxide having a crystal structure of rutile phase, and a second electrode layer formed on the resistance memory layer.09-24-2009
20130069029NON-VOLATILE MEMORY DEVICE AND MANUFACTURING METHOD OF THE SAME - According to one embodiment, a memory cell section includes a memory layer in which a non-volatile memory cell is arranged at an intersecting position of a first wiring and a second wiring to be sandwiched by the first wiring and the second wiring. A first drawing section connects the memory cell section and a first contact section with the first wiring, and a second drawing section connects the memory cell section and a second contact section with the second wiring. A dummy pattern is provided in a layer corresponding to the memory layer immediately below the first and second wirings configuring the first and second drawing sections.03-21-2013
20130069028SELECT DEVICES FOR MEMORY CELL APPLICATIONS - Select devices for memory cell applications and methods of forming the same are described herein. As an example, one or more non-ohmic select devices can include at least two tunnel barrier regions formed between a first metal material and a second metal material, and a third metal material formed between each of the respective at least two tunnel barrier regions. The non-ohmic select device is a two terminal select device that supports bi-directional current flow therethrough.03-21-2013
20130214231IN-SITU NITRIDE INITIATION LAYER FOR RRAM METAL OXIDE SWITCHING MATERIAL - A resistive memory device having an in-situ nitride initiation layer is disclosed. The nitride initiation layer is formed above the first electrode, and the metal oxide switching layer is formed above the nitride initiation layer to prevent oxidation of the first electrode. The nitride initiation layer may be a metal nitride layer that is formed by atomic layer deposition in the same chamber in which the metal oxide switching layer is formed. The nitride initiation layer and metal oxide switching layer may alternatively be formed in a chemical vapor deposition (CVD) chamber or a physical vapor deposition (PVD) chamber.08-22-2013
20090272959Non-Volatile Resistive-Switching Memories - Non-volatile resistive-switching memories are described, including a memory element having a first electrode, a second electrode, a metal oxide between the first electrode and the second electrode. The metal oxide switches using bulk-mediated switching, has a bandgap greater than 4 electron volts (eV), has a set voltage for a set operation of at least one volt per one hundred angstroms of a thickness of the metal oxide, and has a leakage current density less than 40 amps per square centimeter (A/cm11-05-2009
20120235107NONVOLATILE MEMORY DEVICE - According to one embodiment, a nonvolatile memory device includes a word line interconnect layer, a bit line interconnect layer, a pillar, and charge bearing members. The word line interconnect layer includes a plurality of word lines extending in a first direction. The bit line interconnect layer includes a plurality of bit lines extending in a second direction that intersects the first direction. The pillar is disposed between each of the word lines and each of the bit lines. The charge bearing members contain a negative fixed charge, and provided on side faces of the pillars. The pillars includes a diode film provided with a p-type layer and an n-type layer and a variable resistance film stacked on the diode film. The charge bearing member is disposed on side faces of the p-type layer, and is not disposed on side faces of the n-type layer.09-20-2012
20120235106METHODS OF FORMING AT LEAST ONE CONDUCTIVE ELEMENT, METHODS OF FORMING A SEMICONDUCTOR STRUCTURE, METHODS OF FORMING A MEMORY CELL AND RELATED SEMICONDUCTOR STRUCTURES - Methods of forming conductive elements, such as interconnects and electrodes, for semiconductor structures and memory cells. The methods include forming a first conductive material and a second conductive material comprising silver in a portion of at least one opening and performing a polishing process to fill the at least one opening with at least one of the first and second conductive materials. An annealing process may be performed to form a mixture or an alloy of the silver and the material. The methods enable formation of silver containing conductive elements having reduced dimensions (e.g., less than about 20 nm). The resulting conductive elements have a desirable resistivity. The methods may be used, for example, to form interconnects for electrically connecting active devices and to form electrodes for memory cells. A semiconductor structure and a memory cell including such a conductive structure are also disclosed.09-20-2012
20130207065BIPOLAR MULTISTATE NONVOLATILE MEMORY - Embodiments generally include a method of forming a nonvolatile memory device that contains a resistive switching memory element that has an improved device switching capacity by using multiple layers of variable resistance layers. In one embodiment, the resistive switching element comprises at least three layers of variable resistance materials to increase the number of logic states. Each variable resistance layer may have an associated high resistance state and an associated low resistance state. As the resistance of each variable resistance layer determines the digital data bit that is stored, the multiple variable resistance layers per memory element allows for additional data storage without the need to further increase the density of nonvolatile memory devices. Typically, resistive switching memory elements may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices, such as digital cameras, mobile telephones, handheld computers, and music players.08-15-2013
20130207066PLANAR RESISTIVE MEMORY INTEGRATION - In an example, a single damascene structure is formed by, for example, providing a dielectric layer, forming a void in the dielectric layer, and forming a portion of a first two-terminal resistive memory cell and a portion of a second two-terminal resistive memory cell within the void. The portions of the two-terminal resistive memory cells may be vertically stacked within the void.08-15-2013
20110024712PCM With Poly-Emitter BJT Access Devices - A phase change memory (PCM) includes an array comprising a plurality of memory cells, a memory cell comprising a phase change element (PCE); and a PCE access device comprising a bipolar junction transistor (BJT), the BJT comprising an emitter region comprising a polycrystalline semiconductor. A memory cell for a phase change memory (PCM) includes a phase change element (PCE); and a PCE access device comprising a bipolar junction transistor (BJT), the BJT comprising an emitter region comprising a polycrystalline semiconductor.02-03-2011
20100127232NON-VOLATILE MEMORY - A non-volatile memory (05-27-2010
20110315944RESISTIVE MEMORY AND METHODS OF PROCESSING RESISTIVE MEMORY - Resistive memory and methods of processing resistive memory are described herein. One or more method embodiments of processing resistive memory include conformally forming a cell material in an opening in an interlayer dielectric such that a seam is formed in the cell material, forming a conductive pathway by modifying the seam, and forming an electrode on the cell material and the seam.12-29-2011
20120097912SEMICONDUCTOR DEVICE - For example, one memory cell is configured using two memory cell transistors and one phase change element by disposing a plurality of diffusion layers in parallel to a bit-line, disposing gates between the diffusion layers so as to cross the bit-line, disposing bit-line contacts and source contacts alternately to the plurality of diffusion layers arranged in a bit-line direction for each diffusion layer, and providing a phase change element on the source contact. Also, the phase change element can be provided on the bit-line contact instead of the source contact. By this means, for example, increase in drivability of the memory cell transistors and reduction in area can be realized.04-26-2012
20110127483RESISTANCE CHANGE MEMORY AND MANUFACTURING METHOD THEREOF - According to one embodiment, a resistance-change memory of embodiment includes a first interconnect line extending in a first direction, a second interconnect line extending in a second direction intersecting with the first direction, and a cell unit. The cell unit is provided at an intersection of the first interconnect line and the second interconnect line. The cell unit includes a non-ohmic element having a silicide layer on at least one of first and second ends thereof, and a memory element to store data in accordance with a reversible change in a resistance state. The silicide layer includes a 3d transition metal element which combines with an Si element to form silicide and which has a first atomic radius, and at least one kind of an additional element having a second atomic radius greater than the first atomic radius.06-02-2011
20090309088SWITCHING DEVICE, SEMICONDUCTOR DEVICE, PROGRAMMABLE LOGIC INTEGRATED CIRCUIT, AND MEMORY DEVICE - A typical switching device according to the present invention comprises first insulating layer 12-17-2009
20100171089DIELECTRIC LAYERS AND MEMORY CELLS INCLUDING METAL-DOPED ALUMINA - A method of forming (and an apparatus for forming) a metal-doped aluminum oxide layer on a substrate, particularly a semiconductor substrate or substrate assembly, using a vapor deposition process.07-08-2010
20100171086INTEGRATED CIRCUIT MEMORY WITH SINGLE CRYSTAL SILICON ON SILICIDE DRIVER AND MANUFACTURING METHOD - A memory device includes a diode driver and a data storage element, such as an element comprising phase change memory material, and in which the diode driver comprises a silicide element on a silicon substrate with a single crystal silicon node on the silicide element. The silicide element separates the single crystal silicon node from the underlying silicon substrate, preventing the flow of carriers from the single crystal silicon node into the substrate, and is capable of acting as a conductive element for interconnecting devices on the device. The single crystal silicon node acts as one terminal of a diode, and a second semiconductor node is formed on top of it, acting as the other terminal of the diode.07-08-2010
20100171087SEMICONDUCTOR DEVICE AND PROCESS FOR PRODUCING THE SAME - In a semiconductor device including a phase change memory element whose memory layer is formed of a phase change material of M (additive element)-Ge (germanium)-Sb (antimony)-Te (tellurium), both of high heat resistance and stable data retention property are achieved. The memory layer has a fine structure with a different composition ratio therein, and an average composition of M07-08-2010
20110193043Ultra-Low Energy RRAM with Good Endurance and Retention - This invention proposes an ultra-low energy (ULE) RRAM with electrode08-11-2011
20100006812CARBON-BASED RESISTIVITY-SWITCHING MATERIALS AND METHODS OF FORMING THE SAME - Memory devices including a carbon-based resistivity-switchable material, and methods of forming such memory devices are provided, the methods including introducing a processing gas into a processing chamber, wherein the processing gas includes a hydrocarbon compound and a carrier gas, and generating a plasma of the processing gas to deposit a layer of the carbon-based switchable material on a substrate within the processing chamber. Numerous additional aspects are provided.01-14-2010
20100006811CARBON-BASED INTERFACE LAYER FOR A MEMORY DEVICE AND METHODS OF FORMING THE SAME - In a first aspect, a memory cell is provided that includes (1) a first conductor; (2) a reversible resistance-switching element formed above the first conductor including (a) a carbon-based resistivity switching material; and (b) a carbon-based interface layer coupled to the carbon-based resistivity switching material; (3) a steering element formed above the first conductor; and (4) a second conductor formed above the reversible resistance-switching element and the steering element. Numerous other aspects are provided.01-14-2010
20110284814Large Bit-Per-Cell Three-Dimensional Mask-Programmable Read-Only Memory - A large bit-per-cell three-dimensional mask-programmable read-only memory (3D-MPROM11-24-2011
20110291063SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a word line interconnect layer, a bit line interconnect layer and a pillar. The word line interconnect layer includes a plurality of word lines extending in a first direction. The bit line interconnect layer includes a plurality of bit lines extending in a second direction intersecting with the first direction. The pillar is disposed between each of the word lines and each of the bit lines. The pillar has a selector stacked film containing silicon, and a variable resistance film disposed on a side of the word lines or the bit lines. The selector stacked film has a different component-containing layer. The different component-containing layer is formed at one position in a region excluding ends on the sides of the word and bit lines, and contains a 14 group element having a larger atomic radius than an atomic radius of silicon.12-01-2011
20110140064CARBON/TUNNELING-BARRIER/CARBON DIODE - A carbon/tunneling-barrier/carbon diode and method for forming the same are disclosed. The carbon/tunneling-barrier/carbon may be used as a steering element in a memory array. Each memory cell in the memory array may include a reversible resistivity-switching element and a carbon/tunneling-barrier/carbon diode as the steering element. The tunneling-barrier may include a semiconductor or an insulator. Thus, the diode may be a carbon/semiconductor/carbon diode. The semiconductor in the diode may be intrinsic or doped. The semiconductor may be depleted when the diode is under equilibrium conditions. For example, the semiconductor may be lightly doped such that the depletion region extends from one end of the semiconductor region to the other end. The diode may be a carbon/insulator/carbon diode.06-16-2011
20110297910METHOD OF FABRICATION OF PROGRAMMABLE MEMORY MICROELECTRIC DEVICE - A method of fabricating a programmable memory microelectronic device includes depositing onto a first electrode an intermediate layer of a material having a chalcogenide; depositing an ionizable metallic layer on the intermediate layer; irradiating with ultraviolet radiation the ionizable metallic layer so that metallic ions from the ionizable metallic layer diffuse into the intermediate layer to form a chalcogenide material containing metallic ions, and depositing a second electrode on the layer of chalcogenide material containing metallic ions obtained in the prior step. The second and third steps are repeated at least n times, where n is an integer greater than or equal to 1. The ionizable metallic layer deposited during the second step has a sufficiently small thickness that the metallic ions may be diffused totally during the irradiation (third) step.12-08-2011
20100258777Diamond Type Quad-Resistor Cells of PRAM - A method of forming a phase-change random access memory (PRAM) cell, and a structure of a phase-change random access memory (PRAM) cell are disclosed. The PRAM cell includes a bottom electrode, a heater resistor coupled to the bottom electrode, a phase change material (PCM) formed over and coupled to the heater resistor, and a top electrode coupled to the phase change material. The phase change material contacts a portion of a vertical surface of the heater resistor and a portion of a horizontal surface of the heater resistor to form an active region between the heater resistor and the phase change material.10-14-2010
20090289241Phase change memory devices and fabrication methods thereof - In a memory device, a transistor may be formed on a substrate, and a first electrode may be electrically connected thereto. A phase change material film may be vertically formed on the first electrode, and a second electrode may be formed on the phase change material film.11-26-2009
20080272355PHASE CHANGE MEMORY DEVICE AND METHOD FOR FORMING THE SAME - A memory device using a phase change material and a method for forming the same are disclosed. One embodiment of a memory device includes a first insulating layer provided on a substrate and defining an opening; a first conductor including a first portion and a second portion, the first portion provided on a bottom of the opening, the second portion being continuously provided along a sidewall of the opening; a variable resistor connected to the second portion of the first conductor and provided along the sidewall of the opening; and a second conductor provided on the variable resistor.11-06-2008
20120097911PHASE CHANGE MEMORY CELL STRUCTURES AND METHODS - Phase change memory cell structures and methods are described herein. A number of methods of forming a phase change memory cell structure include forming a dielectric stack structure on a first electrode, wherein forming the dielectric stack structure includes creating a second region between a first region and a third region of the dielectric stack structure, the second region having a thermal conductivity different than a thermal conductivity of the first region and different than a thermal conductivity of the third region of the dielectric stack. One or more embodiments include forming a via through the first, second, and third regions of the dielectric stack structure, depositing a phase change material in the via, and forming a second electrode on the phase change material.04-26-2012
20090267043PHASE CHANGE MEMORY DEVICE RESISTANT TO STACK PATTERN COLLAPSE AND A METHOD FOR MANUFACTURING THE SAME - A phase change memory device resistant to stack pattern collapse is presented. The phase change memory device includes a silicon substrate, switching elements, heaters, stack patterns, bit lines and word lines. The silicon substrate has a plurality of active areas. The switching elements are connected to the active areas. The heaters are connected to the switching elements. The stack patterns are connected to the heaters. The bit lines are connected to the stack patterns. The word lines are connected to the active areas of the silicon substrate.10-29-2009
20090184304PHASE CHANGE MEMORY DEVICE HAVING PLUG-SHAPED PHASE CHANGE LAYERS AND METHOD FOR MANUFACTURING THE SAME - A phase change memory device having plug-shaped phase change layers and a process of manufacturing the same is provided. The device and process includes forming first electrodes on a substrate. An insulation layer is then formed to cover the first electrodes. Plug-shaped phase change layers are then formed in the insulation layer to contact the first electrodes. The plug-shaped phase change layers have a straight-line or an ‘L’ shape when viewed as a cross-section and a horseshoe or a semicircle shape when viewed from above. Finally, bit lines are formed on the insulation layer to contact the phase change layers and additionally serve as second electrodes. The device may further include heaters interposed between the first electrodes and the plug-shaped phase change layers.07-23-2009
20090101881SEMICONDUCTOR DEVICES HAVING PHASE CHANGE MEMORY CELLS, ELECTRONIC SYSTEMS EMPLOYING THE SAME AND METHODS OF FABRICATING THE SAME - In one embodiment, a phase-change memory device has an oxidation barrier layer to protect against memory cell contamination or oxidation and a method of manufacturing the same. In one embodiment, a semiconductor memory device comprises a molding layer overlying a semiconductor substrate. The molding layer has a protrusion portion vertically extending from a top surface thereof. The device further includes a phase-changeable material pattern adjacent the protrusion portion and a lower electrode electrically connected to the phase-changeable material pattern.04-23-2009
20090294749Chemical Mechanical Polishing Slurry Composition for Polishing Phase-Change Memory Device and Method for Polishing Phase-Change Memory Device Using the Same - A slurry composition for chemical mechanical polishing (CMP) of a phase-change memory device is provided. The slurry composition comprises deionized water and iron or an iron compound. The slurry composition can achieve high polishing rate on a phase-change memory device and improved polishing selectivity between a phase-change memory material and a polish stop layer (e.g., a silicon oxide film), can minimize the occurrence of processing imperfections (e.g., dishing and erosion), and can lower the etch rate on a phase-change memory material to provide a high-quality polished surface. Further provided is a method for polishing a phase-change memory device using the slurry composition.12-03-2009
20100032637NONVOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is a nonvolatile memory device including a phase-change memory configured with cross-point memory cells in which memory elements formed of a phase-change material and selection elements formed with a diode are combined. A memory cell is configured with a memory element formed of a phase-change material and a selection element formed with a diode having a stacked structure of a first polycrystalline silicon film, a second polycrystalline silicon film, and a third polycrystalline silicon film. The memory cells are arranged at intersection points of a plurality of first metal wirings extending along a first direction with a plurality of third metal wirings extending along a second direction orthogonal to the first direction. An interlayer film is formed between adjacent selection elements and between adjacent memory elements, and voids are formed in the interlayer film provided between the adjacent memory elements.02-11-2010
20100032635ARRAY OF LOW RESISTIVE VERTICAL DIODES AND METHOD OF PRODUCTION - An integrated circuit comprising an array of memory cells and a corresponding production method are described. Each memory cell comprises a resistively switching memory element and a vertical selection diode coupled to a selection line in a selection line trench for selecting one cell from the plurality of memory cells. A selection line is coupled to the vertical selection diode at one vertical sidewall of the selection line trench.02-11-2010
20090250677Reducing drift in chalcogenide devices - Chalcogenide materials conventionally used in chalcogenide memory devices and ovonic threshold switches may exhibit a tendency called drift, wherein threshold voltage or resistance changes with time. By providing a compensating material which exhibits an opposing tendency, the drift may be compensated. The compensating material may be mixed into a chalcogenide, may be layered with chalcogenide, may be provided with a heater, or may be provided as part of an electrode in some embodiments. Both chalcogenide and non-chalcogenide compensating materials may be used.10-08-2009
20120187361Non-Volatile Memory Arrays Comprising Rail Stacks With A Shared Diode Component Portion For Diodes Of Electrically Isolated Pillars - An integrated circuit including vertically oriented diode structures between conductors and methods of fabricating the same are provided. Two-terminal devices such as passive element memory cells can include a diode steering element in series with an antifuse and/or other state change element. The devices are formed using pillar structures at the intersections of upper and lower sets of conductors. The height of the pillar structures are reduced by forming part of the diode for each pillar in a rail stack with one of the conductors. A diode in one embodiment can include a first diode component of a first conductivity type and a second diode component of a second conductivity type. A portion of one of the diode components is divided into first and second portions with one on the portions being formed in the rail stack where it is shared with other diodes formed using pillars at the rail stack.07-26-2012
20090189136SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD OF THE SEMICONDUCTOR DEVICE - A reliability of a semiconductor device having a phase-change memory is improved. A phase-change memory device has a bottom-electrode plug buried in an interlayer insulator that is provided on a main surface of a semiconductor substrate, an electric conductive material layer provided on an upper portion of the bottom-electrode plug and on the interlayer insulator, a phase-change material layer provided on the electric conductive material layer, and an upper-electrode plug provided on the phase-change material layer. The bottom-electrode plug and the upper-electrode plug which configure the phase-change memory device are provided at respective different positions in a plane of the semiconductor substrate.07-30-2009
20100276654Low Operational Current Phase Change Memory Structures - Memory cells described herein have an increased current density at lateral edges of the active region compared to that of conventional mushroom-type memory cells, resulting in improved operational current efficiency.11-04-2010
20090146125RESISTIVE MEMORY AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing resistive memory includes depositing a first conductive material layer on a substrate; etching the first conductive material layer to form a first signal line with a first surface; forming a memory material layer with a second surface coupled to the first signal line via the second surface contacting the first surface; depositing a second conductive material layer coupled to the memory material layer; etching the second conductive material layer to form a second signal line, wherein the area of the second surface is substantially larger or equal to the area of the overlapping region of the first signal line and the second signal line.06-11-2009
20110260131NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a nonvolatile semiconductor memory device includes a memory portion and a rectifying element. The memory portion includes a cathode electrode, a memory layer, and an anode electrode. The rectifying element is connected to one of the cathode electrode and the anode electrode, or incorporates the memory portion into an inner portion of the rectifying element. The rectifying element includes a first semiconductor layer, a second semiconductor layer, and an insulating layer provided between the first semiconductor layer and the second semiconductor layer, and the first semiconductor layer and the second semiconductor layer are a p10-27-2011
20100264393NONVOLATILE MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A nonvolatile memory device of the present invention comprises a substrate (10-21-2010
20120292585CONTINUOUS PLANE OF THIN-FILM MATERIALS FOR A TWO-TERMINAL CROSS-POINT MEMORY - A structure for a memory device including a plurality of substantially planar thin-film layers or a plurality of conformal thin-film layers is disclosed. The thin-film layers form a memory element that is electrically in series with first and second cladded conductors and operative to store data as a plurality of conductivity profiles. A select voltage applied across the first and second cladded conductors is operative to perform data operations on the memory device. The memory device may optionally include a non-ohmic device electrically in series with the memory element and the first and second cladded conductors. Fabrication of the memory device does not require the plurality of thin-film layers be etched in order to form the memory element. The memory element can include a CMO layer having a selectively crystallized polycrystalline portion and an amorphous portion. The cladded conductors can include a core material made from copper.11-22-2012
20090309087PHASE CHANGE MEMORY CELL HAVING TOP AND BOTTOM SIDEWALL CONTACTS - Memory devices and methods for manufacturing are described herein. A memory device as described herein includes a memory element and a first electrode having an inner surface surrounding the memory element to contact the memory element at a first contact surface. The device includes a second electrode spaced away from the first electrode, the second electrode having an inner surface surrounding the memory element to contact the memory element at a second contact surface.12-17-2009
20100038614METHODS OF FORMING A PHASE CHANGE MATERIAL, A PHASE CHANGE MATERIAL, A PHASE CHANGE RANDOM ACCESS MEMORY DEVICE INCLUDING THE PHASE CHANGE MATERIAL, AND A SEMICONDUCTOR STRUCTURE INCLUDING THE PHASE CHANGE MATERIAL - Methods of forming a phase change material are disclosed. The method includes forming a chalcogenide compound on a substrate and simultaneously applying a bias voltage to the substrate to alter the stoichiometry of the chalcogenide compound. In another embodiment, the method includes positioning a substrate and a deposition target having a first stoichiometry in a deposition chamber. A plasma is generated in the deposition chamber to form a phase change material on the substrate. The phase change material has a stoichiometry similar to the first stoichiometry. A bias voltage is applied to the substrate to convert the stoichiometry of the phase change material to a second stoichiometry. A phase change material, a phase change random access memory device, and a semiconductor structure are also disclosed.02-18-2010
20100117041RESISTIVE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A resistive memory device includes a first conductive line on a substrate, a vertical selection diode comprising a nanowire or a nanotube and being arranged over the first conductive line, a resistive element including a resistive layer arranged over the vertical selection diode; and a second conductive line arranged over the resistive element.05-13-2010
20100084624Dielectric mesh isolated phase change structure for phase change memory - A method for manufacturing a memory device, and a resulting device, is described using silicon oxide doped chalcogenide material. A first electrode having a contact surface; a body of phase change memory material in a polycrystalline state including a portion in contact with the contact surface of the first electrode, and a second electrode in contact with the body of phase change material are formed. The process includes melting and cooling the phase change memory material one or more times within an active region in the body of phase change material without disturbing the polycrystalline state outside the active region. A mesh of silicon oxide in the active region with at least one domain of chalcogenide material results. Also, the grain size of the phase change material in the polycrystalline state outside the active region is small, resulting in a more uniform structure.04-08-2010
20100078616NONVOLATILE MEMORY DEVICE AND MANUFACTURING PROCESS THEREOF - A nonvolatile memory device has a first insulating layer, a variable resistance layer provided on the first insulating layer and having a variable resistance material, and a first electrode and second electrode electrically connected with the variable resistance layer. The variable resistance layer has a variable resistance region as a data storing region and a thickness-changing region continuously extending from the variable resistance region and gradually becoming thicker from the variable resistance region.04-01-2010
20110062406Memory Devices and Formation Methods - A method includes forming an electrical insulator material over an integrated circuit having a metal-containing conductive interconnect and activating a dopant in a semiconductor material of a substrate to provide a doped region. The doped region provides a junction of opposite conductivity types. After activating the dopant, the substrate is bonded to the insulator material and at least some of the substrate is removed where bonded to the insulator material. After the removing, a memory cell is formed having a word line, an access diode, a state-changeable memory element containing chalcogenide phase change material, and a bit line all electrically connected in series, the access diode containing the junction as a p-n junction. A memory device includes an adhesion material over the insulator material and bonding the word line to the insulator material.03-17-2011
20110062405INFORMATION RECORDING AND REPRODUCING DEVICE - According to one embodiment, an information recording and reproducing device includes a first layer, a second layer, and a recording layer between the first and second layers, which is capable of a transition between a first state of a low resistance and a second state of a high resistance by flowing a current between the first and second layers. A peripheral portion of the recording layer has a composition different from that of a center portion of the recording layer. The center portion includes two kinds of cation elements. And the center portion is different from the peripheral portion in a ratio of the two kinds of cation elements.03-17-2011
20100090187Resistive memory device - Disclosed is a resistive memory device. In the resistive memory device, at least one variable resistance region and at least one switching device may be horizontally apart from each other, rather than being disposed on the same vertical axis. At least one intermediate electrode, which electrically connects the at least one variable resistance region and the at least one switching device, may be between the at least one variable resistance region and the at least one switching device.04-15-2010
20110168965Reducing Drift in Chalcogenide Devices - Chalcogenide materials conventionally used in chalcogenide memory devices and ovonic threshold switches may exhibit a tendency called drift, wherein threshold voltage or resistance changes with time. By providing a compensating material which exhibits an opposing tendency, the drift may be compensated. The compensating material may be mixed into a chalcogenide, may be layered with chalcogenide, may be provided with a heater, or may be provided as part of an electrode in some embodiments. Both chalcogenide and non-chalcogenide compensating materials may be used.07-14-2011
20110266510Controlled Placement of Dopants in Memristor Active Regions - Various embodiments of the present invention are direct to nanoscale, reconfigurable memristor devices. In one aspect, a memristor device (11-03-2011
20090045385INTEGRATED CIRCUIT INCLUDING MEMORY ELEMENT WITH HIGH SPEED LOW CURRENT PHASE CHANGE MATERIAL - An integrated circuit includes a first electrode, a second electrode, and a memory element coupled to the first electrode and to the second electrode, the memory element includes fast-operation resistance changing material doped with dielectric material.02-19-2009
20090189137NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - In a phase change memory, electric property of a diode used as a selection device is extremely important. However, since crystal grain boundaries are present in the film of a diode using polysilicon, it involves a problem that the off leak property varies greatly making it difficult to prevent erroneous reading. For overcoming the problem, the present invention provides a method of controlling the temperature profile of an amorphous silicon in the laser annealing for crystallizing and activating the amorphous silicon thereby controlling the crystal grain boundaries. According to the invention, variation in the electric property of the diode can be decreased and the yield of the phase-change memory can be improved.07-30-2009
20080210921Silver selenide film stoichiometry and morphology control in sputter deposition - A method of sputter depositing silver selenide and controlling the stoichiometry and nodular defect formations of a sputter deposited silver-selenide film. The method includes depositing silver-selenide using a sputter deposition process at a pressure of about 0.3 mTorr to about 10 mTorr. In accordance with one aspect of the invention, an RF sputter deposition process may be used preferably at pressures of about 2 mTorr to about 3 mTorr. In accordance with another aspect of the invention, a pulse DC sputter deposition process may be used preferably at pressures of about 4 mTorr to about 5 mTorr.09-04-2008
20090108248INTEGRATED CIRCUIT INCLUDING DOPED SEMICONDUCTOR LINE HAVING CONDUCTIVE CLADDING - An integrated circuit includes an array of memory cells and a doped semiconductor line formed in a semiconductor substrate. The doped semiconductor line is coupled to a row of memory cells. The integrated circuit includes conductive cladding contacting the doped semiconductor line.04-30-2009
20090272958Resistive Memory - An integrated circuit including a memory cell and method of manufacturing the integrated circuit are described. The memory cell includes a diode and a resistive memory element coupled to the diode. The resistive memory element includes a thin oxide storage layer that uses multiple resistance levels to store more than one bit of information in the resistive memory element.11-05-2009
20090278107Phase change memory device - The phase change memory device includes a first electrode and a second electrode and a first phase change material pattern and a second phase change material pattern interposed between the first electrode and the second electrode, wherein the first and second phase change material patterns have respectively different electrical characteristics.11-12-2009
20130099187MULTILAYER STRUCTURE BASED ON A NEGATIVE DIFFERENTIAL RESISTANCE MATERIAL - A multilayer structure is disclosed that includes a conductive layer, a layer of a negative differential resistance (NDR) material disposed above the conductive layer, a layer M04-25-2013
20130099188PHASE-CHANGE MEMORY DEVICE HAVING MULTI-LEVEL CELL AND A METHOD OF MANUFACTURING THE SAME - A phase change memory device including a multi-level cell and a method of manufacturing the same are provided. The device includes a first phase-change material layer to which a current is provided from a heating electrode, and a second phase-change material layer formed with continuity to the first phase-change material layer and having a different width from the first phase-change material layer, and to which a current is provided from a heating electrode.04-25-2013
20090289240NON-VOLATILE MULTI-BIT MEMORY WITH PROGRAMMABLE CAPACITANCE - Non-volatile multi-bit memory with programmable capacitance is disclosed. Illustrative data memory units include a substrate including a source region and a drain region. A first insulating layer is over the substrate. A first solid electrolyte cell is over the insulating layer and has a capacitance that is controllable between at least two states and is proximate the source region. A second solid electrolyte cell is over the insulating layer and has a capacitance or resistance that is controllable between at least two states and is proximate the drain region. An insulating element isolates the first solid electrolyte cell from the second solid electrolyte cell. A first anode is electrically coupled to the first solid electrolyte cell. The first solid electrolyte cell is between the anode and the insulating layer. A second anode is electrically coupled to the second solid electrolyte cell. The second solid electrolyte cell is between the anode and the insulating layer. A gate contact layer is over the substrate and between the source region and drain region and in electrical connection with the first anode and the second anode. The gate contact layer is electrically coupled to a voltage source.11-26-2009
20090289242Phase Change Memory With Tapered Heater - An embodiment of the present invention includes a method of forming a nonvolatile phase change memory (PCM) cell. This method includes forming at least one bottom electrode; forming at least one phase change material layer on at least a portion of an upper surface of the bottom electrode; forming at least one heater layer on at least a portion of an upper surface of the phase change material layer; and shaping the heater layer into a tapered shape, such that an upper surface of the heater layer has a cross-sectional width that is longer than a cross-sectional width of a bottom surface of the heater layer contacting the phase change material layer.11-26-2009
20090294748Phase Change Memory Cell with Reduced Switchable Volume - A memory cell is fabricated by forming a dielectric layer and patterning a hole in the dielectric layer. Patterning the hole is accomplished at least in part by contacting the dielectric layer with a catalytic material in the presence of a reactant under conditions effective to remove those areas of the dielectric layer in contact with the catalytic material. A phase change feature is then formed in contact with the dielectric layer such that a portion of the phase change feature at least partially fills the hole in the dielectric layer. At least a portion of the patterned dielectric layer remains in the ultimate memory cell.12-03-2009
20120292584RESISTIVE MEMORY CELL - Semiconductor memory devices, resistive memory devices, memory cell structures, and methods of forming a resistive memory cell are provided. One example method of a resistive memory cell can include a number of dielectric regions formed between two electrodes, and a barrier dielectric region formed between each of the dielectric regions. The barrier dielectric region serves to reduce an oxygen diffusion rate associated with the dielectric regions.11-22-2012
20090008620Nonvolatile Memory Cells Employing a Transition Metal Oxide Layers as a Data Storage Material Layer and Methods of Manufacturing the Same - Non-volatile memory cells employing a transition metal oxide layer as a data storage material layer are provided. The non-volatile memory cells include a lower and upper electrodes overlapped with each other. A transition metal oxide layer pattern is provided between the lower and upper electrodes. The transition metal oxide layer pattern is represented by a chemical formula M01-08-2009
20110204309SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a semiconductor memory device includes a first interconnect, a second interconnect, a first fringe and a second fringe. The first interconnect is connected to a first memory cell. The second interconnect is connected to a second memory cell and is arranged at a first interval from the first interconnect in a first direction. The first fringe is formed on one end of the first interconnect. The second fringe is formed on one end of the second interconnect. The first fringe and the second fringe are arranged at the first interval in a second direction orthogonal to the first direction.08-25-2011
20110198554NON-VOLATILE MEMORY DEVICE - According to one embodiment, a non-volatile memory device includes a first wiring extending in a first direction, a second wiring extending in a second direction, and a variable resistance memory cell which is disposed at an intersection between the first wiring and the second wiring so as to be held between the first wiring and the second wiring and includes a variable resistive element and a rectifying element. In a space between the variable resistance memory cells adjacent to each other, at least a periphery of the variable resistive element is evacuated or filled with a gas.08-18-2011
20100270527PHASE-CHANGE MEMORY DEVICE AND METHOD OF MANUFACTURING THE PHASE-CHANGE MEMORY DEVICE - A phase-change memory device has a plurality of first wiring lines; a plurality of memory cells that are provided on the plurality of first wiring lines; a plurality of second wiring lines that are provided on the plurality of memory cells, respectively; and an interlayer insulating film that is formed between the plurality of first wiring lines and the plurality of second wiring lines and insulates the plurality of first wiring lines from the plurality of second wiring lines; wherein each of the memory cells includes a heat source element that is supplied with a current and generates heat and a phase-change element that is changed to an amorphous state or a crystalline state according to a cooling speed after being heated by the heat source element, a resistance value of the phase-change element varying with the change in the state, and wherein a void is formed between the two adjacent memory cells in the interlayer insulating film.10-28-2010
20090050867FEATURE FORMED BENEATH AN EXISTING MATERIAL DURING FABRICATION OF A SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEMS COMPRISING THE SEMICONDUCTOR DEVICE - A method for forming a first feature within a dielectric, metal, or semiconductor material and, optionally, under an existing second feature, comprises the use of an anisotropic etch, the formation of a spacer used to prevent lateral etching, a subsequent isotropic etch to form a hollow opening, and the formation of one or more conductive and/or dielectric materials within the opening. The anisotropic etch may expose a conductive feature to which contact is to be made, depending on the particular use of the inventive method. An inventive structure is also described.02-26-2009
20080283813Semiconductor memory device and method of manufacturing the same - A semiconductor memory device includes first conductive lines on a substrate, an interlayer insulating layer with a plurality of via holes on the substrate, second conductive lines on the interlayer insulating layer, and a resistive memory material in the via holes and electrically connected to the first and second conductive lines, the resistive memory material having a vertically non-uniform specific resistance profile with respect to the substrate.11-20-2008
20080283812PHASE-CHANGE MEMORY ELEMENT - A phase-change memory element. The phase-change memory comprises first and second electrodes. A phase-change material layer is formed between the first and second electrodes. And a carbon-doped oxide dielectric layer is formed to surround the phase-change material layer, wherein the first electrode electrically connects the second electrodes via the phase-change material layer.11-20-2008
20080272354PHASE CHANGE DIODE MEMORY - An integrated circuit having a memory includes a semiconductor line and a phase change element contacting the semiconductor line. The phase change element provides a storage location. A diode junction is formed at the interface between the semiconductor line and the phase change element.11-06-2008
20130119336Forced Ion Migration for Chalcogenide Phase Change Memory Device - Non-volatile memory devices with two stacked layers of chalcogenide materials comprising the active memory device have been investigated for their potential as phase-change memories. The devices tested included GeTe/SnTe, Ge05-16-2013
20130119337RESISTIVE-SWITCHING DEVICE CAPABLE OF IMPLEMENTING MULTIARY ADDITION OPERATION AND METHOD FOR MULTIARY ADDITION OPERATION - A resistive-switching random access memory device includes a memory cell disposed between a bit line and a word line, the memory cell having a resistive-switching element (05-16-2013
20130119339MEMORY CELL WITH POST DEPOSITION METHOD FOR REGROWTH OF CRYSTALLINE PHASE CHANGE MATERIAL - A phase change memory cell with substantially void free crystalline phase change material. An example memory cell includes a substrate and a bottom electrode carried by the substrate. The bottom electrode is a thermal conductor. A phase change layer includes phase change material. The phase change layer is void free within a switching region when the phase change material is in a crystalline phase. A top electrode is positioned over the phase change layer.05-16-2013
20110006275NON-VOLATILE RESISTIVE SENSE MEMORY - A resistive sense memory cell includes a layer of crystalline praseodymium calcium manganese oxide and a layer of amorphous praseodymium calcium manganese oxide disposed on the layer of crystalline praseodymium calcium manganese oxide forming a resistive sense memory stack. A first and second electrode are separated by the resistive sense memory stack. The resistive sense memory cell can further include an oxygen diffusion barrier layer separating the layer of crystalline praseodymium calcium manganese oxide from the layer of amorphous praseodymium calcium manganese oxide a layer. Methods include depositing an amorphous praseodymium calcium manganese oxide disposed on the layer of crystalline praseodymium calcium manganese oxide forming a resistive sense memory stack.01-13-2011
20080258125Resistive memory cell fabrication methods and devices - A phase change memory cell and methods of fabricating the same are presented. The memory cell includes a variable resistance region and a top and bottom electrode. The shapes of the variable resistance region and the top electrode are configured to evenly distribute a current with a generally hemispherical current density distribution around the first electrode.10-23-2008
20100140578NON VOLATILE MEMORY CELLS INCLUDING A COMPOSITE SOLID ELECTROLYTE LAYER - Programmable metallization cells (PMC) that include a first electrode; a solid electrolyte layer including clusters of high ion conductive material dispersed in a low ion conductive material; and a second electrode, wherein either the first electrode or the second electrode is an active electrode, and wherein the solid electrolyte layer is disposed between the first electrode and the second electrode. Methods of forming them are also included herein.06-10-2010
20100140579SILVER-SELENIDE/CHALCOGENIDE GLASS STACK FOR RESISTANCE VARIABLE MEMORY - The invention is related to methods and apparatus for providing a resistance variable memory element with improved data retention and switching characteristics. According to an embodiment of the invention a resistance variable memory element is provided having at least one silver-selenide layer in between glass layers, wherein at least one of the glass layers is a chalcogenide glass, preferably having a Ge06-10-2010
20090261312INTEGRATED CIRCUIT INCLUDING AN ARRAY OF LOW RESISTIVE VERTICAL DIODES AND METHOD - An integrated circuit including an array of low resistive vertical diodes and method. One embodiment provides an array of diodes at least partially formed in a substrate for selecting one of a plurality of memory cells. A diode is coupled to a word line. The word line includes a straight-lined portion and protrusions. The diode includes an active area located between two adjacent protrusions.10-22-2009
20090184305Resistive memory devices and methods of manufacturing the same - A resistive memory device includes a first electrode and a first insulation layer arranged on the first electrode. A portion of the first electrode is exposed through a first hole in the first insulation layer. A first variable resistance layer contacts the exposed portion of the first electrode and extends on the first insulation layer around the first hole. A first switching device electrically connects to the first resistive switching layer.07-23-2009
20100200828SOLID MEMORY - In one embodiment of the present invention, recording and erasing of data in PRAM have hitherto been performed based on a change in physical characteristics caused by primary phase-transformation of a crystalline state and an amorphous state of a chalcogen compound including Te which serves as a recording material. Since, however, a recording thin film is formed of a polycrystal but not a single crystal, a variation in resistance values occurs and a change in volume caused upon phase-transition has placed a limit on the number of times of readout of record. In one embodiment, the above problem is solved by preparing a solid memory having a superlattice structure of thin films including Ge and thin films including Sb. The solid memory can realize the number of times of repeated recording and erasing of 1008-12-2010
20120068141SILVER-SELENIDE/CHALCOGENIDE GLASS STACK FOR RESISTANCE VARIABLE MEMORY - The invention is related to methods and apparatus for providing a resistance variable memory element with improved data retention and switching characteristics. According to an embodiment of the invention a resistance variable memory element is provided having at least one silver-selenide layer in between glass layers, wherein at least one of the glass layers is a chalcogenide glass, preferably having a Ge03-22-2012
20120068140SWITCHABLE ELECTRONIC DEVICE AND METHOD OF SWITCHING SAID DEVICE - A switchable electronic device comprises a hole blocking layer and a layer comprising a conductive material between first and second electrodes, wherein the conductivity of the device may be irreversibly switched upon application of a current having a current density of less than or equal to 100 A cm03-22-2012
20120068139MAGNETORESISTIVE ELEMENT AND MAGNETIC MEMORY - A magnetoresistive element according to an embodiment includes: a first ferromagnetic layer having an axis of easy magnetization in a direction perpendicular to a film plane; a second ferromagnetic layer having an axis of easy magnetization in a direction perpendicular to a film plane; a nonmagnetic layer placed between the first ferromagnetic layer and the second ferromagnetic layer; a first interfacial magnetic layer placed between the first ferromagnetic layer and the nonmagnetic layer; and a second interfacial magnetic layer placed between the second ferromagnetic layer and the nonmagnetic layer. The first interfacial magnetic layer includes a first interfacial magnetic film, a second interfacial magnetic film placed between the first interfacial magnetic film and the nonmagnetic layer and having a different composition from that of the first interfacial magnetic film, and a first nonmagnetic film placed between the first interfacial magnetic film and the second interfacial magnetic film.03-22-2012
20120068138OPTICAL STORAGE MEDIUM COMPRISING TWO NONLINEAR LAYERS - The optical storage medium comprises a substrate layer, a data layer arranged on the substrate layer, a first nonlinear layer with a first super-resolution structure arranged above the data layer, and a second nonlinear layer with a second super-resolution structure arranged above the first nonlinear layer, the first nonlinear layer comprising a material having an increased reflectivity when irradiated with a laser beam and the second nonlinear layer comprising a material showing a transparency when irradiated with a laser beam. The first nonlinear layer comprises in particular a semiconductor material of one of the III-V semiconductor family having a low band-gap. And the second nonlinear layer comprises in particular a phase change material, for example SbTe or AIST.03-22-2012
20120068137SWITCHING DEVICE AND MEMORY DEVICE INCLUDING THE SAME - A switching device includes a first electrode, a bipolar tunneling layer, and a second electrode. The bipolar tunneling layer is formed on the first electrode and includes a plurality of dielectric layers having different dielectric constants. The second electrode is formed on the bipolar tunneling layer.03-22-2012
20090026433MULTISTATE NONVOLATILE MEMORY ELEMENTS - Multistate nonvolatile memory elements are provided. The multistate nonvolatile memory elements contain multiple layers. Each layer may be based on a different bistable material. The bistable materials may be resistive switching materials such as resistive switching metal oxides. Optional conductor layers and current steering elements may be connected in series with the bistable resistive switching metal oxide layers.01-29-2009
20090321705PHASE CHANGE MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A phase change memory device includes a semiconductor substrate, a first conductive pattern formed on the semiconductor substrate, a second conductive pattern contacting an upper surface of the first conductive pattern and having a diameter less than a diameter of the first conductive pattern, and a phase change material layer contacting the second conductive pattern.12-31-2009
20110140065MEMORY ELEMENT AND MEMORY DEVICE - The present invention provides a memory element and a memory device realizing reduced variations in resistance values in an initial state or erase state of a plurality of memory elements and capable of retaining the resistance value in a write/erase state for writing/erasing operations of a plurality of times. The memory element includes a first electrode, a memory layer, and a second electrode in order. The memory layer has: an ion source layer containing at least one of chalcogen elements of tellurium (Te), sulfur (S), and selenium (Se) and at least one metal element selected from copper (Cu), silver (Ag), zinc (Zn), and zirconium (Zr); and two or more high-resistance layers having a resistance value higher than that of the ion source layer and having different compositions.06-16-2011
20090072214PHASE-CHANGE MEMORY CELL AND METHOD OF FABRICATING THE PHASE-CHANGE MEMORY CELL - A memory cell (and method of fabricating the memory cell) includes a stencil layer having a first opening, a phase-change material layer formed on a first electrode layer, and an electrically conductive layer formed on the first electrode layer, the electrically conductive layer having a pillar-shaped portion which is formed on the phase-change material layer and fills the first opening.03-19-2009
20090050868Nonvolatile Memory Element - Provided is a material composition which allows a nonvolatile memory element made of a perovskite-type transition metal oxide having the CER effect to be formed of three elements, which comprises an electric conductor having a shallow work function or a small electronegativity, such as Ti, as an electrode and a rare earth-copper oxide comprising one type of rare earth element, copper and oxygen, such as La02-26-2009
20090050869Phase-change random access memory and method of manufacturing the same - Provided is a phase-change random access memory (PRAM). The PRAM includes a bottom electrode, a bottom electrode contact layer, which is formed on one area of the bottom electrode, and an insulating layer, which is formed on a side of the bottom electrode contact layer, a phase-change layer, which is formed on the bottom electrode contact layer and the insulating layer and is formed of a phase-change material having a crystallization temperature between 100° C. and 150° C., and a top electrode, which is formed on the phase-change layer.02-26-2009
20090050871SEMICONDUCTOR DEVICE AND PROCESS FOR PRODUCING THE SAME - A semiconductor device having a phase-change memory cell comprises an interlayer dielectric film formed of, for example, SiOF formed on a select transistor formed on a main surface of a semiconductor substrate, a chalcogenide material layer formed of, for example, GeSbTe extending on the interlayer dielectric film, and a top electrode formed on the chalcogenide material layer. A fluorine concentration in an interface between the interlayer dielectric film and the chalcogenide material layer is higher than a fluorine concentration in an interface between the chalcogenide material layer and the top electrode.02-26-2009
20090050870INTEGRATED CIRCUIT INCLUDING MEMORY ELEMENT WITH SPATIALLY STABLE MATERIAL - An integrated circuit includes a heater element serving as a first electrode, a second electrode, a memory element comprising resistance changing material coupled to the heater element and to the second electrode, and a diffusion compensation region coupled to the heater element and to the resistance changing material. The diffusion compensation region includes a surplus of at least one diffusible species present in the memory element and provides at least one diffusible species to the memory element.02-26-2009
20110140066Phase Change Memory with Various Grain Sizes - A memory device includes a phase change element, which further includes a first phase change layer having a first grain size; and a second phase change layer over the first phase change layer. The first and the second phase change layers are depth-wise regions of the phase change element. The second phase change layer has a second average grain size different from the first average grain size.06-16-2011
20090101880PHASE CHANGE MEMORY DEVICES AND METHODS FOR FABRICATING THE SAME - An exemplary memory device includes a first dielectric layer with a first conductive contact therein. A phase change material (PCM) is disposed on top of the first dielectric layer and provided with an insulating layer integrally on a top surface of the PCM. A first electrode is disposed over the first dielectric layer and covered a portion of the first conductive contact and the insulating layer in a first direction, contacting to the first conductive contact and a first side of the PCM. A second electrode is disposed over the first dielectric layer and covered a portion of the insulating layer in a second direction, contacting to a second side of the PCM. A second dielectric layer is disposed over the first dielectric layer to cover the first electrode, the second electrode, the insulating layer and the PCM, including a second conductive contact connected to the second electrode.04-23-2009
20090200533Resistive Memory Element and Method of Fabrication - An integrated circuit including a memory cell and a method of manufacturing the integrated circuit are described. The memory cell includes a buried gate select transistor and a resistive memory element coupled to the buried gate select transistor. The resistive memory element stores information based on a resistivity of the resistive memory element.08-13-2009
20120104342Memristive Device - A memristive device includes a first electrode, a second electrode crossing the first electrode at a non-zero angle, and an active region disposed between the first and second electrodes. The active region has a controlled defect profile throughout its thickness.05-03-2012
20120104341MEMORY CELL DEVICE AND METHOD OF MANUFACTURE - According to one embodiment of the present invention, a solid state electrolyte memory cell includes a cathode, an anode and a solid state electrolyte. The anode includes an intercalating material and first metal species dispersed in the intercalating material.05-03-2012
20120104340NONVOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - A nonvolatile memory device includes: a substrate; a stacked structure member including a plurality of dielectric films and a plurality of electrode films alternately stacked on the substrate and including a through-hole penetrating through the plurality of the dielectric films and the plurality of the electrode films in a stacking direction of the plurality of the dielectric films and the plurality of the electrode films; a semiconductor pillar provided in the through-hole; and a charge storage layer provided between the semiconductor pillar and each of the plurality of the electrode films. At least one of the dielectric films includes a film generating one of a compressive stress and a tensile stress, and at least one of the electrode films includes a film generating the other of the compressive stress and the tensile stress.05-03-2012
20120104339PHASE CHANGE MEMORY CELL - On a first structure having a first dielectric layer, a second dielectric layer, and a third dielectric layer a crown is formed through the third dielectric layer and the second dielectric layer. A fourth dielectric layer is deposited over the first structure and thereby is over the crown. A portion of the fourth dielectric layer is removed to form a first spacer having a remaining portion of the fourth dielectric layer. A portion of the third electric layer is also removed during the removal of the portion the fourth dielectric layer, resulting in a second spacer having a remaining portion of the third dielectric layer. A second structure is thereby formed. A phase change material layer is deposited over the second structure. An electrode layer is deposited over the phase change layer. Portions of the electrode layer and the phase change layer are removed by a chemical-mechanical-polishing process to form a phase change region having a remaining portion of the phase change layer and to form an electrode region having a remaining portion of the electrode layer.05-03-2012
20090250678NONVOLATILE MEMORY APPARATUS, NONVOLATILE MEMORY ELEMENT, AND NONVOLATILE ELEMENT ARRAY - A nonvolatile memory apparatus comprises a first electrode (10-08-2009
20090256128Nonvolatile data storage, semicoductor memory device including nonvolatile data storage and method of forming the same - A data storage and a semiconductor memory device including the same are provided, the data storage including a lower electrode, a first discharge prevention layer stacked on the lower electrode, a phase-transition layer on the first discharge prevention layer, a second discharge prevention layer stacked on the phase-transition layer, and an upper electrode stacked on the second discharge prevention layer. The phase transition layer includes oxygen and exhibits two different resistance characteristics depending on whether an insulating property thereof changed. The first and second discharge prevention layers block discharge of the oxygen from the phase transition layer.10-15-2009
20110227019NON-VOLATILE MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - According to one embodiment, a non-volatile memory device is formed as described below. First, a wiring material layer, which configures a part of a wiring of an element, is stacked above an element layer, the wiring material layer is processed in a predetermined shape, and the element layer is etched using the wiring material layer as a mask. Next, an insulation layer is embedded between etched patterns, and the insulation layer is removed using the wiring material layer as a stopper. Then, a wiring layer, which is in contact with the wiring material layer, is formed on the insulation layer from which the wiring material layer is exposed.09-22-2011
20090242866Phase change memory device and method of fabricating the same - A semiconductor device includes an insulating layer on a substrate, a first electrode in the insulating layer having a first upper surface and a second upper surface, a second electrode in the insulating layer spaced apart from the first electrode by a first distance and having a third upper surface and a fourth upper surface, the third upper surface being disposed at a substantially same level as the first upper surface, and the fourth upper surface being disposed at a substantially same level as the second upper surface, a first phase change material pattern covering a part of the first upper surface of the first electrode, and a second phase change material pattern covering a part of the third upper surface of the second electrode, wherein an interface region between the second phase change pattern and the second electrode is spaced apart from an interface region between the first phase change pattern and the first electrode by a second distance greater than the first distance.10-01-2009
20090242865MEMORY ARRAY WITH DIODE DRIVER AND METHOD FOR FABRICATING THE SAME - A method of fabricating a memory array. The method begins with a structure, generally composed of dielectric fill material and having conductive lines formed at its lower portion, and a sacrificial layer formed on its upper surface. Diodes are formed in the fill material, each diode having a lightly-doped first layer of the same conductivity type as the conductive lines; a heavily doped second layer of opposite conductivity type; and a conductive cap. Self-aligned vias are formed over the diodes. Self-aligned, and self-centered spacers in the self-aligned vias define pores that expose the conductive cap. Memory material is deposited within the pores, the memory material making contact with the conductive cap. A top electrode is formed in contact with the memory material.10-01-2009
20090250679PHASE-CHANGE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A phase-change memory device includes a lower electrode; and at least two phase-change memory cells sharing the lower electrode. Another phase-change memory device includes a heating layer having a smaller contact area with a phase-change material layer and a greater contact area with a PN diode structure.10-08-2009
20100148141NON-VOLATILE PROGRAMMABLE DEVICE INCLUDING PHASE CHANGE LAYER AND FABRICATING METHOD THEREOF - Provided is a non-volatile programmable device including a first terminal, a first threshold switching layer connected to part of the first terminal, a phase change layer connected to the first threshold switching layer, a second threshold switching layer connected to the phase change layer, a second terminal connected to the second threshold switching layer, and third and fourth terminals respectively connected to a side portion of the phase change layer and the other side portion opposite to the side portion of the phase change layer.06-17-2010
20090256127Compounds for Depositing Tellurium-Containing Films - Disclosed herein are tellurium metal-organic precursors and methods for depositing tellurium-containing films on a substrate.10-15-2009
20120193596SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - In accordance with an embodiment, a semiconductor device includes a functional film, first and second trenches, and first and second insulating films. The functional film comprises first and second areas. The first trench is provided in the first area of the functional film and has a first width. The second trench is provided in the second area of the functional film and has a second width larger than the first width. The first insulating film is formed from a polymeric material as a precursor to fill the first trench. The second insulating film has a diameter larger than the first width and is formed from particulates and the polymeric material as precursors. The particulates fill the second trench. The polymeric material fills spaces between the particulates in the second trench and also fills gaps between the particulates and the second trench.08-02-2012
20120193595COMPOSITE TARGET SPUTTERING FOR FORMING DOPED PHASE CHANGE MATERIALS - A layer of phase change material with silicon or another semiconductor, or a silicon-based or other semiconductor-based additive, is formed using a composite sputter target including the silicon or other semiconductor, and the phase change material. The concentration of silicon or other semiconductor is more than five times greater than the specified concentration of silicon or other semiconductor in the layer being formed. For silicon-based additive in GST-type phase change materials, sputter target may comprise more than 40 at % silicon. Silicon-based or other semiconductor-based additives can be formed using the composite sputter target with a flow of reactive gases, such as oxygen or nitrogen, in the sputter chamber during the deposition.08-02-2012
20080308783Memory devices and methods of manufacturing the same - Memory devices and methods of manufacturing the same are provided. In a memory device, a memory-switch structure is formed between a first and second electrode. The memory-switch structure includes a memory resistor and a switch structure. The switch structure controls current supplied to the memory resistor. A memory region of the memory resistor and a switch region of the switch structure are different from each other.12-18-2008
20100264394SEMICONDUCTOR MEMORY AND METHOD OF MANUFACTURING THE SAME - Disclosed herein is a semiconductor memory including: a first MOS transistor having two diffusion layers formed in a semiconductor substrate; a second MOS transistor which is formed in the semiconductor substrate and has one of the two diffusion layers of the first MOS transistor as a common diffusion layer for the first and second MOS transistors; and a variable resistance element which is formed between side wall insulating films formed at respective side walls of a first gate electrode of the first MOS transistor and a second gate electrode of the second MOS transistor and is connected to the common diffusion layer.10-21-2010
20100264395PHASE CHANGE MEMORY STRUCTURES AND METHODS - Methods, devices, and systems associated with phase change memory structures are described herein. One or more embodiments of the present disclosure can reduce thermal crosstalk associated with phase change memory cells, which can provide various benefits including improved data reliability and retention and decreased read and/or write times, among various other benefits. One or more embodiments can reduce the number of processing steps associated with providing local interconnects to phase change memory arrays.10-21-2010
20090315010THREE-TERMINAL CASCADE SWITCH FOR CONTROLLING STATIC POWER CONSUMPTION IN INTEGRATED CIRCUITS - A three-terminal switching device for use in integrated circuit devices, including a phase change material (PCM) disposed in contact between a first terminal and a second terminal; a heating device disposed in direct electrical contact between said second terminal and a third terminal, said heating device positioned proximate said PCM, and configured to switch the conductivity of a transformable portion of said PCM between a lower resistance crystalline state and a higher resistance amorphous state; and an insulating layer configured to electrically isolate said heater from said PCM material, and said heater from said first terminal.12-24-2009
20090072213Programmable Via Structure for Three Dimensional Integration Technology - A programmable link structure for use in three dimensional integration (3DI) semiconductor devices includes a via filled at least in part with a phase change material (PCM) and a heating device proximate the PCM. The heating device is configured to switch the conductivity of a transformable portion of the PCM between a lower resistance crystalline state and a higher resistance amorphous state. Thereby, the via defines a programmable link between an input connection located at one end thereof and an output connection located at another end thereof03-19-2009
20090072210SWITCHING DEVICE - A switching device contains a thin film containing an organic material disposed between at least two electrodes, and the organic material is, for example, a triphenylamine compound represented by the general formula (I):03-19-2009
20100155684NON-VOLATILE MEMORY DEVICE AND METHOD OF FORMING THE SAME - Provided are a non-volatile memory device and a method of forming the non-volatile memory device. The non-volatile memory device includes a substrate, a lower electrode on the substrate, a diffusion barrier preventing the diffusion of a space charge on the lower electrode, a charge storage layer having a space charge limited characteristic on the diffusion barrier, and an upper electrode on the charge storage layer.06-24-2010
20100258776Shallow Trench Type Quadri-Cell of Phase-Change Random Access Memory (PRAM) - A method of forming a phase-change random access memory (PRAM) cell and PRAM arrangement, and embodiments of phase-change random access memory (PRAM) cells and PRAM arrangements are disclosed. A phase-change random access memory (PRAM) cell includes a bottom electrode, a heater resistor coupled to the bottom electrode, a phase change material (PCM) coupled to the heater resistor, and a top electrode coupled to the phase change material. An active region between the heater resistor and the phase change material is defined by a thickness of the heater resistor.10-14-2010
20100012914CARBON-BASED RESISTIVITY-SWITCHING MATERIALS AND METHODS OF FORMING THE SAME - Methods of forming memory devices, and memory devices formed in accordance with such methods, are provided, the methods including forming a via above a first conductive layer, forming a nonconformal carbon-based resistivity-switchable material layer in the via and coupled to the first conductive layer; and forming a second conductive layer in the via, above and coupled to the nonconformal carbon-based resistivity-switchable material layer. Numerous other aspects are provided.01-21-2010
20100181545NON-VOLATILE MEMORY CELL AND FABRICATION METHOD THEREOF - A non-volatile memory cell and the fabrication method thereof are provided. The non-volatile memory cell comprises a top electrode, a bottom electrode and an oxide layer disposed between the top electrode and the bottom electrode. The oxide layer comprises a relatively low oxygen content layer adjacent to the bottom electrode, a relatively high oxygen content layer adjacent to the top electrode, and a transition layer disposed between the relatively high and the relatively low oxygen content layers. The transition layer has an oxygen concentration within a range between those of the relatively high and the relatively low oxygen content layers.07-22-2010
20100163824MODULATION OF RESISTIVITY IN CARBON-BASED READ-WRITEABLE MATERIALS - In a first aspect, a method of forming a memory cell is provided that includes (1) forming a metal-insulator-metal (“MIM”) stack above a substrate, the MIM stack including a carbon-based switching material having a resistivity of at least 1×1007-01-2010
20100193758PROGRAMMABLE METALLIZATION MEMORY CELL WITH PLANARIZED SILVER ELECTRODE - Programmable metallization memory cells having a planarized silver electrode and methods of forming the same are disclosed. The programmable metallization memory cells include a first metal contact and a second metal contact, an ion conductor solid electrolyte material is between the first metal contact and the second metal contact, and either a silver alloy doping electrode separates the ion conductor solid electrolyte material from the first metal contact or the second metal contact, or a silver doping electrode separates the ion conductor solid electrolyte material from the first metal contact. The silver electrode includes a silver layer and a metal seed layer separating the silver layer from the first metal contact.08-05-2010
20130214232NONVOLATILE MEMORY DEVICE USING A VARISTOR AS A CURRENT LIMITER ELEMENT - Embodiments of the invention include a method of forming a nonvolatile memory device that contains a resistive switching memory element that has improved device switching performance and lifetime, due to the addition of a current limiting component disposed therein. The electrical properties of the current limiting component are configured to lower the current flow through the variable resistance layer during the logic state programming steps by adding a fixed series resistance in the resistive switching memory element of the nonvolatile memory device. In some embodiments, the current limiting component comprises a varistor that is a current limiting material disposed within a resistive switching memory element in a nonvolatile resistive switching memory device. Typically, resistive switching memory elements may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices, such as digital cameras, mobile telephones, handheld computers, and music players.08-22-2013
20130214233CONDUCTIVE METAL OXIDE STRUCTURES IN NON VOLATILE RE WRITABLE MEMORY DEVICES - A memory cell including a memory element comprising an electrolytic insulator in contact with a conductive metal oxide (CMO) is disclosed. The CMO includes a crystalline structure and can comprise a pyrochlore oxide, a conductive binary oxide, a multiple B-site perovskite, and a Ruddlesden-Popper structure. The CMO includes mobile ions that can be transported to/from the electrolytic insulator in response to an electric field of appropriate magnitude and direction generated by a write voltage applied across the electrolytic insulator and CMO. The memory cell can include a non-ohmic device (NOD) that is electrically in series with the memory element. The memory cell can be positioned between a cross-point of conductive array lines in a two-terminal cross-point memory array in a single layer of memory or multiple vertically stacked layers of memory that are fabricated over a substrate that includes active circuitry for data operations on the array layer(s).08-22-2013
20100163821VERTICAL DIODE AND METHOD FOR MANUFACTURING SAME AND SEMICONDUCTOR MEMORY DEVICE - In a vertical diode, an N07-01-2010
20100258778RESISTIVE MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A resistive memory device includes a bottom electrode, a resistive layer formed over the bottom electrode and having a structure in which a first resistive layer having an amorphous phase and a second resistive layer having a polycrystal phase are sequentially stacked, and a top electrode formed over the second resistive layer.10-14-2010
20100258779NONVOLATILE MEMORY DEVICE AND MANUFACTURING MEHTOD THEREOF - A nonvolatile memory device of the present invention includes a substrate (10-14-2010
20100012913Multi-level phase change random access memory device - A multi-level phase change random access memory device includes a first electrode, a second electrode, and a phase change material disposed between the first electrode and the second electrode. The multi-level phase change random access memory device also includes a variable bias source coupled to the first electrode. The variable bias source provides a respective bias applied at the first electrode to form a portion of the phase change material to have one of an amorphous state and different crystal states for storing multi-bits data.01-21-2010
20100012912ELECTRONIC DEVICES INCLUDING CARBON-BASED FILMS HAVING SIDEWALL LINERS, AND METHODS OF FORMING SUCH DEVICES - Methods in accordance with aspects of this invention form microelectronic structures in accordance with other aspects of this invention, such as non-volatile memories, that include (1) a layerstack having a pattern including sidewalls, the layerstack comprising a resistivity-switchable layer disposed above and in contact with a bottom electrode, and a top electrode disposed above and in contact with the resistivity-switchable layer; and (2) a dielectric sidewall liner in contact with the sidewalls of the layerstack; wherein the resistivity-switchable layer includes a carbon-based material, and the dielectric sidewall liner includes an oxygen-poor dielectric material. Numerous additional aspects are provided.01-21-2010
20100019217PHASE-CHANGE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A phase-change memory device includes a semiconductor substrate, a bit line and a word line arranged on the semiconductor substrate to intersect each other, and a phase-change material strip interposed between the bit line and the word line and extending lengthwise in a direction that is substantially parallel to at least a portion of the word line.01-28-2010
20100176364ELECTRONIC DEVICE, AND METHOD OF MANUFACTURING AN ELECTRONIC DEVICE - An electronic device (07-15-2010
20100176363VARIABLE RESISTANCE ELEMENT AND SEMICONDUCTOR DEVICE PROVIDED WITH THE SAME - A variable resistance element includes: a first electrode; a variable resistance material layer formed on the first electrode; and a second electrode formed on this variable resistance material layer. The variable resistance material layer is made of an uncrystallized material including a transition metal oxide, which is an oxide of a transition metal M07-15-2010
20100176362POLYSILICON PLUG BIPOLAR TRANSISTOR FOR PHASE CHANGE MEMORY - Memory devices and methods for manufacturing are described herein. A memory device described herein includes a plurality of memory cells. Memory cells in the plurality of memory cells comprise respective bipolar junction transistors and memory elements. The bipolar junction transistors are arranged in a common collector configuration and include an emitter comprising doped polysilicon having a first conductivity type, the emitter contacting a corresponding word line in a plurality of word lines to define a pn junction. The bipolar junction transistors include a portion of the corresponding word line underlying the emitter acting as a base, and a collector comprising a portion of the single-crystalline substrate underlying the base.07-15-2010
20100237311NONVOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A nonvolatile memory device according to an embodiment of the present invention includes: a first wire embedded in a first wiring groove extending in an X direction formed in a first interlayer insulating film; a second interlayer insulating film formed above the first interlayer insulating film; a second wire embedded in a second wiring groove extending in a Y direction formed in the second interlayer insulating film; and a variable resistance memory cell including a variable resistive layer and a rectifying layer arranged to be held between the first wire and the second wire in a position where the first wire and the second wire intersect. A dimension in a plane perpendicular to a thickness direction of the variable resistance memory cell is specified by widths of the first and second wires.09-23-2010
20100213431Treated Chalcogenide Layer for Semiconductor Devices - A phase change memory and a method of manufacture are provided. The phase change memory includes a layer of phase change material treated to increase the hydrophobic nature of the phase change material. The hydrophobic nature of the phase change material improves adhesion between the phase change material and an overlying mask layer. The phase change material may be treated, for example, with a plasma comprising N08-26-2010
20100252794COMPOSITE FILM FOR PHASE CHANGE MEMORY DEVICES - A phase change memory device and a method of manufacture are provided. The phase change memory device includes a phase change layer electrically coupled to a top electrode and a bottom electrode, the phase change layer comprising a phase change material. A mask layer is formed overlying the phase change layer. A first sealing layer is formed overlying the mask layer, and a second sealing layer is formed overlying the first sealing layer.10-07-2010
20100252795Phase change memory device - Provided is a phase change memory device and a method of manufacturing the phase change memory device. In the phase change memory device, since a flat surface of a buffer pattern and a lower electrode are stably in contact with each other in a center of a recess, a resistance of a contact surface between the lower electrode and the buffer pattern can be minimized and thereby the phase change memory device can be operated by a small current. Since a method of manufacturing the phase change memory device needs one time etching process to form a recess exposing a semiconductor substrate to an insulating layer until forming a lower electrode after forming a device isolation layer, it is very economical.10-07-2010
20100237313NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A nonvolatile semiconductor memory device of the present invention includes a substrate (09-23-2010
20100237312Nonvolatile memory device - The nonvolatile memory device includes at least one pair of first electrode lines, at least one device structure disposed between the at least one pair of first electrode lines and a dielectric layer disposed between the at least one device structure and the at least one pair of first electrode lines. The at least one device structure includes a second electrode line including a first conductive type semiconductor, a resistance changing material layer adjacent to the second electrode line, a channel adjacent to the resistance changing material layer and including a second conductive type semiconductor different from the first conductive type semiconductor and a third electrode line adjacent to the channel and including the first conductive type semiconductor.09-23-2010
20100243980NONVOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING NONVOLATILE MEMORY DEVICE - A nonvolatile memory device includes: a first interconnection extending in a first direction; a second interconnection extending in a second direction nonparallel to the first direction; and a memory layer placed between the first interconnection and the second interconnection and reversibly transitioning between a first state and a second state by a current supplied via the first interconnection and the second interconnection. A cross section parallel to the first and the second direction of the memory layer decreases toward the second interconnection.09-30-2010
20100219391LAYERED RESISTANCE VARIABLE MEMORY DEVICE AND METHOD OF FABRICATION - The invention is related to methods and apparatus for providing a resistance variable memory element with improved data retention and switching characteristics. According to one embodiment of the invention, a resistance variable memory element is provided having at least one silver-selenide layer in between two glass layers, wherein at least one of the glass layers is a chalcogenide glass, preferably having a Ge09-02-2010
20100001248PHASE-CHANGE MEMORY CELL WITH A PATTERNED LAYER - A phase-change-material memory cell is provided. The cell comprises at least one patterned layer of a phase-change material, and is characterized in that this patterned layer comprises at least two regions having different resistivities. If the resistivity of the phase-change material is higher in a well-defined area with limited dimensions (“hot spot”) than outside this area, then, for a given current flow between the electrodes, advantageously more Joule heat will be generated within this area compared to the area of the phase-change material where the resistivity is lower.01-07-2010
20100001249Semiconductor device enabling further microfabrication - A semiconductor device includes a plurality of MOS transistors and wiring connected to a source electrode or a drain electrode of the plurality of MOS transistors and, the wiring being provided in the same layer as the source electrode and the drain electrode in a substrate, or in a position deeper than a surface of the substrate.01-07-2010
20110006277INFORMATION RECORDING AND REPRODUCING DEVICE - According to one embodiment, an information recording and reproducing device includes a first layer, a second layer and a recording layer. The recording layer is provided between the first layer and the second layer and being capable of reversibly changing between a first state having a first resistance and a second state having a second resistance higher than the first resistance by a current supplied via the first layer and the second layer. The recording layer includes a first compound layer and an insulating layer. The first compound layer contains a first compound. The first compound includes a first cation element and a second cation element of a type different from the first cation element. The insulating layer contains a third compound, and the third compound includes an element selected from group 1 to 4 elements and group 12 to 17 elements in the periodic table.01-13-2011
20120193598Memory Devices and Formation Methods - A method includes forming an electrical insulator material over an integrated circuit having a metal-containing conductive interconnect and activating a dopant in a semiconductor material of a substrate to provide a doped region. The doped region provides a junction of opposite conductivity types. After activating the dopant, the substrate is bonded to the insulator material and at least some of the substrate is removed where bonded to the insulator material. After the removing, a memory cell is formed having a word line, an access diode, a state-changeable memory element containing chalcogenide phase change material, and a bit line all electrically connected in series, the access diode containing the junction as a p-n junction. A memory device includes an adhesion material over the insulator material and bonding the word line to the insulator material.08-02-2012
20120193597NONVOLATILE MEMORY DEVICE - According to one embodiment, a nonvolatile memory device includes a memory section. The memory section includes a first insulating layer, a second insulating layer and a pair of electrodes. The second insulating layer is formed on and in contact with the first insulating layer. The second insulating layer has at least one of a composition different from a composition of the first insulating layer and a phase state different from a phase state of the first insulating layer. The pair of electrodes is capable of passing a current through a current path along a boundary portion between the first insulating layer and the second insulating layer. An electrical resistance of the current path is changed by a voltage applied between the pair of electrodes.08-02-2012
20090250676LIQUID CRYSTALLINE ORGANIC SEMICONDUCTOR MATERIAL, AND SEMICONDUCTOR ELEMENT OR INFORMATION RECORDING MEDIUM USING THE SAME - An liquid crystalline organic semiconductor material practical as an organic semiconductor is provided. The material is a liquid crystal composition having a smectic liquid crystal phase. The liquid crystalline organic semiconductor material has a distyrylbenzene structure of formula (1). When heated to a temperature range for the smectic liquid crystal phase followed by being cooled, the material takes on a solid state as a result of phase transition from the smectic phase.10-08-2009
20100207091SWITCHING ELEMENT AND MANUFACTURING METHOD THEREOF - A switching element according to the present invention includes an ion-conducting layer, first electrode 08-19-2010
20100032638MEMORY CELL THAT INCLUDES A CARBON-BASED MEMORY ELEMENT AND METHODS OF FORMING THE SAME - Memory cells, and methods of forming such memory cells, are provided that include a carbon-based reversible resistivity switching material. In particular embodiments, methods in accordance with this invention form a memory cell by forming a carbon-based reversible resistance-switching material above a substrate, forming a carbon nitride layer above the carbon-based reversible resistance-switching material, and forming a barrier material above the carbon nitride layer using an atomic layer deposition process. Other aspects are also provided.02-11-2010
20100012911SWITCHING DEVICE - An objective of the present invention is to provide a switching device that shows two markedly different stable resistance characteristics reversibly and repetitively, and which is applicable to highly integrated nonvolatile memories.01-21-2010
20100193759REDUCED POWER CONSUMPTION PHASE CHANGE MEMORY AND METHODS FOR FORMING THE SAME - Memory cells for reduced power consumption and methods for forming the same are provided. A memory cell has a layer of phase change material. A first portion of the phase change material layer includes the programmable volume of the memory cell and its crystalline state has a higher resistivity than that of the crystalline state of a second portion of the phase change material layer.08-05-2010
20090114897PHASE CHANGE MEMORY DEVICE CAPABLE OF INCREASING SENSING MARGIN AND METHOD FOR MANUFACTURING THE SAME - A phase change memory device capable of increasing a sensing margin and a method for manufacturing the same. The phase change memory device includes a semiconductor substrate formed with a device isolation structure which defines active regions; first conductivity type impurity regions formed in surfaces of the active regions and having the shape of a line; a second conductivity type well formed in the semiconductor substrate at a position lower than the device isolation structure; a second conductivity type ion-implantation layer formed in the semiconductor substrate at a boundary between a lower end of the device isolation structure and the semiconductor substrate; a plurality of vertical PN diodes formed on the first conductivity type impurity regions; and phase change memory cells formed on the vertical PN diodes.05-07-2009
20090114896MEMORY DEVICE USING ABRUPT METAL-INSULATOR TRANSITION AND METHOD OF OPERATING THE SAME - Provided are a memory device that undergoes no structural phase change, maintains a uniform thin film, and can perform a high-speed switching operation, and a method of operating the same. The memory device includes a substrate, an abrupt MIT material layer, and a plurality of electrodes. The abrupt MIT material layer is disposed on the substrate and undergoes an abrupt metal-insulator transition by an energy change between electrons. The plurality of electrodes are brought into contact with the abrupt MIT material layer and are melted by heat to form a conductive path on the abrupt MIT material layer.05-07-2009
20080308781STRUCTURE AND PROCESS FOR A RESISTIVE MEMORY CELL WITH SEPARATELY PATTERNED ELECTRODES - Methods of making MIM structures and the resultant MIM structures are provided. The method involves forming a top electrode layer over a bottom electrode and an insulator on a substrate and forming a top electrode by removing portions of the top electrode layer. The bottom electrode, insulator, or combination thereof is isolated from the top electrode forming process, thereby mitigating damage to the resultant metal-insulator-metal structure. The resultant MIM structure can be a portion of a resistive memory cell.12-18-2008
20080308782SEMICONDUCTOR MEMORY STRUCTURES - A semiconductor structure includes a transistor over a substrate, the transistor comprising a gate and a contact region, which is adjacent to the gate and within the substrate. A first dielectric layer is over the contact region. A contact structure is within the first dielectric layer and over the contact region. A first electrode and a second electrode are within the first dielectric layer, wherein at least one of the first electrode and the second electrode is over the contact structure. The first electrode and second electrodes may be laterally or vertically separated. A phase change structure is disposed between the first electrode and the second electrode. The phase change structure includes at least one spacer within the first dielectric layer and a phase change material (PCM) layer over the spacer.12-18-2008
20090039329Integrated Circuit Having a Cell with a Resistivity Changing Layer - In an embodiment of the invention, an integrated circuit having a cell is provided. The cell may include a field effect transistor structure which includes a gate stack and a resistivity changing material structure disposed above the gate stack, wherein the resistivity changing material structure includes a resistivity changing material which is configured to change its resistivity in response to the application of an electrical voltage to the resistivity changing material structure.02-12-2009
20080272356FABRICATION OF PHASE CHANGE MEMORY ELEMENT WITH PHASE-CHANGE ELECTRODES USING CONFORMAL DEPOSITION - A phase change memory element with phase change electrodes, and method of making the same. Exemplary embodiments include a phase change bridge, including a bottom contact layer, a first insulating layer disposed on the bottom contact layer, a first phase change region disposed on the bottom contact layer adjacent the first insulating layer, a second phase change region disposed on the bottom contact layer adjacent the first insulating layer, wherein the first insulating layer thermally and electrically isolates the first and second phase change regions, and a third phase change region disposed on each of the first and second phase change regions, each of the third phase change regions isolated from one another by a conductor layer disposed on the first insulating layer.11-06-2008
20080265235NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A nonvolatile semiconductor memory device includes a first stacked structure in which a plurality of electrode layers are stacked on a substrate via insulating layers, a first resistance changing layer provided on a side surface of the first stacked structure and in contact with the first electrode layers, the first resistance changing layer having a resistance value changing on the basis of an applied voltage, a second electrode layer provided on a side surface of the first resistance changing layer, and a bit line provided on the first stacked structure and electrically connected to the second electrode layer.10-30-2008
20080265234Method of Forming Phase Change Memory Cell With Reduced Switchable Volume - A memory cell is fabricated by forming a dielectric layer and patterning a hole in the dielectric layer. Patterning the hole is accomplished at least in part by contacting the dielectric layer with a catalytic material in the presence of a reactant under conditions effective to remove those areas of the dielectric layer in contact with the catalytic material. A phase change feature is then formed in contact with the dielectric layer such that a portion of the phase change feature at least partially fills the hole in the dielectric layer. At least a portion of the patterned dielectric layer remains in the ultimate memory cell.10-30-2008
20100295009Phase Change Memory Cells Having Vertical Channel Access Transistor and Memory Plane - Memory devices are described along with methods for manufacturing. A memory device as described herein comprises a plurality of word lines overlying a plurality of bit lines, and a plurality of field effect transistors. Field effect transistors in the plurality of field effect transistors comprises a first terminal electrically coupled to a corresponding bit line in the plurality of bit lines, a second terminal overlying the first terminal, and a channel region separating the first and second terminals and adjacent a corresponding word line in the plurality of word lines. The corresponding word line acts as the gate of the field effect transistor. A dielectric separates the corresponding word line from the channel region. A memory plane comprises programmable resistance memory material electrically coupled to respective second terminals of the field effect transistors, and conductive material on the programmable resistance memory material and coupled to a common voltage.11-25-2010
20100295010 ELECTRONIC DEVICE COMPRISING A CONVERTIBLE STRUCTURE - An electronic device (11-25-2010
20130181181MIIIM DIODE HAVING LANTHANUM OXIDE - A MIIIM diode and method of fabricating are disclosed. In one aspect, the MIIIM diode comprises a first metal electrode, a first region comprising a first insulator material having an interface with the first metal electrode, a second region comprising a second insulator material having an interface with the first insulator material, a third region comprising a third insulator material having an interface with the second insulator material, and a second metal electrode having an interface with the third insulator material. At least one of the first, second, or third insulator materials is lanthanum oxide.07-18-2013
20090072211Resistive random access memory and method for manufacturing the same - A resistive random access memory including, an insulating layer, a hard mask layer, a bottom electrode, a memory cell and a top electrode is provided. The insulating layer is disposed on the bottom electrode. The insulating layer has a contact hole having a first width. The hard mask layer has an opening. A portion of the memory cell is exposed from the opening and has a second width smaller than the first width. The top electrode is disposed on the insulating layer and is coupled with the memory cell.03-19-2009
20100314598PHASE CHANGE MEMORY DEVICE HAVING BIT-LINE DISCHARGE BLOCK AND METHOD OF FABRICATING THE SAME - A phase change memory device capable of fully discharging bit lines, even while occupying a relatively small area, and a fabricating method thereof are presented. The phase change memory device includes a semiconductor substrate, a word line area, a discharge line area, a switching PN diode, a dummy PN diode, a phase change structure, and a bit line. The word line area is formed in a memory cell area of the semiconductor substrate. The discharge line area is formed in the bit-line discharge area of the semiconductor substrate. The switching PN diode is formed on the word line area. The dummy PN diode is formed on the discharge line area. The phase change structure is formed on the switching PN diode and is electrically connected to the switching diode. The bit line is electrically connected to the phase change structure and the dummy PN diode.12-16-2010
20110127484RESISTANCE CHANGE MEMORY AND MANUFACTURING METHOD THEREOF - According to one embodiment, a resistance change memory includes a first interconnect extending in a first direction, a second interconnect extending in a second direction intersecting with the first direction, and a cell unit which is provided between the first interconnect and the second interconnect. The cell unit includes a non-ohmic element and a memory element. The non-ohmic element includes a first silicon layer of an n-conductivity type and a conducting layer in contact with a first face of the first silicon layer. The memory element stores data according to a reversible change of a resistance state. The first silicon layer includes a first element and a second element as donor.06-02-2011
20110001109NONVOLATILE MEMORY ELEMENT - A nonvolatile memory element (01-06-2011
20110001110RESISTANCE CHANGE ELEMENT AND MANUFACTURING METHOD THEREOF - A resistance change element including: a lower electrode formed on at least one of a semiconductor and insulating substrate; a resistance change material layer formed on the lower electrode and including a transition metal oxide as a major component; and an upper electrode formed on the resistance change material layer. The resistance change material layer is formed of a nickel oxide containing nickel vacancy and having a higher oxygen concentration than a stoichiometric composition, and has a stacked structure with different composition ratios.01-06-2011
20110001107HOLLOW GST STRUCTURE WITH DIELECTRIC FILL - A memory cell structure, including a substrate having a via therein bound at first and second ends thereof by electrodes. The via is coated on side surfaces thereof with GST material defining a core that is hollow or at least partially filled with material, e.g., germanium or dielectric material. One or more of such memory cell structures may be integrated in a phase change memory device. The memory cell structure can be fabricated in a substrate containing a via closed at one end thereof with a bottom electrode, by conformally coating GST material on sidewall surface of the via and surface of the bottom electrode enclosing the via, to form an open core volume bounded by the GST material, optionally at least partially filling the open core volume with germanium or dielectric material, annealing the GST material film, and forming a top electrode at an upper portion of the via.01-06-2011
20100133499RESISTANCE VARIABLE MEMORY WITH TEMPERATURE TOLERANT MATERIALS - A PCRAM memory device having a chalcogenide glass layer, preferably comprising antimony selenide having a stoichometric formula of about Sb06-03-2010
20100133498MEMORY DEVICE AND SEMICONDUCTOR DEVICE - A memory device has a pair of conductive layers and an organic compound having a liquid crystal property that is interposed between the pair of conductive layers. Data is recorded in the memory device by applying a first voltage to the pair of conductive layers and heating the organic compound, to cause a phase change of the organic compound from a first phase to a second phase.06-03-2010
20110024713NONVOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a nonvolatile memory device includes a stacked body including a first layer, a second layer and a recording layer. The recording layer is provided between the first layer and the second layer. The recording layer is capable of reversibly changing between a first state and a second state having a resistance higher than a resistance in the first state by a current supplied via the first layer and the second layer. The recording layer includes a first portion and a second portion provided in a plane of a major surface of the recording layer. The second portion has a nitrogen amount higher than a nitrogen amount in the first portion.02-03-2011
20110031459INFORMATION RECORDING AND REPRODUCING DEVICE - According to one embodiment, an information recording and reproducing device includes a first layer, a second layer and a recording layer. The recording layer is provided between the first layer and the second layer and being capable of reversibly changing between a first state having a first resistance and a second state having a second resistance higher than the first resistance. The recording layer includes a first compound layer and a second compound layer. The first compound layer contains a first compound. The first compound includes a first cation element and a second cation element of a type different from the first cation element. The second compound layer contains a second compound. The second compound includes a transition element having a d-orbital partially filled with electron, and the second compound includes a void site capable of storing at least one of the first cation element and the second cation element.02-10-2011
20110114911Programmable Resistance Memory Element and Method for Making Same - A programmable resistance memory element. The active volume of memory material is made small by the presence of a small area of contact between the conductive material and the memory material. The area of contact is created by forming a region of conductive material and an intersecting sidewall layer of the memory material. The region of conductive material is preferably a sidewall layer of conductive material.05-19-2011
20130153848SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory device comprising a bit line extending in a first direction, a vertical gate cell including a gate oxide layer and a gate metal layer that are formed in a pillar shape, a lower electrode and a data storage material layer formed on the vertical gate cell, and an interconnection layer formed on the data storage material layer.06-20-2013
20130153849NON-VOLATILE MEMORY WITH RESISTIVE ACCESS COMPONENT - Some embodiments include apparatus and methods having a memory element configured to store information and an access component configured to allow conduction of current through the memory element when a first voltage difference in a first direction across the memory element and the access component exceeds a first voltage value and to prevent conduction of current through the memory element when a second voltage difference in a second direction across the memory element and the access component exceeds a second voltage value, wherein the access component includes a material excluding silicon.06-20-2013
20100171088RESISTANCE VARIABLE MEMORY DEVICE WITH SPUTTERED METAL-CHALCOGENIDE REGION AND METHOD OF FABRICATION - A chalcogenide-based programmable conductor memory device and method of forming the device, wherein a chalcogenide glass region is provided with a plurality of alternating tin chalcogenide and metal layers proximate thereto. The method of forming the device comprises sputtering the alternating tin chalcogenide and metal layers.07-08-2010
20110210303NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, there is provided a nonvolatile semiconductor memory device including a first interconnection layer, memory cell modules each of which is formed by laminating a non-ohmic element layer with an MIM structure having an insulating film sandwiched between metal films and a variable resistance element layer, and a second interconnection layer formed on the memory cell modules, the insulating film of the non-ohmic element layer includes plural layers whose electron barriers and dielectric constants are different, or contains impurity atoms that form defect levels in the insulating film or contains semiconductor or metal dots. The nonvolatile semiconductor memory device using non-ohmic elements and variable resistance elements in which memory cells can be miniaturized and formed at low temperatures is realized by utilizing the above structures.09-01-2011
20100163818FORMING A CARBON PASSIVATED OVONIC THRESHOLD SWITCH - By making an ovonic threshold switch using a carbon interfacial layer having a thickness of less than or equal to ten percent of the thickness of the associated electrode, cycle endurance may be improved. In some embodiments, a glue layer may be used between the carbon and the chalcogenide of the ovonic threshold switch. The glue layer may be effective to improve adherence between carbon and chalcogenide.07-01-2010
20100163817SELF-HEATING PHASE CHANGE MEMORY CELL ARCHITECTURE - A method for manufacturing a phase change memory includes forming a phase change memory cell by forming a phase change layer between two switching layers. The phase change layer is separated from thermal heat sinks, such as the bitline or wordline, by the switching layers.07-01-2010
20100163822OVONIC THRESHOLD SWITCH FILM COMPOSITION FOR TSLAGS MATERIAL - A chalcogenide alloy that optimizes operating parameters of an ovonic threshold switch includes an atomic percentage of arsenic in the range of 9 to 39, an atomic percentage of germanium in the range of 10 and 40, an atomic percentage of silicon in the range of 5 and 18, an atomic percentage of nitrogen in the range of 0 and 10, and an alloy of sulfur, selenium, and tellurium. A ratio of sulfur to selenium in the range of 0.25 and 4, and a ration of sulfur to tellurium in the alloy of sulfur, selenium, and tellurium is in the range of 0.11 and 1.07-01-2010
20100163820PHASE CHANGE MEMORY DEVICE HAVING A REDUCED CONTACT AREA AND METHOD FOR MANUFACTURING THE SAME - A phase change memory device having a reduced contact area and a method for manufacturing the same is presented. The phase change random access memory device includes a bottom electrode contact pattern layer, and at least one phase change pattern layer formed on a sidewall of the bottom electrode contact pattern layer. The contact areas are minimized by being between the narrow width of the bottom electrode contact pattern layer, i.e., at the sidewall, and the phase change pattern layers. As a result the minimized contact area is proportional to the thickness of the bottom electrode contact pattern layer.07-01-2010
20100163819RESISTIVE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A resistive memory device and a fabrication method thereof are provided. The fabrication method includes: providing a substrate; forming a lower electrode over the substrate; forming a variable resistive material layer over the lower electrode; forming an ion implantation region to a predetermined depth from a surface of the variable resistive material layer by implanting metal ions or oxygen ions to the surface of the variable resistive material layer; and forming an upper electrode over the variable resistive material layer including the ion implantation region.07-01-2010
20100032640MEMORY CELL THAT INCLUDES A CARBON-BASED MEMORY ELEMENT AND METHODS OF FORMING THE SAME - Memory cells, and methods of forming such memory cells, are provided that include a carbon-based reversible resistivity switching material. In particular embodiments, methods in accordance with this invention form a memory cell by forming a layer of carbon material above a substrate, forming a barrier layer above the carbon layer, forming a hardmask layer above the barrier layer, forming a photoresist layer above the hardmask layer, patterning and developing the photoresist layer to form a photoresist region, patterning and etching the hardmask layer to form a hardmask region, and using an ashing process to remove the photoresist region while the barrier layer remains above the carbon layer. Other aspects are also provided.02-11-2010
20100123114NONVOLATILE MEMORY DEVICE - A nonvolatile memory device (05-20-2010
20110079763Phase change devices - The present invention is a phase change device with a heater and a selector (e.g., diode) separated by a phase-change alloy. The present invention will find applicability in electronic memory devices.04-07-2011
20110240945Method and Apparatus for Reducing Programmed Volume of Phase Change Memory - A phase change memory includes a volume of phase change material disposed between, and coupled to, two electrodes, with the composition of a region of at least one of the two electrodes or phase change material having been compositionally altered to reduce the programmed volume of the phase change material.10-06-2011
20110240944PHASE CHANGE MEMORY DEVICE WITH PLATED PHASE CHANGE MATERIAL - A method for fabricating a phase change memory device including memory cells includes patterning a via to a contact surface of a substrate corresponding to each of an array of conductive contacts to be connected to access circuitry, lining each via with a conformal conductive seed layer to the contact surface, forming a dielectric layer covering the conductive seed layer, and etching a center region of each via to the contact surface to expose the conformal conductive seed layer at the contact surface. The method further includes electroplating phase change material on exposed portions of the conformal conductive seed layer, recessing the phase change material within the center region forming a conductive material that remains conductive upon oxidation, on the recessed phase change material, oxidizing edges of the conformal conductive seed layer formed along sides of each via, and forming a top electrode over each memory cell.10-06-2011
20110240943 Immunity of Phase Change Material to Disturb in the Amorphous Phase - Disturb from the reset to the set state may be reduced by creating an amorphous phase that is substantially free of crystal nuclei when programming the reset state in a phase change memory. In some embodiments, this can be achieved by using a current or a voltage to program that exceeds the threshold voltage of the phase change memory element, but does not exceed a safe current voltage which would cause a disturb.10-06-2011
20110240942VARIABLE RESISTANCE ELEMENT AND NONVOLATILE SEMICONDUCTOR MEMORY DEVICE USING THE SAME - To provide a variable resistance element capable of preventing the interface resistance, in a side of the variable resistance element in which resistance change is not allowed, from changing to high resistance due to applied voltage. The variable resistance element is configured by providing a variable resistance film (10-06-2011
20110210305METHOD TO PROGRAM A MEMORY CELL COMPRISING A CARBON NANOTUBE FABRIC ELEMENT AND A STEERING ELEMENT - A method of programming a carbon nanotube memory cell is provided, wherein the memory cell comprises a first conductor, a steering element, a carbon nanotube fabric, and a second conductor, wherein the steering element and the carbon nanotube fabric are arranged electrically in series between the first conductor and the second conductor, and wherein the entire carbon nanotube memory cell is formed above a substrate, the carbon nanotube fabric having a first resistivity, the method including applying a first electrical set pulse between the first conductor and the second conductor, wherein, after application of the first electrical set pulse, the carbon nanotube fabric has a second resistivity, the second resistivity less than the first resistivity. Other aspects are also provided.09-01-2011
20110210304STORAGE DEVICE - According to the embodiment, a storage device includes row lines arranged parallel to one another, column lines arranged parallel to one another to intersect with the row lines, and a memory cell disposed at each of intersections of the row lines and the column lines and including a resistance-change element and a diode connected in series to the resistance-change element. The diode includes a stack of a first semiconductor region containing an impurity of a first conductivity type, a second semiconductor region containing an impurity of the first conductivity type lower in concentration than in the first semiconductor region, and a third semiconductor region containing an impurity of a second conductivity type. An impurity concentration in the second semiconductor region of the diode in a first adjacent portion adjacent to the first semiconductor region is higher than that in a second adjacent portion adjacent to the third semiconductor region.09-01-2011
20110210301NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a non-volatile semiconductor memory device includes: a semiconductor substrate; a plurality of first lines; a plurality of second lines; and a plurality of non-volatile memory cells arranged at positions where the plurality of first lines intersect with the plurality of second lines, wherein each of the plurality of non-volatile memory cells includes a resistance change element and a rectifying element connected in series to the resistance change element, and a resistance change film continuously extending over the plurality of second lines is arranged between the plurality of first lines and the plurality of second lines, and the resistance change element includes a portion where the first line intersect with the second line in the resistance change film.09-01-2011
20100258780PHASE-CHANGE RANDOM ACCESS MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided are a Phase-change Random Access Memory (PRAM) device and a method of manufacturing the same. In particular, a PRAM device including a heating layer, wherein the heating layer comprises first and second heating layers having different physical properties from each other and a method of manufacturing the same are provided. Since the PRAM device according to the present invention includes a heating layer having optimal heating characteristics, a PRAM device having high reliability and excellent operating characteristics can be manufactured.10-14-2010
20100032639MEMORY CELL THAT INCLUDES A CARBON-BASED MEMORY ELEMENT AND METHODS OF FORMING THE SAME - Memory cells, and methods of forming such memory cells, are provided that include a steering element coupled to a carbon-based reversible resistivity switching material. In particular embodiments, methods in accordance with this invention form a single layer of a carbon-based reversible resistance switching material above a substrate, wherein the single layer of carbon material has a thickness greater than about three monolayers of the carbon-based reversible resistance switching material, and prior to forming an additional layer above the carbon layer, thermally anneal the carbon layer. Other aspects are also provided.02-11-2010
20090250680SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - With a high-speed nonvolatile phase change memory, reliability in respect of the number of refresh times is enhanced. In a memory cell forming area of a phase change memory using a MISFET as a transistor for selection of memory cells, a phase change material layer of a memory cell comprising a resistor element, using a phase change material, is formed for common use. As a result, variation in shape and a change in composition of the phase change material, caused by isolation of memory cell elements by etching, are reduced, thereby enhancing reliability of memory cells, in respect of the number of refresh times.10-08-2009
20100044665ELECTRONIC COMPONENT, AND A METHOD OF MANUFACTURING AN ELECTRONIC COMPONENT - An electronic component (02-25-2010
20100038616NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND PRODUCING METHOD THEREOF - A cell array includes a memory cell region in which memory cells are formed and a peripheral region that is provided around the memory cell region. In the memory cell region, first lines are extended in parallel with a first direction, and the first lines are repeatedly formed at first intervals in a second direction orthogonal to the first direction. In the peripheral region, each of the first lines located at (4n−3)-th (n is a positive integer) and (4n−2)-th positions in the second direction from a predetermined position has a contact connecting portion on one end side in the first direction of the first line. In the peripheral region, each of the first lines located at (4n−1)-th and 4n-th positions in the second direction from the predetermined position has the contact connecting portion on the other end side in the first direction of the first line. The contact connecting portion is formed so as to contact a contact plug extended in a laminating direction.02-18-2010
20100038617SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device having a first wiring layer which is provided on a first insulator, and which extends in a first direction, and a non-volatile memory cell which is provided in a pillar shape on the first wiring layer, and which includes a non-ohmic element and variable resistance element connected in series. The resistance value of the variable resistance element changes in accordance with a voltage or current applied thereto. A barrier layer is provided on the memory cell and is configured in an in-plane direction. A conductive layer is provided on the barrier layer and is configured in an in-plane direction. A second insulator is provided on the first insulator and covers side surfaces of the memory cell, the barrier layer, and the conductive layer. A second wiring layer is provided on the conductive layer and extends in a second direction.02-18-2010
20100038618SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The invention provides a novel memory for which process technology is relatively simple and which can store multivalued information by a small number of elements. A part of a shape of the first electrode in the first storage element is made different from a shape of the first electrode in the second storage element, and thereby voltage values which change electric resistance between the first electrode and the second electrode are varied, so that one memory cell stores multivalued information over one bit. By partially processing the first electrode, storage capacity per unit area can be increased.02-18-2010
20100038615NONVOLATILE STORAGE DEVICE - An element structure for a resistance variable type nonvolatile storage device is provided in which enables a reduction in variation in operating voltage and in a leakage current in an off state of an element. The nonvolatile storage device is characterized by including a lower electrode, an upper electrode, and a laminated structure in which at least one amorphous insulating layer and at least one resistance variation layer are laminated between the lower electrode and the upper electrode.02-18-2010
20100072446Phase-change semiconductor device and methods of manufacturing the same - In a phase-change semiconductor device and methods of manufacturing the same, an example method may include forming a metal layer pattern on a substrate, the metal layer pattern including an opening that exposes a portion of the substrate, forming an etch stop layer on the metal layer pattern, a sidewall of the opening and the exposed portion of the substrate, the etch stop layer formed with a thickness less than an upper thickness threshold, and reducing at least a portion of the etch stop layer, the reduced portion of the etch stop layer forming an electrical connection with the substrate.03-25-2010
20120241709VARIABLE RESISTANCE ELEMENT USING ELECTROCHEMICAL REACTION AND MANUFACTURING METHOD THEREOF - A structure for a variable-resistance element using an electrochemical reaction. The structure limits a position at which metal cross-linking breaks to a position most preferred for cross-linking break: namely, a part of an ion conduction layer closest to a first electrode. Also provided is a method for manufacturing the variable-resistance element, which has a first electrode serving as a source for a metal ion(s), a second electrode which is less ionizable (i.e. has a higher redox potential) than the first electrode, and an ion conduction layer which is interposed between the first and second electrodes and can conduct the metal ion(s). There is a first region in the ion conduction layer, adjacent to the first electrode, having a diffusion coefficient that increases continuously towards the first electrode right upto contacting the first electrode.09-27-2012
20120241708Memory Cells, Memory Cell Arrays, Methods of Using and Methods of Making - In at least one embodiment, a memory cell includes a substrate having a top surface and a first conductivity type; a first region having a second conductivity type being different from the first conductivity type, the first region being formed in the substrate and exposed at the top surface; a second region having the second conductivity type formed in the substrate, spaced apart from the first region and exposed at the top surface; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region formed between the first and second regions and the buried layer; a gate positioned between the first and second regions and above the top surface; and a nonvolatile memory configured to store data upon transfer from the body region.09-27-2012
20120241707NONVOLATILE MEMORY DEVICE - According to one embodiment, a nonvolatile memory device includes a word line interconnect layer, a bit line interconnect layer, and a pillar. The word line interconnect layer includes a plurality of word lines extending in a first direction. The bit line interconnect layer includes a plurality of bit lines extending in a second direction. The pillar is disposed between each of the word lines and each of the bit lines. The pillar includes a current selection film and a plurality of variable resistance films stacked on the current selection film. One variable resistance film includes a metal and either oxygen or nitrogen. Remainder of the variable resistance films include the metal, either oxygen or nitrogen, and a highly electronegative substance having electronegativity higher than electronegativity of the metal. A concentration of highly electronegative substance in the remainder of the variable resistance films is different among the variable resistance films.09-27-2012
20110175048NONVOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a nonvolatile memory device includes first and second conductive layers, a resistance change layer, and a rectifying element. The first conductive layer has first and second major surfaces. The second conductive layer has third and fourth major surfaces, a side face, and a corner part. The third major surface faces the first major surface and includes a plane parallel to the first major face and is provided between the fourth and first major surfaces. The corner part is provided between the third major surface and the side face. The corner part has a curvature higher than that of the third major surface. The resistance change layer is provided between the first and second conductive layers. The rectifying element faces the second major surface of the first conductive layer. An area of the third major surface is smaller than that the second major surface.07-21-2011
20110175047ELECTRIC FIELD INDUCED PHASE TRANSITIONS AND DYNAMIC TUNING OF THE PROPERTIES OF OXIDE STRUCTURES - Phase transitions (such as metal-insulator transitions) are induced in oxide structures (such as vanadium oxide thin films) by applying an electric field. The electric field-induced phase transitions are achieved in VO07-21-2011
20110068312NONVOLATILE MEMORY DEVICE - According to one embodiment, a nonvolatile memory device comprises a plurality of first lines, a plurality of second lines, and memory cells. Each of the memory cells comprise a variable resistor, and a diode. The variable resistor includes a first metal oxide film and is configured to reversibly change resistance value by energy application. The diode includes a second metal oxide film and is connected in series to the variable resistor. The first metal oxide film has at least one of dielectric constant lower than that of the second metal oxide film and physical film thickness greater than that of the second metal oxide film.03-24-2011
20120119180NON-VOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - Provided are a non-volatile memory device which can be extended in a stack structure and thus can be highly integrated, and a method of manufacturing the non-volatile memory device. The non-volatile memory device includes: at least one first electrode, at least one second electrode crossing the at least one first electrode, at least one data storing layer interposed between the at least one first electrode and the second electrode, at a region in which the at least one first electrode crosses the at least one second electrode and at least one metal silicide layer interposed between the at least one first electrode and the at least one second electrode, at the region in which the at least one first electrode crosses the at least one second electrode.05-17-2012
20120119179MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a memory device includes a nanomaterial aggregate layer of a plurality of fine conductors aggregating via gaps and an insulating material disposed in the gaps.05-17-2012
20120119178MEMORY CELL THAT INCLUDES A CARBON-BASED MEMORY ELEMENT AND METHODS OF FORMING THE SAME - In accordance with aspects of the invention, a method of forming a metal-insulator-metal stack is provided. The method includes forming a first conducting layer, forming a resistivity-switching carbon-based material above the first conducting layer, and forming a second conducting layer above the carbon-based material, wherein the carbon-based material has a thickness of not more than ten atomic layers. Other aspects are also described.05-17-2012
20120119177Chalcogenide Containing Semiconductors with Chalcogenide Gradient - Chalcogenide containing semiconductor devices may be formed with a gradient film between a chalcogenide film and another film. The gradient film may have its chalcogenide concentration decrease as it extends away from the chalcogenide film, while the concentration of the other film material increases across the thickness of the gradient film moving away from the chalcogenide film.05-17-2012
20110042639MEMORY CELL THAT EMPLOYS A SELECTIVELY GROWN REVERSIBLE RESISTANCE-SWITCHING ELEMENT AND METHODS OF FORMING THE SAME - In some aspects, a method of forming a memory cell is provided that includes (02-24-2011
20090026434NONVOLATILE MEMORY ELEMENTS - Nonvolatile memory elements that are based on resistive switching memory element layers are provided. A nonvolatile memory element may have a resistive switching metal oxide layer. The resistive switching metal oxide layer may have one or more layers of oxide. A resistive switching metal oxide may be doped with a dopant that increases its melting temperature and enhances its thermal stability. Layers may be formed to enhance the thermal stability of the nonvolatile memory element. An electrode for a nonvolatile memory element may contain a conductive layer and a buffer layer.01-29-2009
20090026432METHOD AND STRUCTURE FOR UNIFORM CONTACT AREA BETWEEN HEATER AND PHASE CHANGE MATERIAL IN PCRAM DEVICE - A PCM (phase change memory) cell in a PCRAM (phase change random access memory) semiconductor device includes a phase change material subjacently contacted by a heater film. The phase change material is formed over a surface that is a generally planar surface with at least a downwardly extending recess. The phase change material fills the recess and contacts the upper edge of the heater film that forms the bottom of the recess. After a planar surface is initially formed, a selective etching process is used to recede the top edge of the heater film below the planar surface using a selective and isotropic etching process.01-29-2009
20100295011ENHANCED MEMORY DENSITY RESISTANCE VARIABLE MEMORY CELLS, ARRAYS, DEVICES AND SYSTEMS INCLUDING THE SAME, AND METHODS OF FABRICATION - A resistance variable memory cell and method of forming the same. The memory cell includes a first electrode and at least one layer of resistance variable material in contact with the first electrode. A first, second electrode is in contact with a first portion of the at least one layer of resistance variable material and a second, second electrode is in contact with a second portion of the at least one layer of resistance variable material.11-25-2010
20090014703SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes the first transistor having first and second source/drain diffusion regions positioned below a second bit line to sandwich the first word line therebetween, and the second source/drain diffusion region positioned between the first and second word lines and connected to a first bit line, a second transistor having second and third source/drain diffusion regions positioned below the second bit line to sandwich the second word line therebetween, a first resistive memory element formed below the second bit line above the first source/drain diffusion region, and having terminals connected to the second bit line and the first source/drain diffusion region, and a second resistive memory element formed below the second bit line above the third source/drain diffusion region, and having terminals connected to the second bit line and the third source/drain diffusion region.01-15-2009
20110248235VARIABLE RESISTANCE MEMORY DEVICES AND METHODS FOR FABRICATING THE SAME - A nonvolatile memory device includes a substrate and a first insulating layer on the substrate. The first insulating layer includes a first opening therein. A lower electrode is provided in the first opening and protrudes from a surface of the first insulating layer outside the first opening. An electrode passivation pattern is provided on a sidewall of the lower electrode that protrudes from the surface of the first insulating layer. A second insulating layer is provided on the first insulating layer and includes a second opening therein at least partially exposing the lower electrode. A variable resistance material layer extends into the second opening to contact the lower electrode. The electrode passivation layer electrically separates the sidewall of the lower electrode from the variable resistance material layer. The electrode passivation pattern is formed of a material having an etching selectivity to that of the second insulating layer. Related fabrication methods are also discussed.10-13-2011
20100301301SEMICONDUCTOR MEMORY DEVICE - There is offered a switching resistance RAM that is very much reduced in an occupied area and is highly integrated. Memory cells CEL12-02-2010
20100264392NONVOLATILE MEMORY APPARATUS AND MANUFACTURING METHOD THEREOF - A nonvolatile memory device includes via holes (10-21-2010
20100078615SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a variable resistance element including a first electrode, a current path forming region, and a second electrode. The current path forming region includes a first region made of a variable resistance material whose resistivity changes by applying voltage, and a second region formed by doping a metal element to the variable resistance material such that a resistivity of the second region is higher than that of the first region and is not changed by applying a voltage used to change the resistivity of the first region. The first region is in contact with the first electrode and the second electrode, and extends from one electrode side to the other electrode side. The second region is provided outside the first region in at least part of the current path forming region in direction extending from one electrode side to the other electrode side.04-01-2010
20100032636NON-VOLATILE MEMORY CELL WITH ENHANCED FILAMENT FORMATION CHARACTERISTICS - Method and apparatus for constructing a non-volatile memory cell, such as a modified RRAM cell. In some embodiments, a memory cell comprises a resistive storage layer disposed between a first electrode layer and a second electrode layer. Further in some embodiments, the storage layer has a localized region of decreased thickness to facilitate formation of a conductive filament through the storage layer from the first electrode to the second electrode.02-11-2010
20090001337Phase Change Memory Cell with Vertical Transistor - A memory cell in an integrated circuit is fabricated in part by forming a lower electrode feature, an island, a sacrificial feature, a gate feature, and a phase change feature. The island is formed on the lower electrode feature and has one or more sidewalls. It comprises a lower doped feature, a middle doped feature formed above the lower doped feature, and an upper doped feature formed above the middle doped feature. The sacrificial feature is formed above the island, while the gate feature is formed along each sidewall of the island. The gate feature overlies at least a portion of the middle doped feature of the island and is operative to control an electrical resistance therein. Finally, the phase feature is formed above the island at least in part by replacing at least a portion of the sacrificial feature with a phase change material. The phase change material is operative to switch between lower and higher electrical resistance states in response to an application of an electrical signal.01-01-2009
20090283737NONVOLATILE STORAGE DEVICE AND METHOD FOR MANUFACTURING SAME - A nonvolatile storage device having a plurality of unit memory layers, and a plurality of layer selection transistors is provided. The plurality of unit memory layers are laminated in a direction perpendicular to a layer surface of the unit memory layers. Each of the unit memory layers includes a plurality of first wirings, a plurality of second wirings provided non-parallel to the plurality of first wirings, and a recording layer provided between the plurality of first wirings and the plurality of second wirings. The plurality of layer selection transistors are connected to at least one of the plurality of first wirings and the plurality of second wirings of each of the unit memory layers, and collectively selects the at least one in the same plane.11-19-2009
20090230377Phase Change Materials for Applications that Require Fast Switching and High Endurance - A memory device utilizing a phase change material as the storage medium, the phase change material based on antimony as the solvent in a solid solution; wherein the memory device further includes a means for heating the phase change material.09-17-2009
20090230375Phase Change Memory Device - A semiconductor device is provided which includes a substrate having a dielectric layer formed thereon, a heating element formed in the dielectric layer, a phase change element formed on the heating element, and a conductive element formed on the phase change element. The phase change element includes a substantially amorphous background and an active region, the active region capable of changing phase between amorphous and crystalline.09-17-2009
20120199805NONVOLATILE MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - Provided are a nonvolatile memory device which can suppress non-uniformity in initial breakdown voltages among nonvolatile memory elements and prevent reduction of yield, and a manufacturing method thereof. The nonvolatile memory device includes a nonvolatile memory element (08-09-2012
20090001336PHASE CHANGE MATERIAL BASED TEMPERATURE SENSOR - A block of phase change material located in a semiconductor chip is reset to an amorphous state. The block of phase change material may be connected to an internal resistance measurement circuit that can transmit the measured resistance data to input/output pads either in an analog output format or in a digital output format. Depending on the ambient temperature, the resistance of the block of phase change material changes. By measuring a fractional resistance change compared to the resistance of the phase change material at a calibration temperature, the temperature of the region around the phase change material can be accurately measured. A logic decoder and an input/output circuit may be employed between the internal resistance measurement circuit and the input/output pads. A plurality of temperature sensing circuits containing phase change material blocks may be employed in the semiconductor chip to enable an accurate temperature profiling during chip operation.01-01-2009
20090127535PHASE CHANGE MEMORY ELEMENT AND METHOD FOR FABRICATING THE SAME - A phase change memory device is disclosed, including a substrate. The phase change memory also includes a bottom electrode. A conductive structure with a cavity is provided to electrically contact the bottom electrode, wherein the conductive structure includes sidewalls with different thicknesses. A phase change spacer is formed to cross the sidewalls with different thicknesses. A top electrode is electrically contacted to the phase change spacer.05-21-2009
20110037044INFORMATION RECORDING DEVICE AND INFORMATION RECORDING/REPRODUCTION SYSTEM INCLUDING THE SAME - This disclosure provides an information recording device for use in a non-volatile information recording/reproduction system having a high recording density, the device including a resistive material having less phase separation or the like during switching. This disclosure also provides an information recording/reproduction system including the device. This disclosure provides an information recording device including: a pair of electrodes; and a recording layer between the electrodes, the recording layer recording information by its resistance change, the recording layer including at least one of (a) M02-17-2011
20110037043NONVOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a nonvolatile memory device includes a first wire, a second wire and a nonvolatile memory cell. The first wire is formed to extend in a first direction, and the second wire is formed at height different from height of the first wire and to extend in a second direction. The nonvolatile memory cell is arranged to be held between the first wire and the second wire in a poison where the first wire and the second wire cross. The nonvolatile memory cell includes a nonvolatile storage layer and a current limiting resistance layer connected in series to the nonvolatile storage layer and having resistance of 1 kilo-ohm to 1 mega-ohm.02-17-2011
20110037042PHASE CHANGE MEMORY DEVICE WITH PLATED PHASE CHANGE MATERIAL - A method for fabricating a phase change memory device including memory cells includes patterning a via to a contact surface of a substrate corresponding to each of an array of conductive contacts to be connected to access circuitry, lining each via with a conformal conductive seed layer to the contact surface, forming a dielectric layer covering the conductive seed layer, and etching a center region of each via to the contact surface to expose the conformal conductive seed layer at the contact surface. The method further includes electroplating phase change material on exposed portions of the conformal conductive seed layer, recessing the phase change material within the center region forming a conductive material that remains conductive upon oxidation, on the recessed phase change material, oxidizing edges of the conformal conductive seed layer formed along sides of each via, and forming a top electrode over each memory cell.02-17-2011
20090101879Method for Making Self Aligning Pillar Memory Cell Device - A method for making a memory cell assembly includes forming a memory cell access layer over a substrate to create an access device with a bottom electrode. A memory material layer is formed over the memory cell access layer in electrical contact with the bottom electrode. A first electrically conductive layer is formed over the memory material layer. A first mask, extending in a first direction, is formed over the first electrically conductive layer and then trimmed so that those portions of the first electrically conductive layer and the memory material layer not covered by the first mask are removed.04-23-2009
20090020739Method for Delineation of Phase Change Memory Cell Via Film Resistivity Modification - A PCM cell structure comprises a lower electrode composed of a Phase Change Memory (PCM) layer and a conductive encapsulating upper electrode layer. The PCM is protected from damage by a conductive encapsulating layer. Electrical isolation between adjacent cells is provided by modifying the conductivity of the PCM layer and the conductive encapsulating upper electrode layer subsequent to deposition.01-22-2009
20120199804HETEROJUNCTION OXIDE NON-VOLATILE MEMORY DEVICE - A memory device includes a first metal layer and a first metal oxide layer coupled to the first metal layer. The memory device includes a second metal oxide layer coupled to the first metal oxide layer and a second metal layer coupled to the second metal oxide layer. The formation of the first metal oxide layer has a Gibbs free energy that is lower than the Gibbs free energy for the formation of the second metal oxide layer08-09-2012
20080203374Phase-change memory and fabrication method thereof - A phase-change memory is provided. The phase-change memory comprises a substrate. A first electrode is formed on the substrate. A circular or linear phase-change layer is electrically connected to the first electrode. A second electrode formed on the phase-change layer and electrically connected to the phase-change layer, wherein at least one of the first electrode and the second electrode comprises phase-change material.08-28-2008
20100320432VERTICAL MOSFET TRANSISTOR, IN PARTICULAR OPERATING AS A SELECTOR IN NONVOLATILE MEMORY DEVICES - A vertical MOSFET transistor is formed in a body of semiconductor material having a surface. The transistor includes a buried conductive region of a first conductivity type; a channel region of a second conductivity type, arranged on top of the buried conductive region; a surface conductive region of the first conductivity type, arranged on top of the channel region and the buried conductive region; a gate insulation region, extending at the sides of and contiguous to the channel region; and a gate region extending at the sides of and contiguous to the gate insulation region.12-23-2010
20100320433Variable Resistance Memory Device and Method of Manufacturing the Same - A variable resistance memory device includes a substrate, a plurality of active lines formed on the substrate, are uniformly separated, and extend in a first direction, a plurality of switching devices formed on the active lines and are separated from one another, a plurality of variable resistance devices respectively formed on and connected to the switching devices, a plurality of local bit lines formed on the variable resistance devices, are uniformly separated, extend in a second direction, and are connected to the variable resistance devices, a plurality of local word lines formed on the local bit lines, are uniformly separated, and extend in the first direction, a plurality of global bit lines formed on the local word lines, are uniformly separated, and extend in the second direction, and a plurality of global word lines formed on the global bit lines, are uniformly separated, and extend in the first direction.12-23-2010
20130119338RESISTANCE-SWITCHING MEMORY CELLS ADAPTED FOR USE AT LOW VOLTAGE - A memory cell is provided that includes a diode and a resistance-switching material layer coupled in series with the diode. The resistance-switching material layer: (a) includes a material from the family consisting of XvOw, wherein X represents an element from the family consisting of Hf and Zr, and wherein the subscripts v and w have non-zero values that form a stable compound, and (b) has a thickness between 20 and 65 angstroms. Other aspects are also provided.05-16-2013
20100283024Memory Element and Method for Manufacturing the Same, and Semiconductor Device - The memory element has a structure at least including a first conductive layer, a second conductive layer, and a memory layer disposed between the first conductive layer and the second conductive layer. The memory layer is formed by a droplet discharge method using nanoparticles of a conductive material each of which is coated with an organic thin film. Specifically, a composition in which nanoparticles of a conductive material each of which is coated with an organic thin film are dispersed in a solvent is discharged (ejected) as ink droplets, and the solvent is dried to be vaporized to form the memory layer. Accordingly, a memory element can be formed simply. In addition, efficiency in the use of materials can be improved and yield is also improved, so that the memory element can be provided at low cost.11-11-2010
20100283028NON-VOLATILE RESISTANCE SWITCHING MEMORIES AND METHODS OF MAKING SAME - An integrated circuit memory cell including: a semiconductor having a first active area, a second active area, and a channel between the active areas; and a layer of a variable resistance material (VRM) directly above the channel. In one embodiment, there is a first conductive layer between the VRM and the channel and a second conductive layer directly above the VRM layer. The VRM preferably is a correlated electron material (CEM). The memory cell comprises a FET, such as a JFET or a MESFET. In another embodiment, there is a layer of an insulating material between the VRM and the channel. In this case, the memory cell may include a MOSFET structure.11-11-2010
20110133148RESISTIVE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - Provided are resistive memory devices and methods of fabricating the same. The resistive memory devices and the methods are advantageous for high integration because they can provide a multilayer memory cell structure. Also, the parallel conductive lines of adjacent layers do not overlap each other in the vertical direction, thus reducing errors in program/erase operations.06-09-2011
20100181548SOLID-STATE MEMORY AND SEMICONDUCTOR DEVICE - A solid memory may include a recording layer including Ge, Sb and Te as major components. The recording layer may include a superlattice. The recording layer may include multi-layers each having a parent phase showing a phase transformation in solid-states, the phase transformation causing change in electrical property of the recording layer. The recording layer may include an Sb07-22-2010
20100181547Semiconductor device and method of manufacturing the same - A semiconductor device includes: diffusion layers formed at the front surface of a substrate; low-resistance parts formed at the front surfaces of the diffusion layers so as to have resistance lower than the diffusion layer; and rear contact electrodes passing through the substrate from the rear surface of the substrate to be connected to the low-resistance parts through the diffusion layers.07-22-2010
20100181546NONVOLATILE SEMICONDUCTOR MEMORY AND MANUFACTURING METHOD THEREOF - A nonvolatile semiconductor memory using carbon related films as variable resistance films includes bottom electrodes formed above a substrate, buffer layers formed on the bottom electrodes and each formed of a film containing nitrogen and containing carbon as a main component, variable resistance films formed on the buffer layers and each formed of a film containing carbon as a main component and the electrical resistivity thereof being changed according to application of voltage or supply of current, and top electrodes formed on the variable resistance films.07-22-2010
20110253965VERTICAL TRANSISTOR PHASE CHANGE MEMORY - Vertical transistor phase change memory and methods of processing phase change memory are described herein. One or more methods include forming a dielectric on at least a portion of a vertical transistor, forming an electrode on the dielectric, and forming a vertical strip of phase change material on a portion of a side of the electrode and on a portion of a side of the dielectric extending along the electrode and the dielectric into contact with the vertical transistor.10-20-2011
20110168964Processing Phase Change Material to Improve Programming Speed - A phase change material may be processed to reduce its microcrystalline grain size and may also be processed to increase the crystallization or set programming speed of the material. For example, material doped with nitrogen to reduce grain size may be doped with titanium to reduce crystallization time.07-14-2011
20110260132HIGH CONCENTRATION NITROGEN-CONTAINING GERMANIUM TELLURIDE BASED MEMORY DEVICES AND PROCESSES OF MAKING - A PCM device has the composition GexTeyNzAm deposited onto a substrate, where x is about 40% to about 60%, y is about 30% to about 49%, and z is about 5% to about 20% and more preferably about 5% to about 40%. The component represented as A is optional and representative of an element of Sb, Sn, In, Ga, or Zn, and m is up to about 15%. The composition is in the form of a film, and the nitrogen allows for the substantially conformal deposition of the film onto the substrate. A CVD process for depositing the PCM comprises delivering a Ge-based precursor and a Te-based precursor in vapor form to a CVD chamber, heating and pressurizing the chamber, and depositing the film onto a substrate. In making a phase change device using this process, the film is annealed and polished.10-27-2011
20110095256Memory Cells - In some embodiments, a memory cell includes a transistor gate spaced from a channel region by gate dielectric; a source region on one side of the channel region; and a drain region on an opposing side of the channel region from the source region. The channel region has phase change material adjacent the drain region. In some embodiments, the phase change material may be adjacent both the source region and the drain region. Some embodiments include methods of programming a memory cell that has phase change material adjacent a drain region. An inversion layer is formed within the channel region adjacent the gate dielectric, with the inversion layer having a pinch-off region within the phase change material adjacent the drain region. Hot carriers (for instance, electrons) within the pinch-off region are utilized to change a phase within the phase change material.04-28-2011
20110095255MEMORY DEVICE AND FABRICATION PROCESS THEREOF - A memory device that includes a resistive-change memory element, the memory device includes: a first memory element that includes a first resistive-change layer and a first electrode connected to the first resistive-change layer; and a second memory element that includes a second resistive-change layer and a second electrode connected to the second resistive-change layer, wherein at least one of the thickness and the material of the second resistive-change layer and the area of the second electrode in contact with the second resistive-change layer is different from the corresponding one of the thickness and the material of the first resistive-change layer and the area of the first electrode in contact with the first resistive-change layer.04-28-2011
20100059729Apparatus and method for memory - A programmable resistance memory includes a volume of programmable resistance material formed between and coupled to two electrodes. The volume of programmable resistance material includes a region of enhanced programmability that is positioned to maximize the effect of a programming current. The region of enhanced programmability is positioned at a distance from regions of high thermal conductivity, such as areas in close proximity to electrodes.03-11-2010
20100059730RESISTANCE CHANGE ELEMENT AND SEMICONDUCTOR DEVICE INCLUDING THE SAME - To use a resistance change element having an MIM structure, which is obtained by stacking a metal, a metal oxide, and a metal, as a switching element, it is necessary to achieve OFF resistance higher than that required in a memory element by a factor of at least 1000. On the other hand, when a resistance change element is used as a memory element and when the difference between the ON resistance and the OFF resistance is a large value, high performance, for example, a short readout time, can be achieved. The present invention therefore provides a resistance change element capable of maintaining low ON resistance and achieving high OFF resistance. High OFF resistance can be achieved while low ON resistance is maintained by adding a second metal that is not contained in a metal oxide, which is a resistance change material, the second metal being capable of charge-compensating for metal deficiency or oxygen deficiency.03-11-2010
20110186798Phase Changeable Memory Devices and Methods of Forming the Same - Phase changeable memory devices are provided including a mold insulating layer on a substrate, the mold insulating layer defining an opening therein. A phase-change material layer is provided in the opening. The phase-change material includes an upper surface that is below a surface of the mold insulating layer. A first electrode is provided in the opening and on the phase-change material layer. A spacer is provided between a sidewall of the mold insulating layer and the phase-change material layer and the first electrode. The upper surface of the first electrode is coplanar with the surface of the mold insulating layer. Related methods are also provided.08-04-2011
20110147689PHASE CHANGE MEMORY DEVICE CAPABLE OF REDUCING DISTURBANCE AND FABRICATION METHOD THEREOF - A phase change memory device capable of reducing disturbances between adjacent PRAM memory cells and a fabrication method are presented. The phase change memory device includes word lines, heating electrodes, an interlayer insulating layer, and a phase change lines. The word lines are formed on a semiconductor substrate and extend in parallel with a constant space. The heating electrodes are electrically connected to the plurality of word lines. The interlayer insulating layer insulates the heating electrodes. The phase change lines extend in a direction orthogonal to the word line and are electrically connected to the heating electrodes. Curves are formed on a surface of the interlayer insulating layer between the word lines such that the effective length of the phase change layer between adjacent heating electrodes is larger than the physical distance between the adjacent heating electrodes.06-23-2011
20110147693MEMORY CELL THAT EMPLOYS A SELECTIVELY GROWN REVERSIBLE RESISTANCE-SWITCHING ELEMENT AND METHODS OF FORMING THE SAME - In some aspects, a memory cell is provided that includes (1) a steering element above a substrate; and (2) a reversible resistance-switching element coupled to the steering element, wherein the reversible resistance-switching element is selectively formed by: (a) forming a material layer on the substrate; (b) etching the material layer; and (c) oxidizing the etched material layer to form a reversible resistance-switching material. Numerous other aspects are provided.06-23-2011
20110147692VARIABLE RESISTANCE MEMORY DEVICE AND METHOD OF FORMING THE SAME - Provided are a variable resistance memory device and a method of forming the same. The variable resistance memory device may include a substrate, a plurality of bottom electrodes on the substrate, and a first interlayer insulating layer including a trench formed therein. The trench exposes the bottom electrodes and extends in a first direction. The variable resistance memory device further includes a top electrode provided on the first interlayer insulating layer and extending in a second direction crossing the first direction and a plurality of variable resistance patterns provided in the trench and having sidewalls aligned with a sidewall of the top electrode.06-23-2011
20110147691SEMICONDUCTOR MEMORY DEVICE USING VARIABLE RESISTANCE ELEMENT OR PHASE-CHANGE ELEMENT AS MEMORY DEVICE - A semiconductor memory device includes a first conductive line, a second conductive line, a cell unit, a silicon nitride film and a double-sidewall film. The first conductive line extends in a first direction. The second conductive line extends in a second direction crossing the first direction. The cell unit includes a phase-change film and a rectifier element connected in series with each other between the first conductive line and the second conductive line. The silicon nitride film is formed on a side surface of the phase-change film. The double-sidewall film includes a silicon oxide film and the silicon nitride film formed on a side surface of the rectifier element.06-23-2011
20110147690PHASE CHANGE MEMORY DEVICE HAVING 3 DIMENSIONAL STACK STRUCTURE AND FABRICATION METHOD THEREOF - A phase change memory device having a 3-D stack structure and a fabrication method for making the same are presented. The phase change memory device includes a semiconductor substrate, a word line structure and one or more phase change structures. The word line structure extends in one first direction on the semiconductor substrate. The one or more phase change structures extend mutually in parallel from one sidewall of the word line structure. The, the memory cell including a switching device, one side of the switching device contacted with the one sidewall of the word line structure, a heating electrode formed on the other side portion of the switching device, and a phase change pattern, one sidewall of the phase change pattern contacted with the heating electrode.06-23-2011
20110215288SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD THEREOF - Since a chalcogenide material has low adhesion to a silicon oxide film, there is a problem in that it tends to separate from the film during the manufacturing step of a phase change memory. In addition, since the chalcogenide material has to be heated to its melting point or higher during resetting (amorphization) of the phase change memory, there is a problem of requiring extremely large rewriting current. An interfacial layer includes an extremely thin insulator or semiconductor having the function as both an adhesive layer and a high resistance layer (thermal resistance layer) is inserted between chalcogenide material layer/interlayer insulative film and between chalcogenide material layer/plug.09-08-2011
20100019216MULTI-LAYER PHASE-CHANGEABLE MEMORY DEVICES - A phase-changeable memory device includes a phase-changeable material pattern and first and second electrodes electrically connected to the phase-changeable material pattern. The first and second electrodes are configured to provide an electrical signal to the phase-changeable material pattern. The phase-changeable material pattern includes a first phase-changeable material layer and a second phase-changeable material layer. The first and second phase-changeable material patterns have different chemical, physical, and/or electrical characteristics. For example, the second phase-changeable material layer may have a greater resistivity than the first phase-changeable material layer. For instance, the first phase-changeable material layer may include nitrogen at a first concentration, and the second phase-changeable material layer may include nitrogen at a second concentration that is greater than the first concentration. Related devices and fabrication methods are also discussed.01-28-2010
20100019215MUSHROOM TYPE MEMORY CELL HAVING SELF-ALIGNED BOTTOM ELECTRODE AND DIODE ACCESS DEVICE - Memory devices are described along with methods for manufacturing. A memory device as described herein includes a plurality of word lines extending in a first direction, and a plurality of bit lines overlying the plurality of word lines and extending in a second direction. A plurality of memory cells are at cross-point locations. Each memory cell comprises a diode having first and second sides aligned with sides of a corresponding word line. Each memory cell also includes a bottom electrode self-centered on the diode, the bottom electrode having a top surface with a surface area less than that of the top surface of the diode. Each of the memory cells includes a strip of memory material on the top surface of the bottom electrode, the strip of memory material underlying and in electrical communication with a corresponding bit line.01-28-2010
20090121208NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A nonvolatile semiconductor memory device comprises a plurality of first lines; a plurality of second lines crossing the plurality of first lines; a plurality of memory cells each connected at an intersection of the first and second lines between both lines and including a variable resistor operative to store information in accordance with a variation in resistance; and a protection film covering the side of the variable resistor to suppress migration of cations at the side of the variable resistor.05-14-2009
20090173927Storage node, phase change memory device and methods of manufacturing and operating the same - Provided are a storage node, phase change memory device and methods of manufacturing and operating the same. The storage node may include an electrode, a phase change layer, and an anti-diffusion layer between the electrode and the phase change layer and including a silicide compound. The phase change memory device may include the storage node and a switching device connected to the storage node.07-09-2009
20100301300Three-terminal metal-insulator transition switch, switching system including the same, and method of controlling metal-insulator transition of the same - Provided are a 3-terminal MIT switch which can easily control a discontinuous MIT jump and does not need a conventipnal gate insulating layer, a switching system including the 3-terminal MIT switch, and a method of controlling an MIT of the 3-terminal MIT switch. The 3-terminal MIT switch includes a 2-terminal MIT device, which generates discontinuous MIT in a transition voltage, an inlet electrode (12-02-2010
20090001339Chemical Mechanical Polishing Slurry Composition for Polishing Phase-Change Memory Device and Method for Polishing Phase-Change Memory Device Using the Same - A slurry composition for chemical mechanical polishing (CMP) of a phase-change memory device is provided. The slurry composition comprises deionized water, a nitrogenous compound, and optionally abrasive particles, an oxidizing agent, or a combination thereof. The slurry composition can polish a phase-change memory device at a high rate, can achieve high polishing selectivity between a phase-change memory material and a polish stop layer (e.g., a silicon oxide film), and can minimize the occurrence of processing imperfections (e.g., dishing and erosion) to provide a high-quality polished surface. Further provided is a method for polishing a phase-change memory device using the slurry composition.01-01-2009
20090001340Chemical Mechanical Polishing Slurry Composition for Polishing Phase-Change Memory Device and Method for Polishing Phase-Change Memory Device Using the Same - A slurry composition for chemical mechanical polishing (CMP) of a phase-change memory device is provided. The slurry composition comprises deionized water and iron or an iron compound. The slurry composition can achieve high polishing rate on a phase-change memory device and improved polishing selectivity between a phase-change memory material and a polish stop layer (e.g., a silicon oxide film), can minimize the occurrence of processing imperfections (e.g., dishing and erosion), and can lower the etch rate on a phase-change memory material to provide a high-quality polished surface. Further provided is a method for polishing a phase-change memory device using the slurry composition.01-01-2009
20120097910Resistance Element and Inverting Buffer Circuit - There is provided a resistance element and an inverting buffer circuit to suppress a change in a resistance value caused by a potential of a semiconductor substrate in the neighborhood of the resistance element layer, a power line passing on or above the resistance element layer, or a signal line, without generating useless current or a distortion in a signal. In the resistance element 04-26-2012
20110108791PHASE CHANGE MATERIAL, A PHASE CHANGE RANDOM ACCESS MEMORY DEVICE INCLUDING THE PHASE CHANGE MATERIAL, AND A SEMICONDUCTOR STRUCTURE INCLUDING THE PHASE CHANGE MATERIAL - Methods of forming a phase change material are disclosed. The method includes forming a chalcogenide compound on a substrate and simultaneously applying a bias voltage to the substrate to alter the stoichiometry of the chalcogenide compound. In another embodiment, the method includes positioning a substrate and a deposition target having a first stoichiometry in a deposition chamber. A plasma is generated in the deposition chamber to form a phase change material on the substrate. The phase change material has a stoichiometry similar to the first stoichiometry. A bias voltage is applied to the substrate to convert the stoichiometry of the phase change material to a second stoichiometry. A phase change material, a phase change random access memory device, and a semiconductor structure are also disclosed.05-12-2011
20110006276SCHOTTKY DIODE SWITCH AND MEMORY UNITS CONTAINING THE SAME - A switching element that includes a first semiconductor layer, the first semiconductor layer having a first portion and a second portion; a second semiconductor layer, the second semiconductor layer having a first portion and a second portion; an insulating layer disposed between the first semiconductor layer and the second semiconductor layer; a first metal contact in contact with the first portion of the first semiconductor layer forming a first junction and in contact with the first portion of the second semiconductor layer forming a second junction; a second metal contact in contact with the second portion of the first semiconductor layer forming a third junction and in contact with the second portion of the second semiconductor layer forming a fourth junction, wherein the first junction and the fourth junction are Schottky contacts, and the second junction and the third junction are ohmic contacts.01-13-2011
20120305874Vertical Diodes for Non-Volatile Memory Device - A steering device. The steering device includes an n-type impurity region comprising a zinc oxide material and a p-type impurity region comprising a silicon germanium material. A pn junction region formed from the zinc oxide material and the silicon germanium material. The steering device is a serially coupled to a resistive switching device to provide rectification for the resistive switching device to form a non-volatile memory device.12-06-2012
20120305877NON-VOLATILE MEMORY DEVICE HAVING A RESISTANCE-CHANGEABLE ELEMENT AND METHOD OF FORMING THE SAME - A non-volatile memory device is provided wherein a lower molding layer is formed on a substrate; a first horizontal interconnection is formed on the lower molding layer; an upper molding layer is formed on the first horizontal interconnection; a pillar is formed connected to the substrate by vertically passing through the upper molding layer, the first horizontal interconnection and the lower molding layer. The pillar has a lower part and an upper part, wherein the lower part is disposed on the same level as the first horizontal interconnection and has a first width and the upper part is disposed on a higher level than the first horizontal interconnection and has a second width different from the first width.12-06-2012
20120305876SCHOTTKY DIODE, RESISTIVE MEMORY DEVICE HAVING SCHOTTKY DIODE AND METHOD OF MANUFACTURING THE SAME - A schottky diode, a resistive memory device including the schottky diode and a method of manufacturing the same. The resistive memory device includes a semiconductor substrate including a word line, a schottky diode formed on the word line, and a storage layer formed on the schottky diode. The schottky diode includes a first semiconductor layer, a conductive layer formed on the first semiconductor layer and having a lower work function than the first semiconductor layer, and a second semiconductor layer formed on the to conductive layer.12-06-2012
20120145984PUNCH-THROUGH DIODE - A punch-through diode and method of fabricating the same are disclosed herein. The punch-through diode may be used as a steering element in a memory device having a reversible resistivity-switching element. For example, a memory cell may include a reversible resistivity-switching element in series with a punch-through diode. The punch-through diode allows bipolar operation of a cross-point memory array. The punch-through diode may have a symmetrical non-linear current/voltage relationship. The punch-through diode has a high current at high bias for selected cells and a low leakage current at low bias for unselected cells. In other words, the ratio of Ion/Ioff is high. Therefore, the punch-through diode is compatible with bipolar switching in cross-point memory arrays having resistive switching elements.06-14-2012
20120037876Resistance Random Access Memory Structure for Enhanced Retention - A bistable resistance random access memory is described for enhancing the data retention in a resistance random access memory member. A dielectric member, e.g. the bottom dielectric member, underlies the resistance random access memory member which improves the SET/RESET window in the retention of information. The deposition of the bottom dielectric member is carried out by a plasma-enhanced chemical vapor deposition or by high-density-plasma chemical vapor deposition. One suitable material for constructing the bottom dielectric member is a silicon oxide. The bistable resistance random access memory includes a bottom dielectric member disposed between a resistance random access member and a bottom electrode or bottom contact plug. Additional layers including a bit line, a top contact plug, and a top electrode disposed over the top surface of the resistance random access memory member. Sides of the top electrode and the resistance random access memory member are substantially aligned with each other.02-16-2012
20120037875MIRRORED-GATE CELL FOR NON-VOLATILE MEMORY - A memory comprising at least one memory cell operationally connected to a bit line, a source line and a word line. The memory cell comprises a substrate having a first source contact, a second source contact, and a bit contact between the first source contact and the second source contact, a first transistor gate electrically connecting the first source contact and the bit contact and a second transistor gate electrically connecting the bit contact and the second source contact. The word line electrically connects the first transistor gate to the second transistor gate.02-16-2012
20120037874SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Any of a plurality of contact plugs which reaches a diffusion layer serving as a drain layer of an MOS transistor has an end provided in contact with a lower surface of a thin insulating film provided selectively on an interlayer insulating film. A phase change film constituted by GST to be a chalcogenide compound based phase change material is provided on the thin insulating film, and an upper electrode is provided thereon. Any of the plurality of contact plugs which reaches the diffusion layer serving as a source layer has an end connected directly to an end of a contact plug penetrating an interlayer insulating film.02-16-2012
20120037873MEMORY DEVICE - A memory device includes: first and second electrodes; a semiconductor layer of a first conduction type provided on the first electrode side; a solid electrolyte layer containing movable ions and provided on the second electrode side; and an amorphous semiconductor layer of a second conduction type which is provided between the semiconductor layer and the solid electrolyte layer so as to be in contact with the solid electrolyte layer and, at the time of application of voltage to the first and second electrodes, reversibly changes to the first conduction type.02-16-2012
20120037872MEMORY DEVICE - A memory device includes: an amorphous semiconductor layer of a first conduction type; a solid electrolyte layer containing movable ions and provided in contact with a part of one of faces of the amorphous semiconductor layer; a first electrode electrically connected to the amorphous semiconductor layer via the solid electrolyte layer; a second electrode electrically connected to one of the faces of the amorphous semiconductor layer; and a third electrode provided over the other face of the amorphous semiconductor layer with an insulating layer therebetween. At the time of application of voltage to the third electrode, at least a part of the amorphous semiconductor layer reversibly changes to a second conduction type.02-16-2012
20130200321POST-FABRICATION SELF-ALIGNED INITIALIZATION OF INTEGRATED DEVICES - Defining an active region of a phase change memory (PCM) cell including depositing a first layer of material having a first chemical composition. A second layer of material having a second chemical composition is deposited on top of the first layer of material. An electrical current pulse is applied to locally heat a region of the first layer of material and the second layer of material to cause at least one of an inter-diffusion and a liquid mixing of the first layer of material and the second layer of material. This results in in the PCM cell containing a self-aligned region that includes a phase change material that is a mixture of the first chemical composition and the second chemical composition.08-08-2013
20090039330Two-terminal resistance switching element with silicon, and semiconductor device - A two-terminal resistance switching element, wherein two silicon films each doped with an impurity are arranged with a gap width in the order of nanometers.02-12-2009
20110315943Memory Device Using A Dual Layer Conductive Metal Oxide Structure - Memory cell formation using ion implant isolated conductive metal oxide is disclosed, including forming a bottom electrode below un-etched conductive metal oxide layer(s), forming the un-etched conductive metal oxide layer(s) including depositing at least one layer of a conductive metal oxide (CMO) material (e.g., PrCaMnO12-29-2011
20090001338Seek-and-scan probe memory devices with nanostructures for improved bit size and resistance contrast when reading and writing to phase-change media - A seek-and-scan probe memory device comprising a patterned capping layer over a phase-change media, where the patterned capping layer defines the bit locations on the phase-change media. The patterned capping layer may be formed from self-assembled structures. In other embodiments, nanostructures are formed on the bottom electrode below the phase-change media to focus an applied electric field from the probe, so as to increase bit density and contrast. The nanostructures may be a regular or random array of nanostructures, formed by using a self-assembling material. The nanostructures may be conductive or non-conductive. Other embodiments are described and claimed.01-01-2009
20110101297SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device and a method of manufacturing the same with easy formation of a phase change film is realized, realizing high integration at the time of using a phase change film as a memory element.05-05-2011
20120043517NONVOLATILE SEMICONDUCTOR STORAGE DEVICE - A nonvolatile semiconductor storage device according to an embodiment includes a first line; a second line that intersects the first line; and a memory cell that includes a memory element and a non-ohmic element, the memory cell being provided at the intersection of the first line and the second line while the memory element and the non-ohmic element are series-connected, data being stored in the memory element according to a change of a resistance state, wherein the non-ohmic element includes a metallic layer, an intrinsic semiconductor layer that is joined to the metallic layer, and a doped semiconductor layer that is joined to the intrinsic semiconductor layer and contains a first dopant.02-23-2012
20120061639RESISTANCE CHANGE MEMORY - According to one embodiment, a resistance change memory includes a memory cell unit. The memory cell unit is configured to stack a resistance change element and a diode element having non-ohmic properties, and the diode element is configured to stack in order to a semiconductor layer having a first conductivity type, a semiconductor layer having a second conductivity type, and a semiconductor layer having the first conductivity type from the first interconnect layer side. An area density of dopant impurities in the semiconductor layer having the second conductivity type is larger than a sum total of area densities of dopant impurities in the two semiconductor layers having the first conductivity type, and smaller than double an area density of an electric flux number associated with a threshold electric field of an interband tunneling current of a material includes the semiconductor layer having the second conductivity type.03-15-2012
20120001143Switchable Junction with Intrinsic Diode - A switchable junction (01-05-2012
20120001141RRAM structure and method of making the same - An RRAM includes a resistive layer including a dielectric layer and surplus oxygen ions or nitrogen ions from a treatment on the dielectric layer after the dielectric layer is formed. When the RRAM is applied with a voltage, the oxygen ions or nitrogen ions occupy vacancies in the dielectric layer to increase resistance of the resistive layer. When the RRAM is applied with another voltage, the oxygen ions or nitrogen ions are removed from the vacancies to lower the resistance of the resistive layer.01-05-2012
20120001140VOLTAGE SENSITIVE RESISTOR (VSR) READ ONLY MEMORY - Disclosed is a voltage sensitive resistor (VSR) write once (WO) read only memory (ROM) device which includes a semiconductor device and a VSR connected to the semiconductor device. The VSR WO ROM device is a write once read only device. The VSR includes a CVD titanium nitride layer having residual titanium-carbon bonding such that the VSR is resistive as formed and can become less resistive by an order of 1001-05-2012
20120001142CARBON-BASED MEMORY ELEMENT - One embodiment of the disclosure can provide a storage layer of a resistive memory element comprising a resistance changeable material. The resistance changeable material can include carbon. Contact layers can be provided for contacting the storage layer. The storage layer can be disposed between a bottom contact layer and a top contact layer. The resistance changeable material can be annealed at a predetermined temperature over a predetermined annealing time for rearranging an atomic order of the resistance changeable material.01-05-2012
20110155988MEMORY ELEMENT AND MEMORY DEVICE - Provided are a memory element and a memory device. A memory layer is provided with an ion source layer. The ion source layer includes Zr (zirconium), Cu (copper), and Al (aluminum) as a metal element together with an ion conductive material such as S (sulfur), Se (selenium), and Te (tellurium) (chalcogen element). The amount of Al in the ion source layer is 30 to 50 atomic percent. The amount of Zr is preferably 7.5 to 25 atomic percent, and more preferably, the composition ratio of Zr to the chalcogen element in total included in the ion source layer (=Zr (atomic percent)/chalcogen element in total (atomic percent)) falls within a range from 0.2 to 0.74.06-30-2011
20110155987MEMORY ELEMENT AND MEMORY DEVICE - A memory element capable of simultaneously satisfying the number of repeating operation times and a low-voltage operation characteristic which are in a tradeoff relation is provided. The memory element has a high-resistivity layer and an ion source layer between a bottom electrode and a top electrode. The high-resistivity layer is made of an oxide containing Te. Any of elements other than Te such as Al, Zr, Ta, Hf, Si, Ge, Ni, Co, Cu, and Au may be added. In the case of adding Al to Te and also adding Cu and Zr, the composition ratio of the high-resistivity layer is preferably adjusted in the ranges of 30≦Te≦100 atomic %, 0≦Al≦70 atomic %, and 0≦Cu+Zr≦36 atomic % except for oxygen. The ion source layer is made of at least one kind of metal elements and at least one kind of chalcogen elements of Te, S, and Se.06-30-2011
20110155986DUAL RESISTANCE HEATER FOR PHASE CHANGE DEVICES AND MANUFACTURING METHOD THEREOF - A dual resistance heater for a phase change material region is formed by depositing a resistive material. The heater material is then exposed to an implantation or plasma which increases the resistance of the surface of the heater material relative to the remainder of the heater material. As a result, the portion of the heater material approximate to the phase change material region is a highly effective heater because of its high resistance, but the bulk of the heater material is not as resistive and, thus, does not increase the voltage drop and the current usage of the device.06-30-2011
20110155985PHASE CHANGE STRUCTURE, AND PHASE CHANGE MEMORY DEVICE - A phase change structure includes a first phase change material layer pattern and a second phase change material layer pattern. The first phase change material layer pattern may partially fill a high aspect ratio structure, and the second phase change material layer pattern may fully fill the high aspect ratio structure. The first phase change material layer pattern may include a first phase change material, and the second phase change material layer pattern may include a second phase change material having a composition substantially different from a composition of the first phase change material.06-30-2011
20110155984SELF-SELECTING PCM DEVICE NOT REQUIRING A DEDICATED SELECTOR TRANSISTOR - A Zinc Oxide (ZnO) layer deposited using Atomic Layer Deposition (ALD) over a phase-change material forms a self-selected storage device. The diode formed at the ZnO/GST interface shows both rectification and storage capabilities within the PCM architecture.06-30-2011
20120205606Nonvolatile Memory Device Using The Resistive Switching of Graphene Oxide And The Fabrication Method Thereof - Disclosed are an oxide-based nonvolatile memory with superior resistive switching characteristics and a method for preparing the same. More particularly, the disclosure relates to a nonvolatile memory device having a metal/reduced graphene oxide (r-GO) thin film/metal structure and a method for preparing the same.08-16-2012
20120056146RESISTIVE MEMORY ARCHITECTURES WITH MULTIPLE MEMORY CELLS PER ACCESS DEVICE - A resistive memory structure, for example, phase change memory structure, includes one access device and two or more resistive memory cells. Each memory cell is coupled to a rectifying device to prevent parallel leak current from flowing through non-selected memory cells. In an array of resistive memory bit structures, resistive memory cells from different memory bit structures are stacked and share rectifying devices.03-08-2012
20120056147LARGE ARRAY OF UPWARD POINTINIG P-I-N DIODES HAVING LARGE AND UNIFORM CURRENT - A circuit is provided that includes a plurality of vertically oriented p-i-n diodes. Each p-i-n diode is coupled to a resistivity-switching element and includes a bottom heavily doped p-type region. When a voltage between about 1.5 volts and about 3.0 volts is applied across each p-i-n diode, a current of at least 1.5 microamps flows through 99 percent of the p-i-n diodes. Numerous other aspects are also provided.03-08-2012
20120056145NONVOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a nonvolatile memory device includes a selection element layer and a nanomaterial aggregate layer. The selection element layer includes silicon. The nanomaterial aggregate layer is stacked on the selection element layer. The nanomaterial aggregate layer includes a plurality of micro conductive bodies and fine particles dispersed in a plurality of gaps between the micro conductive bodies. At least a surface of the fine particle is made of an insulating material other than silicon oxide.03-08-2012
20120007034PHASE-CHANGE MEMORY DEVICE HAVING MULTIPLE DIODES - A phase-change memory device with an improved current characteristic is provided. The phase-change memory device includes a metal word line, a semiconductor layer of a first conductivity type being in contact with the metal word line, and an auxiliary diode layer being in contact with metal word line and the semiconductor layer.01-12-2012
20120007033PHASE-CHANGE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A phase-change memory device and a method of manufacturing the same are provided. The method of manufacturing the phase-change memory device includes forming a heating electrode, having a pillar shape, on a semiconductor substrate, and forming a phase-change pattern passing through an upper surface of the heating electrode. A sidewall of the phase-change pattern is in contact with the upper surface of the heating electrode.01-12-2012
20120007032PHASE-CHANGE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A phase-change memory device with improved deposition characteristic and a method of fabricating the same are provided. The phase-change memory device includes a semiconductor substrate having a phase-change area, a first material-rich first phase-change layer forming an inner surface of the phase-change area and comprised of a hetero compound of the first material and a second material, and a second phase-change layer formed on a surface of the first phase-change layer to fill the phase-change area.01-12-2012
20120012804THERMAL DIODE DEVICE AND METHODS - A thermal diode comprising a superlyophobic surface, and a lyophilic surface separated from the superlyophobic surface defining a chamber. A liquid is disposed in the chamber, the liquid capable of phase changing during operation of the thermal diode. Methods of cooling and insulating bodies and rectifying heat transfer using the thermal diode.01-19-2012
20120012803NONVOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a nonvolatile memory device includes a lower electrode layer, a nanomaterial assembly layer, and an upper electrode layer. The nanomaterial assembly layer is provided on the lower electrode layer and includes a plurality of micro conductive bodies assembled via a gap. The upper electrode layer is provided on the nanomaterial assembly layer. The portion of the micro conductive bodies is buried at least in a lower part of the upper electrode layer.01-19-2012
20130009122NON-VOLATILE MEMORY DEVICE HAVING VARIABLE RESISTANCE ELEMENT AND METHOD OF FABRICATING THE SAME - A non-volatile memory device includes a lower molding layer, a horizontal interconnection line on the lower molding layer, an upper molding layer on the horizontal interconnection line, pillars extending vertically through the upper molding layer, the horizontal interconnection line, and the lower molding layer, and a buffer layer interposed between the pillars and the molding layers. The device also includes variable resistance material and a diode layer interposed between the pillars and the horizontal interconnection line.01-10-2013
20110049459NON-VOLATILE MEMORY DEVICE INCLUDING PHASE-CHANGE MATERIAL - A non-volatile memory device includes a lower electrode, a phase-change material layer formed on the lower electrode so as to be electrically connected to the lower electrode, and an upper electrode formed on the phase-change material layer so as to be electrically connected to the phase-change material layer. The phase-change material layer includes a phase-change material including a composition represented by the formula (I)03-03-2011
20110049458Non-volatile memory device including phase-change material - A non-volatile memory device including a phase-change material, which has a low operating voltage and low power consumption, includes a lower electrode; a phase-change material layer formed on the lower electrode so as to be electrically connected to the lower electrode, wherein the phase-change material layer includes a phase-change material having a composition represented by Sn03-03-2011
20110049457Non-volatile memory device including phase-change material - A non-volatile memory device including a phase-change material, which has a low operating voltage and low power consumption, includes a lower electrode; a phase-change material layer formed on the lower electrode so as to be electrically connected to the lower electrode, wherein the phase-change material layer includes a phase-change material having a composition represented by In03-03-2011
20110049456PHASE CHANGE STRUCTURE WITH COMPOSITE DOPING FOR PHASE CHANGE MEMORY - A memory device is described using a composite doped phase change material between a first electrode and a second electrode. A memory element of phase change material, such as a chalcogenide, is between the first and second electrodes and has an active region. The phase change material has a first dopant, such as silicon oxide, characterized by tending to segregate from the phase change material on grain boundaries in the active region, and has a second dopant, such as silicon, characterized by causing an increase in recrystallization temperature of, and/or suppressing void formation in, the phase change material in the active region.03-03-2011
20110049455WAFER BONDED ACCESS DEVICE FOR MULTI-LAYER PHASE CHANGE MEMORY USING LOCK-AND-KEY ALIGNMENT - A method for fabricating a multi-layer phase change memory device includes forming a phase change memory layer including a plurality of phase change memory elements on a word line formed on a plurality of semiconductor devices on a first semiconductor substrate, each phase change element having a notch formed at an upper surface thereof, forming an access device layer including plurality of access devices on a second semiconductor substrate, each access device having a conductive bump formed thereon, and combining the first and second semiconductor substrates and slidably inserting and locking each conductive bump of the plurality of access devices into each notch of the plurality of phase change memory elements to electrically connect the access devices to the phase change memory elements.03-03-2011
20110049454SEMICONDUCTOR DEVICE - In a phase-change memory, an interface layer is inserted between a chalcogenide material layer and a plug. The interface layer is arranged so as not to cover the entire interface of a plug-like electrode. When the plug is formed at an upper part than the chalcogenide layer, the degree of integration is increased. The interface layer is formed by carrying out sputtering using an oxide target, or, by forming a metal film by carrying out sputtering using a metal target followed by oxidizing the metal film in an oxidation atmosphere such as oxygen radical, oxygen plasma, etc.03-03-2011
20090146126PROBE-BASED MEMORY - Apparatuses, a method, and a system for a non-volatile, probe-based memory device are disclosed herein. In various embodiments, probe-based memory may be one-time programmable or rewritable nonvolatile probe-based memory.06-11-2009
20120305875PHASE-CHANGE RANDOM ACCESS MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a PCRAM device includes forming a switching device in a contact hole of a first interlayer insulating layer, forming a second interlayer insulating layer having an opening exposing the switching device, forming a lower electrode pattern along a sidewall of the second interlayer insulating layer to be coupled to the switching device, forming an insulating layer to be buried within the lower electrode pattern, forming a lower electrode by removing an exposed surface of the lower electrode pattern by a set height, wherein a height of a sidewall of the lower electrode is lower than that of the second interlayer insulating layer, forming a phase-change layer filing a hole of the second interlayer insulating layer from which the exposed surface of the lower electrode pattern is removed, and forming an upper electrode on the phase-change layer and a portion of the second interlayer insulating layer.12-06-2012
20100264391EPI SUBSTRATE WITH LOW DOPED EPI LAYER AND HIGH DOPED SI SUBSTRATE LAYER FOR MEDIA GROWTH ON EPI AND LOW CONTACT RESISTANCE TO BACK-SIDE SUBSTRATE - The fabrication of seek-scan probe (SSP) memory devices involves processing on both-sides of a wafer. However, there are temperature restrictions on the mover circuitry side of the wafer and doping level constrains for either side of wafer. Using a low doped EPI layer on a highly doped substrate solves this issue and provides good STO growth.10-21-2010
20120153247SEMICONDUCTOR DEVICE HAVING RESISTIVE DEVICE - A semiconductor memory device includes a plurality of word lines vertically formed on a surface of a semiconductor substrate, where each pair of the plurality of word lines form a set of word lines, a bit line formed parallel to the surface of the semiconductor substrate and disposed in plurality stacked between the word lines of each pair constituting the one set of word lines, and unit memory cells disposed between respective ones of the bit lines and an adjacent one of the pair of word lines of said one of the word line sets.06-21-2012
20110057161THERMALLY SHIELDED RESISTIVE MEMORY ELEMENT FOR LOW PROGRAMMING CURRENT - Various embodiments described herein provide a memory device including a variable resistance material having a thermally isolating and electrically conductive isolation region arranged between the variable resistance material and an electrode to allow for efficient heating of the variable resistance material by a programming current. An electrically and thermally isolating isolation region may be arranged around the variable resistance material.03-10-2011
20100096610PHASE-CHANGE MATERIAL MEMORY CELL - A memory cell includes a current-steering device, a phase-change material disposed thereover, and a heating element and/or a cooling element.04-22-2010
20110073825MEMORY DEVICE AND STORAGE APPARATUS - A memory device 03-31-2011
20120153248THREE-TERMINAL CASCADE SWITCH FOR CONTROLLING STATIC POWER CONSUMPTION IN INTEGRATED CIRCUITS - A switching circuit includes a plurality of three-terminal PCM switching devices connected between a voltage supply terminal and a sub-block of logic. Each of the switching devices includes a PCM disposed in contact between a first terminal and a second terminal, a heating device disposed in contact between the second terminal and a third terminal, the heating device positioned proximate the PCM, and configured to switch the conductivity of a transformable portion of the PCM between a lower resistance state and a higher resistance state; and an insulating layer configured to electrically isolate the heater from said PCM material, and the heater from the first terminal. The third terminal of a first of the PCM switching devices is coupled to a set/reset switch, and the third terminal of the remaining PCM switching devices is coupled to the second terminal of an adjacent PCM switching device in a cascade configuration.06-21-2012
20110089392MEMORY USING TUNNELING FIELD EFFECT TRANSISTORS - A memory includes a first tunneling field effect transistor including a first drain and a first source, the first drain coupled to a first resistive memory element. The memory includes a second tunneling field effect transistor including a second drain and sharing the first source, the second drain coupled to a second resistive memory element. The memory includes a first region coupled to the first source for providing a source node.04-21-2011
20110089391PUNCH-THROUGH DIODE STEERING ELEMENT - A storage system and method for forming a storage system that uses punch-through diodes as a steering element in series with a reversible resistivity-switching element is described. The punch-through diode allows bipolar operation of a cross-point memory array. The punch-through diode may have a symmetrical non-linear current/voltage relationship. The punch-through diode has a high current at high bias for selected cells and a low leakage current at low bias for unselected cells. Therefore, it is compatible with bipolar switching in cross-point memory arrays having resistive switching elements. The punch-through diode may be a N+/P−/N+ device or a P+/N−/P+ device.04-21-2011
20120211717SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor memory device in which the cell area can be decreased and the minimum feature size is not restricted by the thickness of the material forming the memory cell. In a semiconductor memory device, a gate insulating film, a channel extending in a direction X, and a resistance change element extending in the direction X are formed successively above multiple word lines extending in a direction Y, and a portion of the channel and a portion of the resistance change element are disposed above each of the plurality of the word lines. Such configuration can decrease the cell area and ensure the degree of design freedom.08-23-2012
20100288993PHASE CHANGE RANDOM ACCESS MEMORY FOR ACTIVELY REMOVING RESIDUAL HEAT AND METHOD OF MANUFACTURING THE SAME - A phase change random access memory for actively removing residual heat and a method of manufacturing the same are presented. The phase change random access memory includes a semiconductor substrate, a phase change pattern, a heating electrode and a cooling electrode. The phase change pattern is on the semiconductor substrate. The heating electrode is electrically coupled to the phase change pattern for heating the phase change pattern. The cooling electrode is electrically coupled to the phase change pattern for removing residual heat from the phase change pattern.11-18-2010
20120126194THERMALLY INSULATED PHASE CHANGE MATERIAL MEMORY CELLS - A memory cell structure and method for forming the same. The method includes forming a pore within a dielectric layer. The pore is formed over the center of an electrically conducting bottom electrode. The method includes depositing a thermally insulating layer along at least one sidewall of the pore. The thermally insulating layer isolates heat from phase change current to the volume of the pore. In one embodiment phase change material is deposited within the pore and the volume of the thermally insulating layer. In another embodiment a pore electrode is formed within the pore and the volume of the thermally insulating layer, with the phase change material being deposited above the pore electrode. The method also includes forming an electrically conducting top electrode above the phase change material.05-24-2012
20120126195Two terminal multi-layer thin film resistance switching device with a diffusion barrier and methods thereof - An electric-pulse-induced-resistance change device (EPIR device) is provided which is a resistance switching device. It has a buffer layer inserted between a first active resistance switching layer and a second active resistance switching layer, with both active switching layers connected to electrode layers directly or through additional buffer layers between the active resistance switching layers and the electrodes. This device in its simplest form has the structure: electrode-active layer-buffer layer-active layer-electrode. The second active resistance switching layer may, in the alternative, be an ion donating layer, such that the structure becomes: electrode-active layer-buffer layer-ion donating layer-electrode. The EPIR device is constructed to mitigate the retention challenge.05-24-2012
20100207090SOLID MEMORY - In one embodiment of the present invention, recording and erasing of data in PRAM have hitherto been performed based on a change in physical characteristics caused by primary phase-transformation of a crystalline state and an amorphous state of a chalcogen compound including Te which serves as a recording material. Since, however, a recording thin film is formed of a polycrystal but not a single crystal, a variation in resistance values occurs and a change in volume caused upon phase-transition has placed a limit on the number of times of readout of the record. The above problem is solved by preparing a solid memory having a superlattice structure with a thin film containing Sb and a thin film containing Te. The solid memory can realize the number of times of repeated recording and erasing of 1008-19-2010
20120211718SEMICONDUCTOR STORAGE DEVICE - There is provided a semiconductor storage device which is capable of further reducing a size of a memory cell, and increasing a storage capacity. Plural memory cells each including a transistor formed on a semiconductor substrate, and a variable resistive device having a resistance value changed by voltage supply and connected between source and drain terminals of the transistor are arranged longitudinally and in an array to configure a three-dimensional memory cell array. A memory cell structure has a double channel structure in which an inside of a switching transistor is filled with a variable resistance element, particularly, a phase change material. The switching transistor is turned off by application of a voltage to increase a channel resistance so that a current flows in the internal phase change material to operate the memory.08-23-2012
20120161093Via-Configurable High-Performance Logic Block Architecture - A via-configurable circuit block may contain chains of p-type and n-type transistors that may or may not be interconnected by means of configurable vias. Configurable vias may also be used to connect various transistor terminals to a ground line, a power line and/or to various terminals that may provide connections outside of the circuit block.06-28-2012
20120161092PHASE CHANGE MEMORY AND METHOD FOR FABRICATING THE SAME - The invention provides a phase change memory and a method for forming the phase change memory. The phase change memory includes a storage region and a peripheral circuit region. The peripheral circuit region has a peripheral substrate, a plurality of peripheral shallow trench isolation (STI) units in the peripheral substrate, and at least one MOS transistor on the peripheral substrate and between the peripheral STI units. The storage region has a storage substrate, an N-type ion buried layer on the storage substrate, a plurality of vertical LEDs on the N-type ion buried layer, a plurality of storage shallow trench isolation (STI) units between the vertical LEDs, and a plurality of phase change layers on the vertical LED and between the storage STI units. The storage STI units have thickness substantially equal to thickness of the vertical LEDs. The peripheral STI units have thickness substantially equal to thickness of the storage STI units. The N-type conductive region contains SiC. A top of P-type conductive region is flush with a top of the peripheral substrate. The N-type conductive region containing SiC reduces drain current through the vertical LED and raises current efficiency of the vertical LED. The peripheral circuit region can work normally without adverse influence on performance of the phase change memory.06-28-2012
20120211716Oxygen ion implanted conductive metal oxide re-writeable non-volatile memory device - A memory device having at least one layer of oxygen ion implanted conductive metal oxide (CMO) is disclosed. The oxygen ion implanted CMO includes mobile oxygen ions. The oxygen ion implanted CMO can be annealed and the annealing can optionally occur in an ambient. An insulating metal oxide (IMO) layer is in direct contact with the oxygenated CMO layer and is electrically in series with the oxygenated CMO layer. A two-terminal memory element is formed by the IMO and CMO layers. The oxygenated CMO layer includes additional mobile oxygen ions operative to improve data retention and cycling of the two-terminal memory element. As deposited, the CMO layer can lose mobile oxygen ions during the fabrication process and the ion implantation serves to increase a quantity of mobile oxygen ions in the CMO layer.08-23-2012
20110180774Phase Change Memory Device - Provided are a phase change memory device and a method for forming the phase change memory device. The method includes forming a phase change material layer by providing reactive radicals to a substrate. The reactive radicals may comprise precursors for a phase change material and nitrogen.07-28-2011
20120313067SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - A memory device includes a lower interconnection in a semiconductor substrate, the lower interconnection being made of a material different from the semiconductor substrate, a selection element on the lower interconnection, and a memory element on the selection element.12-13-2012
20120313064SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor memory device includes a cell array layer having a memory cell. The memory cell has a current control device, a variable resistance device and a metal layer for silicide. A method for manufacturing the semiconductor memory device includes: forming the metal layer for silicide on a semiconductor layer for forming the current control device and a variable resistance device layer; selectively removing the variable resistance device layer and the metal layer through first etching; forming a first protective layer to cover at least a side surface of the metal layer exposed by the first etching; selectively removing a part of the semiconductor layer, through second etching; and forming a second protective layer to cover the variable resistance device layer, the metal layer for silicide, and the semiconductor layer.12-13-2012
20120313065SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor memory device includes a cell array layer including a first wire, a memory cell stacked on the first wire, and a second wire formed on the memory cell. The memory cell includes a variable resistance element and a current control element The current control element includes a first conductivity-type semiconductor into which a first impurity is doped, an i-type semiconductor in contact with the first conductivity-type semiconductor, a second conductivity-type semiconductor into which a second impurity is doped, and an impact ionization acceleration unit being formed between the i-type semiconductor and one of the first conductivity-type semiconductor and the second conductivity-type semiconductor.12-13-2012
20120313063NONVOLATILE MEMORY DEVICE HAVING AN ELECTRODE INTERFACE COUPLING REGION - Embodiments of the invention generally relate to a resistive switching nonvolatile memory device having an interface layer structure disposed between at least one of the electrodes and a variable resistance layer formed in the nonvolatile memory device, and a method of forming the same. Typically, resistive switching memory elements may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices, such as digital cameras, mobile telephones, handheld computers, and music players. In one configuration of the resistive switching nonvolatile memory device, the interface layer structure comprises a passivation region, an interface coupling region, and/or a variable resistance layer interface region that are configured to adjust the nonvolatile memory device's performance, such as lowering the formed device's switching currents and reducing the device's forming voltage, and reducing the performance variation from one formed device to another.12-13-2012
20110186797MEMORY CELL THAT INCLUDES A SIDEWALL COLLAR FOR PILLAR ISOLATION AND METHODS OF FORMING THE SAME - In a first embodiment, a method of forming a memory cell is provided that includes (a) forming one or more layers of steering element material above a substrate; (b) etching a portion of the steering element material to form a pillar of steering element material having an exposed sidewall; (c) forming a sidewall collar along the exposed sidewall of the pillar; and (d) forming a memory cell using the pillar. Numerous other aspects are provided.08-04-2011
20100051894DEVICE FOR STORING DATA WITH OPTICAL ADDRESSING - Data storage device, comprising: 03-04-2010
20100051893PLASMA TREATING METHODS OF FABRICATING PHASE CHANGE MEMORY DEVICES, AND MEMORY DEVICES SO FABRICATED - Phase change memory devices may be fabricated by forming a first electrode on a substrate and forming a chalcogenide material on the first electrode. The chalcogenide material is plasma treated sufficiently to induce a plasma species throughout the chalcogenide material. A second electrode is formed on the chalcogenide material. Related devices are also described.03-04-2010
20100051892NONVOLATILE SEMICONDUCTOR MEMORY APPARATUS AND MANUFACTURING METHOD THEREOF - A nonvolatile semiconductor memory apparatus (03-04-2010
20100051891Electronic element including ferroelectric substance film and method of manufacturing the same - A laminated film structure, method of manufacturing, and a preferable electronic element using the structure. The effective polarization into the electric field can be realized in the direction of crystal axis by enhancing the crystal property and alignment property of the ferroelectric substance film formed through epitaxial growth with reference to the plane alignment of semiconductor substrate. After the yttrium stabilized zirconium film and a film of the rock salt structure are sequentially formed with epitaxial growth on a semiconductor substrate, the ferroelectric substance film of simple Perovskite structure is also formed with epitaxial growth. The ferroelectric substance film can improve the crystal property and alignment property thereof by rotating the plane for 45 degrees within the plane for the crystal axis of the yttrium stabilized zirconium.03-04-2010
20090095948Programmable Resistive Memory with Diode Structure - Programmable resistive memory cells are accessed by semiconductor diode structures. Manufacturing methods and integrated circuits for programmable resistive elements with such diode structures are also disclosed.04-16-2009
20120256150Integrated Circuitry, Methods of Forming Memory Cells, and Methods of Patterning Platinum-Containing Material - Some embodiments include methods of patterning platinum-containing material. An opening may be formed to extend into an oxide. Platinum-containing material may be formed over and directly against an upper surface of the oxide, and within the opening. The platinum-containing material within the opening may be a plug having a lateral periphery. The lateral periphery of the plug may be directly against the oxide. The platinum-containing material may be subjected to polishing to remove the platinum-containing material from over the upper surface of the oxide. The polishing may delaminate the platinum-containing material from the oxide, and may remove the platinum-containing material from over the oxide with an effective selectivity for the platinum-containing material relative to the oxide of at least about 5:1. Some embodiments include methods of forming memory cells. Some embodiments include integrated circuitry having platinum-containing material within an opening in an oxide and directly against the oxide.10-11-2012
20120256151Memory Cells, Methods of Forming Memory Cells and Methods of Forming Memory Arrays - Some embodiments include memory cells which have multiple programmable material structures between a pair of electrodes. One of the programmable material structures has a first edge, and another of the programmable material structures has a second edge that contacts the first edge. Some embodiments include methods of forming an array of memory cells. First programmable material segments are formed over bottom electrodes. The first programmable material segments extend along a first axis. Lines of second programmable material are formed over the first programmable material segments, and are formed to extend along a second axis that intersects the first axis. The second programmable material lines have lower surfaces that contact upper surfaces of the first programmable material segments. Top electrode lines are formed over the second programmable material lines.10-11-2012
20120313068NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND A MANUFACTURING METHOD THEREOF - Provided is a resistance change type nonvolatile semiconductor storage device including a diode capable of passing therethrough a sufficient current to a resistance changing operation even when the memory cell is miniaturized. A nonvolatile semiconductor storage device has first wires extending in X direction, second wires extending in Y direction, and memory cells disposed at intersection points of the first wires and the second wires. The memory cell includes a diode disposed over the first wire, and coupled to the first wire at one end, and a resistance change part disposed over the diode, and series-coupled to the diode at one end, and coupled to the second wire at the other end, and storing information through changes in resistance value. The diode includes a first conductivity type first semiconductor layer, and a second conductivity type second semiconductor layer extending into the inside of the first semiconductor layer.12-13-2012
20120313066NONVOLATILE MEMORY DEVICES, NONVOLATILE MEMORY CELLS AND METHODS OF MANUFACTURING NONVOLATILE MEMORY DEVICES - A nonvolatile memory cell includes first and second interlayer insulating films which are separated from each other and are stacked sequentially, a first electrode which penetrates the first interlayer insulating film and the second interlayer insulating film, a resistance change film which is formed along a side surface of the first electrode and extends parallel to the first electrode, and a second electrode which is formed between the first interlayer insulating film and the second interlayer insulating film. The second electrode includes a conductive film which is made of metal and a diffusion preventing film which prevents diffusion of a conductive material contained in the conductive film.12-13-2012
20120175582PHASE-CHANGE RANDOM ACCESS MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - The PCRAM device includes a semiconductor substrate including a switching device; an interlayer insulating layer having a heating electrode contact hole exposing the switching device, a heating electrode formed to be extended along a side of the interlayer insulating layer in the heating electrode contact hole, wherein the heating electrode has a width gradually increased toward a bottom of the heating electrode and is in contact with the switching device, first and second phase-change layers formed within the heating electrode contact hole that includes the heating electrode, and a phase-change separation layer formed in the heating electrode contact hole between the first and second phase-change layers.07-12-2012
20120175581SWITCHING DEVICE AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - A semiconductor memory device using a diode as a switching device is disclosed. The switching device may enhance on and off characteristics at the same time. The switching device includes a diode including a first conductive layer and a second conductive layer stacked therein, where the first conductive layer and the second conductive layer have complementary conductive types to each other, a control electrode surrounding the first conductive layer, and an insulation layer disposed between the first conductive layer and the control electrode.07-12-2012
20120074370PHASE CHANGE MEMORY STRUCTURES AND METHODS - Methods, devices, and systems associated with phase change memory structures are described herein. One or more embodiments of the present disclosure can reduce thermal crosstalk associated with phase change memory cells, which can provide various benefits including improved data reliability and retention and decreased read and/or write times, among various other benefits. One or more embodiments can reduce the number of processing steps associated with providing local interconnects to phase change memory arrays.03-29-2012
20120074369NONVOLATILE MEMORY APPARATUS, NONVOLATILE MEMORY ELEMENT, AND NONVOLATILE MEMORY ELEMENT ARRAY - A nonvolatile memory apparatus includes a first electrode, a second electrode, a variable resistance layer, a resistance value of the variable resistance layer reversibly varying between a plurality of resistance states based on an electric signal applied between the electrodes. The variable resistance layer includes at least a tantalum oxide, and is configured to satisfy 003-29-2012
20120074367COUNTER DOPING COMPENSATION METHODS TO IMPROVE DIODE PERFORMANCE - A method of forming a memory cell is provided, the method including forming a diode including a first region having a first conductivity type, counter-doping the diode to change the first region to a second conductivity type, and forming a memory element coupled in series with the diode. Other aspects are also provided.03-29-2012
20120074368SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor memory device having a diode and a transistor connected in series, which prevents carriers from going from the diode into the transistor, thereby reducing the possibility of transistor deterioration. A structure to annihilate carriers from the diode is provided between a channel layer of the transistor and a diode semiconductor layer of the diode where the carriers are generated.03-29-2012
20100283027MULTI-VALUE RECORDING PHASE-CHANGE MEMORY DEVICE, MULTI-VALUE RECORDING PHASE-CHANGE CHANNEL TRANSISTOR, AND MEMORY CELL ARRAY - A multi-value recording phase-change memory device that can stably record multi-value information, and that can reproduce information with high reliability, comprises a first electrode layer 11-11-2010
20100001251PHASE CHANGE MEMORY DEVICE IN WHICH A DISTANCE BETWEEN A LOWER ELECTRODE AND A GROUND LINE IS INCREASED TO SECURE THE SENSING MARGIN OF A CELL AND METHOD FOR MANUFACTURING THE SAME - A phase change memory device includes a semiconductor substrate having active regions and an isolation structure; gate lines extending in a direction perpendicular to the active regions; a source region and a drain region formed in a surface of each active region; a dot type lower electrode including a first contact plug formed in the drain region; second contact plugs formed in the source region and the isolation structure forming a line parallel to the gate line; a lower electrode contact formed on the lower electrode; a phase change layer and an upper electrode formed on the lower electrode contact; an upper electrode contact formed on the upper electrode; contacts for ground lines, formed between the active regions to come into contact with the second contact plugs; a bit line formed in the active region; and ground lines formed between the active regions.01-07-2010
20120256153DIODE FOR VARIABLE-RESISTANCE MATERIAL MEMORIES, PROCESSES OF FORMING SAME, AND METHODS OF USING SAME - A variable-resistance material memory (VRMM) device includes a container conductor disposed over an epitaxial semiconductive prominence that is coupled to a VRMM. A VRMM device may also include a conductive plug in a recess that is coupled to a VRMM. A VRMM array may also include a conductive plug in a surrounding recess that is coupled to a VRMM. Apparatuses include the VRMM with one of the diode constructions.10-11-2012
20120256152SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a semiconductor device includes: forming a first insulating film that covers a substrate; forming a conductive plug that penetrates the first insulating film; forming a hole portion on the conductive plug by partly removing upper part of the conductive plug, wherein the hole portion has a top surface of the conductive plug as a bottom surface, and has the first insulating film of a portion that covered the partly removed conductive plug as a sidewall; forming a sidewall insulating film that exposes a part of the bottom surface of the hole portion while covering the sidewall of the hole portion and a bottom portion of the hole portion; forming a variable resistance film that covers the sidewall insulating film and the bottom surface of the hole portion; and forming a conductive film that covers the variable resistance film.10-11-2012
20120187360SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FABRICATING THE SAME - A semiconductor memory device includes a lower wiring disposed on a first region of a substrate and a gate electrode disposed on a second region of the substrate. The lower wiring includes substantially the same conductive material as the gate electrode. A wiring-insulating layer is interposed between the lower wiring and the substrate, and a gate insulating layer is interposed between the gate electrode and the substrate. A diode is disposed on the lower wiring, and a variable resistance element is electrically coupled to the diode.07-26-2012
20090020740RESISTIVE MEMORY STRUCTURE WITH BUFFER LAYER - A memory device comprises first and second electrodes with a memory element and a buffer layer located between and electrically coupled to them. The memory element comprises one or more metal oxygen compounds. The buffer layer comprises at least one of an oxide and a nitride. Another memory device comprises first and second electrodes with a memory element and a buffer layer, having a thickness of less than 50 Å, located between and electrically coupled to them. The memory comprises one or more metal oxygen compounds. An example of a method of fabricating a memory device includes forming first and second electrodes. A memory, located between and electrically coupled to the first and the second electrodes, is formed; the memory comprises one or more metal oxygen compounds and the buffer layer comprises at least one of an oxide and a nitride.01-22-2009
20090020738INTEGRATED CIRCUIT INCLUDING FORCE-FILLED RESISTIVITY CHANGING MATERIAL - An integrated circuit includes a first electrode, a second electrode, and force-filled resistivity changing material electrically coupled to the first electrode and the second electrode.01-22-2009
20120261635RESISTIVE RANDOM ACCESS MEMORY (RAM) CELL AND METHOD FOR FORMING - A resistive random access memory cell over a substrate includes a memory stack structure and a sidewall spacer. The memory stack structure is over the substrate and includes a first electrode layer, a second electrode layer, and a metal oxide layer between the first electrode layer and the second electrode layer. The metal oxide layer has a sidewall. The sidewall spacer is adjacent to the sidewall and has a composition including silicon, carbon, and nitrogen.10-18-2012
20120228574VARIABLE RESISTIVE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A variable resistive memory device includes a substrate comprising a cell region and a peripheral region, a word line extending in a first direction formed on the substrate of the cell region, a switching element formed on the word line, a variable resistance layer formed on the word line, and at least one transistor comprising a gate stack, the gate stack formed on the substrate of the peripheral region, wherein the word line comprises a metal layer formed at a same level as the gate stack.09-13-2012
20110121250HIGH INTEGRATION PHASE CHANGE MEMORY DEVICE HAVING REDUCED THICKNESS PHASE CHANGE LAYER AND FABRICATION METHOD THEREOF - A high integration phase change memory device includes a semiconductor substrate including an access device, a heating electrode formed on the access device, a phase change nano band formed on the heating electrode, and an interlayer insulating layer for supporting the phase change nano band formed in both sides of the phase change nano band.05-26-2011
20080296551RESISTANCE MEMORY ELEMENT AND METHOD OF MANUFACTURING THE SAME - A resistance memory element having a pair of electrodes and an insulating film sandwiched between a pair of electrodes includes a plurality of cylindrical electrodes of a cylindrical structure of carbon formed in a region of at least one of the pair of electrodes, which is in contact with the insulating film. Thus, the position of the filament-shaped current path which contributes to the resistance states of the resistance memory element can be controlled by the positions and the density of the cylindrical electrodes.12-04-2008
20080296550Resistive random access memory device and methods of manufacturing and operating the same - Provided may be a resistive random access memory (RRAM) device and methods of manufacturing and operating the same. The resistive random access memory device may include at least one first electrode, at least one second electrode spaced apart from the at least one first electrode, a first structure including a first resistance-changing layer between the at least one first and second electrodes, and a first switching element electrically connected to the first resistance-changing layer, wherein at least one of the first and second electrodes include an alloy layer having a noble metal and a base metal.12-04-2008
20100327250PHASE CHANGE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A phase change memory device having a strain transistor and a method of making the same are presented. The phase change memory device includes a semiconductor substrate, a junction word line, switching diodes, and a strain transistor. The semiconductor substrate includes a cell area and a core/peri area. The junction word line is formed in the cell area of the semiconductor substrate and includes a strain stress supplying layer doped with impurities. The switching diodes are electrically coupled to the junction word line. The strain transistor is formed in the core/peri area of the substrate and acts as a driving transistor.12-30-2010
20100327251PHASE CHANGE MEMORY DEVICE HAVING PARTIALLY CONFINED HEATING ELECTRODES CAPABLE OF REDUCING HEATING DISTURBANCES BETWEEN ADJACENT MEMORY CELLS - A phase change memory device having partially confined heating electrodes capable of reducing thermal disturbances between adjacent memory cells is presented. The phase change memory device includes a plurality of active regions, a plurality of switching elements, a plurality of heating electrodes, and a plurality of phase change structure lines. The active regions being linear and parallel to each other. The switching elements are coupled to the active regions. The heating electrodes are on and coupled to the switching elements. The phase change structure lines are coupled to the heating electrodes such that the phase change structure lines are substantially vertical to the active regions. The phase change structure lines includes a plurality of plugs projecting downwards that couple to overlapped portions of the heating electrodes.12-30-2010
20100327248CELL PATTERNING WITH MULTIPLE HARD MASKS - A method of making a memory cell or magnetic element by using two hard masks. The method includes first patterning a second hard mask to form a reduced second hard mask, with a first hard mask being an etch stop for the patterning process, and then patterning the first hard mask to form a reduced first hard mask by using the reduced second hard mask as a mask and using an etch stop layer as an etch stop. After patterning both hard masks, then patterning a functional layer by using the reduced first hard mask as a mask. In the resulting memory cell, the first hard mask layer is also a top lead, and the diameter of the first hard mask layer is at least essentially the same as the diameter of the etch stop layer, the adhesion layer, and the functional layer.12-30-2010
20100327247METHOD AND SYSTEM OF USING NANOTUBE FABRICS AS JOULE HEATING ELEMENTS FOR MEMORIES AND OTHER APPLICATIONS - Methods and systems of using nanotube elements as joule heating elements for memories and other applications. Under one aspect, a method includes providing an electrical stimulus, regulated by a drive circuit, through a nanotube element in order to heat an adjacent article. Further, a detection circuit electrically gauges the state of the article. The article heated by the nanotube element is, in preferred embodiments, a phase changing material, hi memory applications, the invention may be used as a small-scale CRAM capable of employing small amounts of current to induce rapid, large temperature changes in a chalcogenide material. Under various embodiments of the disclosed invention, the nanotube element is composed of a non-woven nanotube fabric which is either suspended from supports and positioned adjacent to the phase change material or is disposed on a substrate and in direct contact with the phase change material. A plurality of designs using various geometric orientations of nanotube fabrics, phase change materials, and drive and detection circuitry is disclosed. Additionally, methods of fabricating nanotube heat emitters are disclosed.12-30-2010
20120267595MEMORY COMPONENT AND A MEMORY CELL - According to embodiments of the present invention, a memory component is provided. The memory component includes a storage component comprising a resistance changing material; and an electrical contact coupled to the storage component, wherein the electrical contact comprises silicide, wherein the memory component is free of a metal layer between the storage component and the electrical contact, and wherein the electrical contact is free of a metal layer.10-25-2012
20110210302SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate of a first conductivity type, a first insulating film region that is embedded in a trench formed on the semiconductor substrate, a gate electrode that covers a lower surface of the first insulating film region, and a gate insulating film that is provided between the gate electrode and the semiconductor substrate. The semiconductor device further includes a first diffusion region that covers a first side surface of the first insulating film region, a second diffusion region that covers a second side surface of the first insulating film region, and a third diffusion region that covers an upper surface of the second diffusion region. A selective element includes a field-effect transistor that is constituted by the gate electrode, the first diffusion region, and the second diffusion region, and a bipolar transistor that is constituted by the substrate and the second and third diffusion regions.09-01-2011
20110227021POST DEPOSITION METHOD FOR REGROWTH OF CRYSTALLINE PHASE CHANGE MATERIAL - Techniques for forming a phase change memory cell. An example apparatus includes a substrate and a bottom electrode carried by the substrate. The bottom electrode is a thermal conductor. A phase change layer, including phase change material, is disposed over the bottom electrode. A thermal insulating layer is disposed above the phase change layer. A heater is configured to temporarily melt the phase change material such that the phase change material crystallizes without voids within a switching region after melting.09-22-2011
20110227020BOTTOM ELECTRODES FOR USE WITH METAL OXIDE RESISTIVITY SWITCHING LAYERS - In a first aspect, a metal-insulator-metal (MIM) stack is provided that includes (1) a first conductive layer comprising a silicon-germanium (SiGe) alloy; (2) a resistivity-switching layer comprising a metal oxide layer formed above the first conductive layer; and (3) a second conductive layer formed above the resistivity-switching layer. A memory cell may be formed from the MIM stack. Numerous other aspects are provided.09-22-2011
20110227018MAGNETORESISTANCE ELEMENT, METHOD OF MANUFACTURING THE SAME, AND STORAGE MEDIUM USED IN THE MANUFACTURING METHOD - An embodiment of the invention provides a magnetoresistance element with an MR ratio higher than that of the related art and a method of manufacturing the same.09-22-2011
20120080657LOW OPERATIONAL CURRENT PHASE CHANGE MEMORY STRUCTURES - Memory cells described herein have an increased current density at lateral edges of the active region compared to that of conventional mushroom-type memory cells, resulting in improved operational current efficiency. As a result, the amount of heat generated within the lateral edges per unit value of current is increased relative to that of conventional mushroom-type memory cells. Therefore, the amount of current needed to induce phase change is reduced.04-05-2012
20120080656Graphene oxide memory devices and method of fabricating the same - A graphene oxide memory device includes a substrate, a lower electrode disposed on the substrate, an electron channel layer disposed on the lower electrode by using a graphene oxide, and an upper electrode disposed on the electron channel layer.04-05-2012
20120319069Phase Change Memory Device - Provided are a phase change memory device and a method for forming the phase change memory device. The method includes forming a phase change material layer by providing reactive radicals to a substrate. The reactive radicals may comprise precursors for a phase change material and nitrogen.12-20-2012
20120280198GCIB-TREATED RESISTIVE DEVICE - The present disclosure includes GCIB-treated resistive devices, devices utilizing GCIB-treated resistive devices (e.g., as switches, memory cells), and methods for forming the GCIB-treated resistive devices. One method of forming a GCIB-treated resistive device includes forming a lower electrode, and forming an oxide material on the lower electrode. The oxide material is exposed to a gas cluster ion beam (GCIB) until a change in resistance of a first portion of the oxide material relative to the resistance of a second portion of the oxide material. An upper electrode is formed on the first portion.11-08-2012
20110278529MEMORY EMPLOYING DIAMOND-LIKE CARBON RESISTIVITY-SWITCHABLE MATERIAL AND METHODS OF FORMING THE SAME - In a first aspect, a method of forming a memory cell having a diamond like carbon (DLC) resistivity-switching material is provided that includes (1) forming a metal-insulator-metal (MIM) stack that includes (a) a first conductive layer; (b) a DLC switching layer above the first conductive layer; and (c) a second conductive layer above the DLC switching layer; (2) forming a compressive dielectric liner along a sidewall of the MIM stack; and (3) forming a steering element coupled to the MIM stack. Numerous other aspects are provided.11-17-2011
20110278528SELF ALIGNED FIN-TYPE PROGRAMMABLE MEMORY CELL - A fin-type programmable memory cell includes a bottom electrode electrically coupled to an access device, a top electrode, and an L-shaped memory material element electrically coupled to the bottom and top electrodes. A memory array includes an array of such memory cells, electrically coupled to an array of access devices. Method for making a memory cell, includes: forming a dielectric support layer over a bottom electrode, the dielectric support layer having an upper surface; forming a cavity through the dielectric support layer, exposing a surface of the bottom electrode and defining a dielectric support structure having a sidewall; forming a film of memory material over the dielectric support structure and in the cavity; depositing a dielectric spacer layer over the memory material film; forming a dielectric sidewall spacer from the dielectric spacer layer and a memory material structure having a generally horizontal portion underlying the dielectric sidewall spacer and a generally vertical portion between the dielectric sidewall spacer and the sidewall of the dielectric support structure; forming a dielectric fill; planarizing the dielectric fill to expose upper ends of the vertical portion of the memory material structure; depositing a top electrode material over the planarized dielectric fill; and forming a top electrode from the top electrode material and a memory material element from the memory material structure.11-17-2011
20120326112PHASE-CHANGE RANDOM ACCESS MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A phase-change random access memory (PCRAM) device and a method of manufacturing the same are provided. The PCRAM device includes a semiconductor substrate, a junction word line formed on the semiconductor substrate, an epitaxial word line formed on the junction word line, and a switching device formed on the epitaxial word line.12-27-2012
20120326111Ge-RICH GST-212 PHASE CHANGE MEMORY MATERIALS - A phase change material comprises Ge12-27-2012
20120091417MULTISTATE NONVOLATILE MEMORY ELEMENTS - Multistate nonvolatile memory elements are provided. The multistate nonvolatile memory elements contain multiple layers. Each layer may be based on a different bistable material. The bistable materials may be resistive switching materials such as resistive switching metal oxides. Optional conductor layers and current steering elements may be connected in series with the bistable resistive switching metal oxide layers.04-19-2012
20120091416Phase Change Material for a Phase Change Memory Device and Method for Adjusting the Resistivity of the Material - A phase change material for use in a phase change memory device comprises germanium-antimony-tellurium-indium, wherein the phase change material comprises in total more than 30 at % antimony, preferably 5-16 at % germanium, 30-60 at % antimony, 25-51 at % tellurium, and 2-33% at % indium.04-19-2012
20120091415NONVOLATILE MEMORY DEVICE, NONVOLATILE MEMORY DEVICE GROUP, AND MANUFACTURING METHOD THEREOF - A nonvolatile memory device group includes: (A) a first insulating layer; (B) a second insulating layer that has a first concavity and a second concavity communicating with the first concavity and having a width larger than that of the first concavity and that is disposed on the first insulating layer; (C) a plurality of electrodes that are disposed in the first insulating layer and the top surface of which is exposed from the bottom surface of the first concavity; (D) an information storage layer that is formed on the side walls and the bottom surfaces of the first concavity and the second concavity; and (E) a conductive material layer that is filled in a space surrounded with the information storage layer in the second concavity.04-19-2012
20120091414SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a plurality of silicon films. The plurality of silicon films are disposed on one plane and are made of polysilicon containing an impurity. A crystal orientation of each of the silicon films is a (311) orientation.04-19-2012
20120091413Three Dimensional Horizontal Diode Non-Volatile Memory Array and Method of Making Thereof - A non-volatile memory device contains a three dimensional stack of horizontal diodes located in a trench in an insulating material, a plurality of storage elements, a plurality of word lines extending substantially vertically, and a plurality of bit lines. Each of the plurality of bit lines has a first portion that extends up along at least one side of the trench and a second portion that extends substantially horizontally through the three dimensional stack of the horizontal diodes. Each of the horizontal diodes is a steering element of a respective non-volatile memory cell of the non-volatile memory device, and each of the plurality of storage elements is located adjacent to a respective steering element.04-19-2012
20120286225SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device and a method of manufacturing the same with easy formation of a phase change film is realized, realizing high integration and using a phase change film as a memory element. Between a MISFET of a region forming one memory cell and an adjoining MISFET, each MISFET source adjoins in the front surface of an insulating semiconductor substrate. A multi-layer structure of a phase change film and electric conduction film of specific resistance lower than the specific resistance is formed in plan view of the front surface of a semiconductor substrate ranging over each source of both MISFETs, and a plug is stacked thereon. The multi-layer structure functions as a wiring extending and existing in parallel on the surface of the semiconductor substrate, and an electric conduction film sends current in a parallel direction on the surface of the semiconductor substrate.11-15-2012
20100096609PHASE CHANGE MEMORY DEVICE HAVING A LAYERED PHASE CHANGE LAYER COMPOSED OF MULTIPLE PHASE CHANGE MATERIALS AND METHOD FOR MANUFACTURING THE SAME - A phase change memory device that has a layered phase change layer composed of multiple phase change materials is presented. The device includes a semiconductor substrate, an interlayer dielectric layer, a high-temperature crystallization phase change, a low-temperature crystallization phase change layer, and an upper electrode. The interlayer dielectric layer formed on the semiconductor substrate and the high-temperature crystallization phase change layer is formed on the interlayer dielectric layer. The low-temperature crystallization phase change layer is formed over the high-temperature crystallization phase change layer. The upper electrode is formed over the low-temperature crystallization phase change layer. An optional diffusion barrier may be interposed between the two phase change layers.04-22-2010
20100133496Resistive random access memory - A RRAM may include a first electrode, a second electrode, and a memory resistant layer between the first and second electrodes, wherein the memory resistant layer may include a transition metal oxide doped with a metal having a high oxygen affinity. Because a RRAM includes a memory resistant layer doped with a material having a high oxygen affinity, the RRAM may be stably driven at higher temperatures.06-03-2010
20130015421PHASE-CHANGE RANDOM ACCESS MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAMEAANM SIM; Joon SeopAACI Ichon-siAACO KRAAGP SIM; Joon Seop Ichon-si KRAANM Son; Jae HyunAACI Ichon-siAACO KRAAGP Son; Jae Hyun Ichon-si KRAANM Lee; Dae WoongAACI Ichon-siAACO KRAAGP Lee; Dae Woong Ichon-si KRAANM Oh; Young HoonAACI Ichon-siAACO KRAAGP Oh; Young Hoon Ichon-si KR - A phase change random access memory (PCRAM) device and method of manufacturing the same are provided. The PCRAM includes bottom electrode contacts formed on a semiconductor substrate that includes a lower structure, phase-change material patterns in contact with the bottom electrode contacts, respectively, and heat insulating units formed between the phase-change material patterns.01-17-2013
20130020547PHASE CHANGE CURRENT DENSITY CONTROL STRUCTURE - A phase change memory element and method of forming the same. The memory element includes first and second electrodes. A first layer of phase change material is between the first and second electrodes. A second layer including a metal-chalcogenide material is also between the first and second electrodes and is one of a phase change material and a conductive material. An insulating layer is between the first and second layers. There is at least one opening in the insulating layer providing contact between the first and second layers.01-24-2013
20120241706RESISTANCE SWITCHABLE CONDUCTIVE FILLER FOR RERAM AND ITS PREPARATION METHOD - Disclosed are a resistive random-access memory (ReRAM) based on resistive switching using a resistance-switchable conductive filler and a method for preparing the same. When a resistance-switchable conductive filler prepared by coating a conductive filler with a material whose resistance is changeable is mixed with a dielectric material, the dielectric material is given the resistive switching characteristics without losing its inherent properties. Therefore, various resistance-switchable materials having various properties can be prepared by mixing the resistance-switchable conductive filler with different dielectric materials. The resulting resistance-switchable material shows resistive switching characteristics comparable to those of the existing metal oxide film-based resistance-switchable materials. Accordingly, a ReRAM device having the inherent properties of a dielectric material can be prepared using the resistance-switchable conductive filler.09-27-2012
20120241705Methods of Forming Memory Cells. - Some embodiments include methods of forming memory cells. Programmable material may be formed directly adjacent another material. A dopant implant may be utilized to improve adherence of the programmable material to the other material by inducing bonding of the programmable material to the other material, and/or by scattering the programmable material and the other material across an interface between them. The memory cells may include first electrode material, first ovonic material, second electrode material, second ovonic material and third electrode material. The various electrode materials and ovonic materials may join to one another at boundary bands having ovonic materials embedded in electrode materials and vice versa; and having damage-producing implant species embedded therein. Some embodiments include ovonic material joining dielectric material along a boundary band, with the boundary band having ovonic material embedded in dielectric material and vice versa.09-27-2012
20100090189Nanoscale electrical device - A device consists a disordered relaxation insulator or/and a polyamorphous solid between two or more electrodes. Invented devices can perform passive, logic and memory functions in an electronic integrated circuit.04-15-2010
20130134373NONVOLATILE RESISTIVE MEMORY ELEMENT WITH A NOVEL SWITCHING LAYER - A nonvolatile resistive memory element has a novel variable resistance layer comprising one or more rare-earth oxides. The rare-earth oxide has a high k value, a high bandgap energy, and the ability to maintain an amorphous structure after thermal anneal processes. Thus, the novel variable resistance layer facilitates improved switching performance and reliability of the resistive memory element.05-30-2013
20130175492MEMORY CELLS HAVING STORAGE ELEMENTS THAT SHARE MATERIAL LAYERS WITH STEERING ELEMENTS AND METHODS OF FORMING THE SAME - In some embodiments, a memory cell is provided that includes a metal-insulator-metal stack and a steering element coupled to the metal-insulator-metal stack. The metal-insulator-metal stack includes a first conductive layer, a reversible resistivity switching layer above the first conductive layer, and a second conductive layer above the reversible resistivity switching layer. The first conductive layer and/or the second conductive layer includes a first semiconductor material layer. The steering element includes the first semiconductor material layer. Numerous other aspects are provided.07-11-2013
20130092893NONVOLATILE MEMORY ELEMENT AND METHOD FOR MANUFACTURING SAME - The method includes: forming a lower electrode layer above a substrate; forming a variable resistance layer on the lower electrode layer; forming an upper electrode layer on the variable resistance layer; forming a hard mask layer on the upper electrode layer; forming a photoresist mask on the hard mask layer; forming a hard mask by performing etching on the hard mask layer using the photoresist mask; and forming a nonvolatile memory element by performing etching on the upper electrode layer, the variable resistance layer, and the lower electrode layer, using the hard mask. In the forming of a photoresist mask, the photoresist mask is formed to have corner portions which recede toward the center portion in planar view.04-18-2013
20090072212ANTI-FUSE MEMORY DEVICE - A One Time Programmable (OTP) memory cell (03-19-2009
20130134375SEMICONDUCTOR DEVICE STRUCTURES COMPRISING CRYSTALLINE Pr1-xCaxMnO3 (PCMO) MATERIAL AND METHODS OF FORMING CRYSTALLINE PCMO MATERIAL - A method of forming a crystalline Pr05-30-2013
20100276655VOLTAGE EXCITED PIEZOELECTRIC RESISTANCE MEMORY CELL SYSTEM - The present invention discloses a memory system comprising a plurality of crystals, and at least two conductors. The at least two conductors being orthogonal to each other. Wherein at least one of the plurality of crystals are bounded by the orthogonal intersection of the at least two conductors.11-04-2010
20130146830Semiconductor Devices and Methods of Manufacturing the Same - Semiconductor devices include lower interconnections, upper interconnections crossing over the lower interconnections, selection components disposed at crossing points of the lower interconnections and the upper interconnections, respectively, and memory components disposed between the selection components and the upper interconnections. Each of the selection components may include a semiconductor pattern having a first sidewall and a second sidewall. The first sidewall of the semiconductor pattern may have a first upper width and a first lower width that is greater than the first upper width. The second sidewall of the semiconductor pattern may have a second upper width and a second lower width that is substantially equal to the second upper width.06-13-2013
20130146831PHASE-CHANGE MEMORY DEVICE HAVING MULTIPLE DIODES - A phase-change memory device with an improved current characteristic is provided. The phase-change memory device includes a metal word line, a semiconductor layer of a first conductivity type being in contact with the metal word line, and an auxiliary diode layer being in contact with metal word line and the semiconductor layer,06-13-2013
20130146832MEMORY CELL THAT EMPLOYS A SELECTIVELY GROWN REVERSIBLE RESISTANCE-SWITCHING ELEMENT AND METHODS OF FORMING THE SAME - A memory cell is provided that includes a reversible resistance-switching element above a substrate. The reversible resistance-switching element includes an etched material layer that includes an oxidized layer of the etched material layer above a non-oxidized layer of the etched material layer. Numerous other aspects are provided.06-13-2013
20130146829RESISTIVE RANDOM ACCESS MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - Resistive random access memory (RRAM) devices, and methods of manufacturing the same, include a RRAM device having a switching device, and a storage node connected to the switching device, wherein the storage node includes a first electrode, a metal oxide layer, and a second electrode sequentially stacked. The metal oxide layer contains a semiconductor material element affecting resistance of the storage node.06-13-2013
20080197334Phase Change Memory Cell with Heater and Method for Fabricating the Same - A memory device with a thin heater forms a programmable resistive change region in a sub-lithographic pillar of programmable resistive change material (“memory material”), where the heater is formed within the pillar between the top electrode and the programmable material. The device includes a dielectric material layer and vertically separated top and bottom electrodes having mutually opposed contact surfaces. A sub-lithographic pillar of memory material, which in a particular embodiment is a chalcogenide, is encased within the dielectric material layer. A heater between the pillar of programmable resistive material and the top electrode forms an active region, or programmable resistive change region, next to the heater when the memory device is programmed or reset.08-21-2008
20080197333Programmable Resistive Memory Cell with Self-Forming Gap - A memory device has a first electrode, a second electrode, and memory material defining an inter-electrode current path between the first electrode and the second electrode. A gap is formed by shrinkage of the shrinkable material between the memory material and a shrinkable material next to the memory material.08-21-2008
20110227017SEMICONDUCTOR MEMORY DEVICE INCLUDING VARIABLE RESISTANCE ELEMENT OR PHASE-CHANGE ELEMENT - According to one embodiment, a semiconductor memory device includes a first conductive line, a second conductive line, a cell unit, a silicon nitride film, and an insulating film. The first conductive line extends in a first direction. The second conductive line extends in a second direction crossing the first direction. The cell unit includes a phase-change film and a diode including a p-type semiconductor layer and an n-type semiconductor layer. The cell unit is connected in series between the first conductive line and the second conductive line. The silicon nitride film is formed on a side surface of the phase-change film. The insulating film is formed on a side surface of the diode and has a smaller amount of charge trapping than the silicon nitride film.09-22-2011
20100283026NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A first wire layer (11-11-2010
20100283025Phase change devices - A phase change device includes a native oxide grown on the surface of a first phase change alloy layer. The native oxide is punched through during the first electrical pulse applied between the device electrodes. An aperture created in the native oxide limit a region of localized heating during the device programming. A method for the phase change device fabrication includes a native oxide formation.11-11-2010
20120273744NON-VOLATILE RESISTIVE SENSE MEMORY WITH IMPROVED SWITCHING - A resistive sense memory cell includes a layer of crystalline praseodymium calcium manganese oxide and a layer of amorphous praseodymium calcium manganese oxide disposed on the layer of crystalline praseodymium calcium manganese oxide forming a resistive sense memory stack. A first and second electrode are separated by the resistive sense memory stack. The resistive sense memory cell can further include an oxygen diffusion barrier layer separating the layer of crystalline praseodymium calcium manganese oxide from the layer of amorphous praseodymium calcium manganese oxide a layer. Methods include depositing an amorphous praseodymium calcium manganese oxide disposed on the layer of crystalline praseodymium calcium manganese oxide forming a resistive sense memory stack.11-01-2012
20120273743NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device includes: a first interconnect; a second interconnect at a position opposing the first interconnect; and a variable resistance layer between the first interconnect and the second interconnect, the variable resistance layer being capable of reversibly changing between a first state and a second state by a voltage applied via the first interconnect and the second interconnect or a current supplied via the first interconnect and the second interconnect, the first state having a first resistivity, the second state having a second resistivity higher than the first resistivity. Wherein the variable resistance layer has a compound of carbon and silicon as a main component and including hydrogen.11-01-2012
20120273742SEMICONDUCTOR STORAGE DEVICE - An intermediate layer including at least one of elements constituting a phase change material and silicon is arranged between a recording layer composed of the phase change material and an n11-01-2012
20120273741PHASE CHANGE MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - A method of manufacturing a phase change memory device includes forming a lower electrode layer pattern and an insulating interlayer covering the lower electrode layer pattern, forming a first opening in the insulating interlayer to expose the lower electrode layer pattern, forming an oxide layer pattern on the sidewall of the first opening and a lower electrode under the oxide layer pattern by partially removing the oxide layer and the lower electrode layer pattern, forming an insulation layer filling a remaining portion of the first opening, removing the oxide layer pattern by a wet etching process to form a second opening, and forming a phase change material pattern on the lower electrode such that the phase change material pattern fills the second opening.11-01-2012
20110233504NON-VOLATILE MEMORY WITH RESISTIVE ACCESS COMPONENT - Some embodiments include apparatus and methods having a memory element configured to store information and an access component configured to allow conduction of current through the memory element when a first voltage difference in a first direction across the memory element and the access component exceeds a first voltage value and to prevent conduction of current through the memory element when a second voltage difference in a second direction across the memory element and the access component exceeds a second voltage value, wherein the access component includes a material excluding silicon.09-29-2011
20110233503METHODS OF FORMING PHASE-CHANGE MEMORY DEVICES AND DEVICES SO FORMED - A method of forming can be provided by forming a metal silicide layer that includes a diffusion metal on a substrate. A native oxide layer can be formed on the metal silicide layer and forming a metal oxide layer by reacting the native oxide layer with the diffusion metal. A phase-change layer and an upper electrode can be formed on the metal oxide layer. A phase-change memory device can include a substrate and a conductive region on the substrate with a lower electrode on the conductive region, where the lower electrode can include a metal silicide layer on the conductive region and a metal silicon nitride layer having a resistivity of about 10 to about 100 times that of the metal silicide layer. A metal oxide layer can be located between the metal silicon nitride layer and the metal silicide layer, the metal oxide layer comprising a resistivity that is greater than that of the metal silicide layer and less than the resistivity of the metal silicon nitride layer. A phase-change layer and an upper electrode can be located on the lower electrode.09-29-2011
20110233502NONVOLATILE MEMORY DEVICE - According to one embodiment, a nonvolatile memory device is provided, which includes a nonvolatile memory element in which an anode, a nonvolatile memory layer formed of a metal oxide film, and a cathode are stacked. The anode is formed of a metal nitride material and includes nitrogen more than a stoichiometric ratio of the metal nitride material. The cathode is formed of a metal material.09-29-2011
20110233501RESISTANCE CHANGE MEMORY - According to one embodiment, a resistance change memory includes a first interconnect line extending in a first direction, a second interconnect line extending in a second direction intersecting with the first direction, and a cell unit which is provided at the intersection of the first interconnect line and the second interconnect line and which includes a memory element and a non-ohmic element that are connected in series. The memory element stores data in accordance with a change in a resistance state. The non-ohmic element includes a metal layer, a first semiconductor layer containing a first impurity, and a second semiconductor layer which is provided between the first semiconductor layer and the metal layer and which has an unevenly distributed layer.09-29-2011
20110233500SEMICONDUCTOR MEMORY DEVICE INCLUDING MEMORY CELL HAVING RECTIFYING ELEMENT AND SWITCHING ELEMENT - According to one embodiment, a semiconductor memory device includes a first conductive line, a second conductive line, a rectifying element, a switching element, a first side wall film and a second side wall film. The first conductive line extends in a first direction. The second conductive line extends in a second direction crossing the first direction. The rectifying element is connected between the first and second conductive lines. The switching element is connected in series with the rectifying element between the first and second conductive lines. The first side wall film is formed on a side surface of the rectifying element. The second side wall film is formed on a side surface of at least one of the first and second conductive lines. At least one of a film type and a film thickness of the second side wall film is different from that of the first side wall film.09-29-2011
20100314600Memory Units and Related Semiconductor Devices Including Nanowires - Methods of fabricating a memory unit are provided including forming a plurality of first nanowire structures, each of which includes a first nanowire extending in a first direction parallel to the first substrate and a first electrode layer enclosing the first nanowire, on a first substrate. The first electrode layers are partially removed to form first electrodes beneath the first nanowires. A first insulation layer filling up spaces between structures, each of which includes the first nanowire and the first electrode, is formed on the first substrate. A second electrode layer is formed on the first nanowires and the first insulation layer. A plurality of second nanowires is formed on the second electrode layer, each of which extends in a second direction perpendicular to the first direction. The second electrode layer is partially etched using the second nanowires as an etching mask to form a plurality of second electrodes. Related memory units, methods of fabricating semiconductor devices and semiconductor devices are also provided.12-16-2010
20100314599CHALCOGENIDE FILM AND METHOD OF MANUFACTURING SAME - A chalcogenide film of the invention is formed by a sputtering within a contact hole formed in an insulating layer on a substrate, and is made of a chalcogen compound including a melting-point lowering material that lowers a melting point.12-16-2010
20130126815SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a semiconductor substrate in which a word line region is formed, and a barrier metal layer arranged on the word line region and causing a Schottky junction. The barrier metal layer includes a first nitride material, in which a first material is nitrified, and a second nitride material, in which a second material is nitrified. The barrier metal layer is formed of a mixture of the first nitride material and the second nitride material. At least one of the first material or the second material is rich in a metal used to form the first nitride material or the second nitride material.05-23-2013
20130126814SEMICONDUCTOR DEVICES HAVING MULTI-WIDTH ISOLATION LAYER STRUCTURES - According to example embodiments, there is provided a semiconductor device including a substrate and an isolation layer structure. The substrate includes an active region having an upper active pattern and a lower active pattern on the upper active pattern. The active region has a first aspect ratio larger than about 05-23-2013
20130126813METHOD OF FABRICATING A MICROELECTRONIC DEVICE WITH PROGRAMMABLE MEMORY - A method is provided for fabricating a microelectronic device with programmable memory that includes: i) depositing an intermediate layer of a material having a chalcogenide on a first electrode; ii) irradiating the intermediate layer of step i with ultraviolet radiation; iii) depositing an ionizable metallic layer on the intermediate layer obtained in step ii; iv) diffusing the metal ions originating from the ionizable metallic layer of step iii into the intermediate layer to form a chalcogenide material containing metal ions; and v) depositing a second electrode on the layer of chalcogenide material containing metal ions obtained in step iv to form the microelectronic device.05-23-2013
20130153845NONVOLATILE RESISTIVE MEMORY ELEMENT WITH A METAL NITRIDE CONTAINING SWITCHING LAYER - A nonvolatile resistive memory element has a novel variable resistance layer that includes a metal nitride, a metal oxide-nitride, a two-metal oxide-nitride, or a multilayer stack thereof. One method of forming the novel variable resistance layer comprises an interlayer deposition procedure, in which metal oxide layers are interspersed with metal nitride layers and then converted into a substantially homogeneous layer by an anneal process. Another method of forming the novel variable resistance layer comprises an intralayer deposition procedure, in which various ALD processes are sequentially interleaved to form a metal oxide-nitride layer. Alternatively, a metal oxide is deposited, nitridized, and annealed to form the variable resistance layer or a metal nitride is deposited, oxidized, and annealed to form the variable resistance layer.06-20-2013
20130153846THREE DIMENSIONAL MEMORY ARRAY ADJACENT TO TRENCH SIDEWALLS - A self-aligning stacked memory cell array structure and method for fabricating such structure. The memory cell array includes a stack of memory cells disposed adjacent to opposing sides of a conductive line that is formed within a trench. The memory cells are stacked such that the memory element surface of each memory cell forms a portion of the sidewall of the conductive line. The conductive line is formed within the trench such that electrical contact is made across the entire memory element surface of each memory cell. Such structure and method for making such structure is a self-aligning process that does not require the use of any additional masks.06-20-2013
20130153847RESISTIVE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A resistive memory device capable of improving an integration density is provided. The resistive memory device includes a semiconductor substrate, a plurality of resistive memory cells configured to be stacked on the semiconductor substrate and insulated from one another, where each of the plurality of resistive memory cells includes a switching transistor and a resistive device layer electrically connected to the switching transistor, a common source line electrically connected to the plurality of stacked resistive memory cells, and a bit line electrically connected to the plurality of stacked resistive memory cells and being insulated from the common source line.06-20-2013
20110303888NONVOLATILE MEMORY DEVICE - According to one embodiment, a nonvolatile memory device includes a memory cell connected to a first interconnect and a second interconnect. The memory cell includes a plurality of layers. The plurality of layers includes a carbon-containing memory layer sandwiched between a first electrode film and a second electrode film and a carbon-containing barrier layer provided at least one of between the first electrode film and the memory layer and between the second electrode film and the memory layer. The barrier layer has lower electrical resistivity than the memory layer.12-15-2011
20110309318NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a nonvolatile semiconductor memory device includes a first interconnect, a second interconnect and a resistance change layer. The first interconnect extends in a first direction on a major surface of a substrate. The second interconnect extends in a second direction non-parallel to the first direction. The resistance change layer includes a conductive nanomaterial, the resistance change layer located between the first interconnect and the second interconnect and being capable of reversibly changing between a first resistance state and a second resistance state by a voltage applied or a current supplied through the first interconnect and the second interconnect. The resistance change layer has a density varied along a third direction generally perpendicular to the first direction and the second direction.12-22-2011
20130187113Nonvolatile Memory Device Comprising a Metal-to-Insulator Transition Material - A nonvolatile memory device is disclosed comprising a metal-to-insulator transition material thermally coupled to a Peltier element. During programming, a selected current is flowing through the Peltier element, the level thereof determining whether the temperature of the Peltier element and hence of the thermally coupled metal-to-insulator transition material decreases or increases. In response to this temperature change, the metal-to-insulator transition material will change from one electrical conduction phase to another. The memory device is read by applying current through the metal-to-insulator transition material, the current level being selected to maintain the phase of the metal-to-insulator transition material.07-25-2013
20130187112NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a second electrode layer is formed on first structures where a first electrode layer and a first memory cell layer sequentially stacked above a substrate are patterned in a line-and-space shape extending in a first direction and a first interlayer insulating film embedded between the first structures. Etching is performed from the second electrode layer to a predetermined position in an inner portion of the first memory cell layer by using a first mask layer having a line-and-space pattern extending in a second direction, so that a first trench is formed. A first modifying film is formed on a side surface of the first trench, anisotropic etching is performed on the first memory cell layer by using the first mask layer, and after that, isotropic etching is performed.07-25-2013
20130187111Memory Cells - Some embodiments include memory cells which contain chalcogenide material having germanium in combination with one or both of antimony and tellurium. An atomic percentage of the germanium within the chalcogenide material is greater than 50%; and may be, for example, within a range of from greater than or equal to about 52% to less than or equal to about 78%. In some embodiments, the memory cell has a top electrode over the chalcogenide material, a heater element under and directly against the chalcogenide material, and a bottom electrode beneath the heater element. The heater element may be L-shaped, with the L-shape having a vertical pillar region joining with a horizontal leg region. A bottom surface of the horizontal leg region may be directly against the bottom electrode, and a top surface of the vertical pillar region may be directly against the chalcogenide material.07-25-2013
20130187110NONVOLATILE MEMORY DEVICE USING A TUNNEL OXIDE AS A CURRENT LIMITER ELEMENT - Embodiments of the invention generally include a method of forming a nonvolatile memory device that contains a resistive switching memory element that has improved device switching performance and lifetime, due to the addition of a current limiting component disposed therein. The electrical properties of the current limiting component are configured to lower the current flow through the variable resistance layer during the logic state programming steps by adding a fixed series resistance in the resistive switching memory element of the nonvolatile memory device. In one embodiment, the current limiting component comprises a tunnel oxide that is a current limiting material disposed within a resistive switching memory element in a nonvolatile resistive switching memory device. Typically, resistive switching memory elements may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices, such as digital cameras, mobile telephones, handheld computers, and music players.07-25-2013
20130187109Charging Controlled RRAM Device, and Methods of Making Same - Disclosed herein is a novel charging controlled RRAM (Resistance Random Access Memory), and various methods of making such a charging controlled RRAM device. In one example, a device disclosed herein includes a first word line structure formed above a substrate, wherein the first word line structure includes a gate electrode and a nano-crystal containing layer of insulating material, a second word line structure formed above the substrate, wherein the second word line structure comprises a gate electrode and a nano-crystal containing layer of insulating material, a first implant region formed in the substrate proximate the first word line structure, wherein the first implant region defines a first bit line, and a second implant region formed in the substrate proximate the second word line structure, wherein the second implant region defines a second bit line.07-25-2013
20120018693CONFINED RESISTANCE VARIABLE MEMORY CELL STRUCTURES AND METHODS - Confined resistance variable memory cell structures and methods are described herein. One or more methods of forming a confined resistance variable memory cell structure includes forming a via in a memory cell structure and forming a resistance variable material in the via by performing a process that includes providing a germanium amidinate precursor and a first reactant to a process chamber having the memory cell structure therein and providing an antimony ethoxide precursor and a second reactant to the process chamber subsequent to removing excess germanium.01-26-2012
20120025161DIODE AND RESISTIVE MEMORY DEVICE STRUCTURES - In an electronic device, a diode and a resistive memory device are connected in series. The diode may take a variety of forms, including oxide or silicon layers, and one of the layers of the diode may make up a layer of the resistive memory device which is in series with that diode.02-02-2012
20120025160NONVOLATILE MEMORY DEVICE - According to one embodiment, a nonvolatile memory device includes a stacked structure. The stacked structure includes a plurality of first interconnects, a plurality of second interconnects and a functional layer. The plurality of first interconnects extend in a first direction. The plurality of second interconnects are spaced from the first interconnects and extend in a second direction crossing the first direction. The functional layer is provided at each crossing position between the plurality of first interconnects and the plurality of second interconnects and has a transitioning function of transitioning between different resistance states and a rectifying function of rectifying current. The functional layer includes a metal layer, an opposed layer and a semiconductor layer. The semiconductor layer is provided between the metal layer and the opposed layer and is in contact with each of the metal layer and the opposed layer.02-02-2012
20120025159NONVOLATILE MEMORY DEVICE - According to one embodiment, a nonvolatile memory device includes a first conductive member and a second conductive member. The first conductive member extends in a first direction. The second conductive member extends in a second direction intersecting the first direction. A portion of the first conductive member connected to the second conductive member protrudes toward the second conductive member. A resistivity of the first conductive member in the first direction is lower than a resistivity of the first conductive member in a third direction of the protrusion of the first conductive member. A resistance value of the first conductive member in the third direction changes. A resistivity of the second conductive member in the second direction is lower than a resistivity of the second conductive member in the third direction. A resistance value of the second conductive member in the third direction changes.02-02-2012
20130099189RESISTIVE MEMORY AND METHODS OF PROCESSING RESISTIVE MEMORY - Resistive memory and methods of processing resistive memory are described herein. One or more method embodiments of processing resistive memory include conformally forming a cell material in an opening in an interlayer dielectric such that a seam is formed in the cell material, forming a conductive pathway by modifying the seam, and forming an electrode on the cell material and the seam.04-25-2013
20120298947LOW TEMPERATURE P+ SILICON JUNCTION MATERIAL FOR A NON-VOLATILE MEMORY DEVICE - A method for forming a non-volatile memory device includes forming a dielectric material overlying a semiconductor substrate, forming a first wiring structure overlying the first dielectric material, depositing an undoped amorphous silicon layer, depositing an aluminum layer over the amorphous silicon layer at a temperature of about 450 Degrees Celsius or lower, annealing the amorphous silicon and aluminum at a temperature of about 450 Degrees Celsius or lower to form a p+ polycrystalline layer, depositing a resistive switching material comprising an amorphous silicon material overlying the polycrystalline silicon material, forming a second wiring structure comprising a metal material overlying the resistive switching material.11-29-2012

Patent applications in class Bulk effect switching in amorphous material

Patent applications in all subclasses Bulk effect switching in amorphous material