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BULK EFFECT DEVICE

Subclass of:

257 - Active solid-state devices (e.g., transistors, solid-state diodes)

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Class / Patent application numberDescriptionNumber of patent applications / Date published
257002000 Bulk effect switching in amorphous material 1507
257006000 Intervalley transfer (e.g., Gunn effect) 4
20130207069METAL-INSULATOR TRANSITION SWITCHING DEVICES - A metal-insulator transition switching device includes a first electrode and a second electrode. A channel region which includes a bulk metal-insulator transition material separates the first electrode and the second electrode. A method for forming a metal-insulator transition switching device includes depositing a layer of bulk metal-insulator transition material in between a first electrode and a second electrode to form a channel region and forming a gate electrode operatively connected to the channel region.08-15-2013
20100084627Negative differential resistance polymer devices and circuits incorporating same - A device includes: a first electrical contact; a second electrical contact; a semiconducting or semimetallic organic layer disposed at least partially between the first and second electrical contacts; and a tunneling barrier layer disposed at least partially between the semiconducting or semimetallic organic layer and the first electrical contact. The tunneling barrier layer has a thickness effective to enable flow of an electrical current through the tunneling barrier layer responsive to an operative electrical bias applied across the first and second electrical contacts, the electrical current exhibiting negative differential resistance for at least some applied electrical bias values. Circuits are also disclosed that utilize one or more negative differential resistance polymer diodes to implement logic, memory, or mixed signal applications.04-08-2010
20100163837GUNN DIODE - A Gunn diode includes an active layer having a top and a bottom, a first contact layer disposed adjacent to the top of the active layer, a second contact layer disposed adjacent to the bottom of the active layer, wherein the first and second contact layers are more heavily doped than the active layer, and at least one outer contact layer disposed at an outer region of at least one of the first and second contact layers, the at least one outer contact layer being more heavily doped than the first and second contact layers, wherein the first and second contact layers, the active layer, and the at least one outer contact layer include a base material that is the same.07-01-2010
20090206319SEMICONDUCTOR DEVICE FOR GENERATING AN OSCILLATING VOLTAGE - A semiconductor device which displays an oscillating voltage due to the creation of charge domains which includes a plurality of semiconductor layers and at least two electrodes spaced from one another in the direction of the layers, an upper of which has a composition and/or dimensions predetermined so that a charge therein balances a depletion from a surface charge of the upper layer on application of a potential difference across said electrodes. The electrodes may be in contact solely with the upper layer. A method of manufacturing the device is also provided.08-20-2009
Entries
DocumentTitleDate
20130134372SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes first to n-th semiconductor layers (n is a natural number equal to or more than 2) being stacked in order from a surface of an insulating layer in a first direction perpendicular to the surface of the insulating layer, the first to n-th semiconductor layers extending in a second direction parallel to the surface of the insulating layer, the first to n-th semiconductor layers being insulated from each other, a common electrode connected to the first to n-th semiconductor layers in a first end of the second direction thereof, and a layer select transistor which uses the first to n-th semiconductor layers as channels and which selects one of the first to n-th semiconductor layers.05-30-2013
20110193042MEMORY CELL FORMED USING A RECESS AND METHODS FOR FORMING THE SAME - In a first aspect, a method of forming a memory cell is provided, the method including: (1) forming a pillar above a substrate, the pillar comprising a steering element and a metal hardmask layer; (2) selectively removing the metal hardmask layer to create a void; and (3) forming a carbon-based switching material within the void. Numerous other aspects are provided.08-11-2011
20130032775MRAM with sidewall protection and method of fabrication - BEOL memory cells are described that include one or more sidewall protection layers on the memory device (including, for example, an MTJ element) deposited prior to interconnect via etching to prevent the formation of electrical shorts between layers. One embodiment uses a single layer sidewall protection sleeve that is deposited after the memory device has been patterned. The layer material is vertically etched down to expose the upper surface of the top electrode while leaving a residual layer of protective material surrounding the rest of the memory device. The material for the protection layer is selected to resist the etchant used to remove the first dielectric material from the via in the subsequent interconnect process. A second embodiment uses dual-layer sidewall protection in which the first layer covers the memory element is preferably an oxygen-free dielectric and the second layer protects the first layer during via etching.02-07-2013
20130026434MEMRISTOR WITH CONTROLLED ELECTRODE GRAIN SIZE - A memristor with a controlled electrode grain size includes an adhesion layer, a first electrode having a first surface contacting the adhesion layer and a second surface opposite the first surface, in which the first electrode is formed of an alloy of a base material and at least one second material, and in which the alloy has a relatively smaller grain size than a grain size of the base material. The memristor also includes a switching layer positioned adjacent to the second surface of the first electrode and a second electrode positioned adjacent to the switching layer.01-31-2013
20110278527SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a substrate and an interconnect region on the substrate. The interconnect region includes a first interconnect having a first contact portion whose plane shape is a ring-like plane shape, a second interconnect disposed below the first interconnect, and a contact electrode passing through the ling-like portion of the first contact portion and electrically connecting the first interconnect and the second interconnect.11-17-2011
20110297908Phase Change Memory Cells and Fabrication Thereof - A phase change memory cell, e.g. a line-cell (12-08-2011
20110297909MAGNETIC MEMORY ELEMENT AND MAGNETIC MEMORY - A magnetic memory element includes: a first magnetization free layer formed of a ferromagnetic material having perpendicular magnetic anisotropy; a second magnetization free layer provided near the first magnetization free layer and formed of a ferromagnetic material having in-plane magnetic anisotropy; a reference layer formed of a ferromagnetic material having in-plane magnetic anisotropy; and a non-magnetic layer provided between the second magnetization free layer and the reference layer. The first magnetization free layer includes: a first magnetization fixed region of which magnetization is fixed, a second magnetization fixed region of which magnetization is fixed, and a magnetization free region which is connected to the first magnetization fixed region and the second magnetization fixed region, and of which magnetization can be switched. The second magnetization free layer is included in the first magnetization free layer in a plane parallel to a substrate. The second magnetization free layer is provided in a first direction away from the magnetization free region in the plane.12-08-2011
20090283735CARBON NANO-FILM REVERSIBLE RESISTANCE-SWITCHABLE ELEMENTS AND METHODS OF FORMING THE SAME - Methods of forming a microelectronic structure are provided, the microelectronic structure including a first conductor, a discontinuous film of metal nanoparticles disposed on a surface above the first conductor, a carbon nano-film formed atop the surface and the discontinuous film of metal nanoparticles, and a second conductor disposed above the carbon nano-film. Numerous additional aspects are provided.11-19-2009
20080251777Field Effect Device with a Channel with a Switchable Conductivity - A field effect device includes a source electrode, a drain electrode, a channel formed between the source electrode and the drain electrode, and a gate electrode formed directly on the channel and arranged in a gap between the source electrode and the drain electrode. The channel includes a switching material that is reversibly switchable between a lower conductivity state and a higher conductivity state. The first conductivity state has an electrical conductivity which is lower than an electrical conductivity of the second conductivity state. Each of the conductivity states is persistent without the need for a sustaining excitation signal including an electrical field, heat and/or light applied to the device.10-16-2008
20110220859Two-Terminal Nanotube Devices And Systems And Methods Of Making Same - A two terminal memory device includes first and second conductive terminals and a nanotube article. The article has at least one nanotube, and overlaps at least a portion of each of the first and second terminals. The device also includes stimulus circuitry in electrical communication with at least one of the first and second terminals. The circuit is capable of applying first and second electrical stimuli to at least one of the first and second terminal(s) to change the relative resistance of the device between the first and second terminals between a relatively high resistance and a relatively low resistance. The relatively high resistance between the first and second terminals corresponds to a first state of the device, and the relatively low resistance between the first and second terminals corresponds to a second state of the device.09-15-2011
20120068136Phase Change Memory Device, Storage System Having the Same and Fabricating Method Thereof - Provided are a phase change memory device and a fabricating method thereof. The phase change memory device includes a substrate, an interlayer dielectric layer formed on the substrate, first and second contact holes formed in the interlayer dielectric layer, and a memory cell formed in the first and second contact holes and including a diode, a first electrode on the diode, a phase change material layer on the first electrode, and a second electrode on the phase change material layer, wherein the first contact hole and the second contact hole are spaced apart from and separated from each other.03-22-2012
20080315170Quantum coherent switch utilizing commensurate nanoelectrode and charge density periodicities - A quantum coherent switch having a substrate formed from a density wave (DW) material capable of having a periodic electron density modulation or spin density modulation, a dielectric layer formed onto a surface of the substrate that is orthogonal to an intrinsic wave vector of the DW material; and structure for applying an external spatially periodic electrostatic potential over the dielectric layer.12-25-2008
20130214230MEMORY STRUCTURES, MEMORY ARRAYS, METHODS OF FORMING MEMORY STRUCTURES AND METHODS OF FORMING MEMORY ARRAYS - Some embodiments include methods of forming memory structures. An electrically insulative line is formed over a base. Electrode material is deposited over the line and patterned to form a pair of bottom electrodes along the sidewalls of the line. Programmable material is formed over the bottom electrodes, and a top electrode is formed over the programmable material. The bottom electrodes may each contain at least one segment which extends at angle of from greater than 0° to less than or equal to about 90° relative to a planar topography of the base. Some embodiments include memory structures having a bottom electrode extending upwardly from a conductive contact to a programmable material, with the bottom electrode having a thickness of less than or equal to about 10 nanometers. Some embodiments include memory arrays and methods of forming memory arrays.08-22-2013
20120241704LATERAL PHASE CHANGE MEMORY - A lateral phase change memory includes a pair of electrodes separated by an insulating layer. The first electrode is formed in an opening in an insulating layer and is cup-shaped. The first electrode is covered by the insulating layer which is, in turn, covered by the second electrode. As a result, the spacing between the electrodes may be very precisely controlled and limited to very small dimensions. The electrodes are advantageously formed of the same material, prior to formation of the phase change material region.09-27-2012
20100193757TWO-TERMINAL RESISTANCE SWITCHING DEVICE AND SEMICONDUCTOR DEVICE - The present invention is contemplated for providing a resistance switching device having a very small device size of approximately 20 nm×20 nm in its entirety, by taking advantage of a small diameter of a multilayered carbon nanotube or a multilayered carbon nanofiber per se, via a simpler manner that does not require any molecule inclusion step, with an excellent electric conductivity.08-05-2010
20110248233METHOD FOR FABRICATING A PHASE-CHANGE MEMORY CELL - A method for fabricating a phase-change memory cell is described. The method includes forming a dielectric layer (228) on a metal layer (226) above a substrate. A phase-change material layer (230) is formed on the dielectric layer. A contact region (232) is formed, within the dielectric layer, between the phase-change material layer and the metal layer by breaking-down a portion of the dielectric layer.10-13-2011
20100301299Material and device properties modification by electrochemical charge injection in the absence of contacting electrolyte for either local spatial or final states - In some embodiments, the present invention is directed to processes for the combination of injecting charge in a material electrochemically via non-faradaic (double-layer) charging, and retaining this charge and associated desirable properties changes when the electrolyte is removed. The present invention is also directed to compositions and applications using material property changes that are induced electrochemically by double-layer charging and retained during subsequent electrolyte removal. In some embodiments, the present invention provides reversible processes for electrochemically injecting charge into material that is not in direct contact with an electrolyte. Additionally, in some embodiments, the present invention is directed to devices and other material applications that use properties changes resulting from reversible electrochemical charge injection in the absence of an electrolyte.12-02-2010
20110024710MEMRISTOR WITH A NON-PLANAR SUBSTRATE - A memristor includes a substrate having a plurality of protrusions, wherein each of the plurality of protrusions extends in a first direction, a first electrode provided over at least one of the plurality of protrusions, wherein the first electrode conforms to the shape of the at least one protrusion such that the first electrode has a crest, a switching material positioned upon the first electrode; and a second electrode positioned upon the switching material such that a portion of the second electrode is substantially in line with the crest of the first electrode along the first direction, wherein an active region in the switching material is operable to be formed between the crest of the first electrode and the portion of the second electrode that is substantially in line with the crest of the first electrode.02-03-2011
20120132879NONVOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is a nonvolatile memory device including a phase-change memory configured with cross-point memory cells in which memory elements formed of a phase-change material and selection elements formed with a diode are combined. A memory cell is configured with a memory element formed of a phase-change material and a selection element formed with a diode having a stacked structure of a first polycrystalline silicon film, a second polycrystalline silicon film, and a third polycrystalline silicon film. The memory cells are arranged at intersection points of a plurality of first metal wirings extending along a first direction with a plurality of third metal wirings extending along a second direction orthogonal to the first direction. An interlayer film is formed between adjacent selection elements and between adjacent memory elements, and voids are formed in the interlayer film provided between the adjacent memory elements.05-31-2012
20110024711APPARATUS FOR REDUCING PHOTODIODE THERMAL GAIN COEFFICIENT AND METHOD OF MAKING SAME - An apparatus for reducing photodiode thermal gain coefficient includes a bulk semiconductor material having a light-illumination side. The bulk semiconductor material includes a minority charge carrier diffusion length property configured to substantially match a predetermined hole diffusion length value and a thickness configured to substantially match a predetermined photodiode layer thickness. The apparatus also includes a dead layer coupled to the light-illumination side of the bulk semiconductor material, the dead layer having a thickness configured to substantially match a predetermined thickness value and wherein an absolute value of a thermal coefficient of gain due to the minority carrier diffusion length property of the bulk semiconductor material is configured to substantially match an absolute value of a thermal coefficient of gain due to the thickness of the dead layer.02-03-2011
20110240941Silicon-Based Memristive Device - A memristive device (10-06-2011
20110084247Self-Aligned Bipolar Junction Transistors - A plurality of bipolar transistors are formed by forming a common conduction region, a plurality of control regions extending each in an own active areas on the common conduction region, a plurality of silicide protection strips, and at least one control contact region. Silicide regions are formed on the second conduction regions and the control contact region. The second conduction regions may be formed by selectively implanting a first conductivity type dopant areas on a first side of selected silicide protection strips. The control contact region is formed by selectively implanting an opposite conductivity type dopant on a second side of the selected silicide protection strips.04-14-2011
20110133147Continuous plane of thin-film materials for a two-terminal cross-point memory - A structure for a memory device including a plurality of substantially planar thin-film layers or a plurality of conformal thin-film layers is disclosed. The thin-film layers form a memory element that is electrically in series with first and second cladded conductors and operative to store data as a plurality of conductivity profiles. A select voltage applied across the first and second cladded conductors is operative to perform data operations on the memory device. The memory device may optionally include a non-ohmic device electrically in series with the memory element and the first and second cladded conductors. Fabrication of the memory device does not require the plurality of thin-film layers be etched in order to form the memory element. The memory element can include a CMO layer having a selectively crystallized polycrystalline portion and an amorphous portion. The cladded conductors can include a core material made from copper.06-09-2011
20120305873VERTICAL INTERCONNECT STRUCTURE, MEMORY DEVICE AND ASSOCIATED PRODUCTION METHOD - The present invention relates to a method for producing a vertical interconnect structure, a memory device and an associated production method, in which case, after the formation of a contact region in a carrier substrate a catalyst is produced on the contact region and a free-standing electrically conductive nanoelement is subsequently formed between the catalyst and the contact region and embedded in a dielectric layer.12-06-2012
20120305872PHASE-CHANGE MEMORY DEVICE INCLUDING A VERTICALLY-STACKED CAPACITOR AND A METHOD OF THE SAME - A phase change memory device includes a vertically-stacked capacitor structure having large capacitance and small area. The phase change memory device includes a phase change memory structure, and the vertically-stacked capacitor structure electrically connected to the phase change memory structure and comprising a first capacitor and a second capacitor that are stacked and electrically connected in parallel to each other.12-06-2012
20120037871NOVEL BIFUNCTIONAL MOLECULES COMPRISING A CYCLOALKYNE OR HETEROCYCLOALKYNE GROUP AND A REDOX GROUP - The invention relates to compounds comprising a cycloalkyne or heterocycloalkyne group and a redox group. Said compounds are of general formula (I) wherein Z is a cycloalkyne or heterocycloalkyne with at least 8 links, optionally substituted by a halogen atom or a linear or branched C1 to C5 alkyl, A is an organic structure having oxidation-reduction properties, and B is an organic link between the cycloalkyne or heterocycloalkyne cycle and the organic structure A. The invention is especially applicable to the field of molecular electronics.02-16-2012
20130200320Self-Isolated Conductive Bridge Memory Device - A conductive-bridge random access memory device is disclosed comprising a second metal layer configured to provide second metal cations; a layer of insulator adjacent to the second metal layer; the layer of insulator comprising a layer of first insulator and a layer of second insulator; the layer of second insulator being adjacent to the second metal layer; a first metal layer adjacent to the layer of first insulator, the first metal layer being opposite to the second metal layer; wherein the density of the layer of second insulator is higher than the density of the layer of first insulator.08-08-2013
20110315942SOLID-STATE MEMORY - A solid-state memory that requires a lower current during recording and erasing data and can repeatedly rewrite data an increased number of times. In at least one example embodiment, the solid-state memory includes a recording layer that includes a laminated structure in which electric properties are changed in response to a phase separation. The laminated structure includes a film containing an Sb atom(s) and a film containing a Ge atom(s), which films constitute a superlattice structure. In the laminated structure, phase separation of the film containing the Sb atom and the film containing the Ge atom allows data to be recorded and erased efficiently.12-29-2011
20120205605ORGANIC REDOX ACTIVE COMPOUNDS WITH REVERSIBLE STORAGE OF CHARGES AND SUBSTRATES AND MOLECULAR MEMORY DEVICES COMPRISING THEM - An organic redox active compound with reversible storage of charge is disclosed. The material characterized by a formula R-M-Y-T. According to some aspects, R represents a deconjugating group, M represents an organic redox active fragment, not comprising any metal ion or metal, capable of reversibly storing at least one charge, T represents a tripod group comprising three groups F, capable of being chemically grafted to a surface of a solid substrate, and Y represents a spacer group separating M from T. A substrate on which the compounds are grafted, a molecular memory device including the compound or the substrate, and an electronic apparatus including the molecular memory device are also disclosed.08-16-2012
20120061638MEMORY ELEMENT AND MEMORY DEVICE - There are provided a memory element and a memory device in which the state of erasing remains stable by deactivation of a localized site(s) formed inside of a resistance change layer. The memory element includes a first electrode, a memory layer, and a second electrode in this order. The memory layer includes a resistance change layer including an n-type dopant or a p-type dopant, and disposed on the first electrode side, and an ion source layer disposed between the resistance change layer and the second electrode.03-15-2012
201200616373-D STRUCTURED NONVOLATILE MEMORY ARRAY AND METHOD FOR FABRICATING THE SAME - The present invention relates to a field of nonvolatile memory technology in ULSI circuits manufacturing technology and discloses a 3D-structured resistive-switching memory array and a method for fabricating the same. The 3D-structured resistive-switching memory array according to the invention includes a substrate and a stack structure of bottom electrodes/isolation dielectric layers, deep trenches are etched in the stack structure of the bottom electrodes/the isolation dielectric layers; a resistive-switching material layer and a top electrode layer are deposited on sidewalls of the deep trenches, wherein the top electrodes and the bottom electrodes are crossed over each other on the sidewalls of the deep trenches with the resistive-switching material being interposed at cross-over points, each of the cross-over points forms one resistive-switching memory cell, and all of the resistive-switching memory cells form the 3D-structured resistive-switching memory array, and the 3D resistive-switching memory in the array are isolated by the isolation dielectric layers. According to the invention, the storage density of a resistive-switching memory can be improved, the process can be simplified, and the cost of the process can be reduced.03-15-2012
20120211715SEMICONDUCTOR DEVICE INCLUDING PHASE CHANGE MATERIAL AND METHOD OF MANUFACTURING SAME - Disclosed herein is a device that includes: an interlayer insulation film having a through hole; and a phase change storage element provided in the through hole. The phase change storage element includes: an outer electrode being a conductive film of cylindrical shape and being formed along an inner wall of the through hole; a buffer insulation film being an insulation film of cylindrical shape and being formed along an inner wall of the outer electrode, an upper end of the buffer insulation film being recessed in part to form a recess; a phase change film filling an interior of the recess; and an inner electrode being a conductive film formed along an inner wall of the buffer insulation film including a surface of the phase change film.08-23-2012
20120168704METHOD OF ETCHING A PROGRAMMABLE MEMORY MICROELECTRONIC DEVICE - A method of etching a programmable memory microelectronic device (07-05-2012
20120175580VARIABLE RESISTANCE MEMORY - A method of fabricating a phase change memory includes forming a lower electrode on a semiconductor substrate, forming a phase change pattern, an upper electrode, and a hard mask pattern sequentially on the lower electrode, a width of a bottom surface of the hard mask pattern being greater than a width of a top surface of the hard mask pattern, the bottom surface of the hard mask pattern facing the upper electrode and being opposite the top surface of the hard mask pattern, and forming a capping layer to cover the top surface of the hard mask pattern and sidewalls of the hard mask pattern, phase change pattern, and upper electrode.07-12-2012
20110303887MEMORY STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - A memory storage device includes: a lower electrode formed to be separated for each of memory cells; a memory storage layer formed on the lower electrode and capable of recording information according to a change in resistance; and an upper electrode formed on the memory storage layer, wherein the memory storage device includes a first layer formed of metal or metal silicide and a second layer formed on the first layer and formed of a metal nitride, the lower electrode is formed by lamination of the first layer and the second layer and formed such that only the first layer is in contact with a lower layer and only the second layer is in contact with the memory storage layer, which is an upper layer, the memory storage layer is formed in common to plural memory cells, and the upper electrode is formed in common to the plural memory cells.12-15-2011
20120228573Memory Cell Constructions, and Methods for Fabricating Memory Cell Constructions - Some embodiments include methods for fabricating memory cell constructions. A memory cell may be formed to have a programmable material directly against a material having a different coefficient of expansion than the programmable material. A retaining shell may be formed adjacent the programmable material. The memory cell may be thermally processed to increase a temperature of the memory cell to at least about 300° C., causing thermally-induced stress within the memory cell. The retaining shell may provide a stress which substantially balances the thermally-induced stress. Some embodiments include memory cell constructions. The constructions may include programmable material directly against silicon nitride that has an internal stress of less than or equal to about 200 megapascals. The constructions may also include a retaining shell silicon nitride that has an internal stress of at least about 500 megapascals.09-13-2012
20120298946Shaping a Phase Change Layer in a Phase Change Memory Cell - A phase change memory cell includes a phase change layer of a phase change material on a semiconductor body. A hard mask structure is formed on the phase change layer and a resist mask is formed on the hard mask structure. A hard mask is formed by shaping the hard mask structure using the resist mask. The phase change layer is shaped using the hard mask. The resist mask is removed before shaping the phase change layer.11-29-2012
20120298945NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A nonvolatile semiconductor memory device of the present invention includes a substrate (11-29-2012
20120326109PHASE CHANGE MEMORY CELL AND PHASE CHAGE MEMORY - A phase change memory cell includes a first circuit and a second circuit. The first circuit comprises a first electrode, a carbon nanotube layer and a second electrode electrically connected in series. The first circuit is adapted to write data into the phase change memory cell or reset the phase change memory cell. The second circuit comprises a third electrode, a phase change layer and a fourth electrode electrically connected in series, at least part of the phase change layer is overlapped with the carbon nanotube layer. The second circuit is adapted to read data from the phase change memory cell or reset the phase change memory cell.12-27-2012
20120280196ELECTROFORMING FREE MEMRISTOR - An electroforming free memristor (11-08-2012
20120280195RESISTANCE VARIABLE MEMORY CELLS AND METHODS - Resistance variable memory cells and methods are described herein. One or more methods of forming a resistance variable memory cell include forming a silicide material on a terminal of a select device associated with the resistance variable memory cell, forming a modified region of the silicide material by modifying a resistivity of a region of the silicide material, forming a conductive element on at least a portion of the modified region, and forming a resistance variable material on the conductive element.11-08-2012
20120280197FLAT LOWER BOTTOM ELECTRODE FOR PHASE CHANGE MEMORY CELL - A phase change memory cell having a flat lower bottom electrode and a method for fabricating the same. The method includes forming a dielectric layer over a substrate including an array of conductive contacts, patterning, a via having a low aspect ratio such that a depth of the via is less than a width thereof, to a contact surface of the substrate corresponding to each of the array of conductive contacts to be connected to access circuitry, etching the dielectric layer and depositing electrode material over the etched dielectric layer and within each via, and planarizing the electrode material to form a plurality of lower bottom electrodes on each of the conductive contacts.11-08-2012
20120326110PHASE CHANGE MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - A phase change memory device includes an impurity region on a substrate, the impurity region being in an active region, a metal silicide pattern at least partially buried in the impurity region, a diode on the impurity region, a lower electrode on the diode, a phase change layer pattern on the lower electrode, and an upper electrode on the phase change layer pattern.12-27-2012
20080224115Fabricating a Set of Semiconducting Nanowires, and Electric Device Comprising a Set of Nanowires - The method of fabricating a set of semiconducting nanowires (09-18-2008
20130168628VARIABLE RESISTANCE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A variable resistance memory device includes a first trench extending in a first direction formed in a first insulation layer, a first conductive layer in the first trench, a protective layer over the first conductive layer in the first trench, a second insulation layer over the first insulation layer and the protective layer, a second trench formed in the second insulation layer and extending in a second direction that crosses the first direction, a gap formed in the protective layer exposing the first conductive layer at an intersection between the first trench and the second trench, a variable resistance layer positioned in the gap and coupled to the first conductive layer, and a second conductive layer formed in the second trench and coupled to the variable resistance layer.07-04-2013
20130134371PHASE-CHANGE RANDOM ACCESS MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A phase-change random access memory (PCRAM) device includes a semiconductor substrate; switching elements formed on the semiconductor substrate; a plurality of phase-change structures formed on the switching elements; and heat absorption layers buried between the plurality of phase-change structures, wherein the plurality of phase-change structures are insulated from the heat absorption layers.05-30-2013
20130175490NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a nonvolatile semiconductor memory device includes a fin-type stacked layer structure having memory cells, and a beam connected to an end portion of the structure. Each of the structure and the beam includes semiconductor layers stacked in a perpendicular direction. The beam includes a contact portion provided at one end of the beam, and a low resistance portion provided between the contact portion and the end portion of the structure.07-11-2013
20130175491SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - Semiconductor devices, and methods of manufacturing the same, include a field region in a semiconductor substrate to define an active region. An interlayer insulating layer is on the semiconductor substrate. A semiconductor pattern is within a hole vertically extending through the interlayer insulating layer. The semiconductor pattern is in contact with the active region. A barrier region is between the semiconductor pattern and the interlayer insulating layer. The barrier region includes a first buffer dielectric material and a barrier dielectric material. The first buffer dielectric material is between the barrier dielectric material and the semiconductor pattern, and the barrier dielectric material is spaced apart from both the semiconductor pattern and the active region.07-11-2013
20110210300Reducing Temporal Changes in Phase Change Memories - A phase change memory in the reset state may be heated to reduce or eliminate electrical drift.09-01-2011
20110220858SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device and a method of manufacturing the same. The semiconductor device may include a lower electrode having a hollow cylindrical shape of which an upper portion is open, the lower electrode being disposed on a substrate, an insulating structure wrapping the lower electrode and including a nitride, a variable resistance pattern electrically connected to the lower electrode, and an upper electrode electrically connected to the variable resistance pattern.09-15-2011
20110248234VERTICAL INTERCONNECT STRUCTURE, MEMORY DEVICE AND ASSOCIATED PRODUCTION METHOD - The present invention relates to a method for producing a vertical interconnect structure, a memory device and an associated production method, in which case, after the formation of a contact region in a carrier substrate a catalyst is produced on the contact region and a free-standing electrically conductive nanoelement is subsequently formed between the catalyst and the contact region and embedded in a dielectric layer.10-13-2011
20130126812Memory Cells, Integrated Devices, and Methods of Forming Memory Cells - Some embodiments include integrated devices, such as memory cells. The devices may include chalcogenide material, an electrically conductive material over the chalcogenide material, and a thermal sink between the electrically conductive material and the chalcogenide material. The thermal sink may be of a composition that includes an element in common with the electrically conductive material and includes an element in common with the chalcogenide material. Some embodiments include a method of forming a memory cell. Chalcogenide material may be formed over heater material. Electrically conductive material may be formed over the chalcogenide material. A thermal sink may be formed between the electrically conductive material and the chalcogenide material. The thermal sink may be of a composition that includes an element in common with the electrically conductive material and includes an element in common with the chalcogenide material.05-23-2013
20130181180SEMICONDUCTOR DEVICE - A semiconductor device according to the present invention includes: an unit element which includes a first switch and a second switch, wherein each of the first switch and the second switch includes an electrical resistance changing layer whose state of electrical resistance is changed according to a polarity of an applied voltage, and each of the first switch and the second switch has two electrodes, and wherein one electrode of the first switch and one electrode of the second switch are connected each other to form a common node, and the other electrode of the first switch forms a first node, and the other electrode of the second switch forms a second node; a first wiring which is connected with the first node and forms a signal transmission line; and a second wiring which is connected with the second node and is connected with the first wiring through the unit element.07-18-2013
20120007031PHASE CHANGE MEMORY CELL WITH HEATER AND METHOD THEREFOR - A method for forming a phase change memory cell (PCM) includes forming a heater for the phase change memory and forming a phase change structrure electrically coupled to the heater. The forming a heater includes siliciding a material including silicon to form a silicide structure, wherein the heater includes at least a portion of the silicide structure. The phase change structure exhibits a first resistive value when in a first phase state and exhibits a second resistive value when in a second phase state. The silicide structure produces heat when current flows through the silicide structure for changing the phase state of the phase change structure.01-12-2012

Patent applications in class BULK EFFECT DEVICE

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