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FORMING OR TREATING ELECTRICAL CONDUCTOR ARTICLE (E.G., CIRCUIT, ETC.)

Subclass of:

216 - Etching a substrate: processes

Patent class list (only not empty are listed)

Deeper subclasses:

Class / Patent application numberDescriptionNumber of patent applications / Date published
216017000 Forming or treating of groove or through hole 81
216020000 Adhesive or autogenous bonding of self-sustaining preforms (e.g., prefabricated base, etc.) 43
216016000 Forming or treating resistive material 3
20130032568ELECTRICAL DEVICE WITH TEETH JOINING LAYERS AND METHOD FOR MAKING THE SAME - A process of making an article of manufacture, the process including constructing an electrical device which implements circuitry having a portion in cavities, the portion defined by an epoxy dielectric material delivered with solid content sufficient that etching the epoxy forms cavities located in, and underneath an initial surface of, the dielectric material, sufficient that the etching of the epoxy uses non-homogeneity with the solid content in bringing about formation of the cavities and sufficient that the etching of the epoxy is such that a plurality of the cavities have a cross-sectional width that is greater than a maximum depth with respect to the initial surface, wherein the etching forms the cavities, and a conductive material, a portion of the conductive material in the cavities thereby forming teeth in the cavities, such that the conductive material forms the portion of the circuitry of the electrical device.02-07-2013
20090159558Method of Manufacturing an Integrated Circuit - A method of manufacturing an integrated circuit including a memory device that includes the following processes: forming a mask layer structure above a composite structure including a resistivity changing layer and an electrode layer disposed above the resistivity changing layer; partially patterning the mask layer structure using a first substance; stopping patterning the mask layer structure before exposing the top surface of the electrode layer; at least partially exposing the top surface of the electrode layer using a second substance, the second substance chemically not reacting with the electrode layer material.06-25-2009
20120125881METHOD OF MANUFACTURING A COORDINATE DETECTOR - A method of manufacturing a coordinate detector having a resistive film and a common electrode for applying a voltage to the resistive film is disclosed that includes the steps of (a) applying a photoresist onto the resistive film formed on a substrate formed of an insulator; (b) forming a resist pattern on the resistive film by exposing the applied photoresist to light through a predetermined mask and subsequently developing the applied photoresist; (c) forming a resistive film removal region by removing a portion of the resistive film without the resist pattern; (d) removing the resist pattern after step (c); and (e) forming the common electrode over the resistive film removal region after step (d).05-24-2012
216014000 Forming or treating lead frame or beam lead 3
20110284495ETCH ISOLATION LPCC/QFN STRIP - Various structures and fabrication methods for leadless plastic chip carrier (QFN) packages which utilize carriers in strip format, wherein the leads (or terminals) are formed to be electrically isolated from one another within each unit and in which the units are formed to be electrically isolated from one another within the strip using chemical etching techniques.11-24-2011
20110226729METHOD OF MANUFACTURING A DOUBLE SIDED FLEX CIRCUIT FOR A DISK DRIVE WHEREIN A FIRST SIDE LEAD PROVIDES AN ETCHING MASK FOR A SECOND SIDE LEAD - A method of manufacturing a flex circuit is disclosed for a disk drive comprising a disk, a head actuated radially over the disk, and control circuitry. The flex circuit is for electrically coupling the head to the control circuitry and comprises a substrate. An electrical coating applied to a first side of the substrate is etched to form a first electrical lead. The first side of the substrate is irradiated with radiation such that the first electrical lead masks the radiation from passing through the substrate to prevent curing of a photoresist applied to the second side of the substrate to form an uncured photoresist and a cured photoresist on the second side of the substrate. The uncured photoresist is removed from the second side of the substrate to form a groove, and the groove is filled with electrically conductive material to form the second electrical lead.09-22-2011
20130112652METHOD FOR MANUFACTURING SUBSTRATE FOR SEMICONDUCTOR ELEMENT - A manufacturing method of a semiconductor element substrate including: forming a first photoresist pattern on a first surface of a metallic plate, to form a semiconductor element mounting part, a semiconductor element electrode connection terminal, a wiring, an outer frame part, and a slit; forming a second photoresist pattern on the second surface of the metallic plate; forming the slit by half etching to connect the metallic chip with a four corners of the outer frame part; forming a plurality of concaved parts on the second surface of the metallic plate; forming a resin layer by injecting a resin to the plurality of concaved parts; and etching the first surface of the metallic plate and forming the semiconductor element electrode connection terminal and the outer frame.05-09-2013
Entries
DocumentTitleDate
20110198313METHOD FOR THE CONTROLLED GROWTH OF A GRAPHENE FILM - The invention relates to a controlled graphene film growth process characterized in that it comprises the following steps: 08-18-2011
20110198312AIR CURRENT GENERATING APPARATUS AND METHOD FOR MANUFACTURING SAME - In one embodiment, an air current generating apparatus includes: a dielectric substrate exposed to gas: a first electrode disposed inside the dielectric substrate; a second electrode disposed near a surface of the dielectric so as to correspond the first electrode and having a sharp shape; and a power source applying a voltage between the first and second electrodes and plasmatizing part of the gas to generate an air current.08-18-2011
20090050601INERT GAS ETCHING - A method of patterning a nanostructure film using a plasma is described. The nanostructure film may substantially comprise carbon and/or carbon nanotubes. The plasma may comprise an inert gas. The plasma may be applied to the nanostructure film at close to atmospheric pressure and room temperature.02-26-2009
20100051577COPPER LAYER PROCESSING - The present disclosure includes devices, methods, and systems for processing copper and, in particular, copper layer processing using sulfur plasma, One or more embodiments can include a method of forming a copper sulfur compound by reacting copper with a plasma gas including sulfur and removing at least a portion of the copper sulfur compound with water.03-04-2010
20090071933ETCHING PROCESSES USED IN MEMS PRODUCTION - The efficiency of an etching process may be increased in various ways, and the cost of an etching process may be decreased. Unused etchant may be isolated and recirculated during the etching process. Etching byproducts may be collected and removed from the etching system during the etching process. Components of the etchant may be isolated and used to general additional etchant. Either or both of the etchant or the layers being etched may also be optimized for a particular etching process.03-19-2009
20130075357METHODS OF MAKING AND REPAIRING RESIZED FLAT PANEL DISPLAYS - Electronic flat panel displays (FPDs) including liquid crystal displays (LCDs) may be resized to meet custom size requirements for applications in aerospace and elsewhere. During the resizing process, pixel line defects may occur in the image due to electrical short circuits at the resized cut edge. Methods for repairing such short circuits are described, including use of mechanical, electrical, chemical, thermal, and/or other methods, and any combination thereof, to open the short circuits. The methods may be applied to the sealed cut edge to ruggedize the seal, even if image defects are not exhibited initially. The repaired short circuits may be stress tested to ensure the defects will not recur during the life of the display, and the repaired areas may be resealed.03-28-2013
20100116781Etchant and array substrate having copper lines etched by the etchant - An etchant includes hydrogen peroxide (H05-13-2010
20100116780METHOD FOR PATTERNING NANOWIRES ON SUBSTRATE USING NOVEL SACRIFICIAL LAYER MATERIAL - A method for patterning nanowires on a substrate. The method includes procedures of preparing a substrate having a patterned sacrificial layer of barium fluoride thereon; growing nanowires on an entire surface of the resultant substrate including the patterned sacrificial layer; and removing the patterned sacrificial layer using a solvent to remove part of the nanowires on the patterned sacrificial layer such that part of the nanowires in direct contact with the substrate remains on the substrate to thereby form a nanowire pattern.05-13-2010
20130037511METHOD AND APPARATUS FOR TREATING A WORKPIECE WITH ARRAYS OF NOZZLES - The present invention provides a tool for treating microelectronic workpieces with one or more treatment materials, including liquids, gases, fluidized solids, dispersions, combinations of these, and the like.02-14-2013
20130037512MEMS-BASED MICRO AND NANO GRIPPERS WITH TWO AXIS FORCE SENSORS - The present invention relates to a design and microfabrication method for microgrippers that are capable of grasping micro and nano objects of a large range of sixes and two-axis force sensing capabilities. Gripping motion is produced by one or more electrothermal actuators. Integrated force sensors along x and y directions enable the measurement of gripping forces as well as the forces applied at the end of microgripper arms along the normal direction, both with a resolution down to nanoNewton. The microfabrication method enables monolithic integration of the actuators and the force sensors.02-14-2013
20130037513RESIN BOARD TO BE SUBJECTED TO OZONE TREATMENT, WIRING BOARD, AND METHOD OF MANUFACTURING THE WIRING BOARD - A resin board that consists of at least one of a mixture of a plurality of types of resins having different degrees of susceptibility to erosion by an ozone solution, and a resin having, in a molecule, a plurality of types of components having different degrees of susceptibility to erosion by the ozone solution is treated with ozone water to form a reformed layer, and a catalyst metal is adsorbed by the reformed layer so as to form a resin-metal composite layer, on which a plating process is performed. In the resin board, a component or components that is/are likely to be eroded on by the ozone solution dissolves into the ozone solution, and pores or clearances on the order of nanometers are formed between the component(s) and a component or components that is/are less likely to be eroded by the ozone solution. With the plating deposited in the pores or clearances, the adhesion strength is improved due to an anchoring effect. Thus, the adhesion strength of the plating film is improved even where the resin-metal composite layer has a thickness of 10 to 200 nm.02-14-2013
20100072170SHORT PITCH METAL GRATINGS AND METHODS FOR MAKING THE SAME - Methods for forming a metal grating include providing a first grating including a plurality of grating lines formed from a dielectric material, each grating having a pair of sidewalls, facing sidewalls of adjacent grating lines being separated by corresponding trenches, the grating lines and trenches forming a grating surface; forming a layer of a metal on the grating surface, where the metal layer has a constant thickness and conforms to the grating surface; and removing portions of the metal layer between sidewalls of adjacent grating lines of the first grating to form a metal grating having grating lines formed from the metal, the grating lines of the metal grating corresponding to the portions of the metal layer adjacent the sidewalls of the grating lines of the first grating. The metal grating has a pitch of 200 nm or less, a depth of 50 nm or more, and the grating lines of the metal grating have an aspect ratio of 10-to-1 or more.03-25-2010
20100072169Methods and Systems for Preventing Feature Collapse During Microelectronic Topography Fabrication - Methods for preventing feature collapse subsequent to etching a layer encasing the features include adding a non-aqueous liquid to a microelectronic topography having remnants of an aqueous liquid arranged upon its surface and subsequently exposing the topography to a pressurized chamber including a fluid at or greater than its saturated vapor pressure or critical pressure. The methods include flushing from the pressurized chamber liquid arranged upon the topography and, thereafter, venting the chamber in a manner sufficient to prevent liquid formation therein. The topography features may be submerged in a liquid while pressurizing the chamber. A process chamber used to prevent feature collapse includes a substrate holder for supporting a microelectronic topography, a vessel configured to contain the substrate holder, and a sealable region surrounding the substrate holder and the vessel. The chamber is configured to sequester wet chemistry supplied to the vessel from metallic surfaces of the sealable region.03-25-2010
20100102027Method of Forming Double-sided Patterns in a Touch Panel Circuit - A method of forming double-sided patterns in a touch panel circuit is disclosed. A first conductive layer and a second conductive layer are respectively formed on both sides of a substrate. A blocking layer is formed on a top surface of the first conductive layer for blocking ultraviolet (UV) light. A first photoresist layer is formed on a top surface of the blocking layer, and a second photoresist layer is formed on a bottom surface of the second conductive layer. Accordingly, two sides of the substrate may be exposed, developed and etched at the same time, thereby substantially simplifying the process of manufacturing the touch panel circuit.04-29-2010
20100102026METHOD OF FORMING NANOSTRUCTURED SURFACE ON POLYMER ELECTROLYTE MEMBRANE OF MEMBRANE ELECTRODE ASSEMBLY FOR FUEL CELL - The present invention provides a method of forming a nanostructured surface (NSS) on a polymer electrolyte membrane (PEM) of a membrane electrode assembly (MEA) for a fuel cell, in which a nanostructured surface is suitably formed on a polymer electrolyte membrane by plasma treatment by plasma-assisted chemical vapor deposition (PACVD), where catalyst particles or a catalyst layer are directly deposited on the surface of the polymer electrolyte membrane having the nanostructured surface.04-29-2010
20100102025METHOD AND APPARATUS FOR MARKING COATED OPHTHALMIC SUBSTRATES OR LENS BLANKS HAVING ONE OR MORE ELECTRICALLY CONDUCTIVE LAYERS - A method for marking an ophthalmic substrate or other ophthalmic article comprising the steps of 04-29-2010
20100108636Integrated Tool for Fabricating an Electronic Component - A tool for use in fabricating an electronic component includes a plurality of processing modules and a transfer chamber in communication with each of the plurality of processing modules. The transfer chamber includes a component for transferring a structure to each of the plurality of processing modules. The plurality of processing modules and the transfer chamber are sealed from the surrounding environment and are under a vacuum. The plurality of processing modules includes a first module configured to perform a first process on the structure and a second module configured to perform a second process on the structure. The first process includes performing at least one shaping operation on the structure.05-06-2010
20100108637MULTILAYER PRINTED WIRING BOARD AND METHOD OF MANUFACTURING THE SAME - A multilayer printed wiring board manufacturing method including forming conductor posts, which are of substantially uniform thickness and with which the top surfaces are protected by a resist, on a conductor pattern disposed on an upper surface of a build-up layer formed on a core substrate, shaping the conductor posts to have a constriction by adjusting the time of immersion in an etching solution that etches the conductor posts, forming a low elastic modulus layer of substantially the same height as the conductor posts after removing the resist at the top surfaces, and forming mounting electrodes on upper surfaces of the conductor posts.05-06-2010
20120211465FLEX-RIGID PRINTED WIRING BOARD AND MANUFACTURING METHOD THEREOF - A flex-rigid printed wiring board is provided which can retain flexibility of a flexible portion while increasing durability of the flexible portion against folding, and can ensure conduction in a rigid portion, and a method of manufacturing the printed wiring board. The flex-rigid printed wiring board includes a conductor layer provided on at least one face of a base film, one region of the wiring board containing the base film being a rigid region, an another region containing the base film being a flexible region. The average thickness “tf” of the conductor layer on the base film formed in the flexible region and the average thickness “tR” of the conductor layer on the base film formed in the rigid region satisfy the relationship of tf08-23-2012
20120211463PROCESS FOR REALIZATION OF POLYMERIC MATERIALS WITH SECOND ORDER NONLINEAR ELECTRO-OPTICAL PROPERTIES AND ELECTRO-OPTICAL DEVICES MADE WITH SAID MATERIAL - The present invention concerns a process for realization of polymeric materials with second order nonlinear electro-optical properties comprising the following steps: 08-23-2012
20130082026Method for chemically plating metal on surface of capacitive touch panel - A method for chemically plating metal on surfaces of a capacitive touch panel includes sputtering ITO on surfaces of a glass substrate of a capacitive touch panel to form a double-sided ITO glass; dividing the double-sided ITO glass into a visible region and a peripheral region of a touch glass according to layout; etching on the visible region of each touch glass via a photo art to form induction electrodes of a sensor and etching on the peripheral region thereof to form wiring traces; and thereafter printing a protecting film on the visible region of each touch glass and plating the wiring traces of each touch glass with metal via a chemical nickel plating art and a chemical gold plating art.04-04-2013
20130134127WIRING BOARD AND METHOD OF FABRICATING THE SAME - A wiring board includes an electrode pad having a first surface and a second surface located on an opposite side from the first surface, a conductor pattern connected to the first surface of the electrode pad, and an insulator layer embedded with the electrode pad and the conductor pattern. The insulator layer covers an outer peripheral portion of the second surface of the electrode pad.05-30-2013
20130134126REDUCING DEFECTS IN ELECTRONIC APPARATUS - A technique, comprising defining at least part of one or more electronic devices on a substrate sheet by means of one or more material removal processes, wherein the substrate sheet is arranged on a lower layer so as to overhang said lower layer more at a first end than it does at an opposite, second end; and removing loose material from under said overhang at said first end by means of a stream of gas directed at said substrate and said lower layer from an outlet, said stream of gas having at said outlet at least a directional component parallel to a direction from said second end to said first end.05-30-2013
20120181249PROCESSING LIQUID FOR SUPPRESSING PATTERN COLLAPSE OF FINE METAL STRUCTURE AND METHOD FOR PRODUCING FINE METAL STRUCTURE USING SAME - There are provided a processing liquid for suppressing pattern collapse of a fine metal structure, containing at least one member selected from an imidazolium halide having an alkyl group containing 12, 14 or 16 carbon atoms, a pyridinium halide having an alkyl group containing 14 or 16 carbon atoms, an ammonium halide having an alkyl group containing 14, 16 or 18 carbon atoms, a betaine compound having an alkyl group containing 12, 14 or 16 carbon atoms, and an amine oxide compound having an alkyl group containing 14, 16 or 18 carbon atoms, and a method for producing a fine metal structure using the same.07-19-2012
20120181248RESIST STRIPPING SOLUTION COMPOSITION, AND METHOD FOR STRIPPING RESIST BY USING SAME - Disclosed is a resist stripping solution composition, which is highly capable of removing a resist pattern and an etching residue after dry etching or wet etching, manifests excellent anticorrosive effects on metal wiring including aluminum and/or copper because a predetermined polyol compound is used, and also can process a number of substrates because a predetermined amide compound is used, thus greatly contributing to reducing the cost. A method of stripping a resist using the resist stripping solution composition is also provided.07-19-2012
20090045161INTEGRATED CIRCUITS, MICROMECHANICAL DEVICES, AND METHOD OF MAKING SAME - A method of making an integrated circuit comprises providing a substrate and forming a structure on the substrate comprising a first enclosed portion of a carbon material and a second portion of the carbon material, wherein an intersection of the first and second portion of the carbon material has a defined dimension. The method further comprises processing the substrate with a plasma comprising hydrogen in order to etch the second portion of the carbon material, wherein the defined dimension of the intersection of the first and second portion of the carbon material substantially suppresses etching of the first enclosed portion of the carbon material in a self-limiting way.02-19-2009
20130048597METHOD OF MANUFACTURING TRANSPARENT CONDUCTIVE FILM - A method of manufacturing a transparent conductive film has the steps of: preparing a laminated body in which a transparent conductive layer that is not patterned is formed on a flexible transparent base, removing a part of the transparent conductive layer to form the pattern forming part having the transparent conductive layer on the flexible transparent base and the pattern opening part not having the transparent conductive layer on the flexible transparent base, and heating the laminated body in which the transparent conductive layer is patterned. The absolute value of the difference H02-28-2013
20110000877HEAD SUSPENSION FLEXURE WITH INLINE LEAD PORTIONS - An integrated lead head suspension flexure including a plurality of integrated leads each including at least one lead portion unbacked by the flexure spring metal layer and configured to be substantially inline with the general plane of the spring metal layer. The leads are disposed on a dielectric layer including an unbacked dielectric layer portion having a surface positioned between the major surfaces of the spring metal layer.01-06-2011
20120103930METHOD OF MAKING FUSIBLE LINKS - Methods of fabricating the fusible link are directed to processing a multi-layer clad foil having a first layer suitable for forming a fusible link and a second layer suitable for forming one or more welding pads. In some embodiments, the first layer is an aluminum layer and the second layer is a nickel layer. A two-step etching process or a single step etching process is performed on the clad foil to form an etched clad foil having multiple tabs made of the second layer used as current collector conductor pads and battery cell conductor pads, and one or more tabs made of the first layer that form aluminum conductors. The aluminum conductors are shaped and sized to form aluminum fusible conductors during either the etching process or a subsequent stamping process. A single fusible link or an array of fusible links can be formed.05-03-2012
20120217218PIEZOELECTRIC VIBRATING REED, PIEZOELECTRIC VIBRATING REED MANUFACTURING METHOD, PIEZOELECTRIC VIBRATOR, OSCILLATOR, ELECTRONIC DEVICE AND RADIO TIMEPIECE - An electrode forming step of forming a pair of electrodes by patterning an electrode film on an outer surface of a piezoelectric plate includes: an electrode film forming step of forming the electrode film; a photoresist film forming step of forming a photoresist film on the electrode film; a first exposure step of exposing the photoresist film through a mask; and a second exposure step of further exposing the photoresist film through a correction mask on which a second opening is disposed at a position overlapping with a part of the first opening. An opening width of the second opening corresponding to a clearance between the pair of electrodes is equal to or less than an opening width of the first opening corresponding to the clearance.08-30-2012
20130056439METHOD OF MANUFACTURING METAL-BASE SUBSTRATE AND METHOD OF MANUFACTURING CIRCUIT BOARD - A method of manufacturing a metal-base substrate having an insulative adhesive layer and a conductor layer on a metal-based material is provided. The method includes the steps of dispersing a disperse phase in an insulative adhesive-dispersing medium that contains a wetting dispersant and constitutes the insulative adhesive layer; laminating step of laminating the insulative adhesive on the conductor foil as feeding the roll-shaped conductor foil; curing the insulative adhesive on the conductor foil under heat into a B stage state and thus forming a composite of the conductor foil and the insulative adhesive layer in the B stage state; laminating the metal-based material on the insulative adhesive layer in the B stage state to give a laminate; and then curing the insulative adhesive layer in the B stage state into a C stage state by heat pressurization of the laminate.03-07-2013
20130056438COMPOSITION AND METHOD FOR MICRO ETCHING OF COPPER AND COPPER ALLOYS - Disclosed is a composition for and applying said method for micro etching of copper or copper alloys during manufacture of printed circuit boards. Said composition comprises a copper salt, a source of halide ions, a buffer system and a benzothiazole compound as an etch refiner. The inventive composition and method is especially useful for manufacture of printed circuit boards having structural features of ≦100 μm.03-07-2013
20120305521Conductive Anti-Reflective Films - A method of applying a transparent conductive film to a polymeric substrate having a desired textured therein is provided. The method includes the steps of providing a polymeric material having a texture disposed therein and conformally applying a transparent conductive material to the molded polymeric material to produce a conformal transparent conductive film thereon. The conformal transparent conductive film has a texture corresponding to the texture of the polymeric material and has a period that is not larger than the wavelength of visible light, whereby the conformal transparent conductive film is antireflective.12-06-2012
20090277868Producing method of wired circuit board - A producing method of a wired circuit board includes a laminating step of preparing a metal supporting board, forming an insulating base layer on the metal supporting board, forming a conductive layer including a terminal portion and a plating lead continued from the terminal portion on the insulating base layer, and forming an insulating cover layer on the insulating base layer so as to cover the conductive layer, a first etching step of etching the metal supporting board, and then etching the insulating base layer to expose the plating lead from the metal supporting board and the insulating base layer, and a second etching step of etching the exposed plating lead.11-12-2009
20120223046PRINTING METHOD FOR PRINTING ELECTRONIC DEVICES AND RELATIVE CONTROL APPARATUS - Embodiments of the invention may provide a method of printing one or more print tracks on a print support, or substrate, comprising two or more printing steps in each of which a layer of material is deposited on the print support according to a predetermined print profile. In each printing step, subsequent to the first step, each layer of material is deposited at least partially on top of the layer of material printed in the preceding printing step, so that each layer of printed material has an identical or different print profile with respect to at least a layer of material underneath. The method may further comprise depositing material in each printing step that is equivalent to or different from the material deposited in at least one of other the print layers.09-06-2012
20110011828ORGANICALLY MODIFIED ETCH CHEMISTRY FOR ZNO TCO TEXTURING - Embodiments disclosed herein generally relate to a process of texturing a transparent conductive oxide layer deposited over a substrate. The transparent oxide layer is sometimes deposited onto a substrate for later use in a solar cell device. After the transparent conductive oxide layer is deposited, the layer is textured to increase the haze of the layer. An increase in haze permits the layer to increase light trapping and thus improve the efficiency of a solar cell. A wet etch chemistry that utilizes a component that is less polar than water permits the acidic component, such as nitric acid, to dissociate less and thus etch the transparent conductive oxide to the desired texture. A suitable component is an organic component such as acetic acid which has a dielectric constant substantially below the dielectric constant of water.01-20-2011
20130112650ROOM TEMPERATURE GLASS-TO-GLASS, GLASS-TO-PLASTIC AND GLASS-TO-CERAMIC/SEMICONDUCTOR BONDING - A process for room temperature substrate bonding employs a first substrate substantially transparent to a laser wavelength is selected. A second substrate for mating at an interface with the first substrate is then selected. A transmissivity change at the interface is created and the first and second substrates are mated at the interface. The first substrate is then irradiated with a laser of the transparency wavelength substantially focused at the interface and a localized high temperature at the interface from energy supplied by the laser is created. The first and second substrates immediately adjacent the interface are softened with diffusion across the interface to fuse the substrates.05-09-2013
20130068720PATTERN FORMING METHOD - According to one embodiment, a method includes: forming a film to be processed having a step; forming an uncured first imprint resist; curing the first imprint resist, with a flat surface of a first template pressed against a front surface of the first imprint resist, and planarizing the front surface; forming an intermediate transfer film made of a material different from a material of the first imprint resist; forming an uncured second imprint resist made of a material different from the material of the intermediate transfer film; curing the second imprint resist, with irregularities of a second template contacted with the second imprint resist, and forming an irregular pattern having the irregularities inverted on the second imprint resist; processing the intermediate transfer film by etching using the second imprint resist; and processing the film by etching using the processed intermediate transfer film.03-21-2013
20130068721ELECTRODE FOR SUPER-CAPACITOR, SUPER-CAPACITOR INCLUDING ELECTRODE, AND METHOD FOR PREPARING ELECTRODE - An electrode for a super-capacitor, a super-capacitor including the electrode, and a method of preparing the electrode in which the electrode includes a conductive substrate; metal nano structures formed on the conductive substrate; and a metal oxide coated on the metal nano structures. The electrode for the super-capacitor increases the capacitance of the super-capacitor.03-21-2013
20130161283SAW FILTER HAVING PLANAR BARRIER LAYER AND METHOD OF MAKING - Disclosed herein is a surface acoustic wave (SAW) filter and method of making the same. The SAW filter includes a piezoelectric substrate; a planar barrier layer disposed above the piezoelectric substrate, and at least one conductor buried in the piezoelectric substrate and the planar barrier layer.06-27-2013
20130161284TREATMENT LIQUID FOR INHIBITING PATTERN COLLAPSE IN MICROSTRUCTURES, AND MICROSTRUCTURE MANUFACTURING METHOD USING SAID TREATMENT LIQUID - There are provided a processing liquid for suppressing pattern collapse of a microstructure formed of silicon oxide which includes at least one compound selected from the group consisting of a fluoroalkyl group-containing ammonium halide, a fluoroalkyl group-containing betaine compound and a fluoroalkyl group-containing amine oxide compound, and water; and a method for producing a microstructure formed of silicon oxide using the processing liquid.06-27-2013
20130161285AQUEOUS POLISHING COMPOSITION AND PROCESS FOR CHEMICALLY MECHANICALLY POLISHING SUBSTRATE MATERIALS FOR ELECTRICAL, MECHANICAL AND OPTICAL DEVICES - An aqueous polishing composition comprising (A) abrasive particles which are positively charged when dispersed in an aqueous medium having a pH in the range of from 3 to 9 as evidenced by the electrophoretic mobility; (B) water-soluble and water-dispersible hydroxy group containing components selected from (b1) aliphatic and cycloaliphatic hydroxycarboxylic acids, wherein the molar ratio of hydroxy groups to carboxylic acid groups is at least 1; (b2) esters and lactones of the hydroxycarboxylic acids (b1) having at least one hydroxy group; and (b3) mixtures thereof; and (C) water-soluble and water-dispersible polymer components selected from (c1) linear and branched alkylene oxide polymers; (c2) linear and branched, aliphatic and cycloaliphatic poly(N-vinylamide) polymers; and (c3) cationic polymeric flocculents having a weight average molecular weight of less than 100,000 Dalton.; and a process for polishing substrate materials for electrical, mechanical and optical devices.06-27-2013
20110278257METHOD FOR MANUFACTURING A PIEZOELECTRIC MEMBRANE TYPE DEVICE - A substrate 11-17-2011
20090250428METHOD AND APPARATUS FOR ELECTROCHINETIC TRANSPORT - Controlled electrokinetic transport of constituents of liquid media can be achieved by connecting at least two volumes containing liquid media with at least one dielectric medium with opposing dielectric surfaces in direct contact with said liquid media, and establishing at least one conduit across said dielectric medium, with a conduit inner surface surrounding a conduit volume and at least a first opening and a second opening opposite to the first opening. The conduit is arranged to connect two volumes containing liquid media and includes a set of at least three electrodes positioned in proximity of the inner conduit surface. A power supply is arranged to deliver energy to the electrodes such that time-varying potentials inside the conduit volume are established, where the superposition of said potentials represents at least one controllable traveling potential well that can travel between the opposing conduit openings.10-08-2009
20110315655METHOD OF PROCESSING GRAPHENE SHEET MATERIAL AND METHOD OF MANUFACTURING ELECTRONIC DEVICE - A method of processing a graphene sheet material includes irradiating UV ray to a graphene sheet material in an atmosphere containing a first substance to inactivate an edge of the graphene sheet material by substituting an end group connected to the edge of the graphene sheet material with more stable functional group generated from the first substance, and irradiating UV ray to a surface of the graphene sheet material in an atmosphere containing a second substance containing oxygen to activate the second substance, and oxidize and remove a graphene sheet contained in the graphene sheet material sequentially from a surface side.12-29-2011
20080264898SELECTIVE ETCH OF TiW FOR CAPTURE PAD FORMATION - A chemical etchant containing hydrogen peroxide and phosphate ions at a controlled pH is provided for selectively etching metals in the presence of one or more metals not to be etched. The etchant is useful in the fabrication of semiconductor components particularly for forming capture pads where TiW is used as a barrier layer for a copper, copper/nickel pad, or copper/nickel alloy pad. A commercial hydrogen peroxide solution is preferred to which has been added phosphoric acid as a source of phosphate ions and KOH as the pH adjuster.10-30-2008
20100170868SPIN-ON SPACER MATERIALS FOR DOUBLE- AND TRIPLE-PATTERNING LITHOGRAPHY - Novel double- and triple-patterning methods are provided. The methods involve applying a shrinkable composition to a patterned template structure (e.g., a structure having lines) and heating the composition. The shrinkable composition is selected to possess properties that will cause it to shrink during heating, thus forming a conformal layer over the patterned template structure. The layer is then etched to leave behind pre-spacer structures, which comprise the features from the pattern with remnants of the shrinkable composition adjacent the feature sidewalls. The features are removed, leaving behind a doubled pattern. In an alternative embodiment, an extra etch step can be carried out prior to formation of the features on the template structure, thus allowing the pattern to be tripled rather than doubled.07-08-2010
20110284494Method for Manufacturing an Opto-Electronic Component - A method of producing an optoelectronic component comprises the steps of: A) providing a radiation-emitting layer sequence (11-24-2011
20110297642NANOWIRE-BASED TRANSPARENT CONDUCTORS AND APPLICATIONS THEREOF - A transparent conductor including a conductive layer coated on a substrate is described. More specifically, the conductive layer comprises a network of nanowires that may be embedded in a matrix. The conductive layer is optically clear, patternable and is suitable as a transparent electrode in visual display devices such as touch screens, liquid crystal displays, plasma display panels and the like.12-08-2011
20110297643METHOD OF HYDROPHOBIZING AND PATTERNING FRONTSIDE SURFACE OF INTEGRATED CIRCUIT - A method of hydrophobizing a frontside surface of an integrated circuit. The method includes the steps of: (a) depositing a hydrophobic polymeric layer onto the frontside surface; (b) depositing a protective metal film onto the hydrophobic polymeric layer; (c) depositing a sacrificial material onto the metal film; (d) patterning the sacrificial material; (e) etching through the metal film, the hydrophobic polymeric layer and the frontside surface; (f) performing MEMS processing steps on a backside of the integrated circuit; (g) subjecting the integrated circuit to an oxidizing plasma, wherein the metal film protects the hydrophobic polymeric layer from the oxidizing plasma; and (h) removing the protective metal film to provide an integrated circuit having a relatively hydrophobic patterned frontside surface.12-08-2011
20110297641Rolled Copper Foil or Electrolytic Copper Foil for Electronic Circuit, and Method of Forming Electronic Circuit using same - Provided is a rolled copper foil or electrolytic copper foil for an electronic circuit to be used for forming a circuit by etching, wherein the copper foil comprises a nickel or nickel alloy layer with a lower etching rate than copper formed on an etching side of the rolled copper foil or electrolytic copper foil, and a heat resistance layer composed of zinc or zinc alloy or its oxide formed on the nickel or nickel alloy layer. This invention aims to prevent sagging caused by the etching, to form a uniform circuit having the intended circuit width, and to shorten the time of forming a circuit by etching as much as possible, when forming a circuit by etching a copper foil of the copper-clad laminate; and also aims to make the thickness of the nickel or nickel alloy layer as thin as possible, to inhibit oxidation when exposed to heat, to prevent tarnish (discoloration) known as “YAKS”, to improve the etching properties in pattern etching, and to prevent the occurrence of short circuits and defects in the circuit width.12-08-2011
20110215068ELECTROLESS PLATING PRODUCTION OF NICKEL AND COBALT STRUCTURES - A method comprising forming a structural element 09-08-2011
20120024817APPARATUS AND METHOD FOR PLASMA SURFACE TREATMENT - An apparatus and a method for plasma surface treatment which treats a surface of a treatment portion of an electrically conductive object using ions from plasma are disclosed. The apparatus includes a connector electrically connected to the treatment portion for applying negative voltage pulses to the treatment portion; a pulse voltage generating unit electrically connected to the connector; and magnetic cores disposed at the boundary of the treatment portion for preventing electric current caused by the negative voltage pulses applied to the treatment portion from flowing across the boundary of the treatment portion is provided. The apparatus and method for plasma surface treatment can confine the treatment portion by using negative high voltage pulses and magnetic cores. Also, the apparatus and method can apply negative high voltage pulse to the treatment portion of an electrically grounded object such as a metal sheet coil and a metal wire coil.02-02-2012
20120024816METHOD FOR FABRICATING TOUCH SENSOR PANELS - A method for fabricating a touch sensor panel is disclosed. The method includes providing a substrate for the touch sensor panel, depositing a conductive material layer on a top surface of the substrate, depositing a metal layer on top of the conductive material layer, affixing a resist to a first area of the metal layer, the resist also adapted to serve as a passivation layer during passivation, removing metal from the metal layer outside of the first area; and performing passivation on the substrate while leaving the affixed resist intact.02-02-2012
20090145877METHOD FOR CONTROLLING ADI-AEI CD DIFFERENCE RATIO OF OPENINGS HAVING DIFFERENT SIZES - A method for controlling an ADI-AEI CD difference ratio of openings having different sizes is described. The openings are formed through a silicon-containing material layer, an etching resistive layer and a target material layer in turn. Before the opening etching steps, at least one of the opening patterns in the photoresist mask is altered in size through photoresist trimming or deposition of a substantially conformal polymer layer. A first etching step forming thicker polymer on the sidewall of the wider opening pattern is performed to form a patterned Si-containing material layer. A second etching step is performed to remove exposed portions of the etching resistive layer and the target material layer. At least one parameter among the parameters of the photoresist trimming or polymer layer deposition step and the etching parameters of the first etching step is controlled to obtain a predetermined ADI-AEI CD difference ratio.06-11-2009
20090120901PATTERNED ELECTRODES WITH REDUCED RESIDUE - Aspects of the present invention provide patterned electrodes with substantially reduced or removed residue. Aspects of the present invention for removing residue are applicable to any fabricated structure including transparent electrodes. By substantially reducing or removing residue typically associated with methods used to form patterned electrodes, an improvement in performance can be realized by ensuring that the deposition of subsequent materials onto a substrate is not adversely affected by any such residue. In turn, better interconnects can be formed and better coverage of subsequent layers can be achieved. The method for producing patterned electrodes with substantially reduced or removed residue in accordance with the present invention can be used in conjunction with any known method for patterning conductors or electrodes.05-14-2009
20090212007SURFACE TREATMENT METHOD - According to the present invention, a plasma treatment process is performed for a surface of a metal film exposed through a resin layer, including a foreign resin substance attached to the surface, so that the foreign resin substance can be roughened without substantially damaging the resin layer; and the entire exposed surface of the metal film is etched, using a spray etching method for which an etching fluid is ejected through a nozzle, and the foreign resin substance is removed from the exposed surface.08-27-2009
20110147340TRANSPARENT CONDUCTIVE FILM, METHOD FOR PRODUCTION THEREOF AND TOUCH PANEL THEREWITH - A transparent conductive film includes: a transparent film substrate; a transparent conductor layer provided on one or both sides of the transparent film substrate; and at least one undercoat layer interposed between the transparent film substrate and the transparent conductor layer; wherein: the transparent conductor layer is patterned; and a non-patterned portion not having the transparent conductor layer has the at least one undercoat layer.06-23-2011
20110147337USE OF BLOCK COPOLYMERS FOR PREPARING CONDUCTIVE NANOSTRUCTURES - Methods for preparing one or more conductive nanostructures are provided. In accordance with one embodiment, a method for preparing one or more conductive nanostructures may include providing a composite of nanoparticles and block copolymer including one or more first microdomains and one or more second microdomains, where conductive nanoparticles are selectively distributed in the one or more first microdomains, removing the first microdomains while leaving the conductive nanoparticles in the composite, forming one or more conductive nanostructures on the conductive nanoparticles, and removing the second microdomains.06-23-2011
20090272714METHOD OF FORMING AN INTEGRATED CIRCUIT WITH MM-WAVE ANTENNAS USING CONVENTIONAL IC PACKAGING - A method of forming the integrated circuit. The method includes, in an integrated circuit package, forming each bond to or from an integrated circuit pad that is intended to be an antenna connection to be elongated compared to other bonds, and arranged in an approximately perpendicular direction to the plane of the integrated circuit; encapsulating the top of the integrated circuit package with a dielectric material at a height greater than a desired antenna length; and milling the dielectric encapsulation down to a pre-selected and calibrated height, such that the elongated bond wire to/from the integrated circuit pad that is intended to be an antenna connection is severed, such that the approximately vertical bond wire to/from the integrated circuit pad that is intended to be an antenna connection forms a quarter wave monopole.11-05-2009
20080210660Medium For Etching Oxidic, Transparent, Conductive Layers - The present invention relates to a novel dispensable medium for etching doped tin oxide layers having non-Newtonian flow behaviour for etching surfaces in the production of displays and/or solar cells and to the use thereof. In particular, it relates to corresponding particle-free compositions by means of which fine structures can be etched selectively without damaging or attacking adjacent areas.09-04-2008
20110168666MANUFACTURING METHOD FOR OPTICAL WAVEGUIDE - A method of manufacturing an optical waveguide is disclosed. The method in accordance with an embodiment of the present invention includes providing a carrier, fixing a base substrate to the carrier by using a first insulation layer such that the base substrate is directly stacked on the carrier, stacking an optical waveguide layer on at least one of the base substrate and the first insulation layer, and severing the base substrate such that the base substrate and the optical waveguide layer are separated from the carrier. Accordingly, the optical waveguide layer can be formed with a uniform thickness since wrinkles in the base substrate supporting the optical waveguide layer are prevented from forming during the manufacturing process.07-14-2011
20090277867Topography reduction and control by selective accelerator removal - Plating accelerator is applied selectively to a substantially-unfilled wide (e.g., low-aspect-ratio feature cavity. Then, plating of metal is conducted to fill the wide feature cavity and to form an embossed structure in which the height of a wide-feature metal protrusion over the metal-filled wide-feature cavity is higher than the height of metal over field regions. Most of the overburden metal is removed using non-contact techniques, such as chemical wet etching. Metal above the wide feature cavity protects the metal-filled wide-feature interconnect against dishing, and improved planarization techniques avoid erosion of the metal interconnect and dielectric insulating layer. In some embodiments, plating of metal onto a substrate is conducted to fill narrow (e.g., high-aspect-ratio feature cavities) in the dielectric layer before selective application of plating accelerator and filling of the wide feature cavity.11-12-2009
20090283497METHOD OF MANUFACTURING WIRING SUBSTRATE - A method of manufacturing a wiring substrate of the present invention, includes the steps of forming a seed layer on an underlying layer, forming a plating resist in which an opening portion is provided on the seed layer, forming a copper plating layer in the opening portion by an electroplating, removing the plating resist, wet-etching the seed layer using the copper plating layer as a mask to obtain the wiring layer, roughening a surface of the wiring layer by a blackening process, and forming an insulating layer on the wiring layer, wherein a surface of the copper plating layer is soft-etched simultaneously in the step of etching the seed layer, whereby a soft etching step of the wiring layer carried out prior to the step of the blackening process is omitted.11-19-2009
20100200539PLASTIC CAPACITIVE TOUCH SCREEN AND METHOD OF MANUFACTURING SAME - A method of removing portions of a conductive layer comprising a transparent conductive material and/or a metallic material disposed on a plastic substrate used for capacitive touchscreen devices includes providing a plastic substrate having a conductive layer disposed on a surface thereof and removing portions of the conductive layer at the surface of the plastic substrate to establish a pattern of electrically isolated conductive portions on the surface of the plastic substrate. The conductive portions or traces are electrically connected to a touchscreen controller, which is operable to determine a location of a touch or proximity of an object at or near the surface of the plastic substrate responsive to a detected change in capacitance. The removal process may comprise etching or laser ablating portions of the conductive layer at the surface of the plastic substrate.08-12-2010
20090166319System and Method for Performing High Flow Rate Dispensation of a Chemical onto a Photolithographic Component - A system and method for performing high flow rate dispensation of a chemical onto a photolithographic component are disclosed. The system and method includes providing a photolithographic component in a manufacturing tool. The photolithographic is positioned at a predetermined distance from a nozzle dispensing a chemical. Dispensation of a chemical at a high flow rate onto a photolithographic component, the rate of flow operable to reduce harmful effects from occurring on the surface of the photolithographic substrate.07-02-2009
20110204020Method of and Printable Compositions for Manufacturing a Multilayer Carbon Nanotube Capacitor - Multilayer carbon nanotube capacitors, and methods and printable compositions for manufacturing multilayer carbon nanotubes (CNTs) are disclosed. A first capacitor embodiment comprises: a first conductor; a plurality of fixed CNTs in an ionic liquid, each fixed CNT comprising a magnetic catalyst nanoparticle coupled to a carbon nanotube and further coupled to the first conductor; and a first plurality of free CNTs dispersed and moveable in the ionic liquid. Another capacitor embodiment comprises: a first conductor; a conductive nanomesh coupled to the first conductor; a first plurality of fixed CNTs in an ionic liquid and further coupled to the conductive nanomesh; and a plurality of free CNTs dispersed and moveable in the ionic liquid. Various methods of printing the CNTs and other structures, and methods of aligning and moving the CNTs using applied electric and magnetic fields, are also disclosed.08-25-2011
20110204019Method of making a planar electrode - Chemical mechanical polishing (CMP) of thin film materials using a slurry including a surfactant chemical operative to polish high portions of the film being planarized while preventing the polishing of low portions of the film is disclosed. The low portions can be in a step reduction region of a deposited film. The CMP process can be used for form a planar surface upon which subsequent thin-film layers can be deposited, such as an electrically conductive material for an electrode. The subsequently deposited thin-film layers are substantially planar as deposited without having to use CMP. The resulting thin-film layers are planar and have a uniform cross-sectional thickness that can be beneficial for layers of memory material for a memory cell. The processing can be performed back-end-of-the-line (BEOL) on a previously front-end-of-the-line (FEOL) processed substrate (e.g., silicon wafer) and the BEOL process can be used to fabricate two-terminal non-volatile cross-point memory arrays.08-25-2011
20080237181HYBRID LAYERS FOR USE IN COATINGS ON ELECTRONIC DEVICES OR OTHER ARTICLES - A method for forming a coating over a surface is disclosed. The method comprises depositing over a surface, a hybrid layer comprising a mixture of a polymeric material and a non-polymeric material. The hybrid layer may have a single phase or comprise multiple phases. The hybrid layer is formed by chemical vapor deposition using a single source of precursor material. The chemical vapor deposition process may be plasma-enhanced and may be performed using a reactant gas. The precursor material may be an organo-silicon compound, such as a siloxane. The hybrid layer may comprise various types of polymeric materials, such as silicone polymers, and various types of non-polymeric materials, such as silicon oxides. By varying the reaction conditions, the wt % ratio of polymeric material to non-polymeric material may be adjusted. The hybrid layer may have various characteristics suitable for use with organic light-emitting devices, such as optical transparency, impermeability, and/or flexibility.10-02-2008
20090166318Method of Fabricating an Integrated Circuit - A method of fabricating an integrated circuit includes providing a hard mask that includes at least one first layer and one second layer. An etching step is patterned using the hard mask, and a removal step is performed using an etchant in order to at least partially remove the first layer. The first layer and the second layer are configured in such a way that the first layer is etched by the etchant with a higher etch rate than the second layer.07-02-2009
20080283490PROTECTION LAYER FOR FABRICATING A SOLAR CELL - A method for fabricating a solar cell is described. The method includes first providing, in a process chamber, a substrate having a light-receiving surface. An anti-reflective coating (ARC) layer is then formed, in the process chamber, above the light-receiving surface of the substrate. Finally, without removing the substrate from the process chamber, a protection layer is formed above the ARC layer.11-20-2008
20080283488Method For Producing a Ceramic Printed-Circuit Board - A ceramic substrate (S) has on its top side weldable connection surfaces (LA) and on its underside weldable contacts (LK). In the disclosed substrate (S), the weldable connection surfaces, which were until now produced using printing pastes, is replaced by weld surface contacts precipitated from a solution and directly applied to the ceramic material. These weld contact surfaces are characterised by a more even surface, improved bondability and structurability.11-20-2008
20090314739WET PROCESSING SYSTEM AND WET PROCESSING METHOD - An exemplary system for processing a workpiece comprises a conveyor, a first liquid spraying device, a second liquid spraying device, and a substrate positioning device. The conveyor is configured for conveying the workpiece along a conveying direction. The first and second liquid spraying devices for spraying liquid onto the workpiece transported on the conveyor face the conveyor and are arranged along the conveying direction. The substrate positioning device for reorienting the workpiece on the conveyor is installed between the first and second liquid spraying devices and faces the conveyor.12-24-2009
20080251494Method for manufacturing circuit board - A method of manufacturing a circuit board is disclosed. The method may include: forming a relievo pattern, which is in a corresponding relationship with a circuit pattern, on a metal layer that is stacked on a carrier; stacking and pressing the carrier onto an insulation layer with the relievo pattern facing the insulation layer; transcribing the metal layer and the relievo pattern into the insulation layer by removing the carrier; forming a via hole in the insulation layer on which the metal layer is transcribed; and filling the via hole and forming a plating layer over the metal layer by performing plating over the insulation layer on which the metal layer is transcribed. As the relievo pattern may be formed on the metal layer stacked on the carrier, and the relievo pattern may be transcribed into the insulation layer, high-density circuit patterns can be formed.10-16-2008
20130119012INTERCONNECTION ELEMENT FOR ELECTRIC CIRCUITS - An interconnection element and method for making same is disclosed. The interconnection element may include a plurality of metal conductors, a plurality of solid metal bumps and a low melting point (LMP) metal layer. The solid metal bumps overly and project in a first direction away from respective ones of the conductors. Each bump has at least one edge bounding the bump in at least a second direction transverse to the first direction. The low melting point (LMP) metal layer has a first face joined to the respective ones of the conductors and bounded in the second direction by at least one edge and a second face joined to the bumps. The edges of the bumps and the LMP layer are aligned in the first direction, and the LMP metal layer has a melting temperature substantially lower than the conductors.05-16-2013
20120193323METHOD FOR OPERATING SUBSTRATE PROCESSING APPARATUS - A method for operating a substrate processing apparatus is provided which can contain generation of particles by generating plasma in a stable manner. After a substrate is disposed in an evacuated vacuum chamber, a rare gas is initially supplied into the vacuum chamber, a voltage is applied to a plasma generating means, and plasma of the rare gas is generated. Subsequently, a reaction gas is supplied into the vacuum chamber, the reaction gas is brought into contact with the plasma of the rare gas, and plasma of the reaction gas is generated. The plasma of the reaction gas is brought into contact with the substrate; and the substrate is processed. Plasma is stably generated not by turning the reaction gas into plasma but by first turning the rare gas into plasma by the plasma generating means, and generation of particles is subsequently suppressed.08-02-2012
20090184089FABRICATION OF A SILICON STRUCTURE AND DEEP SILICON ETCH WITH PROFILE CONTROL - A method of etching features into a silicon layer with a steady-state gas flow is provided. An etch gas comprising an oxygen containing gas and a fluorine containing gas is provided. A plasma is provided from the etch gas. Then, the flow of the etch gas is stopped.07-23-2009
20090308836DIHYDROXY ENOL COMPOUNDS USED IN CHEMICAL MECHANICAL POLISHING COMPOSITIONS HAVING METAL ION OXIDIZERS - A chemical mechanical polishing composition contains 1) water, 2) optionally an abrasive material, 3) an oxidizer, preferably a per-type oxidizer, 4) a small amount of soluble metal-ion oxidizer/polishing accelerator, a metal-ion polishing accelerator bound to particles such as to abrasive particles, or both; and 5) at least one of the group selected from a) a small amount of a chelator, b) a small amount of a dihydroxy enolic compound, and c) a small amount of an organic accelerator. Ascorbic acid in an amount less than 800 ppm, preferably between about 100 ppm and 500 ppm, is the preferred dihydroxy enolic compound. The polishing compositions and processes are useful for substantially all metals and metallic compounds found in integrated circuits, but is particularly useful for tungsten. The present invention also pertains to surface-modified colloidal abrasive polishing compositions and associated methods of using these compositions, particularly for chemical mechanical planarization, wherein the slurry comprises low levels of chelating free radical quenchers, non-chelating free radical quenchers, or both.12-17-2009
20090184090THIN-FILM ASSEMBLY AND METHOD FOR PRODUCING SAID ASSEMBLY - A thin-film assembly (07-23-2009
20090184088Aerogel-Bases Mold for MEMS Fabrication and Formation Thereof - The invention is directed to a patterned aerogel-based layer that serves as a mold for at least part of a microelectromechanical feature. The density of an aerogel is less than that of typical materials used in MEMS fabrication, such as poly-silicon, silicon oxide, single-crystal silicon, metals, metal alloys, and the like. Therefore, one may form structural features in an aerogel-based layer at rates significantly higher than the rates at which structural features can be formed in denser materials. The invention further includes a method of patterning an aerogel-based layer to produce such an aerogel-based mold. The invention further includes a method of fabricating a microelectromechanical feature using an aerogel-based mold. This method includes depositing a dense material layer directly onto the outline of at least part of a microelectromechanical feature that has been formed in the aerogel-based layer.07-23-2009
20120138566Method for Lithography Etching a Glass Substrate by Miniature Balls - Disclosed is a method for lithography etching a glass substrate. The method includes the steps of providing a glass substrate, providing miniature balls on the glass substrate so that the miniature balls become an etching-resistant layer, etching the glass substrate covered by the miniature balls to make a miniature pattern on the glass substrate, and removing the miniature balls from the substrate.06-07-2012
20120285923System and Method for Removing Oxide from a Sensor Clip Assembly - According to embodiments of the present disclosure, a method for removing oxide includes placing a sensor chip assembly having an oxide layer formed on a portion thereof within an enclosed and controlled environment. The portion of the sensor chip assembly is exposed to a reactive gas and a UV light to result in a substantial removal of the oxide layer formed on the portion of the sensor chip assembly.11-15-2012
20090200263METHOD FOR METALLIZING INSULATING SUBSTRATES WHEREIN THE ROUGHENING AND ETCHING PROCESSES ARE CONTROLLED BY MEANS OF GLOSS MEASUREMENT - The invention relates to a control of etching processes of insulating substrates by means of gloss measurement. By this method a surface roughness can be achieved which leads to good adhesion of metals layers deposited in subsequent metallization steps. This method is particularly suited for the production of printed circuit boards.08-13-2009
20090321387MANUFACTURING METHOD OF PRINTED CIRCUIT BOARD - Disclosed is a manufacturing method of a printed circuit board. The method in accordance with an embodiment of the present invention includes: providing a laminated substrate having an insulator as well as a first metal layer and a second metal layer, which are sequentially laminated on one side of the insulator; processing a via hole in the laminated substrate; forming a seed layer on an inner wall of the via hole and on a surface of the second metal layer; plating an inside of the via hole and the surface of the second metal layer with a conductive material that is different from a material of the second metal layer; etching the seed layer and the conductive material, formed on the second metal layer; etching the second metal layer; and forming a first circuit pattern by selectively etching the first metal layer.12-31-2009
20110220610FLEXIBLE SUBSTRATE WITH ELECTRONIC DEVICES AND TRACES - A method of manufacturing an electronic device (09-15-2011
20090050600METHOD FOR MANUFACTURING PRINTED CIRCUIT BOARDS - An exemplary method for manufacturing printed circuit boards is provided. In the method, a copper clad substrate having a copper layer thereon is provided. A surface of the copper layer is roughened by applying an atmospheric pressure plasma thereto. A photoresist layer is formed on the roughened surface of the copper layer. The photoresist layer is exposed. The photoresist layer is developed to form a patterned photoresist layer, thereby exposing portions of the copper layer. The exposed portions of the copper layer exposed are removed so that the remaining portions of the copper layer form electrical traces. The patterned photoresist layer is removed.02-26-2009
20090057264HIGH THROUGHPUT LOW TOPOGRAPHY COPPER CMP PROCESS - Embodiments described herein generally provide a method for processing metals disposed on a substrate in a chemical mechanical polishing system. The apparatus advantageously facilitates efficient bulk and residual conductive material removal from a substrate. In one embodiment a method for chemical mechanical polishing (CMP) of a conductive material disposed on a substrate is provided. A substrate comprising a conductive material disposed over an underlying barrier material is positioned on a first platen containing a first polishing pad. The substrate is polished on a first platen to remove a bulk portion of the conductive material. A rate quench process is performed in order to reduce a metal ion concentration in the polishing slurry. The substrate is polished on the first platen to breakthrough the conductive material exposing a portion of the underlying barrier material.03-05-2009
20090101623ETCHING PROCESSES USED IN MEMS PRODUCTION - The efficiency of an etching process may be increased in various ways, and the cost of an etching process may be decreased. Unused etchant may be isolated and recirculated during the etching process. Etching byproducts may be collected and removed from the etching system during the etching process. Components of the etchant may be isolated and used to general additional etchant. Either or both of the etchant or the layers being etched may also be optimized for a particular etching process.04-23-2009
20090101622METHOD FOR FABRICATING VARIABLE PARALLEL PLATE CAPACITORS - A method for fabricating micromachined structures is provided. A structure including a dielectric layer, a metal layer and a passivation layer is formed, wherein the dielectric layer has a via thereon. An etching window is formed on the passivation layer. An etching solution is poured into the via through the etching window to perform a process of etching. After etching, the etching solution is removed and the passivation layer is removed. Finally, the structure is etched again to form the micromachined structure.04-23-2009
20090084754METHOD AND SYSTEM FOR MANUFACTURING MICROSTRUCTURE - A method for manufacturing a microstructure includes treating a surface of the microstructure having a wall body with a liquid, supplying a material activating the surface of the liquid to the surface of the microstructure, and drying the surface of the microstructure.04-02-2009
20090152233PRINTED CIRCUIT BOARD HAVING CHIP PACKAGE MOUNTED THEREON AND METHOD OF FABRICATING SAME - Disclosed is a printed circuit board (PCB) and a method of fabricating the same. A contact portion is formed on an internal layer of the multi-layered PCB. A groove is formed so as to expose the contact portion of the internal layer. A chip package is mounted on the PCB while being flip-chip bonded to the exposed contact portion of the internal layer.06-18-2009
20100200538Analyte Sensor and Fabrication Methods - Methods for fabricating analyte sensor components using IC- or MEMs-based fabrication techniques and sensors prepared therefrom. Fabrication of the analyte sensor component comprises providing an inorganic substrate having deposited thereon a release layer, a first flexible dielectric layer and a second flexible dielectric layer insulating there between electrodes, contact pads and traces connecting the electrodes and the contact pads of a plurality of sensors. Openings are provided in one of the dielectric layers over one or more of the electrodes to receive an analyte sensing membrane for the detection of an analyte of interest and for electrical connection with external electronics. The plurality of fabricated sensor components are lifted off the inorganic substrate.08-12-2010
20100200537Nano-patterned metal electrode for solid oxide fuel cell - The current invention provides a method of fabricating nano-pore structured dense Pt electrodes using particle masking and LB deposition methods. The pore size and TPB density are easily tunable by changing initial size of the masking silica particles and the spacing between them. Compared to the solid oxide fuel cell MEAs with porous Pt electrode deposited by conventional DC sputtering method, fuel cell MEAs with the nano structured electrodes fabricated according to the current invention showed thermal and microstructural stability and superior I-V performance at 400˜450° C. Also, EIS spectra showed significant improvement in the oxygen reduction kinetics by increasing the density of charge transfer sites at the TPB. A nearly linear scaling relationship between TPB density and fuel cell performance was also demonstrated.08-12-2010
20090139957Group III-Nitride layers with patterned surfaces - A fabrication method produces a mechanically patterned layer of group III-nitride. The method includes providing a crystalline substrate and forming a first layer of a first group III-nitride on a planar surface of the substrate. The first layer has a single polarity and also has a pattern of holes or trenches that expose a portion of the substrate. The method includes then, epitaxially growing a second layer of a second group III-nitride over the first layer and the exposed portion of substrate. The first and second group III-nitrides have different alloy compositions. The method also includes subjecting the second layer to an aqueous solution of base to mechanically pattern the second layer.06-04-2009
20090212006Horizontal nanotube/nanofiber growth method - A method for forming a nanotube/nanofiber growth catalyst on the sides of portions of a layer of a first material, comprising the steps of depositing a thin layer of a second material; opening this layer at given locations; depositing a very thin catalyst layer; depositing a layer of the first material over a thickness greater than that of the layer of the second material; eliminating by chem./mech. polishing the upper portion of the structure up to the high level of the layer of the second material; and eliminating the second material facing selected sides of the layer portions of the first material.08-27-2009
20090242506Wired circuit board and method for manufacturing wired circuit board and mounting electronic component thereon - A wired circuit board is provided having a high-reliability conductive pattern formed thereon and mounting an electronic component thereon with high accuracy, and a method is provided for manufacturing the wired circuit board and mounting the electronic component thereon. An insulating layer including a mounting portion is formed on a metal supporting layer having a specular gloss of 150 to 500% at an incidence angle of 45°. A conductive pattern is formed on the insulating layer. By a reflection-type optical sensor, a defective shape of the conductive pattern is inspected. Then, an opening is formed by etching the portion of the metal supporting layer which is overlapping the mounting portion such that the mounting portion of the insulating layer exposed by etching has a haze value of 20 to 50%, whereby a TAB tape carrier is obtained. Thereafter, an electronic component is aligned with the mounting portion by a reflection-type optical sensor such that the electronic component is mounted on the mounting portion.10-01-2009
20090250429Methods of Forming Dual-Damascene Metal Wiring Patterns for Integrated Circuit Devices and Wiring Patterns Formed Thereby - Methods of forming dual-damascene metal wiring patterns include forming a first metal wiring pattern (e.g., copper wiring pattern) on an integrated circuit substrate and forming an etch-stop layer on the first metal wiring pattern. These steps are followed by the steps of forming an electrically insulating layer on the etch-stop layer and forming an inter-metal dielectric layer on the electrically insulating layer. The inter-metal dielectric layer and the electrically insulating layer are selectively etched in sequence to define an opening therein that exposes a first portion of the etch-stop layer. This opening may include a trench and a via hole extending downward from a bottom of the trench. A first barrier metal layer is formed on a sidewall of the opening and directly on the first portion of the etch-stop layer. A portion of the first barrier metal layer is selectively removed from the first portion of the etch-stop layer. The first portion of the etch-stop layer is then selectively etched for a sufficient duration to expose a portion of the first metal wiring pattern. A second metal wiring pattern is formed in the opening in order to complete a dual-damascene structure.10-08-2009
20080245765ELECTRICAL CONTACTS - Certain embodiments are directed to methods, devices and systems designed to remove selected portions of a material to expose an underlying material or substrate. One or more electrical components may be coupled to the underlying substrate through an electrical contact. Kits and systems for producing electrical contacts are also provided.10-09-2008
20090095705PROCESS FOR MANUFACTURING AN INTERACTION STRUCTURE FOR A STORAGE MEDIUM - A process manufactures an interaction structure for a storage medium. The process includes forming a first interaction head provided with a first conductive region having a sub-lithographic dimension. The step of forming a first interaction head includes: forming on a surface a first delimitation region having a side wall; depositing a conductive portion having a deposition thickness substantially matching the sub-lithographic dimension on the side wall; and then defining the conductive portion. The sub-lithographic dimension preferably is between 1 and 50 nm, more preferably 20 nm.04-16-2009
20100176083METHOD AND APPARATUS FOR REMOVING ADJACENT CONDUCTIVE AND NON-CONDUCTIVE MATERIALS OF A MICROELECTRONIC SUBSTRATE - A microelectronic substrate and method for removing adjacent conductive and nonconductive materials from a microelectronic substrate. In one embodiment, the microelectronic substrate includes a substrate material (such as borophosphosilicate glass) having an aperture with a conductive material (such as platinum) disposed in the aperture and a fill material (such as phosphosilicate glass) in the aperture adjacent to the conductive material. The fill material can have a hardness of about 0.04 GPa or higher, and a microelectronics structure, such as an electrode, can be disposed in the aperture, for example, after removing the fill material from the aperture. Portions of the conductive and fill material external to the aperture can be removed by chemically-mechanically polishing the fill material, recessing the fill material inwardly from the conductive material, and electrochemically-mechanically polishing the conductive material. The hard fill material can resist penetration by conductive particles, and recessing the fill material can provide for more complete removal of the conductive material external to the aperture.07-15-2010
20120193322Methods of Forming Dual-Damascene Metal Wiring Patterns for Integrated Circuit Devices and Wiring Patterns Formed Thereby - Methods of forming dual-damascene metal wiring patterns include forming a first metal wiring pattern (e.g., copper wiring pattern) on an integrated circuit substrate and forming an etch-stop layer on the first metal wiring pattern. These steps are followed by the steps of forming an electrically insulating layer on the etch-stop layer and forming an inter-metal dielectric layer on the electrically insulating layer. The inter-metal dielectric layer and the electrically insulating layer are selectively etched in sequence to define an opening therein that exposes a first portion of the etch-stop layer. This opening may include a trench and a via hole extending downward from a bottom of the trench. A first barrier metal layer is formed on a sidewall of the opening and directly on the first portion of the etch-stop layer. A portion of the first barrier metal layer is selectively removed from the first portion of the etch-stop layer. The first portion of the etch-stop layer is then selectively etched for a sufficient duration to expose a portion of the first metal wiring pattern. A second metal wiring pattern is formed in the opening in order to complete a dual-damascene structure.08-02-2012
20100264111Enhanced Focused Ion Beam Etching of Dielectrics and Silicon - Silicon, silicon dielectrics and low-k dielectrics are etched in a focused ion beam process using gaseous fluorinating etchants selected from the group of triethylamine trihydrofluoride (TEATHF) and xenon fluoride. Xenon fluoride is combined with a secondary protecting agent to avoid undesired corrosion of bare silicon. The protecting agent may be an oxidizing agent such as oxygen, perfluorotripentylamine (PFTPA), or a heavy completely fluorinated hydrocarbon.10-21-2010
20120103932METHODS FOR FABRICATING CURRENT-CARRYING STRUCTURES USING VOLTAGE SWITCHABLE DIELECTRIC MATERIALS - A method includes providing a voltage switchable dielectric material having a characteristic voltage, exposing the voltage switchable dielectric material to a source of ions associated with an electrically conductive material, and creating a voltage difference between the source and the voltage switchable dielectric material that is greater than the characteristic voltage. Electrical current is allowed to flow from the voltage switchable dielectric material, and the electrically conductive material is deposited on the voltage switchable dielectric material. A body comprises a voltage switchable dielectric material and a conductive material deposited on the voltage switchable dielectric material using an electrochemical process. In some cases, the conductive material is deposited using electroplating.05-03-2012
20120103931METHOD FOR MANUFACTURING PRINTED WIRING BOARD AND PRINTED WIRING BOARD - A method for manufacturing a printed wiring board includes forming a metal film on a surface of an insulative board, a plating resist on the metal film, and a plated-metal film on the metal film exposed from the plating resist, covering a portion of the plated-metal film with an etching resist, etching to reduce thickness of the plated-metal film exposed from the etching resist, removing the etching and plating resists, and forming a wiring having a pad for wire-bonding an electrode of an electronic component and a conductive circuit thinner than the pad by removing the metal film exposed after the plating resist is removed, a solder-resist layer on the surface of the board and wiring, an opening in the layer exposing the pad and a portion of the circuit contiguous to the pad, and a metal coating on the pad and portion of the circuit exposed through the opening.05-03-2012
20100147789METHOD FOR MANUFACTURING PIEZOELECTRIC ELEMENT - A manufacturing method of the present invention comprises the step of epitaxially growing a PZT layer on a first electrode layer, and the step of processing the PZT layer to a desired shape using an etching solution after the growing step. The etching solution contains at least one acid from among hydrochloric acid and nitric acid in a concentration C06-17-2010
20100176082COMPOSITIONS AND METHODS FOR THE SELECTIVE REMOVAL OF SILICON NITRIDE - Compositions useful for the selective removal of silicon nitride materials relative to poly-silicon, silicon oxide materials and/or silicide materials from a microelectronic device having same thereon. The removal compositions include fluorosilicic acid, silicic acid, and at least one organic solvent. Typical process temperatures are less than about 100° C. and typical selectivity for nitride versus oxide etch is about 200:1 to about 2000:1. Under typical process conditions, nickel-based silicides as well as titanium and tantalum nitrides are largely unaffected, and polysilicon etch rates are less than about 1 Å min07-15-2010
20100155365STAMPER MANUFACTURING METHOD - According to one embodiment, when forming first, second, and third stampers by transferring three-dimensional patterns of a master, a height adjusting layer having a film thickness greater on the upper surface of a projection than on the bottom surface of a recess is formed between the second stamper and a second release layer, and the surface of the third stamper is etched with an acidic solution having a pH of less than 3.06-24-2010
20090039053METHOD FOR MANUFACTURING ELECTRICAL TRACES OF PRINTED CIRCUIT BOARDS - An exemplary method for manufacturing a printed circuit board is provided. Firstly, a copper clad substrate comprising a base film, a copper layer and intermediate layer interposed between the base film and the copper layer is provided. The intermediate layer is comprised of nickel, chromium, or alloy of nickel and chromium. A patterned photoresist layer is formed on the copper layer with portions of the copper layer are exposed from the photoresist pattern layer. Exposed portions of the copper layer are removed using a copper etchant to form a number of electrical traces, thereby exposing portions of the intermediate layer from the patterned photoresist layer. Exposed portions of the intermediate layer are removed using a chromium-nickel etchant. The method can prevent a bottom of each of electrical traces from enlarging, thereby improving quality of printed circuit board.02-12-2009
20100193465SEPARATING METHOD FOR CONDUCTIVE CERAMICS SINTERED BODY - There are provided an aqueous solution for separation of a conductive ceramics sintered body in which a conductive ceramic sintered body separated form a glass can be collected in a recyclable condition, and a separating method therefor, and an aqueous solution for separation with which a dark ceramics sintered body, a conductive ceramics sintered body and a glass are separately collected from a glass with a dark ceramics sintered body in which a conductive ceramics sintered body is formed on the dark ceramics sintered body, and a separating method therefor. A treatment liquid having an etching ability for at least one of a glass and a conductive ceramic sintered body is prepared as an aqueous solution 08-05-2010
20100193467METHOD FOR THE TREATMENT AND REUSE OF A STRIPPER SOLUTION - In the method, the spent stripper solution for tin or a tin mixture is treated to precipitate dissolved or suspended metal compounds. On the one hand chemicals for reuse, and on the other hand metals such as copper, tin, lead and/or iron are recovered from the waste water streams. Efficiency of the precipitation is improved by heating of the stripping solution at elevated temperatures, and by the addition of a precipitating reagent. Once the precipitate is removed, the remaining liquid may be reused, typically as an admixture with a fresh solution. In the production method of a regenerated stripping solution for tin comprising at least one inorganic acid, ferric ions, at least one organic acid, and at least one organic additive, the stripping solution is heated at elevated temperatures, precipitating reagent is added, precipitated matter is separated and removed, and one or some of the acids or additives mentioned are added for the recovery of the desired tin stripping capacity.08-05-2010
20100224586PROCESS FOR MULTIPLE PLATINGS AND FINE ETCH ACCURACY ON THE SAME PRINTED WIRING BOARD - A process for manufacturing a printed wiring board includes specifying overlapping etches for a first portion of the printed wiring board and a second portion of the printed wiring board, the first portion of the printed wiring board having disposed thereon a printed circuit having at least one dimension critical to printed wiring board operation, etching a first conductor in the first portion of the printed wiring board when a first conductor thickness is a predetermined thickness, completing all plating steps, and etching a second conductor in the second portion of the printed wiring board.09-09-2010
20100224587PLASMA ETCHING METHOD, PLASMA ETCHING APPARATUS AND COMPUTER-READABLE STORAGE MEDIUM - Provided are a plasma etching method, a plasma etching apparatus and a computer-readable storage medium capable of plasma-etching a silicon-containing antireflection coating film (Si-ARC) with a high etching rate and a high selectivity while suppressing damage (roughness) of an ArF photoresist. In the plasma etching method, a Si-containing antireflection film 09-09-2010
20120187076POLYMER LAYER REMOVAL ON PZT ARRAYS USING A PLASMA ETCH - A method for forming an ink jet print head can include attaching a plurality of piezoelectric elements to a diaphragm, dispensing a dielectric fill layer over the diaphragm and the plurality of piezoelectric elements to encapsulate the piezoelectric elements, curing the dielectric fill layer to form an interstitial layer, then removing the interstitial layer from an upper surface of the plurality of piezoelectric elements using a plasma etch.07-26-2012
20100237037Ceramic substrate metalization process - A ceramic substrate metallization process for making a ceramic circuit substrate practically in an economic way by means of: washing a non-charged ceramic substrate and roughening the surface of the ceramic substrate by etching, and then coating a negatively charged (or positively charged), silicon-contained, nanoscaled surface active agent on the ceramic substrate, and then coating a positively charged (or negatively charged) first metal layer on the ceramic substrate.09-23-2010
20100237038Thin Film Antenna and the Method of Forming the Same - The present invention discloses a thin film multi-band antenna, which is formed by PVD-Roll to Roll process and is formed of metal-oxide, conductive polymer, conductive glue or CNT. In another aspect, the present invention discloses a manufacturing method of thin film antenna, comprising preparing gel, followed by coating the gel on a substrate to form a transparent thin film. Thermal process is performed to heat the thin film. The gel includes vinyl oxide and metal compounds, wherein the vinyl oxide includes PEO having In(NO)3.3H2O, In(Ac)3, SnCl2.2H2O, or Sn(C2O4) contained thereof.09-23-2010
20100219155EQUIPMENT AND METHODS FOR ETCHING OF MEMS - Etching equipment and methods are disclosed herein for more efficient etching of sacrificial material from between permanent MEMS structures. An etching head includes an elongate etchant inlet structure, which may be slot-shaped or an elongate distribution of inlet holes. A substrate is supported in proximity to the etching head in a manner that defines a flow path substantially parallel to the substrate face, and permits relative motion for the etching head to scan across the substrate.09-02-2010
20100252526Method for Manufacturing a Device on a Substrate - A method for manufacturing a device on a substrate includes forming a layer structure on the substrate, forming an auxiliary layer on the layer structure, forming a planarization layer on the auxiliary layer and on the substrate, exposing the auxiliary layer by a chemical mechanical polishing process and removing at least partly the auxiliary layer to form a planar surface of the remaining auxiliary layer or of the layer structure and the planarization layer. The chemical mechanical polishing process has a first removal rate with respect to the planarization layer and a second removal rate with respect to the auxiliary layer and the first removal rate is greater than the second removal rate.10-07-2010
20100252527METHOD FOR PRODUCING A THIN FILM LAMINATED CAPACITOR - A method for producing a thin film laminated capacitor that makes it possible to reduce the number of operations for etching its electrode layers and its dielectric layers. On a substrate, a capacitor part is formed wherein n electrode layers and (n−1) dielectric layers are alternately laminated onto each other, wherein n is 4 or more. The capacitor part is etched from the same side k times. In any i10-07-2010
20080302759End functionalization of carbon nanotubes - Carbon nanotubes may be selectively opened and their exposed ends functionalized. Opposite ends of carbon nanotubes may be functionalized in different fashions to facilitate self-assembly and other applications.12-11-2008
20100000964METHOD AND SYSTEM FOR ETCHING A MEM DEVICE - A method and system for etching a substrate is described and, in particular, a method for etching large, high aspect ratio features, such as those in micro-electromechanical devices (MEMs), is also described. The method comprises disposing a substrate in a processing system, forming plasma having a substantial population of negatively-charged ions, and etching one or more features in the substrate using the negative ion population.01-07-2010
20090261060Production Method of Suspension Board with Circuit - A production method of a suspension board with circuit includes the steps of forming, on a metal supporting board, an insulating layer formed with a first opening, forming a metal thin film on the insulating layer and on the metal supporting board exposed from the first opening, forming, on a surface of the metal thin film, a conductive layer having terminal portions forming, on the terminal portions, a metal plating layer by electrolytic plating using the metal supporting board as a lead, forming a second opening in a portion of the metal supporting board opposing the first opening, and partially etching the metal supporting board to form the suspension board with circuit and a support frame. In the step of forming the insulating layer, the first opening is formed in the insulating layer in which the supporting frame is formed.10-22-2009
20080283489Method of Manufacturing a Structure - A gold layer (11-20-2008
20090071931INTERCONNECT SUPPORTED FUEL CELL ASSEMBLY, PREFORM AND METHOD OF FABRICATION - A fuel cell assembly includes at least one fuel cell including at least two electrodes and an electrolyte. An interconnect structure includes at least one flow channel initially defined by a removable sacrificial material. A method of forming the fuel cell assembly includes the steps of providing the interconnect structure having at least one flow channel, depositing the sacrificial material into the flow channel, depositing an electrode or an electrode/electrolyte material upon the interconnect structure and the sacrificial material, and processing the fuel cell so as to remove the sacrificial material.03-19-2009
20100301004FABRICATION OF METALLIC STAMPS FOR REPLICATION TECHNOLOGY - The electrodeposited Nickel stamp is replicated from a conductive master, e.g. Titanium metallic master instead of a photoresist patterned master. The conductive layer is served as a working electrode in the subsequent electrodepositing of the Nickel metal. After the electroplating, Nickel stamps are obtained by peeling the Nickel metal sheet off the conductive layer of the metallic master. Low adhesion between metallic master and Nickel stamp make it possible to delaminate the Nickel stamp without any defects.12-02-2010
20110127233METHOD OF MAKING BONDABLE PRINTED WIRING MEMBER - A method for making a printed wiring member including wire-bondable contact pads and wear-resistant connector pads, the method includes the steps of a) providing a blank printed wiring member comprising a copper foil laminated to a dielectric substrate; b) masking the blank printed wiring member to protect regions of the copper foil; c) removing copper in unprotected regions of the blank printed wiring member to form a patterned printed wiring member including contact pads and connector pads; d) depositing a nickel coating on the patterned printed wiring member using an electroless nickel deposition process; e) depositing a gold layer on the nickel coating using an electroless gold deposition process; and f) depositing palladium on the gold layer using an electroless palladium deposition process to improve wear resistance of the connector pads while preserving bondability of the contact pads.06-02-2011
20110240592TEXTURE PROCESSING LIQUID FOR TRANSPARENT CONDUCTIVE FILM MAINLY COMPOSED OF ZINC OXIDE AND METHOD FOR PRODUCING TRANSPARENT CONDUCTIVE FILM HAVING RECESSES AND PROJECTIONS - A texture processing liquid for a transparent conductive film for realizing a high photoelectric conversion efficiency in a thin solar cell and a method for producing a transparent conductive film are provided.10-06-2011
20110000875Methods Of Forming Capacitors - A method of forming a capacitor includes depositing a dielectric metal oxide layer of a first phase to a thickness no greater than 75 Angstroms over an inner conductive capacitor electrode material. The first phase dielectric metal oxide layer has a k of at least 15. Conductive RuO01-06-2011
20110108519WET ETCHED INSULATOR AND ELECTRONIC CIRCUIT COMPONENT - The present invention relates to an insulator as an insulating layer in a laminate which can inhibit dusting at the time of use, more particularly an electronic circuit component to which the insulator has been applied, particularly a wireless suspension. The insulator comprises a laminate of one or more insulation unit layers etchable by a wet process, the insulator having been subjected to plasma treatment after wet etching. The insulator exists mainly as an insulating layer in a laminate having a layer construction of first inorganic material layer-insulating layer-second inorganic material layer or a layer construction of inorganic material layer-insulating layer, and at least a part of the inorganic material layer has been removed to expose the insulating layer.05-12-2011
20110000876STRIPPER SOLUTION AND METHOD OF MANUFACTURING LIQUID CRYSTAL DISPLAY USING THE SAME - A method for manufacturing a liquid crystal display includes simultaneously forming a gate electrode and a gate bus line on a transparent dielectric substrate, simultaneously forming a channel layer, an ohmic contact layer, and source/drain electrodes by forming a gate insulation film, an amorphous silicon film, a doped amorphous silicon film, and a metal film on the transparent dielectric substrate on which the gate electrode and the gate bus line are formed and etching the metal film, the amorphous silicon film, and the doped amorphous silicon film, and forming a pixel electrode by forming a protective film and a transparent metal film on the transparent dielectric substrate upon which the source/drain electrodes are formed and finely etching the transparent metal film through a lift-off process using a stripper solution.01-06-2011
20110000878 INK JET-PRINTABLE COMPOSITION AND A MASKING PROCESS - A radiation-curable, ink jet-printable composition comprising a compound having a reactive silyl group that is suitable for use as a masking composition and/or processes in which the composition is applied onto a substrate; the printed composition is exposed to radiation to form a cured image that masks selected areas of the substrate; the unmasked areas of the substrate are modified; and the cured image is treated with an alkaline solution in order to release the cured image from the substrate.01-06-2011
20110024386ETCHING METHOD AND SUBSTRATE HAVING CONDUCTIVE POLYMER - An object of the present invention is to provide an etching method that enables control of etching of a conductive polymer using a specific cerium (IV) compound to be carried out simply and easily, thus ensuring that etching is carried out stably, and to provide a substrate having a conductive polymer that has been etched by the etching method.02-03-2011
20110042347METHOD AND APPARATUS FOR PLASMA SURFACE TREATMENT OF A MOVING SUBSTRATE - Method and plasma treatment apparatus for treatment of a substrate surface (02-24-2011
20110042346COLOR FILTER SUBSTRATE AND FABRICATING METHOD THEREOF - A color filter substrate includes a substrate, a black matrix that defines cell areas on a substrate and prevents light leakage, a color filter formed in the cell areas defined by the black matrix, and a conductive thin film formed on the rear surface of the substrate for preventing the generation of static electricity, wherein the conductive thin film is formed of a photo-resist containing a conductive material.02-24-2011
20110042348IMPRINT METHOD, IMPRINT APPARATUS, AND PROCESS FOR PRODUCING CHIP - An imprint method for imprinting an imprint pattern of a mold onto a pattern formation material on a substrate so as to realize a high throughput includes the steps of bringing the imprint pattern and the pattern formation material into contact with each other; applying a first pressure between the mold and the substrate to increase a contact area between the imprint pattern and the pattern formation material; and adjusting a positional relationship between the mold and the substrate at a second pressure lower than the first pressure.02-24-2011
20090301996FORMULATIONS FOR REMOVING COOPER-CONTAINING POST-ETCH RESIDUE FROM MICROELECTRONIC DEVICES - A method and composition for removing copper-containing post-etch and/or post-ash residue from patterned microelectronic devices is described. The removal composition includes a diluent, a solvent and a copper corrosion inhibitor, wherein the diluent may be a dense fluid or a liquid solvent. The removal compositions effectively remove the copper-containing post-etch residue from the microelectronic device without damaging exposed low-k dielectric and metal interconnect materials.12-10-2009
20090218312METHOD AND SYSTEM FOR XENON FLUORIDE ETCHING WITH ENHANCED EFFICIENCY - Provided herein is an apparatus and a method useful for manufacturing MEMS devices. An aspect of the disclosed apparatus provides a substrate comprising an etchable material exposed to a solid-state etchant, wherein the substrate and the solid-state etchant are disposed in an etching chamber. In some embodiments, the solid state etchant is moved into close proximity to the substrate. In other embodiments, a configurable partition is between the substrate and the solid-state etchant is opened. The solid-state etchant forms a gas-phase etchant suitable for etching the etchable material. In some preferred embodiments, the solid-state etchant is solid xenon difluoride. The apparatus and method are advantageously used in performing a release etch in the fabrication of optical modulators.09-03-2009
20100032407METHOD OF MANUFACTURING CERAMIC PROBE CARD - Provided is a method of manufacturing a ceramic probe card. A ceramic laminated body having a plurality of ceramic green sheets and an interlayer circuit including a conductive via and a conductive line formed in the plurality of ceramic green sheets is prepared. Then, at least one probe pin structure connected to the interlayer circuit is formed by selectively removing the plurality of photosensitive ceramic sheets having a ceramic powder and a photosensitive organic component on the ceramic laminated body necessarily, and by filling a metal material in a region from which the plurality of photosensitive ceramic sheets have been removed. Then, a ceramic substrate having the at least one probe pin structure is provided by simultaneously firing the ceramic laminated body and the photosensitive ceramic sheets, and by removing the photosensitive ceramic sheets.02-11-2010
20100065530COMPOSITION AND PROCESS FOR THE SELECTIVE REMOVE OF TiSiN - An aqueous removal composition and process for removing heater material, including TiSiN, from a microelectronic device having said material thereon. The aqueous removal composition includes at least one fluoride source, at least one passivating agent, and at least one oxidizing agent. The composition selectively removes TiSiN relative to oxides and nitrides that are adjacently present.03-18-2010
20110174770METHOD FOR MODIFYING AN ETCH RATE OF A MATERIAL LAYER USING ENERGETIC CHARGED PARTICLES - A method of etching a material layer on a substrate is described. In one embodiment, the method includes modifying an etch resistance of a material layer to a pre-determined etch process by doping the material layer using energetic charged particles, and etching the modified material layer using the pre-determined etch process.07-21-2011
20110079578Nickel-Chromium Alloy Stripper for Flexible Wiring Boards - A nickel-chromium alloy etching composition comprising sulfuric acid, a source of chloride ions, including hydrochloric acid or sodium, potassium or ammonium chloride, and a sulfur compound comprising a sulfur atom with an oxidation state between −2 to +5, such as thiosulfate, sulfide, sulfite, bisulfite, metabisulfite and phosphorus pentasulfide that can efficiently remove nickel-chromium alloy in the presence of copper circuits is disclosed.04-07-2011
20110100951METHOD AND APPARATUS FOR TRANSFERRING CARBONACEOUS MATERIAL LAYER - In a method and apparatus for transferring carbonaceous material layer, a carbonaceous material layer is grown on a growth substrate, and a first continuous conveying unit is used to feed the growth substrate and a transfer material, so that a gluing layer of the transfer material is attached to the carbonaceous material layer on the growth substrate. Then, a transformation device changes a viscosity of the gluing layer for the latter to adhere to the carbonaceous material layer. A second continuous conveying unit is further used to transfer and then separate the mutually adhered transfer material and growth substrate from each other, so that some part of the carbonaceous material layer is transferred onto the gluing layer while other part of the carbonaceous material layer remains on the growth substrate. Thus, at least a one-layer-thickness of the carbonaceous material layer is transferred.05-05-2011
20120118851METHOD FOR FORMING A TOUCH SENSING PATTERN AND SIGNAL WIRES - A method for forming a touch sensing pattern and signal wires, comprises the steps of: installing a first and a second conductive plating films on a surface of a highly transparency substrate; projecting a high energy light beam to the conductive plating films; and the high energy light beam moving with respect to the substrate along a predetermined track; a plurality of insulating trenches being formed in the first and second conductive plating films so as to form predetermined patterns for a sensing area and a wire area; a yellow light process being performed on the substrate; a layer of light resistor thin film being formed on a surfaces of the wire area; and etching the first conductive plating film in the sensing area; by above steps, the predetermined pattern in the sensing area being formed in the second conductive plating film.05-17-2012
20110017702METHOD OF MANUFACTURE OF AN ELECTRODE FOR A FUEL CELL - A method of manufacture of an electrode for a fuel cell, the method comprising at least the steps of: (a) providing an electrode substrate; (b) contacting at least a part of the electrode substrate with an electroless plating solution comprising a reducing agent, a metal precursor and a suspension of particulate material; and (c) electrolessly plating the metal from the metal precursor onto the contacted part of the electrode substrate, thereby co-depositing the particulate material on the contacted part of the electrode substrate to provide the electrode.01-27-2011
20090289029MOLD HAVING NANOMETRIC FEATURES, METHOD FOR REALIZING SUCH A MOLD AND CORRESPONDING USE OF IT IN A METHOD FOR REALIZING AN ARRAY OF CARBON NANOTUBES - A mold is for obtaining, on a substrate, an array of carbon nanotubes with a high control of their positioning. The mold includes a first layer of a first preset material having a surface having in relief at least one first plurality of projections having a free end portion with a substantially pointed profile.11-26-2009
20110147338Release Accumulative Charges on Wafers Using O2 Neutralization - A method of forming an integrated circuit structure on a wafer includes providing an etcher having an electrostatic chuck (ESC); and placing the wafer on the ESC. The wafer includes a conductive feature and a dielectric layer over the conductive feature. The method further includes forming and patterning a photo resist over the wafer; and etching the dielectric layer to form a via opening in the wafer using the etcher. An ashing is performed to the photo resist to remove the photo resist. An oxygen neutralization is performed to the wafer. A de-chuck step is performed to release the wafer from the ESC.06-23-2011
20090001045METHODS OF PATTERNING SELF-ASSEMBLY NANO-STRUCTURE AND FORMING POROUS DIELECTRIC - Methods of patterning a self-assembly nano-structure and forming a porous dielectric are disclosed. In one aspect, the method includes providing a hardmask over an underlying layer; predefining an area with a photoresist on the hardmask that is to be protected during the patterning; forming a layer of the copolymer over the hardmask and the photoresist; forming the self-assembly nano-structure from the copolymer; and etching to pattern the self-assembly nano-structure.01-01-2009
20090001046SUBSTRATE PROCESSING METHOD, SUBSTRATE PROCESSING APPARATUS AND RECORDING MEDIUM - The present invention provides a method, an apparatus and the like that may be adopted when executing a specific type of processing on a substrate that includes a recessed portion formed by etching a low dielectric constant insulating film with a low dielectric constant having been formed upon a metal layer. More specifically, a hydrogen radical processing phase in which the surface of the metal layer exposed at the bottom of the recessed portion is cleaned and the low dielectric constant insulating film is dehydrated by supplying hydrogen radicals while heating the substrate to a predetermined temperature and a hydrophobicity processing phase in which the low dielectric constant insulating film exposed at a side surface of the recessed portion is rendered hydrophobic by supplying a specific type of processing gas to the substrate are executed in succession without exposing the substrate to air.01-01-2009
20110155689MORPHOLOGY DESIGN OF TRANSPARENT CONDUCTIVE METAL OXIDE FILMS - An etching paste suitable for etching films comprising an etchant and a component is provided. The etching process comprises applying the etching paste of the present invention to the transparent conductive metal oxide film by a paste application method so that the film is etched. Through the combination of the etching paste and the paste application method, the transparent conductive metal oxide film having stable scattering properties is obtained and can be used in the manufacture of a-Si solar cells.06-30-2011
20110253668ETCH PATTERNING OF NANOSTRUCTURE TRANSPARENT CONDUCTORS - A patterned transparent conductor including a conductive layer coated on a substrate is described. More specifically, the transparent conductor can be patterned by screen-printing an acidic etchant formulation on the conductive layer. A screen-printable etchant formulation is also disclosed.10-20-2011
20080251495Methods of preparing printed circuit boards and packaging substrates of integrated circuit - A method of forming printed circuit boards and packaging substrates for integrated circuits based on filling-vias plating and a semi-additive process, comprising the following steps: (1) providing a dielectric layer on a substrate; (2) providing blind vias on said dielectric layer; (3) providing a first seed layer after providing blind vias; (4) providing solid conductive vias by a filling-vias plating process after providing a first seed layer, and also providing a copper layer covering the first seed layer during the filling-vias plating process; (5) removing said first seed layer as well as the copper layer formed thereon, and retaining solid copper pillars in the conductive vias; (6) providing a second seed layer which is used to form wires by a semi-additive process; (7) providing a photo-sensitive thin film, and providing a plating resistant layer by image-transfer to expose a wire pattern; (8) thickening wires; (9) removing the photo-sensitive thin film; (10) removing the exposed second seed layer and retaining the thickened wires, thus form a desired conductive pattern; (11) repeating steps (1)-(10) to form an upper layer of wires, thereby completing the fabrication of the fine wires in the subsequent layers of wires and effecting inter-layer interconnections of the solid conductive vias.10-16-2008
20110163063METHOD FOR MANUFACTURING CRYSTAL OSCILLATOR - The invention is directed to the provision of a method for manufacturing a crystal oscillator manufacturing method that can achieve a highly precise fine adjustment without applying unnecessary external force to a crystal oscillator, and that can adjust a plurality of crystal oscillators in a collective manner. More specifically, the invention provides a method for manufacturing a crystal oscillator includes a first etching step for forming a prescribed external shape, an electrode forming step for forming an electrode at least in a portion of a surface of the external shape, a leakage amount measuring step for measuring leakage amount associated with leakage vibration of the external shape, and a second etching step for etching the external shape by an amount that is determined based on a measurement result of the leakage amount measuring step so as to adjust balance.07-07-2011
20110163062SELF-ALIGNED BARRIER AND CAPPING LAYERS FOR INTERCONNECTS - An interconnect structure for integrated circuits for copper wires in integrated circuits and methods for making the same are provided. Mn, Cr, or V containing layer forms a barrier against copper diffusing out of the wires, thereby protecting the insulator from premature breakdown, and protecting transistors from degradation by copper. The Mn, Cr, or V containing layer also promotes strong adhesion between copper and insulators, thus preserving the mechanical integrity of the devices during manufacture and use, as well as protecting against failure by electromigration of the copper during use of the devices and protecting the copper from corrosion by oxygen or water from its surroundings. In forming such integrated circuits, certain embodiments of the invention provide methods to selectively deposit Mn, Cr, V, or Co on the copper surfaces while reducing or even preventing deposition of Mn, Cr, V, or Co on insulator surfaces. Catalytic deposition of copper using a Mn, Cr, or V containing precursor and an iodine or bromine containing precursor is also provided.07-07-2011
20090301995Method for Making a Plate-Like Detachable Structure, in Particular Made of Silicon, and Use of Said Method - Process for fabricating a structure in the form of a wafer, including at least a substrate, a superstrate and at least one intermediate layer interposed between the substrate and the superstrate, the process including: forming, on a substrate, at least one intermediate layer including at least one base material in which extrinsic atoms or molecules are distributed, these differing from the atoms or molecules of the base material, so as to constitute a substructure; applying a base heat treatment to this substructure such that, in the temperature range of this heat treatment, the presence of the chosen extrinsic atoms or molecules in the chosen base material causes a structural transformation of said intermediate layer; and joining a superstrate to said heat-treated intermediate layer so as to obtain said structure in the form of a wafer.12-10-2009
20100282709SUBSTRATE PLASMA-PROCESSING APPARATUS - A substrate plasma-processing apparatus for plasma-processing a surface of an electrode of an organic light emitting device. The substrate plasma-processing apparatus may adjust the distance between a first electrode and a substrate and adjust the distance between a second electrode and the substrate.11-11-2010
20110132866Method for Producing a Bulk Wave Acoustic Resonator of FBAR Type - A method for fabricating a bulk wave acoustic resonator (FBAR) which includes at least locally a partially suspended thin layer of piezoelectric material, and includes the following steps: the formation of at least one first so-called lower electrode on the surface of a thin layer of piezoelectric material; the deposition of a so-called sacrificial layer on the surface of the said thin layer of piezoelectric material and of the said first electrode defining a first set; the assembling of the said first set with a second substrate; the formation of at least one second electrode termed the upper electrode on the opposite face of the said thin layer of piezoelectric material from the face comprising the said first electrode; and the elimination of the sacrificial layer so as to unveil the said thin layer of piezoelectric material and the said first electrode and define the bulk wave resonator.06-09-2011
20110073561METHOD FOR MANUFACTURING ELECTRODE FOR POWER STORAGE DEVICE AND METHOD FOR MANUFACTURING POWER STORAGE DEVICE - One of objects is to reduce the effect caused by the volume expansion of an active material. An embodiment is a method for manufacturing an electrode for a power storage device which includes an active material over one of surfaces of a current collector. The active material is formed by forming a conductive body functioning as the current collector; forming a mixed layer including an amorphous region and a microcrystalline region over one of surfaces of the conductive body; and etching the mixed layer selectively, so that a part of or the whole of the amorphous region is removed and the microcrystalline region is exposed. Thus, the effect caused by the volume expansion of the active material is reduced.03-31-2011
20100181283DUAL METAL FOR A BACKSIDE PACKAGE OF BACKSIDE ILLUMINATED IMAGE SENSOR - A method for fabricating a semiconductor device with improved bonding ability is disclosed. The method comprises providing a substrate having a front surface and a back surface; forming one or more sensor elements on the front surface of the substrate; forming one or more metallization layers over the front surface of the substrate, wherein forming a first metallization layer comprises forming a first conductive layer over the front surface of the substrate; removing the first conductive layer from a first region of the substrate; forming a second conductive layer over the front surface of the substrate; and removing portions of the second conductive layer from the first region and a second region of the substrate, wherein the first metallization layer in the first region comprises the second conductive layer and the first metallization layer in the second region comprises the first conductive layer and the second conductive layer.07-22-2010
20100193466METHOD OF MANUFACTURING CIRCUIT BOARD - A method of manufacturing a circuit board is provided. Firstly, a substrate is provided, and a first conductive layer is disposed on the substrate. Next, a barrier layer is formed on the first conductive layer. Thereafter, a through hole passing through the substrate, the first conductive layer, and the barrier layer is formed. A second conductive layer including a conductive rod disposed in the through hole is formed on an inside wall of the through hole and the barrier layer. After that, parts of the second conductive layer located outside the through hole are removed. Next, the barrier layer is removed, and a circuit layer is formed on the first conductive layer and the conductive rod. Parts of the first conductive layer exposed by the circuit layer are then removed.08-05-2010
20110259848Rolled Copper Foil or Electrolytic Copper Foil for Electronic Circuit, and Method of Forming Electronic Circuit Using Same - Provided is a rolled copper foil or electrolytic copper foil for an electronic circuit to be used for forming a circuit by etching, wherein the rolled copper foil or the electrolytic copper foil comprises a nickel alloy layer with lower etching rate than copper, which is formed on an etching side of the copper foil, and the nickel alloy layer contains zinc. This invention aims to prevent sagging caused by the etching, to form a uniform circuit having the intended circuit width, and to shorten the time of forming a circuit by etching as much as possible, when forming a circuit by etching a copper foil of the copper-clad laminate; and also aims to make the thickness of the nickel alloy layer as thin as possible, to inhibit oxidation when exposed to heat, to prevent tarnish (discoloration) known as “YAKE”, to improve the etching properties in pattern etching, and to prevent the occurrence of short circuits and defects in the circuit width.10-27-2011
20110186542SLURRY CONTAINING MULTI-OXIDIZER AND MIXED NANO-ABRASIVES FOR TUNGSTEN CMP - A chemical mechanical polishing slurry containing multiple oxidizers and nano abrasive particles (including engineered nano diamond particles) suitable for polishing multilayer substrate with tungsten and Ti/TiN barrier layers. The slurry contains no metallic catalyst and has low total abrasive particle content. The absence of metal ions can be advantageous for certain applications as certain metal ions may present contamination issues. A low total abrasive content may also lower the total defect counts, reduce the slurry waste treatment burden, and simplify the post CMP clean process.08-04-2011
20110147339METHOD FOR MANUFACTURING WIRING STRUCTURE OF WIRING BOARD - A method for manufacturing a wiring structure of a wiring board is provided. In the method, a substrate including an insulation layer and a film disposed on the insulation layer is provided. Next, a barrier layer completely covering the film is formed. Next, an intaglio pattern partially exposing the insulation layer is formed on an outer surface of the barrier layer. Next, an activated layer is formed on the outer surface and in the intaglio pattern. Then, the activated layer on the outer surface is removed, and the activated layer in the intaglio pattern is remained. After the activated layer on the outer surface is removed, a conductive material is formed in the intaglio pattern by using a chemical deposition method. After forming the conductive material, the barrier layer and the film are removed.06-23-2011
20100018944PATTERNING METHOD - A patterning method is provided. A patterned photoresist layer is formed on a bottom anti-reflective coating (BARC), having therein an opening exposing a portion of the BARC. The patterned photoresist layer is treated with a first plasma-generating gas including a fluorocarbon species to form a polymer layer on the surface of the PR layer and the sidewall of the opening. The patterned photoresist layer is used as a mask to etch the BARC with a second plasma-generating gas, which includes Ar and H01-28-2010
20090032492APPARATUS AND METHOD FOR WET-CHEMICAL PROCESSING OF FLAT, THIN SUBSTRATES IN A CONTINUOUS METHOD - The invention relates to a method and apparatus for wet-chemical processes (cleaning, etching, stripping, coating, dehydration) in a continuous method for flat, thin and fracture-sensitive substrates, the substrate transport and the wet process being effected by media-absorbing rollers.02-05-2009
20100181284METHOD OF OBTAINING ELECTRONIC CIRCUITRY FEATURES - The present disclosure relates to a method of obtaining fine circuitry features by positioning a circuit board precursor, the circuit board precursor having a cover layer and an insulating substrate, in proximity to a source of laser radiation. Selectively laser ablating through the cover layer and into the underlying insulating substrate and then treating with water, dilute alkali solution or dilute acid solution to remove the cover layer to reveal one or more circuitry features on the insulating substrate that are smaller than if a cover layer is not used.07-22-2010
20100089866Method for producing tapered metallic nanowire tips on atomic force microscope cantilevers - A method of making nanowire probes is provided. The method includes providing a template having a nanoporous structure, providing a probe tip that is disposed on top of the template, and growing nanowires on the probe tip, where the nanowires are grown from the probe tip along the nanopores, and the nanowires conform to the shape of the nanopores.04-15-2010
20120305522MEMORY DEVICES AND METHOD OF MANUFACTURING THE SAME - Memory devices and methods of forming memory devices including forming a plurality of preliminary electrodes, each of the plurality of preliminary electrodes including a protruding region, protruding from a first mold insulating layer, forming a second mold insulating layer on the first mold insulating layer, removing at least a portion of the plurality of preliminary electrodes to form a plurality of openings in the second mold insulating layer and a plurality of lower electrodes, and forming a plurality of memory elements in the plurality of openings. Memory devices and methods of forming memory devices including forming one or more insulating layers on sidewalls of all or part of a plurality of lower electrodes and/or a plurality of memory elements.12-06-2012
20090218311Layer-structured fuel cell catalysts and current collectors - A method of fabricating a layer-structured catalysts at the electrode/electrolyte interface of a fuel cell is provided. The method includes providing a substrate, depositing an electrolyte layer on the substrate, depositing a catalyst bonding layer to the electrolyte layer, depositing a catalyst layer to the catalyst bonding layer, and depositing a microstructure stabilizing layer to the catalyst layer, where the bonding layer improves adhesion of the catalyst onto the electrolyte. The catalyst and a current collector is a porous catalyst and a fully dense current collector, or a fully dense catalyst and a fully dense current collector structure layer. A nano-island catalyst and current collector structure layer is deposited over the catalyst and current collector or over the bonding layer, which is deposited over the electrolyte layer. The fuel cell can be hydrogen-fueled solid oxide, solid oxide with hydrocarbons, solid sensor, solid acid, polymer electrolyte or direct methanol.09-03-2009
20090071932ETCHING PROCESSES USED IN MEMS PRODUCTION - The efficiency of an etching process may be increased in various ways, and the cost of an etching process may be decreased. Unused etchant may be isolated and recirculated during the etching process. Etching byproducts may be collected and removed from the etching system during the etching process. Components of the etchant may be isolated and used to general additional etchant. Either or both of the etchant or the layers being etched may also be optimized for a particular etching process.03-19-2009
20110315654METHOD OF MANUFACTURING A BULK ACOUSTIC WAVE DEVICE - A method of manufacturing a Bulk Acoustic Wave device by providing an active layer formed of an electro-mechanical transducer material, providing a first electrode on the active layer, defining a first electrode portion of the device, whereby a remaining portion of the device is defined around the first electrode, providing a stop-layer on the first electrode, depositing a first dielectric layer on the resultant structure, and planarizing the first dielectric layer until the stop-layer on the first electrode is exposed.12-29-2011
20120006781Electrode material and applications thereof - A metal vanadium film is used as an extraction electrode contacting with a vanadium oxide or doped vanadium oxide film. The electrode material is adapted for a detector, sensor and optical switch based on a vanadium oxide or doped vanadium oxide film. The metal vanadium film is in favor of reducing the thermal conductivity of the support structure of the array unit. The preparation process of the vanadium film using the metal vanadium as the source material is more easily controlled than that of NiCr film using the NiCr alloy as the source material. The extraction electrode of the present invention easily obtains an excellent metal-semiconductor contact characteristic. The preparation process and patterning process of the metal vanadium film have an excellent technology compatibility with the IC and MEMS manufacturing processes.01-12-2012
20120061346Conductivity Measurement Device, Its Manufacture And Use - The invention relates to a method of manufacturing a device for measuring conductivity of a liquid, in particular ultrapure water, of the kind comprising two conductivity measurement electrodes suitable for defining a cell constant enabling the measurement of the conductivity of the ultrapure liquid, characterized in that it consists of producing each of the electrodes by forming an electrode pattern from electrically conductive material on a substrate of insulating material.03-15-2012
20120061345METHOD OF DRYING SUBSTRATE, AND METHOD OF MANUFACTURING IMAGE DISPLAY APPARATUS USING THE SAME - A method of drying a substrate comprises: supplying a first air flow 03-15-2012
20120055901SUBSTRATE FABRICATING APPARATUS AND SUBSTRATE FABRICATING METHOD - Disclosed herein are a substrate fabricating apparatus and a substrate fabricating method. The substrate fabricating apparatus includes: a first injector that injects a first etchant to a circuit layer formed as an outermost layer of a base substrate to form first type of ruggedness; and a second injector that injects a second etchant to the circuit layer formed with the first type of ruggedness to form second type of ruggedness. The present invention provides the substrate fabricating apparatus and the substrate fabricating method that inject different etchants to the circuit layer to form different ruggedness, thereby making it possible to widen the specific surface area of the circuit layer to improve adhesion between the circuit layer and the protective layer.03-08-2012
20120006782SUBSTRATE PROCESSING METHOD AND SUBSTRATE PROCESSING APPARATUS - A substrate processing method for removing a copper oxide film on a surface of Cu and a Cu-containing residue adhered to an interlayer insulating film in a Cu wiring structure on a substrate by using an organic acid-containing gas is provided. The substrate processing method includes removing the Cu-containing residue by etching by supplying the substrate with a processing gas containing an organic acid gas, after the temperature of the substrate is set to be maintained at a first temperature; and removing the copper oxide film on the surface of Cu by means of a reduction reaction by supplying the substrate with the processing gas containing the organic acid gas, after the temperature of the substrate is set to be maintained at a second temperature that is higher than the first temperature.01-12-2012
20110089137SUBSTRATE LIQUID PROCESSING APPARATUS, SUBSTRATE LIQUID PROCESSING METHOD, AND STORAGE MEDIUM HAVING SUBSTRATE LIQUID PROCESSING PROGRAM STORED THEREIN - Provided are a substrate liquid processing apparatus, a substrate liquid processing method, and a computer readable storage medium having a substrate liquid processing program stored therein that can prevent the occurrence of the electrostatic breakdown caused by the discharge of electric charges in a substrate. The substrate liquid processing apparatus processes a circuit-forming surface of the substrate with a chemical liquid. Furthermore, prior to processing the substrate with the chemical liquid, the substrate liquid processing apparatus performs an anti-static process for an surface opposite to the circuit-forming surface of the substrate by an anti-static liquid, thereby emitting the electric charges on the substrate.04-21-2011
20120152889METHOD FOR MANUFACTURING PIEZOELECTRIC ELEMENT - A method for manufacturing a piezoelectric element, in which a ferroelectric film is processed in an appropriate shape by plasma etching, is provided. A metal mask made of a metal thin film which is hard to be etched by oxygen gas is placed on an object to be processed formed by laminating a lower electrode layer and a ferroelectric film on a substrate in this order. An etching gas containing a mixture gas of the oxygen gas and a reactive gas including fluorine in a chemical structure is turned into plasma and is brought into contact with the metal mask and the object to be processed. An AC voltage is applied to an electrode disposed beneath the object to be processed so that ions in the plasma are caused to enter the object to be processed to perform anisotropic etching on the ferroelectric film.06-21-2012
20100230382METAL-CLAD LAMINATE - Metal-clad laminates in which a conductor layer having superior peel strength is formed on a smooth surface of an insulating layer can be obtained by a method comprising (A) a step of preparing a metal-clad laminate precursor by providing one or more sheets of prepreg between two sheets of film having a metal film layer on a support layer, and heating and pressing them under reduced pressure, (B) a step of removing the support layer, (C) a step of removing the metal film layer, and (D) a step of forming a metal film layer on the surface of an insulating layer by electroless plating.09-16-2010
20090230085COMPOSITION FOR SURFACE MODIFICATION OF A HEAT SINK AND METHOD FOR SURFACE TREATMENT OF THE HEAT SINK FOR PRINTED CIRCUIT BOARDS USING THE SAME - The present invention provides a composition for surface modification of a heat sink, the composition including: 0.01 to 10 parts by weight of an organic titanium compound; 0.01 to 5 parts by weight of an organic silane compound; 0.1 to 10 parts by weight of an organic acid; 0.01 to 5 parts by weight of a sequestering agent; and 0.1 to 10 parts by weight of a buffer with respect to 100 parts by weight of distilled water. The composition of the present invention provides excellent adhesion strength with prepreg, and improve heat releasing performance.09-17-2009
20110049088ETCHING COMPOSITION AND ETCHING PROCESS - An etching composition which comprises at least one organic carboxylic acid compound selected from acetic acid, propionic acid, butyric acid, succinic acid, citric acid, lactic acid, malic acid, tartaric acid, malonic acid, maleic acid, glutaric acid, aconitic acid, 1,2,3-propanetricarboxylic acid and ammonium salts of these acids, a polysulfonic acid compound and water, and an etching process which comprises etching a conductive film comprising zinc oxide as the main component using the etching composition described above.03-03-2011
20110049087FRAME FOR HOLDING LAMINATE DURING PROCESSING - A rigid holder is provided for supporting a flexible article. The rigid holder may include a first frame member and a second frame member which are held together through magnets.03-03-2011
20100096357THERMOELECTRIC MODULE AND MANUFACTURING METHOD FOR SAME - A thermoelectric module and method of manufacture thereof, capable of preventing short-circuits between electrodes due to solder without causing increases in size or cost. A thermoelectric module is configured with lower electrodes formed on the inside surface of a lower substrate, placed in opposition to an upper substrate, on the inside surface of which are formed upper electrodes; the end faces of thermoelectric elements are soldered to the lower electrodes and upper electrodes. Each of the electrodes is configured from three layers, which are a copper layer, a nickel layer formed on one face of the copper layer, and a gold layer formed on one face of the nickel layer; a visor portion, protruding outward, is formed in the nickel layer, so that when positioning the thermoelectric elements above the electrodes and soldering the electrodes to the thermoelectric elements, the flowing of solder 04-22-2010
20090134118Method of manufacturing printed circuit board - A method of manufacturing a printed circuit board is disclosed. The method may include: stacking a cover layer over a copper foil, for a copper clad laminate that includes the copper foil stacked over one side of an insulation layer; forming an intaglio groove by removing portions of the cover layer and the copper clad laminate; stacking a seed layer over a surface of the intaglio groove and the cover layer; removing a portion of the seed layer stacked over the cover layer, by removing a portion of the cover layer; forming a plating layer, by plating an inside of the intaglio groove; and removing the remaining cover layer and the copper foil.05-28-2009
20120160802 Method For Manufacturing A Wire Grid Polarizer - Provided is a method of manufacturing a wire grid polarizer in which a stable color coordinate can be implemented. According to the present invention, in a process where a second grid pattern of metal pattern is formed over a first grid pattern made of resin material, metal layer is deposited in a concave portion formed between adjacent first grid patterns to form void portion and a width and a height of the second grid pattern are adjusted depending on adjustment of a width of the voids, and thereby improving a process efficiency.06-28-2012
20120211462REMOTELY-EXCITED FLUORINE AND WATER VAPOR ETCH - A method of etching exposed silicon oxide on patterned heterogeneous structures is described and includes a remote plasma etch formed from a fluorine-containing precursor. Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents combine with water vapor. The chemical reaction resulting from the combination produces reactants which etch the patterned heterogeneous structures to produce, in embodiments, a thin residual structure exhibiting little deformation. The methods may be used to conformally trim silicon oxide while removing little or no silicon, polysilicon, silicon nitride, titanium or titanium nitride. In an exemplary embodiment, the etch processes described herein have been found to remove mold oxide around a thin cylindrical conducting structure without causing the cylindrical structure to significantly deform.08-23-2012
20120312775METHOD FOR MANUFACTURING A PRINTED CIRCUIT BOARD - A printed circuit board and a method for manufacturing the printed circuit board are disclosed. The method for manufacturing a printed circuit board can include forming a circuit pattern over a seed layer that is formed over an insulation layer, pressing the circuit pattern such that the circuit pattern and the seed layer corresponding with the circuit pattern are buried in the insulation layer, and removing the exposed seed layer. This method can prevent undercuts caused by etching in the seeds positioned between the circuit pattern and the insulation layer, and can thereby prevent the circuit pattern from becoming detached. Also, the adhesion between the circuit pattern and the insulation layer can be increased, making it possible to implement a finer circuit pattern over the insulation layer.12-13-2012
20120312773METHOD FOR MAKING PATTERNED CONDUCTIVE ELEMENT - The present disclosure relates to a method for making pattern conductive element. The method includes steps. A substrate having a surface is provide. An adhesive layer is formed on the surface of the substrate. Part of the adhesive layer is solidified to form a solidified adhesive layer and a non-solidified adhesive layer. A carbon nanotube layer is applied on the adhesive layer. The non-solidified adhesive layer is solidified so that the carbon nanotube layer on the non-solidified adhesive layer forms a fixed carbon nanotube layer and the carbon nanotube layer on the solidified adhesive layer forms a non-fixed carbon nanotube layer. The non-fixed carbon nanotube layer is removed and the fixed carbon nanotube layer is remained to form a pattern carbon nanotube layer.12-13-2012
20120312774Illuminating waveguide fabrication method - A method for fabricating waveguides comprising nano-apertures for illumination of sub-resolution exposures is presented. In particular, the end of a waveguide, such as an optical fiber, is coated with a material, such as an electrically conducting metal or a semiconductor. This material is then selectively removed through the process of ion milling, creating an aperture in the material at the end of the waveguide. Under normal conditions, if the aperture is smaller than the wavelength of light in the waveguide, there is little or no transmission through the aperture. However, with the appropriate selection of materials and aperture geometry, for example a metallic conducting coating and sub-wavelength “C-shaped” or “bow-tie” aperture, enhancement of transmission of light through the aperture can be achieved, allowing effective illumination of sub-resolution spots using the ion-milled aperture. This can be used in a nanolithography system incorporating waveguide illuminators as well.12-13-2012
20120211464METHOD OF MANUFACTURING PRINTED CIRCUIT BOARD HAVING METAL BUMP - A method of manufacturing a printed circuit board, including: providing a metal layer; forming an insulation layer on the metal layer and then forming via holes for exposing the metal layer in the insulation layer; forming vias charged in the via holes and a circuit layer on the insulation layer; and forming metal bumps at ends of the vias.08-23-2012
20120312772METHOD FOR MAKING TOUCH PANEL - The present disclosure relates to a method for making a plurality of touch panels one time. The method includes following steps. A substrate is provided. The substrate has a surface defining a number of target areas with each including two areas: a touch-view area and a trace area. An adhesive layer is formed on the surface of the substrate. A carbon nanotube film is formed on the adhesive layer. The adhesive layer is solidified. An electrode and a conductive trace are formed on each target area so that part of the carbon nanotube film is exposed from a space between adjacent conductive lines of the conductive trace to form an exposed carbon nanotube film on each trace area. The exposed carbon nanotube film on each trace area is removed to obtain a plurality of transparent conductive layers spaced from each other. A number of touch panels is obtained by cutting the substrate.12-13-2012
20100270262ETCHING LOW-K DIELECTRIC OR REMOVING RESIST WITH A FILTERED IONIZED GAS - A method of etching a low-k dielectric on, or removing resist from, a substrate. In the method, the substrate is placed in a process zone. An ionized gas is generated in a gas ionization zone above the process zone, by introducing a process gas into a gas ionization zone, maintaining the process gas at a pressure of less than about 0.1 mTorr, and coupling RF energy to the process gas to form an ionized gas. The ionized gas is passed through an ion filter to form a filtered ionized gas. The substrate is exposed to the filtered ionized gas to etch the low-k dielectric layer on the substrate or to remove or clean remnant resist on the substrate.10-28-2010
20090095706Selective patterning of Multilayer Systems for OPV in a roll to roll process - Methods of using etching pastes to form a pattern on an electrode of a solar cell, as well as related articles, systems, and components, are disclosed.04-16-2009
20090095704PATTERNING CNT EMITTERS - An industrial scale method for patterning nanoparticle emitters for use as cathodes in a display device is disclosed. The low temperature method can be practiced in high volume applications, with good uniformity of the resulting display device. The method steps involve deposition of CNT emitter material over an entire surface of a prefabricated composite structure, and subsequent removal of the CNT emitter material from unwanted portions of the surface using physical methods.04-16-2009
20100012620WET-PROCESSING APPARATUS AND METHOD OF FABRICATING DISPLAY PANEL - The wet-processing apparatus includes a wet-step bath in which a wet-step is carried out, and a vibration-type film separator for separating impurities out of a solution used in the wet-step. The wet-processing apparatus further includes a re-supply path through which the solution out of which the impurities were removed by means of the vibration-type film separator is re-supplied to the wet-step bath. Thus, it is possible to reuse a solution and a material of which a pattern is composed. Since the vibration-type film separator is used, it is possible to reduce a frequency of exchanging filters equipped in the vibration-type film separator, and ensure a high rate at which a material of which a pattern is composed is recovered, regardless of a specific gravity of the material.01-21-2010
20100012621METHOD OF TREATING COPPER SULPHIDE DEPOSITS IN AN ELECTRICAL APPARATUS BY THE USE OF OXIDISING AGENTS - A method of treating copper sulfide deposits on materials and surfaces that are in contact with electrically insulating oil inside an electrical apparatus. A substantial amount of the electrically insulating oil, normally present in the electrical apparatus, has been removed. The copper sulfide is subjected to treatment with an oxidizing agent which causes a reaction with the copper sulfide deposits. The oxidizing agent can include any compound from the list; chlordioxide, a peroxy acid or ozone.01-21-2010
20120312771METHOD FOR MAKING TOUCH PANEL - The present disclosure relates to a method for making touch panel. A substrate having a surface is provided. The substrate defines two areas: a touch-view area and a trace area. An adhesive layer is formed on the surface of the substrate. The adhesive layer on the trace area is solidified. A carbon nanotube layer is formed on the adhesive layer. The adhesive layer on the touch-view area is solidified. The carbon nanotube layer on the trace area is removed. At least one electrode and a conductive trace is formed.12-13-2012
20120255929ETCHING SOLUTION COMPOSITION FOR TRANSPARENT CONDUCTIVE FILM - The present invention provides an etching solution composition for etching crystalline transparent conductive films which enables etching of a crystalline ITO film without damaging copper and/or copper alloy used in electrode materials. Etching solution compositions for etching crystalline transparent conductive films described herein consist of an aqueous solution that comprises 1-10 wt % of a fluorine compound.10-11-2012
20090020500METHOD OF FORMING PASSAGE THROUGH SUBSTRATE FOR MEMS MODULE - A method of forming a passage through a substrate for a MEMS module is disclosed to include the steps of: a) etching a substrate having a thickness smaller than 0.30 mm to form a bottom recess; b) etching a top side of the substrate to form a top recess to define a part of the substrate as a sacrifice portion; c) forming a bottom layer in the bottom recess of the substrate by injection molding; d) depositing a support layer in the top recess of the substrate; and e) removing the sacrifice portion from the substrate by etching to form a passage defined between the support layer and the bottom layer in the substrate with two ends in communication with ambient atmosphere.01-22-2009
20110120969Process of manufacturing ceramic substrate - The present invention relates to a manufacturing process for the ceramics substrate, more particularly attaching a dry membrane to a surface of the metallic layer of the ceramics substrate, and removing the dry membrane from the circuit portion after exposure and development process to expose the metallic layer therein. Furthermore, the conductive metallic layer coated onto the surface of the metallic layer of the circuit, and the etching resistance layer is coated onto the surface of the conductive metallic layer, and further the dry membrane is removed and the conductive metallic layer and the metallic layer are etched. The etchant is blocked by the etching resistance layer to prevent etchant from directly contacting the surface of the conductive metallic layer. Thus, the predetermined width of the circuit will not be reduced and the precision of the circuit size can be upgraded.05-26-2011
20100326953APPARATUS FOR ETCHING SUBSTRATE AND METHOD OF FABRICATING THIN-GLASS SUBSTRATE - An apparatus for etching a substrate includes (a) a nozzle system including at least one nozzle through which acid solution containing at least hydrofluoric acid is sprayed onto the substrate, (b) a mover which moves at least one of the nozzle system and the substrate relative to the other in a predetermined direction in such a condition that the substrate and the nozzle system face each other, (c) a filter system which filters off particles out of the acid solution having been sprayed onto the substrate, and (d) a circulation system which circulates the acid solution having been sprayed onto the substrate, to the filter system, and further, to the nozzle system from the filter system.12-30-2010
20110006032SURFACE TREATMENT OF AN ORGANIC OR INORGANIC SUBSTRATE FOR ENHANCING STABILITY OF A LITHOGRAPHICALLY DEFINED DEPOSITED METAL LAYER - A method of metal deposition may include chemically modifying a surface of a substrate to make the surface hydrophobic. The method may further include depositing a layer of metal over the hydrophobic surface and masking at least a portion of the deposited metal layer to define a conductive metal structure. The method may also include using an etching agent to etch unmasked portions of the deposited metal layer.01-13-2011
20110226728DEVICE FOR GENERATING A PLASMA DISCHARGE FOR PATTERNING THE SURFACE OF A SUBSTRATE - Device for generating a plasma discharge for patterning the surface of a substrate, comprising a first electrode having a first discharge portion and a second electrode having a second discharge portion, a high voltage source for generating a high voltage difference between the first and the second electrode, and positioning means for positioning the first electrode with respect to the substrate, wherein the positioning means are arranged for selectively positioning the first electrode with respect to the second electrode in a first position in which a distance between the first discharge portion and the second discharge portion is sufficiently small to support the plasma discharge at the high voltage difference, and in a second position in which the distance between the first discharge portion and the second discharge portion is sufficiently large to prevent plasma discharge at the high voltage difference.09-22-2011
20110226727ETCHANT FOR METAL WIRING AND METHOD FOR MANUFACTURING METAL WIRING USING THE SAME - Exemplary embodiments of the present invention provide a metal wiring etchant. A metal wiring etchant according to an exemplary embodiment of the present invention includes ammonium persulfate, an organic acid, an ammonium salt, a fluorine-containing compound, a glycol-based compound, and an azole-based compound.09-22-2011
20110226726Dry etching apparatus and method for manufacturing touch screen panels using the same - A dry etching apparatus for performing dry etching in manufacture of a set of touch screen panels on a mother substrate, including a chamber, an upper electrode in the chamber at an upper portion thereof, the upper electrode configured to apply a high-frequency power source (RF) to the interior of the chamber, a lower electrode in the chamber at a lower portion thereof, the lower electrode configured to apply the high-frequency power source to the interior of the chamber, a gas injection port configured to inject a compound mixture gas into the chamber, an exhaust port configured to exhaust a reactive gas produced in the interior of the chamber, and a shadow mask disposed above a location on the lower electrode for the mother substrate for the touch screen panels, the shadow mask having a plurality of exposure windows respectively corresponding to a plurality of exposure portions to be formed.09-22-2011
20120318770MANUFACTURING METHOD OF CIRCUIT BOARD - A manufacturing method of a circuit board is provided. A circuit substrate having a first surface and at least a first circuit is provided. A dielectric layer having a second surface and covering the first surface and the first circuit is formed on the circuit substrate. The dielectric layer is irradiated by a laser beam to form a first intaglio pattern, a second intaglio pattern and at least a blind via. A first conductive layer is formed in the first intaglio pattern, the second intaglio pattern and the blind via. A barrier layer and a second conductive layer are formed in the second intaglio pattern and the blind via. Parts of the second conductive layer, parts of the barrier layer and parts of the first conductive layer are removed until the second surface of the dielectric layer is exposed, so as to form a patterned circuit structure.12-20-2012
20120318769METHOD OF FORMING A METAL PATTERN AND METHOD OF MANUFACTURING A DISPLAY SUBSTRATE INCLUDING THE METAL PATTERN - A method of forming a metal pattern on a display substrate includes blanket depositing a copper-based layer having a thickness between about 1,500 Å and about 5,500 Å on a base substrate, and forming a patterned photoresist layer on the copper-based layer. The copper-based layer is over-etched by an etching composition containing an oxidizing moderating agent where the over-etch factor is between about 40% and about 200% while using the patterned photoresist layer as an etch stopping layer, and where the etching composition includes ammonium persulfate between about 0.1% by weight and about 50% by weight, includes an azole-based compound between about 0.01% by weight and about 5% by weight and a remainder of water. Thus, reliability of the metal pattern and that of manufacturing a display substrate may be improved.12-20-2012
20120285925Method for forming a mirror mems device - An apparatus for use with a digital micromirror device includes a hinge layer that is disposed outwardly from a substrate. The hinge layer including a hinge that is capable of at least partially supporting a micromirror that is disposed outwardly from the hinge. In one particular embodiment, the hinge and the substrate are separated by a first air gap. The device also including a first hinge support that is disposed outwardly from the substrate and inwardly from at least a portion of the hinge layer. The first hinge support being capable of transmitting a voltage to the hinge. At least a portion of the hinge support coupled to at least the portion of the hinge layer. In one particular embodiment, the first hinge support is formed in a process step that is different than a process step that forms the hinge layer.11-15-2012
20120285924METHOD FOR MANUFACTURING PRINTED CIRCUIT BOARD - Disclosed herein is a method for manufacturing a printed circuit board. The method for manufacturing a printed circuit board includes: preparing a base substrate having first connection pads and second connection pads; forming a solder resist layer on the base substrate, the solder resist layer having a first opening for exposing the first connection pads; forming a first surface treatment layer on the first connection pads; forming a protective film on the solder resist layer; forming a second opening for exposing the second connection pads in the protective film and the solder resist layer; and forming a second surface treatment layer on the second connection pads.11-15-2012
20110147341ETCHING SOLUTION FOR TITANIUM-BASED METAL, TUNGSTEN-BASED METAL, TITANIUM/TUNGSTEN-BASED METAL OR THEIR NITRIDES - An etching solution for titanium-based metals, tungsten-based metals, titanium/tungsten-based metals or their nitrides. The etching solution contains 10-40 mass % hydrogen peroxide, 0.1-15 mass % of an organic acid salt, and water.06-23-2011
20130020279PLANARIZED SACRIFICIAL LAYER FOR MEMS FABRICATION - A method of forming a device is provided. The method includes providing a substrate, forming a sacrificial layer over the substrate, and forming a field layer around the sacrificial layer. After formation, both the sacrificial layer and the field layer are planarized. A component is then formed over the planarized sacrificial layer and the planarized field layer. The component has a first electrode and a second electrode and a single crystal wafer disposed between the first and second electrodes. The component includes anchors disposed substantially over the field layer. Once the component is formed, the sacrificial layer is released with an etchant having a selectivity for the sacrificial layer wherein a cavity is formed beneath the component. The cavity allows free movement within the cavity during operation of the device. The etchant does not release the field layer and the component so the field layer remains below the anchors.01-24-2013
20130020280METHOD OF MANUFACTURING FUEL CELL - A method of manufacturing a fuel cell includes: growing carbon nanotubes substantially perpendicular to a substrate formed by loading a growth catalyst on a base material; arranging the substrate and a polymer electrolyte membrane so as to oppose to each other and combining the carbon nanotubes with the polymer electrolyte membrane; and dissolving and removing part of the substrate by immersing the substrate in a solution which dissolves the substrate, after the carbon nanotubes and the polymer electrolyte membrane are combined.01-24-2013
20080223820METHOD FOR FORMING MINIATURE WIRES - A method for forming miniature wires by printing or dispensing a solution on a substrate, the solution comprising a solute being capable of being etched and forming an inner and outer region on the substrate, each region having a thickness. After an etching process is applied on the substrate, the region inner region is removed so the outer region remains as desired wires. A line width of thus formed wires is narrowed to reach micron-scale wires.09-18-2008
20080223819Method and etchant for removing glass-coating from metal wires - An etchant for and method of removing a glass coating on a metallic wire is provided. The etchant comprises an acid solution having metal ions contained therein. The metal ions prevent the acid solution from pitting or damaging the metallic wire, while allowing the acid solution to effectively etch and remove the glass coating. In one embodiment, a fluorine-based acid solution can be used. In another embodiment, a glass coated, metal alloy microwire is etched and the metal ions added to the etchant are chosen to be the same as the majority constituent element in the metal alloy. The glass coating can be either removed in full or only partially removed.09-18-2008
20130175238ETCHING SOLUTION AND METHOD OF MANUFACTURING PRINTED WIRING SUBSTRATE USING THE SAME - This invention relates to an etching solution including hydrogen peroxide, sulfuric acid, chlorine ions, benzotriazole and pyrazole, and to a method of manufacturing a printed wiring substrate wherein the surface of the metal wiring of the printed wiring substrate is treated with an alkali solution, roughened using the etching solution and then subjected to anti-rust treatment, thus forming porous surface irregularities and micro anchors even with a small etching amount of the metal (Cu) to thereby obtain a high force of adhesion between the metal and an insulating material.07-11-2013
20130168348AQUEOUS POLISHING COMPOSITION AND PROCESS FOR CHEMICALLY MECHANICALLY POLISHING SUBSTRATES CONTAINING SILICON OXIDE DIELECTRIC AND POLYSILICON FILMS - An aqueous polishing composition has been found, the said aqueous polishing composition comprising (A) at least one type of abrasive particles which are positively charged when dispersed in an aqueous medium free from component (B) and having a pH in the range of from 3 to 9 as evidenced by the electrophoretic mobility; (B) at least one water-soluble polymer selected from the group consisting of linear and branched alkylene oxide homopolymers and copolymers; and (C) at least one anionic phosphate dispersing agent; and a process for polishing substrate materials for electrical, mechanical and optical devices making use of the aqueous polishing composition.07-04-2013
20130098866ROTARY NANOTUBE BEARING STRUCTURE AND METHODS FOR MANUFACTURING AND USING THE SAME - In one embodiment, a rotary device includes a multiwall nanotube that extends substantially perpendicularly from a substrate. A rotor may be coupled to an outer wall of the multiwall nanotube, be spaced apart from the substrate, and be free to rotate around an elongate axis of the multiwall nanotube.04-25-2013
20130112651METHOD FOR MANUFACTURING COIL PARTS - The present invention discloses a method for manufacturing coil parts including a ferrite substrate, a conductor line formed on the ferrite substrate, and an external electrode for external electrical connection of the conductor line, including: coating a magnetic layer to cover the external electrode; planarizing a surface of the magnetic layer by mechanical polishing so that a portion of the magnetic layer remains on the external electrode; and exposing the external electrode by removing the remaining magnetic layer by chemical polishing.05-09-2013
20130126465METHOD OF MANUFACTURING PLASTIC METALLIZED THREE-DIMENSIONAL CIRCUIT - A method of manufacturing plastic metallized 3D circuit includes the steps of providing a 3D plastic main body; performing a surface pretreatment on the plastic main body; performing a metallization process on the plastic main body to deposit a thin metal film thereon; performing a photoresist coating process to form a photoresist protective layer on the thin metal film; performing an exposure and development process on the photoresist protective layer to form a patterned photoresist protective layer; performing an etching process on the exposed thin metal film to form a patterned metal circuit layer; stripping the patterned photoresist protective layer; and performing a surface treatment on the patterned metal circuit layer to form a metal protective layer. With the method, a 3D circuit pattern can be directly formed on a 3D plastic main body without providing additional circuit carrier to thereby meet the requirement for miniaturized and compact electronic devices.05-23-2013
20130126466Method for Producing a Dielectric Layer on a Component - A method for producing a dielectric layer on the surface of a component is described. In particular embodiments, a dielectric layer having a planar surface can be generated over a substrate topography having raised structures. In a trimming process, a component property, which depends on the thickness or the third topography of the dielectric layer, is adjusted.05-23-2013
20130140270IC-PROCESSED POLYMER NANO-LIQUID CHROMATOGRAPHY SYSTEM ON-A-CHIP AND METHOD OF MAKING IT - Embodiments in accordance with the present invention relate to packed-column nano-liquid chromatography (nano-LC) systems integrated on-chip, and methods for producing and using same. The microfabricated chip includes a column, flits/filters, an injector, and a detector, fabricated in a process compatible with those conventionally utilized to form integrated circuits. The column can be packed with supports for various different stationary phases to allow performance of different forms of nano-LC, including but not limited to reversed-phase, normal-phase, adsorption, size-exclusion, affinity, and ion chromatography. A cross-channel injector injects a nanolitre/picolitre-volume sample plug at the column inlet. An electrochemical/conductivity sensor integrated at the column outlet measures separation signals. A self-aligned channel-strengthening technique increases pressure rating of the microfluidic system, allowing it to withstand the high pressure normally used in high performance liquid chromatography (HPLC). On-chip sample injection, separation, and detection of mixture of anions in water is successfully demonstrated using ion-exchange nano-LC.06-06-2013
20130140271Capacitor Forming Methods - A capacitor forming method includes forming an electrically conductive support material over a substrate, forming an opening through at least the support material to the substrate, and, after forming the opening, forming a capacitor structure contacting the substrate and the support material in the opening. The support material contains at least 25 at % carbon. Another capacitor forming method includes forming a support material over a substrate, forming an opening through at least the support material to the substrate, and, after forming the opening, forming a capacitor structure contacting the substrate and the support material in the opening. The support material contains at least 20 at % carbon. The support material has a thickness and the opening has an aspect ratio 20:1 or greater within the thickness of the support material.06-06-2013
20130146561METHOD OF MANUFACTURING VERTICAL TRANSISTORS - A method of manufacturing vertical transistors includes steps of: forming a conductive layer on the surface of a substrate with a ditch and two support portions; removing the conductive layer on the bottom wall of the ditch and top walls of the support portions via anisotropic etching through a etch back process; forming an oxidized portion in the ditch; and etching the conductive layer to form two gates without contacting each other. By forming the conductive layer on the surface of the ditch and adopting selective etching of the etch back process, the problem of forming sub-trenches caused by lateral etching or uneven etching rate that might otherwise occur in the conventional etching process is prevented, and the risk of damaging metal wires caused by increasing etching duration also can be averted.06-13-2013
20110240591METHOD OF MANUFACTURING IN-MOLD FORMING FILM WITH METAL SURFACE - A method of manufacturing an in-mold forming film with a metal surface provides a metal sheet layer having a coupling surface predetermining at least one etching area, and then applies an etching measure to the etching area at the coupling surface, such that recessed structures are formed inwardly on a surface of the etching area, and then injects a plastic material to the coupling surface of the metal sheet layer by an injection pressure after the metal sheet layer is etched, such that the plastic material is forced to cover the recessed structures in the etching area, and finally cures the plastic material to carry the metal sheet layer and form a tight connection relation between the cured plastic material and the recessed structures.10-06-2011
20090283496DIRECTING CARBON NANOTUBE GROWTH - Embodiments of the invention include apparatuses and methods relating to directed carbon nanotube growth using a patterned layer. In some embodiments, the patterned layer includes an inhibitor material that directs the growth of carbon nanotubes.11-19-2009
20100288725Acid Chemistries and Methodologies for Texturing Transparent Conductive Oxide Materials - Surface texturing of the transparent conductive oxide (TCO) front contact of a thin film photovoltaic (TFPV) solar cell is needed to enhance the light-trapping capability of the TFPV solar cells and thus improving the solar cell efficiency. Embodiments of the current invention describe chemical formulations and methods for the wet etching of the TCO. The formulations and methods may be optimized to tune the surface texturing of the TCO as desired.11-18-2010
20120273454ETCHING LIQUID FOR CONDUCTIVE POLYMER, AND METHOD FOR PATTERNING CONDUCTIVE POLYMER - An etching liquid for a conductive polymer is disclosed which comprises greater than 0.5 wt % but no greater than 30 wt % of (NH11-01-2012
20100314353Nano-construction of complex 3-D Structures and modification of existing structures - In one preferred aspects, methods are provided to produce a three-dimensional feature, comprising: (a) providing a nano-manipulator device; (b) positioning an article with the nano-manipulator device; and (c) manipulating the article to produce the three-dimensional feature. The invention relates to production of nanoscale systems that can be tailored with specific physical and/or electrical characteristics or need to have these characteristics modified. Methods and apparatus are presented that can construct three-dimensional nanostructures and can also modify existing nanostructures in three dimensions.12-16-2010
20100314352FABRICATING METHOD OF EMBEDDED PACKAGE STRUCTURE - A fabricating method of an embedded package structure includes following steps. First, a first circuit structure and a second circuit structure are formed respectively on a first board and a second board which are combined to form an integrated panel. The first board and the second board are then separated. Next, an embedded element is electrically disposed on the first circuit structure. At least one conductive bump is formed on the second circuit structure. Thereafter, a semi-cured film is provided, and a laminating process is performed to laminate the first circuit structure on the first board, the semi-cured film, and the second circuit structure on the second board. The semi-cured film encapsulates the embedded element and the at least one conductive bump pierces through the semi-cured film and electrically connects the first circuit structure.12-16-2010
20130180945METHOD OF PROCESSING A CONTACT PAD - In various embodiments, a method of processing a contact pad may include providing a contact pad, a topmost layer of the contact pad containing aluminum or an aluminum alloy, at least part of the topmost layer of the contact pad being exposed; subjecting the contact pad to a thermally activated atmosphere containing water or reactive components of water.07-18-2013
20130180946Chemical Removal of Surface Defects from Grain Oriented Electrical Steel - A method of reducing defect heights of iron mound defects on a mill glass coated electrical steel, comprises contacting at least a portion of a surface of a mill glass coated electrical steel with an acidic solution for a contacting time sufficient to reduce an average height of iron defects on the surface to a an average height in a range of 0 percent to 150 percent of the thickness of the mill glass coating, without effectively removing the mill glass coating. After contacting, the acid contacted mill glass coated electrical steel is rinsed with water and dried.07-18-2013
20130180947ETCHING COMPOSITION AND METHOD OF MANUFACTURING A DISPLAY SUBSTRATE USING THE SAME - An etching composition that includes, based on the total weight of the etching composition, from about 0.05% to about 15% by weight of a halogen-containing compound, from about 0.1% to about 20% by weight of a nitrate compound, from about 0.1% to about 10% by weight of an acetate compound, from about 0.1% to about 10% by weight of a cyclic amine compound, from about 0% to about 50% by weight of a polyhydric alcohol, and a remainder of water.07-18-2013
20090032491CONDUCTIVE ELEMENT FORMING USING SACRIFICIAL LAYER PATTERNED TO FORM DIELECTRIC LAYER - Methods of forming a conductive element for an integrated circuit (IC) chip and a related structure are disclosed. One embodiment of the method may include forming a first sacrificial layer having a pattern therein for a first dielectric layer to surround the conductive element; forming the first dielectric layer within the patterned first sacrificial layer; removing the patterned first sacrificial layer, leaving the first dielectric layer; and forming the conductive element in a space vacated by the patterned first sacrificial layer. The methods prevent damage caused to low dielectric constant dielectric layers during etching and stripping/cleaning processes.02-05-2009
20110303635DRY ETCHING APPARATUS AND METHOD OF DRY ETCHING - A dry etching apparatus includes: a vacuum chamber which includes therein a stage on which a member to be etched is mounted; a process gas supply device which supplies a process gas into the vacuum chamber; a plasma generating device which includes an electrode for generating a plasma in the vacuum chamber; a plasma generating power source which supplies high-frequency power for plasma generation to the electrode of the plasma generating device; a bias power source which is a single bias power source for controlling a self-bias potential of the stage and from which output frequency is variable; a matching box which is a single matching box connected electrically between the stage and the bias power source and which matches impedances between a load of the bias power source and the bias power source; a frequency setting device which sets an output frequency of the bias power source; and a control device which controls an impedance of the matching box according to the set output frequency of the bias power source.12-15-2011
20130186850SLURRY FOR COBALT APPLICATIONS - A slurry for chemical mechanical of a cobalt layer or a conductive layer over a cobalt layer includes abrasive particles, an organic complexing compound for Cu or Co ion complexion, a Co corrosion inhibitor that is 0.01-1.0 wt % of the slurry, an oxidizer, and a solvent. The slurry has a pH of 7-12.07-25-2013
20130186851NONPOLYMERIC ANTIREFLECTION COMPOSITIONS CONTAINING ADAMANTYL GROUPS - Nonpolymeric compounds, compositions, and methods for forming microelectronic structures, and the structures formed therefrom are provided. The nonpolymeric compounds are ring-opened, epoxide-adamantane derivatives that comprise at least two epoxy moieties and at least one adamantyl group, along with at least one chemical modification group, such as a chromophore, bonded to a respective epoxy moiety. Anti-reflective and/or planarization compositions can be formed using these compounds and used in lithographic processes, including fabrication of microelectronic structures.07-25-2013
20130186852DEVICE AND METHOD FOR PRODUCING TARGETED FLOW AND CURRENT DENSITY PATTERNS IN A CHEMICAL AND/OR ELECTROLYTIC SURFACE TREATMENT - The invention relates to a device and method for producing targeted flow and current density patterns in a chemical and/or electrolytic surface treatment. The device comprises a flow distributor body which is disposed, with the front face thereof, plane-parallel to a substrate to be processed, and which has outlet openings on the front face, through which process solution flows onto the substrate surface. The process solution flowing back from the substrate is led off through connecting passages onto the rear face of the flow distributor body. At the same time a targeted distribution of an electrical field on a conductive substrate surface is effected by a specific arrangement of said connecting passages.07-25-2013
20120285926DUAL-DAMASCENE BIT LINE STRUCTURES FOR MICROELECTRONIC DEVICES AND METHODS OF FABRICATING MICROELECTRONIC DEVICES - Methods of fabricating components for microelectronic devices, microelectronic devices including memory cells or other components, and computers including memory devices include forming memory cells. For example, one embodiment is directed toward a method of fabricating a memory cell on a workpiece having a substrate, a plurality of active areas in the substrate, and a dielectric layer over the active areas. One embodiment of the method includes constructing bit line contact openings in the dielectric layer over first portions of the active areas and cell plug openings over second portions of the active areas. The method also includes depositing a first conductive material into the bit line contact openings to form bit line contacts and into the cell plug openings to form cell plugs. A conductive line is formed in a trench in the substrate.11-15-2012
20130193104METHOD OF FORMING INKJET NOZZLE CHAMBER - A method of forming an inkjet nozzle chamber includes the steps of: (a) depositing a layer of chamber material onto a substrate, the layer of chamber material defining a depth of the nozzle chamber; (b) removing a predetermined region of the layer of chamber material to define sidewalls of the nozzle chamber and an internal volume of the nozzle chamber; (c) depositing a sacrificial material to fill the internal volume contained within the sidewalls; (d) depositing a roof layer onto the sacrificial material and the sidewalls; (e) etching the roof layer to define a nozzle opening therein; and (f) removing the sacrificial material contained in the internal volume so as to form the nozzle chamber.08-01-2013
20120031872CONDUCTIVE FILM REMOVAL AGENT AND CONDUCTIVE FILM REMOVAL METHOD - Disclosed is an agent for removing a conductive film, which contains: an acid having a boiling point of 80° C. or higher, a base having a boiling point of 80° C. or higher, or a compound which generates an acid or a base by external energy in combination with a solvent, a resin, and a leveling agent. Also disclosed is a method for removing a conducting film, which uses the agent for removing a conductive film. The agent for removing a conductive film and the method for removing a conductive film are capable of in-place uniformity removing a desired portion of a conductive film.02-09-2012
20130200038AQUEOUS POLISHING COMPOSITION AND PROCESS FOR CHEMICALLY MECHANICALLY POLISHING SUBSTRATES FOR ELECTRICAL, MECHANICAL AND OPTICAL DEVICES - An aqueous polishing composition having a pH of 3 to 11 and comprising (A) abrasive particles which are positively charged when dispersed in an aqueous medium free from component (B) and of a pH of 3 to 9 as evidenced by the electrophoretic mobility; (B) anionic phosphate dispersing agents; and (C) a polyhydric alcohol component selected from the group consisting of (c1) water-soluble and water-dispersible, aliphatic and cycloaliphatic, monomeric, dimeric and oligomeric polyols having at least 4 hydroxy groups; (c2) a mixture consisting of (c21) water-soluble and water-dispersible, aliphatic and cycloaliphatic polyols having at least 2 hydroxy groups; and (c22) water-soluble or water-dispersible polymers selected from linear and branched alkylene oxide homopolymers and copolymers (c221); and linear and branched, aliphatic and cycloaliphatic poly(N-vinylamide) homopolymers and copolymers (c222); and (c3) mixtures of (c1) and (c2); and a process for polishing substrates for electrical, mechanical and optical devices.08-08-2013
20130200039AQUEOUS POLISHING COMPOSITIONS CONTAINING N-SUBSTITUTED DIAZENIUM DIOXIDES AND/OR N'-HYDROXY-DIAZENIUM OXIDE SALTS - An aqueous polishing composition comprising (A) at least one water-soluble or water-dispersible compound selected from the group consisting of N-substituted diazenium dioxides and N′-hydroxy-diazenium oxide salts; and (B) at least one type of abrasive particles; the use of the compounds (A) for manufacturing electrical, mechanical and optical devices and a process for polishing substrate materials for electrical, mechanical and optical devices making use of the aqueous polishing composition.08-08-2013
20120085731METHOD OF FABRICATING MEMS DEVICES (SUCH AS IMod) COMPRISING USING A GAS PHASE ETCHANT TO REMOVE A LAYER - Improvements in an interferometric modulator that cavity defined by two walls.04-12-2012
20120085730METHOD OF MANUFACTURING WIRING BOARD - A method for manufacturing a wiring board, includes: forming an insulating resin layer on a conductive layer; forming a metal chloride or a metal sulfate on the insulating resin layer; forming a protective layer on the metal chloride or the metal sulfate; forming an exposed portion in the insulating resin layer, the metal chloride or the metal sulfate, and the protective layer so as to at least partially expose the conductive layer; removing residues in the exposed portion; removing the protective layer; and forming a wiring on the insulating resin layer in which the protective layer has been removed.04-12-2012
20130206720DEVICE AND METHOD FOR GENERATING A PLASMA DISCHARGE FOR PATTERNING THE SURFACE OF A SUBSTRATE - Device for generating a plasma discharge near a substrate for patterning the surface of the substrate, comprising a first electrode having a first discharge portion and a second electrode having a second discharge portion, a high voltage source for generating a high voltage difference between the first and the second electrode, and positioning means for positioning the first electrode with respect to the substrate. The device is further provided with an intermediate structure that is, in use, arranged in between the first electrode and the substrate while allowing for positioning the first electrode with respect to the substrate.08-15-2013

Patent applications in class FORMING OR TREATING ELECTRICAL CONDUCTOR ARTICLE (E.G., CIRCUIT, ETC.)

Patent applications in all subclasses FORMING OR TREATING ELECTRICAL CONDUCTOR ARTICLE (E.G., CIRCUIT, ETC.)