Class / Patent application number | Description | Number of patent applications / Date published |
205123000 | Product is semiconductor or includes semiconductor | 48 |
20080217183 | Electropolishing metal features on a semiconductor wafer - In one embodiment, the present invention includes a method for electroplating a plurality of metal bumps on a device side of a semiconductor wafer and planarizing the metal bumps by electropolishing to obtain a substantially uniform thickness for the plurality of metal bumps. Other embodiments are described and claimed. | 09-11-2008 |
20080230393 | METHOD AND APPARATUS FOR PRODUCING CONDUCTIVE MATERIAL - A photosensitive film, which has a transparent support and a silver salt emulsion layer containing a silver salt formed thereon, is exposed and developed to form a metallic silver portion. The base material to be plated is electrified in an electrolytic solution free of plating substances, using the metallic silver portion as a cathode. Then, the electrified base material is subjected to an electroless plating treatment to form a first plated layer only on the metallic silver portion. The base material is subjected to an electroplating treatment to form a second plated layer on the first plated layer, further form a third plated layer on the second plated layer. | 09-25-2008 |
20080277285 | BIPOLAR ELECTROLESS PROCESSING METHODS - A bipolar photo-electrochemical process is disclosed for electroless deposition (referred to as photo Bi-OCD) of a metallic compound onto the top surface of a semiconducting substrate whereby differential illumination of the front side of the substrate versus the back side of the substrate provides a driving force to separate the cathodic and anodic partial reactions leading to high yield deposition of the metallic compound. A selective photo Bi-OCD process is further disclosed whereby the top surface of the substrate is at least partly covered with an insulating pattern such that the deposition of the metallic compound takes place selectively into the openings of the pattern. | 11-13-2008 |
20090071836 | METHOD OF ELECTRODEPOSITING GERMANIUM COMPOUND MATERIALS ON A SUBSTRATE - A method of electrodepositing germanium compound materials on an exposed region of a substrate structure, which includes forming a plating solution by dissolving at least one germanium salt and at least one salt containing an element other than germanium in water; obtaining a substrate with a clean surface; immersing the substrate in the solution; and electroplating germanium compound materials on the substrate by applying an electrical potential between the substrate and an anode in the plating solution, in which the substrate is included in a semiconductor or phase change device. | 03-19-2009 |
20090101509 | Process Of Making An Optical Lens - A semiconductor substrate is anodized to be shaped into an optical lens. Prior to being anodized, the substrate is finished with an anode pattern on its bottom surface so as to be consolidated into a unitary structure in which the anode pattern is precisely reproduced on the substrate. The anodization utilizes an electrolytic solution which etches out oxidized portion as soon as it is formed as a result of the anodization, to thereby develop a porous layer in a pattern in match with the anode pattern. The anode pattern brings about an in-plane distribution of varying electric field intensity by which the porous layer develops into a shape complementary to a desired lens profile. Upon completion of the anodization, the semiconductor substrate is shaped into the lens by etching out the porous layer and the anode pattern from the substrate. | 04-23-2009 |
20090107846 | Method and apparatus to prewet wafer surface for metallization from electrolyte solutions - The present invention improves the wetting between electrolyte and the wafer surface when they are put into contact by pre-implementing an adsorbed liquid layer on the entire front surface of the wafer just prior to the plating process. The pre-implementing adsorbed liquid layer is realized by transporting vaporized liquid molecules from vapor phase at elevated temperature (relative to wafer) and condensing them onto wafer surface. | 04-30-2009 |
20090194425 | Electrochemical Fabrication Methods Including Use of Surface Treatments to Reduce Overplating and/or Planarization During Formation of Multi-layer Three-Dimensional Structures - A method of fabricating three-dimensional structures from a plurality of adhered layers of at least a first and a second material wherein the first material is a conductive material and wherein each of a plurality of layers includes treating a surface of a first material prior to deposition of the second material. The treatment of the surface of the first material either (1) decreases the susceptibility of deposition of the second material onto the surface of the first material or (2) eases or quickens the removal of any second material deposited on the treated surface of the first material. In some embodiments the treatment of the first surface includes forming a dielectric coating over the surface and the second material is electrodeposited (e.g. using an electroplating or electrophoretic process). In other embodiments the first material is coated with a conductive material that doesn't readily accept deposits of electroplated or electroless deposited materials. | 08-06-2009 |
20090255820 | METHOD FOR ELECTROCHEMICALLY STRUCTURING A CONDUCTIVE OR SEMICONDUCTOR MATERIAL, AND DEVICE FOR IMPLEMENTING IT - The invention relates to a method and to a device for electrochemical micro- and/or nano-structuring, which are reliable, fast, simple, easy to implement, and reproducible. For this purpose, the invention provides a method of electrochemically structuring a sample ( | 10-15-2009 |
20090294293 | ELECTRODEPOSITION COMPOSITION AND METHOD FOR COATING A SEMICONDUCTOR SUBSTRATE USING THE SAID COMPOSITION - The present invention relates to an electrodeposition composition intended particularly for coating a semiconductor substrate in order to fabricate structures of the “through via” type for the production of interconnects in integrated circuits. According to the invention, the said solution comprises copper ions in a concentration of between 14 and 120 mM and ethylenediamine, the molar ratio between ethylenediamine and copper being between 1.80 and 2.03 and the pH of the electrodeposition solution being between 6.6 and 7.5. The present invention also relates to the use of the said electrodeposition solution for the deposition of a copper seed layer, and to the method for depositing a copper a seed layer with the aid of the electrodeposition solution according to the invention. | 12-03-2009 |
20100096273 | CU SURFACE PLASMA TREATMENT TO IMPROVE GAPFILL WINDOW - A method and apparatus for selectively controlling deposition rate of conductive material during an electroplating process. Dopants are predominantly incorporated into a conductive seed layer on field regions of a substrate prior to filling openings in the field regions by electroplating. A substrate is positioned in one or more processing chambers, and barrier and conductive seed layers formed. A dopant precursor is provided to the chamber and ionized, with or without voltage bias. The dopant predominantly incorporates into the conductive seed layer on the field regions. Electrical conductivity of the conductive seed layer on the field regions is reduced relative to that of the conductive seed layer in the openings, resulting in low initial deposition rate of metal on the field regions during electroplating, and little or no void formation in the metal deposited in the openings. | 04-22-2010 |
20100126872 | ELECTRODEPOSITION OF COPPER IN MICROELECTRONICS WITH DIPYRIDYL-BASED LEVELERS - A method for metallizing a via feature in a semiconductor integrated circuit device substrate, wherein the semiconductor integrated circuit device substrate comprises a front surface, a back surface, and the via feature and wherein the via feature comprises an opening in the front surface of the substrate, a sidewall extending from the front surface of the substrate inward, and a bottom. The method comprises contacting the semiconductor integrated circuit device substrate with an electrolytic copper deposition chemistry comprising (a) a source of copper ions and (b) a leveler compound, wherein the leveler compound is a reaction product of a dipyridyl compound and an alkylating agent; and supplying electrical current to the electrolytic deposition chemistry to deposit copper metal onto the bottom and sidewall of the via feature, thereby yielding a copper filled via feature. | 05-27-2010 |
20100200412 | Process For Through Silicon Via Filling - A semiconductor electroplating process deposits copper into the through silicon via hole to completely fill the through silicon via in a substantially void free is disclosed. The through silicon via may be more than about 3 micrometers in diameter and more that about 20 micrometers deep. High copper concentration and low acidity electroplating solution is used for deposition copper into the through silicon vias. | 08-12-2010 |
20100206737 | PROCESS FOR ELECTRODEPOSITION OF COPPER CHIP TO CHIP, CHIP TO WAFER AND WAFER TO WAFER INTERCONNECTS IN THROUGH-SILICON VIAS (TSV) - A process of electrodepositing high purity copper in a via in a silicon substrate to form a through-silicon-via (TSV), including immersing the silicon substrate into an electrolytic bath in an electrolytic copper plating system in which the electrolytic bath includes an acid, a source of copper ions, a source of ferrous and/or ferric ions, and at least one additive for controlling physical-mechanical properties of deposited copper; and applying an electrical voltage for a time sufficient to electrodeposit high purity copper to form a TSV, in which a Fe | 08-19-2010 |
20110017604 | Method for making semiconductor electrodes - Disclosed is a method for making semiconductor electrodes. In the method, there is provided a wafer. The wafer includes first metal layers. A second metal layer is provided on the wafer so that the first metal layers are shielded with the second metal layer. Photo-resist is provided on the second metal layer so that the first metal layers are not shielded with the photo-resist. An electroplating device is used to provide third metal layers on the second metal layer so that each of the first metal layers is shielded with a related one of the third metal layers. The wafer is divided from the photo-resist, thus forming semiconductor electrodes. | 01-27-2011 |
20110042224 | APPARATUS AND METHODS FOR ELECTROCHEMICAL PROCESSING OF MICROFEATURE WAFERS - Apparatus and methods for electrochemically processing microfeature wafers. The apparatus can have a vessel including a processing zone in which a microfeature wafer is positioned for electrochemical processing. The apparatus further includes at least one counter electrode in the vessel that can operate as an anode or a cathode depending upon the particular plating or electropolishing application. The apparatus further includes a supplementary electrode and a supplementary virtual electrode. The supplementary electrode is configured to operate independently from the counter electrode in the vessel, and it can be a thief electrode and/or a de-plating electrode depending upon the type of process. The supplementary electrode can further be used as another counter electrode during a portion of a plating cycle or polishing cycle. The supplementary virtual electrode is located in the processing zone, and it is configured to counteract an electric field offset relative to the wafer associated with an offset between the wafer and the counter electrode in the vessel when the wafer is in the processing zone. | 02-24-2011 |
20110139627 | METHOD AND APPARATUS FOR FLUID PROCESSING A WORKPIECE - A method of fluid processing a semiconductor workpiece, including disposing a workpiece holder with a housing capable of containing a fluid, the workpiece holder retaining the workpiece, providing an agitation system connected to the housing and comprising a member disposed within the housing adjacent the workpiece holder, and agitating the fluid by moving the member substantially parallel to a surface of the workpiece with a non-uniform oscillatory motion, the non-uniform oscillatory motion being a series of substantially continuous geometrically asymmetric oscillations wherein each consecutive oscillation of the series is geometrically asymmetric having at least two substantially continuous opposing strokes wherein reversal positions of each substantially continuous stroke of the substantially continuous asymmetric oscillation are disposed asymmetrically with respect to a center point of each immediately preceding substantially continuous stroke of the oscillation. | 06-16-2011 |
20110308955 | INTEGRATED SHIELDING FOR WAFER PLATING - A semiconductor substrate carrier for use during wet chemical processing may comprise a conductive flange to couple the carrier with processing equipment, a frame coupled with the conductive flange, where the frame is configured to hold a semiconductor substrate, and an integrated shield coupled with the frame. The integrated shield is configured to alter an electric field near at least a portion of a surface of the semiconductor substrate during the wet chemical processing. | 12-22-2011 |
20120024713 | PROCESS FOR ELECTRODEPOSITION OF COPPER CHIP TO CHIP, CHIP TO WAFER AND WAFER TO WAFER INTERCONNECTS IN THROUGH-SILICON VIAS (TSV) WITH HEATED SUBSTRATE AND COOLED ELECTROLYTE - Process of electrodepositing a metal in a high aspect ratio via in a silicon substrate to form a through-silicon-via (TSV), utilizing an electrolytic bath including a redox mediator, in an electrolytic metal plating system including a chuck adapted to hold the silicon substrate and to heat the silicon substrate to a first temperature, a temperature control device to maintain temperature of the electrolytic bath at a second temperature, in which the first temperature is maintained in a range from about 30° C. to about 60° C. and the second temperature is maintained at a temperature (a) at least 5° C. lower than the first temperature and (b) in a range from about 15° C. to about 35° C. | 02-02-2012 |
20120031768 | PROCESS FOR THROUGH SILICON VIA FILLING - A semiconductor electroplating process deposits copper into the through silicon via hole to completely fill the through silicon via in a substantially void free is disclosed. The through silicon via may be more than about 3 micrometers in diameter and more that about 20 micrometers deep. High copper concentration and low acidity electroplating solution is used for deposition copper into the through silicon vias. | 02-09-2012 |
20120175264 | WAFER PRETREATMENT FOR COPPER ELECTROPLATING - The present invention is directed to a pretreatment process for copper electroplating of via or trench features on a wafer, comprising filling the via or trench feature with a pretreatment solution, wherein the pretreatment solution comprises copper ions. | 07-12-2012 |
20130026043 | Foil Plating for Semiconductor Packaging - Arrangements for plating a single surface of a thin foil are described. In one aspect, a metal foil is wrapped tightly at least partially around a plating solution drum. The drum is partially immersed in a plating solution such that the waterline of the metal plating solution is below a break point where the metallic foil strip begins to unwind from the plating solution drum. With this arrangement, one side of the metallic foil strip is exposed to the metal plating solution, while the opposing back side of the metallic foil strip does not come in substantial contact with the metal plating solution. In this manner, the exposed side of the foil is plated while the back surface of the foil is not plated. The drum may be rotated to convey the foil through the plating solution. | 01-31-2013 |
20130062214 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing semiconductor devices comprises: applying a dual pulse power to the semiconductor device during metal electroplating a part of the semiconductor device and applying ultrasonic energy to said semiconductor device during the metal electroplating. | 03-14-2013 |
20130098769 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND APPARATUS FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes providing a template having openings on upper surface, channels for receiving plating solution and connecting from the openings to lower surface of the template, and electrodes in positions corresponding to the channels on the lower surface and extending to the openings through the channels, positioning a substrate having circuits on upper surface of the substrate and through holes penetrating through the substrate and connected to circuit electrodes of the circuits such that the upper surface of the substrate faces downward, coupling the template and substrate such that the holes are positioned to correspond with the openings, supplying plating solution from the channels to the holes, and applying voltage between the circuit electrodes as cathodes and electrodes as anodes such that through-hole electrodes are formed in the holes and that the circuit electrodes are connected to the electrodes. | 04-25-2013 |
20130168255 | COPPER-ELECTROPLATING COMPOSITION AND PROCESS FOR FILLING A CAVITY IN A SEMICONDUCTOR SUBSTRATE USING THIS COMPOSITION - The subject-matter of the present invention is a composition especially intended for filling, by the electroplating of copper, a cavity in a semiconductor substrate such as a “through-via” structure for the production of interconnects in three-dimensional integrated circuits. | 07-04-2013 |
20130213816 | Incorporating High-Purity Copper Deposit As Smoothing Step After Direct On-Barrier Plating To Improve Quality Of Deposited Nucleation Metal In Microscale Features - Techniques disclosed herein a method and system for coating the interior surfaces of microscale hole features fabricated into the substantially planar surface of a substrate. Techniques include creating a separation or smoothing layer between a nucleation layer process and a metallization or gapfill process. The addition of such a separation layer avoids dissolving a seed layer and gapfill complications from remnant organic material. Techniques include adding a conformal copper smoothing layer step after applying a direct on-barrier nucleation layer. The smoothing layer adds a sufficient thickness so that the gapfill chemistry does not erode the nucleation layer. The smoothing layer can also provide a high-purity copper film that will not detrimentally interact with the TSV gapfill chemistry. This smoothing layer can also provide a surface with consistent roughness to allow uniform adhesion of the organic additives in the TSV gapfill chemistry to create a filling profile that is void-free. | 08-22-2013 |
20130264214 | METAL PLATING FOR PH SENSITIVE APPLICATIONS - Metal electroplating processes are used in pH sensitive applications to plate metal layers on semiconductors. The semiconductors may be used in the manufacture of photovoltaic devices and solar cells. | 10-10-2013 |
20130313121 | Method of Forming Interconnects for Three Dimensional Integrated Circuit - A method of forming interconnects for three dimensional integrated circuits comprises attaching a metal layer on a first carrier, attaching a first side of a packaging component on the metal layer, wherein the packaging component comprises a plurality of through vias. The method further comprises filling the plurality of through vias with a metal material using an electrochemical plating process, wherein the metal layer functions as an electrode for the electrochemical plating process, attaching a second carrier on a second side of the packaging component, detaching the first carrier from the packaging component, forming a photoresist layer on the metal layer, patterning the photoresist layer and detaching exposed portions of the metal layer. | 11-28-2013 |
20130334054 | METHOD FOR ELECTROCHEMICALLY MANUFACTURING CuSCN NANOWIRES - A method for forming, on a conductive or semiconductor substrate, nanowires based on CuSCN, including the steps of: preparing an aqueous electrolytic solution from a Cu(II) salt having a concentration lower than 120 mM, a Cu(II) complexing agent from the aminocarboxylic acid family, and a thiocyanate salt, the solution having a pH ranging between 0.1 and 3; electrochemically depositing the aqueous electrolytic solution on the substrate. | 12-19-2013 |
20140027296 | SIDEWALLS OF ELECTROPLATED COPPER INTERCONNECTS - A structure formed in an opening having a substantially vertical sidewall defined by a non-metallic material and having a substantially horizontal bottom defined by a conductive pad, the structure including a diffusion barrier covering the sidewall and a fill composed of conductive material. The structure including a first intermetallic compound separating the diffusion barrier from the conductive material, the first intermetallic compound comprises an alloying material and the conductive material, and is mechanically bound to the conductive material, the alloying material is at least one of the materials selected from the group of chromium, tin, nickel, magnesium, cobalt, aluminum, manganese, titanium, zirconium, indium, palladium, and silver; and a first high friction interface located between the diffusion barrier and the first intermetallic compound and parallel to the sidewall of the opening, wherein the first high friction interface results in a mechanical bond between the diffusion barrier and the first intermetallic compound. | 01-30-2014 |
20140090982 | EDGELESS PULSE PLATING AND METAL CLEANING METHODS FOR SOLAR CELLS - A method for plating metal to a solar cell is disclosed. The method includes plating a metal layer only on the surface of solar cell without plating metal along the solar cell edges by conducting a first current in a first direction in an electroplating bath, ejecting metal from the metal layer by conducting a second current in a second direction and plating additional metal to the metal layer by conducting a third current in the first direction. The first, second and third current can be alternated. Subsequent to an electroplating process, an ultrasonic cleaning process is performed on the solar cell to remove any excess plated metal along the surface and edges of the solar cell. | 04-03-2014 |
20140209476 | LOW COPPER ELECTROPLATING SOLUTIONS FOR FILL AND DEFECT CONTROL - Certain embodiments herein relate to a method of electroplating copper into damascene features using a low copper concentration electrolyte having less than about 10 g/L copper ions and about 2-15 g/L acid. Using the low copper electrolyte produces a relatively high overpotential on the plating substrate surface, allowing for a slow plating process with few fill defects. The low copper electrolyte may have a relatively high cloud point. | 07-31-2014 |
20140231265 | Electronic Packages and Components Thereof Formed by Co-Deposited Carbon Nanotubes - Microelectronic packages may be formed using the co-deposition of carbon nanotubes. The carbon nanotubes may be functionalized to have an appropriate charge so they can be combined with other materials to give suitable properties. The other materials that are co-deposited may include metals, ceramics, and polymers. The electronic package components may be formed including thermal interface materials, vias, trenches, capacitors, memories, substrates, and substrate cores, as a few examples. | 08-21-2014 |
20140305802 | SELF-IONIZED AND INDUCTIVELY-COUPLED PLASMA FOR SPUTTERING AND RESPUTTERING - A magnetron sputter reactor for sputtering deposition materials such as tantalum, tantalum nitride and copper, for example, and its method of use, in which self-ionized plasma (SIP) sputtering and inductively coupled plasma (ICP) sputtering are promoted, either together or alternately, in the same or different chambers. Also, bottom coverage may be thinned or eliminated by ICP resputtering in one chamber and SIP in another. SIP is promoted by a small magnetron having poles of unequal magnetic strength and a high power applied to the target during sputtering. ICP is provided by one or more RF coils which inductively couple RF energy into a plasma. The combined SIP-ICP layers can act as a liner or barrier or seed or nucleation layer for hole. In addition, an RF coil may be sputtered to provide protective material during ICP resputtering. In another chamber an array of auxiliary magnets positioned along sidewalls of a magnetron sputter reactor on a side towards the wafer from the target. The magnetron preferably is a small, strong one having a stronger outer pole of a first magnetic polarity surrounding a weaker outer pole of a second magnetic polarity and rotates about the central axis of the chamber. The auxiliary magnets preferably have the first magnetic polarity to draw the unbalanced magnetic field component toward the wafer. The auxiliary magnets may be either permanent magnets or electromagnets. | 10-16-2014 |
20140318975 | MACHINE SUITABLE FOR PLATING A CAVITY OF A SEMI-CONDUCTIVE OR CONDUCTIVE SUBSTRATE SUCH AS A THROUGH VIA STRUCTURE - The invention relates to a machine ( | 10-30-2014 |
20150303105 | METHOD AND APPARATUS FOR MANUFACTURING SEMICONDUCTOR DEVICE - Disclosed is a method for manufacturing a semiconductor device. The method includes a template disposing step, a processing solution supply step, and a processing step. At the processing step, a template including a plurality of flow paths configured to allow a processing solution to flow therethrough and a plurality of electrodes installed in the flow paths is disposed with respect to a substrate including a plurality of through holes formed therethrough in a thickness direction such that the flow paths correspond to the through holes. At the processing solution supply step, the processing solution is supplied into the through holes through the flow paths, and at the processing step, a predetermined processing is performed with respect to the substrate by applying a voltage using one of the electrodes as a positive electrode and using another electrode as a negative electrode. | 10-22-2015 |
20150322587 | SUPER CONFORMAL PLATING - A method for at least partially filling a feature on a workpiece includes electrochemically depositing a metallization layer on a seed layer formed on a workpiece using a plating electrolyte having at least one plating metal ion, a pH range of about 6 to about 13, an organic additive, and first and second metal complexing agents. | 11-12-2015 |
20150325477 | SUPER CONFORMAL METAL PLATING FROM COMPLEXED ELECTROLYTES - A method for at least partially filling a feature on a workpiece generally includes obtaining a workpiece including a feature; and depositing a first layer in the feature, wherein the chemistry for depositing the first layer has a pH in the range of about 6 to about 13, and includes a metal complexing agent and at least one organic or inorganic additive selected from the group consisting of accelerator, suppressor, and leveler. | 11-12-2015 |
20150329983 | PROCESS FOR THE ELECTROCHEMICAL DEPOSITION OF A SEMICONDUCTOR MATERIAL - A process for the electrochemical deposition of a semiconductor material, which process comprises: (i) providing a non-aqueous solvent; (ii) providing at least one precursor salt which forms a source of the constituent elements within the semiconductor material to be deposited; and (iii) electrodepositing the semiconductor material onto an electrode substrate using the precursor salt in the non-aqueous solvent, characterised in that: (iv) the semiconductor material is a p-block or a post-transition metal semiconductor material containing at least one p-block element or post-transition metal; and (v) the non-aqueous solvent is a halocarbon non-aqueous solvent. | 11-19-2015 |
20160035685 | TIN ALLOY ELECTROPLATING SOLUTION FOR SOLDER BUMPS INCLUDING PERFLUOROALKYL SURFACTANT - Disclosed is a tin-based electroplating solution for forming solder bumps of a flip chip package. The tin-based electroplating solution includes tin methanesulfonate, silver methanesulfonate, methanesulfonic acid, a fluorinated surfactant, an aromatic polyoxyalkylene ether, and water. Also disclosed is a method for forming solder bumps by using the electroplating solution. The method includes (1) electroplating a silicon wafer having a protective layer through which an electrode pad is exposed and an under bump metallurgy (UBM) layer with a copper or copper/nickel plating solution to form copper or copper/nickel pillars on the under bump metallurgy layer and (2) electroplating the pillars with the tin-based electroplating solution to form solder bumps. | 02-04-2016 |
20160102416 | LOW COPPER/HIGH HALIDE ELECTROPLATING SOLUTIONS FOR FILL AND DEFECT CONTROL - Certain embodiments herein relate to a method of electroplating copper into damascene features using a low copper, high halide concentration electrolyte having between about 4-10 g/L copper ions, between about 150-400 ppm halide ions, and about 2-15 g/L acid. Using the low copper electrolyte produces a relatively high overpotential on the plating substrate surface, allowing for a slow plating process with few fill defects. The low copper electrolyte may have a relatively high cloud point. The use of a relatively high halide ion concentration may promote improved nucleation on a seed layer, resulting in fewer and less significant voids within the features. | 04-14-2016 |
20160108538 | SUBSTRATE PROCESSING METHOD AND TEMPLATE - A substrate processing method of performing a predetermined processing by supplying a processing liquid to a processing region of a substrate and using processing target ions in the processing liquid, includes: arranging a template to face the substrate, the template including a passage configured to distribute the processing liquid, a direct electrode, and an indirect electrode, and the substrate including a counter electrode, which matches with the direct electrode, installed in the processing region; supplying the processing liquid to the processing region through the passage; and performing the predetermined processing on the substrate by applying a voltage to the indirect electrode to cause the processing target ions to migrate to the counter electrode side while applying a voltage between the direct electrode and the counter electrode to oxidize or reduce the processing target ions that have migrated to the counter electrode side. | 04-21-2016 |
20160115613 | APPARATUS AND METHOD FOR PLATING AND/OR POLISHING WAFER - An apparatus and a method for plating and/or polishing wafer includes a wafer chuck, an auxiliary nozzle apparatus and a main nozzle apparatus. The wafer chuck holds and positions the wafer, moves horizontally, and rotates. The auxiliary nozzle apparatus supplies uncharged or charged electrolyte to cover the outer edge of the wafer and the wafer chuck, and the main nozzle apparatus supplies charged electrolyte to the surface of the wafer, to improve the plating and/or polishing uniformity of the outer edge of the wafer, reduce the entire electric resistance of the apparatus, and improve the plating and/or polishing rate. | 04-28-2016 |
20160133483 | MANUFACTURING METHOD OF INTERPOSED SUBSTRATE - A manufacturing method of an interposed substrate is provided. A metal-stacked layer comprising a first metal layer, an etching stop layer and a second metal layer is formed. A patterned conductor layer is formed on the first metal layer, wherein the patterned conductor layer exposes a portion of the first metal layer. A plurality of conductive pillars is formed on the patterned conductor layer, wherein the conductive pillars are separated from each other and stacked on a portion of the patterned conductor layer. An insulating material layer is formed on the metal-stacked layer, wherein the insulating material layer covers the portion of the first metal layer and encapsulates the conductive pillars and the other portion of the patterned conductor layer. The metal-stacked layer is removed to expose a lower surface opposite to an upper surface of the insulating material layer and a bottom surface of the patterned conductor layer. | 05-12-2016 |
20160189981 | MANUFACTURING METHOD OF SUBSTRATE STRUCTURE - A manufacturing method of a substrate structure is provided. The method includes the following steps. Firstly, a conductive carrier is provided. Then, a first metal layer is formed on the conductive carrier. Then, a second metal layer is formed on the first metal layer. Then, a third metal layer is formed on the second metal layer, wherein each of the second metal layer and the third metal layer has a first surface and a second surface opposite to the first surface, the first surface of the third metal layer is connected to the second surface of the second metal layer, the surface area of the first surface of the third metal layer is larger than the surface area of the second surface of the second metal layer, and the first metal layer, the second metal layer and the third metal layer form a conductive structure. | 06-30-2016 |
20160190007 | A METHOD FOR MICROVIA FILLING BY COPPER ELECTROPLATING WITH TSV TECHNOLOGY FOR 3D COPPER INTERCONNECTION AT HIGH ASPECT RATIO - A method for microvia filling by copper electroplating with a TSV technology for a 3D copper interconnection at a high aspect ratio, which includes: Step 1: formulating an electroplating solution of a copper methyl sulfonate system, Step 2: wetting the microvias of the TSV technology by means of an electroplating pre-treatment, Step 3: charging into the grooves, completing the ultra-low current diffusion, so that the copper ions and the additives are rationally distributed at the surface and the interior of the microvias of the TSV technology, Step 4: connecting the wafer for the TSV technology to the cathode of a power source, fully immersing the electroplating surface of the wafer in the electroplating solution, and electroplating with a step-by-step current method of rotating or stirring the cathode, the current density of the plating conditions is 0.01-10A/dm2 and the temperature is 15-30° C., Step 5: after the electroplating, washing the wafer completely clean with deionized water, and drying it by spinning or blowing. The method for microvia filling by copper electroplating with a TSV technology for a 3D copper interconnection at a high aspect ratio has a high via-filling speed, a thin copper layer on the surface, no risk of creating voids and cracks, and can achieve the complete filling of microvias having an aspect ratio of more than 10:1 which are extremely difficult to fill. | 06-30-2016 |
20160254156 | Process for Filling Vias in the Microelectronics | 09-01-2016 |
20190145017 | LOW COPPER ELECTROPLATING SOLUTIONS FOR FILL AND DEFECT CONTROL | 05-16-2019 |
205124000 | Predominantly nonmetal electrolytic coating (e.g., anodic oxide, etc.) | 1 |
20180025934 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT | 01-25-2018 |