Class / Patent application number | Description | Number of patent applications / Date published |
174265000 | Preform in hole | 9 |
20080230264 | INTERCONNECTION STRUCTURE AND METHOD THEREOF - The present invention discloses an interconnection structure which is formed by a method comprising providing a first conductive substrate, a second conductive substrate, and an insulating substrate; respectively forming a first circuit and a second circuit on the first conductive substrate and the second conductive substrate; forming a conductive bump on the second circuit; and connecting the insulating substrate with the first circuit and the second circuit by pressing the first conductive substrate, the insulating substrate and the second conductive substrate, wherein the conductive bump penetrates the insulating substrate to contact the first circuit. | 09-25-2008 |
20090145652 | PRINTED WIRING BOARD AND ITS MANUFACTURING METHOD - The present invention has for its object to provide a process for manufacturing multilayer printed circuit boards which is capable of simultaneous via hole filling and formation of conductor circuit and via holes of good crystallinity and uniform deposition can be constructed on a substrate and high-density wiring and highly reliable conductor connections can be realized without annealing. | 06-11-2009 |
20090200074 | Circuit Substrate Having Post-Fed Die Side Power Supply Connections - A circuit substrate uses post-fed top side power supply connections to provide improved routing flexibility and lower power supply voltage drop/power loss. Plated-through holes are used near the outside edges of the substrate to provide power supply connections to the top metal layers of the substrate adjacent to the die, which act as power supply planes. Pins are inserted through the plated-through holes to further lower the resistance of the power supply path(s). The bottom ends of the pins may extend past the bottom of the substrate to provide solderable interconnects for the power supply connections, or the bottom ends of the pins may be soldered to “jog” circuit patterns on a bottom metal layer of the substrate which connect the pins to one or more power supply terminals of an integrated circuit package including the substrate. | 08-13-2009 |
20100038127 | Power-Ground Plane Partitioning and Via Connection to Utilize Channel/Trenches for Power Delivery - An apparatus that includes a plurality of metalized planes, one or more dielectric layers separating the plurality of metalized planes; and one or more conductive trenches connecting to at least one of the plurality of metalized planes. | 02-18-2010 |
20130161082 | Z-Directed Delay Line Components for Printed Circuit Boards - A Z-directed signal delay line component for insertion into a printed circuit board while allowing electrical connection to internal conductive planes contained with the PCB. In one embodiment the Z-directed delay line component is housed within the thickness of the PCB allowing other components to be mounted over it. The delay line embodiments include a W-like line and a plurality of spaced apart, semi-circular line segment connected such that current flow direction alternates in direction between adjacent semi-circular line segments, each of which in other embodiments can be varied by use of shorting bars. Several Z-directed delay line components may be mounted into a PCB and serially connected to provide for longer delays. The body may contain one or more conductors and may include one or more surface channels or wells extending along at least a portion of the length of the body. Methods for mounting Z-directed components are also provided. | 06-27-2013 |
20130186680 | Tape Film Packages and Methods of Fabricating the Same - A tape film package is provided including an insulating pattern; a via contact in a via hole in the insulating pattern; first interconnection patterns extending from the via contact to a cutting surface of the insulating pattern; and second interconnection patterns connected to the via contact below the insulating pattern. The second interconnection patterns are parallel to the first interconnection patterns and spaced apart from the cutting surface of the insulating pattern. | 07-25-2013 |
20140158416 | ACTUATION MECHANISMS FOR ELECTRICAL INTERCONNECTIONS - Some embodiments described herein include apparatuses and methods of forming such apparatuses. In one such embodiment, an apparatus may include an electronic arrangement, a first die, and a second die coupled to the first die and the electronic arrangement. The electronic arrangement may include an opening. At least a portion of the die may occupy at least a portion of the opening in the electronic arrangement. Other embodiments including additional apparatuses and methods are described. | 06-12-2014 |
20150136468 | MICRO VIAS IN PRINTED CIRCUIT BOARDS - Some embodiments relate to micro vias in printed circuit boards (PCBs). In an example, a PCB may include a PCB substrate and a micro via. The micro via may extend between opposing surfaces of the PCB substrate and may have a diameter less than or equal to about 100 microns. In another example, a method of forming micro vias in a PCB may include forming a through hole in a PCB substrate of the PCB. The method may also include positioning a pillar that is electrically conductive within the through hole. The method may also include backfilling the through hole around the pillar with an epoxy backfill. | 05-21-2015 |
20160143141 | MULTILAYER CIRCUIT BOARD - A multilayer circuit board includes a first substrate and a second substrate in stack. The first substrate first substrate a first pad, and a first circuit, wherein the first circuit is embedded in the first substrate, and the first pad is electrically connected to the first circuit. The second substrate has a first through hole, a second pad, and a second circuit, wherein the first through hole is opened at both sides of the second substrate, and the first pad of the first substrate is in the first through hole; the second circuit is embedded in the second substrate, and the second pad is electrically connected to the second circuit. The pads on each substrate are exposed by the through hole(s) of the above substrate(s) to shorten the null sections of the interconnectors and reduce the interference from the null sections. | 05-19-2016 |