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Electrical pulse counters, pulse dividers, or shift registers: circuits and systems

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Class / Patent application numberDescriptionNumber of patent applications / Date published
377064000 SHIFT REGISTER 160
377001000 APPLICATIONS 80
377027000 SYSTEMS 64
20110170657ANALOG COUNTER AND IMAGING DEVICE INCORPORATING SUCH A COUNTER - An analog counter includes, for at least one step, an input for receiving electric pulses and a means for modifying, by consecutive increments or decrements, a storage voltage for each received electrical pulse, a means for resetting the storage voltage, and a comparator for comparing the storage voltage with a threshold voltage and adapted to generate exceedance information. The counter further includes a control means adapted to control the resetting means in the event of the simultaneous detection of exceedance information from the comparator and of an input pulse.07-14-2011
20080267341High Performance, Low Power, Dynamically Latched Up/Down Counter - A high performance, low power up/down counter is set forth. The counter presented is controlled by two clock pulses, an up pulse and a down pulse, and updates all bits of the counter in parallel. These bits are then latched using a scannable pulsed limited output switching dynamic logic latch. By using a limited switch dynamic logic latch, the counter is able to utilize the speed of dynamic logic without requiring the traditional dynamic logic power. The area saved and speed gained by using a dynamic latch is significant compared to a typical edge-triggered flip-flop. Additionally, by computing all the next count state bits in parallel, the counter reduces an overall count computation delay by eliminating the counter ripple.10-30-2008
20120230461CLOCK RECOVERY IN A BATTERY POWERED DEVICE - A battery powered device is able to maintain a clock value when the battery is removed for a short period. During a first time period, while the battery is in the device, clock pulses derived from a first oscillator are counted at a first rate in a first counter that represents the clock value. During a second time period following the first time period, while the battery is removed, the value of the first counter is maintained independent of any clock pulses derived from the first oscillator, clock pulses derived from a second low power oscillator are counted in a second counter. During a recovery time period following the second time period, clock pulses derived from the second oscillator are again counted in the second counter, while clock pulses derived from the first oscillator are counted in the first counter at a second rate higher than the first rate, the duration of the recovery time period being determined based on the number of pulses counted in the second counter during the second time period.09-13-2012
20080226014DOUBLE BEAM SWITCH CONTACT - An LCD counter assembly including a housing that houses an LCD display at a first end and a printed circuit board (PCB) assembly at a second end opposite the first end. A diffuser is intermediate the PCB assembly and the LCD display, the LCD display and the PCB assembly in electrical contact with a connector that provides electrical signals from the PCB assembly to the LCD. The first end of the housing includes an aperture through which the LCD display is readily visible to an observer. The PCB assembly may include a backlight to improve the visibility of the LCD display. The PCB assembly further includes a PCB having a printed circuit and a plurality of pads, a single piece, double beam, activation and trigger switch combination assembled to the board, the board configured to receive the double beam activation and trigger switch combination and a removable tab to separate the activation switch in the double beam combination from one of the plurality of pads.09-18-2008
20090304140ASYNCHRONOUS PING-PONG COUNTER AND THEROF METHOD - An asynchronous ping-pong counter is disclosed. The asynchronous ping-pong counter comprises a first asynchronous counter, a second synchronous counter, and a controller, the asynchronous ping-pong counter operates between a first state and a second state. In the first state, the first asynchronous counter counts a first number of clock edges of a fast clock signal, and the second asynchronous counter holds a first counter output value. In the second state, the second asynchronous counter counts a second number of clock edges of the fast clock signal, and the first asynchronous counter holds a second counter output value. The controller determines a state transition based on a sampling of a slow clock signal by the fast clock signal.12-10-2009
20120093277COUNTER CIRCUIT AND SOLID-STATE IMAGING DEVICE - According to one embodiment, S (S is an integer equal to or larger than two) number of sub counters each count S number of clocks of different frequencies, and a clock switching unit is provided for each sub counter and starts a counting operation of a sub counter of a next stage after finishing a counting operation in a sub counter of a local stage.04-19-2012
20100002827SHIFT REGISTER APPARATUS AND METHOD THEREOF - A shift register apparatus and a method thereof are provided. The technique manner submitted by the present invention utilizes two NMOS transistors for pulling down the voltage level of the scan signals output by the shift registers within the shift register apparatus to the low level gate voltage, wherein one of the NMOS transistors is controlled by a control unit, and the other NMOS transistor is controlled by a clock signal or the inverted clock signal provided to the shift registers. Therefore, shifting amount of the threshold voltage of those NMOS transistors can trend to be flat, and the reliability of those NMOS transistors can be promoted. In addition, since only one control unit is needed to dispose in each shift register so that the layout area of whole shift register apparatus can be reduced, and the panel with narrow frame size also can be achieved by the present invention.01-07-2010
20080205581Common-mode charge control in a pipelined charge-domain signal-processing circuit - In a differential bucket-brigade device (BBD) pipeline it is necessary for proper circuit function to maintain the common-mode charge within an acceptable range at each pipeline stage. Embodiments of the present invention provide for reducing common-mode charge variations in a differential charge-domain pipeline. Common mode charge at a given stage of the pipeline is adjusted according to one or more measured characteristics, thereby controlling common mode charge variation throughout the differential charge-domain pipeline.08-28-2008
20110158378Neuron MOS Transistor based Multi-Valued Counter Unit and Multi-Digit Multi-Valued Counter - The present invention discloses a neuron MOS based multi-valued counter unit. The counter unit includes a neuron MOS source follower and at least a control gate connected the neuron MOS source follower. The control gate includes a first dual-value D flip-flop, a second dual-value D flip-flop, an AND gate, and an OR gate. The present invention utilizes the neuron MOS to replace the complicated threshold value operations of the multi-value logic. The current invention implements the true multi-value logic and a multi-base multi-value counter by increasing the number of the dual-value D flip-flop, and connecting the dual-value D flip-flop to the input control gate of the neuron MOS follower. Comparing to the conventional multi-value counter, the present invention reduces the necessary components in constructing the counter, and it also reduces the cost and power consumption. The present invention applies the asynchronous carry-over concept to implement the multi-digit multi-value counter, and it also has been verified by the simulation of P Simulation Program with Integrated Circuit Emphasis (SPICE).06-30-2011

Patent applications in all subclasses Electrical pulse counters, pulse dividers, or shift registers: circuits and systems