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Electronic digital logic circuitry

Patent class list (only not empty are listed)

Deeper subclasses:

Class / Patent application numberDescriptionNumber of patent applications / Date published
326037000 MULTIFUNCTIONAL OR PROGRAMMABLE (E.G., UNIVERSAL, ETC.) 556
326021000 SIGNAL SENSITIVITY OR TRANSMISSION INTEGRITY 390
326062000 INTERFACE (E.G., CURRENT DRIVE, LEVEL SHIFT, ETC.) 327
326104000 FUNCTION OF AND, OR, NAND, NOR, OR NOT 132
326093000 CLOCKING OR SYNCHRONIZING OF LOGIC STAGES OR GATES 119
326101000 SIGNIFICANT INTEGRATED STRUCTURE, LAYOUT, OR LAYOUT INTERCONNECTIONS 85
326016000 WITH TEST FACILITATING FEATURE 74
326009000 RELIABILITY 67
326008000 SECURITY (E.G., ACCESS OR COPY PREVENTION, ETC.) 59
326052000 EXCLUSIVE FUNCTION (E.G., EXCLUSIVE OR, ETC.) 29
326056000 TRI-STATE (I.E., HIGH IMPEDANCE AS THIRD STATE) 27
326001000 SUPERCONDUCTOR (E.G., CRYOGENIC, ETC.) 25
326035000 THRESHOLD (E.G., MAJORITY, MINORITY, OR WEIGHTED INPUTS, ETC.) 21
326059000 THREE OR MORE ACTIVE LEVELS (E.G., TERNARY, QUATENARY, ETC.) 14
326017000 ACCELERATING SWITCHING 3
20090273362BOOSTER CIRCUITS FOR REDUCING LATENCY - A booster circuit for reducing the nominal latency of a logic gate. The booster circuit includes a charge sharing mechanism to transfer a stored charge to the output of the logic gate in response to a logic state transition on the input of the logic gate. The transfer of stored charge also reduces the charge drawn from the supply during the output transition.11-05-2009
20080238473Push-Pull Pulse Register Circuit - A push-pull pulse register circuit. The push-pull pulse register circuit includes a first logic inverter having first-inverter input and first-inverter output, a second logic inverter having second-inverter input and second-inverter output, a third logic inverter having third-inverter input and third-inverter output and configured to receive logic input data at the third-inverter input, a first logic gate having first-gate input, first-gate output, and first-gate control input, and a second logic gate having second-gate input, second-gate output, and second-gate control input. The third-inverter input is coupled to the first-gate input; the third-inverter output is coupled to the second-gate input; the second-inverter input is coupled to the second-gate output and the first-inverter output; the second-inverter output is coupled to the first-gate output and the first-inverter input; the first-gate control input is coupled to the second-gate control input; and the first-gate and the second-gate control inputs are configured to receive a clock pulse.10-02-2008
20080238474BOOSTER CIRCUITS FOR REDUCING LATENCY - A booster circuit for reducing the nominal latency of a logic gate. The booster circuit includes a charge sharing mechanism to transfer a stored charge to the output of the logic gate in response to a logic state transition on the input of the logic gate. The transfer of stored charge also reduces the charge drawn from the supply during the output transition.10-02-2008
326051000 INHIBITOR 2
20110254589INTEGRATED CIRCUIT AND METHOD FOR MANUFACTURING SAME - An integrated circuit has one or more logic gates and a control circuit. The control circuit has one or more control elements coupled to the logic gates. The control circuit controls the states of the one or more logic gates. The one or more control elements have one or more programmable resistance elements and/or one or more threshold switching elements.10-20-2011
20130176053INTEGRATED CIRCUIT AND METHOD FOR MANUFACTURING THE SAME - An integrated circuit has one or more logic gates and a control circuit. The control circuit has one or more control elements coupled to the logic gates. The control circuit controls the states of the one or more logic gates.07-11-2013
326100000 INTEGRATED INJECTION LOGIC 1
20110279146COMPLEMENTARY SPIN TRANSISTOR LOGIC CIRCUIT - There is provided a complementary spin transistor logic circuit, including: a parallel spin transistor that includes a magnetized first source, a first drain magnetized in parallel with the magnetization direction of the first source, a first channel layer and a first gate electrode; and an anti-parallel spin transistor that includes a magnetized second source, a second drain magnetized in anti-parallel with the magnetization direction of the second source, a second channel layer and a second gate electrode, wherein the first gate electrode and the second gate electrode are connected to a common input terminal.11-17-2011

Patent applications in class Electronic digital logic circuitry

Patent applications in all subclasses Electronic digital logic circuitry