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Active solid-state devices (e.g., transistors, solid-state diodes)

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Class / Patent application numberDescriptionNumber of patent applications / Date published
257213000 FIELD EFFECT DEVICE 11648
257079000 INCOHERENT LIGHT EMITTER STRUCTURE 6706
257734000 COMBINED WITH ELECTRICAL CONTACT OR LEAD 6627
257414000 RESPONSIVE TO NON-ELECTRICAL SIGNAL (E.G., CHEMICAL, STRESS, LIGHT, OR MAGNETIC FIELD SENSORS) 3262
257040000 ORGANIC SEMICONDUCTOR MATERIAL 2737
257049000 NON-SINGLE CRYSTAL, OR RECRYSTALLIZED, SEMICONDUCTOR MATERIAL FORMS PART OF ACTIVE JUNCTION (INCLUDING FIELD-INDUCED ACTIVE JUNCTION) 2704
257499000 INTEGRATED CIRCUIT STRUCTURE WITH ELECTRICALLY ISOLATED COMPONENTS 2495
257678000 HOUSING OR PACKAGE 2477
257009000 THIN ACTIVE PHYSICAL LAYER WHICH IS (1) AN ACTIVE POTENTIAL WELL LAYER THIN ENOUGH TO ESTABLISH DISCRETE QUANTUM ENERGY LEVELS OR (2) AN ACTIVE BARRIER LAYER THIN ENOUGH TO PERMIT QUANTUM MECHANICAL TUNNELING OR (3) AN ACTIVE LAYER THIN ENOUGH TO PERMIT CARRIER TRANSMISSION WITH SUBSTANTIALLY NO SCATTERING (E.G., SUPERLATTICE QUANTUM WELL, OR BALLISTIC TRANSPORT DEVICE) 2020
257076000 SPECIFIED WIDE BAND GAP (1.5EV) SEMICONDUCTOR MATERIAL OTHER THAN GAASP OR GAALAS 1726
257001000 BULK EFFECT DEVICE 1565
257666000 LEAD FRAME 1304
257183000 HETEROJUNCTION DEVICE 1223
257043000 SEMICONDUCTOR IS AN OXIDE OF A METAL (E.G., CUO, ZNO) OR COPPER SULFIDE 1180
257618000 PHYSICAL CONFIGURATION OF SEMICONDUCTOR (E.G., MESA, BEVEL, GROOVE, ETC.) 945
257107000 REGENERATIVE TYPE SWITCHING DEVICE (E.G., SCR, COMFET, THYRISTOR) 605
257048000 TEST OR CALIBRATION STRUCTURE 499
257629000 WITH MEANS TO CONTROL SURFACE EFFECTS 425
257202000 GATE ARRAYS 349
257659000 WITH SHIELDING (E.G., ELECTRICAL OR MAGNETIC SHIELDING, OR FROM ELECTROMAGNETIC RADIATION OR CHARGED PARTICLES) 338
257613000 INCLUDING SEMICONDUCTOR MATERIAL OTHER THAN SILICON OR GALLIUM ARSENIDE (GAAS) (E.G., PB X SN 1-X TE) 273
257787000 ENCAPSULATED 267
257565000 BIPOLAR TRANSISTOR STRUCTURE 154
257471000 SCHOTTKY BARRIER 131
257487000 WITH MEANS TO INCREASE BREAKDOWN VOLTAGE THRESHOLD 106
257797000 ALIGNMENT MARKS 97
257655000 WITH SPECIFIED IMPURITY CONCENTRATION GRADIENT 72
257607000 WITH SPECIFIED DOPANT (E.G., PLURAL DOPANTS OF SAME CONDUCTIVITY IN SAME REGION) 62
257664000 TRANSMISSION LINE LEAD (E.G., STRIPLINE, COAX, ETC.) 45
257617000 INCLUDING REGION CONTAINING CRYSTAL DAMAGE 44
257595000 VOLTAGE VARIABLE CAPACITANCE DEVICE 34
257042000 SEMICONDUCTOR IS SELENIUM OR TELLURIUM IN ELEMENTAL FORM 25
257104000 TUNNELING PN JUNCTION (E.G., ESAKI DIODE) DEVICE 21
257603000 AVALANCHE DIODE (E.G., SO-CALLED "ZENER" DIODE HAVING BREAKDOWN VOLTAGE GREATER THAN 6 VOLTS) 20
257798000 MISCELLANEOUS 20
257603000 AVALANCHE DIODE (E.G., SO-CALLED "ZENER" DIODE HAVING BREAKDOWN VOLTAGE GREATER THAN 6 VOLTS) 16
257653000 WITH SPECIFIED SHAPE OF PN JUNCTION 13
257665000 CONTACTS OR LEADS INCLUDING FUSIBLE LINK MEANS OR NOISE SUPPRESSION MEANS 9
257594000 WITH GROOVE TO DEFINE PLURAL DIODES 2
20090085163VERTICAL DIODE USING SILICON FORMED BY SELECTIVE EPITAXIAL GROWTH - Some embodiments relate to an apparatus that exhibits vertical diode activity to occur between a semiconductive body and an epitaxial film that is disposed over a doping region of the semiconductive body. Some embodiments include an apparatus that causes both vertical and lateral diode activity. Some embodiments include a gated vertical diode for a finned semiconductor apparatus. Process embodiments include the formation of vertical-diode apparatus.04-02-2009
20110304020WAFER LEVEL DIODE PACKAGE STRUCTURE - A wafer level vertical diode package structure includes a first semiconductor layer, a second semiconductor layer, an insulative unit, a first conductive structure, and a second conductive structure. The second semiconductor layer is connected with one surface of the first semiconductor layer. The insulative unit is disposed around a lateral side of the first semiconductor layer and a lateral side of the second semiconductor layer. The first conductive structure is formed on a top surface of the first semiconductor layer and on one lateral side of the insulative layer. The second conductive structure is formed on a top surface of the second semiconductor layer and on another opposite lateral side of the insulative layer.12-15-2011
257497000 PUNCHTHROUGH STRUCTURE DEVICE (E.G., PUNCHTHROUGH TRANSISTOR, CAMEL BARRIER DIODE) 2
20110278694BIPOLAR PUNCH-THROUGH SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SUCH A SEMICONDUCTOR DEVICE - A bipolar punch-through semiconductor device has a semiconductor substrate, which includes at least a two-layer structure, a first main side with a first electrical contact, and a second main side with a second electrical contact. One of the layers in the two-layer structure is a base layer of the first conductivity type. A buffer layer of the first conductivity type is arranged on the base layer. A first layer includes alternating first regions of the first conductivity type and second regions of the second conductivity type. The first layer is arranged between the buffer layer and the second electrical contact. The second regions are activated regions with a depth of at maximum 2 μm and a doping profile, which drops from 90% to 10% of the maximum doping concentration within at most 1 μm.11-17-2011
20120319227BIPOLAR PUNCH-THROUGH SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SUCH A SEMICONDUCTOR DEVICE - A bipolar diode is provided having a drift layer of a first conductivity type on a cathode side and an anode layer of a second conductivity type on an anode side. The anode layer includes a diffused anode contact layer and a double diffused anode buffer layer. The anode contact layer is arranged up to a depth of at most 5 μm, and the anode buffer layer is arranged up to a depth of 18 to 25 μm. The anode buffer layer has a doping concentration between 8.0*1012-20-2012
257044000 WITH METAL CONTACT ALLOYED TO ELEMENTAL SEMICONDUCTOR TYPE PN JUNCTION IN NONREGENERATIVE STRUCTURE 2
20090250696NEAR NATURAL BREAKDOWN DEVICE - A semiconductor device includes a semiconductor region wherein the semiconductor region is a forced or non-forced Near Natural breakdown region, which is completely depleted when a predetermined voltage having a magnitude less than or equal to the breakdown voltage of a non-Natural breakdown (for example, Zener breakdown and Avalanche breakdown) is applied across the device.10-08-2009
20100072472Nanostructures With 0, 1, 2, and 3 Dimensions, With Negative Differential Resistance and Method for Making These Nanostructures - Nanostructures with 0, 1, 2 and 3 dimensions, with negative differential resistance and method for making these nanostructures. A nanostructure according to the invention may notably be used in nanoelectronics. It comprises at least one structure (03-25-2010
257212000 CONDUCTIVITY MODULATION DEVICE (E.G., UNIJUNCTION TRANSISTOR, DOUBLE-BASE DIODE, CONDUCTIVITY-MODULATED TRANSISTOR) 1
20080315260Diode Structure - An open-base semiconductor diode device has an emitter, base, and collector layers. The layers are configured and doped such that the device has an IV characteristic with: i. a punchthrough region beginning at a voltage V12-25-2008
257041000 POINT CONTACT DEVICE 1
20110049505DEVICES AND METHOD FOR MANUFACTURING A DEVICE - A device includes a first semiconductor chip and a second semiconductor chip which are connected to each other in an electrically conductive manner via a bonding wire, the bonding wire having a contact to the first semiconductor chip at a first contact point and having a contact to the second semiconductor chip at a second contact point, and the device including a further bonding wire which has a further first contact point and a further second contact point, a maximum distance between the bonding wire and a direct connecting line between the first and second contact points perpendicular to the connecting line being greater than a further maximum distance between the further bonding wire and a further connecting line between the further first contact point and the further second contact point perpendicular to the further connecting line.03-03-2011
257E21001 PROCESSES OR APPARATUS ADAPTED FOR MANUFACTURE OR TREATMENT OF SEMICONDUCTOR OR SOLID-STATE DEVICES OR OF PARTS THEREOF (EPO) 1
20090289379Methods of Manufacturing Semiconductor Devices and Structures Thereof - Methods of manufacturing semiconductor devices and structures thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming recesses in a first region and a second region of a workpiece. The first region of the workpiece is masked, and the recesses in the second region of the workpiece are filled with a first semiconductive material. The second region of the workpiece is masked, and the recesses in the first region of the workpiece are filled with a second semiconductive material.11-26-2009
257E23001 PACKAGING, INTERCONNECTS, AND MARKINGS FOR SEMICONDUCTOR OR OTHER SOLID-STATE DEVICES (EPO) 1
20130193593BUMP STRUCTURAL DESIGNS TO MINIMIZE PACKAGE DEFECTS - The mechanisms for forming bump structures enable forming bump structures between a chip and a substrate eliminating or reducing the risk of solder shorting, flux residue and voids in underfill. A lower limit can be established for a cc ratio, defined by dividing the total height of copper posts in a bonded bump structure divided by the standoff of the bonded bump structure, to avoid shorting. A lower limit may also be established for standoff the chip package to avoid flux residue and underfill void formation. Further, aspect ratio of a copper post bump has a lower limit to avoid insufficient standoff and a higher limit due to manufacturing process limitation. By following proper bump design and process guidelines, yield and reliability of chip packages may be increases.08-01-2013

Patent applications in class Active solid-state devices (e.g., transistors, solid-state diodes)

Patent applications in all subclasses Active solid-state devices (e.g., transistors, solid-state diodes)