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WILSONVILLE, OR US
1. 20110047522 Hardware Description Language Editing Engine 02-24-20112. 20110047520 Partition Response Surface Modeling - group of models are developed to predict printed contour deviations relative to the corresponding layout edges for 02-24-2011
3. 20110047519 Layout Content Analysis for Source Mask Optimization Acceleration 02-24-2011
4. 20110047425 On-Chip Logic To Log Failures During Production Testing And Enable Debugging For Failure Diagnosis 02-24-2011
5. 20110035720 Dynamic Printed Circuit Board Design Reuse 02-10-2011
6. 20110035638 Timing Failure Debug - debug flow that uses debug-friendly test patterns and logic fault diagnosis techniques to help physical fault isolation of timing 02-10-2011
7. 20110035204 Layered Modeling for High-Level Synthesis of Electronic Designs 02-10-2011
8. 20110016455 Power Profiling for Embedded System Design 01-20-2011
9. 20110010716 Domain Bounding for Symmetric Multiprocessing Systems 01-13-2011
10. 20110010683 Trace Routing According To Freeform Sketches 01-13-2011
11. 20110004856 Inverse Mask Design and Correction for Electronic Design 01-06-2011
12. 20100325591 Generation and Placement Of Sub-Resolution Assist Features 12-23-2010
13. 20100313089 Scan Test Application Through High-Speed Serial Input/Outputs 12-09-2010
14. 20100306728 Coexistence of Multiple Verification Component types in a Hardware Verification Framework 12-02-2010
15. 20100306720 Programmable Electrical Rule Checking - Electrical rule checking techniques for analyzing integrated circuit design data to identify specified circuit 12-02-2010
16. 20100306609 Low Power Decompression Of Test Cubes - Disclosed below are representative embodiments of methods, apparatus, and systems used to generate test patterns 12-02-2010
17. 20100302882 Random Access Memory for Use in an Emulation Environment 12-02-2010
18. 20100299567 On-Chip Logic To Support Compressed X-Masking For BIST 11-25-2010
19. 20100293422 Method And System For Scan Chain Diagnosis 11-18-2010
20. 20100286975 Reliability Simulation Method and System 11-11-2010
21. 20100275077 At-Speed Scan Testing With Controlled Switching Activity 10-28-2010
22. 20100275075 Deterministic Logic Built-In Self-Test Stimuli Generation 10-28-2010
23. 20100274548 Clock Approximation for Hardware Simulation 10-28-2010
24. 20100274518 Diagnostic Test Pattern Generation For Small Delay Defect 10-28-2010
25. 20100269086 Electron Beam Simulation Corner Correction For Optical Lithpography 10-21-2010
26. 20100269084 Visibility and Transport Kernels for Variable Etch Bias Modeling of Optical Lithography 10-21-2010
27. 20100257496 Design-Rule-Check Waiver - When a designer designates one or more errors identified in layout design data as false errors waiver geometric elements 10-07-2010
28. 20100253381 On-Chip Logic To Support In-Field Or Post-Tape-Out X-Masking In BIST Designs 10-07-2010
29. 20100251045 High Speed Clock Control - On-chip high speed clock control techniques for testing circuits with multiple clock systems are disclosed 09-30-2010
30. 20100242003 Hierarchical Verification Of Clock Domain Crossings 09-23-2010
31. 20100229145 Use Of Graphs To Decompose Layout Design Data 09-09-2010
32. 20100229133 Property-Based Classification In Electronic Design Automation 09-09-2010
33. 20100229061 Cell-Aware Fault Model Creation And Pattern Generation 09-09-2010
34. 20100229060 Compression Based On Deterministic Vector Clustering Of Incompatible Test Cubes 09-09-2010
35. 20100229055 Fault Diagnosis For Non-Volatile Memories 09-09-2010
36. 20100223590 Mask Decomposition for Double Dipole Lithography 09-02-2010
37. 20100218161 Joint Calibration for Mask Process Models 08-26-2010
38. 20100218159 Data Flow Branching in Mask Data Preparation 08-26-2010
39. 20100216061 Inverse Lithography For High Transmission Attenuated Phase Shift Mask Design And Creation 08-26-2010
40. 20100199251 Heuristic Routing For Electronic Device Layout Designs 08-05-2010
41. 20100199244 Formal Verification Of Clock Domain Crossings 08-05-2010
42. 20100199242 Verification Test Failure Analysis - Methods and apparatuses are provided that allow for efficient analysis of a graph describing tests, elements of a 08-05-2010
43. 20100199233 Uniquely Marking Products And Product Design Data 08-05-2010
44. 20100198574 Programmer View Timing Model For Performance Modeling And Virtual Prototyping 08-05-2010
45. 20100185995 Electrostatic Damage Protection Circuitry Verification 07-22-2010
46. 20100185994 Topological Pattern Matching - Techniques for more efficiently identifying specific topological patterns in microdevice design data, such as layout 07-22-2010
47. 20100185908 Speed-Path Debug Using At-Speed Scan Test Patterns 07-22-2010
48. 20100135569 Source Mask Optimization For Microcircuit design 06-03-2010
49. 20100095262 Schematic Generation From Analog Netlists 04-15-2010
50. 20100095256 Power State Transition Verification For Electronic Design 04-15-2010
51. 20100082313 Optical Lithographic Process Model Calibration 04-01-2010
52. 20100077608 Alternating Via Fanout Patterns - Various techniques are disclosed for identifying different fanout via configurations that can be created using fanout 04-01-2010
53. 20100070243 Wire Harness Unfolding - Various implementations of the invention provide methods and apparatus for determining an unfolded connector clocking angle 03-18-2010
54. 20100023916 Model Based Hint Generation For Lithographic Friendly Design 01-28-2010
55. 20100023915 Calculation System For Inverse Masks - system for calculating mask data to create a desired layout pattern on a wafer reads all or a portion of a 01-28-2010
56. 20100023914 Use Of Graphs To Decompose Layout Design Data 01-28-2010
57. 20100023905 Critical Area Deterministic Sampling - layout design for a portion of a microdevice design is partitioned into sections or "bins 01-28-2010
58. 20100023897 Property-Based Classification In Electronic Design Automation 01-28-2010
59. 20090327989 Statistical Interconnect Corner Extraction 12-31-2009
60. 20090319579 Electronic Design Automation Process Restart 12-24-2009
61. 20090300446 Selective Per-Cycle Masking Of Scan Chains For System Level Test 12-03-2009
62. 20090287438 Increased Fault Diagnosis Throughput Using Dictionaries For Hyperactive Faults 11-19-2009
63. 20090276747 Segmenting Integrated Circuit Layout Design Files Using Speculative Parsing 11-05-2009
64. 20090259617 Method And System For Data Management - method a system and a computer program product for managing the data of Electronic Design Automation tools in 10-15-2009
65. 20090259457 Trace Routing Network - Hardware emulation produces relevant and irrelevant trace data 10-15-2009
66. 20090254786 Accurately Identifying Failing Scan Bits In Compression Environments 10-08-2009
67. 20090241077 Site Selective Optical Proximity Correction 09-24-2009
68. 20090235213 Layout-Versus-Schematic Analysis For Symmetric Circuits 09-17-2009
69. 20090235209 Manufacturability - Techniques are disclosed for modifying an existing microdevice design to improve its manufacturability 09-17-2009
70. 20090222234 Generating Worst Case Test Sequences For Non-Linearly Driven Channels 09-03-2009
71. 20090210838 INTERPOLATION DISTANCE FOR LAYOUT DESING DATA CORRECTION MODEL 08-20-2009
72. 20090193241 Direct Register Access For Host Simulation 07-30-2009
73. 20090125855 Forming Separation Directives Using A Printing Feasibility Analysis 05-14-2009
74. 20090113359 Model Based Microdevice Design Layout Correction 04-30-2009
75. 20090106715 Programmable Design Rule Checking - analog design-rule-check tool analyzes a microdevice design such as an integrated circuit design 04-23-2009
76. 20090077519 Displacement Aware Optical Proximity Correction For Microcircuit Layout Designs 03-19-2009
77. 20090077506 Simultaneous Multi-Layer Fill Generation 03-19-2009
78. 20090070732 Fracture Shot Count Reduction - Techniques are described for reducing the number of shots in a fractured layout design 03-12-2009
79. 20090070731 Distributed Mask Data Preparation - Layout data is divided into segments of data and each segment of data is distributed to a computing node in a 03-12-2009
80. 20090013298 Offset Fill - Techniques are described for increasing the density of structures in a layout circuit design while reducing undesired total interconnect 01-08-2009
81. 20080301611 Selective Optical Proximity Layout Design Data Correction 12-04-2008
82. 20080235497 Parallel Data Output - Multiple processing threads operate in parallel to convert data produced by one or more electronic design automation processes in 09-25-2008