Inventors list

Agents list

Assignees list

List by place

Classification tree browser

Top 100 Inventors

Top 100 Agents

Top 100 Assignees

ST CLAIR SHORES, MI US

1. 20110043043 BATTERY BACKUP SYSTEM WITH SLEEP MODE - The present invention concerns an apparatus comprising a charger circuit and a control circuit 02-24-2011
2. 20110032992 METHOD AND APPARATUS FOR H.264 TO MPEG-2 VIDEO TRANSCODING 02-10-2011
3. 20110029980 LOW DEPTH PROGRAMMABLE PRIORITY ENCODERS 02-03-2011
4. 20110022794 DISTRIBUTED CACHE SYSTEM IN A DRIVE ARRAY 01-27-2011
5. 20110006395 HYBRID BUMP CAPACITOR - device fabricated on a chip is disclosed 01-13-2011
6. 20100325319 SYSTEMS FOR IMPLEMENTING SDRAM CONTROLLERS, AND BUSES ADAPTED TO INCLUDE ADVANCED HIGH PERFORMANCE BUS FEATURES 12-23-2010
7. 20100321972 SYSTEMS FOR IMPLEMENTING SDRAM CONTROLLERS, AND BUSES ADAPTED TO INCLUDE ADVANCED HIGH PERFORMANCE BUS FEATURES 12-23-2010
8. 20100315559 CONTOUR FREE POINT OPERATION FOR VIDEO SKIN TONE CORRECTION 12-16-2010
9. 20100299580 BCH OR REED-SOLOMON DECODER WITH SYNDROME MODIFICATION 11-25-2010
10. 20100293421 LOW DEPTH PROGRAMMABLE PRIORITY ENCODERS 11-18-2010
11. 20100284686 PRECURSOR ISI CANCELLATION USING ADAPTATION OF NEGATIVE GAIN LINEAR EQUALIZER 11-11-2010
12. 20100281344 SOFT REED-SOLOMON DECODER BASED ON ERROR-AND-ERASURE REED-SOLOMON DECODER 11-04-2010
13. 20100281297 Firmware recovery in a raid controller by using a dual firmware configuration 11-04-2010
14. 20100281219 MANAGING CACHE LINE ALLOCATIONS FOR MULTIPLE ISSUE PROCESSORS 11-04-2010
15. 20100262730 System for handling parallel input/output threads with cache coherency in a multi-core based storage array 10-14-2010
16. 20100251118 HELP UTILITY WITH EXPANDED CONTENT DISPLAY 09-30-2010
17. 20100235602 APPLICATION INDEPENDENT STORAGE ARRAY PERFORMANCE OPTIMIZER 09-16-2010
18. 20100229141 TIMING VIOLATION DEBUGGING INSIDE PLACE AND ROUTE TOOL 09-09-2010
19. 20100223427 SYSTEM FOR HANDLING INPUT/OUTPUT REQUESTS BETWEEN STORAGE ARRAYS WITH DIFFERENT PERFORMANCE CAPABILITIES 09-02-2010
20. 20100220235 METHOD FOR COMPOSITE VIDEO ARTIFACTS REDUCTION 09-02-2010
21. 20100218193 RESOURCE ALLOCATION FAILURE RECOVERY MODULE OF A DISK DRIVER 08-26-2010
22. 20100217564 ADVANCED PHYSICAL SIMULATOR - method of physical simulation of an integrated circuit design comprising the steps of reading design information for an 08-26-2010
23. 20100180151 METHOD FOR HANDLING INTERRUPTED WRITES USING MULTIPLE CORES 07-15-2010
24. 20100172449 METHOD AND/OR APPARATUS FOR STABILIZING THE FREQUENCY OF DIGITALLY SYNTHESIZED WAVEFORMS 07-08-2010
25. 20100161873 COMPRESSED CACHE CONTROLLER VALID WORD STATUS USING POINTERS 06-24-2010
26. 20100153478 PARALLEL TRUE RANDOM NUMBER GENERATOR ARCHITECTURE 06-17-2010
27. 20100131581 METHOD AND/OR APPARATUS FOR CERTIFYING AN IN-BAND MANAGEMENT APPLICATION OF AN EXTERNAL STORAGE ARRAY 05-27-2010
28. 20100131497 METHOD FOR DETERMINING WHICH OF A NUMBER OF TEST CASES SHOULD BE RUN DURING TESTING 05-27-2010
29. 20100131458 GENERATION OF AN EXTRACTED TIMING MODEL FILE 05-27-2010
30. 20100131450 AUTOMATIC CLASSIFICATION OF DEFECTS - method of automatically classifying defects 05-27-2010
31. 20100127978 POINTING DEVICE HOUSED IN A WRITING DEVICE 05-27-2010
32. 20100125765 UNINITIALIZED MEMORY DETECTION USING ERROR CORRECTION CODES AND BUILT-IN SELF TEST 05-20-2010
33. 20100086127 EFFICIENT IMPLEMENTATION OF ARITHMETICAL SECURE HASH TECHNIQUES 04-08-2010
34. 20100086059 COMPRESSED VIDEO FORMAT WITH PARTIAL PICTURE REPRESENTATION 04-08-2010
35. 20100083193 DESIGN OPTIMIZATION WITH ADAPTIVE BODY BIASING 04-01-2010
36. 20100080282 RE-ADAPTION OF EQUALIZER PARAMETER TO CENTER A SAMPLE POINT IN A BAUD-RATE CLOCK AND DATA RECOVERY RECEIVER 04-01-2010
37. 20100080093 OPTIMIZING FOCUS POINT FOR OPTICAL DISC - apparatus includes a first circuit and a second circuit 04-01-2010
38. 20100070936 WAIVER MECHANISM FOR PHYSICAL VERIFICATION OF SYSTEM DESIGNS 03-18-2010
39. 20100070829 Error checking and correction overlap ranges 03-18-2010
40. 20100070548 UNIVERSAL GALOIS FIELD MULTIPLIER - apparatus including a multiplier circuit and a multiplexing circuit 03-18-2010
41. 20100067817 SIGN CORING FOR CONTOUR REDUCTION - method for contour reduction in a digital picture is disclosed 03-18-2010
42. 20100061449 PROGRAMMABLE QUANTIZATION DEAD ZONE AND THRESHOLD FOR STANDARD-BASED H.264 AND/OR VC1 VIDEO ENCODING 03-11-2010
43. 20100057823 Alternate galois field advanced encryption standard round 03-04-2010
44. 20100057483 Software tool for developing patent submissions 03-04-2010
45. 20100050142 SPECIAL ENGINEERING CHANGE ORDER CELLS - method for correcting a plurality of violations in a circuit design and new cells used in the method are 02-25-2010
46. 20100046508 TIME-SLOT INTERCHANGE CIRCUIT - circuit and method are presented for signal processing and routing of digital voice telephony signals 02-25-2010
47. 20100031127 SCHEME FOR ERASURE LOCATOR POLYNOMIAL CALCULATION IN ERROR-AND-ERASURE DECODER 02-04-2010
48. 20100031123 UNIFIED MEMORY ARCHITECTURE FOR RECORDING APPLICATIONS 02-04-2010
49. 20100026365 ROBUST CURRENT MIRROR WITH IMPROVED INPUT VOLTAGE HEADROOM 02-04-2010
50. 20100026342 HIGH VOLTAGE INPUT RECEIVER USING LOW VOLTAGE TRANSISTORS 02-04-2010
51. 20100023715 SYSTEM FOR IMPROVING START OF DAY TIME AVAILABILITY AND/OR PERFORMANCE OF AN ARRAY CONTROLLER 01-28-2010
52. 20090327670 VARIABLE LENGTH STAGES IN A PIPELINE - circuit having a pipeline and a configuration circuit 12-31-2009
53. 20090327614 CACHE TENTATIVE READ BUFFER - apparatus having a cache and a circuit 12-31-2009
54. 20090319747 System for automatically configuring a storage array 12-24-2009
55. 20090316507 Generation Of Test Sequences During Memory Built-In Self Testing Of Multiple Memories 12-24-2009
56. 20090307543 TRANSPORT SUBSYSTEM FOR AN MBIST CHAIN ARCHITECTURE 12-10-2009
57. 20090300441 ADDRESS CONTROLLING IN THE MBIST CHAIN ARCHITECTURE 12-03-2009
58. 20090300440 DATA CONTROLLING IN THE MBIST CHAIN ARCHITECTURE 12-03-2009
59. 20090289348 SOLUTION FOR PACKAGE CROSSTALK MINIMIZATION 11-26-2009
60. 20090282307 Optimizing test code generation for verification environment 11-12-2009
61. 20090282303 BUILT IN TEST CONTROLLER WITH A DOWNLOADABLE TESTING PROGRAM 11-12-2009
62. 20090279397 CENTER ERROR MECHANICAL CENTER ADJUSTMENT 11-12-2009
63. 20090273407 VOLTAGE CONTROLLED OSCILLATOR HAVING A BANDWIDTH ADJUSTED AMPLITUDE CONTROL LOOP 11-05-2009
64. 20090265507 SYSTEM TO REDUCE DRIVE OVERHEAD USING A MIRRORED CACHE VOLUME IN A STORAGE ARRAY 10-22-2009
65. 20090256602 VARIABLE LOOP BANDWIDTH PHASE LOCKED LOOP 10-15-2009
66. 20090243792 PROCESS VARIATION BASED MICROCHIP IDENTIFICATION 10-01-2009
67. 20090237557 DEINTERLACING AND FILM AND VIDEO DETECTION WITH CONFIGURABLE DOWNSAMPLING 09-24-2009
68. 20090219440 RATE CONTROL FOR REAL TIME TRANSCODING OF SUBTITLES FOR APPLICATION WITH LIMITED MEMORY 09-03-2009
69. 20090218680 PROCESS OF GROUNDING HEAT SPREADER/STIFFENER TO A FLIP CHIP PACKAGE USING SOLDER AND FILM ADHESIVE 09-03-2009
70. 20090212413 BALL GRID ARRAY PACKAGE LAYOUT SUPPORTING MANY VOLTAGE SPLITS AND FLEXIBLE SPLIT LOCATIONS 08-27-2009
71. 20090210846 I/O PLANNING WITH LOCK AND INSERTION FEATURES 08-20-2009
72. 20090202230 VIDEO PLAYER WITH ACTION ON PAUSE - The present invention concerns an apparatus comprising a source circuit and a processing circuit 08-13-2009
73. 20090164956 REDISTRIBUTION OF CURRENT DEMAND AND REDUCTION OF POWER AND DCAP 06-25-2009
74. 20090158118 CONFIGURABLE REED-SOLOMON DECODER BASED ON MODIFIED FORNEY SYNDROMES 06-18-2009
75. 20090150846 INTELLIGENT TIMING ANALYSIS AND CONSTRAINT GENERATION GUI 06-11-2009
76. 20090144682 DUAL PATH STATIC TIMING ANALYSIS - method to analyze timing in a circuit generally including simulating reception of an input signal and a clock signal 06-04-2009
77. 20090108925 LOW POWER ON-CHIP GLOBAL INTERCONNECTS - apparatus including a first circuit, a second circuit and a third circuit 04-30-2009
78. 20090100319 Decoder using a memory for storing state metrics implementing a decoder trellis 04-16-2009
79. 20090091999 LEAKAGE OPTIMIZED MEMORY - method of power optimization in a memory is disclosed 04-09-2009
80. 20090091987 Multiple memory standard physical layer macro function 04-09-2009
81. 20090091349 High speed multiple memory interface I/O cell 04-09-2009
82. 20090086870 ADAPTIVE DATA ALIGNMENT - apparatus including a transmit circuit, a receive circuit, and a control circuit 04-02-2009
83. 20090085577 SYSTEM FOR TERMINATING HIGH SPEED INPUT/OUTPUT BUFFERS IN AN AUTOMATIC TEST EQUIPMENT ENVIRONMENT TO ENABLE EXTERNAL LOOPBACK TESTING 04-02-2009
84. 20090077510 RULES AND DIRECTIVES FOR VALIDATING CORRECT DATA USED IN THE DESIGN OF SEMICONDUCTOR PRODUCTS 03-19-2009
85. 20090063564 Statistical design closure - method of statistical design closure is disclosed 03-05-2009
86. 20090044184 Software update from off air broadcast - The present invention concerns a system comprising a server, a digital recorder, a memory, an optical disc and 02-12-2009
87. 20090044084 Combined DC restoration double detection and loops 02-12-2009
88. 20090043955 Configurable high-speed memory interface subsystem 02-12-2009
89. 20090037133 DEVICE FOR THOROUGH TESTING OF SECURE ELECTRONIC COMPONENTS 02-05-2009
90. 20090034741 ASYMMETRIC KEY WRAPPING USING A SYMMETRIC CIPHER 02-05-2009
91. 20090034611 CAVLC run before encode with zero cycle costs 02-05-2009
92. 20090033798 AUTOMATIC LUMINANCE-CHROMINANCE DELAY COMPENSATION 02-05-2009
93. 20090028244 COMPRESSED NON-REFERENCE PICTURE RECONSTRUCTION FROM POST-PROCESSED REFERENCE PICTURES 01-29-2009
94. 20090022223 HIGH QUALITY, LOW MEMORY BANDWIDTH MOTION ESTIMATION PROCESSOR 01-22-2009
95. 20090016444 METHOD AND APPARATUS FOR MASKING OF VIDEO ARTIFACTS AND/OR INSERTION OF FILM GRAIN IN A VIDEO DECODER 01-15-2009
96. 20090016422 SYSTEM FOR AN ADAPTIVE FLOATING TAP DECISION FEEDBACK EQUALIZER 01-15-2009
97. 20090012929 SEEK MINIMIZED RECOVERABLE STREAMING FILE SYSTEM 01-08-2009
98. 20090009523 SYSTEM FOR INTERLEAVED STORAGE OF VIDEO DATA 01-08-2009
99. 20090002862 FEED-FORWARD DC RESTORATION IN A PERPENDICULAR MAGNETIC READ CHANNEL 01-01-2009
100. 20080320420 EFFICIENT CELL SWAPPING SYSTEM FOR LEAKAGE POWER REDUCTION IN A MULTI-THRESHOLD VOLTAGE PROCESS 12-25-2008
101. 20080310500 METHOD FOR ACTIVATION AND DEACTIVATION OF INFREQUENTLY CHANGING SEQUENCE AND PICTURE PARAMETER SETS 12-18-2008
102. 20080304559 SYSTEM FOR AUTOMATIC BANDWIDTH CONTROL OF EQUALIZER ADAPTATION LOOPS 12-11-2008
103. 20080285949 VIDEO MOTION MENU GENERATION IN A LOW MEMORY ENVIRONMENT 11-20-2008
104. 20080278227 SQUELCH DETECTION SYSTEM FOR HIGH SPEED DATA LINKS 11-13-2008
105. 20080278210 SYSTEM FOR GLITCH-FREE DELAY UPDATES OF A STANDARD CELL-BASED PROGRAMMABLE DELAY 11-13-2008
106. 20080273430 SINGLE PLL DEMODULATION OF PRE-FORMATTED INFORMATION EMBEDDED IN OPTICAL RECORDING MEDIUM 11-06-2008
107. 20080250257 Energy efficient memory access technique for single ended bit cells 10-09-2008
108. 20080247257 MEMORY DATA INVERSION ARCHITECTURE FOR MINIMIZING POWER CONSUMPTION 10-09-2008
109. 20080246515 SYSTEM TO REDUCE PROGRAMMABLE RANGE SPECIFICATIONS FOR A GIVEN TARGET ACCURACY IN CALIBRATED ELECTRONIC CIRCUITS 10-09-2008
110. 20080244474 Cell library management for power optimization 10-02-2008
111. 20080240298 Method and/or apparatus for stabilizing the frequency of digitally synthesized waveforms 10-02-2008
112. 20080238737 REFERENCE VOLTAGE SHIFTING TECHNIQUE FOR OPTIMIZING SNR PERFORMANCE IN PIPELINE ADCS WITH RESPECT TO INPUT SIGNAL 10-02-2008
113. 20080229268 Trace optimization in flattened netlist by storing and retrieving intermediate results 09-18-2008
114. 20080212678 COMPUTATIONAL REDUCTION IN MOTION ESTIMATION BASED ON LOWER BOUND OF COST FUNCTION 09-04-2008
115. 20080204472 Method and/or apparatus for color space reduction for transcoding subpicture elements 08-28-2008